UartCore.cpp@ 74911

Last change on this file since 74911 was 74446, checked in by vboxsync, 6 years ago
Devices/Serial: Add callback to flush receive/transmit queues of the underlying driver when the serial device flushes the internal queues to stay in sync. Should fix hanging serial I/O under certain circumstances (Debugging a Windows 7 guest over a serial port attached to a named pipe for example)
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1	/* $Id: UartCore.cpp 74446 2018-09-24 16:05:11Z vboxsync $ */
2	/** @file
3	* UartCore - UART (16550A up to 16950) emulation.
4	*
5	* The documentation for this device was taken from the PC16550D spec from TI.
6	*/
7
8	/*
9	* Copyright (C) 2018 Oracle Corporation
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*/
19
20
21	/*********************************************************************************************************************************
22	* Header Files *
23	*********************************************************************************************************************************/
24	#define LOG_GROUP LOG_GROUP_DEV_SERIAL
25	#include <VBox/vmm/tm.h>
26	#include <iprt/log.h>
27	#include <iprt/uuid.h>
28	#include <iprt/assert.h>
29
30	#include "VBoxDD.h"
31	#include "UartCore.h"
32
33
34	/*********************************************************************************************************************************
35	* Defined Constants And Macros *
36	*********************************************************************************************************************************/
37
38	/** The RBR/DLL register index (from the base of the port range). */
39	#define UART_REG_RBR_DLL_INDEX 0
40
41	/** The THR/DLL register index (from the base of the port range). */
42	#define UART_REG_THR_DLL_INDEX 0
43
44	/** The IER/DLM register index (from the base of the port range). */
45	#define UART_REG_IER_DLM_INDEX 1
46	/** Enable received data available interrupt */
47	# define UART_REG_IER_ERBFI RT_BIT(0)
48	/** Enable transmitter holding register empty interrupt */
49	# define UART_REG_IER_ETBEI RT_BIT(1)
50	/** Enable receiver line status interrupt */
51	# define UART_REG_IER_ELSI RT_BIT(2)
52	/** Enable modem status interrupt. */
53	# define UART_REG_IER_EDSSI RT_BIT(3)
54	/** Sleep mode enable. */
55	# define UART_REG_IER_SLEEP_MODE_EN RT_BIT(4)
56	/** Low power mode enable. */
57	# define UART_REG_IER_LP_MODE_EN RT_BIT(5)
58	/** Mask of writeable bits. */
59	# define UART_REG_IER_MASK_WR 0x0f
60	/** Mask of writeable bits for 16750+. */
61	# define UART_REG_IER_MASK_WR_16750 0x3f
62
63	/** The IIR register index (from the base of the port range). */
64	#define UART_REG_IIR_INDEX 2
65	/** Interrupt Pending - high means no interrupt pending. */
66	# define UART_REG_IIR_IP_NO_INT RT_BIT(0)
67	/** Interrupt identification mask. */
68	# define UART_REG_IIR_ID_MASK 0x0e
69	/** Sets the interrupt identification to the given value. */
70	# define UART_REG_IIR_ID_SET(a_Val) (((a_Val) << 1) & UART_REG_IIR_ID_MASK)
71	/** Gets the interrupt identification from the given IIR register value. */
72	# define UART_REG_IIR_ID_GET(a_Val) (((a_Val) & UART_REG_IIR_ID_MASK) >> 1)
73	/** Receiver Line Status interrupt. */
74	# define UART_REG_IIR_ID_RCL 0x3
75	/** Received Data Available interrupt. */
76	# define UART_REG_IIR_ID_RDA 0x2
77	/** Character Timeou Indicator interrupt. */
78	# define UART_REG_IIR_ID_CTI 0x6
79	/** Transmitter Holding Register Empty interrupt. */
80	# define UART_REG_IIR_ID_THRE 0x1
81	/** Modem Status interrupt. */
82	# define UART_REG_IIR_ID_MS 0x0
83	/** 64 byte FIFOs enabled (15750+ only). */
84	# define UART_REG_IIR_64BYTE_FIFOS_EN RT_BIT(5)
85	/** FIFOs enabled. */
86	# define UART_REG_IIR_FIFOS_EN 0xc0
87	/** Bits relevant for checking whether the interrupt status has changed. */
88	# define UART_REG_IIR_CHANGED_MASK 0x0f
89
90	/** The FCR register index (from the base of the port range). */
91	#define UART_REG_FCR_INDEX 2
92	/** Enable the TX/RX FIFOs. */
93	# define UART_REG_FCR_FIFO_EN RT_BIT(0)
94	/** Reset the receive FIFO. */
95	# define UART_REG_FCR_RCV_FIFO_RST RT_BIT(1)
96	/** Reset the transmit FIFO. */
97	# define UART_REG_FCR_XMIT_FIFO_RST RT_BIT(2)
98	/** DMA Mode Select. */
99	# define UART_REG_FCR_DMA_MODE_SEL RT_BIT(3)
100	/** 64 Byte FIFO enable (15750+ only). */
101	# define UART_REG_FCR_64BYTE_FIFO_EN RT_BIT(5)
102	/** Receiver level interrupt trigger. */
103	# define UART_REG_FCR_RCV_LVL_IRQ_MASK 0xc0
104	/** Returns the receive level trigger value from the given FCR register. */
105	# define UART_REG_FCR_RCV_LVL_IRQ_GET(a_Fcr) (((a_Fcr) & UART_REG_FCR_RCV_LVL_IRQ_MASK) >> 6)
106	/** RCV Interrupt trigger level - 1 byte. */
107	# define UART_REG_FCR_RCV_LVL_IRQ_1 0x0
108	/** RCV Interrupt trigger level - 4 bytes. */
109	# define UART_REG_FCR_RCV_LVL_IRQ_4 0x1
110	/** RCV Interrupt trigger level - 8 bytes. */
111	# define UART_REG_FCR_RCV_LVL_IRQ_8 0x2
112	/** RCV Interrupt trigger level - 14 bytes. */
113	# define UART_REG_FCR_RCV_LVL_IRQ_14 0x3
114	/** Mask of writeable bits. */
115	# define UART_REG_FCR_MASK_WR 0xcf
116	/** Mask of sticky bits. */
117	# define UART_REG_FCR_MASK_STICKY 0xe9
118
119	/** The LCR register index (from the base of the port range). */
120	#define UART_REG_LCR_INDEX 3
121	/** Word Length Select Mask. */
122	# define UART_REG_LCR_WLS_MASK 0x3
123	/** Returns the WLS value form the given LCR register value. */
124	# define UART_REG_LCR_WLS_GET(a_Lcr) ((a_Lcr) & UART_REG_LCR_WLS_MASK)
125	/** Number of stop bits. */
126	# define UART_REG_LCR_STB RT_BIT(2)
127	/** Parity Enable. */
128	# define UART_REG_LCR_PEN RT_BIT(3)
129	/** Even Parity. */
130	# define UART_REG_LCR_EPS RT_BIT(4)
131	/** Stick parity. */
132	# define UART_REG_LCR_PAR_STICK RT_BIT(5)
133	/** Set Break. */
134	# define UART_REG_LCR_BRK_SET RT_BIT(6)
135	/** Divisor Latch Access Bit. */
136	# define UART_REG_LCR_DLAB RT_BIT(7)
137
138	/** The MCR register index (from the base of the port range). */
139	#define UART_REG_MCR_INDEX 4
140	/** Data Terminal Ready. */
141	# define UART_REG_MCR_DTR RT_BIT(0)
142	/** Request To Send. */
143	# define UART_REG_MCR_RTS RT_BIT(1)
144	/** Out1. */
145	# define UART_REG_MCR_OUT1 RT_BIT(2)
146	/** Out2. */
147	# define UART_REG_MCR_OUT2 RT_BIT(3)
148	/** Loopback connection. */
149	# define UART_REG_MCR_LOOP RT_BIT(4)
150	/** Flow Control Enable (15750+ only). */
151	# define UART_REG_MCR_AFE RT_BIT(5)
152	/** Mask of writeable bits (15450 and 15550A). */
153	# define UART_REG_MCR_MASK_WR 0x1f
154	/** Mask of writeable bits (15750+). */
155	# define UART_REG_MCR_MASK_WR_15750 0x3f
156
157	/** The LSR register index (from the base of the port range). */
158	#define UART_REG_LSR_INDEX 5
159	/** Data Ready. */
160	# define UART_REG_LSR_DR RT_BIT(0)
161	/** Overrun Error. */
162	# define UART_REG_LSR_OE RT_BIT(1)
163	/** Parity Error. */
164	# define UART_REG_LSR_PE RT_BIT(2)
165	/** Framing Error. */
166	# define UART_REG_LSR_FE RT_BIT(3)
167	/** Break Interrupt. */
168	# define UART_REG_LSR_BI RT_BIT(4)
169	/** Transmitter Holding Register. */
170	# define UART_REG_LSR_THRE RT_BIT(5)
171	/** Transmitter Empty. */
172	# define UART_REG_LSR_TEMT RT_BIT(6)
173	/** Error in receiver FIFO. */
174	# define UART_REG_LSR_RCV_FIFO_ERR RT_BIT(7)
175	/** The bits to check in this register when checking for the RCL interrupt. */
176	# define UART_REG_LSR_BITS_IIR_RCL 0x1e
177
178	/** The MSR register index (from the base of the port range). */
179	#define UART_REG_MSR_INDEX 6
180	/** Delta Clear to Send. */
181	# define UART_REG_MSR_DCTS RT_BIT(0)
182	/** Delta Data Set Ready. */
183	# define UART_REG_MSR_DDSR RT_BIT(1)
184	/** Trailing Edge Ring Indicator. */
185	# define UART_REG_MSR_TERI RT_BIT(2)
186	/** Delta Data Carrier Detect. */
187	# define UART_REG_MSR_DDCD RT_BIT(3)
188	/** Clear to Send. */
189	# define UART_REG_MSR_CTS RT_BIT(4)
190	/** Data Set Ready. */
191	# define UART_REG_MSR_DSR RT_BIT(5)
192	/** Ring Indicator. */
193	# define UART_REG_MSR_RI RT_BIT(6)
194	/** Data Carrier Detect. */
195	# define UART_REG_MSR_DCD RT_BIT(7)
196	/** The bits to check in this register when checking for the MS interrupt. */
197	# define UART_REG_MSR_BITS_IIR_MS 0x0f
198
199	/** The SCR register index (from the base of the port range). */
200	#define UART_REG_SCR_INDEX 7
201
202	/** Set the specified bits in the given register. */
203	#define UART_REG_SET(a_Reg, a_Set) ((a_Reg) \|= (a_Set))
204	/** Clear the specified bits in the given register. */
205	#define UART_REG_CLR(a_Reg, a_Clr) ((a_Reg) &= ~(a_Clr))
206
207
208	/*********************************************************************************************************************************
209	* Structures and Typedefs *
210	*********************************************************************************************************************************/
211
212	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
213
214
215	/*********************************************************************************************************************************
216	* Global Variables *
217	*********************************************************************************************************************************/
218
219	#ifdef IN_RING3
220	/**
221	* FIFO ITL levels.
222	*/
223	static struct
224	{
225	/** ITL level for a 16byte FIFO. */
226	uint8_t cbItl16;
227	/** ITL level for a 64byte FIFO. */
228	uint8_t cbItl64;
229	} s_aFifoItl[] =
230	{
231	/* cbItl16 cbItl64 */
232	{ 1, 1 },
233	{ 4, 16 },
234	{ 8, 32 },
235	{ 14, 56 }
236	};
237
238
239	/**
240	* String versions of the parity enum.
241	*/
242	static const char *s_aszParity[] =
243	{
244	"INVALID",
245	"NONE",
246	"EVEN",
247	"ODD",
248	"MARK",
249	"SPACE",
250	"INVALID"
251	};
252
253
254	/**
255	* String versions of the stop bits enum.
256	*/
257	static const char *s_aszStopBits[] =
258	{
259	"INVALID",
260	"1",
261	"1.5",
262	"2",
263	"INVALID"
264	};
265	#endif
266
267
268	/*********************************************************************************************************************************
269	* Internal Functions *
270	*********************************************************************************************************************************/
271
272
273	/**
274	* Updates the IRQ state based on the current device state.
275	*
276	* @returns nothing.
277	* @param pThis The UART core instance.
278	*/
279	static void uartIrqUpdate(PUARTCORE pThis)
280	{
281	LogFlowFunc(("pThis=%#p\n", pThis));
282
283	/*
284	* The interrupt uses a priority scheme, only the interrupt with the
285	* highest priority is indicated in the interrupt identification register.
286	*
287	* The priorities are as follows (high to low):
288	* * Receiver line status
289	* * Received data available
290	* * Character timeout indication (only in FIFO mode).
291	* * Transmitter holding register empty
292	* * Modem status change.
293	*/
294	uint8_t uRegIirNew = UART_REG_IIR_IP_NO_INT;
295	if ( (pThis->uRegLsr & UART_REG_LSR_BITS_IIR_RCL)
296	&& (pThis->uRegIer & UART_REG_IER_ELSI))
297	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_RCL);
298	else if ( (pThis->uRegIer & UART_REG_IER_ERBFI)
299	&& pThis->fIrqCtiPending)
300	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_CTI);
301	else if ( (pThis->uRegLsr & UART_REG_LSR_DR)
302	&& (pThis->uRegIer & UART_REG_IER_ERBFI)
303	&& ( !(pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
304	\|\| pThis->FifoRecv.cbUsed >= pThis->FifoRecv.cbItl))
305	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_RDA);
306	else if ( (pThis->uRegLsr & UART_REG_LSR_THRE)
307	&& pThis->fThreEmptyPending)
308	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_THRE);
309	else if ( (pThis->uRegMsr & UART_REG_MSR_BITS_IIR_MS)
310	&& (pThis->uRegIer & UART_REG_IER_EDSSI))
311	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_MS);
312
313	LogFlowFunc((" uRegIirNew=%#x uRegIir=%#x\n", uRegIirNew, pThis->uRegIir));
314
315	/* Change interrupt only if the interrupt status really changed from the previous value. */
316	if (uRegIirNew != (pThis->uRegIir & UART_REG_IIR_CHANGED_MASK))
317	{
318	LogFlow((" Interrupt source changed from %#x -> %#x (IRQ %d -> %d)\n",
319	pThis->uRegIir, uRegIirNew,
320	pThis->uRegIir == UART_REG_IIR_IP_NO_INT ? 0 : 1,
321	uRegIirNew == UART_REG_IIR_IP_NO_INT ? 0 : 1));
322	if (uRegIirNew == UART_REG_IIR_IP_NO_INT)
323	pThis->CTX_SUFF(pfnUartIrqReq)(pThis->CTX_SUFF(pDevIns), pThis, pThis->iLUN, 0);
324	else
325	pThis->CTX_SUFF(pfnUartIrqReq)(pThis->CTX_SUFF(pDevIns), pThis, pThis->iLUN, 1);
326	}
327	else
328	LogFlow((" No change in interrupt source\n"));
329
330	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
331	uRegIirNew \|= UART_REG_IIR_FIFOS_EN;
332	if (pThis->uRegFcr & UART_REG_FCR_64BYTE_FIFO_EN)
333	uRegIirNew \|= UART_REG_IIR_64BYTE_FIFOS_EN;
334
335	pThis->uRegIir = uRegIirNew;
336	}
337
338
339	/**
340	* Returns the amount of bytes stored in the given FIFO.
341	*
342	* @returns Amount of bytes stored in the FIFO.
343	* @param pFifo The FIFO.
344	*/
345	DECLINLINE(size_t) uartFifoUsedGet(PUARTFIFO pFifo)
346	{
347	return pFifo->cbUsed;
348	}
349
350
351	/**
352	* Puts a new character into the given FIFO.
353	*
354	* @returns Flag whether the FIFO overflowed.
355	* @param pFifo The FIFO to put the data into.
356	* @param fOvrWr Flag whether to overwrite data if the FIFO is full.
357	* @param bData The data to add.
358	*/
359	DECLINLINE(bool) uartFifoPut(PUARTFIFO pFifo, bool fOvrWr, uint8_t bData)
360	{
361	if (fOvrWr \|\| pFifo->cbUsed < pFifo->cbMax)
362	{
363	pFifo->abBuf[pFifo->offWrite] = bData;
364	pFifo->offWrite = (pFifo->offWrite + 1) % pFifo->cbMax;
365	}
366
367	bool fOverFlow = false;
368	if (pFifo->cbUsed < pFifo->cbMax)
369	pFifo->cbUsed++;
370	else
371	{
372	fOverFlow = true;
373	if (fOvrWr) /* Advance the read position to account for the lost character. */
374	pFifo->offRead = (pFifo->offRead + 1) % pFifo->cbMax;
375	}
376
377	return fOverFlow;
378	}
379
380
381	/**
382	* Returns the next character in the FIFO.
383	*
384	* @return Next byte in the FIFO.
385	* @param pFifo The FIFO to get data from.
386	*/
387	DECLINLINE(uint8_t) uartFifoGet(PUARTFIFO pFifo)
388	{
389	uint8_t bRet = 0;
390
391	if (pFifo->cbUsed)
392	{
393	bRet = pFifo->abBuf[pFifo->offRead];
394	pFifo->offRead = (pFifo->offRead + 1) % pFifo->cbMax;
395	pFifo->cbUsed--;
396	}
397
398	return bRet;
399	}
400
401
402	#ifdef IN_RING3
403	/**
404	* Clears the given FIFO.
405	*
406	* @returns nothing.
407	* @param pFifo The FIFO to clear.
408	*/
409	DECLINLINE(void) uartFifoClear(PUARTFIFO pFifo)
410	{
411	memset(&pFifo->abBuf[0], 0, sizeof(pFifo->abBuf));
412	pFifo->cbUsed = 0;
413	pFifo->offWrite = 0;
414	pFifo->offRead = 0;
415	}
416
417
418	/**
419	* Returns the amount of free bytes in the given FIFO.
420	*
421	* @returns The amount of bytes free in the given FIFO.
422	* @param pFifo The FIFO.
423	*/
424	DECLINLINE(size_t) uartFifoFreeGet(PUARTFIFO pFifo)
425	{
426	return pFifo->cbMax - pFifo->cbUsed;
427	}
428
429
430	/**
431	* Tries to copy the requested amount of data from the given FIFO into the provided buffer.
432	*
433	* @returns Amount of bytes actually copied.
434	* @param pFifo The FIFO to copy data from.
435	* @param pvDst Where to copy the data to.
436	* @param cbCopy How much to copy.
437	*/
438	DECLINLINE(size_t) uartFifoCopyTo(PUARTFIFO pFifo, void *pvDst, size_t cbCopy)
439	{
440	size_t cbCopied = 0;
441	uint8_t pbDst = (uint8_t )pvDst;
442
443	cbCopy = RT_MIN(cbCopy, pFifo->cbUsed);
444	while (cbCopy)
445	{
446	uint8_t cbThisCopy = (uint8_t)RT_MIN(cbCopy, (uint8_t)(pFifo->cbMax - pFifo->offRead));
447	memcpy(pbDst, &pFifo->abBuf[pFifo->offRead], cbThisCopy);
448
449	pFifo->offRead = (pFifo->offRead + cbThisCopy) % pFifo->cbMax;
450	pFifo->cbUsed -= cbThisCopy;
451	pbDst += cbThisCopy;
452	cbCopied += cbThisCopy;
453	cbCopy -= cbThisCopy;
454	}
455
456	return cbCopied;
457	}
458
459
460	#if 0 /* unused */
461	/**
462	* Tries to copy the requested amount of data from the provided buffer into the given FIFO.
463	*
464	* @returns Amount of bytes actually copied.
465	* @param pFifo The FIFO to copy data to.
466	* @param pvSrc Where to copy the data from.
467	* @param cbCopy How much to copy.
468	*/
469	DECLINLINE(size_t) uartFifoCopyFrom(PUARTFIFO pFifo, void *pvSrc, size_t cbCopy)
470	{
471	size_t cbCopied = 0;
472	uint8_t pbSrc = (uint8_t )pvSrc;
473
474	cbCopy = RT_MIN(cbCopy, uartFifoFreeGet(pFifo));
475	while (cbCopy)
476	{
477	uint8_t cbThisCopy = (uint8_t)RT_MIN(cbCopy, (uint8_t)(pFifo->cbMax - pFifo->offWrite));
478	memcpy(&pFifo->abBuf[pFifo->offWrite], pbSrc, cbThisCopy);
479
480	pFifo->offWrite = (pFifo->offWrite + cbThisCopy) % pFifo->cbMax;
481	pFifo->cbUsed += cbThisCopy;
482	pbSrc += cbThisCopy;
483	cbCopied += cbThisCopy;
484	cbCopy -= cbThisCopy;
485	}
486
487	return cbCopied;
488	}
489	#endif
490
491
492	/**
493	* Updates the delta bits for the given MSR register value which has the status line
494	* bits set.
495	*
496	* @returns nothing.
497	* @param pThis The serial port instance.
498	* @param uMsrSts MSR value with the appropriate status bits set.
499	*/
500	static void uartR3MsrUpdate(PUARTCORE pThis, uint8_t uMsrSts)
501	{
502	/* Compare current and new states and set remaining bits accordingly. */
503	if ((uMsrSts & UART_REG_MSR_CTS) != (pThis->uRegMsr & UART_REG_MSR_CTS))
504	uMsrSts \|= UART_REG_MSR_DCTS;
505	if ((uMsrSts & UART_REG_MSR_DSR) != (pThis->uRegMsr & UART_REG_MSR_DSR))
506	uMsrSts \|= UART_REG_MSR_DDSR;
507	if ((uMsrSts & UART_REG_MSR_RI) != 0 && (pThis->uRegMsr & UART_REG_MSR_RI) == 0)
508	uMsrSts \|= UART_REG_MSR_TERI;
509	if ((uMsrSts & UART_REG_MSR_DCD) != (pThis->uRegMsr & UART_REG_MSR_DCD))
510	uMsrSts \|= UART_REG_MSR_DDCD;
511
512	pThis->uRegMsr = uMsrSts;
513
514	uartIrqUpdate(pThis);
515	}
516
517
518	/**
519	* Updates the serial port parameters of the attached driver with the current configuration.
520	*
521	* @returns nothing.
522	* @param pThis The serial port instance.
523	*/
524	static void uartR3ParamsUpdate(PUARTCORE pThis)
525	{
526	if ( pThis->uRegDivisor != 0
527	&& pThis->pDrvSerial)
528	{
529	uint32_t uBps = 115200 / pThis->uRegDivisor; /* This is for PC compatible serial port with a 1.8432 MHz crystal. */
530	unsigned cDataBits = UART_REG_LCR_WLS_GET(pThis->uRegLcr) + 5;
531	uint32_t cFrameBits = cDataBits;
532	PDMSERIALSTOPBITS enmStopBits = PDMSERIALSTOPBITS_ONE;
533	PDMSERIALPARITY enmParity = PDMSERIALPARITY_NONE;
534
535	if (pThis->uRegLcr & UART_REG_LCR_STB)
536	{
537	enmStopBits = cDataBits == 5 ? PDMSERIALSTOPBITS_ONEPOINTFIVE : PDMSERIALSTOPBITS_TWO;
538	cFrameBits += 2;
539	}
540	else
541	cFrameBits++;
542
543	if (pThis->uRegLcr & UART_REG_LCR_PEN)
544	{
545	/* Select the correct parity mode based on the even and stick parity bits. */
546	switch (pThis->uRegLcr & (UART_REG_LCR_EPS \| UART_REG_LCR_PAR_STICK))
547	{
548	case 0:
549	enmParity = PDMSERIALPARITY_ODD;
550	break;
551	case UART_REG_LCR_EPS:
552	enmParity = PDMSERIALPARITY_EVEN;
553	break;
554	case UART_REG_LCR_EPS \| UART_REG_LCR_PAR_STICK:
555	enmParity = PDMSERIALPARITY_SPACE;
556	break;
557	case UART_REG_LCR_PAR_STICK:
558	enmParity = PDMSERIALPARITY_MARK;
559	break;
560	default:
561	/* We should never get here as all cases where caught earlier. */
562	AssertMsgFailed(("This shouldn't happen at all: %#x\n",
563	pThis->uRegLcr & (UART_REG_LCR_EPS \| UART_REG_LCR_PAR_STICK)));
564	}
565
566	cFrameBits++;
567	}
568
569	uint64_t uTimerFreq = TMTimerGetFreq(pThis->CTX_SUFF(pTimerRcvFifoTimeout));
570	pThis->cSymbolXferTicks = (uTimerFreq / uBps) * cFrameBits;
571
572	LogFlowFunc(("Changing parameters to: %u,%s,%u,%s\n",
573	uBps, s_aszParity[enmParity], cDataBits, s_aszStopBits[enmStopBits]));
574
575	int rc = pThis->pDrvSerial->pfnChgParams(pThis->pDrvSerial, uBps, enmParity, cDataBits, enmStopBits);
576	if (RT_FAILURE(rc))
577	LogRelMax(10, ("Serial#%d: Failed to change parameters to %u,%s,%u,%s -> %Rrc\n",
578	pThis->pDevInsR3->iInstance, uBps, s_aszParity[enmParity], cDataBits, s_aszStopBits[enmStopBits], rc));
579
580	/* Changed parameters will flush all receive queues, so there won't be any data to read even if indicated. */
581	pThis->pDrvSerial->pfnQueuesFlush(pThis->pDrvSerial, true /fQueueRecv/, false /fQueueXmit/);
582	ASMAtomicWriteU32(&pThis->cbAvailRdr, 0);
583	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
584	}
585	}
586
587
588	/**
589	* Updates the internal device state with the given PDM status line states.
590	*
591	* @returns nothing.
592	* @param pThis The serial port instance.
593	* @param fStsLines The PDM status line states.
594	*/
595	static void uartR3StsLinesUpdate(PUARTCORE pThis, uint32_t fStsLines)
596	{
597	uint8_t uRegMsrNew = 0; /* The new MSR value. */
598
599	if (fStsLines & PDMISERIALPORT_STS_LINE_DCD)
600	uRegMsrNew \|= UART_REG_MSR_DCD;
601	if (fStsLines & PDMISERIALPORT_STS_LINE_RI)
602	uRegMsrNew \|= UART_REG_MSR_RI;
603	if (fStsLines & PDMISERIALPORT_STS_LINE_DSR)
604	uRegMsrNew \|= UART_REG_MSR_DSR;
605	if (fStsLines & PDMISERIALPORT_STS_LINE_CTS)
606	uRegMsrNew \|= UART_REG_MSR_CTS;
607
608	uartR3MsrUpdate(pThis, uRegMsrNew);
609	}
610
611
612	/**
613	* Fills up the receive FIFO with as much data as possible.
614	*
615	* @returns nothing.
616	* @param pThis The serial port instance.
617	*/
618	static void uartR3RecvFifoFill(PUARTCORE pThis)
619	{
620	LogFlowFunc(("pThis=%#p\n", pThis));
621
622	PUARTFIFO pFifo = &pThis->FifoRecv;
623	size_t cbFill = RT_MIN(uartFifoFreeGet(pFifo),
624	ASMAtomicReadU32(&pThis->cbAvailRdr));
625	size_t cbFilled = 0;
626
627	while (cbFilled < cbFill)
628	{
629	size_t cbThisRead = cbFill - cbFilled;
630
631	if (pFifo->offRead <= pFifo->offWrite)
632	cbThisRead = RT_MIN(cbThisRead, (uint8_t)(pFifo->cbMax - pFifo->offWrite));
633	else
634	cbThisRead = RT_MIN(cbThisRead, (uint8_t)(pFifo->offRead - pFifo->offWrite));
635
636	size_t cbRead = 0;
637	int rc = pThis->pDrvSerial->pfnReadRdr(pThis->pDrvSerial, &pFifo->abBuf[pFifo->offWrite], cbThisRead, &cbRead);
638	AssertRC(rc); Assert(cbRead <= UINT8_MAX); RT_NOREF(rc);
639
640	pFifo->offWrite = (pFifo->offWrite + (uint8_t)cbRead) % pFifo->cbMax;
641	pFifo->cbUsed += (uint8_t)cbRead;
642	cbFilled += cbRead;
643
644	if (cbRead < cbThisRead)
645	break;
646	}
647
648	if (cbFilled)
649	{
650	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
651	if (pFifo->cbUsed < pFifo->cbItl)
652	{
653	pThis->fIrqCtiPending = false;
654	TMTimerSetRelative(pThis->CTX_SUFF(pTimerRcvFifoTimeout), pThis->cSymbolXferTicks * 4, NULL);
655	}
656	uartIrqUpdate(pThis);
657	}
658
659	Assert(cbFilled <= (size_t)pThis->cbAvailRdr);
660	ASMAtomicSubU32(&pThis->cbAvailRdr, (uint32_t)cbFilled);
661	}
662
663
664	/**
665	* Fetches a single byte and writes it to RBR.
666	*
667	* @returns nothing.
668	* @param pThis The serial port instance.
669	*/
670	static void uartR3ByteFetch(PUARTCORE pThis)
671	{
672	if (ASMAtomicReadU32(&pThis->cbAvailRdr))
673	{
674	AssertPtr(pThis->pDrvSerial);
675	size_t cbRead = 0;
676	int rc2 = pThis->pDrvSerial->pfnReadRdr(pThis->pDrvSerial, &pThis->uRegRbr, 1, &cbRead);
677	AssertMsg(RT_SUCCESS(rc2) && cbRead == 1, ("This shouldn't fail and always return one byte!\n")); RT_NOREF(rc2);
678	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
679	uartIrqUpdate(pThis);
680	}
681	}
682
683
684	/**
685	* Fetches a ready data based on the FIFO setting.
686	*
687	* @returns nothing.
688	* @param pThis The serial port instance.
689	*/
690	static void uartR3DataFetch(PUARTCORE pThis)
691	{
692	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
693	uartR3RecvFifoFill(pThis);
694	else
695	uartR3ByteFetch(pThis);
696	}
697
698
699	/**
700	* Reset the transmit/receive related bits to the standard values
701	* (after a detach/attach/reset event).
702	*
703	* @returns nothing.
704	* @param pThis The serial port instance.
705	*/
706	static void uartR3XferReset(PUARTCORE pThis)
707	{
708	pThis->uRegLsr = UART_REG_LSR_THRE \| UART_REG_LSR_TEMT;
709	pThis->fThreEmptyPending = false;
710
711	uartFifoClear(&pThis->FifoXmit);
712	uartFifoClear(&pThis->FifoRecv);
713	uartR3ParamsUpdate(pThis);
714	uartIrqUpdate(pThis);
715
716	if (pThis->pDrvSerial)
717	{
718	/* Set the modem lines to reflect the current state. */
719	int rc = pThis->pDrvSerial->pfnChgModemLines(pThis->pDrvSerial, false /fRts/, false /fDtr/);
720	if (RT_FAILURE(rc))
721	LogRel(("Serial#%d: Failed to set modem lines with %Rrc during reset\n",
722	pThis->pDevInsR3->iInstance, rc));
723
724	uint32_t fStsLines = 0;
725	rc = pThis->pDrvSerial->pfnQueryStsLines(pThis->pDrvSerial, &fStsLines);
726	if (RT_SUCCESS(rc))
727	uartR3StsLinesUpdate(pThis, fStsLines);
728	else
729	LogRel(("Serial#%d: Failed to query status line status with %Rrc during reset\n",
730	pThis->pDevInsR3->iInstance, rc));
731	}
732
733	}
734	#endif
735
736
737	/**
738	* Write handler for the THR/DLL register (depending on the DLAB bit in LCR).
739	*
740	* @returns VBox status code.
741	* @param pThis The serial port instance.
742	* @param uVal The value to write.
743	*/
744	DECLINLINE(int) uartRegThrDllWrite(PUARTCORE pThis, uint8_t uVal)
745	{
746	int rc = VINF_SUCCESS;
747
748	/* A set DLAB causes a write to the lower 8bits of the divisor latch. */
749	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
750	{
751	if (uVal != (pThis->uRegDivisor & 0xff))
752	{
753	#ifndef IN_RING3
754	rc = VINF_IOM_R3_IOPORT_WRITE;
755	#else
756	pThis->uRegDivisor = (pThis->uRegDivisor & 0xff00) \| uVal;
757	uartR3ParamsUpdate(pThis);
758	#endif
759	}
760	}
761	else
762	{
763	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
764	{
765	#ifndef IN_RING3
766	if (!uartFifoUsedGet(&pThis->FifoXmit))
767	rc = VINF_IOM_R3_IOPORT_WRITE;
768	else
769	{
770	uartFifoPut(&pThis->FifoXmit, true /fOvrWr/, uVal);
771	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE \| UART_REG_LSR_TEMT);
772	}
773	#else
774	uartFifoPut(&pThis->FifoXmit, true /fOvrWr/, uVal);
775	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE \| UART_REG_LSR_TEMT);
776	pThis->fThreEmptyPending = false;
777	uartIrqUpdate(pThis);
778	if ( pThis->pDrvSerial
779	&& uartFifoUsedGet(&pThis->FifoXmit) == 1)
780	{
781	int rc2 = pThis->pDrvSerial->pfnDataAvailWrNotify(pThis->pDrvSerial);
782	if (RT_FAILURE(rc2))
783	LogRelMax(10, ("Serial#%d: Failed to send data with %Rrc\n", pThis->pDevInsR3->iInstance, rc2));
784	}
785	#endif
786	}
787	else
788	{
789	/* Notify the lower driver about available data only if the register was empty before. */
790	if (pThis->uRegLsr & UART_REG_LSR_THRE)
791	{
792	#ifndef IN_RING3
793	rc = VINF_IOM_R3_IOPORT_WRITE;
794	#else
795	pThis->uRegThr = uVal;
796	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE \| UART_REG_LSR_TEMT);
797	pThis->fThreEmptyPending = false;
798	uartIrqUpdate(pThis);
799	if (pThis->pDrvSerial)
800	{
801	int rc2 = pThis->pDrvSerial->pfnDataAvailWrNotify(pThis->pDrvSerial);
802	if (RT_FAILURE(rc2))
803	LogRelMax(10, ("Serial#%d: Failed to send data with %Rrc\n", pThis->pDevInsR3->iInstance, rc2));
804	}
805	#endif
806	}
807	else
808	pThis->uRegThr = uVal;
809	}
810	}
811
812	return rc;
813	}
814
815
816	/**
817	* Write handler for the IER/DLM register (depending on the DLAB bit in LCR).
818	*
819	* @returns VBox status code.
820	* @param pThis The serial port instance.
821	* @param uVal The value to write.
822	*/
823	DECLINLINE(int) uartRegIerDlmWrite(PUARTCORE pThis, uint8_t uVal)
824	{
825	int rc = VINF_SUCCESS;
826
827	/* A set DLAB causes a write to the higher 8bits of the divisor latch. */
828	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
829	{
830	if (uVal != (pThis->uRegDivisor & 0xff00) >> 8)
831	{
832	#ifndef IN_RING3
833	rc = VINF_IOM_R3_IOPORT_WRITE;
834	#else
835	pThis->uRegDivisor = (pThis->uRegDivisor & 0xff) \| (uVal << 8);
836	uartR3ParamsUpdate(pThis);
837	#endif
838	}
839	}
840	else
841	{
842	if (pThis->enmType < UARTTYPE_16750)
843	pThis->uRegIer = uVal & UART_REG_IER_MASK_WR;
844	else
845	pThis->uRegIer = uVal & UART_REG_IER_MASK_WR_16750;
846
847	if (pThis->uRegLsr & UART_REG_LSR_THRE)
848	pThis->fThreEmptyPending = true;
849
850	uartIrqUpdate(pThis);
851	}
852
853	return rc;
854	}
855
856
857	/**
858	* Write handler for the FCR register.
859	*
860	* @returns VBox status code.
861	* @param pThis The serial port instance.
862	* @param uVal The value to write.
863	*/
864	DECLINLINE(int) uartRegFcrWrite(PUARTCORE pThis, uint8_t uVal)
865	{
866	#ifndef IN_RING3
867	RT_NOREF(pThis, uVal);
868	return VINF_IOM_R3_IOPORT_WRITE;
869	#else
870	int rc = VINF_SUCCESS;
871	if ( pThis->enmType >= UARTTYPE_16550A
872	&& uVal != pThis->uRegFcr)
873	{
874	/* A change in the FIFO enable bit clears both FIFOs automatically. */
875	if ((uVal ^ pThis->uRegFcr) & UART_REG_FCR_FIFO_EN)
876	{
877	uartFifoClear(&pThis->FifoXmit);
878	uartFifoClear(&pThis->FifoRecv);
879
880	/*
881	* If the FIFO is about to be enabled and the DR bit is ready we have an unacknowledged
882	* byte in the RBR register which will be lost so we have to adjust the available bytes.
883	*/
884	if ( ASMAtomicReadU32(&pThis->cbAvailRdr) > 0
885	&& (uVal & UART_REG_FCR_FIFO_EN))
886	ASMAtomicDecU32(&pThis->cbAvailRdr);
887
888	/* Clear the DR bit too. */
889	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
890	}
891
892	if (rc == VINF_SUCCESS)
893	{
894	if (uVal & UART_REG_FCR_RCV_FIFO_RST)
895	{
896	TMTimerStop(pThis->CTX_SUFF(pTimerRcvFifoTimeout));
897	pThis->fIrqCtiPending = false;
898	uartFifoClear(&pThis->FifoRecv);
899	}
900	if (uVal & UART_REG_FCR_XMIT_FIFO_RST)
901	uartFifoClear(&pThis->FifoXmit);
902
903	/*
904	* The 64byte FIFO enable bit is only changeable for 16750
905	* and if the DLAB bit in LCR is set.
906	*/
907	if ( pThis->enmType < UARTTYPE_16750
908	\|\| !(pThis->uRegLcr & UART_REG_LCR_DLAB))
909	uVal &= ~UART_REG_FCR_64BYTE_FIFO_EN;
910	else /* Use previous value. */
911	uVal \|= pThis->uRegFcr & UART_REG_FCR_64BYTE_FIFO_EN;
912
913	if (uVal & UART_REG_FCR_64BYTE_FIFO_EN)
914	{
915	pThis->FifoRecv.cbMax = 64;
916	pThis->FifoXmit.cbMax = 64;
917	}
918	else
919	{
920	pThis->FifoRecv.cbMax = 16;
921	pThis->FifoXmit.cbMax = 16;
922	}
923
924	if (uVal & UART_REG_FCR_FIFO_EN)
925	{
926	uint8_t idxItl = UART_REG_FCR_RCV_LVL_IRQ_GET(uVal);
927	if (uVal & UART_REG_FCR_64BYTE_FIFO_EN)
928	pThis->FifoRecv.cbItl = s_aFifoItl[idxItl].cbItl64;
929	else
930	pThis->FifoRecv.cbItl = s_aFifoItl[idxItl].cbItl16;
931	}
932
933	/* The FIFO reset bits are self clearing. */
934	pThis->uRegFcr = uVal & UART_REG_FCR_MASK_STICKY;
935	uartIrqUpdate(pThis);
936	}
937
938	/* Fill in the next data. */
939	if (ASMAtomicReadU32(&pThis->cbAvailRdr))
940	uartR3DataFetch(pThis);
941	}
942
943	return rc;
944	#endif
945	}
946
947
948	/**
949	* Write handler for the LCR register.
950	*
951	* @returns VBox status code.
952	* @param pThis The serial port instance.
953	* @param uVal The value to write.
954	*/
955	DECLINLINE(int) uartRegLcrWrite(PUARTCORE pThis, uint8_t uVal)
956	{
957	int rc = VINF_SUCCESS;
958
959	/* Any change except the DLAB bit causes a switch to R3. */
960	if ((pThis->uRegLcr & ~UART_REG_LCR_DLAB) != (uVal & ~UART_REG_LCR_DLAB))
961	{
962	#ifndef IN_RING3
963	rc = VINF_IOM_R3_IOPORT_WRITE;
964	#else
965	/* Check whether the BREAK bit changed before updating the LCR value. */
966	bool fBrkEn = RT_BOOL(uVal & UART_REG_LCR_BRK_SET);
967	bool fBrkChg = fBrkEn != RT_BOOL(pThis->uRegLcr & UART_REG_LCR_BRK_SET);
968	pThis->uRegLcr = uVal;
969	uartR3ParamsUpdate(pThis);
970
971	if ( fBrkChg
972	&& pThis->pDrvSerial)
973	pThis->pDrvSerial->pfnChgBrk(pThis->pDrvSerial, fBrkEn);
974	#endif
975	}
976	else
977	pThis->uRegLcr = uVal;
978
979	return rc;
980	}
981
982
983	/**
984	* Write handler for the MCR register.
985	*
986	* @returns VBox status code.
987	* @param pThis The serial port instance.
988	* @param uVal The value to write.
989	*/
990	DECLINLINE(int) uartRegMcrWrite(PUARTCORE pThis, uint8_t uVal)
991	{
992	int rc = VINF_SUCCESS;
993
994	if (pThis->enmType < UARTTYPE_16750)
995	uVal &= UART_REG_MCR_MASK_WR;
996	else
997	uVal &= UART_REG_MCR_MASK_WR_15750;
998	if (pThis->uRegMcr != uVal)
999	{
1000	#ifndef IN_RING3
1001	rc = VINF_IOM_R3_IOPORT_WRITE;
1002	#else
1003	/*
1004	* When loopback mode is activated the RTS, DTR, OUT1 and OUT2 lines are
1005	* disconnected and looped back to MSR.
1006	*/
1007	if ( (uVal & UART_REG_MCR_LOOP)
1008	&& !(pThis->uRegMcr & UART_REG_MCR_LOOP)
1009	&& pThis->pDrvSerial)
1010	pThis->pDrvSerial->pfnChgModemLines(pThis->pDrvSerial, false /fRts/, false /fDtr/);
1011
1012	pThis->uRegMcr = uVal;
1013	if (uVal & UART_REG_MCR_LOOP)
1014	{
1015	uint8_t uRegMsrSts = 0;
1016
1017	if (uVal & UART_REG_MCR_RTS)
1018	uRegMsrSts \|= UART_REG_MSR_CTS;
1019	if (uVal & UART_REG_MCR_DTR)
1020	uRegMsrSts \|= UART_REG_MSR_DSR;
1021	if (uVal & UART_REG_MCR_OUT1)
1022	uRegMsrSts \|= UART_REG_MSR_RI;
1023	if (uVal & UART_REG_MCR_OUT2)
1024	uRegMsrSts \|= UART_REG_MSR_DCD;
1025	uartR3MsrUpdate(pThis, uRegMsrSts);
1026	}
1027	else if (pThis->pDrvSerial)
1028	pThis->pDrvSerial->pfnChgModemLines(pThis->pDrvSerial,
1029	RT_BOOL(uVal & UART_REG_MCR_RTS),
1030	RT_BOOL(uVal & UART_REG_MCR_DTR));
1031	#endif
1032	}
1033
1034	return rc;
1035	}
1036
1037
1038	/**
1039	* Read handler for the RBR/DLL register (depending on the DLAB bit in LCR).
1040	*
1041	* @returns VBox status code.
1042	* @param pThis The serial port instance.
1043	* @param puVal Where to store the read value on success.
1044	*/
1045	DECLINLINE(int) uartRegRbrDllRead(PUARTCORE pThis, uint32_t *puVal)
1046	{
1047	int rc = VINF_SUCCESS;
1048
1049	/* A set DLAB causes a read from the lower 8bits of the divisor latch. */
1050	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1051	*puVal = pThis->uRegDivisor & 0xff;
1052	else
1053	{
1054	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
1055	{
1056	/*
1057	* Only go back to R3 if there is new data available for the FIFO
1058	* and we would clear the interrupt to fill it up again.
1059	*/
1060	if ( pThis->FifoRecv.cbUsed <= pThis->FifoRecv.cbItl
1061	&& ASMAtomicReadU32(&pThis->cbAvailRdr) > 0)
1062	{
1063	#ifndef IN_RING3
1064	rc = VINF_IOM_R3_IOPORT_READ;
1065	#else
1066	uartR3RecvFifoFill(pThis);
1067	#endif
1068	}
1069
1070	if (rc == VINF_SUCCESS)
1071	{
1072	*puVal = uartFifoGet(&pThis->FifoRecv);
1073	pThis->fIrqCtiPending = false;
1074	if (!pThis->FifoRecv.cbUsed)
1075	{
1076	TMTimerStop(pThis->CTX_SUFF(pTimerRcvFifoTimeout));
1077	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
1078	}
1079	else if (pThis->FifoRecv.cbUsed < pThis->FifoRecv.cbItl)
1080	TMTimerSetRelative(pThis->CTX_SUFF(pTimerRcvFifoTimeout), pThis->cSymbolXferTicks * 4, NULL);
1081	uartIrqUpdate(pThis);
1082	}
1083	}
1084	else
1085	{
1086	*puVal = pThis->uRegRbr;
1087
1088	if (pThis->uRegLsr & UART_REG_LSR_DR)
1089	{
1090	Assert(pThis->cbAvailRdr);
1091	uint32_t cbAvail = ASMAtomicDecU32(&pThis->cbAvailRdr);
1092	if (!cbAvail)
1093	{
1094	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
1095	uartIrqUpdate(pThis);
1096	}
1097	else
1098	{
1099	#ifndef IN_RING3
1100	/* Restore state and go back to R3. */
1101	ASMAtomicIncU32(&pThis->cbAvailRdr);
1102	rc = VINF_IOM_R3_IOPORT_READ;
1103	#else
1104	/* Fetch new data and keep the DR bit set. */
1105	uartR3DataFetch(pThis);
1106	#endif
1107	}
1108	}
1109	}
1110	}
1111
1112	return rc;
1113	}
1114
1115
1116	/**
1117	* Read handler for the IER/DLM register (depending on the DLAB bit in LCR).
1118	*
1119	* @returns VBox status code.
1120	* @param pThis The serial port instance.
1121	* @param puVal Where to store the read value on success.
1122	*/
1123	DECLINLINE(int) uartRegIerDlmRead(PUARTCORE pThis, uint32_t *puVal)
1124	{
1125	int rc = VINF_SUCCESS;
1126
1127	/* A set DLAB causes a read from the upper 8bits of the divisor latch. */
1128	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1129	*puVal = (pThis->uRegDivisor & 0xff00) >> 8;
1130	else
1131	*puVal = pThis->uRegIer;
1132
1133	return rc;
1134	}
1135
1136
1137	/**
1138	* Read handler for the IIR register.
1139	*
1140	* @returns VBox status code.
1141	* @param pThis The serial port instance.
1142	* @param puVal Where to store the read value on success.
1143	*/
1144	DECLINLINE(int) uartRegIirRead(PUARTCORE pThis, uint32_t *puVal)
1145	{
1146	*puVal = pThis->uRegIir;
1147	/* Reset the THRE empty interrupt id when this gets returned to the guest (see table 3 UART Reset configuration). */
1148	if (UART_REG_IIR_ID_GET(pThis->uRegIir) == UART_REG_IIR_ID_THRE)
1149	{
1150	pThis->fThreEmptyPending = false;
1151	uartIrqUpdate(pThis);
1152	}
1153	return VINF_SUCCESS;
1154	}
1155
1156
1157	/**
1158	* Read handler for the LSR register.
1159	*
1160	* @returns VBox status code.
1161	* @param pThis The serial port instance.
1162	* @param puVal Where to store the read value on success.
1163	*/
1164	DECLINLINE(int) uartRegLsrRead(PUARTCORE pThis, uint32_t *puVal)
1165	{
1166	int rc = VINF_SUCCESS;
1167
1168	/* Yield if configured and there is no data available. */
1169	if ( !(pThis->uRegLsr & UART_REG_LSR_DR)
1170	&& (pThis->fFlags & UART_CORE_YIELD_ON_LSR_READ))
1171	{
1172	#ifndef IN_RING3
1173	return VINF_IOM_R3_IOPORT_READ;
1174	#else
1175	RTThreadYield();
1176	#endif
1177	}
1178
1179	*puVal = pThis->uRegLsr;
1180	/*
1181	* Reading this register clears the Overrun (OE), Parity (PE) and Framing (FE) error
1182	* as well as the Break Interrupt (BI).
1183	*/
1184	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_BITS_IIR_RCL);
1185	uartIrqUpdate(pThis);
1186
1187	return rc;
1188	}
1189
1190
1191	/**
1192	* Read handler for the MSR register.
1193	*
1194	* @returns VBox status code.
1195	* @param pThis The serial port instance.
1196	* @param puVal Where to store the read value on success.
1197	*/
1198	DECLINLINE(int) uartRegMsrRead(PUARTCORE pThis, uint32_t *puVal)
1199	{
1200	*puVal = pThis->uRegMsr;
1201
1202	/* Clear any of the delta bits. */
1203	UART_REG_CLR(pThis->uRegMsr, UART_REG_MSR_BITS_IIR_MS);
1204	uartIrqUpdate(pThis);
1205	return VINF_SUCCESS;
1206	}
1207
1208
1209	#ifdef LOG_ENABLED
1210	/**
1211	* Converts the register index into a sensible memnonic.
1212	*
1213	* @returns Register memnonic.
1214	* @param pThis The serial port instance.
1215	* @param idxReg Register index.
1216	* @param fWrite Flag whether the register gets written.
1217	*/
1218	DECLINLINE(const char *) uartRegIdx2Str(PUARTCORE pThis, uint8_t idxReg, bool fWrite)
1219	{
1220	const char *psz = "INV";
1221
1222	switch (idxReg)
1223	{
1224	/case UART_REG_THR_DLL_INDEX:/
1225	case UART_REG_RBR_DLL_INDEX:
1226	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1227	psz = "DLL";
1228	else if (fWrite)
1229	psz = "THR";
1230	else
1231	psz = "RBR";
1232	break;
1233	case UART_REG_IER_DLM_INDEX:
1234	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1235	psz = "DLM";
1236	else
1237	psz = "IER";
1238	break;
1239	/case UART_REG_IIR_INDEX:/
1240	case UART_REG_FCR_INDEX:
1241	if (fWrite)
1242	psz = "FCR";
1243	else
1244	psz = "IIR";
1245	break;
1246	case UART_REG_LCR_INDEX:
1247	psz = "LCR";
1248	break;
1249	case UART_REG_MCR_INDEX:
1250	psz = "MCR";
1251	break;
1252	case UART_REG_LSR_INDEX:
1253	psz = "LSR";
1254	break;
1255	case UART_REG_MSR_INDEX:
1256	psz = "MSR";
1257	break;
1258	case UART_REG_SCR_INDEX:
1259	psz = "SCR";
1260	break;
1261	}
1262
1263	return psz;
1264	}
1265	#endif
1266
1267
1268	DECLHIDDEN(int) uartRegWrite(PUARTCORE pThis, uint32_t uReg, uint32_t u32, size_t cb)
1269	{
1270	AssertMsgReturn(cb == 1, ("uReg=%#x cb=%d u32=%#x\n", uReg, cb, u32), VINF_SUCCESS);
1271
1272	int rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_R3_IOPORT_WRITE);
1273	if (rc != VINF_SUCCESS)
1274	return rc;
1275
1276	uint8_t idxReg = uReg & 0x7;
1277	LogFlowFunc(("pThis=%#p uReg=%u{%s} u32=%#x cb=%u\n",
1278	pThis, uReg, uartRegIdx2Str(pThis, idxReg, true /fWrite/), u32, cb));
1279
1280	uint8_t uVal = (uint8_t)u32;
1281	switch (idxReg)
1282	{
1283	case UART_REG_THR_DLL_INDEX:
1284	rc = uartRegThrDllWrite(pThis, uVal);
1285	break;
1286	case UART_REG_IER_DLM_INDEX:
1287	rc = uartRegIerDlmWrite(pThis, uVal);
1288	break;
1289	case UART_REG_FCR_INDEX:
1290	rc = uartRegFcrWrite(pThis, uVal);
1291	break;
1292	case UART_REG_LCR_INDEX:
1293	rc = uartRegLcrWrite(pThis, uVal);
1294	break;
1295	case UART_REG_MCR_INDEX:
1296	rc = uartRegMcrWrite(pThis, uVal);
1297	break;
1298	case UART_REG_SCR_INDEX:
1299	pThis->uRegScr = u32;
1300	break;
1301	default:
1302	break;
1303	}
1304
1305	PDMCritSectLeave(&pThis->CritSect);
1306	LogFlowFunc(("-> %Rrc\n", rc));
1307	return rc;
1308	}
1309
1310
1311	DECLHIDDEN(int) uartRegRead(PUARTCORE pThis, uint32_t uReg, uint32_t *pu32, size_t cb)
1312	{
1313	if (cb != 1)
1314	return VERR_IOM_IOPORT_UNUSED;
1315
1316	int rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_R3_IOPORT_READ);
1317	if (rc != VINF_SUCCESS)
1318	return rc;
1319
1320	uint8_t idxReg = uReg & 0x7;
1321	switch (idxReg)
1322	{
1323	case UART_REG_RBR_DLL_INDEX:
1324	rc = uartRegRbrDllRead(pThis, pu32);
1325	break;
1326	case UART_REG_IER_DLM_INDEX:
1327	rc = uartRegIerDlmRead(pThis, pu32);
1328	break;
1329	case UART_REG_IIR_INDEX:
1330	rc = uartRegIirRead(pThis, pu32);
1331	break;
1332	case UART_REG_LCR_INDEX:
1333	*pu32 = pThis->uRegLcr;
1334	break;
1335	case UART_REG_MCR_INDEX:
1336	*pu32 = pThis->uRegMcr;
1337	break;
1338	case UART_REG_LSR_INDEX:
1339	rc = uartRegLsrRead(pThis, pu32);
1340	break;
1341	case UART_REG_MSR_INDEX:
1342	rc = uartRegMsrRead(pThis, pu32);
1343	break;
1344	case UART_REG_SCR_INDEX:
1345	*pu32 = pThis->uRegScr;
1346	break;
1347	default:
1348	rc = VERR_IOM_IOPORT_UNUSED;
1349	}
1350
1351	PDMCritSectLeave(&pThis->CritSect);
1352	LogFlowFunc(("pThis=%#p uReg=%u{%s} u32=%#x cb=%u -> %Rrc\n",
1353	pThis, uReg, uartRegIdx2Str(pThis, idxReg, false /fWrite/), *pu32, cb, rc));
1354	return rc;
1355	}
1356
1357
1358	#ifdef IN_RING3
1359
1360	/* -=-=-=-=-=-=-=-=- Timer callbacks -=-=-=-=-=-=-=-=- */
1361
1362	/**
1363	* @callback_method_impl{FNTMTIMERDEV, Fifo timer function.}
1364	*/
1365	static DECLCALLBACK(void) uartR3RcvFifoTimeoutTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1366	{
1367	LogFlowFunc(("pDevIns=%#p pTimer=%#p pvUser=%#p\n", pDevIns, pTimer, pvUser));
1368	RT_NOREF(pDevIns, pTimer);
1369	PUARTCORE pThis = (PUARTCORE)pvUser;
1370	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1371	if (pThis->FifoRecv.cbUsed < pThis->FifoRecv.cbItl)
1372	{
1373	pThis->fIrqCtiPending = true;
1374	uartIrqUpdate(pThis);
1375	}
1376	PDMCritSectLeave(&pThis->CritSect);
1377	}
1378
1379
1380	/* -=-=-=-=-=-=-=-=- PDMISERIALPORT on LUN#0 -=-=-=-=-=-=-=-=- */
1381
1382
1383	/**
1384	* @interface_method_impl{PDMISERIALPORT,pfnDataAvailRdrNotify}
1385	*/
1386	static DECLCALLBACK(int) uartR3DataAvailRdrNotify(PPDMISERIALPORT pInterface, size_t cbAvail)
1387	{
1388	LogFlowFunc(("pInterface=%#p cbAvail=%zu\n", pInterface, cbAvail));
1389	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1390
1391	AssertMsg((uint32_t)cbAvail == cbAvail, ("Too much data available\n"));
1392
1393	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1394	uint32_t cbAvailOld = ASMAtomicAddU32(&pThis->cbAvailRdr, (uint32_t)cbAvail);
1395	LogFlow((" cbAvailRdr=%u -> cbAvailRdr=%u\n", cbAvailOld, cbAvail + cbAvailOld));
1396	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
1397	uartR3RecvFifoFill(pThis);
1398	else if (!cbAvailOld)
1399	{
1400	size_t cbRead = 0;
1401	int rc = pThis->pDrvSerial->pfnReadRdr(pThis->pDrvSerial, &pThis->uRegRbr, 1, &cbRead);
1402	AssertMsg(RT_SUCCESS(rc) && cbRead == 1, ("This shouldn't fail and always return one byte!\n")); RT_NOREF(rc);
1403	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
1404	uartIrqUpdate(pThis);
1405	}
1406	PDMCritSectLeave(&pThis->CritSect);
1407
1408	return VINF_SUCCESS;
1409	}
1410
1411
1412	/**
1413	* @interface_method_impl{PDMISERIALPORT,pfnDataSentNotify}
1414	*/
1415	static DECLCALLBACK(int) uartR3DataSentNotify(PPDMISERIALPORT pInterface)
1416	{
1417	LogFlowFunc(("pInterface=%#p\n", pInterface));
1418	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1419
1420	/* Set the transmitter empty bit because everything was sent. */
1421	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1422	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_TEMT);
1423	uartIrqUpdate(pThis);
1424	PDMCritSectLeave(&pThis->CritSect);
1425	return VINF_SUCCESS;
1426	}
1427
1428
1429	/**
1430	* @interface_method_impl{PDMISERIALPORT,pfnReadWr}
1431	*/
1432	static DECLCALLBACK(int) uartR3ReadWr(PPDMISERIALPORT pInterface, void pvBuf, size_t cbRead, size_t pcbRead)
1433	{
1434	LogFlowFunc(("pInterface=%#p pvBuf=%#p cbRead=%zu pcbRead=%#p\n", pInterface, pvBuf, cbRead, pcbRead));
1435	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1436
1437	AssertReturn(cbRead > 0, VERR_INVALID_PARAMETER);
1438
1439	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1440	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
1441	{
1442	*pcbRead = uartFifoCopyTo(&pThis->FifoXmit, pvBuf, cbRead);
1443	if (!pThis->FifoXmit.cbUsed)
1444	{
1445	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_THRE);
1446	pThis->fThreEmptyPending = true;
1447	}
1448	if (*pcbRead)
1449	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_TEMT);
1450	uartIrqUpdate(pThis);
1451	}
1452	else if (!(pThis->uRegLsr & UART_REG_LSR_THRE))
1453	{
1454	(uint8_t )pvBuf = pThis->uRegThr;
1455	*pcbRead = 1;
1456	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_THRE);
1457	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_TEMT);
1458	pThis->fThreEmptyPending = true;
1459	uartIrqUpdate(pThis);
1460	}
1461	else
1462	{
1463	/*
1464	* This can happen if there was data in the FIFO when the connection was closed,
1465	* idicate this condition to the lower driver by returning 0 bytes.
1466	*/
1467	*pcbRead = 0;
1468	}
1469	PDMCritSectLeave(&pThis->CritSect);
1470
1471	LogFlowFunc(("-> VINF_SUCCESS{pcbRead=%zu}\n", pcbRead));
1472	return VINF_SUCCESS;
1473	}
1474
1475
1476	/**
1477	* @interface_method_impl{PDMISERIALPORT,pfnNotifyStsLinesChanged}
1478	*/
1479	static DECLCALLBACK(int) uartR3NotifyStsLinesChanged(PPDMISERIALPORT pInterface, uint32_t fNewStatusLines)
1480	{
1481	LogFlowFunc(("pInterface=%#p fNewStatusLines=%#x\n", pInterface, fNewStatusLines));
1482	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1483
1484	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1485	uartR3StsLinesUpdate(pThis, fNewStatusLines);
1486	PDMCritSectLeave(&pThis->CritSect);
1487	return VINF_SUCCESS;
1488	}
1489
1490
1491	/**
1492	* @interface_method_impl{PDMISERIALPORT,pfnNotifyBrk}
1493	*/
1494	static DECLCALLBACK(int) uartR3NotifyBrk(PPDMISERIALPORT pInterface)
1495	{
1496	LogFlowFunc(("pInterface=%#p\n", pInterface));
1497	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1498
1499	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1500	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_BI);
1501	uartIrqUpdate(pThis);
1502	PDMCritSectLeave(&pThis->CritSect);
1503	return VINF_SUCCESS;
1504	}
1505
1506
1507	/* -=-=-=-=-=-=-=-=- PDMIBASE -=-=-=-=-=-=-=-=- */
1508
1509	/**
1510	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
1511	*/
1512	static DECLCALLBACK(void ) uartR3QueryInterface(PPDMIBASE pInterface, const char pszIID)
1513	{
1514	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, IBase);
1515	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
1516	PDMIBASE_RETURN_INTERFACE(pszIID, PDMISERIALPORT, &pThis->ISerialPort);
1517	return NULL;
1518	}
1519
1520
1521	DECLHIDDEN(int) uartR3SaveExec(PUARTCORE pThis, PSSMHANDLE pSSM)
1522	{
1523	SSMR3PutU16(pSSM, pThis->uRegDivisor);
1524	SSMR3PutU8(pSSM, pThis->uRegRbr);
1525	SSMR3PutU8(pSSM, pThis->uRegThr);
1526	SSMR3PutU8(pSSM, pThis->uRegIer);
1527	SSMR3PutU8(pSSM, pThis->uRegIir);
1528	SSMR3PutU8(pSSM, pThis->uRegFcr);
1529	SSMR3PutU8(pSSM, pThis->uRegLcr);
1530	SSMR3PutU8(pSSM, pThis->uRegMcr);
1531	SSMR3PutU8(pSSM, pThis->uRegLsr);
1532	SSMR3PutU8(pSSM, pThis->uRegMsr);
1533	SSMR3PutU8(pSSM, pThis->uRegScr);
1534	SSMR3PutBool(pSSM, pThis->fIrqCtiPending);
1535	SSMR3PutBool(pSSM, pThis->fThreEmptyPending);
1536	SSMR3PutU8(pSSM, pThis->FifoXmit.cbMax);
1537	SSMR3PutU8(pSSM, pThis->FifoXmit.cbItl);
1538	SSMR3PutU8(pSSM, pThis->FifoRecv.cbMax);
1539	SSMR3PutU8(pSSM, pThis->FifoRecv.cbItl);
1540
1541	return TMR3TimerSave(pThis->pTimerRcvFifoTimeoutR3, pSSM);
1542	}
1543
1544
1545	DECLHIDDEN(int) uartR3LoadExec(PUARTCORE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass,
1546	uint8_t puIrq, RTIOPORT pPortBase)
1547	{
1548	RT_NOREF(uPass);
1549	int rc = VINF_SUCCESS;
1550
1551	if (uVersion > UART_SAVED_STATE_VERSION_LEGACY_CODE)
1552	{
1553	SSMR3GetU16(pSSM, &pThis->uRegDivisor);
1554	SSMR3GetU8(pSSM, &pThis->uRegRbr);
1555	SSMR3GetU8(pSSM, &pThis->uRegThr);
1556	SSMR3GetU8(pSSM, &pThis->uRegIer);
1557	SSMR3GetU8(pSSM, &pThis->uRegIir);
1558	SSMR3GetU8(pSSM, &pThis->uRegFcr);
1559	SSMR3GetU8(pSSM, &pThis->uRegLcr);
1560	SSMR3GetU8(pSSM, &pThis->uRegMcr);
1561	SSMR3GetU8(pSSM, &pThis->uRegLsr);
1562	SSMR3GetU8(pSSM, &pThis->uRegMsr);
1563	SSMR3GetU8(pSSM, &pThis->uRegScr);
1564	SSMR3GetBool(pSSM, &pThis->fIrqCtiPending);
1565	SSMR3GetBool(pSSM, &pThis->fThreEmptyPending);
1566	SSMR3GetU8(pSSM, &pThis->FifoXmit.cbMax);
1567	SSMR3GetU8(pSSM, &pThis->FifoXmit.cbItl);
1568	SSMR3GetU8(pSSM, &pThis->FifoRecv.cbMax);
1569	SSMR3GetU8(pSSM, &pThis->FifoRecv.cbItl);
1570
1571	TMR3TimerLoad(pThis->pTimerRcvFifoTimeoutR3, pSSM);
1572	}
1573	else
1574	{
1575	if (uVersion == UART_SAVED_STATE_VERSION_16450)
1576	{
1577	pThis->enmType = UARTTYPE_16450;
1578	LogRel(("Serial#%d: falling back to 16450 mode from load state\n", pThis->pDevInsR3->iInstance));
1579	}
1580
1581	int uIrq;
1582	int32_t iTmp;
1583	uint32_t PortBase;
1584
1585	SSMR3GetU16(pSSM, &pThis->uRegDivisor);
1586	SSMR3GetU8(pSSM, &pThis->uRegRbr);
1587	SSMR3GetU8(pSSM, &pThis->uRegIer);
1588	SSMR3GetU8(pSSM, &pThis->uRegLcr);
1589	SSMR3GetU8(pSSM, &pThis->uRegMcr);
1590	SSMR3GetU8(pSSM, &pThis->uRegLsr);
1591	SSMR3GetU8(pSSM, &pThis->uRegMsr);
1592	SSMR3GetU8(pSSM, &pThis->uRegScr);
1593	if (uVersion > UART_SAVED_STATE_VERSION_16450)
1594	SSMR3GetU8(pSSM, &pThis->uRegFcr);
1595	SSMR3GetS32(pSSM, &iTmp);
1596	pThis->fThreEmptyPending = RT_BOOL(iTmp);
1597	SSMR3GetS32(pSSM, &uIrq);
1598	SSMR3Skip(pSSM, sizeof(int32_t));
1599	SSMR3GetU32(pSSM, &PortBase);
1600	rc = SSMR3Skip(pSSM, sizeof(int32_t));
1601
1602	if ( RT_SUCCESS(rc)
1603	&& uVersion > UART_SAVED_STATE_VERSION_MISSING_BITS)
1604	{
1605	SSMR3GetU8(pSSM, &pThis->uRegThr);
1606	SSMR3Skip(pSSM, sizeof(uint8_t)); /* The old transmit shift register, not used anymore. */
1607	SSMR3GetU8(pSSM, &pThis->uRegIir);
1608
1609	int iTimeoutPending = 0;
1610	SSMR3GetS32(pSSM, &iTimeoutPending);
1611	pThis->fIrqCtiPending = RT_BOOL(iTimeoutPending);
1612
1613	TMR3TimerLoad(pThis->pTimerRcvFifoTimeoutR3, pSSM);
1614	TMR3TimerSkip(pSSM, NULL);
1615	SSMR3GetU8(pSSM, &pThis->FifoRecv.cbItl);
1616	rc = SSMR3GetU8(pSSM, &pThis->FifoRecv.cbItl);
1617	}
1618
1619	if (RT_SUCCESS(rc))
1620	{
1621	AssertPtr(puIrq);
1622	AssertPtr(pPortBase);
1623	*puIrq = (uint8_t)uIrq;
1624	*pPortBase = (RTIOPORT)PortBase;
1625	}
1626	}
1627
1628	return rc;
1629	}
1630
1631
1632	DECLHIDDEN(int) uartR3LoadDone(PUARTCORE pThis, PSSMHANDLE pSSM)
1633	{
1634	RT_NOREF(pSSM);
1635
1636	uartR3ParamsUpdate(pThis);
1637	uartIrqUpdate(pThis);
1638
1639	if (pThis->pDrvSerial)
1640	{
1641	/* Set the modem lines to reflect the current state. */
1642	int rc = pThis->pDrvSerial->pfnChgModemLines(pThis->pDrvSerial,
1643	RT_BOOL(pThis->uRegMcr & UART_REG_MCR_RTS),
1644	RT_BOOL(pThis->uRegMcr & UART_REG_MCR_DTR));
1645	if (RT_FAILURE(rc))
1646	LogRel(("Serial#%d: Failed to set modem lines with %Rrc during saved state load\n",
1647	pThis->pDevInsR3->iInstance, rc));
1648
1649	uint32_t fStsLines = 0;
1650	rc = pThis->pDrvSerial->pfnQueryStsLines(pThis->pDrvSerial, &fStsLines);
1651	if (RT_SUCCESS(rc))
1652	uartR3StsLinesUpdate(pThis, fStsLines);
1653	else
1654	LogRel(("Serial#%d: Failed to query status line status with %Rrc during reset\n",
1655	pThis->pDevInsR3->iInstance, rc));
1656	}
1657
1658	return VINF_SUCCESS;
1659	}
1660
1661
1662	DECLHIDDEN(void) uartR3Relocate(PUARTCORE pThis, RTGCINTPTR offDelta)
1663	{
1664	RT_NOREF(offDelta);
1665	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pThis->pDevInsR3);
1666	pThis->pTimerRcvFifoTimeoutRC = TMTimerRCPtr(pThis->pTimerRcvFifoTimeoutR3);
1667	}
1668
1669
1670	DECLHIDDEN(void) uartR3Reset(PUARTCORE pThis)
1671	{
1672	pThis->uRegDivisor = 0x0c; /* Default to 9600 Baud. */
1673	pThis->uRegRbr = 0;
1674	pThis->uRegThr = 0;
1675	pThis->uRegIer = 0;
1676	pThis->uRegIir = UART_REG_IIR_IP_NO_INT;
1677	pThis->uRegFcr = 0;
1678	pThis->uRegLcr = 0; /* 5 data bits, no parity, 1 stop bit. */
1679	pThis->uRegMcr = 0;
1680	pThis->uRegLsr = UART_REG_LSR_THRE \| UART_REG_LSR_TEMT;
1681	pThis->uRegMsr = 0; /* Updated below. */
1682	pThis->uRegScr = 0;
1683	pThis->fIrqCtiPending = false;
1684	pThis->fThreEmptyPending = true;
1685
1686	/* Standard FIFO size for 15550A. */
1687	pThis->FifoXmit.cbMax = 16;
1688	pThis->FifoRecv.cbMax = 16;
1689	pThis->FifoRecv.cbItl = 1;
1690
1691	uartR3XferReset(pThis);
1692	}
1693
1694
1695	DECLHIDDEN(int) uartR3Attach(PUARTCORE pThis, unsigned iLUN)
1696	{
1697	int rc = PDMDevHlpDriverAttach(pThis->pDevInsR3, iLUN, &pThis->IBase, &pThis->pDrvBase, "Serial Char");
1698	if (RT_SUCCESS(rc))
1699	{
1700	pThis->pDrvSerial = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMISERIALCONNECTOR);
1701	if (!pThis->pDrvSerial)
1702	{
1703	AssertLogRelMsgFailed(("Configuration error: instance %d has no serial interface!\n", pThis->pDevInsR3->iInstance));
1704	return VERR_PDM_MISSING_INTERFACE;
1705	}
1706	uartR3XferReset(pThis);
1707	}
1708	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1709	{
1710	pThis->pDrvBase = NULL;
1711	pThis->pDrvSerial = NULL;
1712	rc = VINF_SUCCESS;
1713	uartR3XferReset(pThis);
1714	LogRel(("Serial#%d: no unit\n", pThis->pDevInsR3->iInstance));
1715	}
1716	else /* Don't call VMSetError here as we assume that the driver already set an appropriate error */
1717	LogRel(("Serial#%d: Failed to attach to serial driver. rc=%Rrc\n", pThis->pDevInsR3->iInstance, rc));
1718
1719	return rc;
1720	}
1721
1722
1723	DECLHIDDEN(void) uartR3Detach(PUARTCORE pThis)
1724	{
1725	/* Zero out important members. */
1726	pThis->pDrvBase = NULL;
1727	pThis->pDrvSerial = NULL;
1728	uartR3XferReset(pThis);
1729	}
1730
1731
1732	DECLHIDDEN(void) uartR3Destruct(PUARTCORE pThis)
1733	{
1734	PDMR3CritSectDelete(&pThis->CritSect);
1735	}
1736
1737
1738	DECLHIDDEN(int) uartR3Init(PUARTCORE pThis, PPDMDEVINS pDevInsR3, UARTTYPE enmType, unsigned iLUN, uint32_t fFlags,
1739	R3PTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReqR3, R0PTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReqR0,
1740	RCPTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReqRC)
1741	{
1742	int rc = VINF_SUCCESS;
1743
1744	/*
1745	* Initialize the instance data.
1746	* (Do this early or the destructor might choke on something!)
1747	*/
1748	pThis->pDevInsR3 = pDevInsR3;
1749	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevInsR3);
1750	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevInsR3);
1751	pThis->iLUN = iLUN;
1752	pThis->enmType = enmType;
1753	pThis->fFlags = fFlags;
1754	pThis->pfnUartIrqReqR3 = pfnUartIrqReqR3;
1755	pThis->pfnUartIrqReqR0 = pfnUartIrqReqR0;
1756	pThis->pfnUartIrqReqRC = pfnUartIrqReqRC;
1757
1758	/* IBase */
1759	pThis->IBase.pfnQueryInterface = uartR3QueryInterface;
1760
1761	/* ISerialPort */
1762	pThis->ISerialPort.pfnDataAvailRdrNotify = uartR3DataAvailRdrNotify;
1763	pThis->ISerialPort.pfnDataSentNotify = uartR3DataSentNotify;
1764	pThis->ISerialPort.pfnReadWr = uartR3ReadWr;
1765	pThis->ISerialPort.pfnNotifyStsLinesChanged = uartR3NotifyStsLinesChanged;
1766	pThis->ISerialPort.pfnNotifyBrk = uartR3NotifyBrk;
1767
1768	rc = PDMDevHlpCritSectInit(pDevInsR3, &pThis->CritSect, RT_SRC_POS, "Uart{%s#%d}#%d",
1769	pDevInsR3->pReg->szName, pDevInsR3->iInstance, iLUN);
1770	AssertRCReturn(rc, rc);
1771
1772	/*
1773	* Attach the char driver and get the interfaces.
1774	*/
1775	rc = PDMDevHlpDriverAttach(pDevInsR3, iLUN, &pThis->IBase, &pThis->pDrvBase, "UART");
1776	if (RT_SUCCESS(rc))
1777	{
1778	pThis->pDrvSerial = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMISERIALCONNECTOR);
1779	if (!pThis->pDrvSerial)
1780	{
1781	AssertLogRelMsgFailed(("Configuration error: instance %d has no serial interface!\n", iLUN));
1782	return VERR_PDM_MISSING_INTERFACE;
1783	}
1784	}
1785	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1786	{
1787	pThis->pDrvBase = NULL;
1788	pThis->pDrvSerial = NULL;
1789	LogRel(("Serial#%d: no unit\n", iLUN));
1790	}
1791	else
1792	{
1793	AssertLogRelMsgFailed(("Serial#%d: Failed to attach to char driver. rc=%Rrc\n", iLUN, rc));
1794	/* Don't call VMSetError here as we assume that the driver already set an appropriate error */
1795	return rc;
1796	}
1797
1798	/*
1799	* Create the receive FIFO character timeout indicator timer.
1800	*/
1801	rc = PDMDevHlpTMTimerCreate(pDevInsR3, TMCLOCK_VIRTUAL, uartR3RcvFifoTimeoutTimer, pThis,
1802	TMTIMER_FLAGS_NO_CRIT_SECT, "UART Rcv FIFO Timer",
1803	&pThis->pTimerRcvFifoTimeoutR3);
1804	AssertRCReturn(rc, rc);
1805
1806	rc = TMR3TimerSetCritSect(pThis->pTimerRcvFifoTimeoutR3, &pThis->CritSect);
1807	AssertRCReturn(rc, rc);
1808
1809	pThis->pTimerRcvFifoTimeoutR0 = TMTimerR0Ptr(pThis->pTimerRcvFifoTimeoutR3);
1810	pThis->pTimerRcvFifoTimeoutRC = TMTimerRCPtr(pThis->pTimerRcvFifoTimeoutR3);
1811
1812	uartR3Reset(pThis);
1813	return VINF_SUCCESS;
1814	}
1815
1816	#endif /* IN_RING3 */
1817
1818	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Serial/UartCore.cpp@ 74911

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