UartCore.cpp@ 77611

Last change on this file since 77611 was 77411, checked in by vboxsync, 6 years ago
Devices/UART: Properly handle loopback mode (feeding the sent data immediately back to the receive side)
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1	/* $Id: UartCore.cpp 77411 2019-02-21 15:57:31Z vboxsync $ */
2	/** @file
3	* UartCore - UART (16550A up to 16950) emulation.
4	*
5	* The documentation for this device was taken from the PC16550D spec from TI.
6	*/
7
8	/*
9	* Copyright (C) 2018-2019 Oracle Corporation
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*/
19
20
21	/*********************************************************************************************************************************
22	* Header Files *
23	*********************************************************************************************************************************/
24	#define LOG_GROUP LOG_GROUP_DEV_SERIAL
25	#include <VBox/vmm/tm.h>
26	#include <iprt/log.h>
27	#include <iprt/uuid.h>
28	#include <iprt/assert.h>
29
30	#include "VBoxDD.h"
31	#include "UartCore.h"
32
33
34	/*********************************************************************************************************************************
35	* Defined Constants And Macros *
36	*********************************************************************************************************************************/
37
38	/** The RBR/DLL register index (from the base of the port range). */
39	#define UART_REG_RBR_DLL_INDEX 0
40
41	/** The THR/DLL register index (from the base of the port range). */
42	#define UART_REG_THR_DLL_INDEX 0
43
44	/** The IER/DLM register index (from the base of the port range). */
45	#define UART_REG_IER_DLM_INDEX 1
46	/** Enable received data available interrupt */
47	# define UART_REG_IER_ERBFI RT_BIT(0)
48	/** Enable transmitter holding register empty interrupt */
49	# define UART_REG_IER_ETBEI RT_BIT(1)
50	/** Enable receiver line status interrupt */
51	# define UART_REG_IER_ELSI RT_BIT(2)
52	/** Enable modem status interrupt. */
53	# define UART_REG_IER_EDSSI RT_BIT(3)
54	/** Sleep mode enable. */
55	# define UART_REG_IER_SLEEP_MODE_EN RT_BIT(4)
56	/** Low power mode enable. */
57	# define UART_REG_IER_LP_MODE_EN RT_BIT(5)
58	/** Mask of writeable bits. */
59	# define UART_REG_IER_MASK_WR 0x0f
60	/** Mask of writeable bits for 16750+. */
61	# define UART_REG_IER_MASK_WR_16750 0x3f
62
63	/** The IIR register index (from the base of the port range). */
64	#define UART_REG_IIR_INDEX 2
65	/** Interrupt Pending - high means no interrupt pending. */
66	# define UART_REG_IIR_IP_NO_INT RT_BIT(0)
67	/** Interrupt identification mask. */
68	# define UART_REG_IIR_ID_MASK 0x0e
69	/** Sets the interrupt identification to the given value. */
70	# define UART_REG_IIR_ID_SET(a_Val) (((a_Val) << 1) & UART_REG_IIR_ID_MASK)
71	/** Gets the interrupt identification from the given IIR register value. */
72	# define UART_REG_IIR_ID_GET(a_Val) (((a_Val) & UART_REG_IIR_ID_MASK) >> 1)
73	/** Receiver Line Status interrupt. */
74	# define UART_REG_IIR_ID_RCL 0x3
75	/** Received Data Available interrupt. */
76	# define UART_REG_IIR_ID_RDA 0x2
77	/** Character Timeou Indicator interrupt. */
78	# define UART_REG_IIR_ID_CTI 0x6
79	/** Transmitter Holding Register Empty interrupt. */
80	# define UART_REG_IIR_ID_THRE 0x1
81	/** Modem Status interrupt. */
82	# define UART_REG_IIR_ID_MS 0x0
83	/** 64 byte FIFOs enabled (15750+ only). */
84	# define UART_REG_IIR_64BYTE_FIFOS_EN RT_BIT(5)
85	/** FIFOs enabled. */
86	# define UART_REG_IIR_FIFOS_EN 0xc0
87	/** Bits relevant for checking whether the interrupt status has changed. */
88	# define UART_REG_IIR_CHANGED_MASK 0x0f
89
90	/** The FCR register index (from the base of the port range). */
91	#define UART_REG_FCR_INDEX 2
92	/** Enable the TX/RX FIFOs. */
93	# define UART_REG_FCR_FIFO_EN RT_BIT(0)
94	/** Reset the receive FIFO. */
95	# define UART_REG_FCR_RCV_FIFO_RST RT_BIT(1)
96	/** Reset the transmit FIFO. */
97	# define UART_REG_FCR_XMIT_FIFO_RST RT_BIT(2)
98	/** DMA Mode Select. */
99	# define UART_REG_FCR_DMA_MODE_SEL RT_BIT(3)
100	/** 64 Byte FIFO enable (15750+ only). */
101	# define UART_REG_FCR_64BYTE_FIFO_EN RT_BIT(5)
102	/** Receiver level interrupt trigger. */
103	# define UART_REG_FCR_RCV_LVL_IRQ_MASK 0xc0
104	/** Returns the receive level trigger value from the given FCR register. */
105	# define UART_REG_FCR_RCV_LVL_IRQ_GET(a_Fcr) (((a_Fcr) & UART_REG_FCR_RCV_LVL_IRQ_MASK) >> 6)
106	/** RCV Interrupt trigger level - 1 byte. */
107	# define UART_REG_FCR_RCV_LVL_IRQ_1 0x0
108	/** RCV Interrupt trigger level - 4 bytes. */
109	# define UART_REG_FCR_RCV_LVL_IRQ_4 0x1
110	/** RCV Interrupt trigger level - 8 bytes. */
111	# define UART_REG_FCR_RCV_LVL_IRQ_8 0x2
112	/** RCV Interrupt trigger level - 14 bytes. */
113	# define UART_REG_FCR_RCV_LVL_IRQ_14 0x3
114	/** Mask of writeable bits. */
115	# define UART_REG_FCR_MASK_WR 0xcf
116	/** Mask of sticky bits. */
117	# define UART_REG_FCR_MASK_STICKY 0xe9
118
119	/** The LCR register index (from the base of the port range). */
120	#define UART_REG_LCR_INDEX 3
121	/** Word Length Select Mask. */
122	# define UART_REG_LCR_WLS_MASK 0x3
123	/** Returns the WLS value form the given LCR register value. */
124	# define UART_REG_LCR_WLS_GET(a_Lcr) ((a_Lcr) & UART_REG_LCR_WLS_MASK)
125	/** Number of stop bits. */
126	# define UART_REG_LCR_STB RT_BIT(2)
127	/** Parity Enable. */
128	# define UART_REG_LCR_PEN RT_BIT(3)
129	/** Even Parity. */
130	# define UART_REG_LCR_EPS RT_BIT(4)
131	/** Stick parity. */
132	# define UART_REG_LCR_PAR_STICK RT_BIT(5)
133	/** Set Break. */
134	# define UART_REG_LCR_BRK_SET RT_BIT(6)
135	/** Divisor Latch Access Bit. */
136	# define UART_REG_LCR_DLAB RT_BIT(7)
137
138	/** The MCR register index (from the base of the port range). */
139	#define UART_REG_MCR_INDEX 4
140	/** Data Terminal Ready. */
141	# define UART_REG_MCR_DTR RT_BIT(0)
142	/** Request To Send. */
143	# define UART_REG_MCR_RTS RT_BIT(1)
144	/** Out1. */
145	# define UART_REG_MCR_OUT1 RT_BIT(2)
146	/** Out2. */
147	# define UART_REG_MCR_OUT2 RT_BIT(3)
148	/** Loopback connection. */
149	# define UART_REG_MCR_LOOP RT_BIT(4)
150	/** Flow Control Enable (15750+ only). */
151	# define UART_REG_MCR_AFE RT_BIT(5)
152	/** Mask of writeable bits (15450 and 15550A). */
153	# define UART_REG_MCR_MASK_WR 0x1f
154	/** Mask of writeable bits (15750+). */
155	# define UART_REG_MCR_MASK_WR_15750 0x3f
156
157	/** The LSR register index (from the base of the port range). */
158	#define UART_REG_LSR_INDEX 5
159	/** Data Ready. */
160	# define UART_REG_LSR_DR RT_BIT(0)
161	/** Overrun Error. */
162	# define UART_REG_LSR_OE RT_BIT(1)
163	/** Parity Error. */
164	# define UART_REG_LSR_PE RT_BIT(2)
165	/** Framing Error. */
166	# define UART_REG_LSR_FE RT_BIT(3)
167	/** Break Interrupt. */
168	# define UART_REG_LSR_BI RT_BIT(4)
169	/** Transmitter Holding Register. */
170	# define UART_REG_LSR_THRE RT_BIT(5)
171	/** Transmitter Empty. */
172	# define UART_REG_LSR_TEMT RT_BIT(6)
173	/** Error in receiver FIFO. */
174	# define UART_REG_LSR_RCV_FIFO_ERR RT_BIT(7)
175	/** The bits to check in this register when checking for the RCL interrupt. */
176	# define UART_REG_LSR_BITS_IIR_RCL 0x1e
177
178	/** The MSR register index (from the base of the port range). */
179	#define UART_REG_MSR_INDEX 6
180	/** Delta Clear to Send. */
181	# define UART_REG_MSR_DCTS RT_BIT(0)
182	/** Delta Data Set Ready. */
183	# define UART_REG_MSR_DDSR RT_BIT(1)
184	/** Trailing Edge Ring Indicator. */
185	# define UART_REG_MSR_TERI RT_BIT(2)
186	/** Delta Data Carrier Detect. */
187	# define UART_REG_MSR_DDCD RT_BIT(3)
188	/** Clear to Send. */
189	# define UART_REG_MSR_CTS RT_BIT(4)
190	/** Data Set Ready. */
191	# define UART_REG_MSR_DSR RT_BIT(5)
192	/** Ring Indicator. */
193	# define UART_REG_MSR_RI RT_BIT(6)
194	/** Data Carrier Detect. */
195	# define UART_REG_MSR_DCD RT_BIT(7)
196	/** The bits to check in this register when checking for the MS interrupt. */
197	# define UART_REG_MSR_BITS_IIR_MS 0x0f
198
199	/** The SCR register index (from the base of the port range). */
200	#define UART_REG_SCR_INDEX 7
201
202	/** Set the specified bits in the given register. */
203	#define UART_REG_SET(a_Reg, a_Set) ((a_Reg) \|= (a_Set))
204	/** Clear the specified bits in the given register. */
205	#define UART_REG_CLR(a_Reg, a_Clr) ((a_Reg) &= ~(a_Clr))
206
207
208	/*********************************************************************************************************************************
209	* Structures and Typedefs *
210	*********************************************************************************************************************************/
211
212	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
213
214
215	/*********************************************************************************************************************************
216	* Global Variables *
217	*********************************************************************************************************************************/
218
219	#ifdef IN_RING3
220	/**
221	* FIFO ITL levels.
222	*/
223	static struct
224	{
225	/** ITL level for a 16byte FIFO. */
226	uint8_t cbItl16;
227	/** ITL level for a 64byte FIFO. */
228	uint8_t cbItl64;
229	} s_aFifoItl[] =
230	{
231	/* cbItl16 cbItl64 */
232	{ 1, 1 },
233	{ 4, 16 },
234	{ 8, 32 },
235	{ 14, 56 }
236	};
237
238
239	/**
240	* String versions of the parity enum.
241	*/
242	static const char *s_aszParity[] =
243	{
244	"INVALID",
245	"NONE",
246	"EVEN",
247	"ODD",
248	"MARK",
249	"SPACE",
250	"INVALID"
251	};
252
253
254	/**
255	* String versions of the stop bits enum.
256	*/
257	static const char *s_aszStopBits[] =
258	{
259	"INVALID",
260	"1",
261	"1.5",
262	"2",
263	"INVALID"
264	};
265	#endif
266
267
268	/*********************************************************************************************************************************
269	* Internal Functions *
270	*********************************************************************************************************************************/
271
272
273	/**
274	* Updates the IRQ state based on the current device state.
275	*
276	* @returns nothing.
277	* @param pThis The UART core instance.
278	*/
279	static void uartIrqUpdate(PUARTCORE pThis)
280	{
281	LogFlowFunc(("pThis=%#p\n", pThis));
282
283	/*
284	* The interrupt uses a priority scheme, only the interrupt with the
285	* highest priority is indicated in the interrupt identification register.
286	*
287	* The priorities are as follows (high to low):
288	* * Receiver line status
289	* * Received data available
290	* * Character timeout indication (only in FIFO mode).
291	* * Transmitter holding register empty
292	* * Modem status change.
293	*/
294	uint8_t uRegIirNew = UART_REG_IIR_IP_NO_INT;
295	if ( (pThis->uRegLsr & UART_REG_LSR_BITS_IIR_RCL)
296	&& (pThis->uRegIer & UART_REG_IER_ELSI))
297	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_RCL);
298	else if ( (pThis->uRegIer & UART_REG_IER_ERBFI)
299	&& pThis->fIrqCtiPending)
300	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_CTI);
301	else if ( (pThis->uRegLsr & UART_REG_LSR_DR)
302	&& (pThis->uRegIer & UART_REG_IER_ERBFI)
303	&& ( !(pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
304	\|\| pThis->FifoRecv.cbUsed >= pThis->FifoRecv.cbItl))
305	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_RDA);
306	else if ( (pThis->uRegIer & UART_REG_IER_ETBEI)
307	&& pThis->fThreEmptyPending)
308	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_THRE);
309	else if ( (pThis->uRegMsr & UART_REG_MSR_BITS_IIR_MS)
310	&& (pThis->uRegIer & UART_REG_IER_EDSSI))
311	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_MS);
312
313	LogFlowFunc((" uRegIirNew=%#x uRegIir=%#x\n", uRegIirNew, pThis->uRegIir));
314
315	/* Change interrupt only if the interrupt status really changed from the previous value. */
316	if (uRegIirNew != (pThis->uRegIir & UART_REG_IIR_CHANGED_MASK))
317	{
318	LogFlow((" Interrupt source changed from %#x -> %#x (IRQ %d -> %d)\n",
319	pThis->uRegIir, uRegIirNew,
320	pThis->uRegIir == UART_REG_IIR_IP_NO_INT ? 0 : 1,
321	uRegIirNew == UART_REG_IIR_IP_NO_INT ? 0 : 1));
322	if (uRegIirNew == UART_REG_IIR_IP_NO_INT)
323	pThis->CTX_SUFF(pfnUartIrqReq)(pThis->CTX_SUFF(pDevIns), pThis, pThis->iLUN, 0);
324	else
325	pThis->CTX_SUFF(pfnUartIrqReq)(pThis->CTX_SUFF(pDevIns), pThis, pThis->iLUN, 1);
326	}
327	else
328	LogFlow((" No change in interrupt source\n"));
329
330	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
331	uRegIirNew \|= UART_REG_IIR_FIFOS_EN;
332	if (pThis->uRegFcr & UART_REG_FCR_64BYTE_FIFO_EN)
333	uRegIirNew \|= UART_REG_IIR_64BYTE_FIFOS_EN;
334
335	pThis->uRegIir = uRegIirNew;
336	}
337
338
339	/**
340	* Returns the amount of bytes stored in the given FIFO.
341	*
342	* @returns Amount of bytes stored in the FIFO.
343	* @param pFifo The FIFO.
344	*/
345	DECLINLINE(size_t) uartFifoUsedGet(PUARTFIFO pFifo)
346	{
347	return pFifo->cbUsed;
348	}
349
350
351	/**
352	* Puts a new character into the given FIFO.
353	*
354	* @returns Flag whether the FIFO overflowed.
355	* @param pFifo The FIFO to put the data into.
356	* @param fOvrWr Flag whether to overwrite data if the FIFO is full.
357	* @param bData The data to add.
358	*/
359	DECLINLINE(bool) uartFifoPut(PUARTFIFO pFifo, bool fOvrWr, uint8_t bData)
360	{
361	if (fOvrWr \|\| pFifo->cbUsed < pFifo->cbMax)
362	{
363	pFifo->abBuf[pFifo->offWrite] = bData;
364	pFifo->offWrite = (pFifo->offWrite + 1) % pFifo->cbMax;
365	}
366
367	bool fOverFlow = false;
368	if (pFifo->cbUsed < pFifo->cbMax)
369	pFifo->cbUsed++;
370	else
371	{
372	fOverFlow = true;
373	if (fOvrWr) /* Advance the read position to account for the lost character. */
374	pFifo->offRead = (pFifo->offRead + 1) % pFifo->cbMax;
375	}
376
377	return fOverFlow;
378	}
379
380
381	/**
382	* Returns the next character in the FIFO.
383	*
384	* @return Next byte in the FIFO.
385	* @param pFifo The FIFO to get data from.
386	*/
387	DECLINLINE(uint8_t) uartFifoGet(PUARTFIFO pFifo)
388	{
389	uint8_t bRet = 0;
390
391	if (pFifo->cbUsed)
392	{
393	bRet = pFifo->abBuf[pFifo->offRead];
394	pFifo->offRead = (pFifo->offRead + 1) % pFifo->cbMax;
395	pFifo->cbUsed--;
396	}
397
398	return bRet;
399	}
400
401
402	#ifdef IN_RING3
403	/**
404	* Clears the given FIFO.
405	*
406	* @returns nothing.
407	* @param pFifo The FIFO to clear.
408	*/
409	DECLINLINE(void) uartFifoClear(PUARTFIFO pFifo)
410	{
411	memset(&pFifo->abBuf[0], 0, sizeof(pFifo->abBuf));
412	pFifo->cbUsed = 0;
413	pFifo->offWrite = 0;
414	pFifo->offRead = 0;
415	}
416
417
418	/**
419	* Returns the amount of free bytes in the given FIFO.
420	*
421	* @returns The amount of bytes free in the given FIFO.
422	* @param pFifo The FIFO.
423	*/
424	DECLINLINE(size_t) uartFifoFreeGet(PUARTFIFO pFifo)
425	{
426	return pFifo->cbMax - pFifo->cbUsed;
427	}
428
429
430	/**
431	* Tries to copy the requested amount of data from the given FIFO into the provided buffer.
432	*
433	* @returns Amount of bytes actually copied.
434	* @param pFifo The FIFO to copy data from.
435	* @param pvDst Where to copy the data to.
436	* @param cbCopy How much to copy.
437	*/
438	DECLINLINE(size_t) uartFifoCopyTo(PUARTFIFO pFifo, void *pvDst, size_t cbCopy)
439	{
440	size_t cbCopied = 0;
441	uint8_t pbDst = (uint8_t )pvDst;
442
443	cbCopy = RT_MIN(cbCopy, pFifo->cbUsed);
444	while (cbCopy)
445	{
446	uint8_t cbThisCopy = (uint8_t)RT_MIN(cbCopy, (uint8_t)(pFifo->cbMax - pFifo->offRead));
447	memcpy(pbDst, &pFifo->abBuf[pFifo->offRead], cbThisCopy);
448
449	pFifo->offRead = (pFifo->offRead + cbThisCopy) % pFifo->cbMax;
450	pFifo->cbUsed -= cbThisCopy;
451	pbDst += cbThisCopy;
452	cbCopied += cbThisCopy;
453	cbCopy -= cbThisCopy;
454	}
455
456	return cbCopied;
457	}
458
459
460	#if 0 /* unused */
461	/**
462	* Tries to copy the requested amount of data from the provided buffer into the given FIFO.
463	*
464	* @returns Amount of bytes actually copied.
465	* @param pFifo The FIFO to copy data to.
466	* @param pvSrc Where to copy the data from.
467	* @param cbCopy How much to copy.
468	*/
469	DECLINLINE(size_t) uartFifoCopyFrom(PUARTFIFO pFifo, void *pvSrc, size_t cbCopy)
470	{
471	size_t cbCopied = 0;
472	uint8_t pbSrc = (uint8_t )pvSrc;
473
474	cbCopy = RT_MIN(cbCopy, uartFifoFreeGet(pFifo));
475	while (cbCopy)
476	{
477	uint8_t cbThisCopy = (uint8_t)RT_MIN(cbCopy, (uint8_t)(pFifo->cbMax - pFifo->offWrite));
478	memcpy(&pFifo->abBuf[pFifo->offWrite], pbSrc, cbThisCopy);
479
480	pFifo->offWrite = (pFifo->offWrite + cbThisCopy) % pFifo->cbMax;
481	pFifo->cbUsed += cbThisCopy;
482	pbSrc += cbThisCopy;
483	cbCopied += cbThisCopy;
484	cbCopy -= cbThisCopy;
485	}
486
487	return cbCopied;
488	}
489	#endif
490
491
492	/**
493	* Updates the delta bits for the given MSR register value which has the status line
494	* bits set.
495	*
496	* @returns nothing.
497	* @param pThis The serial port instance.
498	* @param uMsrSts MSR value with the appropriate status bits set.
499	*/
500	static void uartR3MsrUpdate(PUARTCORE pThis, uint8_t uMsrSts)
501	{
502	/* Compare current and new states and set remaining bits accordingly. */
503	if ((uMsrSts & UART_REG_MSR_CTS) != (pThis->uRegMsr & UART_REG_MSR_CTS))
504	uMsrSts \|= UART_REG_MSR_DCTS;
505	if ((uMsrSts & UART_REG_MSR_DSR) != (pThis->uRegMsr & UART_REG_MSR_DSR))
506	uMsrSts \|= UART_REG_MSR_DDSR;
507	if ((uMsrSts & UART_REG_MSR_RI) != 0 && (pThis->uRegMsr & UART_REG_MSR_RI) == 0)
508	uMsrSts \|= UART_REG_MSR_TERI;
509	if ((uMsrSts & UART_REG_MSR_DCD) != (pThis->uRegMsr & UART_REG_MSR_DCD))
510	uMsrSts \|= UART_REG_MSR_DDCD;
511
512	pThis->uRegMsr = uMsrSts;
513
514	uartIrqUpdate(pThis);
515	}
516
517
518	/**
519	* Updates the serial port parameters of the attached driver with the current configuration.
520	*
521	* @returns nothing.
522	* @param pThis The serial port instance.
523	*/
524	static void uartR3ParamsUpdate(PUARTCORE pThis)
525	{
526	if ( pThis->uRegDivisor != 0
527	&& pThis->pDrvSerial)
528	{
529	uint32_t uBps = 115200 / pThis->uRegDivisor; /* This is for PC compatible serial port with a 1.8432 MHz crystal. */
530	unsigned cDataBits = UART_REG_LCR_WLS_GET(pThis->uRegLcr) + 5;
531	uint32_t cFrameBits = cDataBits;
532	PDMSERIALSTOPBITS enmStopBits = PDMSERIALSTOPBITS_ONE;
533	PDMSERIALPARITY enmParity = PDMSERIALPARITY_NONE;
534
535	if (pThis->uRegLcr & UART_REG_LCR_STB)
536	{
537	enmStopBits = cDataBits == 5 ? PDMSERIALSTOPBITS_ONEPOINTFIVE : PDMSERIALSTOPBITS_TWO;
538	cFrameBits += 2;
539	}
540	else
541	cFrameBits++;
542
543	if (pThis->uRegLcr & UART_REG_LCR_PEN)
544	{
545	/* Select the correct parity mode based on the even and stick parity bits. */
546	switch (pThis->uRegLcr & (UART_REG_LCR_EPS \| UART_REG_LCR_PAR_STICK))
547	{
548	case 0:
549	enmParity = PDMSERIALPARITY_ODD;
550	break;
551	case UART_REG_LCR_EPS:
552	enmParity = PDMSERIALPARITY_EVEN;
553	break;
554	case UART_REG_LCR_EPS \| UART_REG_LCR_PAR_STICK:
555	enmParity = PDMSERIALPARITY_SPACE;
556	break;
557	case UART_REG_LCR_PAR_STICK:
558	enmParity = PDMSERIALPARITY_MARK;
559	break;
560	default:
561	/* We should never get here as all cases where caught earlier. */
562	AssertMsgFailed(("This shouldn't happen at all: %#x\n",
563	pThis->uRegLcr & (UART_REG_LCR_EPS \| UART_REG_LCR_PAR_STICK)));
564	}
565
566	cFrameBits++;
567	}
568
569	uint64_t uTimerFreq = TMTimerGetFreq(pThis->CTX_SUFF(pTimerRcvFifoTimeout));
570	pThis->cSymbolXferTicks = (uTimerFreq / uBps) * cFrameBits;
571
572	LogFlowFunc(("Changing parameters to: %u,%s,%u,%s\n",
573	uBps, s_aszParity[enmParity], cDataBits, s_aszStopBits[enmStopBits]));
574
575	int rc = pThis->pDrvSerial->pfnChgParams(pThis->pDrvSerial, uBps, enmParity, cDataBits, enmStopBits);
576	if (RT_FAILURE(rc))
577	LogRelMax(10, ("Serial#%d: Failed to change parameters to %u,%s,%u,%s -> %Rrc\n",
578	pThis->pDevInsR3->iInstance, uBps, s_aszParity[enmParity], cDataBits, s_aszStopBits[enmStopBits], rc));
579
580	/* Changed parameters will flush all receive queues, so there won't be any data to read even if indicated. */
581	pThis->pDrvSerial->pfnQueuesFlush(pThis->pDrvSerial, true /fQueueRecv/, false /fQueueXmit/);
582	ASMAtomicWriteU32(&pThis->cbAvailRdr, 0);
583	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
584	}
585	}
586
587
588	/**
589	* Updates the internal device state with the given PDM status line states.
590	*
591	* @returns nothing.
592	* @param pThis The serial port instance.
593	* @param fStsLines The PDM status line states.
594	*/
595	static void uartR3StsLinesUpdate(PUARTCORE pThis, uint32_t fStsLines)
596	{
597	uint8_t uRegMsrNew = 0; /* The new MSR value. */
598
599	if (fStsLines & PDMISERIALPORT_STS_LINE_DCD)
600	uRegMsrNew \|= UART_REG_MSR_DCD;
601	if (fStsLines & PDMISERIALPORT_STS_LINE_RI)
602	uRegMsrNew \|= UART_REG_MSR_RI;
603	if (fStsLines & PDMISERIALPORT_STS_LINE_DSR)
604	uRegMsrNew \|= UART_REG_MSR_DSR;
605	if (fStsLines & PDMISERIALPORT_STS_LINE_CTS)
606	uRegMsrNew \|= UART_REG_MSR_CTS;
607
608	uartR3MsrUpdate(pThis, uRegMsrNew);
609	}
610
611
612	/**
613	* Fills up the receive FIFO with as much data as possible.
614	*
615	* @returns nothing.
616	* @param pThis The serial port instance.
617	*/
618	static void uartR3RecvFifoFill(PUARTCORE pThis)
619	{
620	LogFlowFunc(("pThis=%#p\n", pThis));
621
622	PUARTFIFO pFifo = &pThis->FifoRecv;
623	size_t cbFill = RT_MIN(uartFifoFreeGet(pFifo),
624	ASMAtomicReadU32(&pThis->cbAvailRdr));
625	size_t cbFilled = 0;
626
627	while (cbFilled < cbFill)
628	{
629	size_t cbThisRead = cbFill - cbFilled;
630
631	if (pFifo->offRead <= pFifo->offWrite)
632	cbThisRead = RT_MIN(cbThisRead, (uint8_t)(pFifo->cbMax - pFifo->offWrite));
633	else
634	cbThisRead = RT_MIN(cbThisRead, (uint8_t)(pFifo->offRead - pFifo->offWrite));
635
636	size_t cbRead = 0;
637	int rc = pThis->pDrvSerial->pfnReadRdr(pThis->pDrvSerial, &pFifo->abBuf[pFifo->offWrite], cbThisRead, &cbRead);
638	AssertRC(rc); Assert(cbRead <= UINT8_MAX); RT_NOREF(rc);
639
640	pFifo->offWrite = (pFifo->offWrite + (uint8_t)cbRead) % pFifo->cbMax;
641	pFifo->cbUsed += (uint8_t)cbRead;
642	cbFilled += cbRead;
643
644	if (cbRead < cbThisRead)
645	break;
646	}
647
648	if (cbFilled)
649	{
650	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
651	if (pFifo->cbUsed < pFifo->cbItl)
652	{
653	pThis->fIrqCtiPending = false;
654	TMTimerSetRelative(pThis->CTX_SUFF(pTimerRcvFifoTimeout), pThis->cSymbolXferTicks * 4, NULL);
655	}
656	uartIrqUpdate(pThis);
657	}
658
659	Assert(cbFilled <= (size_t)pThis->cbAvailRdr);
660	ASMAtomicSubU32(&pThis->cbAvailRdr, (uint32_t)cbFilled);
661	}
662
663
664	/**
665	* Fetches a single byte and writes it to RBR.
666	*
667	* @returns nothing.
668	* @param pThis The serial port instance.
669	*/
670	static void uartR3ByteFetch(PUARTCORE pThis)
671	{
672	if (ASMAtomicReadU32(&pThis->cbAvailRdr))
673	{
674	AssertPtr(pThis->pDrvSerial);
675	size_t cbRead = 0;
676	int rc2 = pThis->pDrvSerial->pfnReadRdr(pThis->pDrvSerial, &pThis->uRegRbr, 1, &cbRead);
677	AssertMsg(RT_SUCCESS(rc2) && cbRead == 1, ("This shouldn't fail and always return one byte!\n")); RT_NOREF(rc2);
678	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
679	uartIrqUpdate(pThis);
680	}
681	}
682
683
684	/**
685	* Fetches a ready data based on the FIFO setting.
686	*
687	* @returns nothing.
688	* @param pThis The serial port instance.
689	*/
690	static void uartR3DataFetch(PUARTCORE pThis)
691	{
692	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
693	uartR3RecvFifoFill(pThis);
694	else
695	uartR3ByteFetch(pThis);
696	}
697
698
699	/**
700	* Reset the transmit/receive related bits to the standard values
701	* (after a detach/attach/reset event).
702	*
703	* @returns nothing.
704	* @param pThis The serial port instance.
705	*/
706	static void uartR3XferReset(PUARTCORE pThis)
707	{
708	TMTimerStop(pThis->CTX_SUFF(pTimerRcvFifoTimeout));
709	TMTimerStop(pThis->CTX_SUFF(pTimerTxUnconnected));
710	pThis->uRegLsr = UART_REG_LSR_THRE \| UART_REG_LSR_TEMT;
711	pThis->fThreEmptyPending = false;
712
713	uartFifoClear(&pThis->FifoXmit);
714	uartFifoClear(&pThis->FifoRecv);
715	uartR3ParamsUpdate(pThis);
716	uartIrqUpdate(pThis);
717
718	if (pThis->pDrvSerial)
719	{
720	/* Set the modem lines to reflect the current state. */
721	int rc = pThis->pDrvSerial->pfnChgModemLines(pThis->pDrvSerial, false /fRts/, false /fDtr/);
722	if (RT_FAILURE(rc))
723	LogRel(("Serial#%d: Failed to set modem lines with %Rrc during reset\n",
724	pThis->pDevInsR3->iInstance, rc));
725
726	uint32_t fStsLines = 0;
727	rc = pThis->pDrvSerial->pfnQueryStsLines(pThis->pDrvSerial, &fStsLines);
728	if (RT_SUCCESS(rc))
729	uartR3StsLinesUpdate(pThis, fStsLines);
730	else
731	LogRel(("Serial#%d: Failed to query status line status with %Rrc during reset\n",
732	pThis->pDevInsR3->iInstance, rc));
733	}
734
735	}
736
737
738	/**
739	* Tries to copy the specified amount of data from the active TX queue (register or FIFO).
740	*
741	* @returns nothing.
742	* @param pThis The serial port instance.
743	* @param pvBuf Where to store the data.
744	* @param cbRead How much to read from the TX queue.
745	* @param pcbRead Where to store the amount of data read.
746	*/
747	static void uartR3TxQueueCopyFrom(PUARTCORE pThis, void pvBuf, size_t cbRead, size_t pcbRead)
748	{
749	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
750	{
751	*pcbRead = uartFifoCopyTo(&pThis->FifoXmit, pvBuf, cbRead);
752	if (!pThis->FifoXmit.cbUsed)
753	{
754	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_THRE);
755	pThis->fThreEmptyPending = true;
756	}
757	if (*pcbRead)
758	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_TEMT);
759	uartIrqUpdate(pThis);
760	}
761	else if (!(pThis->uRegLsr & UART_REG_LSR_THRE))
762	{
763	(uint8_t )pvBuf = pThis->uRegThr;
764	*pcbRead = 1;
765	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_THRE);
766	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_TEMT);
767	pThis->fThreEmptyPending = true;
768	uartIrqUpdate(pThis);
769	}
770	else
771	{
772	/*
773	* This can happen if there was data in the FIFO when the connection was closed,
774	* indicate this condition to the lower driver by returning 0 bytes.
775	*/
776	*pcbRead = 0;
777	}
778	}
779	#endif
780
781
782	/**
783	* Transmits the given byte.
784	*
785	* @returns VBox status code.
786	* @param pThis The serial port instance.
787	* @param bVal Byte to transmit.
788	*/
789	static int uartXmit(PUARTCORE pThis, uint8_t bVal)
790	{
791	int rc = VINF_SUCCESS;
792
793	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
794	{
795	#ifndef IN_RING3
796	if (!uartFifoUsedGet(&pThis->FifoXmit))
797	rc = VINF_IOM_R3_IOPORT_WRITE;
798	else
799	{
800	uartFifoPut(&pThis->FifoXmit, true /fOvrWr/, bVal);
801	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE \| UART_REG_LSR_TEMT);
802	}
803	#else
804	uartFifoPut(&pThis->FifoXmit, true /fOvrWr/, bVal);
805	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE \| UART_REG_LSR_TEMT);
806	pThis->fThreEmptyPending = false;
807	uartIrqUpdate(pThis);
808	if (uartFifoUsedGet(&pThis->FifoXmit) == 1)
809	{
810	if ( pThis->pDrvSerial
811	&& !(pThis->uRegMcr & UART_REG_MCR_LOOP))
812	{
813	int rc2 = pThis->pDrvSerial->pfnDataAvailWrNotify(pThis->pDrvSerial);
814	if (RT_FAILURE(rc2))
815	LogRelMax(10, ("Serial#%d: Failed to send data with %Rrc\n", pThis->pDevInsR3->iInstance, rc2));
816	}
817	else
818	TMTimerSetRelative(pThis->CTX_SUFF(pTimerTxUnconnected), pThis->cSymbolXferTicks, NULL);
819	}
820	#endif
821	}
822	else
823	{
824	/* Notify the lower driver about available data only if the register was empty before. */
825	if (pThis->uRegLsr & UART_REG_LSR_THRE)
826	{
827	#ifndef IN_RING3
828	rc = VINF_IOM_R3_IOPORT_WRITE;
829	#else
830	pThis->uRegThr = bVal;
831	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE \| UART_REG_LSR_TEMT);
832	pThis->fThreEmptyPending = false;
833	uartIrqUpdate(pThis);
834	if ( pThis->pDrvSerial
835	&& !(pThis->uRegMcr & UART_REG_MCR_LOOP))
836	{
837	int rc2 = pThis->pDrvSerial->pfnDataAvailWrNotify(pThis->pDrvSerial);
838	if (RT_FAILURE(rc2))
839	LogRelMax(10, ("Serial#%d: Failed to send data with %Rrc\n", pThis->pDevInsR3->iInstance, rc2));
840	}
841	else
842	TMTimerSetRelative(pThis->CTX_SUFF(pTimerTxUnconnected), pThis->cSymbolXferTicks, NULL);
843	#endif
844	}
845	else
846	pThis->uRegThr = bVal;
847	}
848
849	return rc;
850	}
851
852
853	/**
854	* Write handler for the THR/DLL register (depending on the DLAB bit in LCR).
855	*
856	* @returns VBox status code.
857	* @param pThis The serial port instance.
858	* @param uVal The value to write.
859	*/
860	DECLINLINE(int) uartRegThrDllWrite(PUARTCORE pThis, uint8_t uVal)
861	{
862	int rc = VINF_SUCCESS;
863
864	/* A set DLAB causes a write to the lower 8bits of the divisor latch. */
865	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
866	{
867	if (uVal != (pThis->uRegDivisor & 0xff))
868	{
869	#ifndef IN_RING3
870	rc = VINF_IOM_R3_IOPORT_WRITE;
871	#else
872	pThis->uRegDivisor = (pThis->uRegDivisor & 0xff00) \| uVal;
873	uartR3ParamsUpdate(pThis);
874	#endif
875	}
876	}
877	else
878	rc = uartXmit(pThis, uVal);
879
880	return rc;
881	}
882
883
884	/**
885	* Write handler for the IER/DLM register (depending on the DLAB bit in LCR).
886	*
887	* @returns VBox status code.
888	* @param pThis The serial port instance.
889	* @param uVal The value to write.
890	*/
891	DECLINLINE(int) uartRegIerDlmWrite(PUARTCORE pThis, uint8_t uVal)
892	{
893	int rc = VINF_SUCCESS;
894
895	/* A set DLAB causes a write to the higher 8bits of the divisor latch. */
896	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
897	{
898	if (uVal != (pThis->uRegDivisor & 0xff00) >> 8)
899	{
900	#ifndef IN_RING3
901	rc = VINF_IOM_R3_IOPORT_WRITE;
902	#else
903	pThis->uRegDivisor = (pThis->uRegDivisor & 0xff) \| (uVal << 8);
904	uartR3ParamsUpdate(pThis);
905	#endif
906	}
907	}
908	else
909	{
910	if (pThis->enmType < UARTTYPE_16750)
911	pThis->uRegIer = uVal & UART_REG_IER_MASK_WR;
912	else
913	pThis->uRegIer = uVal & UART_REG_IER_MASK_WR_16750;
914
915	if (pThis->uRegLsr & UART_REG_LSR_THRE)
916	pThis->fThreEmptyPending = true;
917
918	uartIrqUpdate(pThis);
919	}
920
921	return rc;
922	}
923
924
925	/**
926	* Write handler for the FCR register.
927	*
928	* @returns VBox status code.
929	* @param pThis The serial port instance.
930	* @param uVal The value to write.
931	*/
932	DECLINLINE(int) uartRegFcrWrite(PUARTCORE pThis, uint8_t uVal)
933	{
934	#ifndef IN_RING3
935	RT_NOREF(pThis, uVal);
936	return VINF_IOM_R3_IOPORT_WRITE;
937	#else
938	int rc = VINF_SUCCESS;
939	if ( pThis->enmType >= UARTTYPE_16550A
940	&& uVal != pThis->uRegFcr)
941	{
942	/* A change in the FIFO enable bit clears both FIFOs automatically. */
943	if ((uVal ^ pThis->uRegFcr) & UART_REG_FCR_FIFO_EN)
944	{
945	uartFifoClear(&pThis->FifoXmit);
946	uartFifoClear(&pThis->FifoRecv);
947
948	/*
949	* If the FIFO is about to be enabled and the DR bit is ready we have an unacknowledged
950	* byte in the RBR register which will be lost so we have to adjust the available bytes.
951	*/
952	if ( ASMAtomicReadU32(&pThis->cbAvailRdr) > 0
953	&& (uVal & UART_REG_FCR_FIFO_EN))
954	ASMAtomicDecU32(&pThis->cbAvailRdr);
955
956	/* Clear the DR bit too. */
957	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
958	}
959
960	if (rc == VINF_SUCCESS)
961	{
962	if (uVal & UART_REG_FCR_RCV_FIFO_RST)
963	{
964	TMTimerStop(pThis->CTX_SUFF(pTimerRcvFifoTimeout));
965	pThis->fIrqCtiPending = false;
966	uartFifoClear(&pThis->FifoRecv);
967	}
968	if (uVal & UART_REG_FCR_XMIT_FIFO_RST)
969	uartFifoClear(&pThis->FifoXmit);
970
971	/*
972	* The 64byte FIFO enable bit is only changeable for 16750
973	* and if the DLAB bit in LCR is set.
974	*/
975	if ( pThis->enmType < UARTTYPE_16750
976	\|\| !(pThis->uRegLcr & UART_REG_LCR_DLAB))
977	uVal &= ~UART_REG_FCR_64BYTE_FIFO_EN;
978	else /* Use previous value. */
979	uVal \|= pThis->uRegFcr & UART_REG_FCR_64BYTE_FIFO_EN;
980
981	if (uVal & UART_REG_FCR_64BYTE_FIFO_EN)
982	{
983	pThis->FifoRecv.cbMax = 64;
984	pThis->FifoXmit.cbMax = 64;
985	}
986	else
987	{
988	pThis->FifoRecv.cbMax = 16;
989	pThis->FifoXmit.cbMax = 16;
990	}
991
992	if (uVal & UART_REG_FCR_FIFO_EN)
993	{
994	uint8_t idxItl = UART_REG_FCR_RCV_LVL_IRQ_GET(uVal);
995	if (uVal & UART_REG_FCR_64BYTE_FIFO_EN)
996	pThis->FifoRecv.cbItl = s_aFifoItl[idxItl].cbItl64;
997	else
998	pThis->FifoRecv.cbItl = s_aFifoItl[idxItl].cbItl16;
999	}
1000
1001	/* The FIFO reset bits are self clearing. */
1002	pThis->uRegFcr = uVal & UART_REG_FCR_MASK_STICKY;
1003	uartIrqUpdate(pThis);
1004	}
1005
1006	/* Fill in the next data. */
1007	if (ASMAtomicReadU32(&pThis->cbAvailRdr))
1008	uartR3DataFetch(pThis);
1009	}
1010
1011	return rc;
1012	#endif
1013	}
1014
1015
1016	/**
1017	* Write handler for the LCR register.
1018	*
1019	* @returns VBox status code.
1020	* @param pThis The serial port instance.
1021	* @param uVal The value to write.
1022	*/
1023	DECLINLINE(int) uartRegLcrWrite(PUARTCORE pThis, uint8_t uVal)
1024	{
1025	int rc = VINF_SUCCESS;
1026
1027	/* Any change except the DLAB bit causes a switch to R3. */
1028	if ((pThis->uRegLcr & ~UART_REG_LCR_DLAB) != (uVal & ~UART_REG_LCR_DLAB))
1029	{
1030	#ifndef IN_RING3
1031	rc = VINF_IOM_R3_IOPORT_WRITE;
1032	#else
1033	/* Check whether the BREAK bit changed before updating the LCR value. */
1034	bool fBrkEn = RT_BOOL(uVal & UART_REG_LCR_BRK_SET);
1035	bool fBrkChg = fBrkEn != RT_BOOL(pThis->uRegLcr & UART_REG_LCR_BRK_SET);
1036	pThis->uRegLcr = uVal;
1037	uartR3ParamsUpdate(pThis);
1038
1039	if ( fBrkChg
1040	&& pThis->pDrvSerial)
1041	pThis->pDrvSerial->pfnChgBrk(pThis->pDrvSerial, fBrkEn);
1042	#endif
1043	}
1044	else
1045	pThis->uRegLcr = uVal;
1046
1047	return rc;
1048	}
1049
1050
1051	/**
1052	* Write handler for the MCR register.
1053	*
1054	* @returns VBox status code.
1055	* @param pThis The serial port instance.
1056	* @param uVal The value to write.
1057	*/
1058	DECLINLINE(int) uartRegMcrWrite(PUARTCORE pThis, uint8_t uVal)
1059	{
1060	int rc = VINF_SUCCESS;
1061
1062	if (pThis->enmType < UARTTYPE_16750)
1063	uVal &= UART_REG_MCR_MASK_WR;
1064	else
1065	uVal &= UART_REG_MCR_MASK_WR_15750;
1066	if (pThis->uRegMcr != uVal)
1067	{
1068	#ifndef IN_RING3
1069	rc = VINF_IOM_R3_IOPORT_WRITE;
1070	#else
1071	/*
1072	* When loopback mode is activated the RTS, DTR, OUT1 and OUT2 lines are
1073	* disconnected and looped back to MSR.
1074	*/
1075	if ( (uVal & UART_REG_MCR_LOOP)
1076	&& !(pThis->uRegMcr & UART_REG_MCR_LOOP)
1077	&& pThis->pDrvSerial)
1078	pThis->pDrvSerial->pfnChgModemLines(pThis->pDrvSerial, false /fRts/, false /fDtr/);
1079
1080	pThis->uRegMcr = uVal;
1081	if (uVal & UART_REG_MCR_LOOP)
1082	{
1083	uint8_t uRegMsrSts = 0;
1084
1085	if (uVal & UART_REG_MCR_RTS)
1086	uRegMsrSts \|= UART_REG_MSR_CTS;
1087	if (uVal & UART_REG_MCR_DTR)
1088	uRegMsrSts \|= UART_REG_MSR_DSR;
1089	if (uVal & UART_REG_MCR_OUT1)
1090	uRegMsrSts \|= UART_REG_MSR_RI;
1091	if (uVal & UART_REG_MCR_OUT2)
1092	uRegMsrSts \|= UART_REG_MSR_DCD;
1093	uartR3MsrUpdate(pThis, uRegMsrSts);
1094	}
1095	else if (pThis->pDrvSerial)
1096	pThis->pDrvSerial->pfnChgModemLines(pThis->pDrvSerial,
1097	RT_BOOL(uVal & UART_REG_MCR_RTS),
1098	RT_BOOL(uVal & UART_REG_MCR_DTR));
1099	#endif
1100	}
1101
1102	return rc;
1103	}
1104
1105
1106	/**
1107	* Read handler for the RBR/DLL register (depending on the DLAB bit in LCR).
1108	*
1109	* @returns VBox status code.
1110	* @param pThis The serial port instance.
1111	* @param puVal Where to store the read value on success.
1112	*/
1113	DECLINLINE(int) uartRegRbrDllRead(PUARTCORE pThis, uint32_t *puVal)
1114	{
1115	int rc = VINF_SUCCESS;
1116
1117	/* A set DLAB causes a read from the lower 8bits of the divisor latch. */
1118	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1119	*puVal = pThis->uRegDivisor & 0xff;
1120	else
1121	{
1122	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
1123	{
1124	/*
1125	* Only go back to R3 if there is new data available for the FIFO
1126	* and we would clear the interrupt to fill it up again.
1127	*/
1128	if ( pThis->FifoRecv.cbUsed <= pThis->FifoRecv.cbItl
1129	&& ASMAtomicReadU32(&pThis->cbAvailRdr) > 0)
1130	{
1131	#ifndef IN_RING3
1132	rc = VINF_IOM_R3_IOPORT_READ;
1133	#else
1134	uartR3RecvFifoFill(pThis);
1135	#endif
1136	}
1137
1138	if (rc == VINF_SUCCESS)
1139	{
1140	*puVal = uartFifoGet(&pThis->FifoRecv);
1141	pThis->fIrqCtiPending = false;
1142	if (!pThis->FifoRecv.cbUsed)
1143	{
1144	TMTimerStop(pThis->CTX_SUFF(pTimerRcvFifoTimeout));
1145	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
1146	}
1147	else if (pThis->FifoRecv.cbUsed < pThis->FifoRecv.cbItl)
1148	TMTimerSetRelative(pThis->CTX_SUFF(pTimerRcvFifoTimeout), pThis->cSymbolXferTicks * 4, NULL);
1149	uartIrqUpdate(pThis);
1150	}
1151	}
1152	else
1153	{
1154	*puVal = pThis->uRegRbr;
1155
1156	if (pThis->uRegLsr & UART_REG_LSR_DR)
1157	{
1158	Assert(pThis->cbAvailRdr);
1159	uint32_t cbAvail = ASMAtomicDecU32(&pThis->cbAvailRdr);
1160	if (!cbAvail)
1161	{
1162	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
1163	uartIrqUpdate(pThis);
1164	}
1165	else
1166	{
1167	#ifndef IN_RING3
1168	/* Restore state and go back to R3. */
1169	ASMAtomicIncU32(&pThis->cbAvailRdr);
1170	rc = VINF_IOM_R3_IOPORT_READ;
1171	#else
1172	/* Fetch new data and keep the DR bit set. */
1173	uartR3DataFetch(pThis);
1174	#endif
1175	}
1176	}
1177	}
1178	}
1179
1180	return rc;
1181	}
1182
1183
1184	/**
1185	* Read handler for the IER/DLM register (depending on the DLAB bit in LCR).
1186	*
1187	* @returns VBox status code.
1188	* @param pThis The serial port instance.
1189	* @param puVal Where to store the read value on success.
1190	*/
1191	DECLINLINE(int) uartRegIerDlmRead(PUARTCORE pThis, uint32_t *puVal)
1192	{
1193	int rc = VINF_SUCCESS;
1194
1195	/* A set DLAB causes a read from the upper 8bits of the divisor latch. */
1196	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1197	*puVal = (pThis->uRegDivisor & 0xff00) >> 8;
1198	else
1199	*puVal = pThis->uRegIer;
1200
1201	return rc;
1202	}
1203
1204
1205	/**
1206	* Read handler for the IIR register.
1207	*
1208	* @returns VBox status code.
1209	* @param pThis The serial port instance.
1210	* @param puVal Where to store the read value on success.
1211	*/
1212	DECLINLINE(int) uartRegIirRead(PUARTCORE pThis, uint32_t *puVal)
1213	{
1214	*puVal = pThis->uRegIir;
1215	/* Reset the THRE empty interrupt id when this gets returned to the guest (see table 3 UART Reset configuration). */
1216	if (UART_REG_IIR_ID_GET(pThis->uRegIir) == UART_REG_IIR_ID_THRE)
1217	{
1218	pThis->fThreEmptyPending = false;
1219	uartIrqUpdate(pThis);
1220	}
1221	return VINF_SUCCESS;
1222	}
1223
1224
1225	/**
1226	* Read handler for the LSR register.
1227	*
1228	* @returns VBox status code.
1229	* @param pThis The serial port instance.
1230	* @param puVal Where to store the read value on success.
1231	*/
1232	DECLINLINE(int) uartRegLsrRead(PUARTCORE pThis, uint32_t *puVal)
1233	{
1234	int rc = VINF_SUCCESS;
1235
1236	/* Yield if configured and there is no data available. */
1237	if ( !(pThis->uRegLsr & UART_REG_LSR_DR)
1238	&& (pThis->fFlags & UART_CORE_YIELD_ON_LSR_READ))
1239	{
1240	#ifndef IN_RING3
1241	return VINF_IOM_R3_IOPORT_READ;
1242	#else
1243	RTThreadYield();
1244	#endif
1245	}
1246
1247	*puVal = pThis->uRegLsr;
1248	/*
1249	* Reading this register clears the Overrun (OE), Parity (PE) and Framing (FE) error
1250	* as well as the Break Interrupt (BI).
1251	*/
1252	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_BITS_IIR_RCL);
1253	uartIrqUpdate(pThis);
1254
1255	return rc;
1256	}
1257
1258
1259	/**
1260	* Read handler for the MSR register.
1261	*
1262	* @returns VBox status code.
1263	* @param pThis The serial port instance.
1264	* @param puVal Where to store the read value on success.
1265	*/
1266	DECLINLINE(int) uartRegMsrRead(PUARTCORE pThis, uint32_t *puVal)
1267	{
1268	*puVal = pThis->uRegMsr;
1269
1270	/* Clear any of the delta bits. */
1271	UART_REG_CLR(pThis->uRegMsr, UART_REG_MSR_BITS_IIR_MS);
1272	uartIrqUpdate(pThis);
1273	return VINF_SUCCESS;
1274	}
1275
1276
1277	#ifdef LOG_ENABLED
1278	/**
1279	* Converts the register index into a sensible memnonic.
1280	*
1281	* @returns Register memnonic.
1282	* @param pThis The serial port instance.
1283	* @param idxReg Register index.
1284	* @param fWrite Flag whether the register gets written.
1285	*/
1286	DECLINLINE(const char *) uartRegIdx2Str(PUARTCORE pThis, uint8_t idxReg, bool fWrite)
1287	{
1288	const char *psz = "INV";
1289
1290	switch (idxReg)
1291	{
1292	/case UART_REG_THR_DLL_INDEX:/
1293	case UART_REG_RBR_DLL_INDEX:
1294	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1295	psz = "DLL";
1296	else if (fWrite)
1297	psz = "THR";
1298	else
1299	psz = "RBR";
1300	break;
1301	case UART_REG_IER_DLM_INDEX:
1302	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1303	psz = "DLM";
1304	else
1305	psz = "IER";
1306	break;
1307	/case UART_REG_IIR_INDEX:/
1308	case UART_REG_FCR_INDEX:
1309	if (fWrite)
1310	psz = "FCR";
1311	else
1312	psz = "IIR";
1313	break;
1314	case UART_REG_LCR_INDEX:
1315	psz = "LCR";
1316	break;
1317	case UART_REG_MCR_INDEX:
1318	psz = "MCR";
1319	break;
1320	case UART_REG_LSR_INDEX:
1321	psz = "LSR";
1322	break;
1323	case UART_REG_MSR_INDEX:
1324	psz = "MSR";
1325	break;
1326	case UART_REG_SCR_INDEX:
1327	psz = "SCR";
1328	break;
1329	}
1330
1331	return psz;
1332	}
1333	#endif
1334
1335
1336	DECLHIDDEN(int) uartRegWrite(PUARTCORE pThis, uint32_t uReg, uint32_t u32, size_t cb)
1337	{
1338	AssertMsgReturn(cb == 1, ("uReg=%#x cb=%d u32=%#x\n", uReg, cb, u32), VINF_SUCCESS);
1339
1340	int rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_R3_IOPORT_WRITE);
1341	if (rc != VINF_SUCCESS)
1342	return rc;
1343
1344	uint8_t idxReg = uReg & 0x7;
1345	LogFlowFunc(("pThis=%#p uReg=%u{%s} u32=%#x cb=%u\n",
1346	pThis, uReg, uartRegIdx2Str(pThis, idxReg, true /fWrite/), u32, cb));
1347
1348	uint8_t uVal = (uint8_t)u32;
1349	switch (idxReg)
1350	{
1351	case UART_REG_THR_DLL_INDEX:
1352	rc = uartRegThrDllWrite(pThis, uVal);
1353	break;
1354	case UART_REG_IER_DLM_INDEX:
1355	rc = uartRegIerDlmWrite(pThis, uVal);
1356	break;
1357	case UART_REG_FCR_INDEX:
1358	rc = uartRegFcrWrite(pThis, uVal);
1359	break;
1360	case UART_REG_LCR_INDEX:
1361	rc = uartRegLcrWrite(pThis, uVal);
1362	break;
1363	case UART_REG_MCR_INDEX:
1364	rc = uartRegMcrWrite(pThis, uVal);
1365	break;
1366	case UART_REG_SCR_INDEX:
1367	pThis->uRegScr = u32;
1368	break;
1369	default:
1370	break;
1371	}
1372
1373	PDMCritSectLeave(&pThis->CritSect);
1374	LogFlowFunc(("-> %Rrc\n", rc));
1375	return rc;
1376	}
1377
1378
1379	DECLHIDDEN(int) uartRegRead(PUARTCORE pThis, uint32_t uReg, uint32_t *pu32, size_t cb)
1380	{
1381	if (cb != 1)
1382	return VERR_IOM_IOPORT_UNUSED;
1383
1384	int rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_R3_IOPORT_READ);
1385	if (rc != VINF_SUCCESS)
1386	return rc;
1387
1388	uint8_t idxReg = uReg & 0x7;
1389	switch (idxReg)
1390	{
1391	case UART_REG_RBR_DLL_INDEX:
1392	rc = uartRegRbrDllRead(pThis, pu32);
1393	break;
1394	case UART_REG_IER_DLM_INDEX:
1395	rc = uartRegIerDlmRead(pThis, pu32);
1396	break;
1397	case UART_REG_IIR_INDEX:
1398	rc = uartRegIirRead(pThis, pu32);
1399	break;
1400	case UART_REG_LCR_INDEX:
1401	*pu32 = pThis->uRegLcr;
1402	break;
1403	case UART_REG_MCR_INDEX:
1404	*pu32 = pThis->uRegMcr;
1405	break;
1406	case UART_REG_LSR_INDEX:
1407	rc = uartRegLsrRead(pThis, pu32);
1408	break;
1409	case UART_REG_MSR_INDEX:
1410	rc = uartRegMsrRead(pThis, pu32);
1411	break;
1412	case UART_REG_SCR_INDEX:
1413	*pu32 = pThis->uRegScr;
1414	break;
1415	default:
1416	rc = VERR_IOM_IOPORT_UNUSED;
1417	}
1418
1419	PDMCritSectLeave(&pThis->CritSect);
1420	LogFlowFunc(("pThis=%#p uReg=%u{%s} u32=%#x cb=%u -> %Rrc\n",
1421	pThis, uReg, uartRegIdx2Str(pThis, idxReg, false /fWrite/), *pu32, cb, rc));
1422	return rc;
1423	}
1424
1425
1426	#ifdef IN_RING3
1427
1428	/* -=-=-=-=-=-=-=-=- Timer callbacks -=-=-=-=-=-=-=-=- */
1429
1430	/**
1431	* @callback_method_impl{FNTMTIMERDEV, Fifo timer function.}
1432	*/
1433	static DECLCALLBACK(void) uartR3RcvFifoTimeoutTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1434	{
1435	LogFlowFunc(("pDevIns=%#p pTimer=%#p pvUser=%#p\n", pDevIns, pTimer, pvUser));
1436	RT_NOREF(pDevIns, pTimer);
1437	PUARTCORE pThis = (PUARTCORE)pvUser;
1438	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1439	if (pThis->FifoRecv.cbUsed < pThis->FifoRecv.cbItl)
1440	{
1441	pThis->fIrqCtiPending = true;
1442	uartIrqUpdate(pThis);
1443	}
1444	PDMCritSectLeave(&pThis->CritSect);
1445	}
1446
1447	/**
1448	* @callback_method_impl{FNTMTIMERDEV, TX timer function when there is no driver connected for draining the THR/FIFO.}
1449	*/
1450	static DECLCALLBACK(void) uartR3TxUnconnectedTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1451	{
1452	LogFlowFunc(("pDevIns=%#p pTimer=%#p pvUser=%#p\n", pDevIns, pTimer, pvUser));
1453	RT_NOREF(pDevIns, pTimer);
1454	PUARTCORE pThis = (PUARTCORE)pvUser;
1455	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1456	uint8_t bVal = 0;
1457	size_t cbRead = 0;
1458	uartR3TxQueueCopyFrom(pThis, &bVal, sizeof(bVal), &cbRead);
1459	if (pThis->uRegMcr & UART_REG_MCR_LOOP)
1460	{
1461	/* Loopback mode is active, feed in the data at the receiving end. */
1462	uint32_t cbAvailOld = ASMAtomicAddU32(&pThis->cbAvailRdr, 1);
1463	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
1464	{
1465	PUARTFIFO pFifo = &pThis->FifoRecv;
1466	if (uartFifoFreeGet(pFifo) > 0)
1467	{
1468	pFifo->abBuf[pFifo->offWrite] = bVal;
1469	pFifo->offWrite = (pFifo->offWrite + 1) % pFifo->cbMax;
1470	pFifo->cbUsed++;
1471
1472	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
1473	if (pFifo->cbUsed < pFifo->cbItl)
1474	{
1475	pThis->fIrqCtiPending = false;
1476	TMTimerSetRelative(pThis->CTX_SUFF(pTimerRcvFifoTimeout), pThis->cSymbolXferTicks * 4, NULL);
1477	}
1478	uartIrqUpdate(pThis);
1479	}
1480
1481	ASMAtomicSubU32(&pThis->cbAvailRdr, 1);
1482	}
1483	else if (!cbAvailOld)
1484	{
1485	pThis->uRegRbr = bVal;
1486	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
1487	uartIrqUpdate(pThis);
1488	}
1489	}
1490	if (cbRead == 1)
1491	TMTimerSetRelative(pThis->CTX_SUFF(pTimerTxUnconnected), pThis->cSymbolXferTicks, NULL);
1492	PDMCritSectLeave(&pThis->CritSect);
1493	}
1494
1495
1496	/* -=-=-=-=-=-=-=-=- PDMISERIALPORT on LUN#0 -=-=-=-=-=-=-=-=- */
1497
1498
1499	/**
1500	* @interface_method_impl{PDMISERIALPORT,pfnDataAvailRdrNotify}
1501	*/
1502	static DECLCALLBACK(int) uartR3DataAvailRdrNotify(PPDMISERIALPORT pInterface, size_t cbAvail)
1503	{
1504	LogFlowFunc(("pInterface=%#p cbAvail=%zu\n", pInterface, cbAvail));
1505	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1506
1507	AssertMsg((uint32_t)cbAvail == cbAvail, ("Too much data available\n"));
1508
1509	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1510	uint32_t cbAvailOld = ASMAtomicAddU32(&pThis->cbAvailRdr, (uint32_t)cbAvail);
1511	LogFlow((" cbAvailRdr=%u -> cbAvailRdr=%u\n", cbAvailOld, cbAvail + cbAvailOld));
1512	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
1513	uartR3RecvFifoFill(pThis);
1514	else if (!cbAvailOld)
1515	{
1516	size_t cbRead = 0;
1517	int rc = pThis->pDrvSerial->pfnReadRdr(pThis->pDrvSerial, &pThis->uRegRbr, 1, &cbRead);
1518	AssertMsg(RT_SUCCESS(rc) && cbRead == 1, ("This shouldn't fail and always return one byte!\n")); RT_NOREF(rc);
1519	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
1520	uartIrqUpdate(pThis);
1521	}
1522	PDMCritSectLeave(&pThis->CritSect);
1523
1524	return VINF_SUCCESS;
1525	}
1526
1527
1528	/**
1529	* @interface_method_impl{PDMISERIALPORT,pfnDataSentNotify}
1530	*/
1531	static DECLCALLBACK(int) uartR3DataSentNotify(PPDMISERIALPORT pInterface)
1532	{
1533	LogFlowFunc(("pInterface=%#p\n", pInterface));
1534	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1535
1536	/* Set the transmitter empty bit because everything was sent. */
1537	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1538	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_TEMT);
1539	uartIrqUpdate(pThis);
1540	PDMCritSectLeave(&pThis->CritSect);
1541	return VINF_SUCCESS;
1542	}
1543
1544
1545	/**
1546	* @interface_method_impl{PDMISERIALPORT,pfnReadWr}
1547	*/
1548	static DECLCALLBACK(int) uartR3ReadWr(PPDMISERIALPORT pInterface, void pvBuf, size_t cbRead, size_t pcbRead)
1549	{
1550	LogFlowFunc(("pInterface=%#p pvBuf=%#p cbRead=%zu pcbRead=%#p\n", pInterface, pvBuf, cbRead, pcbRead));
1551	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1552
1553	AssertReturn(cbRead > 0, VERR_INVALID_PARAMETER);
1554
1555	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1556	uartR3TxQueueCopyFrom(pThis, pvBuf, cbRead, pcbRead);
1557	PDMCritSectLeave(&pThis->CritSect);
1558
1559	LogFlowFunc(("-> VINF_SUCCESS{pcbRead=%zu}\n", pcbRead));
1560	return VINF_SUCCESS;
1561	}
1562
1563
1564	/**
1565	* @interface_method_impl{PDMISERIALPORT,pfnNotifyStsLinesChanged}
1566	*/
1567	static DECLCALLBACK(int) uartR3NotifyStsLinesChanged(PPDMISERIALPORT pInterface, uint32_t fNewStatusLines)
1568	{
1569	LogFlowFunc(("pInterface=%#p fNewStatusLines=%#x\n", pInterface, fNewStatusLines));
1570	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1571
1572	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1573	uartR3StsLinesUpdate(pThis, fNewStatusLines);
1574	PDMCritSectLeave(&pThis->CritSect);
1575	return VINF_SUCCESS;
1576	}
1577
1578
1579	/**
1580	* @interface_method_impl{PDMISERIALPORT,pfnNotifyBrk}
1581	*/
1582	static DECLCALLBACK(int) uartR3NotifyBrk(PPDMISERIALPORT pInterface)
1583	{
1584	LogFlowFunc(("pInterface=%#p\n", pInterface));
1585	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1586
1587	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1588	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_BI);
1589	uartIrqUpdate(pThis);
1590	PDMCritSectLeave(&pThis->CritSect);
1591	return VINF_SUCCESS;
1592	}
1593
1594
1595	/* -=-=-=-=-=-=-=-=- PDMIBASE -=-=-=-=-=-=-=-=- */
1596
1597	/**
1598	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
1599	*/
1600	static DECLCALLBACK(void ) uartR3QueryInterface(PPDMIBASE pInterface, const char pszIID)
1601	{
1602	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, IBase);
1603	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
1604	PDMIBASE_RETURN_INTERFACE(pszIID, PDMISERIALPORT, &pThis->ISerialPort);
1605	return NULL;
1606	}
1607
1608
1609	DECLHIDDEN(int) uartR3SaveExec(PUARTCORE pThis, PSSMHANDLE pSSM)
1610	{
1611	SSMR3PutU16(pSSM, pThis->uRegDivisor);
1612	SSMR3PutU8(pSSM, pThis->uRegRbr);
1613	SSMR3PutU8(pSSM, pThis->uRegThr);
1614	SSMR3PutU8(pSSM, pThis->uRegIer);
1615	SSMR3PutU8(pSSM, pThis->uRegIir);
1616	SSMR3PutU8(pSSM, pThis->uRegFcr);
1617	SSMR3PutU8(pSSM, pThis->uRegLcr);
1618	SSMR3PutU8(pSSM, pThis->uRegMcr);
1619	SSMR3PutU8(pSSM, pThis->uRegLsr);
1620	SSMR3PutU8(pSSM, pThis->uRegMsr);
1621	SSMR3PutU8(pSSM, pThis->uRegScr);
1622	SSMR3PutBool(pSSM, pThis->fIrqCtiPending);
1623	SSMR3PutBool(pSSM, pThis->fThreEmptyPending);
1624	SSMR3PutU8(pSSM, pThis->FifoXmit.cbMax);
1625	SSMR3PutU8(pSSM, pThis->FifoXmit.cbItl);
1626	SSMR3PutU8(pSSM, pThis->FifoRecv.cbMax);
1627	SSMR3PutU8(pSSM, pThis->FifoRecv.cbItl);
1628
1629	int rc = TMR3TimerSave(pThis->pTimerRcvFifoTimeoutR3, pSSM);
1630	if (RT_SUCCESS(rc))
1631	rc = TMR3TimerSave(pThis->pTimerTxUnconnectedR3, pSSM);
1632
1633	return rc;
1634	}
1635
1636
1637	DECLHIDDEN(int) uartR3LoadExec(PUARTCORE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass,
1638	uint8_t pbIrq, RTIOPORT pPortBase)
1639	{
1640	RT_NOREF(uPass);
1641	int rc;
1642
1643	if (uVersion > UART_SAVED_STATE_VERSION_LEGACY_CODE)
1644	{
1645	SSMR3GetU16(pSSM, &pThis->uRegDivisor);
1646	SSMR3GetU8(pSSM, &pThis->uRegRbr);
1647	SSMR3GetU8(pSSM, &pThis->uRegThr);
1648	SSMR3GetU8(pSSM, &pThis->uRegIer);
1649	SSMR3GetU8(pSSM, &pThis->uRegIir);
1650	SSMR3GetU8(pSSM, &pThis->uRegFcr);
1651	SSMR3GetU8(pSSM, &pThis->uRegLcr);
1652	SSMR3GetU8(pSSM, &pThis->uRegMcr);
1653	SSMR3GetU8(pSSM, &pThis->uRegLsr);
1654	SSMR3GetU8(pSSM, &pThis->uRegMsr);
1655	SSMR3GetU8(pSSM, &pThis->uRegScr);
1656	SSMR3GetBool(pSSM, &pThis->fIrqCtiPending);
1657	SSMR3GetBool(pSSM, &pThis->fThreEmptyPending);
1658	SSMR3GetU8(pSSM, &pThis->FifoXmit.cbMax);
1659	SSMR3GetU8(pSSM, &pThis->FifoXmit.cbItl);
1660	SSMR3GetU8(pSSM, &pThis->FifoRecv.cbMax);
1661	SSMR3GetU8(pSSM, &pThis->FifoRecv.cbItl);
1662
1663	rc = TMR3TimerLoad(pThis->pTimerRcvFifoTimeoutR3, pSSM);
1664	if (uVersion > UART_SAVED_STATE_VERSION_PRE_UNCONNECTED_TX_TIMER)
1665	rc = TMR3TimerLoad(pThis->pTimerTxUnconnectedR3, pSSM);
1666	}
1667	else
1668	{
1669	AssertPtr(pbIrq);
1670	AssertPtr(pPortBase);
1671	if (uVersion == UART_SAVED_STATE_VERSION_16450)
1672	{
1673	pThis->enmType = UARTTYPE_16450;
1674	LogRel(("Serial#%d: falling back to 16450 mode from load state\n", pThis->pDevInsR3->iInstance));
1675	}
1676
1677	SSMR3GetU16(pSSM, &pThis->uRegDivisor);
1678	SSMR3GetU8(pSSM, &pThis->uRegRbr);
1679	SSMR3GetU8(pSSM, &pThis->uRegIer);
1680	SSMR3GetU8(pSSM, &pThis->uRegLcr);
1681	SSMR3GetU8(pSSM, &pThis->uRegMcr);
1682	SSMR3GetU8(pSSM, &pThis->uRegLsr);
1683	SSMR3GetU8(pSSM, &pThis->uRegMsr);
1684	SSMR3GetU8(pSSM, &pThis->uRegScr);
1685	if (uVersion > UART_SAVED_STATE_VERSION_16450)
1686	SSMR3GetU8(pSSM, &pThis->uRegFcr);
1687
1688	int32_t iTmp = 0;
1689	SSMR3GetS32(pSSM, &iTmp);
1690	pThis->fThreEmptyPending = RT_BOOL(iTmp);
1691
1692	rc = SSMR3GetS32(pSSM, &iTmp);
1693	AssertRCReturn(rc, rc);
1694	*pbIrq = (uint8_t)iTmp;
1695
1696	SSMR3Skip(pSSM, sizeof(int32_t)); /* was: last_break_enable */
1697
1698	uint32_t uPortBaseTmp = 0;
1699	rc = SSMR3GetU32(pSSM, &uPortBaseTmp);
1700	AssertRCReturn(rc, rc);
1701	*pPortBase = (RTIOPORT)uPortBaseTmp;
1702
1703	rc = SSMR3Skip(pSSM, sizeof(bool)); /* was: msr_changed */
1704	if ( RT_SUCCESS(rc)
1705	&& uVersion > UART_SAVED_STATE_VERSION_MISSING_BITS)
1706	{
1707	SSMR3GetU8(pSSM, &pThis->uRegThr);
1708	SSMR3Skip(pSSM, sizeof(uint8_t)); /* The old transmit shift register, not used anymore. */
1709	SSMR3GetU8(pSSM, &pThis->uRegIir);
1710
1711	int32_t iTimeoutPending = 0;
1712	SSMR3GetS32(pSSM, &iTimeoutPending);
1713	pThis->fIrqCtiPending = RT_BOOL(iTimeoutPending);
1714
1715	rc = TMR3TimerLoad(pThis->pTimerRcvFifoTimeoutR3, pSSM);
1716	AssertRCReturn(rc, rc);
1717
1718	bool fWasActiveIgn;
1719	rc = TMR3TimerSkip(pSSM, &fWasActiveIgn); /* was: transmit_timerR3 */
1720	AssertRCReturn(rc, rc);
1721
1722	SSMR3GetU8(pSSM, &pThis->FifoRecv.cbItl);
1723	rc = SSMR3GetU8(pSSM, &pThis->FifoRecv.cbItl);
1724	}
1725	}
1726
1727	return rc;
1728	}
1729
1730
1731	DECLHIDDEN(int) uartR3LoadDone(PUARTCORE pThis, PSSMHANDLE pSSM)
1732	{
1733	RT_NOREF(pSSM);
1734
1735	uartR3ParamsUpdate(pThis);
1736	uartIrqUpdate(pThis);
1737
1738	if (pThis->pDrvSerial)
1739	{
1740	/* Set the modem lines to reflect the current state. */
1741	int rc = pThis->pDrvSerial->pfnChgModemLines(pThis->pDrvSerial,
1742	RT_BOOL(pThis->uRegMcr & UART_REG_MCR_RTS),
1743	RT_BOOL(pThis->uRegMcr & UART_REG_MCR_DTR));
1744	if (RT_FAILURE(rc))
1745	LogRel(("Serial#%d: Failed to set modem lines with %Rrc during saved state load\n",
1746	pThis->pDevInsR3->iInstance, rc));
1747
1748	uint32_t fStsLines = 0;
1749	rc = pThis->pDrvSerial->pfnQueryStsLines(pThis->pDrvSerial, &fStsLines);
1750	if (RT_SUCCESS(rc))
1751	uartR3StsLinesUpdate(pThis, fStsLines);
1752	else
1753	LogRel(("Serial#%d: Failed to query status line status with %Rrc during reset\n",
1754	pThis->pDevInsR3->iInstance, rc));
1755	}
1756
1757	return VINF_SUCCESS;
1758	}
1759
1760
1761	DECLHIDDEN(void) uartR3Relocate(PUARTCORE pThis, RTGCINTPTR offDelta)
1762	{
1763	RT_NOREF(offDelta);
1764	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pThis->pDevInsR3);
1765	pThis->pTimerRcvFifoTimeoutRC = TMTimerRCPtr(pThis->pTimerRcvFifoTimeoutR3);
1766	pThis->pTimerTxUnconnectedRC = TMTimerRCPtr(pThis->pTimerTxUnconnectedR3);
1767	}
1768
1769
1770	DECLHIDDEN(void) uartR3Reset(PUARTCORE pThis)
1771	{
1772	pThis->uRegDivisor = 0x0c; /* Default to 9600 Baud. */
1773	pThis->uRegRbr = 0;
1774	pThis->uRegThr = 0;
1775	pThis->uRegIer = 0;
1776	pThis->uRegIir = UART_REG_IIR_IP_NO_INT;
1777	pThis->uRegFcr = 0;
1778	pThis->uRegLcr = 0; /* 5 data bits, no parity, 1 stop bit. */
1779	pThis->uRegMcr = 0;
1780	pThis->uRegLsr = UART_REG_LSR_THRE \| UART_REG_LSR_TEMT;
1781	pThis->uRegMsr = 0; /* Updated below. */
1782	pThis->uRegScr = 0;
1783	pThis->fIrqCtiPending = false;
1784	pThis->fThreEmptyPending = true;
1785
1786	/* Standard FIFO size for 15550A. */
1787	pThis->FifoXmit.cbMax = 16;
1788	pThis->FifoRecv.cbMax = 16;
1789	pThis->FifoRecv.cbItl = 1;
1790
1791	uartR3XferReset(pThis);
1792	}
1793
1794
1795	DECLHIDDEN(int) uartR3Attach(PUARTCORE pThis, unsigned iLUN)
1796	{
1797	int rc = PDMDevHlpDriverAttach(pThis->pDevInsR3, iLUN, &pThis->IBase, &pThis->pDrvBase, "Serial Char");
1798	if (RT_SUCCESS(rc))
1799	{
1800	pThis->pDrvSerial = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMISERIALCONNECTOR);
1801	if (!pThis->pDrvSerial)
1802	{
1803	AssertLogRelMsgFailed(("Configuration error: instance %d has no serial interface!\n", pThis->pDevInsR3->iInstance));
1804	return VERR_PDM_MISSING_INTERFACE;
1805	}
1806	uartR3XferReset(pThis);
1807	}
1808	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1809	{
1810	pThis->pDrvBase = NULL;
1811	pThis->pDrvSerial = NULL;
1812	rc = VINF_SUCCESS;
1813	uartR3XferReset(pThis);
1814	LogRel(("Serial#%d: no unit\n", pThis->pDevInsR3->iInstance));
1815	}
1816	else /* Don't call VMSetError here as we assume that the driver already set an appropriate error */
1817	LogRel(("Serial#%d: Failed to attach to serial driver. rc=%Rrc\n", pThis->pDevInsR3->iInstance, rc));
1818
1819	return rc;
1820	}
1821
1822
1823	DECLHIDDEN(void) uartR3Detach(PUARTCORE pThis)
1824	{
1825	/* Zero out important members. */
1826	pThis->pDrvBase = NULL;
1827	pThis->pDrvSerial = NULL;
1828	uartR3XferReset(pThis);
1829	}
1830
1831
1832	DECLHIDDEN(void) uartR3Destruct(PUARTCORE pThis)
1833	{
1834	PDMR3CritSectDelete(&pThis->CritSect);
1835	}
1836
1837
1838	DECLHIDDEN(int) uartR3Init(PUARTCORE pThis, PPDMDEVINS pDevInsR3, UARTTYPE enmType, unsigned iLUN, uint32_t fFlags,
1839	R3PTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReqR3, R0PTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReqR0,
1840	RCPTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReqRC)
1841	{
1842	int rc = VINF_SUCCESS;
1843
1844	/*
1845	* Initialize the instance data.
1846	* (Do this early or the destructor might choke on something!)
1847	*/
1848	pThis->pDevInsR3 = pDevInsR3;
1849	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevInsR3);
1850	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevInsR3);
1851	pThis->iLUN = iLUN;
1852	pThis->enmType = enmType;
1853	pThis->fFlags = fFlags;
1854	pThis->pfnUartIrqReqR3 = pfnUartIrqReqR3;
1855	pThis->pfnUartIrqReqR0 = pfnUartIrqReqR0;
1856	pThis->pfnUartIrqReqRC = pfnUartIrqReqRC;
1857
1858	/* IBase */
1859	pThis->IBase.pfnQueryInterface = uartR3QueryInterface;
1860
1861	/* ISerialPort */
1862	pThis->ISerialPort.pfnDataAvailRdrNotify = uartR3DataAvailRdrNotify;
1863	pThis->ISerialPort.pfnDataSentNotify = uartR3DataSentNotify;
1864	pThis->ISerialPort.pfnReadWr = uartR3ReadWr;
1865	pThis->ISerialPort.pfnNotifyStsLinesChanged = uartR3NotifyStsLinesChanged;
1866	pThis->ISerialPort.pfnNotifyBrk = uartR3NotifyBrk;
1867
1868	rc = PDMDevHlpCritSectInit(pDevInsR3, &pThis->CritSect, RT_SRC_POS, "Uart{%s#%d}#%d",
1869	pDevInsR3->pReg->szName, pDevInsR3->iInstance, iLUN);
1870	AssertRCReturn(rc, rc);
1871
1872	/*
1873	* Attach the char driver and get the interfaces.
1874	*/
1875	rc = PDMDevHlpDriverAttach(pDevInsR3, iLUN, &pThis->IBase, &pThis->pDrvBase, "UART");
1876	if (RT_SUCCESS(rc))
1877	{
1878	pThis->pDrvSerial = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMISERIALCONNECTOR);
1879	if (!pThis->pDrvSerial)
1880	{
1881	AssertLogRelMsgFailed(("Configuration error: instance %d has no serial interface!\n", iLUN));
1882	return VERR_PDM_MISSING_INTERFACE;
1883	}
1884	}
1885	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1886	{
1887	pThis->pDrvBase = NULL;
1888	pThis->pDrvSerial = NULL;
1889	LogRel(("Serial#%d: no unit\n", iLUN));
1890	}
1891	else
1892	{
1893	AssertLogRelMsgFailed(("Serial#%d: Failed to attach to char driver. rc=%Rrc\n", iLUN, rc));
1894	/* Don't call VMSetError here as we assume that the driver already set an appropriate error */
1895	return rc;
1896	}
1897
1898	/*
1899	* Create the receive FIFO character timeout indicator timer.
1900	*/
1901	rc = PDMDevHlpTMTimerCreate(pDevInsR3, TMCLOCK_VIRTUAL, uartR3RcvFifoTimeoutTimer, pThis,
1902	TMTIMER_FLAGS_NO_CRIT_SECT, "UART Rcv FIFO Timer",
1903	&pThis->pTimerRcvFifoTimeoutR3);
1904	AssertRCReturn(rc, rc);
1905
1906	rc = TMR3TimerSetCritSect(pThis->pTimerRcvFifoTimeoutR3, &pThis->CritSect);
1907	AssertRCReturn(rc, rc);
1908
1909	pThis->pTimerRcvFifoTimeoutR0 = TMTimerR0Ptr(pThis->pTimerRcvFifoTimeoutR3);
1910	pThis->pTimerRcvFifoTimeoutRC = TMTimerRCPtr(pThis->pTimerRcvFifoTimeoutR3);
1911
1912	/*
1913	* Create the transmit timer when no device is connected.
1914	*/
1915	rc = PDMDevHlpTMTimerCreate(pDevInsR3, TMCLOCK_VIRTUAL, uartR3TxUnconnectedTimer, pThis,
1916	TMTIMER_FLAGS_NO_CRIT_SECT, "UART TX uncon. Timer",
1917	&pThis->pTimerTxUnconnectedR3);
1918	AssertRCReturn(rc, rc);
1919
1920	rc = TMR3TimerSetCritSect(pThis->pTimerTxUnconnectedR3, &pThis->CritSect);
1921	AssertRCReturn(rc, rc);
1922
1923	pThis->pTimerTxUnconnectedR0 = TMTimerR0Ptr(pThis->pTimerTxUnconnectedR3);
1924	pThis->pTimerTxUnconnectedRC = TMTimerRCPtr(pThis->pTimerTxUnconnectedR3);
1925
1926	uartR3Reset(pThis);
1927	return VINF_SUCCESS;
1928	}
1929
1930	#endif /* IN_RING3 */
1931
1932	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Serial/UartCore.cpp@ 77611

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