UartCore.cpp@ 78403

Last change on this file since 78403 was 77806, checked in by vboxsync, 6 years ago
Devices/UartCore: Fix assertion to avoid crash in release builds
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1	/* $Id: UartCore.cpp 77806 2019-03-20 12:52:20Z vboxsync $ */
2	/** @file
3	* UartCore - UART (16550A up to 16950) emulation.
4	*
5	* The documentation for this device was taken from the PC16550D spec from TI.
6	*/
7
8	/*
9	* Copyright (C) 2018-2019 Oracle Corporation
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*/
19
20
21	/*********************************************************************************************************************************
22	* Header Files *
23	*********************************************************************************************************************************/
24	#define LOG_GROUP LOG_GROUP_DEV_SERIAL
25	#include <VBox/vmm/tm.h>
26	#include <iprt/log.h>
27	#include <iprt/uuid.h>
28	#include <iprt/assert.h>
29
30	#include "VBoxDD.h"
31	#include "UartCore.h"
32
33
34	/*********************************************************************************************************************************
35	* Defined Constants And Macros *
36	*********************************************************************************************************************************/
37
38	/** The RBR/DLL register index (from the base of the port range). */
39	#define UART_REG_RBR_DLL_INDEX 0
40
41	/** The THR/DLL register index (from the base of the port range). */
42	#define UART_REG_THR_DLL_INDEX 0
43
44	/** The IER/DLM register index (from the base of the port range). */
45	#define UART_REG_IER_DLM_INDEX 1
46	/** Enable received data available interrupt */
47	# define UART_REG_IER_ERBFI RT_BIT(0)
48	/** Enable transmitter holding register empty interrupt */
49	# define UART_REG_IER_ETBEI RT_BIT(1)
50	/** Enable receiver line status interrupt */
51	# define UART_REG_IER_ELSI RT_BIT(2)
52	/** Enable modem status interrupt. */
53	# define UART_REG_IER_EDSSI RT_BIT(3)
54	/** Sleep mode enable. */
55	# define UART_REG_IER_SLEEP_MODE_EN RT_BIT(4)
56	/** Low power mode enable. */
57	# define UART_REG_IER_LP_MODE_EN RT_BIT(5)
58	/** Mask of writeable bits. */
59	# define UART_REG_IER_MASK_WR 0x0f
60	/** Mask of writeable bits for 16750+. */
61	# define UART_REG_IER_MASK_WR_16750 0x3f
62
63	/** The IIR register index (from the base of the port range). */
64	#define UART_REG_IIR_INDEX 2
65	/** Interrupt Pending - high means no interrupt pending. */
66	# define UART_REG_IIR_IP_NO_INT RT_BIT(0)
67	/** Interrupt identification mask. */
68	# define UART_REG_IIR_ID_MASK 0x0e
69	/** Sets the interrupt identification to the given value. */
70	# define UART_REG_IIR_ID_SET(a_Val) (((a_Val) << 1) & UART_REG_IIR_ID_MASK)
71	/** Gets the interrupt identification from the given IIR register value. */
72	# define UART_REG_IIR_ID_GET(a_Val) (((a_Val) & UART_REG_IIR_ID_MASK) >> 1)
73	/** Receiver Line Status interrupt. */
74	# define UART_REG_IIR_ID_RCL 0x3
75	/** Received Data Available interrupt. */
76	# define UART_REG_IIR_ID_RDA 0x2
77	/** Character Timeou Indicator interrupt. */
78	# define UART_REG_IIR_ID_CTI 0x6
79	/** Transmitter Holding Register Empty interrupt. */
80	# define UART_REG_IIR_ID_THRE 0x1
81	/** Modem Status interrupt. */
82	# define UART_REG_IIR_ID_MS 0x0
83	/** 64 byte FIFOs enabled (15750+ only). */
84	# define UART_REG_IIR_64BYTE_FIFOS_EN RT_BIT(5)
85	/** FIFOs enabled. */
86	# define UART_REG_IIR_FIFOS_EN 0xc0
87	/** Bits relevant for checking whether the interrupt status has changed. */
88	# define UART_REG_IIR_CHANGED_MASK 0x0f
89
90	/** The FCR register index (from the base of the port range). */
91	#define UART_REG_FCR_INDEX 2
92	/** Enable the TX/RX FIFOs. */
93	# define UART_REG_FCR_FIFO_EN RT_BIT(0)
94	/** Reset the receive FIFO. */
95	# define UART_REG_FCR_RCV_FIFO_RST RT_BIT(1)
96	/** Reset the transmit FIFO. */
97	# define UART_REG_FCR_XMIT_FIFO_RST RT_BIT(2)
98	/** DMA Mode Select. */
99	# define UART_REG_FCR_DMA_MODE_SEL RT_BIT(3)
100	/** 64 Byte FIFO enable (15750+ only). */
101	# define UART_REG_FCR_64BYTE_FIFO_EN RT_BIT(5)
102	/** Receiver level interrupt trigger. */
103	# define UART_REG_FCR_RCV_LVL_IRQ_MASK 0xc0
104	/** Returns the receive level trigger value from the given FCR register. */
105	# define UART_REG_FCR_RCV_LVL_IRQ_GET(a_Fcr) (((a_Fcr) & UART_REG_FCR_RCV_LVL_IRQ_MASK) >> 6)
106	/** RCV Interrupt trigger level - 1 byte. */
107	# define UART_REG_FCR_RCV_LVL_IRQ_1 0x0
108	/** RCV Interrupt trigger level - 4 bytes. */
109	# define UART_REG_FCR_RCV_LVL_IRQ_4 0x1
110	/** RCV Interrupt trigger level - 8 bytes. */
111	# define UART_REG_FCR_RCV_LVL_IRQ_8 0x2
112	/** RCV Interrupt trigger level - 14 bytes. */
113	# define UART_REG_FCR_RCV_LVL_IRQ_14 0x3
114	/** Mask of writeable bits. */
115	# define UART_REG_FCR_MASK_WR 0xcf
116	/** Mask of sticky bits. */
117	# define UART_REG_FCR_MASK_STICKY 0xe9
118
119	/** The LCR register index (from the base of the port range). */
120	#define UART_REG_LCR_INDEX 3
121	/** Word Length Select Mask. */
122	# define UART_REG_LCR_WLS_MASK 0x3
123	/** Returns the WLS value form the given LCR register value. */
124	# define UART_REG_LCR_WLS_GET(a_Lcr) ((a_Lcr) & UART_REG_LCR_WLS_MASK)
125	/** Number of stop bits. */
126	# define UART_REG_LCR_STB RT_BIT(2)
127	/** Parity Enable. */
128	# define UART_REG_LCR_PEN RT_BIT(3)
129	/** Even Parity. */
130	# define UART_REG_LCR_EPS RT_BIT(4)
131	/** Stick parity. */
132	# define UART_REG_LCR_PAR_STICK RT_BIT(5)
133	/** Set Break. */
134	# define UART_REG_LCR_BRK_SET RT_BIT(6)
135	/** Divisor Latch Access Bit. */
136	# define UART_REG_LCR_DLAB RT_BIT(7)
137
138	/** The MCR register index (from the base of the port range). */
139	#define UART_REG_MCR_INDEX 4
140	/** Data Terminal Ready. */
141	# define UART_REG_MCR_DTR RT_BIT(0)
142	/** Request To Send. */
143	# define UART_REG_MCR_RTS RT_BIT(1)
144	/** Out1. */
145	# define UART_REG_MCR_OUT1 RT_BIT(2)
146	/** Out2. */
147	# define UART_REG_MCR_OUT2 RT_BIT(3)
148	/** Loopback connection. */
149	# define UART_REG_MCR_LOOP RT_BIT(4)
150	/** Flow Control Enable (15750+ only). */
151	# define UART_REG_MCR_AFE RT_BIT(5)
152	/** Mask of writeable bits (15450 and 15550A). */
153	# define UART_REG_MCR_MASK_WR 0x1f
154	/** Mask of writeable bits (15750+). */
155	# define UART_REG_MCR_MASK_WR_15750 0x3f
156
157	/** The LSR register index (from the base of the port range). */
158	#define UART_REG_LSR_INDEX 5
159	/** Data Ready. */
160	# define UART_REG_LSR_DR RT_BIT(0)
161	/** Overrun Error. */
162	# define UART_REG_LSR_OE RT_BIT(1)
163	/** Parity Error. */
164	# define UART_REG_LSR_PE RT_BIT(2)
165	/** Framing Error. */
166	# define UART_REG_LSR_FE RT_BIT(3)
167	/** Break Interrupt. */
168	# define UART_REG_LSR_BI RT_BIT(4)
169	/** Transmitter Holding Register. */
170	# define UART_REG_LSR_THRE RT_BIT(5)
171	/** Transmitter Empty. */
172	# define UART_REG_LSR_TEMT RT_BIT(6)
173	/** Error in receiver FIFO. */
174	# define UART_REG_LSR_RCV_FIFO_ERR RT_BIT(7)
175	/** The bits to check in this register when checking for the RCL interrupt. */
176	# define UART_REG_LSR_BITS_IIR_RCL 0x1e
177
178	/** The MSR register index (from the base of the port range). */
179	#define UART_REG_MSR_INDEX 6
180	/** Delta Clear to Send. */
181	# define UART_REG_MSR_DCTS RT_BIT(0)
182	/** Delta Data Set Ready. */
183	# define UART_REG_MSR_DDSR RT_BIT(1)
184	/** Trailing Edge Ring Indicator. */
185	# define UART_REG_MSR_TERI RT_BIT(2)
186	/** Delta Data Carrier Detect. */
187	# define UART_REG_MSR_DDCD RT_BIT(3)
188	/** Clear to Send. */
189	# define UART_REG_MSR_CTS RT_BIT(4)
190	/** Data Set Ready. */
191	# define UART_REG_MSR_DSR RT_BIT(5)
192	/** Ring Indicator. */
193	# define UART_REG_MSR_RI RT_BIT(6)
194	/** Data Carrier Detect. */
195	# define UART_REG_MSR_DCD RT_BIT(7)
196	/** The bits to check in this register when checking for the MS interrupt. */
197	# define UART_REG_MSR_BITS_IIR_MS 0x0f
198
199	/** The SCR register index (from the base of the port range). */
200	#define UART_REG_SCR_INDEX 7
201
202	/** Set the specified bits in the given register. */
203	#define UART_REG_SET(a_Reg, a_Set) ((a_Reg) \|= (a_Set))
204	/** Clear the specified bits in the given register. */
205	#define UART_REG_CLR(a_Reg, a_Clr) ((a_Reg) &= ~(a_Clr))
206
207
208	/*********************************************************************************************************************************
209	* Structures and Typedefs *
210	*********************************************************************************************************************************/
211
212	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
213
214
215	/*********************************************************************************************************************************
216	* Global Variables *
217	*********************************************************************************************************************************/
218
219	#ifdef IN_RING3
220	/**
221	* FIFO ITL levels.
222	*/
223	static struct
224	{
225	/** ITL level for a 16byte FIFO. */
226	uint8_t cbItl16;
227	/** ITL level for a 64byte FIFO. */
228	uint8_t cbItl64;
229	} s_aFifoItl[] =
230	{
231	/* cbItl16 cbItl64 */
232	{ 1, 1 },
233	{ 4, 16 },
234	{ 8, 32 },
235	{ 14, 56 }
236	};
237
238
239	/**
240	* String versions of the parity enum.
241	*/
242	static const char *s_aszParity[] =
243	{
244	"INVALID",
245	"NONE",
246	"EVEN",
247	"ODD",
248	"MARK",
249	"SPACE",
250	"INVALID"
251	};
252
253
254	/**
255	* String versions of the stop bits enum.
256	*/
257	static const char *s_aszStopBits[] =
258	{
259	"INVALID",
260	"1",
261	"1.5",
262	"2",
263	"INVALID"
264	};
265	#endif
266
267
268	/*********************************************************************************************************************************
269	* Internal Functions *
270	*********************************************************************************************************************************/
271
272
273	/**
274	* Updates the IRQ state based on the current device state.
275	*
276	* @returns nothing.
277	* @param pThis The UART core instance.
278	*/
279	static void uartIrqUpdate(PUARTCORE pThis)
280	{
281	LogFlowFunc(("pThis=%#p\n", pThis));
282
283	/*
284	* The interrupt uses a priority scheme, only the interrupt with the
285	* highest priority is indicated in the interrupt identification register.
286	*
287	* The priorities are as follows (high to low):
288	* * Receiver line status
289	* * Received data available
290	* * Character timeout indication (only in FIFO mode).
291	* * Transmitter holding register empty
292	* * Modem status change.
293	*/
294	uint8_t uRegIirNew = UART_REG_IIR_IP_NO_INT;
295	if ( (pThis->uRegLsr & UART_REG_LSR_BITS_IIR_RCL)
296	&& (pThis->uRegIer & UART_REG_IER_ELSI))
297	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_RCL);
298	else if ( (pThis->uRegIer & UART_REG_IER_ERBFI)
299	&& pThis->fIrqCtiPending)
300	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_CTI);
301	else if ( (pThis->uRegLsr & UART_REG_LSR_DR)
302	&& (pThis->uRegIer & UART_REG_IER_ERBFI)
303	&& ( !(pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
304	\|\| pThis->FifoRecv.cbUsed >= pThis->FifoRecv.cbItl))
305	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_RDA);
306	else if ( (pThis->uRegIer & UART_REG_IER_ETBEI)
307	&& pThis->fThreEmptyPending)
308	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_THRE);
309	else if ( (pThis->uRegMsr & UART_REG_MSR_BITS_IIR_MS)
310	&& (pThis->uRegIer & UART_REG_IER_EDSSI))
311	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_MS);
312
313	LogFlowFunc((" uRegIirNew=%#x uRegIir=%#x\n", uRegIirNew, pThis->uRegIir));
314
315	/* Change interrupt only if the interrupt status really changed from the previous value. */
316	if (uRegIirNew != (pThis->uRegIir & UART_REG_IIR_CHANGED_MASK))
317	{
318	LogFlow((" Interrupt source changed from %#x -> %#x (IRQ %d -> %d)\n",
319	pThis->uRegIir, uRegIirNew,
320	pThis->uRegIir == UART_REG_IIR_IP_NO_INT ? 0 : 1,
321	uRegIirNew == UART_REG_IIR_IP_NO_INT ? 0 : 1));
322	if (uRegIirNew == UART_REG_IIR_IP_NO_INT)
323	pThis->CTX_SUFF(pfnUartIrqReq)(pThis->CTX_SUFF(pDevIns), pThis, pThis->iLUN, 0);
324	else
325	pThis->CTX_SUFF(pfnUartIrqReq)(pThis->CTX_SUFF(pDevIns), pThis, pThis->iLUN, 1);
326	}
327	else
328	LogFlow((" No change in interrupt source\n"));
329
330	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
331	uRegIirNew \|= UART_REG_IIR_FIFOS_EN;
332	if (pThis->uRegFcr & UART_REG_FCR_64BYTE_FIFO_EN)
333	uRegIirNew \|= UART_REG_IIR_64BYTE_FIFOS_EN;
334
335	pThis->uRegIir = uRegIirNew;
336	}
337
338
339	/**
340	* Returns the amount of bytes stored in the given FIFO.
341	*
342	* @returns Amount of bytes stored in the FIFO.
343	* @param pFifo The FIFO.
344	*/
345	DECLINLINE(size_t) uartFifoUsedGet(PUARTFIFO pFifo)
346	{
347	return pFifo->cbUsed;
348	}
349
350
351	/**
352	* Puts a new character into the given FIFO.
353	*
354	* @returns Flag whether the FIFO overflowed.
355	* @param pFifo The FIFO to put the data into.
356	* @param fOvrWr Flag whether to overwrite data if the FIFO is full.
357	* @param bData The data to add.
358	*/
359	DECLINLINE(bool) uartFifoPut(PUARTFIFO pFifo, bool fOvrWr, uint8_t bData)
360	{
361	if (fOvrWr \|\| pFifo->cbUsed < pFifo->cbMax)
362	{
363	pFifo->abBuf[pFifo->offWrite] = bData;
364	pFifo->offWrite = (pFifo->offWrite + 1) % pFifo->cbMax;
365	}
366
367	bool fOverFlow = false;
368	if (pFifo->cbUsed < pFifo->cbMax)
369	pFifo->cbUsed++;
370	else
371	{
372	fOverFlow = true;
373	if (fOvrWr) /* Advance the read position to account for the lost character. */
374	pFifo->offRead = (pFifo->offRead + 1) % pFifo->cbMax;
375	}
376
377	return fOverFlow;
378	}
379
380
381	/**
382	* Returns the next character in the FIFO.
383	*
384	* @return Next byte in the FIFO.
385	* @param pFifo The FIFO to get data from.
386	*/
387	DECLINLINE(uint8_t) uartFifoGet(PUARTFIFO pFifo)
388	{
389	uint8_t bRet = 0;
390
391	if (pFifo->cbUsed)
392	{
393	bRet = pFifo->abBuf[pFifo->offRead];
394	pFifo->offRead = (pFifo->offRead + 1) % pFifo->cbMax;
395	pFifo->cbUsed--;
396	}
397
398	return bRet;
399	}
400
401
402	#ifdef IN_RING3
403	/**
404	* Clears the given FIFO.
405	*
406	* @returns nothing.
407	* @param pFifo The FIFO to clear.
408	*/
409	DECLINLINE(void) uartFifoClear(PUARTFIFO pFifo)
410	{
411	memset(&pFifo->abBuf[0], 0, sizeof(pFifo->abBuf));
412	pFifo->cbUsed = 0;
413	pFifo->offWrite = 0;
414	pFifo->offRead = 0;
415	}
416
417
418	/**
419	* Returns the amount of free bytes in the given FIFO.
420	*
421	* @returns The amount of bytes free in the given FIFO.
422	* @param pFifo The FIFO.
423	*/
424	DECLINLINE(size_t) uartFifoFreeGet(PUARTFIFO pFifo)
425	{
426	return pFifo->cbMax - pFifo->cbUsed;
427	}
428
429
430	/**
431	* Tries to copy the requested amount of data from the given FIFO into the provided buffer.
432	*
433	* @returns Amount of bytes actually copied.
434	* @param pFifo The FIFO to copy data from.
435	* @param pvDst Where to copy the data to.
436	* @param cbCopy How much to copy.
437	*/
438	DECLINLINE(size_t) uartFifoCopyTo(PUARTFIFO pFifo, void *pvDst, size_t cbCopy)
439	{
440	size_t cbCopied = 0;
441	uint8_t pbDst = (uint8_t )pvDst;
442
443	cbCopy = RT_MIN(cbCopy, pFifo->cbUsed);
444	while (cbCopy)
445	{
446	uint8_t cbThisCopy = (uint8_t)RT_MIN(cbCopy, (uint8_t)(pFifo->cbMax - pFifo->offRead));
447	memcpy(pbDst, &pFifo->abBuf[pFifo->offRead], cbThisCopy);
448
449	pFifo->offRead = (pFifo->offRead + cbThisCopy) % pFifo->cbMax;
450	pFifo->cbUsed -= cbThisCopy;
451	pbDst += cbThisCopy;
452	cbCopied += cbThisCopy;
453	cbCopy -= cbThisCopy;
454	}
455
456	return cbCopied;
457	}
458
459
460	#if 0 /* unused */
461	/**
462	* Tries to copy the requested amount of data from the provided buffer into the given FIFO.
463	*
464	* @returns Amount of bytes actually copied.
465	* @param pFifo The FIFO to copy data to.
466	* @param pvSrc Where to copy the data from.
467	* @param cbCopy How much to copy.
468	*/
469	DECLINLINE(size_t) uartFifoCopyFrom(PUARTFIFO pFifo, void *pvSrc, size_t cbCopy)
470	{
471	size_t cbCopied = 0;
472	uint8_t pbSrc = (uint8_t )pvSrc;
473
474	cbCopy = RT_MIN(cbCopy, uartFifoFreeGet(pFifo));
475	while (cbCopy)
476	{
477	uint8_t cbThisCopy = (uint8_t)RT_MIN(cbCopy, (uint8_t)(pFifo->cbMax - pFifo->offWrite));
478	memcpy(&pFifo->abBuf[pFifo->offWrite], pbSrc, cbThisCopy);
479
480	pFifo->offWrite = (pFifo->offWrite + cbThisCopy) % pFifo->cbMax;
481	pFifo->cbUsed += cbThisCopy;
482	pbSrc += cbThisCopy;
483	cbCopied += cbThisCopy;
484	cbCopy -= cbThisCopy;
485	}
486
487	return cbCopied;
488	}
489	#endif
490
491
492	/**
493	* Updates the delta bits for the given MSR register value which has the status line
494	* bits set.
495	*
496	* @returns nothing.
497	* @param pThis The serial port instance.
498	* @param uMsrSts MSR value with the appropriate status bits set.
499	*/
500	static void uartR3MsrUpdate(PUARTCORE pThis, uint8_t uMsrSts)
501	{
502	/* Compare current and new states and set remaining bits accordingly. */
503	if ((uMsrSts & UART_REG_MSR_CTS) != (pThis->uRegMsr & UART_REG_MSR_CTS))
504	uMsrSts \|= UART_REG_MSR_DCTS;
505	if ((uMsrSts & UART_REG_MSR_DSR) != (pThis->uRegMsr & UART_REG_MSR_DSR))
506	uMsrSts \|= UART_REG_MSR_DDSR;
507	if ((uMsrSts & UART_REG_MSR_RI) != 0 && (pThis->uRegMsr & UART_REG_MSR_RI) == 0)
508	uMsrSts \|= UART_REG_MSR_TERI;
509	if ((uMsrSts & UART_REG_MSR_DCD) != (pThis->uRegMsr & UART_REG_MSR_DCD))
510	uMsrSts \|= UART_REG_MSR_DDCD;
511
512	pThis->uRegMsr = uMsrSts;
513
514	uartIrqUpdate(pThis);
515	}
516
517
518	/**
519	* Updates the serial port parameters of the attached driver with the current configuration.
520	*
521	* @returns nothing.
522	* @param pThis The serial port instance.
523	*/
524	static void uartR3ParamsUpdate(PUARTCORE pThis)
525	{
526	if ( pThis->uRegDivisor != 0
527	&& pThis->pDrvSerial)
528	{
529	uint32_t uBps = 115200 / pThis->uRegDivisor; /* This is for PC compatible serial port with a 1.8432 MHz crystal. */
530	unsigned cDataBits = UART_REG_LCR_WLS_GET(pThis->uRegLcr) + 5;
531	uint32_t cFrameBits = cDataBits;
532	PDMSERIALSTOPBITS enmStopBits = PDMSERIALSTOPBITS_ONE;
533	PDMSERIALPARITY enmParity = PDMSERIALPARITY_NONE;
534
535	if (pThis->uRegLcr & UART_REG_LCR_STB)
536	{
537	enmStopBits = cDataBits == 5 ? PDMSERIALSTOPBITS_ONEPOINTFIVE : PDMSERIALSTOPBITS_TWO;
538	cFrameBits += 2;
539	}
540	else
541	cFrameBits++;
542
543	if (pThis->uRegLcr & UART_REG_LCR_PEN)
544	{
545	/* Select the correct parity mode based on the even and stick parity bits. */
546	switch (pThis->uRegLcr & (UART_REG_LCR_EPS \| UART_REG_LCR_PAR_STICK))
547	{
548	case 0:
549	enmParity = PDMSERIALPARITY_ODD;
550	break;
551	case UART_REG_LCR_EPS:
552	enmParity = PDMSERIALPARITY_EVEN;
553	break;
554	case UART_REG_LCR_EPS \| UART_REG_LCR_PAR_STICK:
555	enmParity = PDMSERIALPARITY_SPACE;
556	break;
557	case UART_REG_LCR_PAR_STICK:
558	enmParity = PDMSERIALPARITY_MARK;
559	break;
560	default:
561	/* We should never get here as all cases where caught earlier. */
562	AssertMsgFailed(("This shouldn't happen at all: %#x\n",
563	pThis->uRegLcr & (UART_REG_LCR_EPS \| UART_REG_LCR_PAR_STICK)));
564	}
565
566	cFrameBits++;
567	}
568
569	uint64_t uTimerFreq = TMTimerGetFreq(pThis->CTX_SUFF(pTimerRcvFifoTimeout));
570	pThis->cSymbolXferTicks = (uTimerFreq / uBps) * cFrameBits;
571
572	LogFlowFunc(("Changing parameters to: %u,%s,%u,%s\n",
573	uBps, s_aszParity[enmParity], cDataBits, s_aszStopBits[enmStopBits]));
574
575	int rc = pThis->pDrvSerial->pfnChgParams(pThis->pDrvSerial, uBps, enmParity, cDataBits, enmStopBits);
576	if (RT_FAILURE(rc))
577	LogRelMax(10, ("Serial#%d: Failed to change parameters to %u,%s,%u,%s -> %Rrc\n",
578	pThis->pDevInsR3->iInstance, uBps, s_aszParity[enmParity], cDataBits, s_aszStopBits[enmStopBits], rc));
579
580	/* Changed parameters will flush all receive queues, so there won't be any data to read even if indicated. */
581	pThis->pDrvSerial->pfnQueuesFlush(pThis->pDrvSerial, true /fQueueRecv/, false /fQueueXmit/);
582	ASMAtomicWriteU32(&pThis->cbAvailRdr, 0);
583	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
584	}
585	}
586
587
588	/**
589	* Updates the internal device state with the given PDM status line states.
590	*
591	* @returns nothing.
592	* @param pThis The serial port instance.
593	* @param fStsLines The PDM status line states.
594	*/
595	static void uartR3StsLinesUpdate(PUARTCORE pThis, uint32_t fStsLines)
596	{
597	uint8_t uRegMsrNew = 0; /* The new MSR value. */
598
599	if (fStsLines & PDMISERIALPORT_STS_LINE_DCD)
600	uRegMsrNew \|= UART_REG_MSR_DCD;
601	if (fStsLines & PDMISERIALPORT_STS_LINE_RI)
602	uRegMsrNew \|= UART_REG_MSR_RI;
603	if (fStsLines & PDMISERIALPORT_STS_LINE_DSR)
604	uRegMsrNew \|= UART_REG_MSR_DSR;
605	if (fStsLines & PDMISERIALPORT_STS_LINE_CTS)
606	uRegMsrNew \|= UART_REG_MSR_CTS;
607
608	uartR3MsrUpdate(pThis, uRegMsrNew);
609	}
610
611
612	/**
613	* Fills up the receive FIFO with as much data as possible.
614	*
615	* @returns nothing.
616	* @param pThis The serial port instance.
617	*/
618	static void uartR3RecvFifoFill(PUARTCORE pThis)
619	{
620	LogFlowFunc(("pThis=%#p\n", pThis));
621
622	PUARTFIFO pFifo = &pThis->FifoRecv;
623	size_t cbFill = RT_MIN(uartFifoFreeGet(pFifo),
624	ASMAtomicReadU32(&pThis->cbAvailRdr));
625	size_t cbFilled = 0;
626
627	while (cbFilled < cbFill)
628	{
629	size_t cbThisRead = cbFill - cbFilled;
630
631	if (pFifo->offRead <= pFifo->offWrite)
632	cbThisRead = RT_MIN(cbThisRead, (uint8_t)(pFifo->cbMax - pFifo->offWrite));
633	else
634	cbThisRead = RT_MIN(cbThisRead, (uint8_t)(pFifo->offRead - pFifo->offWrite));
635
636	size_t cbRead = 0;
637	int rc = pThis->pDrvSerial->pfnReadRdr(pThis->pDrvSerial, &pFifo->abBuf[pFifo->offWrite], cbThisRead, &cbRead);
638	AssertRC(rc); Assert(cbRead <= UINT8_MAX); RT_NOREF(rc);
639
640	pFifo->offWrite = (pFifo->offWrite + (uint8_t)cbRead) % pFifo->cbMax;
641	pFifo->cbUsed += (uint8_t)cbRead;
642	cbFilled += cbRead;
643
644	if (cbRead < cbThisRead)
645	break;
646	}
647
648	if (cbFilled)
649	{
650	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
651	if (pFifo->cbUsed < pFifo->cbItl)
652	{
653	pThis->fIrqCtiPending = false;
654	TMTimerSetRelative(pThis->CTX_SUFF(pTimerRcvFifoTimeout), pThis->cSymbolXferTicks * 4, NULL);
655	}
656	uartIrqUpdate(pThis);
657	}
658
659	Assert(cbFilled <= (size_t)pThis->cbAvailRdr);
660	ASMAtomicSubU32(&pThis->cbAvailRdr, (uint32_t)cbFilled);
661	}
662
663
664	/**
665	* Fetches a single byte and writes it to RBR.
666	*
667	* @returns nothing.
668	* @param pThis The serial port instance.
669	*/
670	static void uartR3ByteFetch(PUARTCORE pThis)
671	{
672	if (ASMAtomicReadU32(&pThis->cbAvailRdr))
673	{
674	size_t cbRead = 0;
675	int rc2 = pThis->pDrvSerial->pfnReadRdr(pThis->pDrvSerial, &pThis->uRegRbr, 1, &cbRead);
676	AssertMsg(RT_SUCCESS(rc2) && cbRead == 1, ("This shouldn't fail and always return one byte!\n")); RT_NOREF(rc2);
677	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
678	uartIrqUpdate(pThis);
679	}
680	}
681
682
683	/**
684	* Fetches a ready data based on the FIFO setting.
685	*
686	* @returns nothing.
687	* @param pThis The serial port instance.
688	*/
689	static void uartR3DataFetch(PUARTCORE pThis)
690	{
691	AssertPtrReturnVoid(pThis->pDrvSerial);
692
693	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
694	uartR3RecvFifoFill(pThis);
695	else
696	uartR3ByteFetch(pThis);
697	}
698
699
700	/**
701	* Reset the transmit/receive related bits to the standard values
702	* (after a detach/attach/reset event).
703	*
704	* @returns nothing.
705	* @param pThis The serial port instance.
706	*/
707	static void uartR3XferReset(PUARTCORE pThis)
708	{
709	TMTimerStop(pThis->CTX_SUFF(pTimerRcvFifoTimeout));
710	TMTimerStop(pThis->CTX_SUFF(pTimerTxUnconnected));
711	pThis->uRegLsr = UART_REG_LSR_THRE \| UART_REG_LSR_TEMT;
712	pThis->fThreEmptyPending = false;
713
714	uartFifoClear(&pThis->FifoXmit);
715	uartFifoClear(&pThis->FifoRecv);
716	uartR3ParamsUpdate(pThis);
717	uartIrqUpdate(pThis);
718
719	if (pThis->pDrvSerial)
720	{
721	/* Set the modem lines to reflect the current state. */
722	int rc = pThis->pDrvSerial->pfnChgModemLines(pThis->pDrvSerial, false /fRts/, false /fDtr/);
723	if (RT_FAILURE(rc))
724	LogRel(("Serial#%d: Failed to set modem lines with %Rrc during reset\n",
725	pThis->pDevInsR3->iInstance, rc));
726
727	uint32_t fStsLines = 0;
728	rc = pThis->pDrvSerial->pfnQueryStsLines(pThis->pDrvSerial, &fStsLines);
729	if (RT_SUCCESS(rc))
730	uartR3StsLinesUpdate(pThis, fStsLines);
731	else
732	LogRel(("Serial#%d: Failed to query status line status with %Rrc during reset\n",
733	pThis->pDevInsR3->iInstance, rc));
734	}
735
736	}
737
738
739	/**
740	* Tries to copy the specified amount of data from the active TX queue (register or FIFO).
741	*
742	* @returns nothing.
743	* @param pThis The serial port instance.
744	* @param pvBuf Where to store the data.
745	* @param cbRead How much to read from the TX queue.
746	* @param pcbRead Where to store the amount of data read.
747	*/
748	static void uartR3TxQueueCopyFrom(PUARTCORE pThis, void pvBuf, size_t cbRead, size_t pcbRead)
749	{
750	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
751	{
752	*pcbRead = uartFifoCopyTo(&pThis->FifoXmit, pvBuf, cbRead);
753	if (!pThis->FifoXmit.cbUsed)
754	{
755	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_THRE);
756	pThis->fThreEmptyPending = true;
757	}
758	if (*pcbRead)
759	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_TEMT);
760	uartIrqUpdate(pThis);
761	}
762	else if (!(pThis->uRegLsr & UART_REG_LSR_THRE))
763	{
764	(uint8_t )pvBuf = pThis->uRegThr;
765	*pcbRead = 1;
766	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_THRE);
767	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_TEMT);
768	pThis->fThreEmptyPending = true;
769	uartIrqUpdate(pThis);
770	}
771	else
772	{
773	/*
774	* This can happen if there was data in the FIFO when the connection was closed,
775	* indicate this condition to the lower driver by returning 0 bytes.
776	*/
777	*pcbRead = 0;
778	}
779	}
780	#endif
781
782
783	/**
784	* Transmits the given byte.
785	*
786	* @returns VBox status code.
787	* @param pThis The serial port instance.
788	* @param bVal Byte to transmit.
789	*/
790	static int uartXmit(PUARTCORE pThis, uint8_t bVal)
791	{
792	int rc = VINF_SUCCESS;
793
794	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
795	{
796	#ifndef IN_RING3
797	if (!uartFifoUsedGet(&pThis->FifoXmit))
798	rc = VINF_IOM_R3_IOPORT_WRITE;
799	else
800	{
801	uartFifoPut(&pThis->FifoXmit, true /fOvrWr/, bVal);
802	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE \| UART_REG_LSR_TEMT);
803	}
804	#else
805	uartFifoPut(&pThis->FifoXmit, true /fOvrWr/, bVal);
806	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE \| UART_REG_LSR_TEMT);
807	pThis->fThreEmptyPending = false;
808	uartIrqUpdate(pThis);
809	if (uartFifoUsedGet(&pThis->FifoXmit) == 1)
810	{
811	if ( pThis->pDrvSerial
812	&& !(pThis->uRegMcr & UART_REG_MCR_LOOP))
813	{
814	int rc2 = pThis->pDrvSerial->pfnDataAvailWrNotify(pThis->pDrvSerial);
815	if (RT_FAILURE(rc2))
816	LogRelMax(10, ("Serial#%d: Failed to send data with %Rrc\n", pThis->pDevInsR3->iInstance, rc2));
817	}
818	else
819	TMTimerSetRelative(pThis->CTX_SUFF(pTimerTxUnconnected), pThis->cSymbolXferTicks, NULL);
820	}
821	#endif
822	}
823	else
824	{
825	/* Notify the lower driver about available data only if the register was empty before. */
826	if (pThis->uRegLsr & UART_REG_LSR_THRE)
827	{
828	#ifndef IN_RING3
829	rc = VINF_IOM_R3_IOPORT_WRITE;
830	#else
831	pThis->uRegThr = bVal;
832	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE \| UART_REG_LSR_TEMT);
833	pThis->fThreEmptyPending = false;
834	uartIrqUpdate(pThis);
835	if ( pThis->pDrvSerial
836	&& !(pThis->uRegMcr & UART_REG_MCR_LOOP))
837	{
838	int rc2 = pThis->pDrvSerial->pfnDataAvailWrNotify(pThis->pDrvSerial);
839	if (RT_FAILURE(rc2))
840	LogRelMax(10, ("Serial#%d: Failed to send data with %Rrc\n", pThis->pDevInsR3->iInstance, rc2));
841	}
842	else
843	TMTimerSetRelative(pThis->CTX_SUFF(pTimerTxUnconnected), pThis->cSymbolXferTicks, NULL);
844	#endif
845	}
846	else
847	pThis->uRegThr = bVal;
848	}
849
850	return rc;
851	}
852
853
854	/**
855	* Write handler for the THR/DLL register (depending on the DLAB bit in LCR).
856	*
857	* @returns VBox status code.
858	* @param pThis The serial port instance.
859	* @param uVal The value to write.
860	*/
861	DECLINLINE(int) uartRegThrDllWrite(PUARTCORE pThis, uint8_t uVal)
862	{
863	int rc = VINF_SUCCESS;
864
865	/* A set DLAB causes a write to the lower 8bits of the divisor latch. */
866	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
867	{
868	if (uVal != (pThis->uRegDivisor & 0xff))
869	{
870	#ifndef IN_RING3
871	rc = VINF_IOM_R3_IOPORT_WRITE;
872	#else
873	pThis->uRegDivisor = (pThis->uRegDivisor & 0xff00) \| uVal;
874	uartR3ParamsUpdate(pThis);
875	#endif
876	}
877	}
878	else
879	rc = uartXmit(pThis, uVal);
880
881	return rc;
882	}
883
884
885	/**
886	* Write handler for the IER/DLM register (depending on the DLAB bit in LCR).
887	*
888	* @returns VBox status code.
889	* @param pThis The serial port instance.
890	* @param uVal The value to write.
891	*/
892	DECLINLINE(int) uartRegIerDlmWrite(PUARTCORE pThis, uint8_t uVal)
893	{
894	int rc = VINF_SUCCESS;
895
896	/* A set DLAB causes a write to the higher 8bits of the divisor latch. */
897	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
898	{
899	if (uVal != (pThis->uRegDivisor & 0xff00) >> 8)
900	{
901	#ifndef IN_RING3
902	rc = VINF_IOM_R3_IOPORT_WRITE;
903	#else
904	pThis->uRegDivisor = (pThis->uRegDivisor & 0xff) \| (uVal << 8);
905	uartR3ParamsUpdate(pThis);
906	#endif
907	}
908	}
909	else
910	{
911	if (pThis->enmType < UARTTYPE_16750)
912	pThis->uRegIer = uVal & UART_REG_IER_MASK_WR;
913	else
914	pThis->uRegIer = uVal & UART_REG_IER_MASK_WR_16750;
915
916	if (pThis->uRegLsr & UART_REG_LSR_THRE)
917	pThis->fThreEmptyPending = true;
918
919	uartIrqUpdate(pThis);
920	}
921
922	return rc;
923	}
924
925
926	/**
927	* Write handler for the FCR register.
928	*
929	* @returns VBox status code.
930	* @param pThis The serial port instance.
931	* @param uVal The value to write.
932	*/
933	DECLINLINE(int) uartRegFcrWrite(PUARTCORE pThis, uint8_t uVal)
934	{
935	#ifndef IN_RING3
936	RT_NOREF(pThis, uVal);
937	return VINF_IOM_R3_IOPORT_WRITE;
938	#else
939	int rc = VINF_SUCCESS;
940	if ( pThis->enmType >= UARTTYPE_16550A
941	&& uVal != pThis->uRegFcr)
942	{
943	/* A change in the FIFO enable bit clears both FIFOs automatically. */
944	if ((uVal ^ pThis->uRegFcr) & UART_REG_FCR_FIFO_EN)
945	{
946	uartFifoClear(&pThis->FifoXmit);
947	uartFifoClear(&pThis->FifoRecv);
948
949	/*
950	* If the FIFO is about to be enabled and the DR bit is ready we have an unacknowledged
951	* byte in the RBR register which will be lost so we have to adjust the available bytes.
952	*/
953	if ( ASMAtomicReadU32(&pThis->cbAvailRdr) > 0
954	&& (uVal & UART_REG_FCR_FIFO_EN))
955	ASMAtomicDecU32(&pThis->cbAvailRdr);
956
957	/* Clear the DR bit too. */
958	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
959	}
960
961	if (rc == VINF_SUCCESS)
962	{
963	if (uVal & UART_REG_FCR_RCV_FIFO_RST)
964	{
965	TMTimerStop(pThis->CTX_SUFF(pTimerRcvFifoTimeout));
966	pThis->fIrqCtiPending = false;
967	uartFifoClear(&pThis->FifoRecv);
968	}
969	if (uVal & UART_REG_FCR_XMIT_FIFO_RST)
970	uartFifoClear(&pThis->FifoXmit);
971
972	/*
973	* The 64byte FIFO enable bit is only changeable for 16750
974	* and if the DLAB bit in LCR is set.
975	*/
976	if ( pThis->enmType < UARTTYPE_16750
977	\|\| !(pThis->uRegLcr & UART_REG_LCR_DLAB))
978	uVal &= ~UART_REG_FCR_64BYTE_FIFO_EN;
979	else /* Use previous value. */
980	uVal \|= pThis->uRegFcr & UART_REG_FCR_64BYTE_FIFO_EN;
981
982	if (uVal & UART_REG_FCR_64BYTE_FIFO_EN)
983	{
984	pThis->FifoRecv.cbMax = 64;
985	pThis->FifoXmit.cbMax = 64;
986	}
987	else
988	{
989	pThis->FifoRecv.cbMax = 16;
990	pThis->FifoXmit.cbMax = 16;
991	}
992
993	if (uVal & UART_REG_FCR_FIFO_EN)
994	{
995	uint8_t idxItl = UART_REG_FCR_RCV_LVL_IRQ_GET(uVal);
996	if (uVal & UART_REG_FCR_64BYTE_FIFO_EN)
997	pThis->FifoRecv.cbItl = s_aFifoItl[idxItl].cbItl64;
998	else
999	pThis->FifoRecv.cbItl = s_aFifoItl[idxItl].cbItl16;
1000	}
1001
1002	/* The FIFO reset bits are self clearing. */
1003	pThis->uRegFcr = uVal & UART_REG_FCR_MASK_STICKY;
1004	uartIrqUpdate(pThis);
1005	}
1006
1007	/* Fill in the next data. */
1008	if (ASMAtomicReadU32(&pThis->cbAvailRdr))
1009	uartR3DataFetch(pThis);
1010	}
1011
1012	return rc;
1013	#endif
1014	}
1015
1016
1017	/**
1018	* Write handler for the LCR register.
1019	*
1020	* @returns VBox status code.
1021	* @param pThis The serial port instance.
1022	* @param uVal The value to write.
1023	*/
1024	DECLINLINE(int) uartRegLcrWrite(PUARTCORE pThis, uint8_t uVal)
1025	{
1026	int rc = VINF_SUCCESS;
1027
1028	/* Any change except the DLAB bit causes a switch to R3. */
1029	if ((pThis->uRegLcr & ~UART_REG_LCR_DLAB) != (uVal & ~UART_REG_LCR_DLAB))
1030	{
1031	#ifndef IN_RING3
1032	rc = VINF_IOM_R3_IOPORT_WRITE;
1033	#else
1034	/* Check whether the BREAK bit changed before updating the LCR value. */
1035	bool fBrkEn = RT_BOOL(uVal & UART_REG_LCR_BRK_SET);
1036	bool fBrkChg = fBrkEn != RT_BOOL(pThis->uRegLcr & UART_REG_LCR_BRK_SET);
1037	pThis->uRegLcr = uVal;
1038	uartR3ParamsUpdate(pThis);
1039
1040	if ( fBrkChg
1041	&& pThis->pDrvSerial)
1042	pThis->pDrvSerial->pfnChgBrk(pThis->pDrvSerial, fBrkEn);
1043	#endif
1044	}
1045	else
1046	pThis->uRegLcr = uVal;
1047
1048	return rc;
1049	}
1050
1051
1052	/**
1053	* Write handler for the MCR register.
1054	*
1055	* @returns VBox status code.
1056	* @param pThis The serial port instance.
1057	* @param uVal The value to write.
1058	*/
1059	DECLINLINE(int) uartRegMcrWrite(PUARTCORE pThis, uint8_t uVal)
1060	{
1061	int rc = VINF_SUCCESS;
1062
1063	if (pThis->enmType < UARTTYPE_16750)
1064	uVal &= UART_REG_MCR_MASK_WR;
1065	else
1066	uVal &= UART_REG_MCR_MASK_WR_15750;
1067	if (pThis->uRegMcr != uVal)
1068	{
1069	#ifndef IN_RING3
1070	rc = VINF_IOM_R3_IOPORT_WRITE;
1071	#else
1072	/*
1073	* When loopback mode is activated the RTS, DTR, OUT1 and OUT2 lines are
1074	* disconnected and looped back to MSR.
1075	*/
1076	if ( (uVal & UART_REG_MCR_LOOP)
1077	&& !(pThis->uRegMcr & UART_REG_MCR_LOOP)
1078	&& pThis->pDrvSerial)
1079	pThis->pDrvSerial->pfnChgModemLines(pThis->pDrvSerial, false /fRts/, false /fDtr/);
1080
1081	pThis->uRegMcr = uVal;
1082	if (uVal & UART_REG_MCR_LOOP)
1083	{
1084	uint8_t uRegMsrSts = 0;
1085
1086	if (uVal & UART_REG_MCR_RTS)
1087	uRegMsrSts \|= UART_REG_MSR_CTS;
1088	if (uVal & UART_REG_MCR_DTR)
1089	uRegMsrSts \|= UART_REG_MSR_DSR;
1090	if (uVal & UART_REG_MCR_OUT1)
1091	uRegMsrSts \|= UART_REG_MSR_RI;
1092	if (uVal & UART_REG_MCR_OUT2)
1093	uRegMsrSts \|= UART_REG_MSR_DCD;
1094	uartR3MsrUpdate(pThis, uRegMsrSts);
1095	}
1096	else if (pThis->pDrvSerial)
1097	pThis->pDrvSerial->pfnChgModemLines(pThis->pDrvSerial,
1098	RT_BOOL(uVal & UART_REG_MCR_RTS),
1099	RT_BOOL(uVal & UART_REG_MCR_DTR));
1100	#endif
1101	}
1102
1103	return rc;
1104	}
1105
1106
1107	/**
1108	* Read handler for the RBR/DLL register (depending on the DLAB bit in LCR).
1109	*
1110	* @returns VBox status code.
1111	* @param pThis The serial port instance.
1112	* @param puVal Where to store the read value on success.
1113	*/
1114	DECLINLINE(int) uartRegRbrDllRead(PUARTCORE pThis, uint32_t *puVal)
1115	{
1116	int rc = VINF_SUCCESS;
1117
1118	/* A set DLAB causes a read from the lower 8bits of the divisor latch. */
1119	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1120	*puVal = pThis->uRegDivisor & 0xff;
1121	else
1122	{
1123	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
1124	{
1125	/*
1126	* Only go back to R3 if there is new data available for the FIFO
1127	* and we would clear the interrupt to fill it up again.
1128	*/
1129	if ( pThis->FifoRecv.cbUsed <= pThis->FifoRecv.cbItl
1130	&& ASMAtomicReadU32(&pThis->cbAvailRdr) > 0)
1131	{
1132	#ifndef IN_RING3
1133	rc = VINF_IOM_R3_IOPORT_READ;
1134	#else
1135	uartR3RecvFifoFill(pThis);
1136	#endif
1137	}
1138
1139	if (rc == VINF_SUCCESS)
1140	{
1141	*puVal = uartFifoGet(&pThis->FifoRecv);
1142	pThis->fIrqCtiPending = false;
1143	if (!pThis->FifoRecv.cbUsed)
1144	{
1145	TMTimerStop(pThis->CTX_SUFF(pTimerRcvFifoTimeout));
1146	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
1147	}
1148	else if (pThis->FifoRecv.cbUsed < pThis->FifoRecv.cbItl)
1149	TMTimerSetRelative(pThis->CTX_SUFF(pTimerRcvFifoTimeout), pThis->cSymbolXferTicks * 4, NULL);
1150	uartIrqUpdate(pThis);
1151	}
1152	}
1153	else
1154	{
1155	*puVal = pThis->uRegRbr;
1156
1157	if (pThis->uRegLsr & UART_REG_LSR_DR)
1158	{
1159	Assert(pThis->cbAvailRdr);
1160	uint32_t cbAvail = ASMAtomicDecU32(&pThis->cbAvailRdr);
1161	if (!cbAvail)
1162	{
1163	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
1164	uartIrqUpdate(pThis);
1165	}
1166	else
1167	{
1168	#ifndef IN_RING3
1169	/* Restore state and go back to R3. */
1170	ASMAtomicIncU32(&pThis->cbAvailRdr);
1171	rc = VINF_IOM_R3_IOPORT_READ;
1172	#else
1173	/* Fetch new data and keep the DR bit set. */
1174	uartR3DataFetch(pThis);
1175	#endif
1176	}
1177	}
1178	}
1179	}
1180
1181	return rc;
1182	}
1183
1184
1185	/**
1186	* Read handler for the IER/DLM register (depending on the DLAB bit in LCR).
1187	*
1188	* @returns VBox status code.
1189	* @param pThis The serial port instance.
1190	* @param puVal Where to store the read value on success.
1191	*/
1192	DECLINLINE(int) uartRegIerDlmRead(PUARTCORE pThis, uint32_t *puVal)
1193	{
1194	int rc = VINF_SUCCESS;
1195
1196	/* A set DLAB causes a read from the upper 8bits of the divisor latch. */
1197	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1198	*puVal = (pThis->uRegDivisor & 0xff00) >> 8;
1199	else
1200	*puVal = pThis->uRegIer;
1201
1202	return rc;
1203	}
1204
1205
1206	/**
1207	* Read handler for the IIR register.
1208	*
1209	* @returns VBox status code.
1210	* @param pThis The serial port instance.
1211	* @param puVal Where to store the read value on success.
1212	*/
1213	DECLINLINE(int) uartRegIirRead(PUARTCORE pThis, uint32_t *puVal)
1214	{
1215	*puVal = pThis->uRegIir;
1216	/* Reset the THRE empty interrupt id when this gets returned to the guest (see table 3 UART Reset configuration). */
1217	if (UART_REG_IIR_ID_GET(pThis->uRegIir) == UART_REG_IIR_ID_THRE)
1218	{
1219	pThis->fThreEmptyPending = false;
1220	uartIrqUpdate(pThis);
1221	}
1222	return VINF_SUCCESS;
1223	}
1224
1225
1226	/**
1227	* Read handler for the LSR register.
1228	*
1229	* @returns VBox status code.
1230	* @param pThis The serial port instance.
1231	* @param puVal Where to store the read value on success.
1232	*/
1233	DECLINLINE(int) uartRegLsrRead(PUARTCORE pThis, uint32_t *puVal)
1234	{
1235	int rc = VINF_SUCCESS;
1236
1237	/* Yield if configured and there is no data available. */
1238	if ( !(pThis->uRegLsr & UART_REG_LSR_DR)
1239	&& (pThis->fFlags & UART_CORE_YIELD_ON_LSR_READ))
1240	{
1241	#ifndef IN_RING3
1242	return VINF_IOM_R3_IOPORT_READ;
1243	#else
1244	RTThreadYield();
1245	#endif
1246	}
1247
1248	*puVal = pThis->uRegLsr;
1249	/*
1250	* Reading this register clears the Overrun (OE), Parity (PE) and Framing (FE) error
1251	* as well as the Break Interrupt (BI).
1252	*/
1253	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_BITS_IIR_RCL);
1254	uartIrqUpdate(pThis);
1255
1256	return rc;
1257	}
1258
1259
1260	/**
1261	* Read handler for the MSR register.
1262	*
1263	* @returns VBox status code.
1264	* @param pThis The serial port instance.
1265	* @param puVal Where to store the read value on success.
1266	*/
1267	DECLINLINE(int) uartRegMsrRead(PUARTCORE pThis, uint32_t *puVal)
1268	{
1269	*puVal = pThis->uRegMsr;
1270
1271	/* Clear any of the delta bits. */
1272	UART_REG_CLR(pThis->uRegMsr, UART_REG_MSR_BITS_IIR_MS);
1273	uartIrqUpdate(pThis);
1274	return VINF_SUCCESS;
1275	}
1276
1277
1278	#ifdef LOG_ENABLED
1279	/**
1280	* Converts the register index into a sensible memnonic.
1281	*
1282	* @returns Register memnonic.
1283	* @param pThis The serial port instance.
1284	* @param idxReg Register index.
1285	* @param fWrite Flag whether the register gets written.
1286	*/
1287	DECLINLINE(const char *) uartRegIdx2Str(PUARTCORE pThis, uint8_t idxReg, bool fWrite)
1288	{
1289	const char *psz = "INV";
1290
1291	switch (idxReg)
1292	{
1293	/case UART_REG_THR_DLL_INDEX:/
1294	case UART_REG_RBR_DLL_INDEX:
1295	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1296	psz = "DLL";
1297	else if (fWrite)
1298	psz = "THR";
1299	else
1300	psz = "RBR";
1301	break;
1302	case UART_REG_IER_DLM_INDEX:
1303	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1304	psz = "DLM";
1305	else
1306	psz = "IER";
1307	break;
1308	/case UART_REG_IIR_INDEX:/
1309	case UART_REG_FCR_INDEX:
1310	if (fWrite)
1311	psz = "FCR";
1312	else
1313	psz = "IIR";
1314	break;
1315	case UART_REG_LCR_INDEX:
1316	psz = "LCR";
1317	break;
1318	case UART_REG_MCR_INDEX:
1319	psz = "MCR";
1320	break;
1321	case UART_REG_LSR_INDEX:
1322	psz = "LSR";
1323	break;
1324	case UART_REG_MSR_INDEX:
1325	psz = "MSR";
1326	break;
1327	case UART_REG_SCR_INDEX:
1328	psz = "SCR";
1329	break;
1330	}
1331
1332	return psz;
1333	}
1334	#endif
1335
1336
1337	DECLHIDDEN(int) uartRegWrite(PUARTCORE pThis, uint32_t uReg, uint32_t u32, size_t cb)
1338	{
1339	AssertMsgReturn(cb == 1, ("uReg=%#x cb=%d u32=%#x\n", uReg, cb, u32), VINF_SUCCESS);
1340
1341	int rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_R3_IOPORT_WRITE);
1342	if (rc != VINF_SUCCESS)
1343	return rc;
1344
1345	uint8_t idxReg = uReg & 0x7;
1346	LogFlowFunc(("pThis=%#p uReg=%u{%s} u32=%#x cb=%u\n",
1347	pThis, uReg, uartRegIdx2Str(pThis, idxReg, true /fWrite/), u32, cb));
1348
1349	uint8_t uVal = (uint8_t)u32;
1350	switch (idxReg)
1351	{
1352	case UART_REG_THR_DLL_INDEX:
1353	rc = uartRegThrDllWrite(pThis, uVal);
1354	break;
1355	case UART_REG_IER_DLM_INDEX:
1356	rc = uartRegIerDlmWrite(pThis, uVal);
1357	break;
1358	case UART_REG_FCR_INDEX:
1359	rc = uartRegFcrWrite(pThis, uVal);
1360	break;
1361	case UART_REG_LCR_INDEX:
1362	rc = uartRegLcrWrite(pThis, uVal);
1363	break;
1364	case UART_REG_MCR_INDEX:
1365	rc = uartRegMcrWrite(pThis, uVal);
1366	break;
1367	case UART_REG_SCR_INDEX:
1368	pThis->uRegScr = u32;
1369	break;
1370	default:
1371	break;
1372	}
1373
1374	PDMCritSectLeave(&pThis->CritSect);
1375	LogFlowFunc(("-> %Rrc\n", rc));
1376	return rc;
1377	}
1378
1379
1380	DECLHIDDEN(int) uartRegRead(PUARTCORE pThis, uint32_t uReg, uint32_t *pu32, size_t cb)
1381	{
1382	if (cb != 1)
1383	return VERR_IOM_IOPORT_UNUSED;
1384
1385	int rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_R3_IOPORT_READ);
1386	if (rc != VINF_SUCCESS)
1387	return rc;
1388
1389	uint8_t idxReg = uReg & 0x7;
1390	switch (idxReg)
1391	{
1392	case UART_REG_RBR_DLL_INDEX:
1393	rc = uartRegRbrDllRead(pThis, pu32);
1394	break;
1395	case UART_REG_IER_DLM_INDEX:
1396	rc = uartRegIerDlmRead(pThis, pu32);
1397	break;
1398	case UART_REG_IIR_INDEX:
1399	rc = uartRegIirRead(pThis, pu32);
1400	break;
1401	case UART_REG_LCR_INDEX:
1402	*pu32 = pThis->uRegLcr;
1403	break;
1404	case UART_REG_MCR_INDEX:
1405	*pu32 = pThis->uRegMcr;
1406	break;
1407	case UART_REG_LSR_INDEX:
1408	rc = uartRegLsrRead(pThis, pu32);
1409	break;
1410	case UART_REG_MSR_INDEX:
1411	rc = uartRegMsrRead(pThis, pu32);
1412	break;
1413	case UART_REG_SCR_INDEX:
1414	*pu32 = pThis->uRegScr;
1415	break;
1416	default:
1417	rc = VERR_IOM_IOPORT_UNUSED;
1418	}
1419
1420	PDMCritSectLeave(&pThis->CritSect);
1421	LogFlowFunc(("pThis=%#p uReg=%u{%s} u32=%#x cb=%u -> %Rrc\n",
1422	pThis, uReg, uartRegIdx2Str(pThis, idxReg, false /fWrite/), *pu32, cb, rc));
1423	return rc;
1424	}
1425
1426
1427	#ifdef IN_RING3
1428
1429	/* -=-=-=-=-=-=-=-=- Timer callbacks -=-=-=-=-=-=-=-=- */
1430
1431	/**
1432	* @callback_method_impl{FNTMTIMERDEV, Fifo timer function.}
1433	*/
1434	static DECLCALLBACK(void) uartR3RcvFifoTimeoutTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1435	{
1436	LogFlowFunc(("pDevIns=%#p pTimer=%#p pvUser=%#p\n", pDevIns, pTimer, pvUser));
1437	RT_NOREF(pDevIns, pTimer);
1438	PUARTCORE pThis = (PUARTCORE)pvUser;
1439	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1440	if (pThis->FifoRecv.cbUsed < pThis->FifoRecv.cbItl)
1441	{
1442	pThis->fIrqCtiPending = true;
1443	uartIrqUpdate(pThis);
1444	}
1445	PDMCritSectLeave(&pThis->CritSect);
1446	}
1447
1448	/**
1449	* @callback_method_impl{FNTMTIMERDEV, TX timer function when there is no driver connected for draining the THR/FIFO.}
1450	*/
1451	static DECLCALLBACK(void) uartR3TxUnconnectedTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1452	{
1453	LogFlowFunc(("pDevIns=%#p pTimer=%#p pvUser=%#p\n", pDevIns, pTimer, pvUser));
1454	RT_NOREF(pDevIns, pTimer);
1455	PUARTCORE pThis = (PUARTCORE)pvUser;
1456	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1457	uint8_t bVal = 0;
1458	size_t cbRead = 0;
1459	uartR3TxQueueCopyFrom(pThis, &bVal, sizeof(bVal), &cbRead);
1460	if (pThis->uRegMcr & UART_REG_MCR_LOOP)
1461	{
1462	/* Loopback mode is active, feed in the data at the receiving end. */
1463	uint32_t cbAvailOld = ASMAtomicAddU32(&pThis->cbAvailRdr, 1);
1464	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
1465	{
1466	PUARTFIFO pFifo = &pThis->FifoRecv;
1467	if (uartFifoFreeGet(pFifo) > 0)
1468	{
1469	pFifo->abBuf[pFifo->offWrite] = bVal;
1470	pFifo->offWrite = (pFifo->offWrite + 1) % pFifo->cbMax;
1471	pFifo->cbUsed++;
1472
1473	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
1474	if (pFifo->cbUsed < pFifo->cbItl)
1475	{
1476	pThis->fIrqCtiPending = false;
1477	TMTimerSetRelative(pThis->CTX_SUFF(pTimerRcvFifoTimeout), pThis->cSymbolXferTicks * 4, NULL);
1478	}
1479	uartIrqUpdate(pThis);
1480	}
1481
1482	ASMAtomicSubU32(&pThis->cbAvailRdr, 1);
1483	}
1484	else if (!cbAvailOld)
1485	{
1486	pThis->uRegRbr = bVal;
1487	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
1488	uartIrqUpdate(pThis);
1489	}
1490	}
1491	if (cbRead == 1)
1492	TMTimerSetRelative(pThis->CTX_SUFF(pTimerTxUnconnected), pThis->cSymbolXferTicks, NULL);
1493	PDMCritSectLeave(&pThis->CritSect);
1494	}
1495
1496
1497	/* -=-=-=-=-=-=-=-=- PDMISERIALPORT on LUN#0 -=-=-=-=-=-=-=-=- */
1498
1499
1500	/**
1501	* @interface_method_impl{PDMISERIALPORT,pfnDataAvailRdrNotify}
1502	*/
1503	static DECLCALLBACK(int) uartR3DataAvailRdrNotify(PPDMISERIALPORT pInterface, size_t cbAvail)
1504	{
1505	LogFlowFunc(("pInterface=%#p cbAvail=%zu\n", pInterface, cbAvail));
1506	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1507
1508	AssertMsg((uint32_t)cbAvail == cbAvail, ("Too much data available\n"));
1509
1510	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1511	uint32_t cbAvailOld = ASMAtomicAddU32(&pThis->cbAvailRdr, (uint32_t)cbAvail);
1512	LogFlow((" cbAvailRdr=%u -> cbAvailRdr=%u\n", cbAvailOld, cbAvail + cbAvailOld));
1513	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
1514	uartR3RecvFifoFill(pThis);
1515	else if (!cbAvailOld)
1516	{
1517	size_t cbRead = 0;
1518	int rc = pThis->pDrvSerial->pfnReadRdr(pThis->pDrvSerial, &pThis->uRegRbr, 1, &cbRead);
1519	AssertMsg(RT_SUCCESS(rc) && cbRead == 1, ("This shouldn't fail and always return one byte!\n")); RT_NOREF(rc);
1520	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
1521	uartIrqUpdate(pThis);
1522	}
1523	PDMCritSectLeave(&pThis->CritSect);
1524
1525	return VINF_SUCCESS;
1526	}
1527
1528
1529	/**
1530	* @interface_method_impl{PDMISERIALPORT,pfnDataSentNotify}
1531	*/
1532	static DECLCALLBACK(int) uartR3DataSentNotify(PPDMISERIALPORT pInterface)
1533	{
1534	LogFlowFunc(("pInterface=%#p\n", pInterface));
1535	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1536
1537	/* Set the transmitter empty bit because everything was sent. */
1538	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1539	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_TEMT);
1540	uartIrqUpdate(pThis);
1541	PDMCritSectLeave(&pThis->CritSect);
1542	return VINF_SUCCESS;
1543	}
1544
1545
1546	/**
1547	* @interface_method_impl{PDMISERIALPORT,pfnReadWr}
1548	*/
1549	static DECLCALLBACK(int) uartR3ReadWr(PPDMISERIALPORT pInterface, void pvBuf, size_t cbRead, size_t pcbRead)
1550	{
1551	LogFlowFunc(("pInterface=%#p pvBuf=%#p cbRead=%zu pcbRead=%#p\n", pInterface, pvBuf, cbRead, pcbRead));
1552	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1553
1554	AssertReturn(cbRead > 0, VERR_INVALID_PARAMETER);
1555
1556	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1557	uartR3TxQueueCopyFrom(pThis, pvBuf, cbRead, pcbRead);
1558	PDMCritSectLeave(&pThis->CritSect);
1559
1560	LogFlowFunc(("-> VINF_SUCCESS{pcbRead=%zu}\n", pcbRead));
1561	return VINF_SUCCESS;
1562	}
1563
1564
1565	/**
1566	* @interface_method_impl{PDMISERIALPORT,pfnNotifyStsLinesChanged}
1567	*/
1568	static DECLCALLBACK(int) uartR3NotifyStsLinesChanged(PPDMISERIALPORT pInterface, uint32_t fNewStatusLines)
1569	{
1570	LogFlowFunc(("pInterface=%#p fNewStatusLines=%#x\n", pInterface, fNewStatusLines));
1571	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1572
1573	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1574	uartR3StsLinesUpdate(pThis, fNewStatusLines);
1575	PDMCritSectLeave(&pThis->CritSect);
1576	return VINF_SUCCESS;
1577	}
1578
1579
1580	/**
1581	* @interface_method_impl{PDMISERIALPORT,pfnNotifyBrk}
1582	*/
1583	static DECLCALLBACK(int) uartR3NotifyBrk(PPDMISERIALPORT pInterface)
1584	{
1585	LogFlowFunc(("pInterface=%#p\n", pInterface));
1586	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1587
1588	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1589	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_BI);
1590	uartIrqUpdate(pThis);
1591	PDMCritSectLeave(&pThis->CritSect);
1592	return VINF_SUCCESS;
1593	}
1594
1595
1596	/* -=-=-=-=-=-=-=-=- PDMIBASE -=-=-=-=-=-=-=-=- */
1597
1598	/**
1599	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
1600	*/
1601	static DECLCALLBACK(void ) uartR3QueryInterface(PPDMIBASE pInterface, const char pszIID)
1602	{
1603	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, IBase);
1604	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
1605	PDMIBASE_RETURN_INTERFACE(pszIID, PDMISERIALPORT, &pThis->ISerialPort);
1606	return NULL;
1607	}
1608
1609
1610	DECLHIDDEN(int) uartR3SaveExec(PUARTCORE pThis, PSSMHANDLE pSSM)
1611	{
1612	SSMR3PutU16(pSSM, pThis->uRegDivisor);
1613	SSMR3PutU8(pSSM, pThis->uRegRbr);
1614	SSMR3PutU8(pSSM, pThis->uRegThr);
1615	SSMR3PutU8(pSSM, pThis->uRegIer);
1616	SSMR3PutU8(pSSM, pThis->uRegIir);
1617	SSMR3PutU8(pSSM, pThis->uRegFcr);
1618	SSMR3PutU8(pSSM, pThis->uRegLcr);
1619	SSMR3PutU8(pSSM, pThis->uRegMcr);
1620	SSMR3PutU8(pSSM, pThis->uRegLsr);
1621	SSMR3PutU8(pSSM, pThis->uRegMsr);
1622	SSMR3PutU8(pSSM, pThis->uRegScr);
1623	SSMR3PutBool(pSSM, pThis->fIrqCtiPending);
1624	SSMR3PutBool(pSSM, pThis->fThreEmptyPending);
1625	SSMR3PutU8(pSSM, pThis->FifoXmit.cbMax);
1626	SSMR3PutU8(pSSM, pThis->FifoXmit.cbItl);
1627	SSMR3PutU8(pSSM, pThis->FifoRecv.cbMax);
1628	SSMR3PutU8(pSSM, pThis->FifoRecv.cbItl);
1629
1630	int rc = TMR3TimerSave(pThis->pTimerRcvFifoTimeoutR3, pSSM);
1631	if (RT_SUCCESS(rc))
1632	rc = TMR3TimerSave(pThis->pTimerTxUnconnectedR3, pSSM);
1633
1634	return rc;
1635	}
1636
1637
1638	DECLHIDDEN(int) uartR3LoadExec(PUARTCORE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass,
1639	uint8_t pbIrq, RTIOPORT pPortBase)
1640	{
1641	RT_NOREF(uPass);
1642	int rc;
1643
1644	if (uVersion > UART_SAVED_STATE_VERSION_LEGACY_CODE)
1645	{
1646	SSMR3GetU16(pSSM, &pThis->uRegDivisor);
1647	SSMR3GetU8(pSSM, &pThis->uRegRbr);
1648	SSMR3GetU8(pSSM, &pThis->uRegThr);
1649	SSMR3GetU8(pSSM, &pThis->uRegIer);
1650	SSMR3GetU8(pSSM, &pThis->uRegIir);
1651	SSMR3GetU8(pSSM, &pThis->uRegFcr);
1652	SSMR3GetU8(pSSM, &pThis->uRegLcr);
1653	SSMR3GetU8(pSSM, &pThis->uRegMcr);
1654	SSMR3GetU8(pSSM, &pThis->uRegLsr);
1655	SSMR3GetU8(pSSM, &pThis->uRegMsr);
1656	SSMR3GetU8(pSSM, &pThis->uRegScr);
1657	SSMR3GetBool(pSSM, &pThis->fIrqCtiPending);
1658	SSMR3GetBool(pSSM, &pThis->fThreEmptyPending);
1659	SSMR3GetU8(pSSM, &pThis->FifoXmit.cbMax);
1660	SSMR3GetU8(pSSM, &pThis->FifoXmit.cbItl);
1661	SSMR3GetU8(pSSM, &pThis->FifoRecv.cbMax);
1662	SSMR3GetU8(pSSM, &pThis->FifoRecv.cbItl);
1663
1664	rc = TMR3TimerLoad(pThis->pTimerRcvFifoTimeoutR3, pSSM);
1665	if (uVersion > UART_SAVED_STATE_VERSION_PRE_UNCONNECTED_TX_TIMER)
1666	rc = TMR3TimerLoad(pThis->pTimerTxUnconnectedR3, pSSM);
1667	}
1668	else
1669	{
1670	AssertPtr(pbIrq);
1671	AssertPtr(pPortBase);
1672	if (uVersion == UART_SAVED_STATE_VERSION_16450)
1673	{
1674	pThis->enmType = UARTTYPE_16450;
1675	LogRel(("Serial#%d: falling back to 16450 mode from load state\n", pThis->pDevInsR3->iInstance));
1676	}
1677
1678	SSMR3GetU16(pSSM, &pThis->uRegDivisor);
1679	SSMR3GetU8(pSSM, &pThis->uRegRbr);
1680	SSMR3GetU8(pSSM, &pThis->uRegIer);
1681	SSMR3GetU8(pSSM, &pThis->uRegLcr);
1682	SSMR3GetU8(pSSM, &pThis->uRegMcr);
1683	SSMR3GetU8(pSSM, &pThis->uRegLsr);
1684	SSMR3GetU8(pSSM, &pThis->uRegMsr);
1685	SSMR3GetU8(pSSM, &pThis->uRegScr);
1686	if (uVersion > UART_SAVED_STATE_VERSION_16450)
1687	SSMR3GetU8(pSSM, &pThis->uRegFcr);
1688
1689	int32_t iTmp = 0;
1690	SSMR3GetS32(pSSM, &iTmp);
1691	pThis->fThreEmptyPending = RT_BOOL(iTmp);
1692
1693	rc = SSMR3GetS32(pSSM, &iTmp);
1694	AssertRCReturn(rc, rc);
1695	*pbIrq = (uint8_t)iTmp;
1696
1697	SSMR3Skip(pSSM, sizeof(int32_t)); /* was: last_break_enable */
1698
1699	uint32_t uPortBaseTmp = 0;
1700	rc = SSMR3GetU32(pSSM, &uPortBaseTmp);
1701	AssertRCReturn(rc, rc);
1702	*pPortBase = (RTIOPORT)uPortBaseTmp;
1703
1704	rc = SSMR3Skip(pSSM, sizeof(bool)); /* was: msr_changed */
1705	if ( RT_SUCCESS(rc)
1706	&& uVersion > UART_SAVED_STATE_VERSION_MISSING_BITS)
1707	{
1708	SSMR3GetU8(pSSM, &pThis->uRegThr);
1709	SSMR3Skip(pSSM, sizeof(uint8_t)); /* The old transmit shift register, not used anymore. */
1710	SSMR3GetU8(pSSM, &pThis->uRegIir);
1711
1712	int32_t iTimeoutPending = 0;
1713	SSMR3GetS32(pSSM, &iTimeoutPending);
1714	pThis->fIrqCtiPending = RT_BOOL(iTimeoutPending);
1715
1716	rc = TMR3TimerLoad(pThis->pTimerRcvFifoTimeoutR3, pSSM);
1717	AssertRCReturn(rc, rc);
1718
1719	bool fWasActiveIgn;
1720	rc = TMR3TimerSkip(pSSM, &fWasActiveIgn); /* was: transmit_timerR3 */
1721	AssertRCReturn(rc, rc);
1722
1723	SSMR3GetU8(pSSM, &pThis->FifoRecv.cbItl);
1724	rc = SSMR3GetU8(pSSM, &pThis->FifoRecv.cbItl);
1725	}
1726	}
1727
1728	return rc;
1729	}
1730
1731
1732	DECLHIDDEN(int) uartR3LoadDone(PUARTCORE pThis, PSSMHANDLE pSSM)
1733	{
1734	RT_NOREF(pSSM);
1735
1736	uartR3ParamsUpdate(pThis);
1737	uartIrqUpdate(pThis);
1738
1739	if (pThis->pDrvSerial)
1740	{
1741	/* Set the modem lines to reflect the current state. */
1742	int rc = pThis->pDrvSerial->pfnChgModemLines(pThis->pDrvSerial,
1743	RT_BOOL(pThis->uRegMcr & UART_REG_MCR_RTS),
1744	RT_BOOL(pThis->uRegMcr & UART_REG_MCR_DTR));
1745	if (RT_FAILURE(rc))
1746	LogRel(("Serial#%d: Failed to set modem lines with %Rrc during saved state load\n",
1747	pThis->pDevInsR3->iInstance, rc));
1748
1749	uint32_t fStsLines = 0;
1750	rc = pThis->pDrvSerial->pfnQueryStsLines(pThis->pDrvSerial, &fStsLines);
1751	if (RT_SUCCESS(rc))
1752	uartR3StsLinesUpdate(pThis, fStsLines);
1753	else
1754	LogRel(("Serial#%d: Failed to query status line status with %Rrc during reset\n",
1755	pThis->pDevInsR3->iInstance, rc));
1756	}
1757
1758	return VINF_SUCCESS;
1759	}
1760
1761
1762	DECLHIDDEN(void) uartR3Relocate(PUARTCORE pThis, RTGCINTPTR offDelta)
1763	{
1764	RT_NOREF(offDelta);
1765	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pThis->pDevInsR3);
1766	pThis->pTimerRcvFifoTimeoutRC = TMTimerRCPtr(pThis->pTimerRcvFifoTimeoutR3);
1767	pThis->pTimerTxUnconnectedRC = TMTimerRCPtr(pThis->pTimerTxUnconnectedR3);
1768	}
1769
1770
1771	DECLHIDDEN(void) uartR3Reset(PUARTCORE pThis)
1772	{
1773	pThis->uRegDivisor = 0x0c; /* Default to 9600 Baud. */
1774	pThis->uRegRbr = 0;
1775	pThis->uRegThr = 0;
1776	pThis->uRegIer = 0;
1777	pThis->uRegIir = UART_REG_IIR_IP_NO_INT;
1778	pThis->uRegFcr = 0;
1779	pThis->uRegLcr = 0; /* 5 data bits, no parity, 1 stop bit. */
1780	pThis->uRegMcr = 0;
1781	pThis->uRegLsr = UART_REG_LSR_THRE \| UART_REG_LSR_TEMT;
1782	pThis->uRegMsr = 0; /* Updated below. */
1783	pThis->uRegScr = 0;
1784	pThis->fIrqCtiPending = false;
1785	pThis->fThreEmptyPending = true;
1786
1787	/* Standard FIFO size for 15550A. */
1788	pThis->FifoXmit.cbMax = 16;
1789	pThis->FifoRecv.cbMax = 16;
1790	pThis->FifoRecv.cbItl = 1;
1791
1792	uartR3XferReset(pThis);
1793	}
1794
1795
1796	DECLHIDDEN(int) uartR3Attach(PUARTCORE pThis, unsigned iLUN)
1797	{
1798	int rc = PDMDevHlpDriverAttach(pThis->pDevInsR3, iLUN, &pThis->IBase, &pThis->pDrvBase, "Serial Char");
1799	if (RT_SUCCESS(rc))
1800	{
1801	pThis->pDrvSerial = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMISERIALCONNECTOR);
1802	if (!pThis->pDrvSerial)
1803	{
1804	AssertLogRelMsgFailed(("Configuration error: instance %d has no serial interface!\n", pThis->pDevInsR3->iInstance));
1805	return VERR_PDM_MISSING_INTERFACE;
1806	}
1807	uartR3XferReset(pThis);
1808	}
1809	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1810	{
1811	pThis->pDrvBase = NULL;
1812	pThis->pDrvSerial = NULL;
1813	rc = VINF_SUCCESS;
1814	uartR3XferReset(pThis);
1815	LogRel(("Serial#%d: no unit\n", pThis->pDevInsR3->iInstance));
1816	}
1817	else /* Don't call VMSetError here as we assume that the driver already set an appropriate error */
1818	LogRel(("Serial#%d: Failed to attach to serial driver. rc=%Rrc\n", pThis->pDevInsR3->iInstance, rc));
1819
1820	return rc;
1821	}
1822
1823
1824	DECLHIDDEN(void) uartR3Detach(PUARTCORE pThis)
1825	{
1826	/* Zero out important members. */
1827	pThis->pDrvBase = NULL;
1828	pThis->pDrvSerial = NULL;
1829	uartR3XferReset(pThis);
1830	}
1831
1832
1833	DECLHIDDEN(void) uartR3Destruct(PUARTCORE pThis)
1834	{
1835	PDMR3CritSectDelete(&pThis->CritSect);
1836	}
1837
1838
1839	DECLHIDDEN(int) uartR3Init(PUARTCORE pThis, PPDMDEVINS pDevInsR3, UARTTYPE enmType, unsigned iLUN, uint32_t fFlags,
1840	R3PTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReqR3, R0PTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReqR0,
1841	RCPTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReqRC)
1842	{
1843	int rc = VINF_SUCCESS;
1844
1845	/*
1846	* Initialize the instance data.
1847	* (Do this early or the destructor might choke on something!)
1848	*/
1849	pThis->pDevInsR3 = pDevInsR3;
1850	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevInsR3);
1851	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevInsR3);
1852	pThis->iLUN = iLUN;
1853	pThis->enmType = enmType;
1854	pThis->fFlags = fFlags;
1855	pThis->pfnUartIrqReqR3 = pfnUartIrqReqR3;
1856	pThis->pfnUartIrqReqR0 = pfnUartIrqReqR0;
1857	pThis->pfnUartIrqReqRC = pfnUartIrqReqRC;
1858
1859	/* IBase */
1860	pThis->IBase.pfnQueryInterface = uartR3QueryInterface;
1861
1862	/* ISerialPort */
1863	pThis->ISerialPort.pfnDataAvailRdrNotify = uartR3DataAvailRdrNotify;
1864	pThis->ISerialPort.pfnDataSentNotify = uartR3DataSentNotify;
1865	pThis->ISerialPort.pfnReadWr = uartR3ReadWr;
1866	pThis->ISerialPort.pfnNotifyStsLinesChanged = uartR3NotifyStsLinesChanged;
1867	pThis->ISerialPort.pfnNotifyBrk = uartR3NotifyBrk;
1868
1869	rc = PDMDevHlpCritSectInit(pDevInsR3, &pThis->CritSect, RT_SRC_POS, "Uart{%s#%d}#%d",
1870	pDevInsR3->pReg->szName, pDevInsR3->iInstance, iLUN);
1871	AssertRCReturn(rc, rc);
1872
1873	/*
1874	* Attach the char driver and get the interfaces.
1875	*/
1876	rc = PDMDevHlpDriverAttach(pDevInsR3, iLUN, &pThis->IBase, &pThis->pDrvBase, "UART");
1877	if (RT_SUCCESS(rc))
1878	{
1879	pThis->pDrvSerial = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMISERIALCONNECTOR);
1880	if (!pThis->pDrvSerial)
1881	{
1882	AssertLogRelMsgFailed(("Configuration error: instance %d has no serial interface!\n", iLUN));
1883	return VERR_PDM_MISSING_INTERFACE;
1884	}
1885	}
1886	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1887	{
1888	pThis->pDrvBase = NULL;
1889	pThis->pDrvSerial = NULL;
1890	LogRel(("Serial#%d: no unit\n", iLUN));
1891	}
1892	else
1893	{
1894	AssertLogRelMsgFailed(("Serial#%d: Failed to attach to char driver. rc=%Rrc\n", iLUN, rc));
1895	/* Don't call VMSetError here as we assume that the driver already set an appropriate error */
1896	return rc;
1897	}
1898
1899	/*
1900	* Create the receive FIFO character timeout indicator timer.
1901	*/
1902	rc = PDMDevHlpTMTimerCreate(pDevInsR3, TMCLOCK_VIRTUAL, uartR3RcvFifoTimeoutTimer, pThis,
1903	TMTIMER_FLAGS_NO_CRIT_SECT, "UART Rcv FIFO Timer",
1904	&pThis->pTimerRcvFifoTimeoutR3);
1905	AssertRCReturn(rc, rc);
1906
1907	rc = TMR3TimerSetCritSect(pThis->pTimerRcvFifoTimeoutR3, &pThis->CritSect);
1908	AssertRCReturn(rc, rc);
1909
1910	pThis->pTimerRcvFifoTimeoutR0 = TMTimerR0Ptr(pThis->pTimerRcvFifoTimeoutR3);
1911	pThis->pTimerRcvFifoTimeoutRC = TMTimerRCPtr(pThis->pTimerRcvFifoTimeoutR3);
1912
1913	/*
1914	* Create the transmit timer when no device is connected.
1915	*/
1916	rc = PDMDevHlpTMTimerCreate(pDevInsR3, TMCLOCK_VIRTUAL, uartR3TxUnconnectedTimer, pThis,
1917	TMTIMER_FLAGS_NO_CRIT_SECT, "UART TX uncon. Timer",
1918	&pThis->pTimerTxUnconnectedR3);
1919	AssertRCReturn(rc, rc);
1920
1921	rc = TMR3TimerSetCritSect(pThis->pTimerTxUnconnectedR3, &pThis->CritSect);
1922	AssertRCReturn(rc, rc);
1923
1924	pThis->pTimerTxUnconnectedR0 = TMTimerR0Ptr(pThis->pTimerTxUnconnectedR3);
1925	pThis->pTimerTxUnconnectedRC = TMTimerRCPtr(pThis->pTimerTxUnconnectedR3);
1926
1927	uartR3Reset(pThis);
1928	return VINF_SUCCESS;
1929	}
1930
1931	#endif /* IN_RING3 */
1932
1933	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Serial/UartCore.cpp@ 78403

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