VirtualBox

source: vbox/trunk/src/VBox/Devices/Serial/UartCore.cpp@ 87875

Last change on this file since 87875 was 87773, checked in by vboxsync, 4 years ago

VMM/TM,Devices: Store the timer name in the TMTIMER structure and limit it to 31 characters. Shortened most timer names. bugref:9943
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1/* $Id: UartCore.cpp 87773 2021-02-16 23:36:15Z vboxsync $ */
2/** @file
3 * UartCore - UART (16550A up to 16950) emulation.
4 *
5 * The documentation for this device was taken from the PC16550D spec from TI.
6 */
7
8/*
9 * Copyright (C) 2018-2020 Oracle Corporation
10 *
11 * This file is part of VirtualBox Open Source Edition (OSE), as
12 * available from http://www.virtualbox.org. This file is free software;
13 * you can redistribute it and/or modify it under the terms of the GNU
14 * General Public License (GPL) as published by the Free Software
15 * Foundation, in version 2 as it comes in the "COPYING" file of the
16 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18 */
19
20
21/*********************************************************************************************************************************
22* Header Files *
23*********************************************************************************************************************************/
24#define LOG_GROUP LOG_GROUP_DEV_SERIAL
25#include <VBox/vmm/tm.h>
26#include <iprt/log.h>
27#include <iprt/uuid.h>
28#include <iprt/assert.h>
29
30#include "VBoxDD.h"
31#include "UartCore.h"
32
33
34/*********************************************************************************************************************************
35* Defined Constants And Macros *
36*********************************************************************************************************************************/
37
38/** The RBR/DLL register index (from the base of the port range). */
39#define UART_REG_RBR_DLL_INDEX 0
40
41/** The THR/DLL register index (from the base of the port range). */
42#define UART_REG_THR_DLL_INDEX 0
43
44/** The IER/DLM register index (from the base of the port range). */
45#define UART_REG_IER_DLM_INDEX 1
46/** Enable received data available interrupt */
47# define UART_REG_IER_ERBFI RT_BIT(0)
48/** Enable transmitter holding register empty interrupt */
49# define UART_REG_IER_ETBEI RT_BIT(1)
50/** Enable receiver line status interrupt */
51# define UART_REG_IER_ELSI RT_BIT(2)
52/** Enable modem status interrupt. */
53# define UART_REG_IER_EDSSI RT_BIT(3)
54/** Sleep mode enable. */
55# define UART_REG_IER_SLEEP_MODE_EN RT_BIT(4)
56/** Low power mode enable. */
57# define UART_REG_IER_LP_MODE_EN RT_BIT(5)
58/** Mask of writeable bits. */
59# define UART_REG_IER_MASK_WR 0x0f
60/** Mask of writeable bits for 16750+. */
61# define UART_REG_IER_MASK_WR_16750 0x3f
62
63/** The IIR register index (from the base of the port range). */
64#define UART_REG_IIR_INDEX 2
65/** Interrupt Pending - high means no interrupt pending. */
66# define UART_REG_IIR_IP_NO_INT RT_BIT(0)
67/** Interrupt identification mask. */
68# define UART_REG_IIR_ID_MASK 0x0e
69/** Sets the interrupt identification to the given value. */
70# define UART_REG_IIR_ID_SET(a_Val) (((a_Val) << 1) & UART_REG_IIR_ID_MASK)
71/** Gets the interrupt identification from the given IIR register value. */
72# define UART_REG_IIR_ID_GET(a_Val) (((a_Val) & UART_REG_IIR_ID_MASK) >> 1)
73/** Receiver Line Status interrupt. */
74# define UART_REG_IIR_ID_RCL 0x3
75/** Received Data Available interrupt. */
76# define UART_REG_IIR_ID_RDA 0x2
77/** Character Timeou Indicator interrupt. */
78# define UART_REG_IIR_ID_CTI 0x6
79/** Transmitter Holding Register Empty interrupt. */
80# define UART_REG_IIR_ID_THRE 0x1
81/** Modem Status interrupt. */
82# define UART_REG_IIR_ID_MS 0x0
83/** 64 byte FIFOs enabled (15750+ only). */
84# define UART_REG_IIR_64BYTE_FIFOS_EN RT_BIT(5)
85/** FIFOs enabled. */
86# define UART_REG_IIR_FIFOS_EN 0xc0
87/** Bits relevant for checking whether the interrupt status has changed. */
88# define UART_REG_IIR_CHANGED_MASK 0x0f
89
90/** The FCR register index (from the base of the port range). */
91#define UART_REG_FCR_INDEX 2
92/** Enable the TX/RX FIFOs. */
93# define UART_REG_FCR_FIFO_EN RT_BIT(0)
94/** Reset the receive FIFO. */
95# define UART_REG_FCR_RCV_FIFO_RST RT_BIT(1)
96/** Reset the transmit FIFO. */
97# define UART_REG_FCR_XMIT_FIFO_RST RT_BIT(2)
98/** DMA Mode Select. */
99# define UART_REG_FCR_DMA_MODE_SEL RT_BIT(3)
100/** 64 Byte FIFO enable (15750+ only). */
101# define UART_REG_FCR_64BYTE_FIFO_EN RT_BIT(5)
102/** Receiver level interrupt trigger. */
103# define UART_REG_FCR_RCV_LVL_IRQ_MASK 0xc0
104/** Returns the receive level trigger value from the given FCR register. */
105# define UART_REG_FCR_RCV_LVL_IRQ_GET(a_Fcr) (((a_Fcr) & UART_REG_FCR_RCV_LVL_IRQ_MASK) >> 6)
106/** RCV Interrupt trigger level - 1 byte. */
107# define UART_REG_FCR_RCV_LVL_IRQ_1 0x0
108/** RCV Interrupt trigger level - 4 bytes. */
109# define UART_REG_FCR_RCV_LVL_IRQ_4 0x1
110/** RCV Interrupt trigger level - 8 bytes. */
111# define UART_REG_FCR_RCV_LVL_IRQ_8 0x2
112/** RCV Interrupt trigger level - 14 bytes. */
113# define UART_REG_FCR_RCV_LVL_IRQ_14 0x3
114/** Mask of writeable bits. */
115# define UART_REG_FCR_MASK_WR 0xcf
116/** Mask of sticky bits. */
117# define UART_REG_FCR_MASK_STICKY 0xe9
118
119/** The LCR register index (from the base of the port range). */
120#define UART_REG_LCR_INDEX 3
121/** Word Length Select Mask. */
122# define UART_REG_LCR_WLS_MASK 0x3
123/** Returns the WLS value form the given LCR register value. */
124# define UART_REG_LCR_WLS_GET(a_Lcr) ((a_Lcr) & UART_REG_LCR_WLS_MASK)
125/** Number of stop bits. */
126# define UART_REG_LCR_STB RT_BIT(2)
127/** Parity Enable. */
128# define UART_REG_LCR_PEN RT_BIT(3)
129/** Even Parity. */
130# define UART_REG_LCR_EPS RT_BIT(4)
131/** Stick parity. */
132# define UART_REG_LCR_PAR_STICK RT_BIT(5)
133/** Set Break. */
134# define UART_REG_LCR_BRK_SET RT_BIT(6)
135/** Divisor Latch Access Bit. */
136# define UART_REG_LCR_DLAB RT_BIT(7)
137
138/** The MCR register index (from the base of the port range). */
139#define UART_REG_MCR_INDEX 4
140/** Data Terminal Ready. */
141# define UART_REG_MCR_DTR RT_BIT(0)
142/** Request To Send. */
143# define UART_REG_MCR_RTS RT_BIT(1)
144/** Out1. */
145# define UART_REG_MCR_OUT1 RT_BIT(2)
146/** Out2. */
147# define UART_REG_MCR_OUT2 RT_BIT(3)
148/** Loopback connection. */
149# define UART_REG_MCR_LOOP RT_BIT(4)
150/** Flow Control Enable (15750+ only). */
151# define UART_REG_MCR_AFE RT_BIT(5)
152/** Mask of writeable bits (15450 and 15550A). */
153# define UART_REG_MCR_MASK_WR 0x1f
154/** Mask of writeable bits (15750+). */
155# define UART_REG_MCR_MASK_WR_15750 0x3f
156
157/** The LSR register index (from the base of the port range). */
158#define UART_REG_LSR_INDEX 5
159/** Data Ready. */
160# define UART_REG_LSR_DR RT_BIT(0)
161/** Overrun Error. */
162# define UART_REG_LSR_OE RT_BIT(1)
163/** Parity Error. */
164# define UART_REG_LSR_PE RT_BIT(2)
165/** Framing Error. */
166# define UART_REG_LSR_FE RT_BIT(3)
167/** Break Interrupt. */
168# define UART_REG_LSR_BI RT_BIT(4)
169/** Transmitter Holding Register. */
170# define UART_REG_LSR_THRE RT_BIT(5)
171/** Transmitter Empty. */
172# define UART_REG_LSR_TEMT RT_BIT(6)
173/** Error in receiver FIFO. */
174# define UART_REG_LSR_RCV_FIFO_ERR RT_BIT(7)
175/** The bits to check in this register when checking for the RCL interrupt. */
176# define UART_REG_LSR_BITS_IIR_RCL 0x1e
177
178/** The MSR register index (from the base of the port range). */
179#define UART_REG_MSR_INDEX 6
180/** Delta Clear to Send. */
181# define UART_REG_MSR_DCTS RT_BIT(0)
182/** Delta Data Set Ready. */
183# define UART_REG_MSR_DDSR RT_BIT(1)
184/** Trailing Edge Ring Indicator. */
185# define UART_REG_MSR_TERI RT_BIT(2)
186/** Delta Data Carrier Detect. */
187# define UART_REG_MSR_DDCD RT_BIT(3)
188/** Clear to Send. */
189# define UART_REG_MSR_CTS RT_BIT(4)
190/** Data Set Ready. */
191# define UART_REG_MSR_DSR RT_BIT(5)
192/** Ring Indicator. */
193# define UART_REG_MSR_RI RT_BIT(6)
194/** Data Carrier Detect. */
195# define UART_REG_MSR_DCD RT_BIT(7)
196/** The bits to check in this register when checking for the MS interrupt. */
197# define UART_REG_MSR_BITS_IIR_MS 0x0f
198
199/** The SCR register index (from the base of the port range). */
200#define UART_REG_SCR_INDEX 7
201
202/** Set the specified bits in the given register. */
203#define UART_REG_SET(a_Reg, a_Set) ((a_Reg) |= (a_Set))
204/** Clear the specified bits in the given register. */
205#define UART_REG_CLR(a_Reg, a_Clr) ((a_Reg) &= ~(a_Clr))
206
207
208/*********************************************************************************************************************************
209* Structures and Typedefs *
210*********************************************************************************************************************************/
211
212#ifndef VBOX_DEVICE_STRUCT_TESTCASE
213
214
215/*********************************************************************************************************************************
216* Global Variables *
217*********************************************************************************************************************************/
218
219#ifdef IN_RING3
220/**
221 * FIFO ITL levels.
222 */
223static struct
224{
225 /** ITL level for a 16byte FIFO. */
226 uint8_t cbItl16;
227 /** ITL level for a 64byte FIFO. */
228 uint8_t cbItl64;
229} s_aFifoItl[] =
230{
231 /* cbItl16 cbItl64 */
232 { 1, 1 },
233 { 4, 16 },
234 { 8, 32 },
235 { 14, 56 }
236};
237
238
239/**
240 * String versions of the parity enum.
241 */
242static const char *s_aszParity[] =
243{
244 "INVALID",
245 "NONE",
246 "EVEN",
247 "ODD",
248 "MARK",
249 "SPACE",
250 "INVALID"
251};
252
253
254/**
255 * String versions of the stop bits enum.
256 */
257static const char *s_aszStopBits[] =
258{
259 "INVALID",
260 "1",
261 "1.5",
262 "2",
263 "INVALID"
264};
265#endif
266
267
268/*********************************************************************************************************************************
269* Internal Functions *
270*********************************************************************************************************************************/
271
272
273/**
274 * Updates the IRQ state based on the current device state.
275 *
276 * @returns nothing.
277 * @param pDevIns The device instance.
278 * @param pThis The shared serial port instance data.
279 * @param pThisCC The serial port instance data for the current context.
280 */
281static void uartIrqUpdate(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC)
282{
283 LogFlowFunc(("pThis=%#p\n", pThis));
284
285 /*
286 * The interrupt uses a priority scheme, only the interrupt with the
287 * highest priority is indicated in the interrupt identification register.
288 *
289 * The priorities are as follows (high to low):
290 * * Receiver line status
291 * * Received data available
292 * * Character timeout indication (only in FIFO mode).
293 * * Transmitter holding register empty
294 * * Modem status change.
295 */
296 uint8_t uRegIirNew = UART_REG_IIR_IP_NO_INT;
297 if ( (pThis->uRegLsr & UART_REG_LSR_BITS_IIR_RCL)
298 && (pThis->uRegIer & UART_REG_IER_ELSI))
299 uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_RCL);
300 else if ( (pThis->uRegIer & UART_REG_IER_ERBFI)
301 && pThis->fIrqCtiPending)
302 uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_CTI);
303 else if ( (pThis->uRegLsr & UART_REG_LSR_DR)
304 && (pThis->uRegIer & UART_REG_IER_ERBFI)
305 && ( !(pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
306 || pThis->FifoRecv.cbUsed >= pThis->FifoRecv.cbItl))
307 uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_RDA);
308 else if ( (pThis->uRegIer & UART_REG_IER_ETBEI)
309 && pThis->fThreEmptyPending)
310 uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_THRE);
311 else if ( (pThis->uRegMsr & UART_REG_MSR_BITS_IIR_MS)
312 && (pThis->uRegIer & UART_REG_IER_EDSSI))
313 uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_MS);
314
315 LogFlowFunc((" uRegIirNew=%#x uRegIir=%#x\n", uRegIirNew, pThis->uRegIir));
316
317 /* Change interrupt only if the interrupt status really changed from the previous value. */
318 if (uRegIirNew != (pThis->uRegIir & UART_REG_IIR_CHANGED_MASK))
319 {
320 LogFlow((" Interrupt source changed from %#x -> %#x (IRQ %d -> %d)\n",
321 pThis->uRegIir, uRegIirNew,
322 pThis->uRegIir == UART_REG_IIR_IP_NO_INT ? 0 : 1,
323 uRegIirNew == UART_REG_IIR_IP_NO_INT ? 0 : 1));
324 if (uRegIirNew == UART_REG_IIR_IP_NO_INT)
325 pThisCC->pfnUartIrqReq(pDevIns, pThis, pThis->iLUN, 0);
326 else
327 pThisCC->pfnUartIrqReq(pDevIns, pThis, pThis->iLUN, 1);
328 }
329 else
330 LogFlow((" No change in interrupt source\n"));
331
332 if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
333 uRegIirNew |= UART_REG_IIR_FIFOS_EN;
334 if (pThis->uRegFcr & UART_REG_FCR_64BYTE_FIFO_EN)
335 uRegIirNew |= UART_REG_IIR_64BYTE_FIFOS_EN;
336
337 pThis->uRegIir = uRegIirNew;
338}
339
340
341/**
342 * Returns the amount of bytes stored in the given FIFO.
343 *
344 * @returns Amount of bytes stored in the FIFO.
345 * @param pFifo The FIFO.
346 */
347DECLINLINE(size_t) uartFifoUsedGet(PUARTFIFO pFifo)
348{
349 return pFifo->cbUsed;
350}
351
352
353/**
354 * Puts a new character into the given FIFO.
355 *
356 * @returns Flag whether the FIFO overflowed.
357 * @param pFifo The FIFO to put the data into.
358 * @param fOvrWr Flag whether to overwrite data if the FIFO is full.
359 * @param bData The data to add.
360 */
361DECLINLINE(bool) uartFifoPut(PUARTFIFO pFifo, bool fOvrWr, uint8_t bData)
362{
363 if (fOvrWr || pFifo->cbUsed < pFifo->cbMax)
364 {
365 pFifo->abBuf[pFifo->offWrite] = bData;
366 pFifo->offWrite = (pFifo->offWrite + 1) % pFifo->cbMax;
367 }
368
369 bool fOverFlow = false;
370 if (pFifo->cbUsed < pFifo->cbMax)
371 pFifo->cbUsed++;
372 else
373 {
374 fOverFlow = true;
375 if (fOvrWr) /* Advance the read position to account for the lost character. */
376 pFifo->offRead = (pFifo->offRead + 1) % pFifo->cbMax;
377 }
378
379 return fOverFlow;
380}
381
382
383/**
384 * Returns the next character in the FIFO.
385 *
386 * @return Next byte in the FIFO.
387 * @param pFifo The FIFO to get data from.
388 */
389DECLINLINE(uint8_t) uartFifoGet(PUARTFIFO pFifo)
390{
391 uint8_t bRet = 0;
392
393 if (pFifo->cbUsed)
394 {
395 bRet = pFifo->abBuf[pFifo->offRead];
396 pFifo->offRead = (pFifo->offRead + 1) % pFifo->cbMax;
397 pFifo->cbUsed--;
398 }
399
400 return bRet;
401}
402
403#ifdef IN_RING3
404
405/**
406 * Clears the given FIFO.
407 *
408 * @returns nothing.
409 * @param pFifo The FIFO to clear.
410 */
411DECLINLINE(void) uartFifoClear(PUARTFIFO pFifo)
412{
413 memset(&pFifo->abBuf[0], 0, sizeof(pFifo->abBuf));
414 pFifo->cbUsed = 0;
415 pFifo->offWrite = 0;
416 pFifo->offRead = 0;
417}
418
419
420/**
421 * Returns the amount of free bytes in the given FIFO.
422 *
423 * @returns The amount of bytes free in the given FIFO.
424 * @param pFifo The FIFO.
425 */
426DECLINLINE(size_t) uartFifoFreeGet(PUARTFIFO pFifo)
427{
428 return pFifo->cbMax - pFifo->cbUsed;
429}
430
431
432/**
433 * Tries to copy the requested amount of data from the given FIFO into the provided buffer.
434 *
435 * @returns Amount of bytes actually copied.
436 * @param pFifo The FIFO to copy data from.
437 * @param pvDst Where to copy the data to.
438 * @param cbCopy How much to copy.
439 */
440DECLINLINE(size_t) uartFifoCopyTo(PUARTFIFO pFifo, void *pvDst, size_t cbCopy)
441{
442 size_t cbCopied = 0;
443 uint8_t *pbDst = (uint8_t *)pvDst;
444
445 cbCopy = RT_MIN(cbCopy, pFifo->cbUsed);
446 while (cbCopy)
447 {
448 uint8_t cbThisCopy = (uint8_t)RT_MIN(cbCopy, (uint8_t)(pFifo->cbMax - pFifo->offRead));
449 memcpy(pbDst, &pFifo->abBuf[pFifo->offRead], cbThisCopy);
450
451 pFifo->offRead = (pFifo->offRead + cbThisCopy) % pFifo->cbMax;
452 pFifo->cbUsed -= cbThisCopy;
453 pbDst += cbThisCopy;
454 cbCopied += cbThisCopy;
455 cbCopy -= cbThisCopy;
456 }
457
458 return cbCopied;
459}
460
461
462#if 0 /* unused */
463/**
464 * Tries to copy the requested amount of data from the provided buffer into the given FIFO.
465 *
466 * @returns Amount of bytes actually copied.
467 * @param pFifo The FIFO to copy data to.
468 * @param pvSrc Where to copy the data from.
469 * @param cbCopy How much to copy.
470 */
471DECLINLINE(size_t) uartFifoCopyFrom(PUARTFIFO pFifo, void *pvSrc, size_t cbCopy)
472{
473 size_t cbCopied = 0;
474 uint8_t *pbSrc = (uint8_t *)pvSrc;
475
476 cbCopy = RT_MIN(cbCopy, uartFifoFreeGet(pFifo));
477 while (cbCopy)
478 {
479 uint8_t cbThisCopy = (uint8_t)RT_MIN(cbCopy, (uint8_t)(pFifo->cbMax - pFifo->offWrite));
480 memcpy(&pFifo->abBuf[pFifo->offWrite], pbSrc, cbThisCopy);
481
482 pFifo->offWrite = (pFifo->offWrite + cbThisCopy) % pFifo->cbMax;
483 pFifo->cbUsed += cbThisCopy;
484 pbSrc += cbThisCopy;
485 cbCopied += cbThisCopy;
486 cbCopy -= cbThisCopy;
487 }
488
489 return cbCopied;
490}
491#endif
492
493
494/**
495 * Updates the delta bits for the given MSR register value which has the status line
496 * bits set.
497 *
498 * @returns nothing.
499 * @param pDevIns The device instance.
500 * @param pThis The shared serial port instance data.
501 * @param pThisCC The serial port instance data for the current context.
502 * @param uMsrSts MSR value with the appropriate status bits set.
503 */
504static void uartR3MsrUpdate(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint8_t uMsrSts)
505{
506 /* Compare current and new states and set remaining bits accordingly. */
507 if ((uMsrSts & UART_REG_MSR_CTS) != (pThis->uRegMsr & UART_REG_MSR_CTS))
508 uMsrSts |= UART_REG_MSR_DCTS;
509 if ((uMsrSts & UART_REG_MSR_DSR) != (pThis->uRegMsr & UART_REG_MSR_DSR))
510 uMsrSts |= UART_REG_MSR_DDSR;
511 if ((uMsrSts & UART_REG_MSR_RI) != 0 && (pThis->uRegMsr & UART_REG_MSR_RI) == 0)
512 uMsrSts |= UART_REG_MSR_TERI;
513 if ((uMsrSts & UART_REG_MSR_DCD) != (pThis->uRegMsr & UART_REG_MSR_DCD))
514 uMsrSts |= UART_REG_MSR_DDCD;
515
516 pThis->uRegMsr = uMsrSts;
517
518 uartIrqUpdate(pDevIns, pThis, pThisCC);
519}
520
521
522/**
523 * Updates the serial port parameters of the attached driver with the current configuration.
524 *
525 * @returns nothing.
526 * @param pDevIns The device instance.
527 * @param pThis The shared serial port instance data.
528 * @param pThisCC The serial port instance data for the current context.
529 */
530static void uartR3ParamsUpdate(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC)
531{
532 if ( pThis->uRegDivisor != 0
533 && pThisCC->pDrvSerial)
534 {
535 uint32_t uBps = 115200 / pThis->uRegDivisor; /* This is for PC compatible serial port with a 1.8432 MHz crystal. */
536 unsigned cDataBits = UART_REG_LCR_WLS_GET(pThis->uRegLcr) + 5;
537 uint32_t cFrameBits = cDataBits;
538 PDMSERIALSTOPBITS enmStopBits = PDMSERIALSTOPBITS_ONE;
539 PDMSERIALPARITY enmParity = PDMSERIALPARITY_NONE;
540
541 if (pThis->uRegLcr & UART_REG_LCR_STB)
542 {
543 enmStopBits = cDataBits == 5 ? PDMSERIALSTOPBITS_ONEPOINTFIVE : PDMSERIALSTOPBITS_TWO;
544 cFrameBits += 2;
545 }
546 else
547 cFrameBits++;
548
549 if (pThis->uRegLcr & UART_REG_LCR_PEN)
550 {
551 /* Select the correct parity mode based on the even and stick parity bits. */
552 switch (pThis->uRegLcr & (UART_REG_LCR_EPS | UART_REG_LCR_PAR_STICK))
553 {
554 case 0:
555 enmParity = PDMSERIALPARITY_ODD;
556 break;
557 case UART_REG_LCR_EPS:
558 enmParity = PDMSERIALPARITY_EVEN;
559 break;
560 case UART_REG_LCR_EPS | UART_REG_LCR_PAR_STICK:
561 enmParity = PDMSERIALPARITY_SPACE;
562 break;
563 case UART_REG_LCR_PAR_STICK:
564 enmParity = PDMSERIALPARITY_MARK;
565 break;
566 default:
567 /* We should never get here as all cases where caught earlier. */
568 AssertMsgFailed(("This shouldn't happen at all: %#x\n",
569 pThis->uRegLcr & (UART_REG_LCR_EPS | UART_REG_LCR_PAR_STICK)));
570 }
571
572 cFrameBits++;
573 }
574
575 uint64_t uTimerFreq = PDMDevHlpTimerGetFreq(pDevIns, pThis->hTimerRcvFifoTimeout);
576 pThis->cSymbolXferTicks = (uTimerFreq / uBps) * cFrameBits;
577
578 LogFlowFunc(("Changing parameters to: %u,%s,%u,%s\n",
579 uBps, s_aszParity[enmParity], cDataBits, s_aszStopBits[enmStopBits]));
580
581 int rc = pThisCC->pDrvSerial->pfnChgParams(pThisCC->pDrvSerial, uBps, enmParity, cDataBits, enmStopBits);
582 if (RT_FAILURE(rc))
583 LogRelMax(10, ("Serial#%d: Failed to change parameters to %u,%s,%u,%s -> %Rrc\n",
584 pDevIns->iInstance, uBps, s_aszParity[enmParity], cDataBits, s_aszStopBits[enmStopBits], rc));
585
586 /* Changed parameters will flush all receive queues, so there won't be any data to read even if indicated. */
587 pThisCC->pDrvSerial->pfnQueuesFlush(pThisCC->pDrvSerial, true /*fQueueRecv*/, false /*fQueueXmit*/);
588 ASMAtomicWriteU32(&pThis->cbAvailRdr, 0);
589 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
590 }
591}
592
593
594/**
595 * Updates the internal device state with the given PDM status line states.
596 *
597 * @returns nothing.
598 * @param pDevIns The device instance.
599 * @param pThis The shared serial port instance data.
600 * @param pThisCC The serial port instance data for the current context.
601 * @param fStsLines The PDM status line states.
602 */
603static void uartR3StsLinesUpdate(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint32_t fStsLines)
604{
605 uint8_t uRegMsrNew = 0; /* The new MSR value. */
606
607 if (fStsLines & PDMISERIALPORT_STS_LINE_DCD)
608 uRegMsrNew |= UART_REG_MSR_DCD;
609 if (fStsLines & PDMISERIALPORT_STS_LINE_RI)
610 uRegMsrNew |= UART_REG_MSR_RI;
611 if (fStsLines & PDMISERIALPORT_STS_LINE_DSR)
612 uRegMsrNew |= UART_REG_MSR_DSR;
613 if (fStsLines & PDMISERIALPORT_STS_LINE_CTS)
614 uRegMsrNew |= UART_REG_MSR_CTS;
615
616 uartR3MsrUpdate(pDevIns, pThis, pThisCC, uRegMsrNew);
617}
618
619
620/**
621 * Fills up the receive FIFO with as much data as possible.
622 *
623 * @returns nothing.
624 * @param pDevIns The device instance.
625 * @param pThis The shared serial port instance data.
626 * @param pThisCC The serial port instance data for the current context.
627 */
628static void uartR3RecvFifoFill(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC)
629{
630 LogFlowFunc(("pThis=%#p\n", pThis));
631
632 PUARTFIFO pFifo = &pThis->FifoRecv;
633 size_t cbFill = RT_MIN(uartFifoFreeGet(pFifo),
634 ASMAtomicReadU32(&pThis->cbAvailRdr));
635 size_t cbFilled = 0;
636
637 while (cbFilled < cbFill)
638 {
639 size_t cbThisRead = cbFill - cbFilled;
640
641 if (pFifo->offRead <= pFifo->offWrite)
642 cbThisRead = RT_MIN(cbThisRead, (uint8_t)(pFifo->cbMax - pFifo->offWrite));
643 else
644 cbThisRead = RT_MIN(cbThisRead, (uint8_t)(pFifo->offRead - pFifo->offWrite));
645
646 size_t cbRead = 0;
647 int rc = pThisCC->pDrvSerial->pfnReadRdr(pThisCC->pDrvSerial, &pFifo->abBuf[pFifo->offWrite], cbThisRead, &cbRead);
648 AssertRC(rc); Assert(cbRead <= UINT8_MAX); RT_NOREF(rc);
649
650 pFifo->offWrite = (pFifo->offWrite + (uint8_t)cbRead) % pFifo->cbMax;
651 pFifo->cbUsed += (uint8_t)cbRead;
652 cbFilled += cbRead;
653
654 if (cbRead < cbThisRead)
655 break;
656 }
657
658 if (cbFilled)
659 {
660 UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
661 if (pFifo->cbUsed < pFifo->cbItl)
662 {
663 pThis->fIrqCtiPending = false;
664 PDMDevHlpTimerSetRelative(pDevIns, pThis->hTimerRcvFifoTimeout, pThis->cSymbolXferTicks * 4, NULL);
665 }
666 uartIrqUpdate(pDevIns, pThis, pThisCC);
667 }
668
669 Assert(cbFilled <= (size_t)pThis->cbAvailRdr);
670 ASMAtomicSubU32(&pThis->cbAvailRdr, (uint32_t)cbFilled);
671}
672
673
674/**
675 * Fetches a single byte and writes it to RBR.
676 *
677 * @returns nothing.
678 * @param pDevIns The device instance.
679 * @param pThis The shared serial port instance data.
680 * @param pThisCC The serial port instance data for the current context.
681 */
682static void uartR3ByteFetch(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC)
683{
684 if (ASMAtomicReadU32(&pThis->cbAvailRdr))
685 {
686 size_t cbRead = 0;
687 int rc2 = pThisCC->pDrvSerial->pfnReadRdr(pThisCC->pDrvSerial, &pThis->uRegRbr, 1, &cbRead);
688 AssertMsg(RT_SUCCESS(rc2) && cbRead == 1, ("This shouldn't fail and always return one byte!\n")); RT_NOREF(rc2);
689 UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
690 uartIrqUpdate(pDevIns, pThis, pThisCC);
691 }
692}
693
694
695/**
696 * Fetches a ready data based on the FIFO setting.
697 *
698 * @returns nothing.
699 * @param pDevIns The device instance.
700 * @param pThis The shared serial port instance data.
701 * @param pThisCC The serial port instance data for the current context.
702 */
703static void uartR3DataFetch(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC)
704{
705 AssertPtrReturnVoid(pThisCC->pDrvSerial);
706
707 if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
708 uartR3RecvFifoFill(pDevIns, pThis, pThisCC);
709 else
710 uartR3ByteFetch(pDevIns, pThis, pThisCC);
711}
712
713
714/**
715 * Reset the transmit/receive related bits to the standard values
716 * (after a detach/attach/reset event).
717 *
718 * @returns nothing.
719 * @param pDevIns The device instance.
720 * @param pThis The shared serial port instance data.
721 * @param pThisCC The serial port instance data for the current context.
722 */
723static void uartR3XferReset(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC)
724{
725 PDMDevHlpTimerStop(pDevIns, pThis->hTimerRcvFifoTimeout);
726 PDMDevHlpTimerStop(pDevIns, pThis->hTimerTxUnconnected);
727 pThis->uRegLsr = UART_REG_LSR_THRE | UART_REG_LSR_TEMT;
728 pThis->fThreEmptyPending = false;
729
730 uartFifoClear(&pThis->FifoXmit);
731 uartFifoClear(&pThis->FifoRecv);
732 uartR3ParamsUpdate(pDevIns, pThis, pThisCC);
733 uartIrqUpdate(pDevIns, pThis, pThisCC);
734
735 if (pThisCC->pDrvSerial)
736 {
737 /* Set the modem lines to reflect the current state. */
738 int rc = pThisCC->pDrvSerial->pfnChgModemLines(pThisCC->pDrvSerial, false /*fRts*/, false /*fDtr*/);
739 if (RT_FAILURE(rc))
740 LogRel(("Serial#%d: Failed to set modem lines with %Rrc during reset\n",
741 pDevIns->iInstance, rc));
742
743 uint32_t fStsLines = 0;
744 rc = pThisCC->pDrvSerial->pfnQueryStsLines(pThisCC->pDrvSerial, &fStsLines);
745 if (RT_SUCCESS(rc))
746 uartR3StsLinesUpdate(pDevIns, pThis, pThisCC, fStsLines);
747 else
748 LogRel(("Serial#%d: Failed to query status line status with %Rrc during reset\n",
749 pDevIns->iInstance, rc));
750 }
751
752}
753
754
755/**
756 * Tries to copy the specified amount of data from the active TX queue (register or FIFO).
757 *
758 * @returns nothing.
759 * @param pDevIns The device instance.
760 * @param pThis The shared serial port instance data.
761 * @param pThisCC The serial port instance data for the current context.
762 * @param pvBuf Where to store the data.
763 * @param cbRead How much to read from the TX queue.
764 * @param pcbRead Where to store the amount of data read.
765 */
766static void uartR3TxQueueCopyFrom(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC,
767 void *pvBuf, size_t cbRead, size_t *pcbRead)
768{
769 if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
770 {
771 *pcbRead = uartFifoCopyTo(&pThis->FifoXmit, pvBuf, cbRead);
772 if (!pThis->FifoXmit.cbUsed)
773 {
774 UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_THRE);
775 pThis->fThreEmptyPending = true;
776 }
777 if (*pcbRead)
778 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_TEMT);
779 uartIrqUpdate(pDevIns, pThis, pThisCC);
780 }
781 else if (!(pThis->uRegLsr & UART_REG_LSR_THRE))
782 {
783 *(uint8_t *)pvBuf = pThis->uRegThr;
784 *pcbRead = 1;
785 UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_THRE);
786 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_TEMT);
787 pThis->fThreEmptyPending = true;
788 uartIrqUpdate(pDevIns, pThis, pThisCC);
789 }
790 else
791 {
792 /*
793 * This can happen if there was data in the FIFO when the connection was closed,
794 * indicate this condition to the lower driver by returning 0 bytes.
795 */
796 *pcbRead = 0;
797 }
798}
799
800#endif /* IN_RING3 */
801
802
803/**
804 * Transmits the given byte.
805 *
806 * @returns Strict VBox status code.
807 * @param pDevIns The device instance.
808 * @param pThis The shared serial port instance data.
809 * @param pThisCC The serial port instance data for the current context.
810 * @param bVal Byte to transmit.
811 */
812static VBOXSTRICTRC uartXmit(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint8_t bVal)
813{
814 int rc = VINF_SUCCESS;
815#ifdef IN_RING3
816 bool fNotifyDrv = false;
817#endif
818
819 if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
820 {
821#ifndef IN_RING3
822 RT_NOREF(pDevIns, pThisCC);
823 if (!uartFifoUsedGet(&pThis->FifoXmit))
824 rc = VINF_IOM_R3_IOPORT_WRITE;
825 else
826 {
827 uartFifoPut(&pThis->FifoXmit, true /*fOvrWr*/, bVal);
828 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE | UART_REG_LSR_TEMT);
829 }
830#else
831 uartFifoPut(&pThis->FifoXmit, true /*fOvrWr*/, bVal);
832 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE | UART_REG_LSR_TEMT);
833 pThis->fThreEmptyPending = false;
834 uartIrqUpdate(pDevIns, pThis, pThisCC);
835 if (uartFifoUsedGet(&pThis->FifoXmit) == 1)
836 fNotifyDrv = true;
837#endif
838 }
839 else
840 {
841 /* Notify the lower driver about available data only if the register was empty before. */
842 if (pThis->uRegLsr & UART_REG_LSR_THRE)
843 {
844#ifndef IN_RING3
845 rc = VINF_IOM_R3_IOPORT_WRITE;
846#else
847 pThis->uRegThr = bVal;
848 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE | UART_REG_LSR_TEMT);
849 pThis->fThreEmptyPending = false;
850 uartIrqUpdate(pDevIns, pThis, pThisCC);
851 fNotifyDrv = true;
852#endif
853 }
854 else
855 pThis->uRegThr = bVal;
856 }
857
858#ifdef IN_RING3
859 if (fNotifyDrv)
860 {
861 /* Leave the device critical section before calling into the lower driver. */
862 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
863
864 if ( pThisCC->pDrvSerial
865 && !(pThis->uRegMcr & UART_REG_MCR_LOOP))
866 {
867 int rc2 = pThisCC->pDrvSerial->pfnDataAvailWrNotify(pThisCC->pDrvSerial);
868 if (RT_FAILURE(rc2))
869 LogRelMax(10, ("Serial#%d: Failed to send data with %Rrc\n", pDevIns->iInstance, rc2));
870 }
871 else
872 PDMDevHlpTimerSetRelative(pDevIns, pThis->hTimerTxUnconnected, pThis->cSymbolXferTicks, NULL);
873
874 PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VINF_SUCCESS);
875 }
876#endif
877
878 return rc;
879}
880
881
882/**
883 * Write handler for the THR/DLL register (depending on the DLAB bit in LCR).
884 *
885 * @returns Strict VBox status code.
886 * @param pDevIns The device instance.
887 * @param pThis The shared serial port instance data.
888 * @param pThisCC The serial port instance data for the current context.
889 * @param uVal The value to write.
890 */
891DECLINLINE(VBOXSTRICTRC) uartRegThrDllWrite(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint8_t uVal)
892{
893 VBOXSTRICTRC rc = VINF_SUCCESS;
894
895 /* A set DLAB causes a write to the lower 8bits of the divisor latch. */
896 if (pThis->uRegLcr & UART_REG_LCR_DLAB)
897 {
898 if (uVal != (pThis->uRegDivisor & 0xff))
899 {
900#ifndef IN_RING3
901 rc = VINF_IOM_R3_IOPORT_WRITE;
902#else
903 pThis->uRegDivisor = (pThis->uRegDivisor & 0xff00) | uVal;
904 uartR3ParamsUpdate(pDevIns, pThis, pThisCC);
905#endif
906 }
907 }
908 else
909 rc = uartXmit(pDevIns, pThis, pThisCC, uVal);
910
911 return rc;
912}
913
914
915/**
916 * Write handler for the IER/DLM register (depending on the DLAB bit in LCR).
917 *
918 * @returns Strict VBox status code.
919 * @param pDevIns The device instance.
920 * @param pThis The shared serial port instance data.
921 * @param pThisCC The serial port instance data for the current context.
922 * @param uVal The value to write.
923 */
924DECLINLINE(VBOXSTRICTRC) uartRegIerDlmWrite(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint8_t uVal)
925{
926 /* A set DLAB causes a write to the higher 8bits of the divisor latch. */
927 if (pThis->uRegLcr & UART_REG_LCR_DLAB)
928 {
929 if (uVal != (pThis->uRegDivisor & 0xff00) >> 8)
930 {
931#ifndef IN_RING3
932 return VINF_IOM_R3_IOPORT_WRITE;
933#else
934 pThis->uRegDivisor = (pThis->uRegDivisor & 0xff) | (uVal << 8);
935 uartR3ParamsUpdate(pDevIns, pThis, pThisCC);
936#endif
937 }
938 }
939 else
940 {
941 if (pThis->enmType < UARTTYPE_16750)
942 pThis->uRegIer = uVal & UART_REG_IER_MASK_WR;
943 else
944 pThis->uRegIer = uVal & UART_REG_IER_MASK_WR_16750;
945
946 if (pThis->uRegLsr & UART_REG_LSR_THRE)
947 pThis->fThreEmptyPending = true;
948
949 uartIrqUpdate(pDevIns, pThis, pThisCC);
950 }
951 return VINF_SUCCESS;
952}
953
954
955/**
956 * Write handler for the FCR register.
957 *
958 * @returns Strict VBox status code.
959 * @param pDevIns The device instance.
960 * @param pThis The shared serial port instance data.
961 * @param pThisCC The serial port instance data for the current context.
962 * @param uVal The value to write.
963 */
964DECLINLINE(VBOXSTRICTRC) uartRegFcrWrite(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint8_t uVal)
965{
966#ifndef IN_RING3
967 RT_NOREF(pDevIns, pThis, pThisCC, uVal);
968 return VINF_IOM_R3_IOPORT_WRITE;
969#else /* IN_RING3 */
970 if ( pThis->enmType >= UARTTYPE_16550A
971 && uVal != pThis->uRegFcr)
972 {
973 /* A change in the FIFO enable bit clears both FIFOs automatically. */
974 if ((uVal ^ pThis->uRegFcr) & UART_REG_FCR_FIFO_EN)
975 {
976 uartFifoClear(&pThis->FifoXmit);
977 uartFifoClear(&pThis->FifoRecv);
978
979 /*
980 * If the FIFO is about to be enabled and the DR bit is ready we have an unacknowledged
981 * byte in the RBR register which will be lost so we have to adjust the available bytes.
982 */
983 if ( ASMAtomicReadU32(&pThis->cbAvailRdr) > 0
984 && (uVal & UART_REG_FCR_FIFO_EN))
985 ASMAtomicDecU32(&pThis->cbAvailRdr);
986
987 /* Clear the DR bit too. */
988 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
989 }
990
991 /** @todo r=bird: Why was this here: if (rc == VINF_SUCCESS) */
992 {
993 if (uVal & UART_REG_FCR_RCV_FIFO_RST)
994 {
995 PDMDevHlpTimerStop(pDevIns, pThis->hTimerRcvFifoTimeout);
996 pThis->fIrqCtiPending = false;
997 uartFifoClear(&pThis->FifoRecv);
998 }
999 if (uVal & UART_REG_FCR_XMIT_FIFO_RST)
1000 uartFifoClear(&pThis->FifoXmit);
1001
1002 /*
1003 * The 64byte FIFO enable bit is only changeable for 16750
1004 * and if the DLAB bit in LCR is set.
1005 */
1006 if ( pThis->enmType < UARTTYPE_16750
1007 || !(pThis->uRegLcr & UART_REG_LCR_DLAB))
1008 uVal &= ~UART_REG_FCR_64BYTE_FIFO_EN;
1009 else /* Use previous value. */
1010 uVal |= pThis->uRegFcr & UART_REG_FCR_64BYTE_FIFO_EN;
1011
1012 if (uVal & UART_REG_FCR_64BYTE_FIFO_EN)
1013 {
1014 pThis->FifoRecv.cbMax = 64;
1015 pThis->FifoXmit.cbMax = 64;
1016 }
1017 else
1018 {
1019 pThis->FifoRecv.cbMax = 16;
1020 pThis->FifoXmit.cbMax = 16;
1021 }
1022
1023 if (uVal & UART_REG_FCR_FIFO_EN)
1024 {
1025 uint8_t idxItl = UART_REG_FCR_RCV_LVL_IRQ_GET(uVal);
1026 if (uVal & UART_REG_FCR_64BYTE_FIFO_EN)
1027 pThis->FifoRecv.cbItl = s_aFifoItl[idxItl].cbItl64;
1028 else
1029 pThis->FifoRecv.cbItl = s_aFifoItl[idxItl].cbItl16;
1030 }
1031
1032 /* The FIFO reset bits are self clearing. */
1033 pThis->uRegFcr = uVal & UART_REG_FCR_MASK_STICKY;
1034 uartIrqUpdate(pDevIns, pThis, pThisCC);
1035 }
1036
1037 /* Fill in the next data. */
1038 if (ASMAtomicReadU32(&pThis->cbAvailRdr))
1039 uartR3DataFetch(pDevIns, pThis, pThisCC);
1040 }
1041
1042 return VINF_SUCCESS;
1043#endif /* IN_RING3 */
1044}
1045
1046
1047/**
1048 * Write handler for the LCR register.
1049 *
1050 * @returns Strict VBox status code.
1051 * @param pDevIns The device instance.
1052 * @param pThis The shared serial port instance data.
1053 * @param pThisCC The serial port instance data for the current context.
1054 * @param uVal The value to write.
1055 */
1056DECLINLINE(VBOXSTRICTRC) uartRegLcrWrite(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint8_t uVal)
1057{
1058 /* Any change except the DLAB bit causes a switch to R3. */
1059 if ((pThis->uRegLcr & ~UART_REG_LCR_DLAB) != (uVal & ~UART_REG_LCR_DLAB))
1060 {
1061#ifndef IN_RING3
1062 RT_NOREF(pThisCC, pDevIns);
1063 return VINF_IOM_R3_IOPORT_WRITE;
1064#else
1065 /* Check whether the BREAK bit changed before updating the LCR value. */
1066 bool fBrkEn = RT_BOOL(uVal & UART_REG_LCR_BRK_SET);
1067 bool fBrkChg = fBrkEn != RT_BOOL(pThis->uRegLcr & UART_REG_LCR_BRK_SET);
1068 pThis->uRegLcr = uVal;
1069 uartR3ParamsUpdate(pDevIns, pThis, pThisCC);
1070
1071 if ( fBrkChg
1072 && pThisCC->pDrvSerial)
1073 pThisCC->pDrvSerial->pfnChgBrk(pThisCC->pDrvSerial, fBrkEn);
1074#endif
1075 }
1076 else
1077 pThis->uRegLcr = uVal;
1078
1079 return VINF_SUCCESS;
1080}
1081
1082
1083/**
1084 * Write handler for the MCR register.
1085 *
1086 * @returns Strict VBox status code.
1087 * @param pDevIns The device instance.
1088 * @param pThis The shared serial port instance data.
1089 * @param pThisCC The serial port instance data for the current context.
1090 * @param uVal The value to write.
1091 */
1092DECLINLINE(VBOXSTRICTRC) uartRegMcrWrite(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint8_t uVal)
1093{
1094 if (pThis->enmType < UARTTYPE_16750)
1095 uVal &= UART_REG_MCR_MASK_WR;
1096 else
1097 uVal &= UART_REG_MCR_MASK_WR_15750;
1098 if (pThis->uRegMcr != uVal)
1099 {
1100#ifndef IN_RING3
1101 RT_NOREF(pThisCC, pDevIns);
1102 return VINF_IOM_R3_IOPORT_WRITE;
1103#else
1104 /*
1105 * When loopback mode is activated the RTS, DTR, OUT1 and OUT2 lines are
1106 * disconnected and looped back to MSR.
1107 */
1108 if ( (uVal & UART_REG_MCR_LOOP)
1109 && !(pThis->uRegMcr & UART_REG_MCR_LOOP)
1110 && pThisCC->pDrvSerial)
1111 pThisCC->pDrvSerial->pfnChgModemLines(pThisCC->pDrvSerial, false /*fRts*/, false /*fDtr*/);
1112
1113 pThis->uRegMcr = uVal;
1114 if (uVal & UART_REG_MCR_LOOP)
1115 {
1116 uint8_t uRegMsrSts = 0;
1117
1118 if (uVal & UART_REG_MCR_RTS)
1119 uRegMsrSts |= UART_REG_MSR_CTS;
1120 if (uVal & UART_REG_MCR_DTR)
1121 uRegMsrSts |= UART_REG_MSR_DSR;
1122 if (uVal & UART_REG_MCR_OUT1)
1123 uRegMsrSts |= UART_REG_MSR_RI;
1124 if (uVal & UART_REG_MCR_OUT2)
1125 uRegMsrSts |= UART_REG_MSR_DCD;
1126 uartR3MsrUpdate(pDevIns, pThis, pThisCC, uRegMsrSts);
1127 }
1128 else if (pThisCC->pDrvSerial)
1129 {
1130 pThisCC->pDrvSerial->pfnChgModemLines(pThisCC->pDrvSerial,
1131 RT_BOOL(uVal & UART_REG_MCR_RTS),
1132 RT_BOOL(uVal & UART_REG_MCR_DTR));
1133
1134 uint32_t fStsLines = 0;
1135 int rc = pThisCC->pDrvSerial->pfnQueryStsLines(pThisCC->pDrvSerial, &fStsLines);
1136 if (RT_SUCCESS(rc))
1137 uartR3StsLinesUpdate(pDevIns, pThis, pThisCC, fStsLines);
1138 else
1139 LogRelMax(10, ("Serial#%d: Failed to query status line status with %Rrc during reset\n",
1140 pDevIns->iInstance, rc));
1141 }
1142 else /* Loopback mode got disabled and no driver attached, fake presence. */
1143 uartR3MsrUpdate(pDevIns, pThis, pThisCC, UART_REG_MSR_DCD | UART_REG_MSR_CTS | UART_REG_MSR_DSR);
1144#endif
1145 }
1146
1147 return VINF_SUCCESS;
1148}
1149
1150
1151/**
1152 * Read handler for the RBR/DLL register (depending on the DLAB bit in LCR).
1153 *
1154 * @returns VBox status code.
1155 * @param pDevIns The device instance.
1156 * @param pThis The shared serial port instance data.
1157 * @param pThisCC The serial port instance data for the current context.
1158 * @param puVal Where to store the read value on success.
1159 */
1160DECLINLINE(VBOXSTRICTRC) uartRegRbrDllRead(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint32_t *puVal)
1161{
1162 VBOXSTRICTRC rc = VINF_SUCCESS;
1163
1164 /* A set DLAB causes a read from the lower 8bits of the divisor latch. */
1165 if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1166 *puVal = pThis->uRegDivisor & 0xff;
1167 else
1168 {
1169 if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
1170 {
1171 /*
1172 * Only go back to R3 if there is new data available for the FIFO
1173 * and we would clear the interrupt to fill it up again.
1174 */
1175 if ( pThis->FifoRecv.cbUsed <= pThis->FifoRecv.cbItl
1176 && ASMAtomicReadU32(&pThis->cbAvailRdr) > 0)
1177 {
1178#ifndef IN_RING3
1179 rc = VINF_IOM_R3_IOPORT_READ;
1180#else
1181 uartR3RecvFifoFill(pDevIns, pThis, pThisCC);
1182#endif
1183 }
1184
1185 if (rc == VINF_SUCCESS)
1186 {
1187 *puVal = uartFifoGet(&pThis->FifoRecv);
1188 pThis->fIrqCtiPending = false;
1189 if (!pThis->FifoRecv.cbUsed)
1190 {
1191 PDMDevHlpTimerStop(pDevIns, pThis->hTimerRcvFifoTimeout);
1192 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
1193 }
1194 else if (pThis->FifoRecv.cbUsed < pThis->FifoRecv.cbItl)
1195 PDMDevHlpTimerSetRelative(pDevIns, pThis->hTimerRcvFifoTimeout,
1196 pThis->cSymbolXferTicks * 4, NULL);
1197 uartIrqUpdate(pDevIns, pThis, pThisCC);
1198 }
1199 }
1200 else
1201 {
1202 *puVal = pThis->uRegRbr;
1203
1204 if (pThis->uRegLsr & UART_REG_LSR_DR)
1205 {
1206 Assert(pThis->cbAvailRdr);
1207 uint32_t cbAvail = ASMAtomicDecU32(&pThis->cbAvailRdr);
1208 if (!cbAvail)
1209 {
1210 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
1211 uartIrqUpdate(pDevIns, pThis, pThisCC);
1212 }
1213 else
1214 {
1215#ifndef IN_RING3
1216 /* Restore state and go back to R3. */
1217 ASMAtomicIncU32(&pThis->cbAvailRdr);
1218 rc = VINF_IOM_R3_IOPORT_READ;
1219#else
1220 /* Fetch new data and keep the DR bit set. */
1221 uartR3DataFetch(pDevIns, pThis, pThisCC);
1222#endif
1223 }
1224 }
1225 }
1226 }
1227
1228 return rc;
1229}
1230
1231
1232/**
1233 * Read handler for the IER/DLM register (depending on the DLAB bit in LCR).
1234 *
1235 * @param pThis The shared serial port instance data.
1236 * @param puVal Where to store the read value on success.
1237 */
1238DECLINLINE(void) uartRegIerDlmRead(PUARTCORE pThis, uint32_t *puVal)
1239{
1240 /* A set DLAB causes a read from the upper 8bits of the divisor latch. */
1241 if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1242 *puVal = (pThis->uRegDivisor & 0xff00) >> 8;
1243 else
1244 *puVal = pThis->uRegIer;
1245}
1246
1247
1248/**
1249 * Read handler for the IIR register.
1250 *
1251 * @param pDevIns The device instance.
1252 * @param pThis The shared serial port instance data.
1253 * @param pThisCC The serial port instance data for the current context.
1254 * @param puVal Where to store the read value on success.
1255 */
1256DECLINLINE(void) uartRegIirRead(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint32_t *puVal)
1257{
1258 *puVal = pThis->uRegIir;
1259 /* Reset the THRE empty interrupt id when this gets returned to the guest (see table 3 UART Reset configuration). */
1260 if (UART_REG_IIR_ID_GET(pThis->uRegIir) == UART_REG_IIR_ID_THRE)
1261 {
1262 pThis->fThreEmptyPending = false;
1263 uartIrqUpdate(pDevIns, pThis, pThisCC);
1264 }
1265}
1266
1267
1268/**
1269 * Read handler for the LSR register.
1270 *
1271 * @returns Strict VBox status code.
1272 * @param pDevIns The device instance.
1273 * @param pThis The shared serial port instance data.
1274 * @param pThisCC The serial port instance data for the current context.
1275 * @param puVal Where to store the read value on success.
1276 */
1277DECLINLINE(VBOXSTRICTRC) uartRegLsrRead(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint32_t *puVal)
1278{
1279 /* Yield if configured and there is no data available. */
1280 if ( !(pThis->uRegLsr & UART_REG_LSR_DR)
1281 && (pThis->fFlags & UART_CORE_YIELD_ON_LSR_READ))
1282 {
1283#ifndef IN_RING3
1284 return VINF_IOM_R3_IOPORT_READ;
1285#else
1286 RTThreadYield();
1287#endif
1288 }
1289
1290 *puVal = pThis->uRegLsr;
1291 /*
1292 * Reading this register clears the Overrun (OE), Parity (PE) and Framing (FE) error
1293 * as well as the Break Interrupt (BI).
1294 */
1295 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_BITS_IIR_RCL);
1296 uartIrqUpdate(pDevIns, pThis, pThisCC);
1297
1298 return VINF_SUCCESS;
1299}
1300
1301
1302/**
1303 * Read handler for the MSR register.
1304 *
1305 * @param pDevIns The device instance.
1306 * @param pThis The shared serial port instance data.
1307 * @param pThisCC The serial port instance data for the current context.
1308 * @param puVal Where to store the read value on success.
1309 */
1310DECLINLINE(void) uartRegMsrRead(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint32_t *puVal)
1311{
1312 *puVal = pThis->uRegMsr;
1313
1314 /* Clear any of the delta bits. */
1315 UART_REG_CLR(pThis->uRegMsr, UART_REG_MSR_BITS_IIR_MS);
1316 uartIrqUpdate(pDevIns, pThis, pThisCC);
1317}
1318
1319
1320#ifdef LOG_ENABLED
1321/**
1322 * Converts the register index into a sensible memnonic.
1323 *
1324 * @returns Register memnonic.
1325 * @param pThis The shared serial port instance data.
1326 * @param idxReg Register index.
1327 * @param fWrite Flag whether the register gets written.
1328 */
1329DECLINLINE(const char *) uartRegIdx2Str(PUARTCORE pThis, uint8_t idxReg, bool fWrite)
1330{
1331 const char *psz = "INV";
1332
1333 switch (idxReg)
1334 {
1335 /*case UART_REG_THR_DLL_INDEX:*/
1336 case UART_REG_RBR_DLL_INDEX:
1337 if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1338 psz = "DLL";
1339 else if (fWrite)
1340 psz = "THR";
1341 else
1342 psz = "RBR";
1343 break;
1344 case UART_REG_IER_DLM_INDEX:
1345 if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1346 psz = "DLM";
1347 else
1348 psz = "IER";
1349 break;
1350 /*case UART_REG_IIR_INDEX:*/
1351 case UART_REG_FCR_INDEX:
1352 if (fWrite)
1353 psz = "FCR";
1354 else
1355 psz = "IIR";
1356 break;
1357 case UART_REG_LCR_INDEX:
1358 psz = "LCR";
1359 break;
1360 case UART_REG_MCR_INDEX:
1361 psz = "MCR";
1362 break;
1363 case UART_REG_LSR_INDEX:
1364 psz = "LSR";
1365 break;
1366 case UART_REG_MSR_INDEX:
1367 psz = "MSR";
1368 break;
1369 case UART_REG_SCR_INDEX:
1370 psz = "SCR";
1371 break;
1372 }
1373
1374 return psz;
1375}
1376#endif
1377
1378
1379/**
1380 * Performs a register write to the given register offset.
1381 *
1382 * @returns Strict VBox status code.
1383 * @param pDevIns The device instance.
1384 * @param pThis The shared UART core instance data.
1385 * @param pThisCC The current context UART core instance data.
1386 * @param uReg The register offset (byte offset) to start writing to.
1387 * @param u32 The value to write.
1388 * @param cb Number of bytes to write.
1389 */
1390DECLHIDDEN(VBOXSTRICTRC) uartRegWrite(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC,
1391 uint32_t uReg, uint32_t u32, size_t cb)
1392{
1393 AssertMsgReturn(cb == 1, ("uReg=%#x cb=%d u32=%#x\n", uReg, cb, u32), VINF_SUCCESS);
1394
1395 VBOXSTRICTRC rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VINF_IOM_R3_IOPORT_WRITE);
1396 if (rc == VINF_SUCCESS)
1397 {
1398 uint8_t idxReg = uReg & 0x7;
1399 LogFlowFunc(("pThis=%#p uReg=%u{%s} u32=%#x cb=%u\n",
1400 pThis, uReg, uartRegIdx2Str(pThis, idxReg, true /*fWrite*/), u32, cb));
1401
1402 uint8_t uVal = (uint8_t)u32;
1403 switch (idxReg)
1404 {
1405 case UART_REG_THR_DLL_INDEX:
1406 rc = uartRegThrDllWrite(pDevIns, pThis, pThisCC, uVal);
1407 break;
1408 case UART_REG_IER_DLM_INDEX:
1409 rc = uartRegIerDlmWrite(pDevIns, pThis, pThisCC, uVal);
1410 break;
1411 case UART_REG_FCR_INDEX:
1412 rc = uartRegFcrWrite(pDevIns, pThis, pThisCC, uVal);
1413 break;
1414 case UART_REG_LCR_INDEX:
1415 rc = uartRegLcrWrite(pDevIns, pThis, pThisCC, uVal);
1416 break;
1417 case UART_REG_MCR_INDEX:
1418 rc = uartRegMcrWrite(pDevIns, pThis, pThisCC, uVal);
1419 break;
1420 case UART_REG_SCR_INDEX:
1421 pThis->uRegScr = uVal;
1422 break;
1423 default:
1424 break;
1425 }
1426
1427 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
1428 }
1429 LogFlowFunc(("-> %Rrc\n", VBOXSTRICTRC_VAL(rc)));
1430 return rc;
1431}
1432
1433
1434/**
1435 * Performs a register read from the given register offset.
1436 *
1437 * @returns VBox status code.
1438 * @param pDevIns The device instance.
1439 * @param pThis The shared UART core instance data.
1440 * @param pThisCC The current context UART core instance data.
1441 * @param uReg The register offset (byte offset) to start reading from.
1442 * @param pu32 Where to store the read value.
1443 * @param cb Number of bytes to read.
1444 */
1445DECLHIDDEN(VBOXSTRICTRC) uartRegRead(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC,
1446 uint32_t uReg, uint32_t *pu32, size_t cb)
1447{
1448 if (cb != 1)
1449 return VERR_IOM_IOPORT_UNUSED;
1450
1451 VBOXSTRICTRC rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VINF_IOM_R3_IOPORT_READ);
1452 if (rc == VINF_SUCCESS)
1453 {
1454 uint8_t idxReg = uReg & 0x7;
1455 switch (idxReg)
1456 {
1457 case UART_REG_RBR_DLL_INDEX:
1458 rc = uartRegRbrDllRead(pDevIns, pThis, pThisCC, pu32);
1459 break;
1460 case UART_REG_IER_DLM_INDEX:
1461 uartRegIerDlmRead(pThis, pu32);
1462 break;
1463 case UART_REG_IIR_INDEX:
1464 uartRegIirRead(pDevIns, pThis, pThisCC, pu32);
1465 break;
1466 case UART_REG_LCR_INDEX:
1467 *pu32 = pThis->uRegLcr;
1468 break;
1469 case UART_REG_MCR_INDEX:
1470 *pu32 = pThis->uRegMcr;
1471 break;
1472 case UART_REG_LSR_INDEX:
1473 rc = uartRegLsrRead(pDevIns, pThis, pThisCC, pu32);
1474 break;
1475 case UART_REG_MSR_INDEX:
1476 uartRegMsrRead(pDevIns, pThis, pThisCC, pu32);
1477 break;
1478 case UART_REG_SCR_INDEX:
1479 *pu32 = pThis->uRegScr;
1480 break;
1481 default:
1482 rc = VERR_IOM_IOPORT_UNUSED;
1483 }
1484 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
1485 LogFlowFunc(("pThis=%#p uReg=%u{%s} u32=%#x cb=%u -> %Rrc\n",
1486 pThis, uReg, uartRegIdx2Str(pThis, idxReg, false /*fWrite*/), *pu32, cb, VBOXSTRICTRC_VAL(rc)));
1487 }
1488 else
1489 LogFlowFunc(("-> %Rrc\n", VBOXSTRICTRC_VAL(rc)));
1490 return rc;
1491}
1492
1493
1494#ifdef IN_RING3
1495
1496/* -=-=-=-=-=-=-=-=- Timer callbacks -=-=-=-=-=-=-=-=- */
1497
1498/**
1499 * @callback_method_impl{FNTMTIMERDEV, Fifo timer function.}
1500 */
1501static DECLCALLBACK(void) uartR3RcvFifoTimeoutTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
1502{
1503 LogFlowFunc(("pDevIns=%#p hTimer=%#p pvUser=%#p\n", pDevIns, hTimer, pvUser));
1504 PUARTCORER3 pThisCC = (PUARTCORECC)pvUser;
1505 PUARTCORE pThis = pThisCC->pShared;
1506 RT_NOREF(hTimer);
1507
1508 if (pThis->FifoRecv.cbUsed < pThis->FifoRecv.cbItl)
1509 {
1510 pThis->fIrqCtiPending = true;
1511 uartIrqUpdate(pDevIns, pThis, pThisCC);
1512 }
1513}
1514
1515/**
1516 * @callback_method_impl{FNTMTIMERDEV,
1517 * TX timer function when there is no driver connected for
1518 * draining the THR/FIFO.}
1519 */
1520static DECLCALLBACK(void) uartR3TxUnconnectedTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
1521{
1522 LogFlowFunc(("pDevIns=%#p hTimer=%#p pvUser=%#p\n", pDevIns, hTimer, pvUser));
1523 PUARTCORER3 pThisCC = (PUARTCORECC)pvUser;
1524 PUARTCORE pThis = pThisCC->pShared;
1525 Assert(hTimer == pThis->hTimerTxUnconnected);
1526
1527 VBOXSTRICTRC rc1 = PDMDevHlpTimerLockClock2(pDevIns, hTimer, &pThis->CritSect, VINF_SUCCESS /* must get it */);
1528 AssertRCReturnVoid(VBOXSTRICTRC_VAL(rc1));
1529
1530 uint8_t bVal = 0;
1531 size_t cbRead = 0;
1532 uartR3TxQueueCopyFrom(pDevIns, pThis, pThisCC, &bVal, sizeof(bVal), &cbRead);
1533 if (pThis->uRegMcr & UART_REG_MCR_LOOP)
1534 {
1535 /* Loopback mode is active, feed in the data at the receiving end. */
1536 uint32_t cbAvailOld = ASMAtomicAddU32(&pThis->cbAvailRdr, 1);
1537 if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
1538 {
1539 PUARTFIFO pFifo = &pThis->FifoRecv;
1540 if (uartFifoFreeGet(pFifo) > 0)
1541 {
1542 pFifo->abBuf[pFifo->offWrite] = bVal;
1543 pFifo->offWrite = (pFifo->offWrite + 1) % pFifo->cbMax;
1544 pFifo->cbUsed++;
1545
1546 UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
1547 if (pFifo->cbUsed < pFifo->cbItl)
1548 {
1549 pThis->fIrqCtiPending = false;
1550 PDMDevHlpTimerSetRelative(pDevIns, pThis->hTimerRcvFifoTimeout,
1551 pThis->cSymbolXferTicks * 4, NULL);
1552 }
1553 uartIrqUpdate(pDevIns, pThis, pThisCC);
1554 }
1555
1556 ASMAtomicSubU32(&pThis->cbAvailRdr, 1);
1557 }
1558 else if (!cbAvailOld)
1559 {
1560 pThis->uRegRbr = bVal;
1561 UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
1562 uartIrqUpdate(pDevIns, pThis, pThisCC);
1563 }
1564 else
1565 ASMAtomicSubU32(&pThis->cbAvailRdr, 1);
1566 }
1567
1568 if (cbRead == 1)
1569 PDMDevHlpTimerSetRelative(pDevIns, hTimer, pThis->cSymbolXferTicks, NULL);
1570 else
1571 {
1572 /* NO data left, set the transmitter holding register as empty. */
1573 UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_TEMT);
1574 }
1575
1576 PDMDevHlpTimerUnlockClock2(pDevIns, hTimer, &pThis->CritSect);
1577}
1578
1579
1580/* -=-=-=-=-=-=-=-=- PDMISERIALPORT on LUN#0 -=-=-=-=-=-=-=-=- */
1581
1582
1583/**
1584 * @interface_method_impl{PDMISERIALPORT,pfnDataAvailRdrNotify}
1585 */
1586static DECLCALLBACK(int) uartR3DataAvailRdrNotify(PPDMISERIALPORT pInterface, size_t cbAvail)
1587{
1588 LogFlowFunc(("pInterface=%#p cbAvail=%zu\n", pInterface, cbAvail));
1589 PUARTCORECC pThisCC = RT_FROM_MEMBER(pInterface, UARTCORECC, ISerialPort);
1590 PUARTCORE pThis = pThisCC->pShared;
1591 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1592
1593 AssertMsg((uint32_t)cbAvail == cbAvail, ("Too much data available\n"));
1594
1595 PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1596 uint32_t cbAvailOld = ASMAtomicAddU32(&pThis->cbAvailRdr, (uint32_t)cbAvail);
1597 LogFlow((" cbAvailRdr=%u -> cbAvailRdr=%u\n", cbAvailOld, cbAvail + cbAvailOld));
1598 if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
1599 uartR3RecvFifoFill(pDevIns, pThis, pThisCC);
1600 else if (!cbAvailOld)
1601 {
1602 size_t cbRead = 0;
1603 int rc = pThisCC->pDrvSerial->pfnReadRdr(pThisCC->pDrvSerial, &pThis->uRegRbr, 1, &cbRead);
1604 AssertRC(rc);
1605
1606 if (cbRead)
1607 {
1608 UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
1609 uartIrqUpdate(pDevIns, pThis, pThisCC);
1610 }
1611 }
1612 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
1613
1614 return VINF_SUCCESS;
1615}
1616
1617
1618/**
1619 * @interface_method_impl{PDMISERIALPORT,pfnDataSentNotify}
1620 */
1621static DECLCALLBACK(int) uartR3DataSentNotify(PPDMISERIALPORT pInterface)
1622{
1623 LogFlowFunc(("pInterface=%#p\n", pInterface));
1624 PUARTCORECC pThisCC = RT_FROM_MEMBER(pInterface, UARTCORECC, ISerialPort);
1625 PUARTCORE pThis = pThisCC->pShared;
1626 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1627
1628 /* Set the transmitter empty bit because everything was sent. */
1629 PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1630 UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_TEMT);
1631 uartIrqUpdate(pDevIns, pThis, pThisCC);
1632 PDMCritSectLeave(&pThis->CritSect);
1633 return VINF_SUCCESS;
1634}
1635
1636
1637/**
1638 * @interface_method_impl{PDMISERIALPORT,pfnReadWr}
1639 */
1640static DECLCALLBACK(int) uartR3ReadWr(PPDMISERIALPORT pInterface, void *pvBuf, size_t cbRead, size_t *pcbRead)
1641{
1642 LogFlowFunc(("pInterface=%#p pvBuf=%#p cbRead=%zu pcbRead=%#p\n", pInterface, pvBuf, cbRead, pcbRead));
1643 PUARTCORECC pThisCC = RT_FROM_MEMBER(pInterface, UARTCORECC, ISerialPort);
1644 PUARTCORE pThis = pThisCC->pShared;
1645 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1646
1647 AssertReturn(cbRead > 0, VERR_INVALID_PARAMETER);
1648
1649 PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1650 uartR3TxQueueCopyFrom(pDevIns, pThis, pThisCC, pvBuf, cbRead, pcbRead);
1651 PDMCritSectLeave(&pThis->CritSect);
1652
1653 LogFlowFunc(("-> VINF_SUCCESS{*pcbRead=%zu}\n", *pcbRead));
1654 return VINF_SUCCESS;
1655}
1656
1657
1658/**
1659 * @interface_method_impl{PDMISERIALPORT,pfnNotifyStsLinesChanged}
1660 */
1661static DECLCALLBACK(int) uartR3NotifyStsLinesChanged(PPDMISERIALPORT pInterface, uint32_t fNewStatusLines)
1662{
1663 LogFlowFunc(("pInterface=%#p fNewStatusLines=%#x\n", pInterface, fNewStatusLines));
1664 PUARTCORECC pThisCC = RT_FROM_MEMBER(pInterface, UARTCORECC, ISerialPort);
1665 PUARTCORE pThis = pThisCC->pShared;
1666 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1667
1668 PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1669 uartR3StsLinesUpdate(pDevIns, pThis, pThisCC, fNewStatusLines);
1670 PDMCritSectLeave(&pThis->CritSect);
1671 return VINF_SUCCESS;
1672}
1673
1674
1675/**
1676 * @interface_method_impl{PDMISERIALPORT,pfnNotifyBrk}
1677 */
1678static DECLCALLBACK(int) uartR3NotifyBrk(PPDMISERIALPORT pInterface)
1679{
1680 LogFlowFunc(("pInterface=%#p\n", pInterface));
1681 PUARTCORECC pThisCC = RT_FROM_MEMBER(pInterface, UARTCORECC, ISerialPort);
1682 PUARTCORE pThis = pThisCC->pShared;
1683 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1684
1685 PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1686 UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_BI);
1687 uartIrqUpdate(pDevIns, pThis, pThisCC);
1688 PDMCritSectLeave(&pThis->CritSect);
1689 return VINF_SUCCESS;
1690}
1691
1692
1693/* -=-=-=-=-=-=-=-=- PDMIBASE -=-=-=-=-=-=-=-=- */
1694
1695/**
1696 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
1697 */
1698static DECLCALLBACK(void *) uartR3QueryInterface(PPDMIBASE pInterface, const char *pszIID)
1699{
1700 PUARTCORECC pThisCC = RT_FROM_MEMBER(pInterface, UARTCORECC, IBase);
1701 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
1702 PDMIBASE_RETURN_INTERFACE(pszIID, PDMISERIALPORT, &pThisCC->ISerialPort);
1703 return NULL;
1704}
1705
1706
1707/**
1708 * Saves the UART state to the given SSM handle.
1709 *
1710 * @returns VBox status code.
1711 * @param pDevIns The device instance.
1712 * @param pThis The UART core instance.
1713 * @param pSSM The SSM handle to save to.
1714 */
1715DECLHIDDEN(int) uartR3SaveExec(PPDMDEVINS pDevIns, PUARTCORE pThis, PSSMHANDLE pSSM)
1716{
1717 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1718
1719 pHlp->pfnSSMPutU16(pSSM, pThis->uRegDivisor);
1720 pHlp->pfnSSMPutU8(pSSM, pThis->uRegRbr);
1721 pHlp->pfnSSMPutU8(pSSM, pThis->uRegThr);
1722 pHlp->pfnSSMPutU8(pSSM, pThis->uRegIer);
1723 pHlp->pfnSSMPutU8(pSSM, pThis->uRegIir);
1724 pHlp->pfnSSMPutU8(pSSM, pThis->uRegFcr);
1725 pHlp->pfnSSMPutU8(pSSM, pThis->uRegLcr);
1726 pHlp->pfnSSMPutU8(pSSM, pThis->uRegMcr);
1727 pHlp->pfnSSMPutU8(pSSM, pThis->uRegLsr);
1728 pHlp->pfnSSMPutU8(pSSM, pThis->uRegMsr);
1729 pHlp->pfnSSMPutU8(pSSM, pThis->uRegScr);
1730 pHlp->pfnSSMPutBool(pSSM, pThis->fIrqCtiPending);
1731 pHlp->pfnSSMPutBool(pSSM, pThis->fThreEmptyPending);
1732 pHlp->pfnSSMPutU8(pSSM, pThis->FifoXmit.cbMax);
1733 pHlp->pfnSSMPutU8(pSSM, pThis->FifoXmit.cbItl);
1734 pHlp->pfnSSMPutU8(pSSM, pThis->FifoRecv.cbMax);
1735 pHlp->pfnSSMPutU8(pSSM, pThis->FifoRecv.cbItl);
1736
1737 int rc = PDMDevHlpTimerSave(pDevIns, pThis->hTimerRcvFifoTimeout, pSSM);
1738 if (RT_SUCCESS(rc))
1739 rc = PDMDevHlpTimerSave(pDevIns, pThis->hTimerTxUnconnected, pSSM);
1740
1741 return rc;
1742}
1743
1744
1745/**
1746 * Loads the UART state from the given SSM handle.
1747 *
1748 * @returns VBox status code.
1749 * @param pDevIns The device instance.
1750 * @param pThis The UART core instance.
1751 * @param pSSM The SSM handle to load from.
1752 * @param uVersion Saved state version.
1753 * @param uPass The SSM pass the call is done in.
1754 * @param pbIrq Where to store the IRQ value for legacy
1755 * saved states - optional.
1756 * @param pPortBase Where to store the I/O port base for legacy
1757 * saved states - optional.
1758 */
1759DECLHIDDEN(int) uartR3LoadExec(PPDMDEVINS pDevIns, PUARTCORE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass,
1760 uint8_t *pbIrq, RTIOPORT *pPortBase)
1761{
1762 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1763 int rc;
1764 RT_NOREF(uPass);
1765
1766 if (uVersion > UART_SAVED_STATE_VERSION_LEGACY_CODE)
1767 {
1768 pHlp->pfnSSMGetU16(pSSM, &pThis->uRegDivisor);
1769 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegRbr);
1770 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegThr);
1771 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegIer);
1772 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegIir);
1773 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegFcr);
1774 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegLcr);
1775 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegMcr);
1776 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegLsr);
1777 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegMsr);
1778 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegScr);
1779 pHlp->pfnSSMGetBool(pSSM, &pThis->fIrqCtiPending);
1780 pHlp->pfnSSMGetBool(pSSM, &pThis->fThreEmptyPending);
1781 pHlp->pfnSSMGetU8(pSSM, &pThis->FifoXmit.cbMax);
1782 pHlp->pfnSSMGetU8(pSSM, &pThis->FifoXmit.cbItl);
1783 pHlp->pfnSSMGetU8(pSSM, &pThis->FifoRecv.cbMax);
1784 pHlp->pfnSSMGetU8(pSSM, &pThis->FifoRecv.cbItl);
1785
1786 rc = PDMDevHlpTimerLoad(pDevIns, pThis->hTimerRcvFifoTimeout, pSSM);
1787 if (uVersion > UART_SAVED_STATE_VERSION_PRE_UNCONNECTED_TX_TIMER)
1788 rc = PDMDevHlpTimerLoad(pDevIns, pThis->hTimerTxUnconnected, pSSM);
1789 }
1790 else
1791 {
1792 AssertPtr(pbIrq);
1793 AssertPtr(pPortBase);
1794 if (uVersion == UART_SAVED_STATE_VERSION_16450)
1795 {
1796 pThis->enmType = UARTTYPE_16450;
1797 LogRel(("Serial#%d: falling back to 16450 mode from load state\n", pDevIns->iInstance));
1798 }
1799
1800 pHlp->pfnSSMGetU16(pSSM, &pThis->uRegDivisor);
1801 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegRbr);
1802 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegIer);
1803 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegLcr);
1804 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegMcr);
1805 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegLsr);
1806 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegMsr);
1807 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegScr);
1808 if (uVersion > UART_SAVED_STATE_VERSION_16450)
1809 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegFcr);
1810
1811 int32_t iTmp = 0;
1812 pHlp->pfnSSMGetS32(pSSM, &iTmp);
1813 pThis->fThreEmptyPending = RT_BOOL(iTmp);
1814
1815 rc = pHlp->pfnSSMGetS32(pSSM, &iTmp);
1816 AssertRCReturn(rc, rc);
1817 *pbIrq = (uint8_t)iTmp;
1818
1819 pHlp->pfnSSMSkip(pSSM, sizeof(int32_t)); /* was: last_break_enable */
1820
1821 uint32_t uPortBaseTmp = 0;
1822 rc = pHlp->pfnSSMGetU32(pSSM, &uPortBaseTmp);
1823 AssertRCReturn(rc, rc);
1824 *pPortBase = (RTIOPORT)uPortBaseTmp;
1825
1826 rc = pHlp->pfnSSMSkip(pSSM, sizeof(bool)); /* was: msr_changed */
1827 if ( RT_SUCCESS(rc)
1828 && uVersion > UART_SAVED_STATE_VERSION_MISSING_BITS)
1829 {
1830 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegThr);
1831 pHlp->pfnSSMSkip(pSSM, sizeof(uint8_t)); /* The old transmit shift register, not used anymore. */
1832 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegIir);
1833
1834 int32_t iTimeoutPending = 0;
1835 pHlp->pfnSSMGetS32(pSSM, &iTimeoutPending);
1836 pThis->fIrqCtiPending = RT_BOOL(iTimeoutPending);
1837
1838 rc = PDMDevHlpTimerLoad(pDevIns, pThis->hTimerRcvFifoTimeout, pSSM);
1839 AssertRCReturn(rc, rc);
1840
1841 bool fWasActiveIgn;
1842 rc = pHlp->pfnTimerSkipLoad(pSSM, &fWasActiveIgn); /* was: transmit_timerR3 */
1843 AssertRCReturn(rc, rc);
1844
1845 pHlp->pfnSSMGetU8(pSSM, &pThis->FifoRecv.cbItl);
1846 rc = pHlp->pfnSSMGetU8(pSSM, &pThis->FifoRecv.cbItl);
1847 }
1848 }
1849
1850 return rc;
1851}
1852
1853
1854/**
1855 * Called when loading the state completed, updates the parameters of any driver underneath.
1856 *
1857 * @returns VBox status code.
1858 * @param pDevIns The device instance.
1859 * @param pThis The shared serial port instance data.
1860 * @param pThisCC The serial port instance data for the current context.
1861 * @param pSSM The SSM handle.
1862 */
1863DECLHIDDEN(int) uartR3LoadDone(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, PSSMHANDLE pSSM)
1864{
1865 RT_NOREF(pSSM);
1866
1867 uartR3ParamsUpdate(pDevIns, pThis, pThisCC);
1868 uartIrqUpdate(pDevIns, pThis, pThisCC);
1869
1870 if (pThisCC->pDrvSerial)
1871 {
1872 /* Set the modem lines to reflect the current state. */
1873 int rc = pThisCC->pDrvSerial->pfnChgModemLines(pThisCC->pDrvSerial,
1874 RT_BOOL(pThis->uRegMcr & UART_REG_MCR_RTS),
1875 RT_BOOL(pThis->uRegMcr & UART_REG_MCR_DTR));
1876 if (RT_FAILURE(rc))
1877 LogRel(("Serial#%d: Failed to set modem lines with %Rrc during saved state load\n",
1878 pDevIns->iInstance, rc));
1879
1880 uint32_t fStsLines = 0;
1881 rc = pThisCC->pDrvSerial->pfnQueryStsLines(pThisCC->pDrvSerial, &fStsLines);
1882 if (RT_SUCCESS(rc))
1883 uartR3StsLinesUpdate(pDevIns, pThis, pThisCC, fStsLines);
1884 else
1885 LogRel(("Serial#%d: Failed to query status line status with %Rrc during reset\n",
1886 pDevIns->iInstance, rc));
1887 }
1888
1889 return VINF_SUCCESS;
1890}
1891
1892
1893/**
1894 * Resets the given UART core instance.
1895 *
1896 * @returns nothing.
1897 * @param pDevIns The device instance.
1898 * @param pThis The shared serial port instance data.
1899 * @param pThisCC The serial port instance data for the current context.
1900 */
1901DECLHIDDEN(void) uartR3Reset(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC)
1902{
1903 pThis->uRegDivisor = 0x0c; /* Default to 9600 Baud. */
1904 pThis->uRegRbr = 0;
1905 pThis->uRegThr = 0;
1906 pThis->uRegIer = 0;
1907 pThis->uRegIir = UART_REG_IIR_IP_NO_INT;
1908 pThis->uRegFcr = 0;
1909 pThis->uRegLcr = 0; /* 5 data bits, no parity, 1 stop bit. */
1910 pThis->uRegMcr = 0;
1911 pThis->uRegLsr = UART_REG_LSR_THRE | UART_REG_LSR_TEMT;
1912 pThis->uRegMsr = UART_REG_MSR_DCD | UART_REG_MSR_CTS | UART_REG_MSR_DSR | UART_REG_MSR_DCTS | UART_REG_MSR_DDSR | UART_REG_MSR_DDCD;
1913 pThis->uRegScr = 0;
1914 pThis->fIrqCtiPending = false;
1915 pThis->fThreEmptyPending = true;
1916
1917 /* Standard FIFO size for 15550A. */
1918 pThis->FifoXmit.cbMax = 16;
1919 pThis->FifoRecv.cbMax = 16;
1920 pThis->FifoRecv.cbItl = 1;
1921
1922 uartR3XferReset(pDevIns, pThis, pThisCC);
1923}
1924
1925
1926/**
1927 * Attaches the given UART core instance to the drivers at the given LUN.
1928 *
1929 * @returns VBox status code.
1930 * @param pDevIns The device instance.
1931 * @param pThis The shared serial port instance data.
1932 * @param pThisCC The serial port instance data for the current context.
1933 * @param iLUN The LUN being attached.
1934 */
1935DECLHIDDEN(int) uartR3Attach(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, unsigned iLUN)
1936{
1937 int rc = PDMDevHlpDriverAttach(pDevIns, iLUN, &pThisCC->IBase, &pThisCC->pDrvBase, "Serial Char");
1938 if (RT_SUCCESS(rc))
1939 {
1940 pThisCC->pDrvSerial = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMISERIALCONNECTOR);
1941 if (!pThisCC->pDrvSerial)
1942 {
1943 AssertLogRelMsgFailed(("Configuration error: instance %d has no serial interface!\n", pDevIns->iInstance));
1944 return VERR_PDM_MISSING_INTERFACE;
1945 }
1946 PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1947 uartR3XferReset(pDevIns, pThis, pThisCC);
1948 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
1949 }
1950 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1951 {
1952 pThisCC->pDrvBase = NULL;
1953 pThisCC->pDrvSerial = NULL;
1954 rc = VINF_SUCCESS;
1955 PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1956 uartR3XferReset(pDevIns, pThis, pThisCC);
1957 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
1958 LogRel(("Serial#%d: no unit\n", pDevIns->iInstance));
1959 }
1960 else /* Don't call VMSetError here as we assume that the driver already set an appropriate error */
1961 LogRel(("Serial#%d: Failed to attach to serial driver. rc=%Rrc\n", pDevIns->iInstance, rc));
1962
1963 return rc;
1964}
1965
1966
1967/**
1968 * Detaches any attached driver from the given UART core instance.
1969 *
1970 * @returns nothing.
1971 * @param pDevIns The device instance.
1972 * @param pThis The shared serial port instance data.
1973 * @param pThisCC The serial port instance data for the current context.
1974 */
1975DECLHIDDEN(void) uartR3Detach(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC)
1976{
1977 /* Zero out important members. */
1978 pThisCC->pDrvBase = NULL;
1979 pThisCC->pDrvSerial = NULL;
1980 PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1981 uartR3XferReset(pDevIns, pThis, pThisCC);
1982 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
1983}
1984
1985
1986/**
1987 * Destroys the given UART core instance freeing all allocated resources.
1988 *
1989 * @returns nothing.
1990 * @param pDevIns The device instance.
1991 * @param pThis The shared UART core instance data..
1992 */
1993DECLHIDDEN(void) uartR3Destruct(PPDMDEVINS pDevIns, PUARTCORE pThis)
1994{
1995 PDMDevHlpCritSectDelete(pDevIns, &pThis->CritSect);
1996}
1997
1998
1999/**
2000 * Initializes the given UART core instance using the provided configuration.
2001 *
2002 * @returns VBox status code.
2003 * @param pDevIns The device instance pointer.
2004 * @param pThis The shared UART core instance data to
2005 * initialize.
2006 * @param pThisCC The ring-3 UART core instance data to
2007 * initialize.
2008 * @param enmType The type of UART emulated.
2009 * @param iLUN The LUN the UART should look for attached drivers.
2010 * @param fFlags Additional flags controlling device behavior.
2011 * @param pfnUartIrqReq Pointer to the interrupt request callback.
2012 */
2013DECLHIDDEN(int) uartR3Init(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC,
2014 UARTTYPE enmType, unsigned iLUN, uint32_t fFlags, PFNUARTCOREIRQREQ pfnUartIrqReq)
2015{
2016 /*
2017 * Initialize the instance data.
2018 * (Do this early or the destructor might choke on something!)
2019 */
2020 pThis->iLUN = iLUN;
2021 pThis->enmType = enmType;
2022 pThis->fFlags = fFlags;
2023
2024 pThisCC->iLUN = iLUN;
2025 pThisCC->pDevIns = pDevIns;
2026 pThisCC->pShared = pThis;
2027 pThisCC->pfnUartIrqReq = pfnUartIrqReq;
2028
2029 /* IBase */
2030 pThisCC->IBase.pfnQueryInterface = uartR3QueryInterface;
2031
2032 /* ISerialPort */
2033 pThisCC->ISerialPort.pfnDataAvailRdrNotify = uartR3DataAvailRdrNotify;
2034 pThisCC->ISerialPort.pfnDataSentNotify = uartR3DataSentNotify;
2035 pThisCC->ISerialPort.pfnReadWr = uartR3ReadWr;
2036 pThisCC->ISerialPort.pfnNotifyStsLinesChanged = uartR3NotifyStsLinesChanged;
2037 pThisCC->ISerialPort.pfnNotifyBrk = uartR3NotifyBrk;
2038
2039 int rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "Uart{%s#%d}#%d",
2040 pDevIns->pReg->szName, pDevIns->iInstance, iLUN);
2041 AssertRCReturn(rc, rc);
2042
2043 /*
2044 * Attach the char driver and get the interfaces.
2045 */
2046 rc = PDMDevHlpDriverAttach(pDevIns, iLUN, &pThisCC->IBase, &pThisCC->pDrvBase, "UART");
2047 if (RT_SUCCESS(rc))
2048 {
2049 pThisCC->pDrvSerial = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMISERIALCONNECTOR);
2050 if (!pThisCC->pDrvSerial)
2051 {
2052 AssertLogRelMsgFailed(("Configuration error: instance %d has no serial interface!\n", iLUN));
2053 return VERR_PDM_MISSING_INTERFACE;
2054 }
2055 }
2056 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2057 {
2058 pThisCC->pDrvBase = NULL;
2059 pThisCC->pDrvSerial = NULL;
2060 LogRel(("Serial#%d: no unit\n", iLUN));
2061 }
2062 else
2063 {
2064 AssertLogRelMsgFailed(("Serial#%d: Failed to attach to char driver. rc=%Rrc\n", iLUN, rc));
2065 /* Don't call VMSetError here as we assume that the driver already set an appropriate error */
2066 return rc;
2067 }
2068
2069 /*
2070 * Create the receive FIFO character timeout indicator timer.
2071 */
2072 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, uartR3RcvFifoTimeoutTimer, pThisCC,
2073 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "UART Rcv FIFO",
2074 &pThis->hTimerRcvFifoTimeout);
2075 AssertRCReturn(rc, rc);
2076
2077 rc = PDMDevHlpTimerSetCritSect(pDevIns, pThis->hTimerRcvFifoTimeout, &pThis->CritSect);
2078 AssertRCReturn(rc, rc);
2079
2080 /*
2081 * Create the transmit timer when no device is connected.
2082 */
2083 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, uartR3TxUnconnectedTimer, pThisCC,
2084 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_NO_RING0, "UART TX unconnect",
2085 &pThis->hTimerTxUnconnected);
2086 AssertRCReturn(rc, rc);
2087
2088 uartR3Reset(pDevIns, pThis, pThisCC);
2089 return VINF_SUCCESS;
2090}
2091
2092#else /* !IN_RING3 */
2093
2094/**
2095 * Initializes the ring-0 / raw-mode instance data.
2096 *
2097 * @returns VBox status code.
2098 * @param pThisCC The serial port instance data for the current context.
2099 * @param pfnUartIrqReq Pointer to the interrupt request callback.
2100 */
2101DECLHIDDEN(int) uartRZInit(PUARTCORECC pThisCC, PFNUARTCOREIRQREQ pfnUartIrqReq)
2102{
2103 AssertPtrReturn(pfnUartIrqReq, VERR_INVALID_POINTER);
2104 AssertPtrReturn(pThisCC, VERR_INVALID_POINTER);
2105 pThisCC->pfnUartIrqReq = pfnUartIrqReq;
2106 return VINF_SUCCESS;
2107}
2108
2109#endif /* !IN_RING3 */
2110
2111#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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