1 | /* $Id: UartCore.h 77411 2019-02-21 15:57:31Z vboxsync $ */
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2 | /** @file
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3 | * UartCore - UART (16550A up to 16950) emulation.
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4 | *
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5 | * The documentation for this device was taken from the PC16550D spec from TI.
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6 | */
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7 |
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8 | /*
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9 | * Copyright (C) 2018-2019 Oracle Corporation
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10 | *
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11 | * This file is part of VirtualBox Open Source Edition (OSE), as
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12 | * available from http://www.virtualbox.org. This file is free software;
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13 | * you can redistribute it and/or modify it under the terms of the GNU
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14 | * General Public License (GPL) as published by the Free Software
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15 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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16 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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17 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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18 | */
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19 |
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20 | #ifndef VBOX_INCLUDED_SRC_Serial_UartCore_h
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21 | #define VBOX_INCLUDED_SRC_Serial_UartCore_h
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22 | #ifndef RT_WITHOUT_PRAGMA_ONCE
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23 | # pragma once
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24 | #endif
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25 |
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26 | #include <VBox/types.h>
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27 | #include <VBox/vmm/pdmdev.h>
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28 | #include <VBox/vmm/pdmserialifs.h>
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29 | #include <VBox/vmm/ssm.h>
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30 | #include <iprt/assert.h>
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31 |
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32 | RT_C_DECLS_BEGIN
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33 |
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34 | /*********************************************************************************************************************************
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35 | * Defined Constants And Macros *
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36 | *********************************************************************************************************************************/
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37 |
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38 | /** The current serial code saved state version. */
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39 | #define UART_SAVED_STATE_VERSION 7
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40 | /** Saved state version before the TX timer for the connected device case was added. */
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41 | #define UART_SAVED_STATE_VERSION_PRE_UNCONNECTED_TX_TIMER 6
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42 | /** Saved state version of the legacy code which got replaced after 5.2. */
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43 | #define UART_SAVED_STATE_VERSION_LEGACY_CODE 5
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44 | /** Includes some missing bits from the previous saved state. */
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45 | #define UART_SAVED_STATE_VERSION_MISSING_BITS 4
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46 | /** Saved state version when only the 16450 variant was implemented. */
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47 | #define UART_SAVED_STATE_VERSION_16450 3
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48 |
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49 | /** Maximum size of a FIFO. */
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50 | #define UART_FIFO_LENGTH_MAX 128
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51 |
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52 |
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53 | /*********************************************************************************************************************************
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54 | * Structures and Typedefs *
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55 | *********************************************************************************************************************************/
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56 |
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57 | /** Pointer to the UART core state. */
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58 | typedef struct UARTCORE *PUARTCORE;
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59 |
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60 |
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61 | /**
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62 | * UART core IRQ request callback to let the core instance raise/clear interrupt requests.
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63 | *
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64 | * @returns nothing.
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65 | * @param pDevIns The owning device instance.
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66 | * @param pThis The UART core instance.
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67 | * @param iLUN The LUN associated with the UART core.
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68 | * @param iLvl The interrupt level.
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69 | */
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70 | typedef DECLCALLBACK(void) FNUARTCOREIRQREQ(PPDMDEVINS pDevIns, PUARTCORE pThis, unsigned iLUN, int iLvl);
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71 | /** Pointer to a UART core IRQ request callback. */
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72 | typedef FNUARTCOREIRQREQ *PFNUARTCOREIRQREQ;
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73 |
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74 |
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75 | /**
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76 | * UART type.
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77 | */
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78 | typedef enum UARTTYPE
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79 | {
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80 | /** Invalid UART type. */
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81 | UARTTYPE_INVALID = 0,
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82 | /** 16450 UART type. */
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83 | UARTTYPE_16450,
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84 | /** 16550A UART type. */
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85 | UARTTYPE_16550A,
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86 | /** 16750 UART type. */
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87 | UARTTYPE_16750,
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88 | /** 32bit hack. */
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89 | UARTTYPE_32BIT_HACK = 0x7fffffff
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90 | } UARTTYPE;
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91 |
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92 |
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93 | /**
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94 | * UART FIFO.
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95 | */
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96 | typedef struct UARTFIFO
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97 | {
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98 | /** Fifo size configured. */
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99 | uint8_t cbMax;
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100 | /** Current amount of bytes used. */
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101 | uint8_t cbUsed;
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102 | /** Next index to write to. */
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103 | uint8_t offWrite;
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104 | /** Next index to read from. */
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105 | uint8_t offRead;
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106 | /** The interrupt trigger level (only used for the receive FIFO). */
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107 | uint8_t cbItl;
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108 | /** The data in the FIFO. */
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109 | uint8_t abBuf[UART_FIFO_LENGTH_MAX];
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110 | /** Alignment to a 4 byte boundary. */
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111 | uint8_t au8Alignment0[3];
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112 | } UARTFIFO;
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113 | /** Pointer to a FIFO. */
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114 | typedef UARTFIFO *PUARTFIFO;
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115 |
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116 |
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117 | /**
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118 | * UART core device.
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119 | *
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120 | * @implements PDMIBASE
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121 | * @implements PDMISERIALPORT
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122 | */
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123 | typedef struct UARTCORE
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124 | {
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125 | /** Access critical section. */
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126 | PDMCRITSECT CritSect;
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127 | /** Pointer to the device instance - R3 Ptr. */
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128 | PPDMDEVINSR3 pDevInsR3;
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129 | /** Pointer to the device instance - R0 Ptr. */
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130 | PPDMDEVINSR0 pDevInsR0;
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131 | /** Pointer to the device instance - RC Ptr. */
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132 | PPDMDEVINSRC pDevInsRC;
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133 | /** The LUN on the owning device instance for this core. */
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134 | uint32_t iLUN;
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135 | /** LUN\#0: The base interface. */
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136 | PDMIBASE IBase;
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137 | /** LUN\#0: The serial port interface. */
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138 | PDMISERIALPORT ISerialPort;
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139 | /** Pointer to the attached base driver. */
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140 | R3PTRTYPE(PPDMIBASE) pDrvBase;
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141 | /** Pointer to the attached serial driver. */
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142 | R3PTRTYPE(PPDMISERIALCONNECTOR) pDrvSerial;
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143 | /** Configuration flags. */
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144 | uint32_t fFlags;
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145 | /** The selected UART type. */
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146 | UARTTYPE enmType;
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147 |
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148 | /** R3 timer pointer for the character timeout indication. */
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149 | PTMTIMERR3 pTimerRcvFifoTimeoutR3;
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150 | /** R3 timer pointer for the send loop if no driver is connected/loopback mode is active. */
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151 | PTMTIMERR3 pTimerTxUnconnectedR3;
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152 | /** R3 interrupt request callback of the owning device. */
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153 | R3PTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReqR3;
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154 | /** R0 timer pointer fo the character timeout indication. */
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155 | PTMTIMERR0 pTimerRcvFifoTimeoutR0;
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156 | /** R0 timer pointer for the send loop if no driver is connected/loopback mode is active. */
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157 | PTMTIMERR0 pTimerTxUnconnectedR0;
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158 | /** R0 interrupt request callback of the owning device. */
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159 | R0PTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReqR0;
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160 | /** RC timer pointer fo the character timeout indication. */
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161 | PTMTIMERRC pTimerRcvFifoTimeoutRC;
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162 | /** RC timer pointer for the send loop if no driver is connected/loopback mode is active. */
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163 | PTMTIMERRC pTimerTxUnconnectedRC;
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164 | /** RC interrupt request callback of the owning device. */
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165 | RCPTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReqRC;
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166 | /** Alignment */
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167 | uint32_t u32Alignment;
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168 |
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169 | /** The divisor register (DLAB = 1). */
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170 | uint16_t uRegDivisor;
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171 | /** The Receiver Buffer Register (RBR, DLAB = 0). */
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172 | uint8_t uRegRbr;
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173 | /** The Transmitter Holding Register (THR, DLAB = 0). */
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174 | uint8_t uRegThr;
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175 | /** The Interrupt Enable Register (IER, DLAB = 0). */
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176 | uint8_t uRegIer;
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177 | /** The Interrupt Identification Register (IIR). */
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178 | uint8_t uRegIir;
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179 | /** The FIFO Control Register (FCR). */
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180 | uint8_t uRegFcr;
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181 | /** The Line Control Register (LCR). */
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182 | uint8_t uRegLcr;
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183 | /** The Modem Control Register (MCR). */
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184 | uint8_t uRegMcr;
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185 | /** The Line Status Register (LSR). */
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186 | uint8_t uRegLsr;
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187 | /** The Modem Status Register (MSR). */
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188 | uint8_t uRegMsr;
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189 | /** The Scratch Register (SCR). */
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190 | uint8_t uRegScr;
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191 |
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192 | /** Flag whether a character timeout interrupt is pending
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193 | * (no symbols were inserted or removed from the receive FIFO
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194 | * during an 4 times the character transmit/receive period and the FIFO
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195 | * is not empty). */
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196 | bool fIrqCtiPending;
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197 | /** Flag whether the transmitter holding register went empty since last time the
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198 | * IIR register was read. This gets reset when IIR is read so the guest will get this
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199 | * interrupt ID only once. */
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200 | bool fThreEmptyPending;
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201 | /** Alignment. */
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202 | bool afAlignment[2];
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203 | /** The transmit FIFO. */
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204 | UARTFIFO FifoXmit;
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205 | /** The receive FIFO. */
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206 | UARTFIFO FifoRecv;
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207 |
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208 | /** Time it takes to transmit/receive a single symbol in timer ticks. */
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209 | uint64_t cSymbolXferTicks;
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210 | /** Number of bytes available for reading from the layer below. */
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211 | volatile uint32_t cbAvailRdr;
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212 |
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213 | #if defined(IN_RC) || HC_ARCH_BITS == 32
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214 | uint32_t uAlignment;
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215 | #endif
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216 | } UARTCORE;
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217 |
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218 | AssertCompileSizeAlignment(UARTCORE, 8);
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219 |
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220 |
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221 | #ifndef VBOX_DEVICE_STRUCT_TESTCASE
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222 |
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223 | /** Flag whether to yield the CPU on an LSR read. */
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224 | #define UART_CORE_YIELD_ON_LSR_READ RT_BIT_32(0)
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225 |
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226 | /**
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227 | * Performs a register write to the given register offset.
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228 | *
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229 | * @returns VBox status code.
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230 | * @param pThis The UART core instance.
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231 | * @param uReg The register offset (byte offset) to start writing to.
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232 | * @param u32 The value to write.
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233 | * @param cb Number of bytes to write.
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234 | */
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235 | DECLHIDDEN(int) uartRegWrite(PUARTCORE pThis, uint32_t uReg, uint32_t u32, size_t cb);
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236 |
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237 | /**
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238 | * Performs a register read from the given register offset.
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239 | *
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240 | * @returns VBox status code.
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241 | * @param pThis The UART core instance.
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242 | * @param uReg The register offset (byte offset) to start reading from.
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243 | * @param pu32 Where to store the read value.
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244 | * @param cb Number of bytes to read.
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245 | */
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246 | DECLHIDDEN(int) uartRegRead(PUARTCORE pThis, uint32_t uReg, uint32_t *pu32, size_t cb);
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247 |
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248 | # ifdef IN_RING3
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249 | /**
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250 | * Initializes the given UART core instance using the provided configuration.
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251 | *
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252 | * @returns VBox status code.
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253 | * @param pThis The UART core instance to initialize.
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254 | * @param pDevInsR3 The R3 device instance pointer.
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255 | * @param enmType The type of UART emulated.
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256 | * @param iLUN The LUN the UART should look for attached drivers.
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257 | * @param fFlags Additional flags controlling device behavior.
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258 | * @param pfnUartIrqReqR3 Pointer to the R3 interrupt request callback.
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259 | * @param pfnUartIrqReqR0 Pointer to the R0 interrupt request callback.
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260 | * @param pfnUartIrqReqRC Pointer to the RC interrupt request callback.
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261 | */
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262 | DECLHIDDEN(int) uartR3Init(PUARTCORE pThis, PPDMDEVINS pDevInsR3, UARTTYPE enmType, unsigned iLUN, uint32_t fFlags,
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263 | R3PTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReqR3, R0PTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReqR0,
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264 | RCPTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReqRC);
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265 |
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266 | /**
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267 | * Destroys the given UART core instance freeing all allocated resources.
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268 | *
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269 | * @returns nothing.
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270 | * @param pThis The UART core instance.
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271 | */
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272 | DECLHIDDEN(void) uartR3Destruct(PUARTCORE pThis);
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273 |
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274 | /**
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275 | * Detaches any attached driver from the given UART core instance.
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276 | *
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277 | * @returns nothing.
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278 | * @param pThis The UART core instance.
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279 | */
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280 | DECLHIDDEN(void) uartR3Detach(PUARTCORE pThis);
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281 |
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282 | /**
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283 | * Attaches the given UART core instance to the drivers at the given LUN.
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284 | *
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285 | * @returns VBox status code.
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286 | * @param pThis The UART core instance.
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287 | * @param iLUN The LUN being attached.
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288 | */
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289 | DECLHIDDEN(int) uartR3Attach(PUARTCORE pThis, unsigned iLUN);
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290 |
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291 | /**
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292 | * Resets the given UART core instance.
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293 | *
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294 | * @returns nothing.
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295 | * @param pThis The UART core instance.
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296 | */
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297 | DECLHIDDEN(void) uartR3Reset(PUARTCORE pThis);
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298 |
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299 | /**
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300 | * Relocates an RC pointers of the given UART core instance
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301 | *
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302 | * @returns nothing.
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303 | * @param pThis The UART core instance.
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304 | * @param offDelta The delta to relocate RC pointers with.
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305 | */
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306 | DECLHIDDEN(void) uartR3Relocate(PUARTCORE pThis, RTGCINTPTR offDelta);
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307 |
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308 | /**
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309 | * Saves the UART state to the given SSM handle.
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310 | *
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311 | * @returns VBox status code.
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312 | * @param pThis The UART core instance.
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313 | * @param pSSM The SSM handle to save to.
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314 | */
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315 | DECLHIDDEN(int) uartR3SaveExec(PUARTCORE pThis, PSSMHANDLE pSSM);
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316 |
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317 | /**
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318 | * Loads the UART state from the given SSM handle.
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319 | *
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320 | * @returns VBox status code.
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321 | * @param pThis The UART core instance.
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322 | * @param pSSM The SSM handle to load from.
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323 | * @param uVersion Saved state version.
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324 | * @param uPass The SSM pass the call is done in.
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325 | * @param puIrq Where to store the IRQ value for legacy
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326 | * saved states - optional.
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327 | * @param pPortBase Where to store the I/O port base for legacy
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328 | * saved states - optional.
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329 | */
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330 | DECLHIDDEN(int) uartR3LoadExec(PUARTCORE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass,
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331 | uint8_t *puIrq, RTIOPORT *pPortBase);
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332 |
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333 | /**
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334 | * Called when loading the state completed, updates the parameters of any driver underneath.
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335 | *
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336 | * @returns VBox status code.
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337 | * @param pThis The UART core instance.
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338 | * @param pSSM The SSM handle.
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339 | */
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340 | DECLHIDDEN(int) uartR3LoadDone(PUARTCORE pThis, PSSMHANDLE pSSM);
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341 |
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342 | # endif
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343 |
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344 | #endif
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345 |
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346 | RT_C_DECLS_END
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347 |
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348 | #endif /* !VBOX_INCLUDED_SRC_Serial_UartCore_h */
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