ATAController.h@ 15164

Last change on this file since 15164 was 13004, checked in by vboxsync, 16 years ago
ATA: implemented atapiGetEventStatusNotificationSS() for virtual ATAPI mode; overwrite the string returned by `SCSI_INQUIRY` even in passthrough mode (again); fixed determination of transfer length for `SCSI_INQUIRY`
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 18.1 KB

Line
1	/* $Id: ATAController.h 13004 2008-10-06 12:25:56Z vboxsync $ */
2	/** @file
3	* DevATA, DevAHCI - Shared ATA/ATAPI controller types.
4	*/
5
6	/*
7	* Copyright (C) 2006-2008 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___Storage_ATAController_h
23	#define ___Storage_ATAController_h
24
25	/*******************************************************************************
26	* Header Files *
27	*******************************************************************************/
28	#include <VBox/pdmdev.h>
29	#ifdef IN_RING3
30	# include <iprt/semaphore.h>
31	# include <iprt/thread.h>
32	#endif /* IN_RING3 */
33	#include <iprt/critsect.h>
34	#include <VBox/stam.h>
35
36	#include "PIIX3ATABmDma.h"
37	#include "ide.h"
38
39
40	/*******************************************************************************
41	* Defined Constants And Macros *
42	*******************************************************************************/
43	/**
44	* Maximum number of sectors to transfer in a READ/WRITE MULTIPLE request.
45	* Set to 1 to disable multi-sector read support. According to the ATA
46	* specification this must be a power of 2 and it must fit in an 8 bit
47	* value. Thus the only valid values are 1, 2, 4, 8, 16, 32, 64 and 128.
48	*/
49	#define ATA_MAX_MULT_SECTORS 128
50
51	/**
52	* Fastest PIO mode supported by the drive.
53	*/
54	#define ATA_PIO_MODE_MAX 4
55	/**
56	* Fastest MDMA mode supported by the drive.
57	*/
58	#define ATA_MDMA_MODE_MAX 2
59	/**
60	* Fastest UDMA mode supported by the drive.
61	*/
62	#define ATA_UDMA_MODE_MAX 6
63
64	/** ATAPI sense info size. */
65	#define ATAPI_SENSE_SIZE 64
66
67	/** The maximum number of release log entries per device. */
68	#define MAX_LOG_REL_ERRORS 1024
69
70	/* MediaEventStatus */
71	#define ATA_EVENT_STATUS_UNCHANGED 0 /*< medium event status not changed /
72	#define ATA_EVENT_STATUS_MEDIA_NEW 1 /*< new medium inserted /
73	#define ATA_EVENT_STATUS_MEDIA_REMOVED 2 /*< medium removed /
74	#define ATA_EVENT_STATUS_MEDIA_CHANGED 3 /*< medium was removed + new medium was inserted /
75
76
77	/*******************************************************************************
78	* Structures and Typedefs *
79	*******************************************************************************/
80	typedef struct ATADevState {
81	/** Flag indicating whether the current command uses LBA48 mode. */
82	bool fLBA48;
83	/** Flag indicating whether this drive implements the ATAPI command set. */
84	bool fATAPI;
85	/** Set if this interface has asserted the IRQ. */
86	bool fIrqPending;
87	/** Currently configured number of sectors in a multi-sector transfer. */
88	uint8_t cMultSectors;
89	/** PCHS disk geometry. */
90	PDMMEDIAGEOMETRY PCHSGeometry;
91	/** Total number of sectors on this disk. */
92	uint64_t cTotalSectors;
93	/** Number of sectors to transfer per IRQ. */
94	uint32_t cSectorsPerIRQ;
95
96	/** ATA/ATAPI register 1: feature (write-only). */
97	uint8_t uATARegFeature;
98	/** ATA/ATAPI register 1: feature, high order byte. */
99	uint8_t uATARegFeatureHOB;
100	/** ATA/ATAPI register 1: error (read-only). */
101	uint8_t uATARegError;
102	/** ATA/ATAPI register 2: sector count (read/write). */
103	uint8_t uATARegNSector;
104	/** ATA/ATAPI register 2: sector count, high order byte. */
105	uint8_t uATARegNSectorHOB;
106	/** ATA/ATAPI register 3: sector (read/write). */
107	uint8_t uATARegSector;
108	/** ATA/ATAPI register 3: sector, high order byte. */
109	uint8_t uATARegSectorHOB;
110	/** ATA/ATAPI register 4: cylinder low (read/write). */
111	uint8_t uATARegLCyl;
112	/** ATA/ATAPI register 4: cylinder low, high order byte. */
113	uint8_t uATARegLCylHOB;
114	/** ATA/ATAPI register 5: cylinder high (read/write). */
115	uint8_t uATARegHCyl;
116	/** ATA/ATAPI register 5: cylinder high, high order byte. */
117	uint8_t uATARegHCylHOB;
118	/** ATA/ATAPI register 6: select drive/head (read/write). */
119	uint8_t uATARegSelect;
120	/** ATA/ATAPI register 7: status (read-only). */
121	uint8_t uATARegStatus;
122	/** ATA/ATAPI register 7: command (write-only). */
123	uint8_t uATARegCommand;
124	/** ATA/ATAPI drive control register (write-only). */
125	uint8_t uATARegDevCtl;
126
127	/** Currently active transfer mode (MDMA/UDMA) and speed. */
128	uint8_t uATATransferMode;
129	/** Current transfer direction. */
130	uint8_t uTxDir;
131	/** Index of callback for begin transfer. */
132	uint8_t iBeginTransfer;
133	/** Index of callback for source/sink of data. */
134	uint8_t iSourceSink;
135	/** Flag indicating whether the current command transfers data in DMA mode. */
136	bool fDMA;
137	/** Set to indicate that ATAPI transfer semantics must be used. */
138	bool fATAPITransfer;
139
140	/** Total ATA/ATAPI transfer size, shared PIO/DMA. */
141	uint32_t cbTotalTransfer;
142	/** Elementary ATA/ATAPI transfer size, shared PIO/DMA. */
143	uint32_t cbElementaryTransfer;
144	/** Current read/write buffer position, shared PIO/DMA. */
145	uint32_t iIOBufferCur;
146	/** First element beyond end of valid buffer content, shared PIO/DMA. */
147	uint32_t iIOBufferEnd;
148
149	/** ATA/ATAPI current PIO read/write transfer position. Not shared with DMA for safety reasons. */
150	uint32_t iIOBufferPIODataStart;
151	/** ATA/ATAPI current PIO read/write transfer end. Not shared with DMA for safety reasons. */
152	uint32_t iIOBufferPIODataEnd;
153
154	/** ATAPI current LBA position. */
155	uint32_t iATAPILBA;
156	/** ATAPI current sector size. */
157	uint32_t cbATAPISector;
158	/** ATAPI current command. */
159	uint8_t aATAPICmd[ATAPI_PACKET_SIZE];
160	/** ATAPI sense data. */
161	uint8_t abATAPISense[ATAPI_SENSE_SIZE];
162	/** HACK: Countdown till we report a newly unmounted drive as mounted. */
163	uint8_t cNotifiedMediaChange;
164	/** The same for GET_EVENT_STATUS for mechanism */
165	volatile uint32_t MediaEventStatus;
166
167	uint32_t Alignment0;
168
169	/** The status LED state for this drive. */
170	PDMLED Led;
171
172	/** Size of I/O buffer. */
173	uint32_t cbIOBuffer;
174	/** Pointer to the I/O buffer. */
175	R3PTRTYPE(uint8_t *) pbIOBufferR3;
176	/** Pointer to the I/O buffer. */
177	R0PTRTYPE(uint8_t *) pbIOBufferR0;
178	/** Pointer to the I/O buffer. */
179	RCPTRTYPE(uint8_t *) pbIOBufferRC;
180
181	RTRCPTR Aligmnent1; /*< Align the statistics at an 8-byte boundrary. /
182
183	/*
184	* No data that is part of the saved state after this point!!!!!
185	*/
186
187	/* Release statistics: number of ATA DMA commands. */
188	STAMCOUNTER StatATADMA;
189	/* Release statistics: number of ATA PIO commands. */
190	STAMCOUNTER StatATAPIO;
191	/* Release statistics: number of ATAPI PIO commands. */
192	STAMCOUNTER StatATAPIDMA;
193	/* Release statistics: number of ATAPI PIO commands. */
194	STAMCOUNTER StatATAPIPIO;
195	#ifdef VBOX_INSTRUMENT_DMA_WRITES
196	/* Release statistics: number of DMA sector writes and the time spent. */
197	STAMPROFILEADV StatInstrVDWrites;
198	#endif
199
200	/** Statistics: number of read operations and the time spent reading. */
201	STAMPROFILEADV StatReads;
202	/** Statistics: number of bytes read. */
203	STAMCOUNTER StatBytesRead;
204	/** Statistics: number of write operations and the time spent writing. */
205	STAMPROFILEADV StatWrites;
206	/** Statistics: number of bytes written. */
207	STAMCOUNTER StatBytesWritten;
208	/** Statistics: number of flush operations and the time spend flushing. */
209	STAMPROFILE StatFlushes;
210
211	/** Enable passing through commands directly to the ATAPI drive. */
212	bool fATAPIPassthrough;
213	/** Number of errors we've reported to the release log.
214	* This is to prevent flooding caused by something going horribly wrong.
215	* this value against MAX_LOG_REL_ERRORS in places likely to cause floods
216	* like the ones we currently seeing on the linux smoke tests (2006-11-10). */
217	uint32_t cErrors;
218	/** Timestamp of last started command. 0 if no command pending. */
219	uint64_t u64CmdTS;
220
221	/** Pointer to the attached driver's base interface. */
222	R3PTRTYPE(PPDMIBASE) pDrvBase;
223	/** Pointer to the attached driver's block interface. */
224	R3PTRTYPE(PPDMIBLOCK) pDrvBlock;
225	/** Pointer to the attached driver's block bios interface. */
226	R3PTRTYPE(PPDMIBLOCKBIOS) pDrvBlockBios;
227	/** Pointer to the attached driver's mount interface.
228	* This is NULL if the driver isn't a removable unit. */
229	R3PTRTYPE(PPDMIMOUNT) pDrvMount;
230	/** The base interface. */
231	PDMIBASE IBase;
232	/** The block port interface. */
233	PDMIBLOCKPORT IPort;
234	/** The mount notify interface. */
235	PDMIMOUNTNOTIFY IMountNotify;
236	/** The LUN #. */
237	RTUINT iLUN;
238	#if HC_ARCH_BITS == 64
239	RTUINT Alignment2; /*< Align pDevInsR3 correctly. /
240	#endif
241	/** Pointer to device instance. */
242	PPDMDEVINSR3 pDevInsR3;
243	/** Pointer to controller instance. */
244	R3PTRTYPE(struct ATACONTROLLER *) pControllerR3;
245	/** Pointer to device instance. */
246	PPDMDEVINSR0 pDevInsR0;
247	/** Pointer to controller instance. */
248	R0PTRTYPE(struct ATACONTROLLER *) pControllerR0;
249	/** Pointer to device instance. */
250	PPDMDEVINSRC pDevInsRC;
251	/** Pointer to controller instance. */
252	RCPTRTYPE(struct ATACONTROLLER *) pControllerRC;
253	} ATADevState;
254
255
256	typedef struct ATATransferRequest
257	{
258	uint8_t iIf;
259	uint8_t iBeginTransfer;
260	uint8_t iSourceSink;
261	uint32_t cbTotalTransfer;
262	uint8_t uTxDir;
263	} ATATransferRequest;
264
265
266	typedef struct ATAAbortRequest
267	{
268	uint8_t iIf;
269	bool fResetDrive;
270	} ATAAbortRequest;
271
272
273	typedef enum
274	{
275	/** Begin a new transfer. */
276	ATA_AIO_NEW = 0,
277	/** Continue a DMA transfer. */
278	ATA_AIO_DMA,
279	/** Continue a PIO transfer. */
280	ATA_AIO_PIO,
281	/** Reset the drives on current controller, stop all transfer activity. */
282	ATA_AIO_RESET_ASSERTED,
283	/** Reset the drives on current controller, resume operation. */
284	ATA_AIO_RESET_CLEARED,
285	/** Abort the current transfer of a particular drive. */
286	ATA_AIO_ABORT
287	} ATAAIO;
288
289
290	typedef struct ATARequest
291	{
292	ATAAIO ReqType;
293	union
294	{
295	ATATransferRequest t;
296	ATAAbortRequest a;
297	} u;
298	} ATARequest;
299
300
301	typedef struct ATACONTROLLER
302	{
303	/** The base of the first I/O Port range. */
304	RTIOPORT IOPortBase1;
305	/** The base of the second I/O Port range. (0 if none) */
306	RTIOPORT IOPortBase2;
307	/** The assigned IRQ. */
308	RTUINT irq;
309	/** Access critical section */
310	PDMCRITSECT lock;
311
312	/** Selected drive. */
313	uint8_t iSelectedIf;
314	/** The interface on which to handle async I/O. */
315	uint8_t iAIOIf;
316	/** The state of the async I/O thread. */
317	uint8_t uAsyncIOState;
318	/** Flag indicating whether the next transfer is part of the current command. */
319	bool fChainedTransfer;
320	/** Set when the reset processing is currently active on this controller. */
321	bool fReset;
322	/** Flag whether the current transfer needs to be redone. */
323	bool fRedo;
324	/** Flag whether the redo suspend has been finished. */
325	bool fRedoIdle;
326	/** Flag whether the DMA operation to be redone is the final transfer. */
327	bool fRedoDMALastDesc;
328	/** The BusMaster DMA state. */
329	BMDMAState BmDma;
330	/** Pointer to first DMA descriptor. */
331	RTGCPHYS32 pFirstDMADesc;
332	/** Pointer to last DMA descriptor. */
333	RTGCPHYS32 pLastDMADesc;
334	/** Pointer to current DMA buffer (for redo operations). */
335	RTGCPHYS32 pRedoDMABuffer;
336	/** Size of current DMA buffer (for redo operations). */
337	uint32_t cbRedoDMABuffer;
338
339	/** The ATA/ATAPI interfaces of this controller. */
340	ATADevState aIfs[2];
341
342	/** Pointer to device instance. */
343	PPDMDEVINSR3 pDevInsR3;
344	/** Pointer to device instance. */
345	PPDMDEVINSR0 pDevInsR0;
346	/** Pointer to device instance. */
347	PPDMDEVINSRC pDevInsRC;
348
349	/** Set when the destroying the device instance and the thread must exit. */
350	uint32_t volatile fShutdown;
351	/** The async I/O thread handle. NIL_RTTHREAD if no thread. */
352	RTTHREAD AsyncIOThread;
353	/** The event semaphore the thread is waiting on for requests. */
354	RTSEMEVENT AsyncIOSem;
355	/** The request queue for the AIO thread. One element is always unused. */
356	ATARequest aAsyncIORequests[4];
357	/** The position at which to insert a new request for the AIO thread. */
358	uint8_t AsyncIOReqHead;
359	/** The position at which to get a new request for the AIO thread. */
360	uint8_t AsyncIOReqTail;
361	uint8_t Alignment3[2]; /*< Explicit padding of the 2 byte gap. /
362	/** Magic delay before triggering interrupts in DMA mode. */
363	uint32_t DelayIRQMillies;
364	/** The mutex protecting the request queue. */
365	RTSEMMUTEX AsyncIORequestMutex;
366	/** The event semaphore the thread is waiting on during suspended I/O. */
367	RTSEMEVENT SuspendIOSem;
368	#if 0 /HC_ARCH_BITS == 32/
369	uint32_t Alignment0;
370	#endif
371
372	/* Statistics */
373	STAMCOUNTER StatAsyncOps;
374	uint64_t StatAsyncMinWait;
375	uint64_t StatAsyncMaxWait;
376	STAMCOUNTER StatAsyncTimeUS;
377	STAMPROFILEADV StatAsyncTime;
378	STAMPROFILE StatLockWait;
379	} ATACONTROLLER, *PATACONTROLLER;
380
381	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
382
383	#define ATADEVSTATE_2_CONTROLLER(pIf) ( (pIf)->CTX_SUFF(pController) )
384	#define ATADEVSTATE_2_DEVINS(pIf) ( (pIf)->CTX_SUFF(pDevIns) )
385	#define CONTROLLER_2_DEVINS(pController) ( (pController)->CTX_SUFF(pDevIns) )
386	#define PDMIBASE_2_ATASTATE(pInterface) ( (ATADevState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ATADevState, IBase)) )
387
388
389	/*******************************************************************************
390	* Internal Functions *
391	******************************************************************************/
392	__BEGIN_DECLS
393	int ataControllerIOPortWrite1(PATACONTROLLER pCtl, RTIOPORT Port, uint32_t u32, unsigned cb);
394	int ataControllerIOPortRead1(PATACONTROLLER pCtl, RTIOPORT Port, uint32_t *u32, unsigned cb);
395	int ataControllerIOPortWriteStr1(PATACONTROLLER pCtl, RTIOPORT Port, RTGCPTR *pGCPtrSrc, PRTGCUINTREG pcTransfer, unsigned cb);
396	int ataControllerIOPortReadStr1(PATACONTROLLER pCtl, RTIOPORT Port, RTGCPTR *pGCPtrDst, PRTGCUINTREG pcTransfer, unsigned cb);
397	int ataControllerIOPortWrite2(PATACONTROLLER pCtl, RTIOPORT Port, uint32_t u32, unsigned cb);
398	int ataControllerIOPortRead2(PATACONTROLLER pCtl, RTIOPORT Port, uint32_t *u32, unsigned cb);
399	int ataControllerBMDMAIOPortRead(PATACONTROLLER pCtl, RTIOPORT Port, uint32_t *pu32, unsigned cb);
400	int ataControllerBMDMAIOPortWrite(PATACONTROLLER pCtl, RTIOPORT Port, uint32_t u32, unsigned cb);
401	__END_DECLS
402
403	#ifdef IN_RING3
404	/**
405	* Initialize a controller state.
406	*
407	* @returns VBox status code.
408	* @param pDevIns Pointer to the device instance which creates a controller.
409	* @param pCtl Pointer to the unitialized ATA controller structure.
410	* @param pDrvBaseMaster Pointer to the base driver interface which acts as the master.
411	* @param pDrvBaseSlave Pointer to the base driver interface which acts as the slave.
412	* @param pcbSSMState Where to store the size of the device state for loading/saving.
413	* @param szName Name of the controller (Used to initialize the critical section).
414	*/
415	int ataControllerInit(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PPDMIBASE pDrvBaseMaster, PPDMIBASE pDrvBaseSlave,
416	uint32_t pcbSSMState, const char szName);
417
418	/**
419	* Free all allocated resources for one controller instance.
420	*
421	* @returns VBox status code.
422	* @param pCtl The controller instance.
423	*/
424	int ataControllerDestroy(PATACONTROLLER pCtl);
425
426	/**
427	* Power off a controller.
428	*
429	* @returns nothing.
430	* @param pCtl the controller instance.
431	*/
432	void ataControllerPowerOff(PATACONTROLLER pCtl);
433
434	/**
435	* Reset a controller instance to an initial state.
436	*
437	* @returns VBox status code.
438	* @param pCtl Pointer to the controller.
439	*/
440	void ataControllerReset(PATACONTROLLER pCtl);
441
442	/**
443	* Suspend operation of an controller.
444	*
445	* @returns nothing
446	* @param pCtl The controller instance.
447	*/
448	void ataControllerSuspend(PATACONTROLLER pCtl);
449
450	/**
451	* Resume operation of an controller.
452	*
453	* @returns nothing
454	* @param pCtl The controller instance.
455	*/
456
457	void ataControllerResume(PATACONTROLLER pCtl);
458
459	/**
460	* Relocate neccessary pointers.
461	*
462	* @returns nothing.
463	* @param pCtl The controller instance.
464	* @param offDelta The relocation delta relative to the old location.
465	*/
466	void ataControllerRelocate(PATACONTROLLER pCtl, RTGCINTPTR offDelta);
467
468	/**
469	* Execute state save operation.
470	*
471	* @returns VBox status code.
472	* @param pCtl The controller instance.
473	* @param pSSM SSM operation handle.
474	*/
475	int ataControllerSaveExec(PATACONTROLLER pCtl, PSSMHANDLE pSSM);
476
477	/**
478	* Prepare state save operation.
479	*
480	* @returns VBox status code.
481	* @param pCtl The controller instance.
482	* @param pSSM SSM operation handle.
483	*/
484	int ataControllerSavePrep(PATACONTROLLER pCtl, PSSMHANDLE pSSM);
485
486	/**
487	* Excute state load operation.
488	*
489	* @returns VBox status code.
490	* @param pCtl The controller instance.
491	* @param pSSM SSM operation handle.
492	*/
493	int ataControllerLoadExec(PATACONTROLLER pCtl, PSSMHANDLE pSSM);
494
495	/**
496	* Prepare state load operation.
497	*
498	* @returns VBox status code.
499	* @param pCtl The controller instance.
500	* @param pSSM SSM operation handle.
501	*/
502	int ataControllerLoadPrep(PATACONTROLLER pCtl, PSSMHANDLE pSSM);
503
504	#endif /* IN_RING3 */
505
506	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
507	#endif /* !___Storage_ATAController_h */
508

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source: vbox/trunk/src/VBox/Devices/Storage/ATAController.h@ 15164

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