VirtualBox

source: vbox/trunk/src/VBox/Devices/Storage/ATAController.h@ 12571

Last change on this file since 12571 was 12508, checked in by vboxsync, 16 years ago

Device/Storage: fix CD/DVD media change problems in passthrough mode.
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1/* $Id: ATAController.h 12508 2008-09-16 16:52:11Z vboxsync $ */
2/** @file
3 * DevATA, DevAHCI - Shared ATA/ATAPI controller types.
4 */
5
6/*
7 * Copyright (C) 2006-2008 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___Storage_ATAController_h
23#define ___Storage_ATAController_h
24
25/*******************************************************************************
26* Header Files *
27*******************************************************************************/
28#include <VBox/pdmdev.h>
29#ifdef IN_RING3
30# include <iprt/semaphore.h>
31# include <iprt/thread.h>
32#endif /* IN_RING3 */
33#include <iprt/critsect.h>
34#include <VBox/stam.h>
35
36#include "PIIX3ATABmDma.h"
37#include "ide.h"
38
39
40/*******************************************************************************
41* Defined Constants And Macros *
42*******************************************************************************/
43/**
44 * Maximum number of sectors to transfer in a READ/WRITE MULTIPLE request.
45 * Set to 1 to disable multi-sector read support. According to the ATA
46 * specification this must be a power of 2 and it must fit in an 8 bit
47 * value. Thus the only valid values are 1, 2, 4, 8, 16, 32, 64 and 128.
48 */
49#define ATA_MAX_MULT_SECTORS 128
50
51/**
52 * Fastest PIO mode supported by the drive.
53 */
54#define ATA_PIO_MODE_MAX 4
55/**
56 * Fastest MDMA mode supported by the drive.
57 */
58#define ATA_MDMA_MODE_MAX 2
59/**
60 * Fastest UDMA mode supported by the drive.
61 */
62#define ATA_UDMA_MODE_MAX 6
63
64/** ATAPI sense info size. */
65#define ATAPI_SENSE_SIZE 64
66
67/** The maximum number of release log entries per device. */
68#define MAX_LOG_REL_ERRORS 1024
69
70
71/*******************************************************************************
72* Structures and Typedefs *
73*******************************************************************************/
74typedef struct ATADevState {
75 /** Flag indicating whether the current command uses LBA48 mode. */
76 bool fLBA48;
77 /** Flag indicating whether this drive implements the ATAPI command set. */
78 bool fATAPI;
79 /** Set if this interface has asserted the IRQ. */
80 bool fIrqPending;
81 /** Currently configured number of sectors in a multi-sector transfer. */
82 uint8_t cMultSectors;
83 /** PCHS disk geometry. */
84 PDMMEDIAGEOMETRY PCHSGeometry;
85 /** Total number of sectors on this disk. */
86 uint64_t cTotalSectors;
87 /** Number of sectors to transfer per IRQ. */
88 uint32_t cSectorsPerIRQ;
89
90 /** ATA/ATAPI register 1: feature (write-only). */
91 uint8_t uATARegFeature;
92 /** ATA/ATAPI register 1: feature, high order byte. */
93 uint8_t uATARegFeatureHOB;
94 /** ATA/ATAPI register 1: error (read-only). */
95 uint8_t uATARegError;
96 /** ATA/ATAPI register 2: sector count (read/write). */
97 uint8_t uATARegNSector;
98 /** ATA/ATAPI register 2: sector count, high order byte. */
99 uint8_t uATARegNSectorHOB;
100 /** ATA/ATAPI register 3: sector (read/write). */
101 uint8_t uATARegSector;
102 /** ATA/ATAPI register 3: sector, high order byte. */
103 uint8_t uATARegSectorHOB;
104 /** ATA/ATAPI register 4: cylinder low (read/write). */
105 uint8_t uATARegLCyl;
106 /** ATA/ATAPI register 4: cylinder low, high order byte. */
107 uint8_t uATARegLCylHOB;
108 /** ATA/ATAPI register 5: cylinder high (read/write). */
109 uint8_t uATARegHCyl;
110 /** ATA/ATAPI register 5: cylinder high, high order byte. */
111 uint8_t uATARegHCylHOB;
112 /** ATA/ATAPI register 6: select drive/head (read/write). */
113 uint8_t uATARegSelect;
114 /** ATA/ATAPI register 7: status (read-only). */
115 uint8_t uATARegStatus;
116 /** ATA/ATAPI register 7: command (write-only). */
117 uint8_t uATARegCommand;
118 /** ATA/ATAPI drive control register (write-only). */
119 uint8_t uATARegDevCtl;
120
121 /** Currently active transfer mode (MDMA/UDMA) and speed. */
122 uint8_t uATATransferMode;
123 /** Current transfer direction. */
124 uint8_t uTxDir;
125 /** Index of callback for begin transfer. */
126 uint8_t iBeginTransfer;
127 /** Index of callback for source/sink of data. */
128 uint8_t iSourceSink;
129 /** Flag indicating whether the current command transfers data in DMA mode. */
130 bool fDMA;
131 /** Set to indicate that ATAPI transfer semantics must be used. */
132 bool fATAPITransfer;
133
134 /** Total ATA/ATAPI transfer size, shared PIO/DMA. */
135 uint32_t cbTotalTransfer;
136 /** Elementary ATA/ATAPI transfer size, shared PIO/DMA. */
137 uint32_t cbElementaryTransfer;
138 /** Current read/write buffer position, shared PIO/DMA. */
139 uint32_t iIOBufferCur;
140 /** First element beyond end of valid buffer content, shared PIO/DMA. */
141 uint32_t iIOBufferEnd;
142
143 /** ATA/ATAPI current PIO read/write transfer position. Not shared with DMA for safety reasons. */
144 uint32_t iIOBufferPIODataStart;
145 /** ATA/ATAPI current PIO read/write transfer end. Not shared with DMA for safety reasons. */
146 uint32_t iIOBufferPIODataEnd;
147
148 /** ATAPI current LBA position. */
149 uint32_t iATAPILBA;
150 /** ATAPI current sector size. */
151 uint32_t cbATAPISector;
152 /** ATAPI current command. */
153 uint8_t aATAPICmd[ATAPI_PACKET_SIZE];
154 /** ATAPI sense data. */
155 uint8_t abATAPISense[ATAPI_SENSE_SIZE];
156 /** HACK: Countdown till we report a newly unmounted drive as mounted. */
157 uint8_t cNotifiedMediaChange;
158
159 /** The status LED state for this drive. */
160 PDMLED Led;
161
162 /** Size of I/O buffer. */
163 uint32_t cbIOBuffer;
164 /** Pointer to the I/O buffer. */
165 R3PTRTYPE(uint8_t *) pbIOBufferR3;
166 /** Pointer to the I/O buffer. */
167 R0PTRTYPE(uint8_t *) pbIOBufferR0;
168 /** Pointer to the I/O buffer. */
169 RCPTRTYPE(uint8_t *) pbIOBufferRC;
170#if 1 /*HC_ARCH_BITS == 64*/
171 RTRCPTR Aligmnent0; /**< Align the statistics at an 8-byte boundrary. */
172#endif
173
174 /*
175 * No data that is part of the saved state after this point!!!!!
176 */
177
178 /* Release statistics: number of ATA DMA commands. */
179 STAMCOUNTER StatATADMA;
180 /* Release statistics: number of ATA PIO commands. */
181 STAMCOUNTER StatATAPIO;
182 /* Release statistics: number of ATAPI PIO commands. */
183 STAMCOUNTER StatATAPIDMA;
184 /* Release statistics: number of ATAPI PIO commands. */
185 STAMCOUNTER StatATAPIPIO;
186#ifdef VBOX_INSTRUMENT_DMA_WRITES
187 /* Release statistics: number of DMA sector writes and the time spent. */
188 STAMPROFILEADV StatInstrVDWrites;
189#endif
190
191 /** Statistics: number of read operations and the time spent reading. */
192 STAMPROFILEADV StatReads;
193 /** Statistics: number of bytes read. */
194 STAMCOUNTER StatBytesRead;
195 /** Statistics: number of write operations and the time spent writing. */
196 STAMPROFILEADV StatWrites;
197 /** Statistics: number of bytes written. */
198 STAMCOUNTER StatBytesWritten;
199 /** Statistics: number of flush operations and the time spend flushing. */
200 STAMPROFILE StatFlushes;
201
202 /** Enable passing through commands directly to the ATAPI drive. */
203 bool fATAPIPassthrough;
204 /** Number of errors we've reported to the release log.
205 * This is to prevent flooding caused by something going horribly wrong.
206 * this value against MAX_LOG_REL_ERRORS in places likely to cause floods
207 * like the ones we currently seeing on the linux smoke tests (2006-11-10). */
208 uint32_t cErrors;
209 /** Timestamp of last started command. 0 if no command pending. */
210 uint64_t u64CmdTS;
211
212 /** Pointer to the attached driver's base interface. */
213 R3PTRTYPE(PPDMIBASE) pDrvBase;
214 /** Pointer to the attached driver's block interface. */
215 R3PTRTYPE(PPDMIBLOCK) pDrvBlock;
216 /** Pointer to the attached driver's block bios interface. */
217 R3PTRTYPE(PPDMIBLOCKBIOS) pDrvBlockBios;
218 /** Pointer to the attached driver's mount interface.
219 * This is NULL if the driver isn't a removable unit. */
220 R3PTRTYPE(PPDMIMOUNT) pDrvMount;
221 /** The base interface. */
222 PDMIBASE IBase;
223 /** The block port interface. */
224 PDMIBLOCKPORT IPort;
225 /** The mount notify interface. */
226 PDMIMOUNTNOTIFY IMountNotify;
227 /** The LUN #. */
228 RTUINT iLUN;
229#if HC_ARCH_BITS == 64
230 RTUINT Alignment2; /**< Align pDevInsR3 correctly. */
231#endif
232 /** Pointer to device instance. */
233 PPDMDEVINSR3 pDevInsR3;
234 /** Pointer to controller instance. */
235 R3PTRTYPE(struct ATACONTROLLER *) pControllerR3;
236 /** Pointer to device instance. */
237 PPDMDEVINSR0 pDevInsR0;
238 /** Pointer to controller instance. */
239 R0PTRTYPE(struct ATACONTROLLER *) pControllerR0;
240 /** Pointer to device instance. */
241 PPDMDEVINSRC pDevInsRC;
242 /** Pointer to controller instance. */
243 RCPTRTYPE(struct ATACONTROLLER *) pControllerRC;
244} ATADevState;
245
246
247typedef struct ATATransferRequest
248{
249 uint8_t iIf;
250 uint8_t iBeginTransfer;
251 uint8_t iSourceSink;
252 uint32_t cbTotalTransfer;
253 uint8_t uTxDir;
254} ATATransferRequest;
255
256
257typedef struct ATAAbortRequest
258{
259 uint8_t iIf;
260 bool fResetDrive;
261} ATAAbortRequest;
262
263
264typedef enum
265{
266 /** Begin a new transfer. */
267 ATA_AIO_NEW = 0,
268 /** Continue a DMA transfer. */
269 ATA_AIO_DMA,
270 /** Continue a PIO transfer. */
271 ATA_AIO_PIO,
272 /** Reset the drives on current controller, stop all transfer activity. */
273 ATA_AIO_RESET_ASSERTED,
274 /** Reset the drives on current controller, resume operation. */
275 ATA_AIO_RESET_CLEARED,
276 /** Abort the current transfer of a particular drive. */
277 ATA_AIO_ABORT
278} ATAAIO;
279
280
281typedef struct ATARequest
282{
283 ATAAIO ReqType;
284 union
285 {
286 ATATransferRequest t;
287 ATAAbortRequest a;
288 } u;
289} ATARequest;
290
291
292typedef struct ATACONTROLLER
293{
294 /** The base of the first I/O Port range. */
295 RTIOPORT IOPortBase1;
296 /** The base of the second I/O Port range. (0 if none) */
297 RTIOPORT IOPortBase2;
298 /** The assigned IRQ. */
299 RTUINT irq;
300 /** Access critical section */
301 PDMCRITSECT lock;
302
303 /** Selected drive. */
304 uint8_t iSelectedIf;
305 /** The interface on which to handle async I/O. */
306 uint8_t iAIOIf;
307 /** The state of the async I/O thread. */
308 uint8_t uAsyncIOState;
309 /** Flag indicating whether the next transfer is part of the current command. */
310 bool fChainedTransfer;
311 /** Set when the reset processing is currently active on this controller. */
312 bool fReset;
313 /** Flag whether the current transfer needs to be redone. */
314 bool fRedo;
315 /** Flag whether the redo suspend has been finished. */
316 bool fRedoIdle;
317 /** Flag whether the DMA operation to be redone is the final transfer. */
318 bool fRedoDMALastDesc;
319 /** The BusMaster DMA state. */
320 BMDMAState BmDma;
321 /** Pointer to first DMA descriptor. */
322 RTGCPHYS32 pFirstDMADesc;
323 /** Pointer to last DMA descriptor. */
324 RTGCPHYS32 pLastDMADesc;
325 /** Pointer to current DMA buffer (for redo operations). */
326 RTGCPHYS32 pRedoDMABuffer;
327 /** Size of current DMA buffer (for redo operations). */
328 uint32_t cbRedoDMABuffer;
329
330 /** The ATA/ATAPI interfaces of this controller. */
331 ATADevState aIfs[2];
332
333 /** Pointer to device instance. */
334 PPDMDEVINSR3 pDevInsR3;
335 /** Pointer to device instance. */
336 PPDMDEVINSR0 pDevInsR0;
337 /** Pointer to device instance. */
338 PPDMDEVINSRC pDevInsRC;
339
340 /** Set when the destroying the device instance and the thread must exit. */
341 uint32_t volatile fShutdown;
342 /** The async I/O thread handle. NIL_RTTHREAD if no thread. */
343 RTTHREAD AsyncIOThread;
344 /** The event semaphore the thread is waiting on for requests. */
345 RTSEMEVENT AsyncIOSem;
346 /** The request queue for the AIO thread. One element is always unused. */
347 ATARequest aAsyncIORequests[4];
348 /** The position at which to insert a new request for the AIO thread. */
349 uint8_t AsyncIOReqHead;
350 /** The position at which to get a new request for the AIO thread. */
351 uint8_t AsyncIOReqTail;
352 uint8_t Alignment3[2]; /**< Explicit padding of the 2 byte gap. */
353 /** Magic delay before triggering interrupts in DMA mode. */
354 uint32_t DelayIRQMillies;
355 /** The mutex protecting the request queue. */
356 RTSEMMUTEX AsyncIORequestMutex;
357 /** The event semaphore the thread is waiting on during suspended I/O. */
358 RTSEMEVENT SuspendIOSem;
359#if 0 /*HC_ARCH_BITS == 32*/
360 uint32_t Alignment0;
361#endif
362
363 /* Statistics */
364 STAMCOUNTER StatAsyncOps;
365 uint64_t StatAsyncMinWait;
366 uint64_t StatAsyncMaxWait;
367 STAMCOUNTER StatAsyncTimeUS;
368 STAMPROFILEADV StatAsyncTime;
369 STAMPROFILE StatLockWait;
370} ATACONTROLLER, *PATACONTROLLER;
371
372#ifndef VBOX_DEVICE_STRUCT_TESTCASE
373
374#define ATADEVSTATE_2_CONTROLLER(pIf) ( (pIf)->CTX_SUFF(pController) )
375#define ATADEVSTATE_2_DEVINS(pIf) ( (pIf)->CTX_SUFF(pDevIns) )
376#define CONTROLLER_2_DEVINS(pController) ( (pController)->CTX_SUFF(pDevIns) )
377#define PDMIBASE_2_ATASTATE(pInterface) ( (ATADevState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ATADevState, IBase)) )
378
379
380/*******************************************************************************
381 * Internal Functions *
382 ******************************************************************************/
383__BEGIN_DECLS
384int ataControllerIOPortWrite1(PATACONTROLLER pCtl, RTIOPORT Port, uint32_t u32, unsigned cb);
385int ataControllerIOPortRead1(PATACONTROLLER pCtl, RTIOPORT Port, uint32_t *u32, unsigned cb);
386int ataControllerIOPortWriteStr1(PATACONTROLLER pCtl, RTIOPORT Port, RTGCPTR *pGCPtrSrc, PRTGCUINTREG pcTransfer, unsigned cb);
387int ataControllerIOPortReadStr1(PATACONTROLLER pCtl, RTIOPORT Port, RTGCPTR *pGCPtrDst, PRTGCUINTREG pcTransfer, unsigned cb);
388int ataControllerIOPortWrite2(PATACONTROLLER pCtl, RTIOPORT Port, uint32_t u32, unsigned cb);
389int ataControllerIOPortRead2(PATACONTROLLER pCtl, RTIOPORT Port, uint32_t *u32, unsigned cb);
390int ataControllerBMDMAIOPortRead(PATACONTROLLER pCtl, RTIOPORT Port, uint32_t *pu32, unsigned cb);
391int ataControllerBMDMAIOPortWrite(PATACONTROLLER pCtl, RTIOPORT Port, uint32_t u32, unsigned cb);
392__END_DECLS
393
394#ifdef IN_RING3
395/**
396 * Initialize a controller state.
397 *
398 * @returns VBox status code.
399 * @param pDevIns Pointer to the device instance which creates a controller.
400 * @param pCtl Pointer to the unitialized ATA controller structure.
401 * @param pDrvBaseMaster Pointer to the base driver interface which acts as the master.
402 * @param pDrvBaseSlave Pointer to the base driver interface which acts as the slave.
403 * @param pcbSSMState Where to store the size of the device state for loading/saving.
404 * @param szName Name of the controller (Used to initialize the critical section).
405 */
406int ataControllerInit(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PPDMIBASE pDrvBaseMaster, PPDMIBASE pDrvBaseSlave,
407 uint32_t *pcbSSMState, const char *szName);
408
409/**
410 * Free all allocated resources for one controller instance.
411 *
412 * @returns VBox status code.
413 * @param pCtl The controller instance.
414 */
415int ataControllerDestroy(PATACONTROLLER pCtl);
416
417/**
418 * Power off a controller.
419 *
420 * @returns nothing.
421 * @param pCtl the controller instance.
422 */
423void ataControllerPowerOff(PATACONTROLLER pCtl);
424
425/**
426 * Reset a controller instance to an initial state.
427 *
428 * @returns VBox status code.
429 * @param pCtl Pointer to the controller.
430 */
431void ataControllerReset(PATACONTROLLER pCtl);
432
433/**
434 * Suspend operation of an controller.
435 *
436 * @returns nothing
437 * @param pCtl The controller instance.
438 */
439void ataControllerSuspend(PATACONTROLLER pCtl);
440
441/**
442 * Resume operation of an controller.
443 *
444 * @returns nothing
445 * @param pCtl The controller instance.
446 */
447
448void ataControllerResume(PATACONTROLLER pCtl);
449
450/**
451 * Relocate neccessary pointers.
452 *
453 * @returns nothing.
454 * @param pCtl The controller instance.
455 * @param offDelta The relocation delta relative to the old location.
456 */
457void ataControllerRelocate(PATACONTROLLER pCtl, RTGCINTPTR offDelta);
458
459/**
460 * Execute state save operation.
461 *
462 * @returns VBox status code.
463 * @param pCtl The controller instance.
464 * @param pSSM SSM operation handle.
465 */
466int ataControllerSaveExec(PATACONTROLLER pCtl, PSSMHANDLE pSSM);
467
468/**
469 * Prepare state save operation.
470 *
471 * @returns VBox status code.
472 * @param pCtl The controller instance.
473 * @param pSSM SSM operation handle.
474 */
475int ataControllerSavePrep(PATACONTROLLER pCtl, PSSMHANDLE pSSM);
476
477/**
478 * Excute state load operation.
479 *
480 * @returns VBox status code.
481 * @param pCtl The controller instance.
482 * @param pSSM SSM operation handle.
483 */
484int ataControllerLoadExec(PATACONTROLLER pCtl, PSSMHANDLE pSSM);
485
486/**
487 * Prepare state load operation.
488 *
489 * @returns VBox status code.
490 * @param pCtl The controller instance.
491 * @param pSSM SSM operation handle.
492 */
493int ataControllerLoadPrep(PATACONTROLLER pCtl, PSSMHANDLE pSSM);
494
495#endif /* IN_RING3 */
496
497#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
498#endif /* !___Storage_ATAController_h */
499
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