VirtualBox

source: vbox/trunk/src/VBox/Devices/Storage/DevAHCI.cpp@ 26165

Last change on this file since 26165 was 26165, checked in by vboxsync, 15 years ago

PDM: s/szDeviceName/szName/g - PDMDEVREG & PDMUSBREG.
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1/* $Id: DevAHCI.cpp 26165 2010-02-02 19:50:31Z vboxsync $ */
2/** @file
3 * VBox storage devices: AHCI controller device (disk and cdrom).
4 * Implements the AHCI standard 1.1
5 */
6
7/*
8 * Copyright (C) 2006-2009 Sun Microsystems, Inc.
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License (GPL) as published by the Free Software
14 * Foundation, in version 2 as it comes in the "COPYING" file of the
15 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17 *
18 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
19 * Clara, CA 95054 USA or visit http://www.sun.com if you need
20 * additional information or have any questions.
21 */
22
23/** @page pg_dev_ahci AHCI - Advanced Host Controller Interface Emulation.
24 *
25 * This component implements an AHCI serial ATA controller. The device is split
26 * into two parts. The first part implements the register interface for the
27 * guest and the second one does the data transfer.
28 *
29 * The guest can access the controller in two ways. The first one is the native
30 * way implementing the registers described in the AHCI specification and is
31 * the preferred one. The second implements the I/O ports used for booting from
32 * the hard disk and for guests which don't have an AHCI SATA driver.
33 *
34 * The data is transfered in an asychronous way using one thread per implemented
35 * port or using the new async completion interface which is still under
36 * development. [not quite up to date]
37 */
38
39/*******************************************************************************
40* Header Files *
41*******************************************************************************/
42//#define DEBUG
43#define LOG_GROUP LOG_GROUP_DEV_AHCI
44#include <VBox/pdmdev.h>
45#include <VBox/pdmqueue.h>
46#include <VBox/pdmthread.h>
47#include <VBox/pdmcritsect.h>
48#include <VBox/scsi.h>
49#include <iprt/assert.h>
50#include <iprt/asm.h>
51#include <iprt/string.h>
52#ifdef IN_RING3
53# include <iprt/param.h>
54# include <iprt/thread.h>
55# include <iprt/semaphore.h>
56# include <iprt/alloc.h>
57# include <iprt/uuid.h>
58# include <iprt/time.h>
59#endif
60
61#include "ide.h"
62#include "ATAController.h"
63#include "../Builtins.h"
64
65#define AHCI_MAX_NR_PORTS_IMPL 30
66#define AHCI_NR_COMMAND_SLOTS 32
67#define AHCI_NR_OF_ALLOWED_BIGGER_LISTS 100
68
69/** The current saved state version. */
70#define AHCI_SAVED_STATE_VERSION 3
71/** The saved state version use in VirtualBox 3.0 and earlier.
72 * This was before the config was added and ahciIOTasks was dropped. */
73#define AHCI_SAVED_STATE_VERSION_VBOX_30 2
74
75/**
76 * Maximum number of sectors to transfer in a READ/WRITE MULTIPLE request.
77 * Set to 1 to disable multi-sector read support. According to the ATA
78 * specification this must be a power of 2 and it must fit in an 8 bit
79 * value. Thus the only valid values are 1, 2, 4, 8, 16, 32, 64 and 128.
80 */
81#define ATA_MAX_MULT_SECTORS 128
82
83/**
84 * Fastest PIO mode supported by the drive.
85 */
86#define ATA_PIO_MODE_MAX 4
87/**
88 * Fastest MDMA mode supported by the drive.
89 */
90#define ATA_MDMA_MODE_MAX 2
91/**
92 * Fastest UDMA mode supported by the drive.
93 */
94#define ATA_UDMA_MODE_MAX 6
95
96/**
97 * Length of the configurable VPD data (without termination)
98 */
99#define AHCI_SERIAL_NUMBER_LENGTH 20
100#define AHCI_FIRMWARE_REVISION_LENGTH 8
101#define AHCI_MODEL_NUMBER_LENGTH 40
102#define AHCI_ATAPI_INQUIRY_VENDOR_ID_LENGTH 8
103#define AHCI_ATAPI_INQUIRY_PRODUCT_ID_LENGTH 16
104#define AHCI_ATAPI_INQUIRY_REVISION_LENGTH 4
105
106/* Command Header. */
107typedef struct
108{
109 /** Description Information. */
110 uint32_t u32DescInf;
111 /** Command status. */
112 uint32_t u32PRDBC;
113 /** Command Table Base Address. */
114 uint32_t u32CmdTblAddr;
115 /** Command Table Base Address - upper 32-bits. */
116 uint32_t u32CmdTblAddrUp;
117 /** Reserved */
118 uint32_t u32Reserved[4];
119} CmdHdr;
120AssertCompileSize(CmdHdr, 32);
121
122/* Defines for the command header. */
123#define AHCI_CMDHDR_PRDTL_MASK 0xffff0000
124#define AHCI_CMDHDR_PRDTL_ENTRIES(x) ((x & AHCI_CMDHDR_PRDTL_MASK) >> 16)
125#define AHCI_CMDHDR_C RT_BIT(10)
126#define AHCI_CMDHDR_B RT_BIT(9)
127#define AHCI_CMDHDR_R RT_BIT(8)
128#define AHCI_CMDHDR_P RT_BIT(7)
129#define AHCI_CMDHDR_W RT_BIT(6)
130#define AHCI_CMDHDR_A RT_BIT(5)
131#define AHCI_CMDHDR_CFL_MASK 0x1f
132
133#define AHCI_CMDHDR_PRDT_OFFSET 0x80
134#define AHCI_CMDHDR_ACMD_OFFSET 0x40
135
136/* Defines for the command FIS. */
137/* Defines that are used in the first double word. */
138#define AHCI_CMDFIS_TYPE 0 /* The first byte. */
139# define AHCI_CMDFIS_TYPE_H2D 0x27 /* Register - Host to Device FIS. */
140# define AHCI_CMDFIS_TYPE_H2D_SIZE 20 /* Five double words. */
141# define AHCI_CMDFIS_TYPE_D2H 0x34 /* Register - Device to Host FIS. */
142# define AHCI_CMDFIS_TYPE_D2H_SIZE 20 /* Five double words. */
143# define AHCI_CMDFIS_TYPE_SETDEVBITS 0xa1 /* Set Device Bits - Device to Host FIS. */
144# define AHCI_CMDFIS_TYPE_SETDEVBITS_SIZE 8 /* Two double words. */
145# define AHCI_CMDFIS_TYPE_DMAACTD2H 0x39 /* DMA Activate - Device to Host FIS. */
146# define AHCI_CMDFIS_TYPE_DMAACTD2H_SIZE 4 /* One double word. */
147# define AHCI_CMDFIS_TYPE_DMASETUP 0x41 /* DMA Setup - Bidirectional FIS. */
148# define AHCI_CMDFIS_TYPE_DMASETUP_SIZE 28 /* Seven double words. */
149# define AHCI_CMDFIS_TYPE_PIOSETUP 0x5f /* PIO Setup - Device to Host FIS. */
150# define AHCI_CMDFIS_TYPE_PIOSETUP_SIZE 20 /* Five double words. */
151# define AHCI_CMDFIS_TYPE_DATA 0x46 /* Data - Bidirectional FIS. */
152
153#define AHCI_CMDFIS_BITS 1 /* Interrupt and Update bit. */
154#define AHCI_CMDFIS_C RT_BIT(7) /* Host to device. */
155#define AHCI_CMDFIS_I RT_BIT(6) /* Device to Host. */
156
157#define AHCI_CMDFIS_CMD 2
158#define AHCI_CMDFIS_FET 3
159
160#define AHCI_CMDFIS_SECTN 4
161#define AHCI_CMDFIS_CYLL 5
162#define AHCI_CMDFIS_CYLH 6
163#define AHCI_CMDFIS_HEAD 7
164
165#define AHCI_CMDFIS_SECTNEXP 8
166#define AHCI_CMDFIS_CYLLEXP 9
167#define AHCI_CMDFIS_CYLHEXP 10
168#define AHCI_CMDFIS_FETEXP 11
169
170#define AHCI_CMDFIS_SECTC 12
171#define AHCI_CMDFIS_SECTCEXP 13
172#define AHCI_CMDFIS_CTL 15
173# define AHCI_CMDFIS_CTL_SRST RT_BIT(2) /* Reset device. */
174# define AHCI_CMDFIS_CTL_NIEN RT_BIT(1) /* Assert or clear interrupt. */
175
176/* For D2H FIS */
177#define AHCI_CMDFIS_STS 2
178#define AHCI_CMDFIS_ERR 3
179
180/**
181 * Scatter gather list entry data.
182 */
183typedef struct AHCIPORTTASKSTATESGENTRY
184{
185 /** Flag whether the buffer in the list is from the guest or an
186 * allocated temporary buffer because the segments in the guest
187 * are not sector aligned.
188 */
189 bool fGuestMemory;
190 /** Flag dependent data. */
191 union
192 {
193 /** Data to handle direct mappings of guest buffers. */
194 struct
195 {
196 /** The page lock. */
197 PGMPAGEMAPLOCK PageLock;
198 } direct;
199 /** Data to handle temporary buffers. */
200 struct
201 {
202 /** The first segment in the guest which is not sector aligned. */
203 RTGCPHYS GCPhysAddrBaseFirstUnaligned;
204 /** Number of unaligned buffers in the guest. */
205 uint32_t cUnaligned;
206 /** Pointer to the start of the buffer. */
207 void *pvBuf;
208 } temp;
209 } u;
210} AHCIPORTTASKSTATESGENTRY, *PAHCIPORTTASKSTATESGENTRY;
211
212/** Pointer to a pointer of a scatter gather list entry. */
213typedef PAHCIPORTTASKSTATESGENTRY *PPAHCIPORTTASKSTATESGENTRY;
214/** Pointer to a task state. */
215typedef struct AHCIPORTTASKSTATE *PAHCIPORTTASKSTATE;
216
217/**
218 * Data processing callback
219 *
220 * @returns VBox status.
221 * @param pAhciPortTaskState The task state.
222 */
223typedef DECLCALLBACK(int) FNAHCIPOSTPROCESS(PAHCIPORTTASKSTATE pAhciPortTaskState);
224/** Pointer to a FNAHCIPOSTPROCESS() function. */
225typedef FNAHCIPOSTPROCESS *PFNAHCIPOSTPROCESS;
226
227/**
228 * A task state.
229 */
230typedef struct AHCIPORTTASKSTATE
231{
232 /** Tag of the task. */
233 uint32_t uTag;
234 /** Command is queued. */
235 bool fQueued;
236 /** The command header for this task. */
237 CmdHdr cmdHdr;
238 /** The command Fis for this task. */
239 uint8_t cmdFis[AHCI_CMDFIS_TYPE_H2D_SIZE];
240 /** The ATAPI comnmand data. */
241 uint8_t aATAPICmd[ATAPI_PACKET_SIZE];
242 /** Physical address of the command header. - GC */
243 RTGCPHYS GCPhysCmdHdrAddr;
244 /** Data direction. */
245 uint8_t uTxDir;
246 /** Start offset. */
247 uint64_t uOffset;
248 /** Number of bytes to transfer. */
249 uint32_t cbTransfer;
250 /** ATA error register */
251 uint8_t uATARegError;
252 /** ATA status register */
253 uint8_t uATARegStatus;
254 /** How many entries would fit into the sg list. */
255 uint32_t cSGListSize;
256 /** Number of used SG list entries. */
257 uint32_t cSGListUsed;
258 /** Pointer to the first entry of the scatter gather list. */
259 PPDMDATASEG pSGListHead;
260 /** Number of scatter gather list entries. */
261 uint32_t cSGEntries;
262 /** Total number of bytes the guest reserved for this request.
263 * Sum of all SG entries. */
264 uint32_t cbSGBuffers;
265 /** Pointer to the first mapping information entry. */
266 PAHCIPORTTASKSTATESGENTRY paSGEntries;
267 /** Size of the temporary buffer for unaligned guest segments. */
268 uint32_t cbBufferUnaligned;
269 /** Pointer to the temporary buffer. */
270 void *pvBufferUnaligned;
271 /** Number of times in a row the scatter gather list was too big. */
272 uint32_t cSGListTooBig;
273 /** Post processing callback.
274 * If this is set we will use a buffer for the data
275 * and the callback copies the data to the destination. */
276 PFNAHCIPOSTPROCESS pfnPostProcess;
277} AHCIPORTTASKSTATE;
278
279/**
280 * Notifier queue item.
281 */
282typedef struct DEVPORTNOTIFIERQUEUEITEM
283{
284 /** The core part owned by the queue manager. */
285 PDMQUEUEITEMCORE Core;
286 /** On which port the async io thread should be put into action. */
287 uint8_t iPort;
288 /** Which task to process. */
289 uint8_t iTask;
290 /** Flag whether the task is queued. */
291 uint8_t fQueued;
292} DEVPORTNOTIFIERQUEUEITEM, *PDEVPORTNOTIFIERQUEUEITEM;
293
294
295/**
296 * @implements PDMIBASE
297 * @implements PDMIBLOCKPORT
298 * @implements PDMIBLOCKASYNCPORT
299 * @implements PDMIMOUNTNOTIFY
300 */
301typedef struct AHCIPort
302{
303 /** Pointer to the device instance - HC ptr */
304 PPDMDEVINSR3 pDevInsR3;
305 /** Pointer to the device instance - R0 ptr */
306 PPDMDEVINSR0 pDevInsR0;
307 /** Pointer to the device instance - RC ptr. */
308 PPDMDEVINSRC pDevInsRC;
309
310#if HC_ARCH_BITS == 64
311 uint32_t Alignment0;
312#endif
313
314 /** Pointer to the parent AHCI structure - R3 ptr. */
315 R3PTRTYPE(struct AHCI *) pAhciR3;
316 /** Pointer to the parent AHCI structure - R0 ptr. */
317 R0PTRTYPE(struct AHCI *) pAhciR0;
318 /** Pointer to the parent AHCI structure - RC ptr. */
319 RCPTRTYPE(struct AHCI *) pAhciRC;
320 /** Command List Base Address. */
321 uint32_t regCLB;
322 /** Command List Base Address upper bits. */
323 uint32_t regCLBU;
324 /** FIS Base Address. */
325 uint32_t regFB;
326 /** FIS Base Address upper bits. */
327 uint32_t regFBU;
328 /** Interrupt Status. */
329 volatile uint32_t regIS;
330 /** Interrupt Enable. */
331 uint32_t regIE;
332 /** Command. */
333 uint32_t regCMD;
334 /** Task File Data. */
335 uint32_t regTFD;
336 /** Signature */
337 uint32_t regSIG;
338 /** Serial ATA Status. */
339 uint32_t regSSTS;
340 /** Serial ATA Control. */
341 uint32_t regSCTL;
342 /** Serial ATA Error. */
343 uint32_t regSERR;
344 /** Serial ATA Active. */
345 uint32_t regSACT;
346 /** Command Issue. */
347 uint32_t regCI;
348
349#if HC_ARCH_BITS == 64
350 uint32_t Alignment1;
351#endif
352
353 /** Command List Base Address */
354 volatile RTGCPHYS GCPhysAddrClb;
355 /** FIS Base Address */
356 volatile RTGCPHYS GCPhysAddrFb;
357
358 /** If we use the new async interface. */
359 bool fAsyncInterface;
360
361#if HC_ARCH_BITS == 64
362 uint32_t Alignment2;
363#endif
364
365 /** Async IO Thread. */
366 PPDMTHREAD pAsyncIOThread;
367 /** Request semaphore. */
368 RTSEMEVENT AsyncIORequestSem;
369
370 /** Task queue. */
371 volatile uint8_t ahciIOTasks[2*AHCI_NR_COMMAND_SLOTS];
372 /** Actual write position. */
373 uint8_t uActWritePos;
374 /** Actual read position. */
375 uint8_t uActReadPos;
376 /** Actual number of active tasks. */
377 volatile uint32_t uActTasksActive;
378
379 /** Device is powered on. */
380 bool fPoweredOn;
381 /** Device has spun up. */
382 bool fSpunUp;
383 /** First D2H FIS was send. */
384 bool fFirstD2HFisSend;
385 /** Attached device is a CD/DVD drive. */
386 bool fATAPI;
387
388#if HC_ARCH_BITS == 64
389 uint32_t Alignment3;
390#endif
391
392 /** Device specific settings. */
393 /** Pointer to the attached driver's base interface. */
394 R3PTRTYPE(PPDMIBASE) pDrvBase;
395 /** Pointer to the attached driver's block interface. */
396 R3PTRTYPE(PPDMIBLOCK) pDrvBlock;
397 /** Pointer to the attached driver's async block interface. */
398 R3PTRTYPE(PPDMIBLOCKASYNC) pDrvBlockAsync;
399 /** Pointer to the attached driver's block bios interface. */
400 R3PTRTYPE(PPDMIBLOCKBIOS) pDrvBlockBios;
401 /** Pointer to the attached driver's mount interface. */
402 R3PTRTYPE(PPDMIMOUNT) pDrvMount;
403 /** The base interface. */
404 PDMIBASE IBase;
405 /** The block port interface. */
406 PDMIBLOCKPORT IPort;
407 /** The optional block async port interface. */
408 PDMIBLOCKASYNCPORT IPortAsync;
409 /** The mount notify interface. */
410 PDMIMOUNTNOTIFY IMountNotify;
411 /** Physical geometry of this image. */
412 PDMMEDIAGEOMETRY PCHSGeometry;
413 /** The status LED state for this drive. */
414 PDMLED Led;
415
416#if HC_ARCH_BITS == 64
417 uint32_t Alignment4;
418#endif
419
420 /** Number of total sectors. */
421 uint64_t cTotalSectors;
422 /** Currently configured number of sectors in a multi-sector transfer. */
423 uint32_t cMultSectors;
424 /** Currently active transfer mode (MDMA/UDMA) and speed. */
425 uint8_t uATATransferMode;
426 /** ATAPI sense key. */
427 uint8_t uATAPISenseKey;
428 /** ATAPI additional sens code. */
429 uint8_t uATAPIASC;
430 /** HACK: Countdown till we report a newly unmounted drive as mounted. */
431 uint8_t cNotifiedMediaChange;
432
433 /** The LUN. */
434 RTUINT iLUN;
435 /** Flag if we are in a device reset. */
436 bool fResetDevice;
437
438 /** Bitmask for finished tasks. */
439 volatile uint32_t u32TasksFinished;
440 /** Bitmask for finished queued tasks. */
441 volatile uint32_t u32QueuedTasksFinished;
442
443 /**
444 * Array of cached tasks. The tag number is the index value.
445 * Only used with the async interface.
446 */
447 R3PTRTYPE(PAHCIPORTTASKSTATE) aCachedTasks[AHCI_NR_COMMAND_SLOTS];
448
449 uint32_t u32Alignment5[4];
450
451#if HC_ARCH_BITS == 32
452 uint32_t u32Alignment6;
453#endif
454
455 /** Release statistics: number of DMA commands. */
456 STAMCOUNTER StatDMA;
457 /** Release statistics: number of bytes written. */
458 STAMCOUNTER StatBytesWritten;
459 /** Release statistics: number of bytes read. */
460 STAMCOUNTER StatBytesRead;
461 /** Release statistics: Number of I/O requests processed per second. */
462 STAMCOUNTER StatIORequestsPerSecond;
463#ifdef VBOX_WITH_STATISTICS
464 /** Statistics: Time to complete one request. */
465 STAMPROFILE StatProfileProcessTime;
466 /** Statistics: Time to map requests into R3. */
467 STAMPROFILE StatProfileMapIntoR3;
468 /** Statistics: Amount of time to read/write data. */
469 STAMPROFILE StatProfileReadWrite;
470 /** Statistics: Amount of time to destroy a list. */
471 STAMPROFILE StatProfileDestroyScatterGatherList;
472#endif /* VBOX_WITH_STATISTICS */
473 /** Flag whether a notification was already send to R3. */
474 volatile bool fNotificationSend;
475 /** Flag whether this port is in a reset state. */
476 volatile bool fPortReset;
477 /** Flag whether the I/O thread idles. */
478 volatile bool fAsyncIOThreadIdle;
479
480 /** The serial numnber to use for IDENTIFY DEVICE commands. */
481 char szSerialNumber[AHCI_SERIAL_NUMBER_LENGTH+1]; /** < one extra byte for termination */
482 /** The firmware revision to use for IDENTIFY DEVICE commands. */
483 char szFirmwareRevision[AHCI_FIRMWARE_REVISION_LENGTH+1]; /** < one extra byte for termination */
484 /** The model number to use for IDENTIFY DEVICE commands. */
485 char szModelNumber[AHCI_MODEL_NUMBER_LENGTH+1]; /** < one extra byte for termination */
486 /** The vendor identification string for SCSI INQUIRY commands. */
487 char szInquiryVendorId[AHCI_ATAPI_INQUIRY_VENDOR_ID_LENGTH+1];
488 /** The product identification string for SCSI INQUIRY commands. */
489 char szInquiryProductId[AHCI_ATAPI_INQUIRY_PRODUCT_ID_LENGTH+1];
490 /** The revision string for SCSI INQUIRY commands. */
491 char szInquiryRevision[AHCI_ATAPI_INQUIRY_REVISION_LENGTH+1];
492
493 uint32_t Alignment7;
494
495} AHCIPort;
496/** Pointer to the state of an AHCI port. */
497typedef AHCIPort *PAHCIPort;
498
499/**
500 * Main AHCI device state.
501 *
502 * @implements PDMILEDPORTS
503 */
504typedef struct AHCI
505{
506 /** The PCI device structure. */
507 PCIDEVICE dev;
508 /** Pointer to the device instance - R3 ptr */
509 PPDMDEVINSR3 pDevInsR3;
510 /** Pointer to the device instance - R0 ptr */
511 PPDMDEVINSR0 pDevInsR0;
512 /** Pointer to the device instance - RC ptr. */
513 PPDMDEVINSRC pDevInsRC;
514
515#if HC_ARCH_BITS == 64
516 uint32_t Alignment0;
517#endif
518
519 /** Status LUN: The base interface. */
520 PDMIBASE IBase;
521 /** Status LUN: Leds interface. */
522 PDMILEDPORTS ILeds;
523 /** Status LUN: Partner of ILeds. */
524 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
525
526#if HC_ARCH_BITS == 64
527 uint32_t Alignment1[2];
528#endif
529
530 /** Base address of the MMIO region. */
531 RTGCPHYS MMIOBase;
532
533 /** Global Host Control register of the HBA */
534
535 /** HBA Capabilities - Readonly */
536 uint32_t regHbaCap;
537 /** HBA Control */
538 uint32_t regHbaCtrl;
539 /** Interrupt Status */
540 uint32_t regHbaIs;
541 /** Ports Implemented - Readonly */
542 uint32_t regHbaPi;
543 /** AHCI Version - Readonly */
544 uint32_t regHbaVs;
545 /** Command completion coalescing control */
546 uint32_t regHbaCccCtl;
547 /** Command completion coalescing ports */
548 uint32_t regHbaCccPorts;
549
550#if HC_ARCH_BITS == 64
551 uint32_t Alignment3;
552#endif
553
554 /** Countdown timer for command completion coalescing - R3 ptr */
555 PTMTIMERR3 pHbaCccTimerR3;
556 /** Countdown timer for command completion coalescing - R0 ptr */
557 PTMTIMERR0 pHbaCccTimerR0;
558 /** Countdown timer for command completion coalescing - RC ptr */
559 PTMTIMERRC pHbaCccTimerRC;
560
561#if HC_ARCH_BITS == 64
562 uint32_t Alignment4;
563#endif
564
565 /** Queue to send tasks to R3. - HC ptr */
566 R3PTRTYPE(PPDMQUEUE) pNotifierQueueR3;
567 /** Queue to send tasks to R3. - HC ptr */
568 R0PTRTYPE(PPDMQUEUE) pNotifierQueueR0;
569 /** Queue to send tasks to R3. - RC ptr */
570 RCPTRTYPE(PPDMQUEUE) pNotifierQueueRC;
571
572#if HC_ARCH_BITS == 64
573 uint32_t Alignment5;
574#endif
575
576
577 /** Which port number is used to mark an CCC interrupt */
578 uint8_t uCccPortNr;
579
580#if HC_ARCH_BITS == 64
581 uint32_t Alignment6;
582#endif
583
584 /** Timeout value */
585 uint64_t uCccTimeout;
586 /** Number of completions used to assert an interrupt */
587 uint32_t uCccNr;
588 /** Current number of completed commands */
589 uint32_t uCccCurrentNr;
590
591 /** Register structure per port */
592 AHCIPort ahciPort[AHCI_MAX_NR_PORTS_IMPL];
593
594 /** Needed values for the emulated ide channels. */
595 AHCIATACONTROLLER aCts[2];
596
597 /** The critical section. */
598 PDMCRITSECT lock;
599
600 /** Bitmask of ports which asserted an interrupt. */
601 uint32_t u32PortsInterrupted;
602 /** Device is in a reset state. */
603 bool fReset;
604 /** Supports 64bit addressing */
605 bool f64BitAddr;
606 /** GC enabled. */
607 bool fGCEnabled;
608 /** R0 enabled. */
609 bool fR0Enabled;
610 /** If the new async interface is used if available. */
611 bool fUseAsyncInterfaceIfAvailable;
612 /** Indicates that PDMDevHlpAsyncNotificationCompleted should be called when
613 * a port is entering the idle state. */
614 bool volatile fSignalIdle;
615 bool afAlignment8[1];
616
617 /** Number of usable ports on this controller. */
618 uint32_t cPortsImpl;
619
620#if HC_ARCH_BITS == 64
621 uint32_t Alignment9;
622#endif
623
624 /** Flag whether we have written the first 4bytes in an 8byte MMIO write successfully. */
625 volatile bool f8ByteMMIO4BytesWrittenSuccessfully;
626 /** At which number of I/O requests per second we consider having high I/O load. */
627 uint32_t cHighIOThreshold;
628 /** How many milliseconds to sleep. */
629 uint32_t cMillisToSleep;
630
631} AHCI;
632/** Pointer to the state of an AHCI device. */
633typedef AHCI *PAHCI;
634
635/**
636 * Scatter gather list entry.
637 */
638typedef struct
639{
640 /** Data Base Address. */
641 uint32_t u32DBA;
642 /** Data Base Address - Upper 32-bits. */
643 uint32_t u32DBAUp;
644 /** Reserved */
645 uint32_t u32Reserved;
646 /** Description information. */
647 uint32_t u32DescInf;
648} SGLEntry;
649AssertCompileSize(SGLEntry, 16);
650
651/** Defines for a scatter gather list entry. */
652#define SGLENTRY_DBA_READONLY ~(RT_BIT(0))
653#define SGLENTRY_DESCINF_I RT_BIT(31)
654#define SGLENTRY_DESCINF_DBC 0x3fffff
655#define SGLENTRY_DESCINF_READONLY 0x803fffff
656
657/* Defines for the global host control registers for the HBA. */
658
659#define AHCI_HBA_GLOBAL_SIZE 0x100
660
661/* Defines for the HBA Capabilities - Readonly */
662#define AHCI_HBA_CAP_S64A RT_BIT(31)
663#define AHCI_HBA_CAP_SNCQ RT_BIT(30)
664#define AHCI_HBA_CAP_SIS RT_BIT(28)
665#define AHCI_HBA_CAP_SSS RT_BIT(27)
666#define AHCI_HBA_CAP_SALP RT_BIT(26)
667#define AHCI_HBA_CAP_SAL RT_BIT(25)
668#define AHCI_HBA_CAP_SCLO RT_BIT(24)
669#define AHCI_HBA_CAP_ISS (RT_BIT(23) | RT_BIT(22) | RT_BIT(21) | RT_BIT(20))
670# define AHCI_HBA_CAP_ISS_SHIFT(x) (((x) << 20) & AHCI_HBA_CAP_ISS)
671# define AHCI_HBA_CAP_ISS_GEN1 RT_BIT(0)
672# define AHCI_HBA_CAP_ISS_GEN2 RT_BIT(1)
673#define AHCI_HBA_CAP_SNZO RT_BIT(19)
674#define AHCI_HBA_CAP_SAM RT_BIT(18)
675#define AHCI_HBA_CAP_SPM RT_BIT(17)
676#define AHCI_HBA_CAP_PMD RT_BIT(15)
677#define AHCI_HBA_CAP_SSC RT_BIT(14)
678#define AHCI_HBA_CAP_PSC RT_BIT(13)
679#define AHCI_HBA_CAP_NCS (RT_BIT(12) | RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8))
680#define AHCI_HBA_CAP_NCS_SET(x) (((x-1) << 8) & AHCI_HBA_CAP_NCS) /* 0's based */
681#define AHCI_HBA_CAP_CCCS RT_BIT(7)
682#define AHCI_HBA_CAP_NP (RT_BIT(4) | RT_BIT(3) | RT_BIT(2) | RT_BIT(1) | RT_BIT(0))
683#define AHCI_HBA_CAP_NP_SET(x) ((x-1) & AHCI_HBA_CAP_NP) /* 0's based */
684
685/* Defines for the HBA Control register - Read/Write */
686#define AHCI_HBA_CTRL_AE RT_BIT(31)
687#define AHCI_HBA_CTRL_IE RT_BIT(1)
688#define AHCI_HBA_CTRL_HR RT_BIT(0)
689#define AHCI_HBA_CTRL_RW_MASK (RT_BIT(0) | RT_BIT(1)) /* Mask for the used bits */
690
691/* Defines for the HBA Version register - Readonly (We support AHCI 1.0) */
692#define AHCI_HBA_VS_MJR (1 << 16)
693#define AHCI_HBA_VS_MNR 0x100
694
695/* Defines for the command completion coalescing control register */
696#define AHCI_HBA_CCC_CTL_TV 0xffff0000
697#define AHCI_HBA_CCC_CTL_TV_SET(x) (x << 16)
698#define AHCI_HBA_CCC_CTL_TV_GET(x) ((x & AHCI_HBA_CCC_CTL_TV) >> 16)
699
700#define AHCI_HBA_CCC_CTL_CC 0xff00
701#define AHCI_HBA_CCC_CTL_CC_SET(x) (x << 8)
702#define AHCI_HBA_CCC_CTL_CC_GET(x) ((x & AHCI_HBA_CCC_CTL_CC) >> 8)
703
704#define AHCI_HBA_CCC_CTL_INT 0xf8
705#define AHCI_HBA_CCC_CTL_INT_SET(x) (x << 3)
706#define AHCI_HBA_CCC_CTL_INT_GET(x) ((x & AHCI_HBA_CCC_CTL_INT) >> 3)
707
708#define AHCI_HBA_CCC_CTL_EN RT_BIT(0)
709
710/* Defines for the port registers. */
711
712#define AHCI_PORT_REGISTER_SIZE 0x80
713
714#define AHCI_PORT_CLB_RESERVED 0xfffffc00 /* For masking out the reserved bits. */
715
716#define AHCI_PORT_FB_RESERVED 0x7fffff00 /* For masking out the reserved bits. */
717
718#define AHCI_PORT_IS_CPDS RT_BIT(31)
719#define AHCI_PORT_IS_TFES RT_BIT(30)
720#define AHCI_PORT_IS_HBFS RT_BIT(29)
721#define AHCI_PORT_IS_HBDS RT_BIT(28)
722#define AHCI_PORT_IS_IFS RT_BIT(27)
723#define AHCI_PORT_IS_INFS RT_BIT(26)
724#define AHCI_PORT_IS_OFS RT_BIT(24)
725#define AHCI_PORT_IS_IPMS RT_BIT(23)
726#define AHCI_PORT_IS_PRCS RT_BIT(22)
727#define AHCI_PORT_IS_DIS RT_BIT(7)
728#define AHCI_PORT_IS_PCS RT_BIT(6)
729#define AHCI_PORT_IS_DPS RT_BIT(5)
730#define AHCI_PORT_IS_UFS RT_BIT(4)
731#define AHCI_PORT_IS_SDBS RT_BIT(3)
732#define AHCI_PORT_IS_DSS RT_BIT(2)
733#define AHCI_PORT_IS_PSS RT_BIT(1)
734#define AHCI_PORT_IS_DHRS RT_BIT(0)
735#define AHCI_PORT_IS_READONLY 0xfd8000af /* Readonly mask including reserved bits. */
736
737#define AHCI_PORT_IE_CPDE RT_BIT(31)
738#define AHCI_PORT_IE_TFEE RT_BIT(30)
739#define AHCI_PORT_IE_HBFE RT_BIT(29)
740#define AHCI_PORT_IE_HBDE RT_BIT(28)
741#define AHCI_PORT_IE_IFE RT_BIT(27)
742#define AHCI_PORT_IE_INFE RT_BIT(26)
743#define AHCI_PORT_IE_OFE RT_BIT(24)
744#define AHCI_PORT_IE_IPME RT_BIT(23)
745#define AHCI_PORT_IE_PRCE RT_BIT(22)
746#define AHCI_PORT_IE_DIE RT_BIT(7) /* Not supported for now, readonly. */
747#define AHCI_PORT_IE_PCE RT_BIT(6)
748#define AHCI_PORT_IE_DPE RT_BIT(5)
749#define AHCI_PORT_IE_UFE RT_BIT(4)
750#define AHCI_PORT_IE_SDBE RT_BIT(3)
751#define AHCI_PORT_IE_DSE RT_BIT(2)
752#define AHCI_PORT_IE_PSE RT_BIT(1)
753#define AHCI_PORT_IE_DHRE RT_BIT(0)
754#define AHCI_PORT_IE_READONLY (0xfdc000ff) /* Readonly mask including reserved bits. */
755
756#define AHCI_PORT_CMD_ICC (RT_BIT(28) | RT_BIT(29) | RT_BIT(30) | RT_BIT(31))
757#define AHCI_PORT_CMD_ICC_SHIFT(x) ((x) << 28)
758# define AHCI_PORT_CMD_ICC_IDLE 0x0
759# define AHCI_PORT_CMD_ICC_ACTIVE 0x1
760# define AHCI_PORT_CMD_ICC_PARTIAL 0x2
761# define AHCI_PORT_CMD_ICC_SLUMBER 0x6
762#define AHCI_PORT_CMD_ASP RT_BIT(27) /* Not supported - Readonly */
763#define AHCI_PORT_CMD_ALPE RT_BIT(26) /* Not supported - Readonly */
764#define AHCI_PORT_CMD_DLAE RT_BIT(25)
765#define AHCI_PORT_CMD_ATAPI RT_BIT(24)
766#define AHCI_PORT_CMD_CPD RT_BIT(20)
767#define AHCI_PORT_CMD_ISP RT_BIT(19) /* Readonly */
768#define AHCI_PORT_CMD_HPCP RT_BIT(18)
769#define AHCI_PORT_CMD_PMA RT_BIT(17) /* Not supported - Readonly */
770#define AHCI_PORT_CMD_CPS RT_BIT(16)
771#define AHCI_PORT_CMD_CR RT_BIT(15) /* Readonly */
772#define AHCI_PORT_CMD_FR RT_BIT(14) /* Readonly */
773#define AHCI_PORT_CMD_ISS RT_BIT(13) /* Readonly */
774#define AHCI_PORT_CMD_CCS (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11) | RT_BIT(12))
775#define AHCI_PORT_CMD_CCS_SHIFT(x) (x << 8) /* Readonly */
776#define AHCI_PORT_CMD_FRE RT_BIT(4)
777#define AHCI_PORT_CMD_CLO RT_BIT(3)
778#define AHCI_PORT_CMD_POD RT_BIT(2)
779#define AHCI_PORT_CMD_SUD RT_BIT(1)
780#define AHCI_PORT_CMD_ST RT_BIT(0)
781#define AHCI_PORT_CMD_READONLY (0xff02001f & ~(AHCI_PORT_CMD_ASP | AHCI_PORT_CMD_ALPE | AHCI_PORT_CMD_PMA))
782
783#define AHCI_PORT_SCTL_IPM (RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8))
784#define AHCI_PORT_SCTL_IPM_GET(x) ((x & AHCI_PORT_SCTL_IPM) >> 8)
785#define AHCI_PORT_SCTL_SPD (RT_BIT(7) | RT_BIT(6) | RT_BIT(5) | RT_BIT(4))
786#define AHCI_PORT_SCTL_SPD_GET(x) ((x & AHCI_PORT_SCTL_SPD) >> 4)
787#define AHCI_PORT_SCTL_DET (RT_BIT(3) | RT_BIT(2) | RT_BIT(1) | RT_BIT(0))
788#define AHCI_PORT_SCTL_DET_GET(x) (x & AHCI_PORT_SCTL_DET)
789#define AHCI_PORT_SCTL_DET_NINIT 0
790#define AHCI_PORT_SCTL_DET_INIT 1
791#define AHCI_PORT_SCTL_DET_OFFLINE 4
792#define AHCI_PORT_SCTL_READONLY 0xfff
793
794#define AHCI_PORT_SSTS_IPM (RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8))
795#define AHCI_PORT_SSTS_IPM_GET(x) ((x & AHCI_PORT_SCTL_IPM) >> 8)
796#define AHCI_PORT_SSTS_SPD (RT_BIT(7) | RT_BIT(6) | RT_BIT(5) | RT_BIT(4))
797#define AHCI_PORT_SSTS_SPD_GET(x) ((x & AHCI_PORT_SCTL_SPD) >> 4)
798#define AHCI_PORT_SSTS_DET (RT_BIT(3) | RT_BIT(2) | RT_BIT(1) | RT_BIT(0))
799#define AHCI_PORT_SSTS_DET_GET(x) (x & AHCI_PORT_SCTL_DET)
800
801#define AHCI_PORT_TFD_BSY RT_BIT(7)
802#define AHCI_PORT_TFD_DRQ RT_BIT(3)
803#define AHCI_PORT_TFD_ERR RT_BIT(0)
804
805#define AHCI_PORT_SERR_X RT_BIT(26)
806#define AHCI_PORT_SERR_W RT_BIT(18)
807#define AHCI_PORT_SERR_N RT_BIT(16)
808
809/* Signatures for attached storage devices. */
810#define AHCI_PORT_SIG_DISK 0x00000101
811#define AHCI_PORT_SIG_ATAPI 0xeb140101
812
813/*
814 * The AHCI spec defines an area of memory where the HBA posts received FIS's from the device.
815 * regFB points to the base of this area.
816 * Every FIS type has an offset where it is posted in this area.
817 */
818#define AHCI_RECFIS_DSFIS_OFFSET 0x00 /* DMA Setup FIS */
819#define AHCI_RECFIS_PSFIS_OFFSET 0x20 /* PIO Setup FIS */
820#define AHCI_RECFIS_RFIS_OFFSET 0x40 /* D2H Register FIS */
821#define AHCI_RECFIS_SDBFIS_OFFSET 0x58 /* Set Device Bits FIS */
822#define AHCI_RECFIS_UFIS_OFFSET 0x60 /* Unknown FIS type */
823
824#define AHCI_TASK_IS_QUEUED(x) ((x) & 0x1)
825#define AHCI_TASK_GET_TAG(x) ((x) >> 1)
826#define AHCI_TASK_SET(tag, queued) (((tag) << 1) | (queued))
827
828/**
829 * AHCI register operator.
830 */
831typedef struct ahci_opreg
832{
833 const char *pszName;
834 int (*pfnRead )(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value);
835 int (*pfnWrite)(PAHCI ahci, uint32_t iReg, uint32_t u32Value);
836} AHCIOPREG;
837
838/**
839 * AHCI port register operator.
840 */
841typedef struct pAhciPort_opreg
842{
843 const char *pszName;
844 int (*pfnRead )(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value);
845 int (*pfnWrite)(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value);
846} AHCIPORTOPREG;
847
848#ifndef VBOX_DEVICE_STRUCT_TESTCASE
849RT_C_DECLS_BEGIN
850PDMBOTHCBDECL(int) ahciMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
851PDMBOTHCBDECL(int) ahciMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
852static void ahciHBAReset(PAHCI pThis);
853PDMBOTHCBDECL(int) ahciIOPortWrite1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
854PDMBOTHCBDECL(int) ahciIOPortRead1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
855PDMBOTHCBDECL(int) ahciIOPortWrite2(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
856PDMBOTHCBDECL(int) ahciIOPortRead2(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
857PDMBOTHCBDECL(int) ahciLegacyFakeWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
858PDMBOTHCBDECL(int) ahciLegacyFakeRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
859#ifdef IN_RING3
860static int ahciPostFisIntoMemory(PAHCIPort pAhciPort, unsigned uFisType, uint8_t *cmdFis);
861static void ahciPostFirstD2HFisIntoMemory(PAHCIPort pAhciPort);
862static int ahciScatterGatherListCopyFromBuffer(PAHCIPORTTASKSTATE pAhciPortTaskState, void *pvBuf, size_t cbBuf);
863static int ahciScatterGatherListCreate(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState, bool fReadonly);
864static int ahciScatterGatherListDestroy(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState);
865static void ahciCopyFromBufferIntoSGList(PPDMDEVINS pDevIns, PAHCIPORTTASKSTATESGENTRY pSGInfo);
866static void ahciCopyFromSGListIntoBuffer(PPDMDEVINS pDevIns, PAHCIPORTTASKSTATESGENTRY pSGInfo);
867static void ahciScatterGatherListGetTotalBufferSize(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState);
868static int ahciScatterGatherListCreateSafe(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState,
869 bool fReadonly, unsigned cSGEntriesProcessed);
870#endif
871RT_C_DECLS_END
872
873#define PCIDEV_2_PAHCI(pPciDev) ( (PAHCI)(pPciDev) )
874#define PDMIMOUNT_2_PAHCIPORT(pInterface) ( (PAHCIPort)((uintptr_t)(pInterface) - RT_OFFSETOF(AHCIPort, IMount)) )
875#define PDMIMOUNTNOTIFY_2_PAHCIPORT(pInterface) ( (PAHCIPort)((uintptr_t)(pInterface) - RT_OFFSETOF(AHCIPort, IMountNotify)) )
876#define PDMIBASE_2_PAHCIPORT(pInterface) ( (PAHCIPort)((uintptr_t)(pInterface) - RT_OFFSETOF(AHCIPort, IBase)) )
877#define PDMIBASE_2_PAHCI(pInterface) ( (PAHCI)((uintptr_t)(pInterface) - RT_OFFSETOF(AHCI, IBase)) )
878#define PDMILEDPORTS_2_PAHCI(pInterface) ( (PAHCI)((uintptr_t)(pInterface) - RT_OFFSETOF(AHCI, ILeds)) )
879
880#if 1
881#define AHCI_RTGCPHYS_FROM_U32(Hi, Lo) ( (RTGCPHYS)RT_MAKE_U64(Lo, Hi) )
882#else
883#define AHCI_RTGCPHYS_FROM_U32(Hi, Lo) ( (RTGCPHYS)(Lo) )
884#endif
885
886#ifdef IN_RING3
887
888# ifdef LOG_USE_C99
889# define ahciLog(a) \
890 Log(("R3 P%u: %M", pAhciPort->iLUN, _LogRelRemoveParentheseis a))
891# else
892# define ahciLog(a) \
893 do { Log(("R3 P%u: ", pAhciPort->iLUN)); Log(a); } while(0)
894# endif
895
896#elif IN_RING0
897
898# ifdef LOG_USE_C99
899# define ahciLog(a) \
900 Log(("R0 P%u: %M", pAhciPort->iLUN, _LogRelRemoveParentheseis a))
901# else
902# define ahciLog(a) \
903 do { Log(("R0 P%u: ", pAhciPort->iLUN)); Log(a); } while(0)
904# endif
905
906#elif IN_RC
907
908# ifdef LOG_USE_C99
909# define ahciLog(a) \
910 Log(("GC P%u: %M", pAhciPort->iLUN, _LogRelRemoveParentheseis a))
911# else
912# define ahciLog(a) \
913 do { Log(("GC P%u: ", pAhciPort->iLUN)); Log(a); } while(0)
914# endif
915
916#endif
917
918/**
919 * Update PCI IRQ levels
920 */
921static void ahciHbaClearInterrupt(PAHCI pAhci)
922{
923 Log(("%s: Clearing interrupt\n", __FUNCTION__));
924 PDMDevHlpPCISetIrqNoWait(pAhci->CTX_SUFF(pDevIns), 0, 0);
925}
926
927/**
928 * Updates the IRQ level and sets port bit in the global interrupt status register of the HBA.
929 */
930static void ahciHbaSetInterrupt(PAHCI pAhci, uint8_t iPort)
931{
932 Log(("P%u: %s: Setting interrupt\n", iPort, __FUNCTION__));
933
934 PDMCritSectEnter(&pAhci->lock, VINF_SUCCESS);
935
936 if (pAhci->regHbaCtrl & AHCI_HBA_CTRL_IE)
937 {
938 if ((pAhci->regHbaCccCtl & AHCI_HBA_CCC_CTL_EN) && (pAhci->regHbaCccPorts & (1 << iPort)))
939 {
940 pAhci->uCccCurrentNr++;
941 if (pAhci->uCccCurrentNr >= pAhci->uCccNr)
942 {
943 /* Reset command completion coalescing state. */
944 TMTimerSetMillies(pAhci->CTX_SUFF(pHbaCccTimer), pAhci->uCccTimeout);
945 pAhci->uCccCurrentNr = 0;
946
947 pAhci->u32PortsInterrupted |= (1 << pAhci->uCccPortNr);
948 if (!(pAhci->u32PortsInterrupted & ~(1 << pAhci->uCccPortNr)))
949 {
950 Log(("P%u: %s: Fire interrupt\n", iPort, __FUNCTION__));
951 PDMDevHlpPCISetIrqNoWait(pAhci->CTX_SUFF(pDevIns), 0, 1);
952 }
953 }
954 }
955 else
956 {
957 /* If only the bit of the actual port is set assert an interrupt
958 * because the interrupt status register was already read by the guest
959 * and we need to send a new notification.
960 * Otherwise an interrupt is still pending.
961 */
962 ASMAtomicOrU32((volatile uint32_t *)&pAhci->u32PortsInterrupted, (1 << iPort));
963 if (!(pAhci->u32PortsInterrupted & ~(1 << iPort)))
964 {
965 Log(("P%u: %s: Fire interrupt\n", iPort, __FUNCTION__));
966 PDMDevHlpPCISetIrqNoWait(pAhci->CTX_SUFF(pDevIns), 0, 1);
967 }
968 }
969 }
970
971 PDMCritSectLeave(&pAhci->lock);
972}
973
974#ifdef IN_RING3
975/*
976 * Assert irq when an CCC timeout occurs
977 */
978DECLCALLBACK(void) ahciCccTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
979{
980 PAHCI pAhci = (PAHCI)pvUser;
981
982 ahciHbaSetInterrupt(pAhci, pAhci->uCccPortNr);
983}
984#endif
985
986static int PortCmdIssue_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
987{
988 uint32_t uCIValue;
989
990 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
991
992 /* Update the CI register first. */
993 uCIValue = ASMAtomicXchgU32(&pAhciPort->u32TasksFinished, 0);
994 pAhciPort->regCI &= ~uCIValue;
995
996
997 if ((pAhciPort->regCMD & AHCI_PORT_CMD_ST) && (u32Value > 0))
998 {
999 PDEVPORTNOTIFIERQUEUEITEM pItem;
1000
1001 /* Mark the tasks set in the value as used. */
1002 for (uint8_t i = 0; i < AHCI_NR_COMMAND_SLOTS; i++)
1003 {
1004 /* Queue task if bit is set in written value and not already in progress. */
1005 if (((u32Value >> i) & 0x01) && !(pAhciPort->regCI & (1 << i)))
1006 {
1007 if (!pAhciPort->fAsyncInterface)
1008 {
1009 /* Put the tag number of the task into the FIFO. */
1010 uint8_t uTag = AHCI_TASK_SET(i, ((pAhciPort->regSACT & (1 << i)) ? 1 : 0));
1011 ASMAtomicWriteU8(&pAhciPort->ahciIOTasks[pAhciPort->uActWritePos], uTag);
1012 ahciLog(("%s: Before uActWritePos=%u\n", __FUNCTION__, pAhciPort->uActWritePos));
1013 pAhciPort->uActWritePos++;
1014 pAhciPort->uActWritePos %= RT_ELEMENTS(pAhciPort->ahciIOTasks);
1015 ahciLog(("%s: After uActWritePos=%u\n", __FUNCTION__, pAhciPort->uActWritePos));
1016
1017 ASMAtomicIncU32(&pAhciPort->uActTasksActive);
1018
1019 bool fNotificationSend = ASMAtomicXchgBool(&pAhciPort->fNotificationSend, true);
1020 if (!fNotificationSend)
1021 {
1022 /* Send new notification. */
1023 pItem = (PDEVPORTNOTIFIERQUEUEITEM)PDMQueueAlloc(ahci->CTX_SUFF(pNotifierQueue));
1024 AssertMsg(pItem, ("Allocating item for queue failed\n"));
1025
1026 pItem->iPort = pAhciPort->iLUN;
1027 PDMQueueInsert(ahci->CTX_SUFF(pNotifierQueue), (PPDMQUEUEITEMCORE)pItem);
1028 }
1029 }
1030 else
1031 {
1032 pItem = (PDEVPORTNOTIFIERQUEUEITEM)PDMQueueAlloc(ahci->CTX_SUFF(pNotifierQueue));
1033 AssertMsg(pItem, ("Allocating item for queue failed\n"));
1034
1035 pItem->iPort = pAhciPort->iLUN;
1036 pItem->iTask = i;
1037 pItem->fQueued = !!(pAhciPort->regSACT & (1 << i)); /* Mark if the task is queued. */
1038 PDMQueueInsert(ahci->CTX_SUFF(pNotifierQueue), (PPDMQUEUEITEMCORE)pItem);
1039 }
1040 }
1041 }
1042 }
1043
1044 pAhciPort->regCI |= u32Value;
1045
1046 return VINF_SUCCESS;
1047}
1048
1049static int PortCmdIssue_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1050{
1051 uint32_t uCIValue = 0;
1052
1053 uCIValue = ASMAtomicXchgU32(&pAhciPort->u32TasksFinished, 0);
1054
1055 ahciLog(("%s: read regCI=%#010x uCIValue=%#010x\n", __FUNCTION__, pAhciPort->regCI, uCIValue));
1056
1057 pAhciPort->regCI &= ~uCIValue;
1058
1059 *pu32Value = pAhciPort->regCI;
1060
1061 return VINF_SUCCESS;
1062}
1063
1064static int PortSActive_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1065{
1066 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1067
1068 pAhciPort->regSACT |= u32Value;
1069
1070 return VINF_SUCCESS;
1071}
1072
1073static int PortSActive_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1074{
1075 uint32_t u32TasksFinished = ASMAtomicXchgU32(&pAhciPort->u32QueuedTasksFinished, 0);
1076
1077 pAhciPort->regSACT &= ~u32TasksFinished;
1078
1079 ahciLog(("%s: read regSACT=%#010x regCI=%#010x u32TasksFinished=%#010x\n",
1080 __FUNCTION__, pAhciPort->regSACT, pAhciPort->regCI, u32TasksFinished));
1081
1082 *pu32Value = pAhciPort->regSACT;
1083
1084 return VINF_SUCCESS;
1085}
1086
1087static int PortSError_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1088{
1089 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1090
1091 if ( (u32Value & AHCI_PORT_SERR_X)
1092 && (pAhciPort->regSERR & AHCI_PORT_SERR_X))
1093 {
1094 ASMAtomicAndU32(&pAhciPort->regIS, ~AHCI_PORT_IS_PCS);
1095 pAhciPort->regTFD |= ATA_STAT_ERR;
1096 pAhciPort->regTFD &= ~(ATA_STAT_DRQ | ATA_STAT_BUSY);
1097 }
1098
1099 pAhciPort->regSERR &= ~u32Value;
1100
1101 return VINF_SUCCESS;
1102}
1103
1104static int PortSError_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1105{
1106 ahciLog(("%s: read regSERR=%#010x\n", __FUNCTION__, pAhciPort->regSERR));
1107 *pu32Value = pAhciPort->regSERR;
1108 return VINF_SUCCESS;
1109}
1110
1111static int PortSControl_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1112{
1113 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1114 ahciLog(("%s: IPM=%d SPD=%d DET=%d\n", __FUNCTION__,
1115 AHCI_PORT_SCTL_IPM_GET(u32Value), AHCI_PORT_SCTL_SPD_GET(u32Value), AHCI_PORT_SCTL_DET_GET(u32Value)));
1116
1117 if ((u32Value & AHCI_PORT_SCTL_DET) == AHCI_PORT_SCTL_DET_INIT)
1118 {
1119 ASMAtomicXchgBool(&pAhciPort->fPortReset, true);
1120 pAhciPort->regSSTS = 0;
1121 pAhciPort->regSIG = ~0;
1122 pAhciPort->regTFD = 0x7f;
1123 pAhciPort->fFirstD2HFisSend = false;
1124 }
1125 else if ((u32Value & AHCI_PORT_SCTL_DET) == AHCI_PORT_SCTL_DET_NINIT && pAhciPort->pDrvBase &&
1126 (pAhciPort->regSCTL & AHCI_PORT_SCTL_DET) == AHCI_PORT_SCTL_DET_INIT)
1127 {
1128#ifndef IN_RING3
1129 return VINF_IOM_HC_MMIO_WRITE;
1130#else
1131 if (pAhciPort->pDrvBase)
1132 {
1133 /* Reset queue. */
1134 pAhciPort->uActWritePos = 0;
1135 pAhciPort->uActReadPos = 0;
1136 ASMAtomicXchgBool(&pAhciPort->fPortReset, false);
1137
1138 /* Signature for SATA device. */
1139 if (pAhciPort->fATAPI)
1140 pAhciPort->regSIG = AHCI_PORT_SIG_ATAPI;
1141 else
1142 pAhciPort->regSIG = AHCI_PORT_SIG_DISK;
1143
1144 pAhciPort->regSSTS = (0x01 << 8) | /* Interface is active. */
1145 (0x03 << 0); /* Device detected and communication established. */
1146
1147 /*
1148 * Use the maximum allowed speed.
1149 * (Not that it changes anything really)
1150 */
1151 switch (AHCI_PORT_SCTL_SPD_GET(pAhciPort->regSCTL))
1152 {
1153 case 0x01:
1154 pAhciPort->regSSTS |= (0x01 << 4); /* Generation 1 (1.5GBps) speed. */
1155 break;
1156 case 0x02:
1157 case 0x00:
1158 default:
1159 pAhciPort->regSSTS |= (0x02 << 4); /* Generation 2 (3.0GBps) speed. */
1160 break;
1161 }
1162
1163 /* We received a COMINIT from the device. Tell the guest. */
1164 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_PCS);
1165 pAhciPort->regSERR |= AHCI_PORT_SERR_X;
1166 pAhciPort->regTFD |= ATA_STAT_BUSY;
1167
1168 if ((pAhciPort->regCMD & AHCI_PORT_CMD_FRE) && (!pAhciPort->fFirstD2HFisSend))
1169 {
1170 ahciPostFirstD2HFisIntoMemory(pAhciPort);
1171 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_DHRS);
1172
1173 if (pAhciPort->regIE & AHCI_PORT_IE_DHRE)
1174 ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN);
1175 }
1176 }
1177#endif
1178 }
1179
1180 pAhciPort->regSCTL = u32Value;
1181
1182 return VINF_SUCCESS;
1183}
1184
1185static int PortSControl_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1186{
1187 ahciLog(("%s: read regSCTL=%#010x\n", __FUNCTION__, pAhciPort->regSCTL));
1188 ahciLog(("%s: IPM=%d SPD=%d DET=%d\n", __FUNCTION__,
1189 AHCI_PORT_SCTL_IPM_GET(pAhciPort->regSCTL), AHCI_PORT_SCTL_SPD_GET(pAhciPort->regSCTL),
1190 AHCI_PORT_SCTL_DET_GET(pAhciPort->regSCTL)));
1191
1192 *pu32Value = pAhciPort->regSCTL;
1193 return VINF_SUCCESS;
1194}
1195
1196static int PortSStatus_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1197{
1198 ahciLog(("%s: read regSSTS=%#010x\n", __FUNCTION__, pAhciPort->regSSTS));
1199 ahciLog(("%s: IPM=%d SPD=%d DET=%d\n", __FUNCTION__,
1200 AHCI_PORT_SSTS_IPM_GET(pAhciPort->regSSTS), AHCI_PORT_SSTS_SPD_GET(pAhciPort->regSSTS),
1201 AHCI_PORT_SSTS_DET_GET(pAhciPort->regSSTS)));
1202
1203 *pu32Value = pAhciPort->regSSTS;
1204 return VINF_SUCCESS;
1205}
1206
1207static int PortSignature_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1208{
1209 ahciLog(("%s: read regSIG=%#010x\n", __FUNCTION__, pAhciPort->regSIG));
1210 *pu32Value = pAhciPort->regSIG;
1211 return VINF_SUCCESS;
1212}
1213
1214static int PortTaskFileData_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1215{
1216 ahciLog(("%s: read regTFD=%#010x\n", __FUNCTION__, pAhciPort->regTFD));
1217 ahciLog(("%s: ERR=%x BSY=%d DRQ=%d ERR=%d\n", __FUNCTION__,
1218 (pAhciPort->regTFD >> 8), (pAhciPort->regTFD & AHCI_PORT_TFD_BSY) >> 7,
1219 (pAhciPort->regTFD & AHCI_PORT_TFD_DRQ) >> 3, (pAhciPort->regTFD & AHCI_PORT_TFD_ERR)));
1220 *pu32Value = pAhciPort->regTFD;
1221 return VINF_SUCCESS;
1222}
1223
1224/**
1225 * Read from the port command register.
1226 */
1227static int PortCmd_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1228{
1229 ahciLog(("%s: read regCMD=%#010x\n", __FUNCTION__, pAhciPort->regCMD));
1230 ahciLog(("%s: ICC=%d ASP=%d ALPE=%d DLAE=%d ATAPI=%d CPD=%d ISP=%d HPCP=%d PMA=%d CPS=%d CR=%d FR=%d ISS=%d CCS=%d FRE=%d CLO=%d POD=%d SUD=%d ST=%d\n",
1231 __FUNCTION__, (pAhciPort->regCMD & AHCI_PORT_CMD_ICC) >> 28, (pAhciPort->regCMD & AHCI_PORT_CMD_ASP) >> 27,
1232 (pAhciPort->regCMD & AHCI_PORT_CMD_ALPE) >> 26, (pAhciPort->regCMD & AHCI_PORT_CMD_DLAE) >> 25,
1233 (pAhciPort->regCMD & AHCI_PORT_CMD_ATAPI) >> 24, (pAhciPort->regCMD & AHCI_PORT_CMD_CPD) >> 20,
1234 (pAhciPort->regCMD & AHCI_PORT_CMD_ISP) >> 19, (pAhciPort->regCMD & AHCI_PORT_CMD_HPCP) >> 18,
1235 (pAhciPort->regCMD & AHCI_PORT_CMD_PMA) >> 17, (pAhciPort->regCMD & AHCI_PORT_CMD_CPS) >> 16,
1236 (pAhciPort->regCMD & AHCI_PORT_CMD_CR) >> 15, (pAhciPort->regCMD & AHCI_PORT_CMD_FR) >> 14,
1237 (pAhciPort->regCMD & AHCI_PORT_CMD_ISS) >> 13, (pAhciPort->regCMD & AHCI_PORT_CMD_CCS) >> 8,
1238 (pAhciPort->regCMD & AHCI_PORT_CMD_FRE) >> 4, (pAhciPort->regCMD & AHCI_PORT_CMD_CLO) >> 3,
1239 (pAhciPort->regCMD & AHCI_PORT_CMD_POD) >> 2, (pAhciPort->regCMD & AHCI_PORT_CMD_SUD) >> 1,
1240 (pAhciPort->regCMD & AHCI_PORT_CMD_ST)));
1241 *pu32Value = pAhciPort->regCMD;
1242 return VINF_SUCCESS;
1243}
1244
1245/**
1246 * Write to the port command register.
1247 * This is the register where all the data transfer is started
1248 */
1249static int PortCmd_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1250{
1251 int rc = VINF_SUCCESS;
1252 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1253 ahciLog(("%s: ICC=%d ASP=%d ALPE=%d DLAE=%d ATAPI=%d CPD=%d ISP=%d HPCP=%d PMA=%d CPS=%d CR=%d FR=%d ISS=%d CCS=%d FRE=%d CLO=%d POD=%d SUD=%d ST=%d\n",
1254 __FUNCTION__, (u32Value & AHCI_PORT_CMD_ICC) >> 28, (u32Value & AHCI_PORT_CMD_ASP) >> 27,
1255 (u32Value & AHCI_PORT_CMD_ALPE) >> 26, (u32Value & AHCI_PORT_CMD_DLAE) >> 25,
1256 (u32Value & AHCI_PORT_CMD_ATAPI) >> 24, (u32Value & AHCI_PORT_CMD_CPD) >> 20,
1257 (u32Value & AHCI_PORT_CMD_ISP) >> 19, (u32Value & AHCI_PORT_CMD_HPCP) >> 18,
1258 (u32Value & AHCI_PORT_CMD_PMA) >> 17, (u32Value & AHCI_PORT_CMD_CPS) >> 16,
1259 (u32Value & AHCI_PORT_CMD_CR) >> 15, (u32Value & AHCI_PORT_CMD_FR) >> 14,
1260 (u32Value & AHCI_PORT_CMD_ISS) >> 13, (u32Value & AHCI_PORT_CMD_CCS) >> 8,
1261 (u32Value & AHCI_PORT_CMD_FRE) >> 4, (u32Value & AHCI_PORT_CMD_CLO) >> 3,
1262 (u32Value & AHCI_PORT_CMD_POD) >> 2, (u32Value & AHCI_PORT_CMD_SUD) >> 1,
1263 (u32Value & AHCI_PORT_CMD_ST)));
1264
1265 if (pAhciPort->fPoweredOn && pAhciPort->fSpunUp)
1266 {
1267 if (u32Value & AHCI_PORT_CMD_CLO)
1268 {
1269 ahciLog(("%s: Command list override requested\n", __FUNCTION__));
1270 u32Value &= ~(AHCI_PORT_TFD_BSY | AHCI_PORT_TFD_DRQ);
1271 /* Clear the CLO bit. */
1272 u32Value &= ~(AHCI_PORT_CMD_CLO);
1273 }
1274
1275 if (u32Value & AHCI_PORT_CMD_ST)
1276 {
1277 ahciLog(("%s: Engine starts\n", __FUNCTION__));
1278
1279 /** Set engine state to running. */
1280 u32Value |= AHCI_PORT_CMD_CR;
1281 }
1282 else
1283 {
1284 ahciLog(("%s: Engine stops\n", __FUNCTION__));
1285 /* Clear command issue register. */
1286 pAhciPort->regCI = 0;
1287 /** Clear current command slot. */
1288 u32Value &= ~(AHCI_PORT_CMD_CCS_SHIFT(0xff));
1289 u32Value &= ~AHCI_PORT_CMD_CR;
1290 }
1291 }
1292 else if (pAhciPort->pDrvBase)
1293 {
1294 if ((u32Value & AHCI_PORT_CMD_POD) && (pAhciPort->regCMD & AHCI_PORT_CMD_CPS) && !pAhciPort->fPoweredOn)
1295 {
1296 ahciLog(("%s: Power on the device\n", __FUNCTION__));
1297 pAhciPort->fPoweredOn = true;
1298
1299 /*
1300 * Set states in the Port Signature and SStatus registers.
1301 */
1302 pAhciPort->regSIG = 0x101; /* Signature for SATA device. */
1303 pAhciPort->regSSTS = (0x01 << 8) | /* Interface is active. */
1304 (0x02 << 4) | /* Generation 2 (3.0GBps) speed. */
1305 (0x03 << 0); /* Device detected and communication established. */
1306
1307 if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
1308 {
1309#ifndef IN_RING3
1310 return VINF_IOM_HC_MMIO_WRITE;
1311#else
1312 ahciPostFirstD2HFisIntoMemory(pAhciPort);
1313 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_DHRS);
1314
1315 if (pAhciPort->regIE & AHCI_PORT_IE_DHRE)
1316 ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN);
1317#endif
1318 }
1319 }
1320
1321 if ((u32Value & AHCI_PORT_CMD_SUD) && pAhciPort->fPoweredOn && !pAhciPort->fSpunUp)
1322 {
1323 ahciLog(("%s: Spin up the device\n", __FUNCTION__));
1324 pAhciPort->fSpunUp = true;
1325 }
1326 }
1327
1328 if (u32Value & AHCI_PORT_CMD_FRE)
1329 {
1330 ahciLog(("%s: FIS receive enabled\n", __FUNCTION__));
1331
1332 u32Value |= AHCI_PORT_CMD_FR;
1333
1334 /* Send the first D2H FIS only if it wasn't already send. */
1335 if (!pAhciPort->fFirstD2HFisSend)
1336 {
1337#ifndef IN_RING3
1338 return VINF_IOM_HC_MMIO_WRITE;
1339#else
1340 ahciPostFirstD2HFisIntoMemory(pAhciPort);
1341 pAhciPort->fFirstD2HFisSend = true;
1342#endif
1343 }
1344 }
1345 else if (!(u32Value & AHCI_PORT_CMD_FRE))
1346 {
1347 ahciLog(("%s: FIS receive disabled\n", __FUNCTION__));
1348 u32Value &= ~AHCI_PORT_CMD_FR;
1349 }
1350
1351 pAhciPort->regCMD = u32Value;
1352
1353 return rc;
1354}
1355
1356/**
1357 * Read from the port interrupt enable register.
1358 */
1359static int PortIntrEnable_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1360{
1361 ahciLog(("%s: read regIE=%#010x\n", __FUNCTION__, pAhciPort->regIE));
1362 ahciLog(("%s: CPDE=%d TFEE=%d HBFE=%d HBDE=%d IFE=%d INFE=%d OFE=%d IPME=%d PRCE=%d DIE=%d PCE=%d DPE=%d UFE=%d SDBE=%d DSE=%d PSE=%d DHRE=%d\n",
1363 __FUNCTION__, (pAhciPort->regIE & AHCI_PORT_IE_CPDE) >> 31, (pAhciPort->regIE & AHCI_PORT_IE_TFEE) >> 30,
1364 (pAhciPort->regIE & AHCI_PORT_IE_HBFE) >> 29, (pAhciPort->regIE & AHCI_PORT_IE_HBDE) >> 28,
1365 (pAhciPort->regIE & AHCI_PORT_IE_IFE) >> 27, (pAhciPort->regIE & AHCI_PORT_IE_INFE) >> 26,
1366 (pAhciPort->regIE & AHCI_PORT_IE_OFE) >> 24, (pAhciPort->regIE & AHCI_PORT_IE_IPME) >> 23,
1367 (pAhciPort->regIE & AHCI_PORT_IE_PRCE) >> 22, (pAhciPort->regIE & AHCI_PORT_IE_DIE) >> 7,
1368 (pAhciPort->regIE & AHCI_PORT_IE_PCE) >> 6, (pAhciPort->regIE & AHCI_PORT_IE_DPE) >> 5,
1369 (pAhciPort->regIE & AHCI_PORT_IE_UFE) >> 4, (pAhciPort->regIE & AHCI_PORT_IE_SDBE) >> 3,
1370 (pAhciPort->regIE & AHCI_PORT_IE_DSE) >> 2, (pAhciPort->regIE & AHCI_PORT_IE_PSE) >> 1,
1371 (pAhciPort->regIE & AHCI_PORT_IE_DHRE)));
1372 *pu32Value = pAhciPort->regIE;
1373 return VINF_SUCCESS;
1374}
1375
1376/**
1377 * Write to the port interrupt enable register.
1378 */
1379static int PortIntrEnable_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1380{
1381 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1382 ahciLog(("%s: CPDE=%d TFEE=%d HBFE=%d HBDE=%d IFE=%d INFE=%d OFE=%d IPME=%d PRCE=%d DIE=%d PCE=%d DPE=%d UFE=%d SDBE=%d DSE=%d PSE=%d DHRE=%d\n",
1383 __FUNCTION__, (u32Value & AHCI_PORT_IE_CPDE) >> 31, (u32Value & AHCI_PORT_IE_TFEE) >> 30,
1384 (u32Value & AHCI_PORT_IE_HBFE) >> 29, (u32Value & AHCI_PORT_IE_HBDE) >> 28,
1385 (u32Value & AHCI_PORT_IE_IFE) >> 27, (u32Value & AHCI_PORT_IE_INFE) >> 26,
1386 (u32Value & AHCI_PORT_IE_OFE) >> 24, (u32Value & AHCI_PORT_IE_IPME) >> 23,
1387 (u32Value & AHCI_PORT_IE_PRCE) >> 22, (u32Value & AHCI_PORT_IE_DIE) >> 7,
1388 (u32Value & AHCI_PORT_IE_PCE) >> 6, (u32Value & AHCI_PORT_IE_DPE) >> 5,
1389 (u32Value & AHCI_PORT_IE_UFE) >> 4, (u32Value & AHCI_PORT_IE_SDBE) >> 3,
1390 (u32Value & AHCI_PORT_IE_DSE) >> 2, (u32Value & AHCI_PORT_IE_PSE) >> 1,
1391 (u32Value & AHCI_PORT_IE_DHRE)));
1392
1393 pAhciPort->regIE = (u32Value & AHCI_PORT_IE_READONLY);
1394
1395 /* Check if some a interrupt status bit changed*/
1396 uint32_t u32IntrStatus = ASMAtomicReadU32(&pAhciPort->regIS);
1397
1398 if (pAhciPort->regIE & u32IntrStatus)
1399 ahciHbaSetInterrupt(ahci, pAhciPort->iLUN);
1400
1401 return VINF_SUCCESS;
1402}
1403
1404/**
1405 * Read from the port interrupt status register.
1406 */
1407static int PortIntrSts_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1408{
1409 ahciLog(("%s: read regIS=%#010x\n", __FUNCTION__, pAhciPort->regIS));
1410 ahciLog(("%s: CPDS=%d TFES=%d HBFS=%d HBDS=%d IFS=%d INFS=%d OFS=%d IPMS=%d PRCS=%d DIS=%d PCS=%d DPS=%d UFS=%d SDBS=%d DSS=%d PSS=%d DHRS=%d\n",
1411 __FUNCTION__, (pAhciPort->regIS & AHCI_PORT_IS_CPDS) >> 31, (pAhciPort->regIS & AHCI_PORT_IS_TFES) >> 30,
1412 (pAhciPort->regIS & AHCI_PORT_IS_HBFS) >> 29, (pAhciPort->regIS & AHCI_PORT_IS_HBDS) >> 28,
1413 (pAhciPort->regIS & AHCI_PORT_IS_IFS) >> 27, (pAhciPort->regIS & AHCI_PORT_IS_INFS) >> 26,
1414 (pAhciPort->regIS & AHCI_PORT_IS_OFS) >> 24, (pAhciPort->regIS & AHCI_PORT_IS_IPMS) >> 23,
1415 (pAhciPort->regIS & AHCI_PORT_IS_PRCS) >> 22, (pAhciPort->regIS & AHCI_PORT_IS_DIS) >> 7,
1416 (pAhciPort->regIS & AHCI_PORT_IS_PCS) >> 6, (pAhciPort->regIS & AHCI_PORT_IS_DPS) >> 5,
1417 (pAhciPort->regIS & AHCI_PORT_IS_UFS) >> 4, (pAhciPort->regIS & AHCI_PORT_IS_SDBS) >> 3,
1418 (pAhciPort->regIS & AHCI_PORT_IS_DSS) >> 2, (pAhciPort->regIS & AHCI_PORT_IS_PSS) >> 1,
1419 (pAhciPort->regIS & AHCI_PORT_IS_DHRS)));
1420 *pu32Value = pAhciPort->regIS;
1421 return VINF_SUCCESS;
1422}
1423
1424/**
1425 * Write to the port interrupt status register.
1426 */
1427static int PortIntrSts_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1428{
1429 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1430 ASMAtomicAndU32(&pAhciPort->regIS, ~(u32Value & AHCI_PORT_IS_READONLY));
1431
1432 return VINF_SUCCESS;
1433}
1434
1435/**
1436 * Read from the port FIS base address upper 32bit register.
1437 */
1438static int PortFisAddrUp_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1439{
1440 ahciLog(("%s: read regFBU=%#010x\n", __FUNCTION__, pAhciPort->regFBU));
1441 *pu32Value = pAhciPort->regFBU;
1442 return VINF_SUCCESS;
1443}
1444
1445/**
1446 * Write to the port FIS base address upper 32bit register.
1447 */
1448static int PortFisAddrUp_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1449{
1450 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1451
1452 pAhciPort->regFBU = u32Value;
1453 pAhciPort->GCPhysAddrFb = AHCI_RTGCPHYS_FROM_U32(pAhciPort->regFBU, pAhciPort->regFB);
1454
1455 return VINF_SUCCESS;
1456}
1457
1458/**
1459 * Read from the port FIS base address register.
1460 */
1461static int PortFisAddr_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1462{
1463 ahciLog(("%s: read regFB=%#010x\n", __FUNCTION__, pAhciPort->regFB));
1464 *pu32Value = pAhciPort->regFB;
1465 return VINF_SUCCESS;
1466}
1467
1468/**
1469 * Write to the port FIS base address register.
1470 */
1471static int PortFisAddr_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1472{
1473 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1474
1475 pAhciPort->regFB = (u32Value & AHCI_PORT_FB_RESERVED);
1476 pAhciPort->GCPhysAddrFb = AHCI_RTGCPHYS_FROM_U32(pAhciPort->regFBU, pAhciPort->regFB);
1477
1478 return VINF_SUCCESS;
1479}
1480
1481/**
1482 * Write to the port command list base address upper 32bit register.
1483 */
1484static int PortCmdLstAddrUp_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1485{
1486 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1487
1488 pAhciPort->regCLBU = u32Value;
1489 pAhciPort->GCPhysAddrClb = AHCI_RTGCPHYS_FROM_U32(pAhciPort->regCLBU, pAhciPort->regCLB);
1490
1491 return VINF_SUCCESS;
1492}
1493
1494/**
1495 * Read from the port command list base address upper 32bit register.
1496 */
1497static int PortCmdLstAddrUp_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1498{
1499 ahciLog(("%s: read regCLBU=%#010x\n", __FUNCTION__, pAhciPort->regCLBU));
1500 *pu32Value = pAhciPort->regCLBU;
1501 return VINF_SUCCESS;
1502}
1503
1504/**
1505 * Read from the port command list base address register.
1506 */
1507static int PortCmdLstAddr_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1508{
1509 ahciLog(("%s: read regCLB=%#010x\n", __FUNCTION__, pAhciPort->regCLB));
1510 *pu32Value = pAhciPort->regCLB;
1511 return VINF_SUCCESS;
1512}
1513
1514/**
1515 * Write to the port command list base address register.
1516 */
1517static int PortCmdLstAddr_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1518{
1519 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1520
1521 pAhciPort->regCLB = (u32Value & AHCI_PORT_CLB_RESERVED);
1522 pAhciPort->GCPhysAddrClb = AHCI_RTGCPHYS_FROM_U32(pAhciPort->regCLBU, pAhciPort->regCLB);
1523
1524 return VINF_SUCCESS;
1525}
1526
1527/**
1528 * Read from the global Version register.
1529 */
1530static int HbaVersion_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)
1531{
1532 Log(("%s: read regHbaVs=%#010x\n", __FUNCTION__, ahci->regHbaVs));
1533 *pu32Value = ahci->regHbaVs;
1534 return VINF_SUCCESS;
1535}
1536
1537/**
1538 * Read from the global Ports implemented register.
1539 */
1540static int HbaPortsImplemented_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)
1541{
1542 Log(("%s: read regHbaPi=%#010x\n", __FUNCTION__, ahci->regHbaPi));
1543 *pu32Value = ahci->regHbaPi;
1544 return VINF_SUCCESS;
1545}
1546
1547/**
1548 * Write to the global interrupt status register.
1549 */
1550static int HbaInterruptStatus_w(PAHCI ahci, uint32_t iReg, uint32_t u32Value)
1551{
1552 int rc;
1553 Log(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1554
1555 rc = PDMCritSectEnter(&ahci->lock, VINF_IOM_HC_MMIO_WRITE);
1556 if (rc != VINF_SUCCESS)
1557 return rc;
1558
1559 if (u32Value > 0)
1560 {
1561 /*
1562 * Clear the interrupt only if no port has signalled
1563 * an interrupt and the guest has cleared all set interrupt
1564 * notification bits.
1565 */
1566 bool fClear = true;
1567
1568 ahci->regHbaIs &= ~(u32Value);
1569
1570 fClear = (!ahci->u32PortsInterrupted) && (!ahci->regHbaIs);
1571 if (fClear)
1572 {
1573 unsigned i = 0;
1574
1575 /* Check if the cleared ports have a interrupt status bit set. */
1576 while ((u32Value > 0) && (i < AHCI_MAX_NR_PORTS_IMPL))
1577 {
1578 if (u32Value & 0x01)
1579 {
1580 PAHCIPort pAhciPort = &ahci->ahciPort[i];
1581
1582 if (pAhciPort->regIE & pAhciPort->regIS)
1583 {
1584 Log(("%s: Interrupt status of port %u set -> Set interrupt again\n", __FUNCTION__, i));
1585 ASMAtomicOrU32(&ahci->u32PortsInterrupted, 1 << i);
1586 fClear = false;
1587 break;
1588 }
1589 }
1590 u32Value = u32Value >> 1;
1591 i++;
1592 }
1593 }
1594
1595 if (fClear)
1596 ahciHbaClearInterrupt(ahci);
1597 else
1598 {
1599 Log(("%s: Not clearing interrupt: u32PortsInterrupted=%#010x\n", __FUNCTION__, ahci->u32PortsInterrupted));
1600 /*
1601 * We need to set the interrupt again because the I/O APIC does not set it again even if the
1602 * line is still high.
1603 * We need to clear it first because the PCI bus only calls the interrupt controller if the state changes.
1604 */
1605 PDMDevHlpPCISetIrqNoWait(ahci->CTX_SUFF(pDevIns), 0, 0);
1606 PDMDevHlpPCISetIrqNoWait(ahci->CTX_SUFF(pDevIns), 0, 1);
1607 }
1608 }
1609
1610 PDMCritSectLeave(&ahci->lock);
1611 return VINF_SUCCESS;
1612}
1613
1614/**
1615 * Read from the global interrupt status register.
1616 */
1617static int HbaInterruptStatus_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)
1618{
1619 uint32_t u32PortsInterrupted;
1620 int rc;
1621
1622 rc = PDMCritSectEnter(&ahci->lock, VINF_IOM_HC_MMIO_READ);
1623 if (rc != VINF_SUCCESS)
1624 return rc;
1625
1626 u32PortsInterrupted = ASMAtomicXchgU32(&ahci->u32PortsInterrupted, 0);
1627
1628 PDMCritSectLeave(&ahci->lock);
1629 Log(("%s: read regHbaIs=%#010x u32PortsInterrupted=%#010x\n", __FUNCTION__, ahci->regHbaIs, u32PortsInterrupted));
1630
1631 ahci->regHbaIs |= u32PortsInterrupted;
1632
1633#ifdef LOG_ENABLED
1634 Log(("%s:", __FUNCTION__));
1635 unsigned i;
1636 for (i = 0; i < ahci->cPortsImpl; i++)
1637 {
1638 if ((ahci->regHbaIs >> i) & 0x01)
1639 Log((" P%d", i));
1640 }
1641 Log(("\n"));
1642#endif
1643
1644 *pu32Value = ahci->regHbaIs;
1645
1646 return VINF_SUCCESS;
1647}
1648
1649/**
1650 * Write to the global control register.
1651 */
1652static int HbaControl_w(PAHCI ahci, uint32_t iReg, uint32_t u32Value)
1653{
1654 Log(("%s: write u32Value=%#010x\n"
1655 "%s: AE=%d IE=%d HR=%d\n",
1656 __FUNCTION__, u32Value,
1657 __FUNCTION__, (u32Value & AHCI_HBA_CTRL_AE) >> 31, (u32Value & AHCI_HBA_CTRL_IE) >> 1,
1658 (u32Value & AHCI_HBA_CTRL_HR)));
1659
1660 ahci->regHbaCtrl = (u32Value & AHCI_HBA_CTRL_RW_MASK) | AHCI_HBA_CTRL_AE;
1661 if (ahci->regHbaCtrl & AHCI_HBA_CTRL_HR)
1662 ahciHBAReset(ahci);
1663 return VINF_SUCCESS;
1664}
1665
1666/**
1667 * Read the global control register.
1668 */
1669static int HbaControl_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)
1670{
1671 Log(("%s: read regHbaCtrl=%#010x\n"
1672 "%s: AE=%d IE=%d HR=%d\n",
1673 __FUNCTION__, ahci->regHbaCtrl,
1674 __FUNCTION__, (ahci->regHbaCtrl & AHCI_HBA_CTRL_AE) >> 31, (ahci->regHbaCtrl & AHCI_HBA_CTRL_IE) >> 1,
1675 (ahci->regHbaCtrl & AHCI_HBA_CTRL_HR)));
1676 *pu32Value = ahci->regHbaCtrl;
1677 return VINF_SUCCESS;
1678}
1679
1680/**
1681 * Read the global capabilities register.
1682 */
1683static int HbaCapabilities_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)
1684{
1685 Log(("%s: read regHbaCap=%#010x\n"
1686 "%s: S64A=%d SNCQ=%d SIS=%d SSS=%d SALP=%d SAL=%d SCLO=%d ISS=%d SNZO=%d SAM=%d SPM=%d PMD=%d SSC=%d PSC=%d NCS=%d NP=%d\n",
1687 __FUNCTION__, ahci->regHbaCap,
1688 __FUNCTION__, (ahci->regHbaCap & AHCI_HBA_CAP_S64A) >> 31, (ahci->regHbaCap & AHCI_HBA_CAP_SNCQ) >> 30,
1689 (ahci->regHbaCap & AHCI_HBA_CAP_SIS) >> 28, (ahci->regHbaCap & AHCI_HBA_CAP_SSS) >> 27,
1690 (ahci->regHbaCap & AHCI_HBA_CAP_SALP) >> 26, (ahci->regHbaCap & AHCI_HBA_CAP_SAL) >> 25,
1691 (ahci->regHbaCap & AHCI_HBA_CAP_SCLO) >> 24, (ahci->regHbaCap & AHCI_HBA_CAP_ISS) >> 20,
1692 (ahci->regHbaCap & AHCI_HBA_CAP_SNZO) >> 19, (ahci->regHbaCap & AHCI_HBA_CAP_SAM) >> 18,
1693 (ahci->regHbaCap & AHCI_HBA_CAP_SPM) >> 17, (ahci->regHbaCap & AHCI_HBA_CAP_PMD) >> 15,
1694 (ahci->regHbaCap & AHCI_HBA_CAP_SSC) >> 14, (ahci->regHbaCap & AHCI_HBA_CAP_PSC) >> 13,
1695 (ahci->regHbaCap & AHCI_HBA_CAP_NCS) >> 8, (ahci->regHbaCap & AHCI_HBA_CAP_NP)));
1696 *pu32Value = ahci->regHbaCap;
1697 return VINF_SUCCESS;
1698}
1699
1700/**
1701 * Write to the global command completion coalescing control register.
1702 */
1703static int HbaCccCtl_w(PAHCI ahci, uint32_t iReg, uint32_t u32Value)
1704{
1705 Log(("%s: write u32Value=%#010x\n"
1706 "%s: TV=%d CC=%d INT=%d EN=%d\n",
1707 __FUNCTION__, u32Value,
1708 __FUNCTION__, AHCI_HBA_CCC_CTL_TV_GET(u32Value), AHCI_HBA_CCC_CTL_CC_GET(u32Value),
1709 AHCI_HBA_CCC_CTL_INT_GET(u32Value), (u32Value & AHCI_HBA_CCC_CTL_EN)));
1710
1711 ahci->regHbaCccCtl = u32Value;
1712 ahci->uCccTimeout = AHCI_HBA_CCC_CTL_TV_GET(u32Value);
1713 ahci->uCccPortNr = AHCI_HBA_CCC_CTL_INT_GET(u32Value);
1714 ahci->uCccNr = AHCI_HBA_CCC_CTL_CC_GET(u32Value);
1715
1716 if (u32Value & AHCI_HBA_CCC_CTL_EN)
1717 {
1718 /* Arm the timer */
1719 TMTimerSetMillies(ahci->CTX_SUFF(pHbaCccTimer), ahci->uCccTimeout);
1720 }
1721 else
1722 {
1723 TMTimerStop(ahci->CTX_SUFF(pHbaCccTimer));
1724 }
1725
1726 return VINF_SUCCESS;
1727}
1728
1729/**
1730 * Read the global command completion coalescing control register.
1731 */
1732static int HbaCccCtl_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)
1733{
1734 Log(("%s: read regHbaCccCtl=%#010x\n"
1735 "%s: TV=%d CC=%d INT=%d EN=%d\n",
1736 __FUNCTION__, ahci->regHbaCccCtl,
1737 __FUNCTION__, AHCI_HBA_CCC_CTL_TV_GET(ahci->regHbaCccCtl), AHCI_HBA_CCC_CTL_CC_GET(ahci->regHbaCccCtl),
1738 AHCI_HBA_CCC_CTL_INT_GET(ahci->regHbaCccCtl), (ahci->regHbaCccCtl & AHCI_HBA_CCC_CTL_EN)));
1739 *pu32Value = ahci->regHbaCccCtl;
1740 return VINF_SUCCESS;
1741}
1742
1743/**
1744 * Write to the global command completion coalescing ports register.
1745 */
1746static int HbaCccPorts_w(PAHCI ahci, uint32_t iReg, uint32_t u32Value)
1747{
1748 Log(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1749
1750 ahci->regHbaCccPorts = u32Value;
1751
1752 return VINF_SUCCESS;
1753}
1754
1755/**
1756 * Read the global command completion coalescing ports register.
1757 */
1758static int HbaCccPorts_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)
1759{
1760 Log(("%s: read regHbaCccPorts=%#010x\n", __FUNCTION__, ahci->regHbaCccPorts));
1761
1762#ifdef LOG_ENABLED
1763 Log(("%s:", __FUNCTION__));
1764 unsigned i;
1765 for (i = 0; i < ahci->cPortsImpl; i++)
1766 {
1767 if ((ahci->regHbaCccPorts >> i) & 0x01)
1768 Log((" P%d", i));
1769 }
1770 Log(("\n"));
1771#endif
1772
1773 *pu32Value = ahci->regHbaCccPorts;
1774 return VINF_SUCCESS;
1775}
1776
1777/**
1778 * Invalid write to global register
1779 */
1780static int HbaInvalid_w(PAHCI ahci, uint32_t iReg, uint32_t u32Value)
1781{
1782 Log(("%s: Write denied!!! iReg=%u u32Value=%#010x\n", __FUNCTION__, iReg, u32Value));
1783 return VINF_SUCCESS;
1784}
1785
1786/**
1787 * Invalid Port write.
1788 */
1789static int PortInvalid_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1790{
1791 ahciLog(("%s: Write denied!!! iReg=%u u32Value=%#010x\n", __FUNCTION__, iReg, u32Value));
1792 return VINF_SUCCESS;
1793}
1794
1795/**
1796 * Invalid Port read.
1797 */
1798static int PortInvalid_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1799{
1800 ahciLog(("%s: Read denied!!! iReg=%u\n", __FUNCTION__, iReg));
1801 return VINF_SUCCESS;
1802}
1803
1804/**
1805 * Register descriptor table for global HBA registers
1806 */
1807static const AHCIOPREG g_aOpRegs[] =
1808{
1809 {"HbaCapabilites", HbaCapabilities_r, HbaInvalid_w}, /* Readonly */
1810 {"HbaControl" , HbaControl_r, HbaControl_w},
1811 {"HbaInterruptStatus", HbaInterruptStatus_r, HbaInterruptStatus_w},
1812 {"HbaPortsImplemented", HbaPortsImplemented_r, HbaInvalid_w}, /* Readonly */
1813 {"HbaVersion", HbaVersion_r, HbaInvalid_w}, /* ReadOnly */
1814 {"HbaCccCtl", HbaCccCtl_r, HbaCccCtl_w},
1815 {"HbaCccPorts", HbaCccPorts_r, HbaCccPorts_w},
1816};
1817
1818/**
1819 * Register descriptor table for port registers
1820 */
1821static const AHCIPORTOPREG g_aPortOpRegs[] =
1822{
1823 {"PortCmdLstAddr", PortCmdLstAddr_r, PortCmdLstAddr_w},
1824 {"PortCmdLstAddrUp", PortCmdLstAddrUp_r, PortCmdLstAddrUp_w},
1825 {"PortFisAddr", PortFisAddr_r, PortFisAddr_w},
1826 {"PortFisAddrUp", PortFisAddrUp_r, PortFisAddrUp_w},
1827 {"PortIntrSts", PortIntrSts_r, PortIntrSts_w},
1828 {"PortIntrEnable", PortIntrEnable_r, PortIntrEnable_w},
1829 {"PortCmd", PortCmd_r, PortCmd_w},
1830 {"PortReserved1", PortInvalid_r, PortInvalid_w}, /* Not used. */
1831 {"PortTaskFileData", PortTaskFileData_r, PortInvalid_w}, /* Readonly */
1832 {"PortSignature", PortSignature_r, PortInvalid_w}, /* Readonly */
1833 {"PortSStatus", PortSStatus_r, PortInvalid_w}, /* Readonly */
1834 {"PortSControl", PortSControl_r, PortSControl_w},
1835 {"PortSError", PortSError_r, PortSError_w},
1836 {"PortSActive", PortSActive_r, PortSActive_w},
1837 {"PortCmdIssue", PortCmdIssue_r, PortCmdIssue_w},
1838 {"PortReserved2", PortInvalid_r, PortInvalid_w}, /* Not used. */
1839};
1840
1841/**
1842 * Reset initiated by system software for one port.
1843 *
1844 * @param pAhciPort The port to reset.
1845 */
1846static void ahciPortSwReset(PAHCIPort pAhciPort)
1847{
1848 pAhciPort->regIS = 0;
1849 pAhciPort->regIE = 0;
1850 pAhciPort->regCMD = AHCI_PORT_CMD_CPD | /* Cold presence detection */
1851 AHCI_PORT_CMD_SUD | /* Device has spun up. */
1852 AHCI_PORT_CMD_POD; /* Port is powered on. */
1853 pAhciPort->regTFD = (1 << 8) | ATA_STAT_SEEK | ATA_STAT_WRERR;
1854 pAhciPort->regSIG = ~0;
1855 pAhciPort->regSSTS = 0;
1856 pAhciPort->regSCTL = 0;
1857 pAhciPort->regSERR = 0;
1858 pAhciPort->regSACT = 0;
1859 pAhciPort->regCI = 0;
1860
1861 pAhciPort->fResetDevice = false;
1862 pAhciPort->fPoweredOn = true;
1863 pAhciPort->fSpunUp = true;
1864 pAhciPort->fNotificationSend = false;
1865 pAhciPort->cMultSectors = ATA_MAX_MULT_SECTORS;
1866 pAhciPort->uATATransferMode = ATA_MODE_UDMA | 6;
1867
1868 pAhciPort->u32TasksFinished = 0;
1869 pAhciPort->u32QueuedTasksFinished = 0;
1870
1871 pAhciPort->uActWritePos = 0;
1872 pAhciPort->uActReadPos = 0;
1873 pAhciPort->uActTasksActive = 0;
1874
1875 if (pAhciPort->pDrvBase)
1876 {
1877 pAhciPort->regCMD |= AHCI_PORT_CMD_CPS; /* Indicate that there is a device on that port */
1878
1879 if (pAhciPort->fPoweredOn)
1880 {
1881 /*
1882 * Set states in the Port Signature and SStatus registers.
1883 */
1884 pAhciPort->regSIG = 0x101; /* Signature for SATA device. */
1885 pAhciPort->regSSTS = (0x01 << 8) | /* Interface is active. */
1886 (0x02 << 4) | /* Generation 2 (3.0GBps) speed. */
1887 (0x03 << 0); /* Device detected and communication established. */
1888 }
1889 }
1890}
1891
1892#ifdef IN_RING3
1893/**
1894 * Hardware reset used for machine power on and reset.
1895 *
1896 * @param pAhciport The port to reset.
1897 */
1898static void ahciPortHwReset(PAHCIPort pAhciPort)
1899{
1900 /* Reset the address registers. */
1901 pAhciPort->regCLB = 0;
1902 pAhciPort->regCLBU = 0;
1903 pAhciPort->regFB = 0;
1904 pAhciPort->regFBU = 0;
1905
1906 /* Reset calculated addresses. */
1907 pAhciPort->GCPhysAddrClb = 0;
1908 pAhciPort->GCPhysAddrFb = 0;
1909}
1910#endif
1911
1912/**
1913 * Create implemented ports bitmap.
1914 *
1915 * @returns 32bit bitmask with a bit set for every implemented port.
1916 * @param cPorts Number of ports.
1917 */
1918static uint32_t ahciGetPortsImplemented(unsigned cPorts)
1919{
1920 uint32_t uPortsImplemented = 0;
1921
1922 for (unsigned i = 0; i < cPorts; i++)
1923 uPortsImplemented |= (1 << i);
1924
1925 return uPortsImplemented;
1926}
1927
1928/**
1929 * Reset the entire HBA.
1930 *
1931 * @param pThis The HBA state.
1932 */
1933static void ahciHBAReset(PAHCI pThis)
1934{
1935 unsigned i;
1936 int rc = VINF_SUCCESS;
1937
1938 LogFlow(("Reset the HBA controller\n"));
1939
1940 /* Stop the CCC timer. */
1941 if (pThis->regHbaCccCtl & AHCI_HBA_CCC_CTL_EN)
1942 {
1943 rc = TMTimerStop(pThis->CTX_SUFF(pHbaCccTimer));
1944 if (RT_FAILURE(rc))
1945 AssertMsgFailed(("%s: Failed to stop timer!\n", __FUNCTION__));
1946 }
1947
1948 /* Reset every port */
1949 for (i = 0; i < pThis->cPortsImpl; i++)
1950 {
1951 PAHCIPort pAhciPort = &pThis->ahciPort[i];
1952
1953 pAhciPort->iLUN = i;
1954 ahciPortSwReset(pAhciPort);
1955 }
1956
1957 /* Init Global registers */
1958 pThis->regHbaCap = AHCI_HBA_CAP_ISS_SHIFT(AHCI_HBA_CAP_ISS_GEN2) |
1959 AHCI_HBA_CAP_S64A | /* 64bit addressing supported */
1960 AHCI_HBA_CAP_SAM | /* AHCI mode only */
1961 AHCI_HBA_CAP_SNCQ | /* Support native command queuing */
1962 AHCI_HBA_CAP_SSS | /* Staggered spin up */
1963 AHCI_HBA_CAP_CCCS | /* Support command completion coalescing */
1964 AHCI_HBA_CAP_NCS_SET(AHCI_NR_COMMAND_SLOTS) | /* Number of command slots we support */
1965 AHCI_HBA_CAP_NP_SET(pThis->cPortsImpl); /* Number of supported ports */
1966 pThis->regHbaCtrl = AHCI_HBA_CTRL_AE;
1967 pThis->regHbaIs = 0;
1968 pThis->regHbaPi = ahciGetPortsImplemented(pThis->cPortsImpl);
1969 pThis->regHbaVs = AHCI_HBA_VS_MJR | AHCI_HBA_VS_MNR;
1970 pThis->regHbaCccCtl = 0;
1971 pThis->regHbaCccPorts = 0;
1972 pThis->uCccTimeout = 0;
1973 pThis->uCccPortNr = 0;
1974 pThis->uCccNr = 0;
1975
1976 pThis->f64BitAddr = false;
1977 pThis->u32PortsInterrupted = 0;
1978 pThis->f8ByteMMIO4BytesWrittenSuccessfully = false;
1979 /* Clear the HBA Reset bit */
1980 pThis->regHbaCtrl &= ~AHCI_HBA_CTRL_HR;
1981}
1982
1983/**
1984 * Memory mapped I/O Handler for read operations.
1985 *
1986 * @returns VBox status code.
1987 *
1988 * @param pDevIns The device instance.
1989 * @param pvUser User argument.
1990 * @param GCPhysAddr Physical address (in GC) where the read starts.
1991 * @param pv Where to store the result.
1992 * @param cb Number of bytes read.
1993 */
1994PDMBOTHCBDECL(int) ahciMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1995{
1996 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
1997 int rc = VINF_SUCCESS;
1998
1999 /* Break up 64 bits reads into two dword reads. */
2000 if (cb == 8)
2001 {
2002 rc = ahciMMIORead(pDevIns, pvUser, GCPhysAddr, pv, 4);
2003 if (RT_FAILURE(rc))
2004 return rc;
2005
2006 return ahciMMIORead(pDevIns, pvUser, GCPhysAddr + 4, (uint8_t *)pv + 4, 4);
2007 }
2008
2009 Log2(("#%d ahciMMIORead: pvUser=%p:{%.*Rhxs} cb=%d GCPhysAddr=%RGp rc=%Rrc\n",
2010 pDevIns->iInstance, pv, cb, pv, cb, GCPhysAddr, rc));
2011
2012 /*
2013 * If the access offset is smaller than AHCI_HBA_GLOBAL_SIZE the guest accesses the global registers.
2014 * Otherwise it accesses the registers of a port.
2015 */
2016 uint32_t uOffset = (GCPhysAddr - pAhci->MMIOBase);
2017 uint32_t iReg;
2018
2019 if (uOffset < AHCI_HBA_GLOBAL_SIZE)
2020 {
2021 iReg = uOffset >> 2;
2022 Log3(("%s: Trying to read from global register %u\n", __FUNCTION__, iReg));
2023 if (iReg < RT_ELEMENTS(g_aOpRegs))
2024 {
2025 const AHCIOPREG *pReg = &g_aOpRegs[iReg];
2026 rc = pReg->pfnRead(pAhci, iReg, (uint32_t *)pv);
2027 }
2028 else
2029 {
2030 Log3(("%s: Trying to read global register %u/%u!!!\n", __FUNCTION__, iReg, RT_ELEMENTS(g_aOpRegs)));
2031 *(uint32_t *)pv = 0;
2032 }
2033 }
2034 else
2035 {
2036 uint32_t iRegOffset;
2037 uint32_t iPort;
2038
2039 /* Calculate accessed port. */
2040 uOffset -= AHCI_HBA_GLOBAL_SIZE;
2041 iPort = uOffset / AHCI_PORT_REGISTER_SIZE;
2042 iRegOffset = (uOffset % AHCI_PORT_REGISTER_SIZE);
2043 iReg = iRegOffset >> 2;
2044
2045 Log3(("%s: Trying to read from port %u and register %u\n", __FUNCTION__, iPort, iReg));
2046
2047 if (RT_LIKELY( iPort < pAhci->cPortsImpl
2048 && iReg < RT_ELEMENTS(g_aPortOpRegs)))
2049 {
2050 const AHCIPORTOPREG *pPortReg = &g_aPortOpRegs[iReg];
2051 rc = pPortReg->pfnRead(pAhci, &pAhci->ahciPort[iPort], iReg, (uint32_t *)pv);
2052 }
2053 else
2054 {
2055 Log3(("%s: Trying to read port %u register %u/%u!!!\n", __FUNCTION__, iPort, iReg, RT_ELEMENTS(g_aPortOpRegs)));
2056 rc = VINF_IOM_MMIO_UNUSED_00;
2057 }
2058
2059 /*
2060 * Windows Vista tries to read one byte from some registers instead of four.
2061 * Correct the value according to the read size.
2062 */
2063 if (RT_SUCCESS(rc) && cb != sizeof(uint32_t))
2064 {
2065 switch (cb)
2066 {
2067 case 1:
2068 {
2069 uint8_t uNewValue;
2070 uint8_t *p = (uint8_t *)pv;
2071
2072 iRegOffset &= 3;
2073 Log3(("%s: iRegOffset=%u\n", __FUNCTION__, iRegOffset));
2074 uNewValue = p[iRegOffset];
2075 /* Clear old value */
2076 *(uint32_t *)pv = 0;
2077 *(uint8_t *)pv = uNewValue;
2078 break;
2079 }
2080 default:
2081 AssertMsgFailed(("%s: unsupported access width cb=%d uOffset=%x iPort=%x iRegOffset=%x iReg=%x!!!\n", __FUNCTION__, cb, uOffset, iPort, iRegOffset, iReg));
2082 }
2083 }
2084 }
2085
2086 Log2(("#%d ahciMMIORead: return pvUser=%p:{%.*Rhxs} cb=%d GCPhysAddr=%RGp rc=%Rrc\n",
2087 pDevIns->iInstance, pv, cb, pv, cb, GCPhysAddr, rc));
2088 return rc;
2089}
2090
2091
2092/**
2093 * Memory mapped I/O Handler for write operations.
2094 *
2095 * @returns VBox status code.
2096 *
2097 * @param pDevIns The device instance.
2098 * @param pvUser User argument.
2099 * @param GCPhysAddr Physical address (in GC) where the read starts.
2100 * @param pv Where to fetch the result.
2101 * @param cb Number of bytes to write.
2102 */
2103PDMBOTHCBDECL(int) ahciMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2104{
2105 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
2106 int rc = VINF_SUCCESS;
2107
2108 /* Break up 64 bits writes into two dword writes. */
2109 if (cb == 8)
2110 {
2111 /*
2112 * Only write the first 4 bytes if they weren't already.
2113 * It is possible that the last write to the register caused a world
2114 * switch and we entered this function again.
2115 * Writing the first 4 bytes again could cause indeterminate behavior
2116 * which can cause errors in the guest.
2117 */
2118 if (!pAhci->f8ByteMMIO4BytesWrittenSuccessfully)
2119 {
2120 rc = ahciMMIOWrite(pDevIns, pvUser, GCPhysAddr, pv, 4);
2121 if (rc != VINF_SUCCESS)
2122 return rc;
2123
2124 pAhci->f8ByteMMIO4BytesWrittenSuccessfully = true;
2125 }
2126
2127 rc = ahciMMIOWrite(pDevIns, pvUser, GCPhysAddr + 4, (uint8_t *)pv + 4, 4);
2128 /*
2129 * Reset flag again so that the first 4 bytes are written again on the next
2130 * 8byte MMIO access.
2131 */
2132 if (rc == VINF_SUCCESS)
2133 pAhci->f8ByteMMIO4BytesWrittenSuccessfully = false;
2134
2135 return rc;
2136 }
2137
2138 Log2(("#%d ahciMMIOWrite: pvUser=%p:{%.*Rhxs} cb=%d GCPhysAddr=%RGp\n",
2139 pDevIns->iInstance, pv, cb, pv, cb, GCPhysAddr));
2140
2141 /* Validate access. */
2142 if (cb != sizeof(uint32_t))
2143 {
2144 Log2(("%s: Bad write size!!! GCPhysAddr=%RGp cb=%d\n", __FUNCTION__, GCPhysAddr, cb));
2145 return VINF_SUCCESS;
2146 }
2147 if (GCPhysAddr & 0x3)
2148 {
2149 Log2(("%s: Unaligned write!!! GCPhysAddr=%RGp cb=%d\n", __FUNCTION__, GCPhysAddr, cb));
2150 return VINF_SUCCESS;
2151 }
2152
2153 /*
2154 * If the access offset is smaller than 100h the guest accesses the global registers.
2155 * Otherwise it accesses the registers of a port.
2156 */
2157 uint32_t uOffset = (GCPhysAddr - pAhci->MMIOBase);
2158 uint32_t iReg;
2159 if (uOffset < AHCI_HBA_GLOBAL_SIZE)
2160 {
2161 Log3(("Write global HBA register\n"));
2162 iReg = uOffset >> 2;
2163 if (iReg < RT_ELEMENTS(g_aOpRegs))
2164 {
2165 const AHCIOPREG *pReg = &g_aOpRegs[iReg];
2166 rc = pReg->pfnWrite(pAhci, iReg, *(uint32_t *)pv);
2167 }
2168 else
2169 {
2170 Log3(("%s: Trying to write global register %u/%u!!!\n", __FUNCTION__, iReg, RT_ELEMENTS(g_aOpRegs)));
2171 rc = VINF_SUCCESS;
2172 }
2173 }
2174 else
2175 {
2176 uint32_t iPort;
2177 Log3(("Write Port register\n"));
2178 /* Calculate accessed port. */
2179 uOffset -= AHCI_HBA_GLOBAL_SIZE;
2180 iPort = uOffset / AHCI_PORT_REGISTER_SIZE;
2181 iReg = (uOffset % AHCI_PORT_REGISTER_SIZE) >> 2;
2182 Log3(("%s: Trying to write to port %u and register %u\n", __FUNCTION__, iPort, iReg));
2183 if (RT_LIKELY( iPort < pAhci->cPortsImpl
2184 && iReg < RT_ELEMENTS(g_aPortOpRegs)))
2185 {
2186 const AHCIPORTOPREG *pPortReg = &g_aPortOpRegs[iReg];
2187 rc = pPortReg->pfnWrite(pAhci, &pAhci->ahciPort[iPort], iReg, *(uint32_t *)pv);
2188 }
2189 else
2190 {
2191 Log3(("%s: Trying to write port %u register %u/%u!!!\n", __FUNCTION__, iPort, iReg, RT_ELEMENTS(g_aPortOpRegs)));
2192 rc = VINF_SUCCESS;
2193 }
2194 }
2195
2196 return rc;
2197}
2198
2199PDMBOTHCBDECL(int) ahciIOPortWrite1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2200{
2201 uint32_t iChannel = (uint32_t)(uintptr_t)pvUser;
2202 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
2203 PAHCIATACONTROLLER pCtl = &pAhci->aCts[iChannel];
2204
2205 Assert(iChannel < 2);
2206
2207 return ataControllerIOPortWrite1(pCtl, Port, u32, cb);
2208}
2209
2210PDMBOTHCBDECL(int) ahciIOPortRead1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
2211{
2212 uint32_t iChannel = (uint32_t)(uintptr_t)pvUser;
2213 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
2214 PAHCIATACONTROLLER pCtl = &pAhci->aCts[iChannel];
2215
2216 Assert(iChannel < 2);
2217
2218 return ataControllerIOPortRead1(pCtl, Port, pu32, cb);
2219}
2220
2221PDMBOTHCBDECL(int) ahciIOPortWrite2(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2222{
2223 uint32_t iChannel = (uint32_t)(uintptr_t)pvUser;
2224 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
2225 PAHCIATACONTROLLER pCtl = &pAhci->aCts[iChannel];
2226
2227 Assert(iChannel < 2);
2228
2229 return ataControllerIOPortWrite2(pCtl, Port, u32, cb);
2230}
2231
2232PDMBOTHCBDECL(int) ahciIOPortRead2(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
2233{
2234 uint32_t iChannel = (uint32_t)(uintptr_t)pvUser;
2235 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
2236 PAHCIATACONTROLLER pCtl = &pAhci->aCts[iChannel];
2237
2238 Assert(iChannel < 2);
2239
2240 return ataControllerIOPortRead2(pCtl, Port, pu32, cb);
2241}
2242
2243PDMBOTHCBDECL(int) ahciLegacyFakeWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2244{
2245 AssertMsgFailed(("Should not happen\n"));
2246 return VINF_SUCCESS;
2247}
2248
2249PDMBOTHCBDECL(int) ahciLegacyFakeRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
2250{
2251 AssertMsgFailed(("Should not happen\n"));
2252 return VINF_SUCCESS;
2253}
2254
2255#ifndef IN_RING0
2256/**
2257 * Port I/O Handler for primary port range IN string operations.
2258 * @see FNIOMIOPORTINSTRING for details.
2259 */
2260PDMBOTHCBDECL(int) ahciIOPortReadStr1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrDst, PRTGCUINTREG pcTransfer, unsigned cb)
2261{
2262 uint32_t iChannel = (uint32_t)(uintptr_t)pvUser;
2263 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
2264 PAHCIATACONTROLLER pCtl = &pAhci->aCts[iChannel];
2265
2266 Assert(iChannel < 2);
2267
2268 return ataControllerIOPortReadStr1(pCtl, Port, pGCPtrDst, pcTransfer, cb);
2269}
2270
2271
2272/**
2273 * Port I/O Handler for primary port range OUT string operations.
2274 * @see FNIOMIOPORTOUTSTRING for details.
2275 */
2276PDMBOTHCBDECL(int) ahciIOPortWriteStr1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrSrc, PRTGCUINTREG pcTransfer, unsigned cb)
2277{
2278 uint32_t iChannel = (uint32_t)(uintptr_t)pvUser;
2279 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
2280 PAHCIATACONTROLLER pCtl = &pAhci->aCts[iChannel];
2281
2282 Assert(iChannel < 2);
2283
2284 return ataControllerIOPortReadStr1(pCtl, Port, pGCPtrSrc, pcTransfer, cb);
2285}
2286#endif /* !IN_RING0 */
2287
2288#ifdef IN_RING3
2289
2290static DECLCALLBACK(int) ahciR3MMIOMap(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
2291{
2292 PAHCI pThis = PCIDEV_2_PAHCI(pPciDev);
2293 PPDMDEVINS pDevIns = pPciDev->pDevIns;
2294 int rc = VINF_SUCCESS;
2295
2296 Log2(("%s: registering MMIO area at GCPhysAddr=%RGp cb=%u\n", __FUNCTION__, GCPhysAddress, cb));
2297
2298 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
2299 Assert(cb >= 4352);
2300
2301 /* We use the assigned size here, because we currently only support page aligned MMIO ranges. */
2302 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL,
2303 ahciMMIOWrite, ahciMMIORead, NULL, "AHCI");
2304 if (RT_FAILURE(rc))
2305 return rc;
2306
2307 if (pThis->fR0Enabled)
2308 {
2309 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, 0,
2310 "ahciMMIOWrite", "ahciMMIORead", NULL);
2311 if (RT_FAILURE(rc))
2312 return rc;
2313 }
2314
2315 if (pThis->fGCEnabled)
2316 {
2317 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, 0,
2318 "ahciMMIOWrite", "ahciMMIORead", NULL);
2319 if (RT_FAILURE(rc))
2320 return rc;
2321 }
2322
2323 pThis->MMIOBase = GCPhysAddress;
2324 return rc;
2325}
2326
2327/**
2328 * Map the legacy I/O port ranges to make Solaris work with the controller.
2329 */
2330static DECLCALLBACK(int) ahciR3LegacyFakeIORangeMap(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
2331{
2332 PAHCI pThis = PCIDEV_2_PAHCI(pPciDev);
2333 PPDMDEVINS pDevIns = pPciDev->pDevIns;
2334 int rc = VINF_SUCCESS;
2335
2336 Log2(("%s: registering fake I/O area at GCPhysAddr=%RGp cb=%u\n", __FUNCTION__, GCPhysAddress, cb));
2337
2338 Assert(enmType == PCI_ADDRESS_SPACE_IO);
2339
2340 /* We use the assigned size here, because we currently only support page aligned MMIO ranges. */
2341 rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, NULL,
2342 ahciLegacyFakeWrite, ahciLegacyFakeRead, NULL, NULL, "AHCI Fake");
2343 if (RT_FAILURE(rc))
2344 return rc;
2345
2346 if (pThis->fR0Enabled)
2347 {
2348 rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
2349 "ahciLegacyFakeWrite", "ahciLegacyFakeRead", NULL, NULL, "AHCI Fake");
2350 if (RT_FAILURE(rc))
2351 return rc;
2352 }
2353
2354 if (pThis->fGCEnabled)
2355 {
2356 rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
2357 "ahciLegacyFakeWrite", "ahciLegacyFakeRead", NULL, NULL, "AHCI Fake");
2358 if (RT_FAILURE(rc))
2359 return rc;
2360 }
2361
2362 return rc;
2363}
2364
2365/* -=-=-=-=-=- PAHCI::ILeds -=-=-=-=-=- */
2366
2367/**
2368 * Gets the pointer to the status LED of a unit.
2369 *
2370 * @returns VBox status code.
2371 * @param pInterface Pointer to the interface structure containing the called function pointer.
2372 * @param iLUN The unit which status LED we desire.
2373 * @param ppLed Where to store the LED pointer.
2374 */
2375static DECLCALLBACK(int) ahciR3Status_QueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
2376{
2377 PAHCI pAhci = PDMILEDPORTS_2_PAHCI(pInterface);
2378 if (iLUN < AHCI_MAX_NR_PORTS_IMPL)
2379 {
2380 *ppLed = &pAhci->ahciPort[iLUN].Led;
2381 Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
2382 return VINF_SUCCESS;
2383 }
2384 return VERR_PDM_LUN_NOT_FOUND;
2385}
2386
2387/**
2388 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2389 */
2390static DECLCALLBACK(void *) ahciR3Status_QueryInterface(PPDMIBASE pInterface, const char *pszIID)
2391{
2392 PAHCI pThis = PDMIBASE_2_PAHCI(pInterface);
2393 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
2394 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
2395 return NULL;
2396}
2397
2398/**
2399 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2400 */
2401static DECLCALLBACK(void *) ahciR3PortQueryInterface(PPDMIBASE pInterface, const char *pszIID)
2402{
2403 PAHCIPort pAhciPort = PDMIBASE_2_PAHCIPORT(pInterface);
2404 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pAhciPort->IBase);
2405 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBLOCKPORT, &pAhciPort->IPort);
2406 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBLOCKASYNCPORT, &pAhciPort->IPortAsync);
2407 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIMOUNTNOTIFY, &pAhciPort->IMountNotify);
2408 return NULL;
2409}
2410
2411#ifdef DEBUG
2412
2413/**
2414 * Dump info about the FIS
2415 *
2416 * @returns nothing
2417 * @param pAhciPort The port the command FIS was read from.
2418 * @param cmdFis The FIS to print info from.
2419 */
2420static void ahciDumpFisInfo(PAHCIPort pAhciPort, uint8_t *cmdFis)
2421{
2422 ahciLog(("%s: *** Begin FIS info dump. ***\n", __FUNCTION__));
2423 /* Print FIS type. */
2424 switch (cmdFis[AHCI_CMDFIS_TYPE])
2425 {
2426 case AHCI_CMDFIS_TYPE_H2D:
2427 {
2428 ahciLog(("%s: Command Fis type: H2D\n", __FUNCTION__));
2429 ahciLog(("%s: Command Fis size: %d bytes\n", __FUNCTION__, AHCI_CMDFIS_TYPE_H2D_SIZE));
2430 if (cmdFis[AHCI_CMDFIS_BITS] & AHCI_CMDFIS_C)
2431 {
2432 ahciLog(("%s: Command register update\n", __FUNCTION__));
2433 }
2434 else
2435 {
2436 ahciLog(("%s: Control register update\n", __FUNCTION__));
2437 }
2438 ahciLog(("%s: CMD=%#04x \"%s\"\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CMD], ATACmdText(cmdFis[AHCI_CMDFIS_CMD])));
2439 ahciLog(("%s: FEAT=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_FET]));
2440 ahciLog(("%s: SECTN=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_SECTN]));
2441 ahciLog(("%s: CYLL=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CYLL]));
2442 ahciLog(("%s: CYLH=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CYLH]));
2443 ahciLog(("%s: HEAD=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_HEAD]));
2444
2445 ahciLog(("%s: SECTNEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_SECTNEXP]));
2446 ahciLog(("%s: CYLLEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CYLLEXP]));
2447 ahciLog(("%s: CYLHEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CYLHEXP]));
2448 ahciLog(("%s: FETEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_FETEXP]));
2449
2450 ahciLog(("%s: SECTC=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_SECTC]));
2451 ahciLog(("%s: SECTCEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_SECTCEXP]));
2452 ahciLog(("%s: CTL=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CTL]));
2453 if (cmdFis[AHCI_CMDFIS_CTL] & AHCI_CMDFIS_CTL_SRST)
2454 {
2455 ahciLog(("%s: Reset bit is set\n", __FUNCTION__));
2456 }
2457 }
2458 break;
2459 case AHCI_CMDFIS_TYPE_D2H:
2460 {
2461 ahciLog(("%s: Command Fis type D2H\n", __FUNCTION__));
2462 ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_D2H_SIZE));
2463 }
2464 break;
2465 case AHCI_CMDFIS_TYPE_SETDEVBITS:
2466 {
2467 ahciLog(("%s: Command Fis type Set Device Bits\n", __FUNCTION__));
2468 ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_SETDEVBITS_SIZE));
2469 }
2470 break;
2471 case AHCI_CMDFIS_TYPE_DMAACTD2H:
2472 {
2473 ahciLog(("%s: Command Fis type DMA Activate H2D\n", __FUNCTION__));
2474 ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_DMAACTD2H_SIZE));
2475 }
2476 break;
2477 case AHCI_CMDFIS_TYPE_DMASETUP:
2478 {
2479 ahciLog(("%s: Command Fis type DMA Setup\n", __FUNCTION__));
2480 ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_DMASETUP_SIZE));
2481 }
2482 break;
2483 case AHCI_CMDFIS_TYPE_PIOSETUP:
2484 {
2485 ahciLog(("%s: Command Fis type PIO Setup\n", __FUNCTION__));
2486 ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_PIOSETUP_SIZE));
2487 }
2488 break;
2489 case AHCI_CMDFIS_TYPE_DATA:
2490 {
2491 ahciLog(("%s: Command Fis type Data\n", __FUNCTION__));
2492 }
2493 break;
2494 default:
2495 ahciLog(("%s: ERROR Unknown command FIS type\n", __FUNCTION__));
2496 break;
2497 }
2498 ahciLog(("%s: *** End FIS info dump. ***\n", __FUNCTION__));
2499}
2500
2501/**
2502 * Dump info about the command header
2503 *
2504 * @returns nothing
2505 * @param pAhciPort Poitner to the port the command header was read from.
2506 * @param pCmdHdr The command header to print info from.
2507 */
2508static void ahciDumpCmdHdrInfo(PAHCIPort pAhciPort, CmdHdr *pCmdHdr)
2509{
2510 ahciLog(("%s: *** Begin command header info dump. ***\n", __FUNCTION__));
2511 ahciLog(("%s: Number of Scatter/Gatther List entries: %u\n", __FUNCTION__, AHCI_CMDHDR_PRDTL_ENTRIES(pCmdHdr->u32DescInf)));
2512 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_C)
2513 ahciLog(("%s: Clear busy upon R_OK\n", __FUNCTION__));
2514 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_B)
2515 ahciLog(("%s: BIST Fis\n", __FUNCTION__));
2516 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_R)
2517 ahciLog(("%s: Device Reset Fis\n", __FUNCTION__));
2518 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_P)
2519 ahciLog(("%s: Command prefetchable\n", __FUNCTION__));
2520 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_W)
2521 ahciLog(("%s: Device write\n", __FUNCTION__));
2522 else
2523 ahciLog(("%s: Device read\n", __FUNCTION__));
2524 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_A)
2525 ahciLog(("%s: ATAPI command\n", __FUNCTION__));
2526 else
2527 ahciLog(("%s: ATA command\n", __FUNCTION__));
2528
2529 ahciLog(("%s: Command FIS length %u DW\n", __FUNCTION__, (pCmdHdr->u32DescInf & AHCI_CMDHDR_CFL_MASK)));
2530 ahciLog(("%s: *** End command header info dump. ***\n", __FUNCTION__));
2531}
2532#endif /* DEBUG */
2533
2534/**
2535 * Post the first D2H FIS from the device into guest memory.
2536 *
2537 * @returns nothing
2538 * @param pAhciPort Pointer to the port which "receives" the FIS.
2539 */
2540static void ahciPostFirstD2HFisIntoMemory(PAHCIPort pAhciPort)
2541{
2542 uint8_t d2hFis[AHCI_CMDFIS_TYPE_D2H_SIZE];
2543
2544 pAhciPort->fFirstD2HFisSend = true;
2545
2546 ahciLog(("%s: Sending First D2H FIS from FIFO\n", __FUNCTION__));
2547 memset(&d2hFis[0], 0, sizeof(d2hFis));
2548 d2hFis[AHCI_CMDFIS_TYPE] = AHCI_CMDFIS_TYPE_D2H;
2549 d2hFis[AHCI_CMDFIS_ERR] = 0x01;
2550
2551 d2hFis[AHCI_CMDFIS_STS] = 0x00;
2552
2553 /* Set the signature based on the device type. */
2554 if (pAhciPort->fATAPI)
2555 {
2556 d2hFis[AHCI_CMDFIS_CYLL] = 0x14;
2557 d2hFis[AHCI_CMDFIS_CYLH] = 0xeb;
2558 }
2559 else
2560 {
2561 d2hFis[AHCI_CMDFIS_CYLL] = 0x00;
2562 d2hFis[AHCI_CMDFIS_CYLH] = 0x00;
2563 }
2564
2565 d2hFis[AHCI_CMDFIS_HEAD] = 0x00;
2566 d2hFis[AHCI_CMDFIS_SECTN] = 0x01;
2567 d2hFis[AHCI_CMDFIS_SECTC] = 0x01;
2568
2569 pAhciPort->regTFD = (1 << 8) | ATA_STAT_SEEK | ATA_STAT_WRERR;
2570
2571 ahciPostFisIntoMemory(pAhciPort, AHCI_CMDFIS_TYPE_D2H, d2hFis);
2572}
2573
2574/**
2575 * Post the FIS in the memory area allocated by the guest and set interrupt if neccessary.
2576 *
2577 * @returns VBox status code
2578 * @param pAhciPort The port which "receives" the FIS.
2579 * @param uFisType The type of the FIS.
2580 * @param pCmdFis Pointer to the FIS which is to be posted into memory.
2581 */
2582static int ahciPostFisIntoMemory(PAHCIPort pAhciPort, unsigned uFisType, uint8_t *pCmdFis)
2583{
2584 int rc = VINF_SUCCESS;
2585 RTGCPHYS GCPhysAddrRecFis = pAhciPort->GCPhysAddrFb;
2586 unsigned cbFis = 0;
2587
2588 ahciLog(("%s: pAhciPort=%p uFisType=%u pCmdFis=%p\n", __FUNCTION__, pAhciPort, uFisType, pCmdFis));
2589
2590 if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
2591 {
2592 AssertMsg(GCPhysAddrRecFis, ("%s: GCPhysAddrRecFis is 0\n", __FUNCTION__));
2593
2594 /* Determine the offset and size of the FIS based on uFisType. */
2595 switch (uFisType)
2596 {
2597 case AHCI_CMDFIS_TYPE_D2H:
2598 {
2599 GCPhysAddrRecFis += AHCI_RECFIS_RFIS_OFFSET;
2600 cbFis = AHCI_CMDFIS_TYPE_D2H_SIZE;
2601 }
2602 break;
2603 case AHCI_CMDFIS_TYPE_SETDEVBITS:
2604 {
2605 GCPhysAddrRecFis += AHCI_RECFIS_SDBFIS_OFFSET;
2606 cbFis = AHCI_CMDFIS_TYPE_SETDEVBITS_SIZE;
2607 }
2608 break;
2609 case AHCI_CMDFIS_TYPE_DMASETUP:
2610 {
2611 GCPhysAddrRecFis += AHCI_RECFIS_DSFIS_OFFSET;
2612 cbFis = AHCI_CMDFIS_TYPE_DMASETUP_SIZE;
2613 }
2614 break;
2615 case AHCI_CMDFIS_TYPE_PIOSETUP:
2616 {
2617 GCPhysAddrRecFis += AHCI_RECFIS_PSFIS_OFFSET;
2618 cbFis = AHCI_CMDFIS_TYPE_PIOSETUP_SIZE;
2619 }
2620 break;
2621 default:
2622 /*
2623 * We should post the unknown FIS into memory too but this never happens because
2624 * we know which FIS types we generate. ;)
2625 */
2626 AssertMsgFailed(("%s: Unknown FIS type!\n", __FUNCTION__));
2627 }
2628
2629 /* Post the FIS into memory. */
2630 ahciLog(("%s: PDMDevHlpPhysWrite GCPhysAddrRecFis=%RGp cbFis=%u\n", __FUNCTION__, GCPhysAddrRecFis, cbFis));
2631 PDMDevHlpPhysWrite(pAhciPort->CTX_SUFF(pDevIns), GCPhysAddrRecFis, pCmdFis, cbFis);
2632 }
2633
2634 return rc;
2635}
2636
2637DECLINLINE(void) ataH2BE_U16(uint8_t *pbBuf, uint16_t val)
2638{
2639 pbBuf[0] = val >> 8;
2640 pbBuf[1] = val;
2641}
2642
2643
2644DECLINLINE(void) ataH2BE_U24(uint8_t *pbBuf, uint32_t val)
2645{
2646 pbBuf[0] = val >> 16;
2647 pbBuf[1] = val >> 8;
2648 pbBuf[2] = val;
2649}
2650
2651
2652DECLINLINE(void) ataH2BE_U32(uint8_t *pbBuf, uint32_t val)
2653{
2654 pbBuf[0] = val >> 24;
2655 pbBuf[1] = val >> 16;
2656 pbBuf[2] = val >> 8;
2657 pbBuf[3] = val;
2658}
2659
2660
2661DECLINLINE(uint16_t) ataBE2H_U16(const uint8_t *pbBuf)
2662{
2663 return (pbBuf[0] << 8) | pbBuf[1];
2664}
2665
2666
2667DECLINLINE(uint32_t) ataBE2H_U24(const uint8_t *pbBuf)
2668{
2669 return (pbBuf[0] << 16) | (pbBuf[1] << 8) | pbBuf[2];
2670}
2671
2672
2673DECLINLINE(uint32_t) ataBE2H_U32(const uint8_t *pbBuf)
2674{
2675 return (pbBuf[0] << 24) | (pbBuf[1] << 16) | (pbBuf[2] << 8) | pbBuf[3];
2676}
2677
2678
2679DECLINLINE(void) ataLBA2MSF(uint8_t *pbBuf, uint32_t iATAPILBA)
2680{
2681 iATAPILBA += 150;
2682 pbBuf[0] = (iATAPILBA / 75) / 60;
2683 pbBuf[1] = (iATAPILBA / 75) % 60;
2684 pbBuf[2] = iATAPILBA % 75;
2685}
2686
2687
2688DECLINLINE(uint32_t) ataMSF2LBA(const uint8_t *pbBuf)
2689{
2690 return (pbBuf[0] * 60 + pbBuf[1]) * 75 + pbBuf[2];
2691}
2692
2693static void atapiCmdOK(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState)
2694{
2695 pAhciPortTaskState->uATARegError = 0;
2696 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
2697 pAhciPortTaskState->cmdFis[AHCI_CMDFIS_SECTN] = (pAhciPortTaskState->cmdFis[AHCI_CMDFIS_SECTN] & ~7)
2698 | ((pAhciPortTaskState->uTxDir != PDMBLOCKTXDIR_TO_DEVICE) ? ATAPI_INT_REASON_IO : 0)
2699 | (!pAhciPortTaskState->cbTransfer ? ATAPI_INT_REASON_CD : 0);
2700 pAhciPort->uATAPISenseKey = SCSI_SENSE_NONE;
2701 pAhciPort->uATAPIASC = SCSI_ASC_NONE;
2702}
2703
2704
2705static void atapiCmdError(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState, uint8_t uATAPISenseKey, uint8_t uATAPIASC)
2706{
2707 pAhciPortTaskState->uATARegError = uATAPISenseKey << 4;
2708 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_ERR;
2709 pAhciPortTaskState->cmdFis[AHCI_CMDFIS_SECTN] = (pAhciPortTaskState->cmdFis[AHCI_CMDFIS_SECTN] & ~7) |
2710 ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
2711 pAhciPort->uATAPISenseKey = uATAPISenseKey;
2712 pAhciPort->uATAPIASC = uATAPIASC;
2713}
2714
2715static void ataSCSIPadStr(uint8_t *pbDst, const char *pbSrc, uint32_t cbSize)
2716{
2717 for (uint32_t i = 0; i < cbSize; i++)
2718 {
2719 if (*pbSrc)
2720 pbDst[i] = *pbSrc++;
2721 else
2722 pbDst[i] = ' ';
2723 }
2724}
2725
2726static void ataPadString(uint8_t *pbDst, const char *pbSrc, uint32_t cbSize)
2727{
2728 for (uint32_t i = 0; i < cbSize; i++)
2729 {
2730 if (*pbSrc)
2731 pbDst[i ^ 1] = *pbSrc++;
2732 else
2733 pbDst[i ^ 1] = ' ';
2734 }
2735}
2736
2737static int ahciIdentifySS(PAHCIPort pAhciPort, void *pvBuf)
2738{
2739 uint16_t *p;
2740 int rc = VINF_SUCCESS;
2741
2742 p = (uint16_t *)pvBuf;
2743 memset(p, 0, 512);
2744 p[0] = RT_H2LE_U16(0x0040);
2745 p[1] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383));
2746 p[3] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cHeads);
2747 /* Block size; obsolete, but required for the BIOS. */
2748 p[5] = RT_H2LE_U16(512);
2749 p[6] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cSectors);
2750 ataPadString((uint8_t *)(p + 10), pAhciPort->szSerialNumber, AHCI_SERIAL_NUMBER_LENGTH); /* serial number */
2751 p[20] = RT_H2LE_U16(3); /* XXX: retired, cache type */
2752 p[21] = RT_H2LE_U16(512); /* XXX: retired, cache size in sectors */
2753 p[22] = RT_H2LE_U16(0); /* ECC bytes per sector */
2754 ataPadString((uint8_t *)(p + 23), pAhciPort->szFirmwareRevision, AHCI_FIRMWARE_REVISION_LENGTH); /* firmware version */
2755 ataPadString((uint8_t *)(p + 27), pAhciPort->szModelNumber, AHCI_MODEL_NUMBER_LENGTH); /* model */
2756#if ATA_MAX_MULT_SECTORS > 1
2757 p[47] = RT_H2LE_U16(0x8000 | ATA_MAX_MULT_SECTORS);
2758#endif
2759 p[48] = RT_H2LE_U16(1); /* dword I/O, used by the BIOS */
2760 p[49] = RT_H2LE_U16(1 << 11 | 1 << 9 | 1 << 8); /* DMA and LBA supported */
2761 p[50] = RT_H2LE_U16(1 << 14); /* No drive specific standby timer minimum */
2762 p[51] = RT_H2LE_U16(240); /* PIO transfer cycle */
2763 p[52] = RT_H2LE_U16(240); /* DMA transfer cycle */
2764 p[53] = RT_H2LE_U16(1 | 1 << 1 | 1 << 2); /* words 54-58,64-70,88 valid */
2765 p[54] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383));
2766 p[55] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cHeads);
2767 p[56] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cSectors);
2768 p[57] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383) * pAhciPort->PCHSGeometry.cHeads * pAhciPort->PCHSGeometry.cSectors);
2769 p[58] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383) * pAhciPort->PCHSGeometry.cHeads * pAhciPort->PCHSGeometry.cSectors >> 16);
2770 if (pAhciPort->cMultSectors)
2771 p[59] = RT_H2LE_U16(0x100 | pAhciPort->cMultSectors);
2772 if (pAhciPort->cTotalSectors <= (1 << 28) - 1)
2773 {
2774 p[60] = RT_H2LE_U16(pAhciPort->cTotalSectors);
2775 p[61] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 16);
2776 }
2777 else
2778 {
2779 /* Report maximum number of sectors possible with LBA28 */
2780 p[60] = RT_H2LE_U16(((1 << 28) - 1) & 0xffff);
2781 p[61] = RT_H2LE_U16(((1 << 28) - 1) >> 16);
2782 }
2783 p[63] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_MDMA, ATA_MDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* MDMA modes supported / mode enabled */
2784 p[64] = RT_H2LE_U16(ATA_PIO_MODE_MAX > 2 ? (1 << (ATA_PIO_MODE_MAX - 2)) - 1 : 0); /* PIO modes beyond PIO2 supported */
2785 p[65] = RT_H2LE_U16(120); /* minimum DMA multiword tx cycle time */
2786 p[66] = RT_H2LE_U16(120); /* recommended DMA multiword tx cycle time */
2787 p[67] = RT_H2LE_U16(120); /* minimum PIO cycle time without flow control */
2788 p[68] = RT_H2LE_U16(120); /* minimum PIO cycle time with IORDY flow control */
2789 p[80] = RT_H2LE_U16(0x7e); /* support everything up to ATA/ATAPI-6 */
2790 p[81] = RT_H2LE_U16(0x22); /* conforms to ATA/ATAPI-6 */
2791 p[82] = RT_H2LE_U16(1 << 3 | 1 << 5 | 1 << 6); /* supports power management, write cache and look-ahead */
2792 p[83] = RT_H2LE_U16(1 << 14 | 1 << 10 | 1 << 12 | 1 << 13); /* supports LBA48, FLUSH CACHE and FLUSH CACHE EXT */
2793 p[84] = RT_H2LE_U16(1 << 14);
2794 p[85] = RT_H2LE_U16(1 << 3 | 1 << 5 | 1 << 6); /* enabled power management, write cache and look-ahead */
2795 p[86] = RT_H2LE_U16(1 << 10 | 1 << 12 | 1 << 13); /* enabled LBA48, FLUSH CACHE and FLUSH CACHE EXT */
2796 p[87] = RT_H2LE_U16(1 << 14);
2797 p[88] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_UDMA, ATA_UDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* UDMA modes supported / mode enabled */
2798 p[93] = RT_H2LE_U16(0x00);
2799 p[100] = RT_H2LE_U16(pAhciPort->cTotalSectors);
2800 p[101] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 16);
2801 p[102] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 32);
2802 p[103] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 48);
2803
2804 /* The following are SATA specific */
2805 p[75] = RT_H2LE_U16(31); /* We support 32 commands */
2806 p[76] = RT_H2LE_U16((1 << 8) | (1 << 2)); /* Native command queuing and Serial ATA Gen2 (3.0 Gbps) speed supported */
2807
2808 return VINF_SUCCESS;
2809}
2810
2811typedef int (*PAtapiFunc)(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2812
2813static int atapiGetConfigurationSS(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2814static int atapiIdentifySS(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2815static int atapiInquirySS(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2816static int atapiMechanismStatusSS(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2817static int atapiModeSenseErrorRecoverySS(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2818static int atapiModeSenseCDStatusSS(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2819static int atapiReadCapacitySS(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2820static int atapiReadDiscInformationSS(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2821static int atapiReadTOCNormalSS(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2822static int atapiReadTOCMultiSS(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2823static int atapiReadTOCRawSS(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2824static int atapiReadTrackInformationSS(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2825static int atapiRequestSenseSS(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2826//static int atapiPassthroughSS(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2827
2828/**
2829 * Source/sink function indexes for g_apfnAtapiFuncs.
2830 */
2831typedef enum ATAPIFN
2832{
2833 ATAFN_SS_NULL = 0,
2834 ATAFN_SS_ATAPI_GET_CONFIGURATION,
2835 ATAFN_SS_ATAPI_IDENTIFY,
2836 ATAFN_SS_ATAPI_INQUIRY,
2837 ATAFN_SS_ATAPI_MECHANISM_STATUS,
2838 ATAFN_SS_ATAPI_MODE_SENSE_ERROR_RECOVERY,
2839 ATAFN_SS_ATAPI_MODE_SENSE_CD_STATUS,
2840 ATAFN_SS_ATAPI_READ_CAPACITY,
2841 ATAFN_SS_ATAPI_READ_DISC_INFORMATION,
2842 ATAFN_SS_ATAPI_READ_TOC_NORMAL,
2843 ATAFN_SS_ATAPI_READ_TOC_MULTI,
2844 ATAFN_SS_ATAPI_READ_TOC_RAW,
2845 ATAFN_SS_ATAPI_READ_TRACK_INFORMATION,
2846 ATAFN_SS_ATAPI_REQUEST_SENSE,
2847 //ATAFN_SS_ATAPI_PASSTHROUGH,
2848 ATAFN_SS_MAX
2849} ATAPIFN;
2850
2851/**
2852 * Array of source/sink functions, the index is ATAFNSS.
2853 * Make sure ATAFNSS and this array match!
2854 */
2855static const PAtapiFunc g_apfnAtapiFuncs[ATAFN_SS_MAX] =
2856{
2857 NULL,
2858 atapiGetConfigurationSS,
2859 atapiIdentifySS,
2860 atapiInquirySS,
2861 atapiMechanismStatusSS,
2862 atapiModeSenseErrorRecoverySS,
2863 atapiModeSenseCDStatusSS,
2864 atapiReadCapacitySS,
2865 atapiReadDiscInformationSS,
2866 atapiReadTOCNormalSS,
2867 atapiReadTOCMultiSS,
2868 atapiReadTOCRawSS,
2869 atapiReadTrackInformationSS,
2870 atapiRequestSenseSS
2871 //atapiPassthroughSS
2872};
2873
2874static int atapiIdentifySS(PAHCIPORTTASKSTATE pAhciPortTaskState, PAHCIPort pAhciPort, int *pcbData)
2875{
2876 uint16_t p[256];
2877
2878 memset(p, 0, 512);
2879 /* Removable CDROM, 50us response, 12 byte packets */
2880 p[0] = RT_H2LE_U16(2 << 14 | 5 << 8 | 1 << 7 | 2 << 5 | 0 << 0);
2881 ataPadString((uint8_t *)(p + 10), pAhciPort->szSerialNumber, AHCI_SERIAL_NUMBER_LENGTH); /* serial number */
2882 p[20] = RT_H2LE_U16(3); /* XXX: retired, cache type */
2883 p[21] = RT_H2LE_U16(512); /* XXX: retired, cache size in sectors */
2884 ataPadString((uint8_t *)(p + 23), pAhciPort->szFirmwareRevision, AHCI_FIRMWARE_REVISION_LENGTH); /* firmware version */
2885 ataPadString((uint8_t *)(p + 27), pAhciPort->szModelNumber, AHCI_MODEL_NUMBER_LENGTH); /* model */
2886 p[49] = RT_H2LE_U16(1 << 11 | 1 << 9 | 1 << 8); /* DMA and LBA supported */
2887 p[50] = RT_H2LE_U16(1 << 14); /* No drive specific standby timer minimum */
2888 p[51] = RT_H2LE_U16(240); /* PIO transfer cycle */
2889 p[52] = RT_H2LE_U16(240); /* DMA transfer cycle */
2890 p[53] = RT_H2LE_U16(1 << 1 | 1 << 2); /* words 64-70,88 are valid */
2891 p[63] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_MDMA, ATA_MDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* MDMA modes supported / mode enabled */
2892 p[64] = RT_H2LE_U16(ATA_PIO_MODE_MAX > 2 ? (1 << (ATA_PIO_MODE_MAX - 2)) - 1 : 0); /* PIO modes beyond PIO2 supported */
2893 p[65] = RT_H2LE_U16(120); /* minimum DMA multiword tx cycle time */
2894 p[66] = RT_H2LE_U16(120); /* recommended DMA multiword tx cycle time */
2895 p[67] = RT_H2LE_U16(120); /* minimum PIO cycle time without flow control */
2896 p[68] = RT_H2LE_U16(120); /* minimum PIO cycle time with IORDY flow control */
2897 p[73] = RT_H2LE_U16(0x003e); /* ATAPI CDROM major */
2898 p[74] = RT_H2LE_U16(9); /* ATAPI CDROM minor */
2899 p[75] = RT_H2LE_U16(1); /* queue depth 1 */
2900 p[80] = RT_H2LE_U16(0x7e); /* support everything up to ATA/ATAPI-6 */
2901 p[81] = RT_H2LE_U16(0x22); /* conforms to ATA/ATAPI-6 */
2902 p[82] = RT_H2LE_U16(1 << 4 | 1 << 9); /* supports packet command set and DEVICE RESET */
2903 p[83] = RT_H2LE_U16(1 << 14);
2904 p[84] = RT_H2LE_U16(1 << 14);
2905 p[85] = RT_H2LE_U16(1 << 4 | 1 << 9); /* enabled packet command set and DEVICE RESET */
2906 p[86] = RT_H2LE_U16(0);
2907 p[87] = RT_H2LE_U16(1 << 14);
2908 p[88] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_UDMA, ATA_UDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* UDMA modes supported / mode enabled */
2909 p[93] = RT_H2LE_U16((1 | 1 << 1) << ((pAhciPort->iLUN & 1) == 0 ? 0 : 8) | 1 << 13 | 1 << 14);
2910
2911 /* The following are SATA specific */
2912 p[75] = RT_H2LE_U16(31); /* We support 32 commands */
2913 p[76] = RT_H2LE_U16((1 << 8) | (1 << 2)); /* Native command queuing and Serial ATA Gen2 (3.0 Gbps) speed supported */
2914
2915 /* Copy the buffer in to the scatter gather list. */
2916 *pcbData = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, (void *)&p[0], sizeof(p));
2917
2918 atapiCmdOK(pAhciPort, pAhciPortTaskState);
2919 return VINF_SUCCESS;
2920}
2921
2922static int atapiReadCapacitySS(PAHCIPORTTASKSTATE pAhciPortTaskState, PAHCIPort pAhciPort, int *pcbData)
2923{
2924 uint8_t aBuf[8];
2925
2926 ataH2BE_U32(aBuf, pAhciPort->cTotalSectors - 1);
2927 ataH2BE_U32(aBuf + 4, 2048);
2928
2929 /* Copy the buffer in to the scatter gather list. */
2930 *pcbData = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, (void *)&aBuf[0], sizeof(aBuf));
2931
2932 atapiCmdOK(pAhciPort, pAhciPortTaskState);
2933 return VINF_SUCCESS;
2934}
2935
2936
2937static int atapiReadDiscInformationSS(PAHCIPORTTASKSTATE pAhciPortTaskState, PAHCIPort pAhciPort, int *pcbData)
2938{
2939 uint8_t aBuf[34];
2940
2941 memset(aBuf, '\0', 34);
2942 ataH2BE_U16(aBuf, 32);
2943 aBuf[2] = (0 << 4) | (3 << 2) | (2 << 0); /* not erasable, complete session, complete disc */
2944 aBuf[3] = 1; /* number of first track */
2945 aBuf[4] = 1; /* number of sessions (LSB) */
2946 aBuf[5] = 1; /* first track number in last session (LSB) */
2947 aBuf[6] = 1; /* last track number in last session (LSB) */
2948 aBuf[7] = (0 << 7) | (0 << 6) | (1 << 5) | (0 << 2) | (0 << 0); /* disc id not valid, disc bar code not valid, unrestricted use, not dirty, not RW medium */
2949 aBuf[8] = 0; /* disc type = CD-ROM */
2950 aBuf[9] = 0; /* number of sessions (MSB) */
2951 aBuf[10] = 0; /* number of sessions (MSB) */
2952 aBuf[11] = 0; /* number of sessions (MSB) */
2953 ataH2BE_U32(aBuf + 16, 0x00ffffff); /* last session lead-in start time is not available */
2954 ataH2BE_U32(aBuf + 20, 0x00ffffff); /* last possible start time for lead-out is not available */
2955
2956 /* Copy the buffer in to the scatter gather list. */
2957 *pcbData = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, (void *)&aBuf[0], sizeof(aBuf));
2958
2959 atapiCmdOK(pAhciPort, pAhciPortTaskState);
2960 return VINF_SUCCESS;
2961}
2962
2963
2964static int atapiReadTrackInformationSS(PAHCIPORTTASKSTATE pAhciPortTaskState, PAHCIPort pAhciPort, int *pcbData)
2965{
2966 uint8_t aBuf[36];
2967
2968 /* Accept address/number type of 1 only, and only track 1 exists. */
2969 if ((pAhciPortTaskState->aATAPICmd[1] & 0x03) != 1 || ataBE2H_U32(&pAhciPortTaskState->aATAPICmd[2]) != 1)
2970 {
2971 atapiCmdError(pAhciPort, pAhciPortTaskState, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
2972 return VINF_SUCCESS;
2973 }
2974 memset(aBuf, '\0', 36);
2975 ataH2BE_U16(aBuf, 34);
2976 aBuf[2] = 1; /* track number (LSB) */
2977 aBuf[3] = 1; /* session number (LSB) */
2978 aBuf[5] = (0 << 5) | (0 << 4) | (4 << 0); /* not damaged, primary copy, data track */
2979 aBuf[6] = (0 << 7) | (0 << 6) | (0 << 5) | (0 << 6) | (1 << 0); /* not reserved track, not blank, not packet writing, not fixed packet, data mode 1 */
2980 aBuf[7] = (0 << 1) | (0 << 0); /* last recorded address not valid, next recordable address not valid */
2981 ataH2BE_U32(aBuf + 8, 0); /* track start address is 0 */
2982 ataH2BE_U32(aBuf + 24, pAhciPort->cTotalSectors); /* track size */
2983 aBuf[32] = 0; /* track number (MSB) */
2984 aBuf[33] = 0; /* session number (MSB) */
2985
2986 /* Copy the buffer in to the scatter gather list. */
2987 *pcbData = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, (void *)&aBuf[0], sizeof(aBuf));
2988
2989 atapiCmdOK(pAhciPort, pAhciPortTaskState);
2990 return VINF_SUCCESS;
2991}
2992
2993
2994static int atapiGetConfigurationSS(PAHCIPORTTASKSTATE pAhciPortTaskState, PAHCIPort pAhciPort, int *pcbData)
2995{
2996 uint8_t aBuf[32];
2997
2998 /* Accept valid request types only, and only starting feature 0. */
2999 if ((pAhciPortTaskState->aATAPICmd[1] & 0x03) == 3 || ataBE2H_U16(&pAhciPortTaskState->aATAPICmd[2]) != 0)
3000 {
3001 atapiCmdError(pAhciPort, pAhciPortTaskState, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
3002 return VINF_SUCCESS;
3003 }
3004 memset(aBuf, '\0', 32);
3005 ataH2BE_U32(aBuf, 16);
3006 /** @todo implement switching between CD-ROM and DVD-ROM profile (the only
3007 * way to differentiate them right now is based on the image size). Also
3008 * implement signalling "no current profile" if no medium is loaded. */
3009 ataH2BE_U16(aBuf + 6, 0x08); /* current profile: read-only CD */
3010
3011 ataH2BE_U16(aBuf + 8, 0); /* feature 0: list of profiles supported */
3012 aBuf[10] = (0 << 2) | (1 << 1) | (1 || 0); /* version 0, persistent, current */
3013 aBuf[11] = 8; /* additional bytes for profiles */
3014 /* The MMC-3 spec says that DVD-ROM read capability should be reported
3015 * before CD-ROM read capability. */
3016 ataH2BE_U16(aBuf + 12, 0x10); /* profile: read-only DVD */
3017 aBuf[14] = (0 << 0); /* NOT current profile */
3018 ataH2BE_U16(aBuf + 16, 0x08); /* profile: read only CD */
3019 aBuf[18] = (1 << 0); /* current profile */
3020
3021 /* Copy the buffer in to the scatter gather list. */
3022 *pcbData = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, (void *)&aBuf[0], sizeof(aBuf));
3023
3024 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3025 return VINF_SUCCESS;
3026}
3027
3028
3029static int atapiInquirySS(PAHCIPORTTASKSTATE pAhciPortTaskState, PAHCIPort pAhciPort, int *pcbData)
3030{
3031 uint8_t aBuf[36];
3032
3033 aBuf[0] = 0x05; /* CD-ROM */
3034 aBuf[1] = 0x80; /* removable */
3035 aBuf[2] = 0x00; /* ISO */
3036 aBuf[3] = 0x21; /* ATAPI-2 (XXX: put ATAPI-4 ?) */
3037 aBuf[4] = 31; /* additional length */
3038 aBuf[5] = 0; /* reserved */
3039 aBuf[6] = 0; /* reserved */
3040 aBuf[7] = 0; /* reserved */
3041 ataSCSIPadStr(aBuf + 8, pAhciPort->szInquiryVendorId, 8);
3042 ataSCSIPadStr(aBuf + 16, pAhciPort->szInquiryProductId, 16);
3043 ataSCSIPadStr(aBuf + 32, pAhciPort->szInquiryRevision, 4);
3044
3045 /* Copy the buffer in to the scatter gather list. */
3046 *pcbData = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, (void *)&aBuf[0], sizeof(aBuf));
3047
3048 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3049 return VINF_SUCCESS;
3050}
3051
3052
3053static int atapiModeSenseErrorRecoverySS(PAHCIPORTTASKSTATE pAhciPortTaskState, PAHCIPort pAhciPort, int *pcbData)
3054{
3055 uint8_t aBuf[16];
3056
3057 ataH2BE_U16(&aBuf[0], 16 + 6);
3058 aBuf[2] = 0x70;
3059 aBuf[3] = 0;
3060 aBuf[4] = 0;
3061 aBuf[5] = 0;
3062 aBuf[6] = 0;
3063 aBuf[7] = 0;
3064
3065 aBuf[8] = 0x01;
3066 aBuf[9] = 0x06;
3067 aBuf[10] = 0x00;
3068 aBuf[11] = 0x05;
3069 aBuf[12] = 0x00;
3070 aBuf[13] = 0x00;
3071 aBuf[14] = 0x00;
3072 aBuf[15] = 0x00;
3073
3074 /* Copy the buffer in to the scatter gather list. */
3075 *pcbData = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, (void *)&aBuf[0], sizeof(aBuf));
3076
3077 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3078 return VINF_SUCCESS;
3079}
3080
3081
3082static int atapiModeSenseCDStatusSS(PAHCIPORTTASKSTATE pAhciPortTaskState, PAHCIPort pAhciPort, int *pcbData)
3083{
3084 uint8_t aBuf[40];
3085
3086 ataH2BE_U16(&aBuf[0], 38);
3087 aBuf[2] = 0x70;
3088 aBuf[3] = 0;
3089 aBuf[4] = 0;
3090 aBuf[5] = 0;
3091 aBuf[6] = 0;
3092 aBuf[7] = 0;
3093
3094 aBuf[8] = 0x2a;
3095 aBuf[9] = 30; /* page length */
3096 aBuf[10] = 0x08; /* DVD-ROM read support */
3097 aBuf[11] = 0x00; /* no write support */
3098 /* The following claims we support audio play. This is obviously false,
3099 * but the Linux generic CDROM support makes many features depend on this
3100 * capability. If it's not set, this causes many things to be disabled. */
3101 aBuf[12] = 0x71; /* multisession support, mode 2 form 1/2 support, audio play */
3102 aBuf[13] = 0x00; /* no subchannel reads supported */
3103 aBuf[14] = (1 << 0) | (1 << 3) | (1 << 5); /* lock supported, eject supported, tray type loading mechanism */
3104 if (pAhciPort->pDrvMount->pfnIsLocked(pAhciPort->pDrvMount))
3105 aBuf[14] |= 1 << 1; /* report lock state */
3106 aBuf[15] = 0; /* no subchannel reads supported, no separate audio volume control, no changer etc. */
3107 ataH2BE_U16(&aBuf[16], 5632); /* (obsolete) claim 32x speed support */
3108 ataH2BE_U16(&aBuf[18], 2); /* number of audio volume levels */
3109 ataH2BE_U16(&aBuf[20], 128); /* buffer size supported in Kbyte - We don't have a buffer because we write directly into guest memory.
3110 Just write the value DevATA is using. */
3111 ataH2BE_U16(&aBuf[22], 5632); /* (obsolete) current read speed 32x */
3112 aBuf[24] = 0; /* reserved */
3113 aBuf[25] = 0; /* reserved for digital audio (see idx 15) */
3114 ataH2BE_U16(&aBuf[26], 0); /* (obsolete) maximum write speed */
3115 ataH2BE_U16(&aBuf[28], 0); /* (obsolete) current write speed */
3116 ataH2BE_U16(&aBuf[30], 0); /* copy management revision supported 0=no CSS */
3117 aBuf[32] = 0; /* reserved */
3118 aBuf[33] = 0; /* reserved */
3119 aBuf[34] = 0; /* reserved */
3120 aBuf[35] = 1; /* rotation control CAV */
3121 ataH2BE_U16(&aBuf[36], 0); /* current write speed */
3122 ataH2BE_U16(&aBuf[38], 0); /* number of write speed performance descriptors */
3123
3124 /* Copy the buffer in to the scatter gather list. */
3125 *pcbData = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, (void *)&aBuf[0], sizeof(aBuf));
3126
3127 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3128 return VINF_SUCCESS;
3129}
3130
3131
3132static int atapiRequestSenseSS(PAHCIPORTTASKSTATE pAhciPortTaskState, PAHCIPort pAhciPort, int *pcbData)
3133{
3134 uint8_t aBuf[18];
3135
3136 memset(&aBuf[0], 0, 18);
3137 aBuf[0] = 0x70 | (1 << 7);
3138 aBuf[2] = pAhciPort->uATAPISenseKey;
3139 aBuf[7] = 10;
3140 aBuf[12] = pAhciPort->uATAPIASC;
3141
3142 /* Copy the buffer in to the scatter gather list. */
3143 *pcbData = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, (void *)&aBuf[0], sizeof(aBuf));
3144
3145 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3146 return VINF_SUCCESS;
3147}
3148
3149
3150static int atapiMechanismStatusSS(PAHCIPORTTASKSTATE pAhciPortTaskState, PAHCIPort pAhciPort, int *pcbData)
3151{
3152 uint8_t aBuf[8];
3153
3154 ataH2BE_U16(&aBuf[0], 0);
3155 /* no current LBA */
3156 aBuf[2] = 0;
3157 aBuf[3] = 0;
3158 aBuf[4] = 0;
3159 aBuf[5] = 1;
3160 ataH2BE_U16(aBuf + 6, 0);
3161
3162 /* Copy the buffer in to the scatter gather list. */
3163 *pcbData = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, (void *)&aBuf[0], sizeof(aBuf));
3164
3165 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3166 return VINF_SUCCESS;
3167}
3168
3169
3170static int atapiReadTOCNormalSS(PAHCIPORTTASKSTATE pAhciPortTaskState, PAHCIPort pAhciPort, int *pcbData)
3171{
3172 uint8_t aBuf[20], *q, iStartTrack;
3173 bool fMSF;
3174 uint32_t cbSize;
3175
3176 fMSF = (pAhciPortTaskState->aATAPICmd[1] >> 1) & 1;
3177 iStartTrack = pAhciPortTaskState->aATAPICmd[6];
3178 if (iStartTrack > 1 && iStartTrack != 0xaa)
3179 {
3180 atapiCmdError(pAhciPort, pAhciPortTaskState, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
3181 return VINF_SUCCESS;
3182 }
3183 q = aBuf + 2;
3184 *q++ = 1; /* first session */
3185 *q++ = 1; /* last session */
3186 if (iStartTrack <= 1)
3187 {
3188 *q++ = 0; /* reserved */
3189 *q++ = 0x14; /* ADR, control */
3190 *q++ = 1; /* track number */
3191 *q++ = 0; /* reserved */
3192 if (fMSF)
3193 {
3194 *q++ = 0; /* reserved */
3195 ataLBA2MSF(q, 0);
3196 q += 3;
3197 }
3198 else
3199 {
3200 /* sector 0 */
3201 ataH2BE_U32(q, 0);
3202 q += 4;
3203 }
3204 }
3205 /* lead out track */
3206 *q++ = 0; /* reserved */
3207 *q++ = 0x14; /* ADR, control */
3208 *q++ = 0xaa; /* track number */
3209 *q++ = 0; /* reserved */
3210 if (fMSF)
3211 {
3212 *q++ = 0; /* reserved */
3213 ataLBA2MSF(q, pAhciPort->cTotalSectors);
3214 q += 3;
3215 }
3216 else
3217 {
3218 ataH2BE_U32(q, pAhciPort->cTotalSectors);
3219 q += 4;
3220 }
3221 cbSize = q - aBuf;
3222 ataH2BE_U16(aBuf, cbSize - 2);
3223
3224 /* Copy the buffer in to the scatter gather list. */
3225 *pcbData = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, (void *)&aBuf[0], cbSize);
3226
3227 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3228 return VINF_SUCCESS;
3229}
3230
3231
3232static int atapiReadTOCMultiSS(PAHCIPORTTASKSTATE pAhciPortTaskState, PAHCIPort pAhciPort, int *pcbData)
3233{
3234 uint8_t aBuf[12];
3235 bool fMSF;
3236
3237 fMSF = (pAhciPortTaskState->aATAPICmd[1] >> 1) & 1;
3238 /* multi session: only a single session defined */
3239/** @todo double-check this stuff against what a real drive says for a CD-ROM (not a CD-R) with only a single data session. Maybe solve the problem with "cdrdao read-toc" not being able to figure out whether numbers are in BCD or hex. */
3240 memset(aBuf, 0, 12);
3241 aBuf[1] = 0x0a;
3242 aBuf[2] = 0x01;
3243 aBuf[3] = 0x01;
3244 aBuf[5] = 0x14; /* ADR, control */
3245 aBuf[6] = 1; /* first track in last complete session */
3246 if (fMSF)
3247 {
3248 aBuf[8] = 0; /* reserved */
3249 ataLBA2MSF(&aBuf[9], 0);
3250 }
3251 else
3252 {
3253 /* sector 0 */
3254 ataH2BE_U32(aBuf + 8, 0);
3255 }
3256
3257 /* Copy the buffer in to the scatter gather list. */
3258 *pcbData = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, (void *)&aBuf[0], sizeof(aBuf));
3259
3260 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3261 return VINF_SUCCESS;
3262}
3263
3264
3265static int atapiReadTOCRawSS(PAHCIPORTTASKSTATE pAhciPortTaskState, PAHCIPort pAhciPort, int *pcbData)
3266{
3267 uint8_t aBuf[50]; /* Counted a maximum of 45 bytes but better be on the safe side. */
3268 uint8_t *q, iStartTrack;
3269 bool fMSF;
3270 uint32_t cbSize;
3271
3272 fMSF = (pAhciPortTaskState->aATAPICmd[1] >> 1) & 1;
3273 iStartTrack = pAhciPortTaskState->aATAPICmd[6];
3274
3275 q = aBuf + 2;
3276 *q++ = 1; /* first session */
3277 *q++ = 1; /* last session */
3278
3279 *q++ = 1; /* session number */
3280 *q++ = 0x14; /* data track */
3281 *q++ = 0; /* track number */
3282 *q++ = 0xa0; /* first track in program area */
3283 *q++ = 0; /* min */
3284 *q++ = 0; /* sec */
3285 *q++ = 0; /* frame */
3286 *q++ = 0;
3287 *q++ = 1; /* first track */
3288 *q++ = 0x00; /* disk type CD-DA or CD data */
3289 *q++ = 0;
3290
3291 *q++ = 1; /* session number */
3292 *q++ = 0x14; /* data track */
3293 *q++ = 0; /* track number */
3294 *q++ = 0xa1; /* last track in program area */
3295 *q++ = 0; /* min */
3296 *q++ = 0; /* sec */
3297 *q++ = 0; /* frame */
3298 *q++ = 0;
3299 *q++ = 1; /* last track */
3300 *q++ = 0;
3301 *q++ = 0;
3302
3303 *q++ = 1; /* session number */
3304 *q++ = 0x14; /* data track */
3305 *q++ = 0; /* track number */
3306 *q++ = 0xa2; /* lead-out */
3307 *q++ = 0; /* min */
3308 *q++ = 0; /* sec */
3309 *q++ = 0; /* frame */
3310 if (fMSF)
3311 {
3312 *q++ = 0; /* reserved */
3313 ataLBA2MSF(q, pAhciPort->cTotalSectors);
3314 q += 3;
3315 }
3316 else
3317 {
3318 ataH2BE_U32(q, pAhciPort->cTotalSectors);
3319 q += 4;
3320 }
3321
3322 *q++ = 1; /* session number */
3323 *q++ = 0x14; /* ADR, control */
3324 *q++ = 0; /* track number */
3325 *q++ = 1; /* point */
3326 *q++ = 0; /* min */
3327 *q++ = 0; /* sec */
3328 *q++ = 0; /* frame */
3329 if (fMSF)
3330 {
3331 *q++ = 0; /* reserved */
3332 ataLBA2MSF(q, 0);
3333 q += 3;
3334 }
3335 else
3336 {
3337 /* sector 0 */
3338 ataH2BE_U32(q, 0);
3339 q += 4;
3340 }
3341
3342 cbSize = q - aBuf;
3343 ataH2BE_U16(aBuf, cbSize - 2);
3344
3345 /* Copy the buffer in to the scatter gather list. */
3346 *pcbData = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, (void *)&aBuf[0], cbSize);
3347
3348 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3349 return VINF_SUCCESS;
3350}
3351
3352static int atapiDoTransfer(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState, ATAPIFN iSourceSink)
3353{
3354 int cbTransfered;
3355 int rc, rcSourceSink;
3356
3357 /*
3358 * Create scatter gather list. We use a safe mapping here because it is
3359 * possible that the buffer is not a multiple of 512. The normal
3360 * creator would assert later here.
3361 */
3362 ahciScatterGatherListGetTotalBufferSize(pAhciPort, pAhciPortTaskState);
3363 rc = ahciScatterGatherListCreateSafe(pAhciPort, pAhciPortTaskState, false, 0);
3364 AssertRC(rc);
3365
3366 rcSourceSink = g_apfnAtapiFuncs[iSourceSink](pAhciPortTaskState, pAhciPort, &cbTransfered);
3367
3368 pAhciPortTaskState->cmdHdr.u32PRDBC = cbTransfered;
3369
3370 rc = ahciScatterGatherListDestroy(pAhciPort, pAhciPortTaskState);
3371 AssertRC(rc);
3372
3373 /* Write updated command header into memory of the guest. */
3374 PDMDevHlpPhysWrite(pAhciPort->CTX_SUFF(pDevIns), pAhciPortTaskState->GCPhysCmdHdrAddr, &pAhciPortTaskState->cmdHdr, sizeof(CmdHdr));
3375
3376 return rcSourceSink;
3377}
3378
3379static int atapiReadSectors2352PostProcess(PAHCIPORTTASKSTATE pAhciPortTaskState)
3380{
3381 uint32_t cSectors = pAhciPortTaskState->cbTransfer / 2048;
3382 uint32_t iATAPILBA = pAhciPortTaskState->uOffset / 2048;
3383 uint8_t *pbBufDst = (uint8_t *)pAhciPortTaskState->pvBufferUnaligned;
3384 uint8_t *pbBufSrc = (uint8_t *)pAhciPortTaskState->pSGListHead[0].pvSeg;
3385
3386 for (uint32_t i = iATAPILBA; i < iATAPILBA + cSectors; i++)
3387 {
3388 /* sync bytes */
3389 *pbBufDst++ = 0x00;
3390 memset(pbBufDst, 0xff, 11);
3391 pbBufDst += 11;
3392 /* MSF */
3393 ataLBA2MSF(pbBufDst, i);
3394 pbBufDst += 3;
3395 *pbBufDst++ = 0x01; /* mode 1 data */
3396 /* data */
3397 memcpy(pbBufDst, pbBufSrc, 2048);
3398 pbBufDst += 2048;
3399 pbBufSrc += 2048;
3400 /* ECC */
3401 memset(pbBufDst, 0, 288);
3402 pbBufDst += 288;
3403 }
3404
3405 return VINF_SUCCESS;
3406}
3407
3408static int atapiReadSectors(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState, uint32_t iATAPILBA, uint32_t cSectors, uint32_t cbSector)
3409{
3410 Log(("%s: %d sectors at LBA %d\n", __FUNCTION__, cSectors, iATAPILBA));
3411
3412 switch (cbSector)
3413 {
3414 case 2048:
3415 pAhciPortTaskState->uOffset = iATAPILBA * cbSector;
3416 pAhciPortTaskState->cbTransfer = cSectors * cbSector;
3417 break;
3418 case 2352:
3419 {
3420 pAhciPortTaskState->pfnPostProcess = atapiReadSectors2352PostProcess;
3421 pAhciPortTaskState->uOffset = iATAPILBA * 2048;
3422 pAhciPortTaskState->cbTransfer = cSectors * 2048;
3423 break;
3424 }
3425 default:
3426 AssertMsgFailed(("Unsupported sectors size\n"));
3427 break;
3428 }
3429
3430 return VINF_SUCCESS;
3431}
3432
3433static int atapiParseCmdVirtualATAPI(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState)
3434{
3435 int iTxDir = PDMBLOCKTXDIR_NONE;
3436 const uint8_t *pbPacket;
3437 uint32_t cbMax;
3438
3439 pbPacket = pAhciPortTaskState->aATAPICmd;
3440
3441 ahciLog(("%s: ATAPI CMD=%#04x \"%s\"\n", __FUNCTION__, pbPacket[0], SCSICmdText(pbPacket[0])));
3442
3443 switch (pbPacket[0])
3444 {
3445 case SCSI_TEST_UNIT_READY:
3446 if (pAhciPort->cNotifiedMediaChange > 0)
3447 {
3448 if (pAhciPort->cNotifiedMediaChange-- > 2)
3449 atapiCmdError(pAhciPort, pAhciPortTaskState, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3450 else
3451 atapiCmdError(pAhciPort, pAhciPortTaskState, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3452 }
3453 else if (pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
3454 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3455 else
3456 atapiCmdError(pAhciPort, pAhciPortTaskState, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3457 break;
3458 case SCSI_MODE_SENSE_10:
3459 {
3460 uint8_t uPageControl, uPageCode;
3461 cbMax = ataBE2H_U16(pbPacket + 7);
3462 uPageControl = pbPacket[2] >> 6;
3463 uPageCode = pbPacket[2] & 0x3f;
3464 switch (uPageControl)
3465 {
3466 case SCSI_PAGECONTROL_CURRENT:
3467 switch (uPageCode)
3468 {
3469 case SCSI_MODEPAGE_ERROR_RECOVERY:
3470 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_MODE_SENSE_ERROR_RECOVERY);
3471 break;
3472 case SCSI_MODEPAGE_CD_STATUS:
3473 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_MODE_SENSE_CD_STATUS);
3474 break;
3475 default:
3476 goto error_cmd;
3477 }
3478 break;
3479 case SCSI_PAGECONTROL_CHANGEABLE:
3480 goto error_cmd;
3481 case SCSI_PAGECONTROL_DEFAULT:
3482 goto error_cmd;
3483 default:
3484 case SCSI_PAGECONTROL_SAVED:
3485 atapiCmdError(pAhciPort, pAhciPortTaskState, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_SAVING_PARAMETERS_NOT_SUPPORTED);
3486 break;
3487 }
3488 }
3489 break;
3490 case SCSI_REQUEST_SENSE:
3491 cbMax = pbPacket[4];
3492 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_REQUEST_SENSE);
3493 break;
3494 case SCSI_PREVENT_ALLOW_MEDIUM_REMOVAL:
3495 if (pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
3496 {
3497 if (pbPacket[4] & 1)
3498 pAhciPort->pDrvMount->pfnLock(pAhciPort->pDrvMount);
3499 else
3500 pAhciPort->pDrvMount->pfnUnlock(pAhciPort->pDrvMount);
3501 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3502 }
3503 else
3504 atapiCmdError(pAhciPort, pAhciPortTaskState, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3505 break;
3506 case SCSI_READ_10:
3507 case SCSI_READ_12:
3508 {
3509 uint32_t cSectors, iATAPILBA;
3510
3511 if (pAhciPort->cNotifiedMediaChange > 0)
3512 {
3513 pAhciPort->cNotifiedMediaChange-- ;
3514 atapiCmdError(pAhciPort, pAhciPortTaskState, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3515 break;
3516 }
3517 else if (!pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
3518 {
3519 atapiCmdError(pAhciPort, pAhciPortTaskState, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3520 break;
3521 }
3522 if (pbPacket[0] == SCSI_READ_10)
3523 cSectors = ataBE2H_U16(pbPacket + 7);
3524 else
3525 cSectors = ataBE2H_U32(pbPacket + 6);
3526 iATAPILBA = ataBE2H_U32(pbPacket + 2);
3527 if (cSectors == 0)
3528 {
3529 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3530 break;
3531 }
3532 if ((uint64_t)iATAPILBA + cSectors > pAhciPort->cTotalSectors)
3533 {
3534 /* Rate limited logging, one log line per second. For
3535 * guests that insist on reading from places outside the
3536 * valid area this often generates too many release log
3537 * entries otherwise. */
3538 static uint64_t uLastLogTS = 0;
3539 if (RTTimeMilliTS() >= uLastLogTS + 1000)
3540 {
3541 LogRel(("AHCI ATAPI: LUN#%d: CD-ROM block number %Ld invalid (READ)\n", pAhciPort->iLUN, (uint64_t)iATAPILBA + cSectors));
3542 uLastLogTS = RTTimeMilliTS();
3543 }
3544 atapiCmdError(pAhciPort, pAhciPortTaskState, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_LOGICAL_BLOCK_OOR);
3545 break;
3546 }
3547 atapiReadSectors(pAhciPort, pAhciPortTaskState, iATAPILBA, cSectors, 2048);
3548 iTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3549 }
3550 break;
3551 case SCSI_READ_CD:
3552 {
3553 uint32_t cSectors, iATAPILBA;
3554
3555 if (pAhciPort->cNotifiedMediaChange > 0)
3556 {
3557 pAhciPort->cNotifiedMediaChange-- ;
3558 atapiCmdError(pAhciPort, pAhciPortTaskState, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3559 break;
3560 }
3561 else if (!pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
3562 {
3563 atapiCmdError(pAhciPort, pAhciPortTaskState, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3564 break;
3565 }
3566 cSectors = (pbPacket[6] << 16) | (pbPacket[7] << 8) | pbPacket[8];
3567 iATAPILBA = ataBE2H_U32(pbPacket + 2);
3568 if (cSectors == 0)
3569 {
3570 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3571 break;
3572 }
3573 if ((uint64_t)iATAPILBA + cSectors > pAhciPort->cTotalSectors)
3574 {
3575 /* Rate limited logging, one log line per second. For
3576 * guests that insist on reading from places outside the
3577 * valid area this often generates too many release log
3578 * entries otherwise. */
3579 static uint64_t uLastLogTS = 0;
3580 if (RTTimeMilliTS() >= uLastLogTS + 1000)
3581 {
3582 LogRel(("AHCI ATA: LUN#%d: CD-ROM block number %Ld invalid (READ CD)\n", pAhciPort->iLUN, (uint64_t)iATAPILBA + cSectors));
3583 uLastLogTS = RTTimeMilliTS();
3584 }
3585 atapiCmdError(pAhciPort, pAhciPortTaskState, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_LOGICAL_BLOCK_OOR);
3586 break;
3587 }
3588 switch (pbPacket[9] & 0xf8)
3589 {
3590 case 0x00:
3591 /* nothing */
3592 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3593 break;
3594 case 0x10:
3595 /* normal read */
3596 atapiReadSectors(pAhciPort, pAhciPortTaskState, iATAPILBA, cSectors, 2048);
3597 iTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3598 break;
3599 case 0xf8:
3600 /* read all data */
3601 atapiReadSectors(pAhciPort, pAhciPortTaskState, iATAPILBA, cSectors, 2352);
3602 iTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3603 break;
3604 default:
3605 LogRel(("AHCI ATAPI: LUN#%d: CD-ROM sector format not supported\n", pAhciPort->iLUN));
3606 atapiCmdError(pAhciPort, pAhciPortTaskState, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
3607 break;
3608 }
3609 }
3610 break;
3611 case SCSI_SEEK_10:
3612 {
3613 uint32_t iATAPILBA;
3614 if (pAhciPort->cNotifiedMediaChange > 0)
3615 {
3616 pAhciPort->cNotifiedMediaChange-- ;
3617 atapiCmdError(pAhciPort, pAhciPortTaskState, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3618 break;
3619 }
3620 else if (!pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
3621 {
3622 atapiCmdError(pAhciPort, pAhciPortTaskState, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3623 break;
3624 }
3625 iATAPILBA = ataBE2H_U32(pbPacket + 2);
3626 if (iATAPILBA > pAhciPort->cTotalSectors)
3627 {
3628 /* Rate limited logging, one log line per second. For
3629 * guests that insist on seeking to places outside the
3630 * valid area this often generates too many release log
3631 * entries otherwise. */
3632 static uint64_t uLastLogTS = 0;
3633 if (RTTimeMilliTS() >= uLastLogTS + 1000)
3634 {
3635 LogRel(("AHCI ATAPI: LUN#%d: CD-ROM block number %Ld invalid (SEEK)\n", pAhciPort->iLUN, (uint64_t)iATAPILBA));
3636 uLastLogTS = RTTimeMilliTS();
3637 }
3638 atapiCmdError(pAhciPort, pAhciPortTaskState, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_LOGICAL_BLOCK_OOR);
3639 break;
3640 }
3641 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3642 pAhciPortTaskState->uATARegStatus |= ATA_STAT_SEEK; /* Linux expects this. */
3643 }
3644 break;
3645 case SCSI_START_STOP_UNIT:
3646 {
3647 int rc = VINF_SUCCESS;
3648 switch (pbPacket[4] & 3)
3649 {
3650 case 0: /* 00 - Stop motor */
3651 case 1: /* 01 - Start motor */
3652 break;
3653 case 2: /* 10 - Eject media */
3654 /* This must be done from EMT. */
3655 {
3656 PAHCI pAhci = pAhciPort->CTX_SUFF(pAhci);
3657 PPDMDEVINS pDevIns = pAhci->CTX_SUFF(pDevIns);
3658
3659 rc = VMR3ReqCallWait(PDMDevHlpGetVM(pDevIns), VMCPUID_ANY,
3660 (PFNRT)pAhciPort->pDrvMount->pfnUnmount, 2, pAhciPort->pDrvMount, false);
3661 Assert(RT_SUCCESS(rc) || (rc == VERR_PDM_MEDIA_LOCKED));
3662 }
3663 break;
3664 case 3: /* 11 - Load media */
3665 /** @todo rc = s->pDrvMount->pfnLoadMedia(s->pDrvMount) */
3666 break;
3667 }
3668 if (RT_SUCCESS(rc))
3669 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3670 else
3671 atapiCmdError(pAhciPort, pAhciPortTaskState, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIA_LOAD_OR_EJECT_FAILED);
3672 }
3673 break;
3674 case SCSI_MECHANISM_STATUS:
3675 {
3676 cbMax = ataBE2H_U16(pbPacket + 8);
3677 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_MECHANISM_STATUS);
3678 }
3679 break;
3680 case SCSI_READ_TOC_PMA_ATIP:
3681 {
3682 uint8_t format;
3683
3684 if (pAhciPort->cNotifiedMediaChange > 0)
3685 {
3686 pAhciPort->cNotifiedMediaChange-- ;
3687 atapiCmdError(pAhciPort, pAhciPortTaskState, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3688 break;
3689 }
3690 else if (!pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
3691 {
3692 atapiCmdError(pAhciPort, pAhciPortTaskState, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3693 break;
3694 }
3695 cbMax = ataBE2H_U16(pbPacket + 7);
3696 /* SCSI MMC-3 spec says format is at offset 2 (lower 4 bits),
3697 * but Linux kernel uses offset 9 (topmost 2 bits). Hope that
3698 * the other field is clear... */
3699 format = (pbPacket[2] & 0xf) | (pbPacket[9] >> 6);
3700 switch (format)
3701 {
3702 case 0:
3703 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_READ_TOC_NORMAL);
3704 break;
3705 case 1:
3706 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_READ_TOC_MULTI);
3707 break;
3708 case 2:
3709 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_READ_TOC_RAW);
3710 break;
3711 default:
3712 error_cmd:
3713 atapiCmdError(pAhciPort, pAhciPortTaskState, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
3714 break;
3715 }
3716 }
3717 break;
3718 case SCSI_READ_CAPACITY:
3719 if (pAhciPort->cNotifiedMediaChange > 0)
3720 {
3721 pAhciPort->cNotifiedMediaChange-- ;
3722 atapiCmdError(pAhciPort, pAhciPortTaskState, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3723 break;
3724 }
3725 else if (!pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
3726 {
3727 atapiCmdError(pAhciPort, pAhciPortTaskState, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3728 break;
3729 }
3730 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_READ_CAPACITY);
3731 break;
3732 case SCSI_READ_DISC_INFORMATION:
3733 if (pAhciPort->cNotifiedMediaChange > 0)
3734 {
3735 pAhciPort->cNotifiedMediaChange-- ;
3736 atapiCmdError(pAhciPort, pAhciPortTaskState, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3737 break;
3738 }
3739 else if (!pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
3740 {
3741 atapiCmdError(pAhciPort, pAhciPortTaskState, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3742 break;
3743 }
3744 cbMax = ataBE2H_U16(pbPacket + 7);
3745 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_READ_DISC_INFORMATION);
3746 break;
3747 case SCSI_READ_TRACK_INFORMATION:
3748 if (pAhciPort->cNotifiedMediaChange > 0)
3749 {
3750 pAhciPort->cNotifiedMediaChange-- ;
3751 atapiCmdError(pAhciPort, pAhciPortTaskState, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3752 break;
3753 }
3754 else if (!pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
3755 {
3756 atapiCmdError(pAhciPort, pAhciPortTaskState, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3757 break;
3758 }
3759 cbMax = ataBE2H_U16(pbPacket + 7);
3760 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_READ_TRACK_INFORMATION);
3761 break;
3762 case SCSI_GET_CONFIGURATION:
3763 /* No media change stuff here, it can confuse Linux guests. */
3764 cbMax = ataBE2H_U16(pbPacket + 7);
3765 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_GET_CONFIGURATION);
3766 break;
3767 case SCSI_INQUIRY:
3768 cbMax = pbPacket[4];
3769 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_INQUIRY);
3770 break;
3771 default:
3772 atapiCmdError(pAhciPort, pAhciPortTaskState, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE);
3773 break;
3774 }
3775
3776 return iTxDir;
3777}
3778
3779/**
3780 * Reset all values after a reset of the attached storage device.
3781 *
3782 * @returns nothing
3783 * @param pAhciPort The port the device is attached to.
3784 * @param pAhciPortTaskState The state to get the tag number from.
3785 */
3786static void ahciFinishStorageDeviceReset(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState)
3787{
3788 /* Send a status good D2H FIS. */
3789 pAhciPort->fResetDevice = false;
3790 if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
3791 ahciPostFirstD2HFisIntoMemory(pAhciPort);
3792
3793 /* As this is the first D2H FIS after the reset update the signature in the SIG register of the port. */
3794 pAhciPort->regSIG = 0x101;
3795 ASMAtomicOrU32(&pAhciPort->u32TasksFinished, (1 << pAhciPortTaskState->uTag));
3796
3797 ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN);
3798}
3799
3800/**
3801 * Build a D2H FIS and post into the memory area of the guest.
3802 *
3803 * @returns Nothing
3804 * @param pAhciPort The port of the SATA controller.
3805 * @param pAhciPortTaskState The state of the task.
3806 * @param pCmdFis Pointer to the command FIS from the guest.
3807 * @param fInterrupt If an interrupt should be send to the guest.
3808 */
3809static void ahciSendD2HFis(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState, uint8_t *pCmdFis, bool fInterrupt)
3810{
3811 uint8_t d2hFis[20];
3812 bool fAssertIntr = false;
3813 PAHCI pAhci = pAhciPort->CTX_SUFF(pAhci);
3814
3815 ahciLog(("%s: building D2H Fis\n", __FUNCTION__));
3816
3817 if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
3818 {
3819 memset(&d2hFis[0], 0, sizeof(d2hFis));
3820 d2hFis[AHCI_CMDFIS_TYPE] = AHCI_CMDFIS_TYPE_D2H;
3821 d2hFis[AHCI_CMDFIS_BITS] = (fInterrupt ? AHCI_CMDFIS_I : 0);
3822 d2hFis[AHCI_CMDFIS_STS] = pAhciPortTaskState->uATARegStatus;
3823 d2hFis[AHCI_CMDFIS_ERR] = pAhciPortTaskState->uATARegError;
3824 d2hFis[AHCI_CMDFIS_SECTN] = pCmdFis[AHCI_CMDFIS_SECTN];
3825 d2hFis[AHCI_CMDFIS_CYLL] = pCmdFis[AHCI_CMDFIS_CYLL];
3826 d2hFis[AHCI_CMDFIS_CYLH] = pCmdFis[AHCI_CMDFIS_CYLH];
3827 d2hFis[AHCI_CMDFIS_HEAD] = pCmdFis[AHCI_CMDFIS_HEAD];
3828 d2hFis[AHCI_CMDFIS_SECTNEXP] = pCmdFis[AHCI_CMDFIS_SECTNEXP];
3829 d2hFis[AHCI_CMDFIS_CYLLEXP] = pCmdFis[AHCI_CMDFIS_CYLLEXP];
3830 d2hFis[AHCI_CMDFIS_CYLHEXP] = pCmdFis[AHCI_CMDFIS_CYLHEXP];
3831 d2hFis[AHCI_CMDFIS_SECTC] = pCmdFis[AHCI_CMDFIS_SECTC];
3832 d2hFis[AHCI_CMDFIS_SECTCEXP] = pCmdFis[AHCI_CMDFIS_SECTCEXP];
3833
3834 /* Update registers. */
3835 pAhciPort->regTFD = (pAhciPortTaskState->uATARegError << 8) | pAhciPortTaskState->uATARegStatus;
3836
3837 ahciPostFisIntoMemory(pAhciPort, AHCI_CMDFIS_TYPE_D2H, d2hFis);
3838
3839 if (pAhciPortTaskState->uATARegStatus & ATA_STAT_ERR)
3840 {
3841 /* Error bit is set. */
3842 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_TFES);
3843 if (pAhciPort->regIE & AHCI_PORT_IE_TFEE)
3844 fAssertIntr = true;
3845 }
3846
3847 if (fInterrupt)
3848 {
3849 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_DHRS);
3850 /* Check if we should assert an interrupt */
3851 if (pAhciPort->regIE & AHCI_PORT_IE_DHRE)
3852 fAssertIntr = true;
3853 }
3854
3855 ASMAtomicOrU32(&pAhciPort->u32TasksFinished, (1 << pAhciPortTaskState->uTag));
3856
3857 if (fAssertIntr)
3858 ahciHbaSetInterrupt(pAhci, pAhciPort->iLUN);
3859 }
3860}
3861
3862/**
3863 * Build a SDB Fis and post it into the memory area of the guest.
3864 *
3865 * @returns Nothing
3866 * @param pAhciPort The port for which the SDB Fis is send.
3867 * @param uFinishedTasks Bitmask of finished tasks.
3868 * @param pAhciPortTaskState The state of the last task.
3869 * @param fInterrupt If an interrupt should be asserted.
3870 */
3871static void ahciSendSDBFis(PAHCIPort pAhciPort, uint32_t uFinishedTasks, PAHCIPORTTASKSTATE pAhciPortTaskState, bool fInterrupt)
3872{
3873 uint32_t sdbFis[2];
3874 bool fAssertIntr = false;
3875 PAHCI pAhci = pAhciPort->CTX_SUFF(pAhci);
3876
3877 ahciLog(("%s: Building SDB FIS\n", __FUNCTION__));
3878
3879 if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
3880 {
3881 memset(&sdbFis[0], 0, sizeof(sdbFis));
3882 sdbFis[0] = AHCI_CMDFIS_TYPE_SETDEVBITS;
3883 sdbFis[0] |= (fInterrupt ? (1 << 14) : 0);
3884 sdbFis[0] |= pAhciPortTaskState->uATARegError << 24;
3885 sdbFis[0] |= (pAhciPortTaskState->uATARegStatus & 0x77) << 16; /* Some bits are marked as reserved and thus are masked out. */
3886 sdbFis[1] = uFinishedTasks;
3887
3888 ahciPostFisIntoMemory(pAhciPort, AHCI_CMDFIS_TYPE_SETDEVBITS, (uint8_t *)sdbFis);
3889
3890 if (pAhciPortTaskState->uATARegStatus & ATA_STAT_ERR)
3891 {
3892 /* Error bit is set. */
3893 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_TFES);
3894 if (pAhciPort->regIE & AHCI_PORT_IE_TFEE)
3895 fAssertIntr = true;
3896 }
3897
3898 if (fInterrupt)
3899 {
3900 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_SDBS);
3901 /* Check if we should assert an interrupt */
3902 if (pAhciPort->regIE & AHCI_PORT_IE_SDBE)
3903 fAssertIntr = true;
3904 }
3905
3906 /* Update registers. */
3907 pAhciPort->regTFD = (pAhciPortTaskState->uATARegError << 8) | pAhciPortTaskState->uATARegStatus;
3908
3909 ASMAtomicOrU32(&pAhciPort->u32QueuedTasksFinished, uFinishedTasks);
3910
3911 if (fAssertIntr)
3912 ahciHbaSetInterrupt(pAhci, pAhciPort->iLUN);
3913 }
3914}
3915
3916static uint32_t ahciGetNSectors(uint8_t *pCmdFis, bool fLBA48)
3917{
3918 /* 0 means either 256 (LBA28) or 65536 (LBA48) sectors. */
3919 if (fLBA48)
3920 {
3921 if (!pCmdFis[AHCI_CMDFIS_SECTC] && !pCmdFis[AHCI_CMDFIS_SECTCEXP])
3922 return 65536;
3923 else
3924 return pCmdFis[AHCI_CMDFIS_SECTCEXP] << 8 | pCmdFis[AHCI_CMDFIS_SECTC];
3925 }
3926 else
3927 {
3928 if (!pCmdFis[AHCI_CMDFIS_SECTC])
3929 return 256;
3930 else
3931 return pCmdFis[AHCI_CMDFIS_SECTC];
3932 }
3933}
3934
3935static uint64_t ahciGetSector(PAHCIPort pAhciPort, uint8_t *pCmdFis, bool fLBA48)
3936{
3937 uint64_t iLBA;
3938 if (pCmdFis[AHCI_CMDFIS_HEAD] & 0x40)
3939 {
3940 /* any LBA variant */
3941 if (fLBA48)
3942 {
3943 /* LBA48 */
3944 iLBA = ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLHEXP] << 40) |
3945 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLLEXP] << 32) |
3946 ((uint64_t)pCmdFis[AHCI_CMDFIS_SECTNEXP] << 24) |
3947 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLH] << 16) |
3948 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLL] << 8) |
3949 pCmdFis[AHCI_CMDFIS_SECTN];
3950 }
3951 else
3952 {
3953 /* LBA */
3954 iLBA = ((pCmdFis[AHCI_CMDFIS_HEAD] & 0x0f) << 24) | (pCmdFis[AHCI_CMDFIS_CYLH] << 16) |
3955 (pCmdFis[AHCI_CMDFIS_CYLL] << 8) | pCmdFis[AHCI_CMDFIS_SECTN];
3956 }
3957 }
3958 else
3959 {
3960 /* CHS */
3961 iLBA = ((pCmdFis[AHCI_CMDFIS_CYLH] << 8) | pCmdFis[AHCI_CMDFIS_CYLL]) * pAhciPort->PCHSGeometry.cHeads * pAhciPort->PCHSGeometry.cSectors +
3962 (pCmdFis[AHCI_CMDFIS_HEAD] & 0x0f) * pAhciPort->PCHSGeometry.cSectors +
3963 (pCmdFis[AHCI_CMDFIS_SECTN] - 1);
3964 }
3965 return iLBA;
3966}
3967
3968static uint64_t ahciGetSectorQueued(uint8_t *pCmdFis)
3969{
3970 uint64_t uLBA;
3971
3972 uLBA = ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLHEXP] << 40) |
3973 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLLEXP] << 32) |
3974 ((uint64_t)pCmdFis[AHCI_CMDFIS_SECTNEXP] << 24) |
3975 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLH] << 16) |
3976 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLL] << 8) |
3977 pCmdFis[AHCI_CMDFIS_SECTN];
3978
3979 return uLBA;
3980}
3981
3982DECLINLINE(uint32_t) ahciGetNSectorsQueued(uint8_t *pCmdFis)
3983{
3984 if (!pCmdFis[AHCI_CMDFIS_FETEXP] && !pCmdFis[AHCI_CMDFIS_FET])
3985 return 65536;
3986 else
3987 return pCmdFis[AHCI_CMDFIS_FETEXP] << 8 | pCmdFis[AHCI_CMDFIS_FET];
3988}
3989
3990DECLINLINE(uint8_t) ahciGetTagQueued(uint8_t *pCmdFis)
3991{
3992 return pCmdFis[AHCI_CMDFIS_SECTC] >> 3;
3993}
3994
3995static void ahciScatterGatherListGetTotalBufferSize(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState)
3996{
3997 CmdHdr *pCmdHdr = &pAhciPortTaskState->cmdHdr;
3998 PPDMDEVINS pDevIns = pAhciPort->CTX_SUFF(pDevIns);
3999 unsigned cActualSGEntry;
4000 SGLEntry aSGLEntry[32]; /* Holds read sg entries from guest. Biggest seen number of entries a guest set up. */
4001 unsigned cSGLEntriesGCRead;
4002 unsigned cSGLEntriesGCLeft; /* Available scatter gather list entries in GC */
4003 RTGCPHYS GCPhysAddrPRDTLEntryStart; /* Start address to read the entries from. */
4004 uint32_t cbSGBuffers = 0; /* Total number of bytes reserved for this request. */
4005
4006 /* Retrieve the total number of bytes reserved for this request. */
4007 cSGLEntriesGCLeft = AHCI_CMDHDR_PRDTL_ENTRIES(pCmdHdr->u32DescInf);
4008 ahciLog(("%s: cSGEntriesGC=%u\n", __FUNCTION__, cSGLEntriesGCLeft));
4009
4010 /* Set start address of the entries. */
4011 GCPhysAddrPRDTLEntryStart = AHCI_RTGCPHYS_FROM_U32(pCmdHdr->u32CmdTblAddrUp, pCmdHdr->u32CmdTblAddr) + AHCI_CMDHDR_PRDT_OFFSET;
4012
4013 do
4014 {
4015 cSGLEntriesGCRead = (cSGLEntriesGCLeft < RT_ELEMENTS(aSGLEntry)) ? cSGLEntriesGCLeft : RT_ELEMENTS(aSGLEntry);
4016 cSGLEntriesGCLeft -= cSGLEntriesGCRead;
4017
4018 /* Read the SG entries. */
4019 PDMDevHlpPhysRead(pDevIns, GCPhysAddrPRDTLEntryStart, &aSGLEntry[0], cSGLEntriesGCRead * sizeof(SGLEntry));
4020
4021 for (cActualSGEntry = 0; cActualSGEntry < cSGLEntriesGCRead; cActualSGEntry++)
4022 cbSGBuffers += (aSGLEntry[cActualSGEntry].u32DescInf & SGLENTRY_DESCINF_DBC) + 1;
4023
4024 /* Set address to the next entries to read. */
4025 GCPhysAddrPRDTLEntryStart += cSGLEntriesGCRead * sizeof(SGLEntry);
4026
4027 } while (cSGLEntriesGCLeft);
4028
4029 pAhciPortTaskState->cbSGBuffers = cbSGBuffers;
4030}
4031
4032static int ahciScatterGatherListAllocate(PAHCIPORTTASKSTATE pAhciPortTaskState, uint32_t cSGList, uint32_t cbUnaligned)
4033{
4034 if (pAhciPortTaskState->cSGListSize < cSGList)
4035 {
4036 /* The entries are not allocated yet or the number is too small. */
4037 if (pAhciPortTaskState->cSGListSize)
4038 {
4039 RTMemFree(pAhciPortTaskState->pSGListHead);
4040 RTMemFree(pAhciPortTaskState->paSGEntries);
4041 }
4042
4043 /* Allocate R3 scatter gather list. */
4044 pAhciPortTaskState->pSGListHead = (PPDMDATASEG)RTMemAllocZ(cSGList * sizeof(PDMDATASEG));
4045 if (!pAhciPortTaskState->pSGListHead)
4046 return VERR_NO_MEMORY;
4047
4048 pAhciPortTaskState->paSGEntries = (PAHCIPORTTASKSTATESGENTRY)RTMemAllocZ(cSGList * sizeof(AHCIPORTTASKSTATESGENTRY));
4049 if (!pAhciPortTaskState->paSGEntries)
4050 return VERR_NO_MEMORY;
4051
4052 /* Reset usage statistics. */
4053 pAhciPortTaskState->cSGListSize = cSGList;
4054 pAhciPortTaskState->cSGListTooBig = 0;
4055 }
4056 else if (pAhciPortTaskState->cSGListSize > cSGList)
4057 {
4058 /*
4059 * The list is too big. Increment counter.
4060 * So that the destroying function can free
4061 * the list if it is too big too many times
4062 * in a row.
4063 */
4064 pAhciPortTaskState->cSGListTooBig++;
4065 }
4066 else
4067 {
4068 /*
4069 * Needed entries matches current size.
4070 * Reset counter.
4071 */
4072 pAhciPortTaskState->cSGListTooBig = 0;
4073 }
4074
4075 pAhciPortTaskState->cSGEntries = cSGList;
4076
4077 if (pAhciPortTaskState->cbBufferUnaligned < cbUnaligned)
4078 {
4079 if (pAhciPortTaskState->pvBufferUnaligned)
4080 RTMemFree(pAhciPortTaskState->pvBufferUnaligned);
4081
4082 Log(("%s: Allocating buffer for unaligned segments cbUnaligned=%u\n", __FUNCTION__, cbUnaligned));
4083
4084 pAhciPortTaskState->pvBufferUnaligned = RTMemAllocZ(cbUnaligned);
4085 if (!pAhciPortTaskState->pvBufferUnaligned)
4086 return VERR_NO_MEMORY;
4087
4088 pAhciPortTaskState->cbBufferUnaligned = cbUnaligned;
4089 }
4090
4091 /* Make debugging easier. */
4092#ifdef DEBUG
4093 memset(pAhciPortTaskState->pSGListHead, 0, pAhciPortTaskState->cSGListSize * sizeof(PDMDATASEG));
4094 memset(pAhciPortTaskState->paSGEntries, 0, pAhciPortTaskState->cSGListSize * sizeof(AHCIPORTTASKSTATESGENTRY));
4095 if (pAhciPortTaskState->pvBufferUnaligned)
4096 memset(pAhciPortTaskState->pvBufferUnaligned, 0, pAhciPortTaskState->cbBufferUnaligned);
4097#endif
4098
4099 return VINF_SUCCESS;
4100}
4101
4102/**
4103 * Fallback scatter gather list creator.
4104 * Used if the normal one fails in PDMDevHlpPhysGCPhys2CCPtr() or
4105 * PDMDevHlpPhysGCPhys2CCPtrReadonly() or post processing
4106 * is used.
4107 *
4108 * returns VBox status code.
4109 * @param pAhciPort The ahci port.
4110 * @param pAhciPortTaskState The task state which contains the S/G list entries.
4111 * @param fReadonly If the mappings should be readonly.
4112 * @param cSGEntriesProcessed Number of entries the normal creator procecssed
4113 * before an error occurred. Used to free
4114 * any ressources allocated before.
4115 * @thread EMT
4116 */
4117static int ahciScatterGatherListCreateSafe(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState,
4118 bool fReadonly, unsigned cSGEntriesProcessed)
4119{
4120 CmdHdr *pCmdHdr = &pAhciPortTaskState->cmdHdr;
4121 PPDMDEVINS pDevIns = pAhciPort->CTX_SUFF(pDevIns);
4122 PAHCIPORTTASKSTATESGENTRY pSGInfoCurr = pAhciPortTaskState->paSGEntries;
4123
4124 Assert(VALID_PTR(pAhciPortTaskState->pSGListHead) || !cSGEntriesProcessed);
4125 Assert(VALID_PTR(pAhciPortTaskState->paSGEntries) || !cSGEntriesProcessed);
4126
4127 for (unsigned cSGEntryCurr = 0; cSGEntryCurr < cSGEntriesProcessed; cSGEntryCurr++)
4128 {
4129 if (pSGInfoCurr->fGuestMemory)
4130 {
4131 /* Release the lock. */
4132 PDMDevHlpPhysReleasePageMappingLock(pDevIns, &pSGInfoCurr->u.direct.PageLock);
4133 }
4134
4135 /* Go to the next entry. */
4136 pSGInfoCurr++;
4137 }
4138
4139 if (pAhciPortTaskState->pvBufferUnaligned)
4140 {
4141 RTMemFree(pAhciPortTaskState->pvBufferUnaligned);
4142 pAhciPortTaskState->pvBufferUnaligned = NULL;
4143 }
4144 if (pAhciPortTaskState->pSGListHead)
4145 {
4146 RTMemFree(pAhciPortTaskState->pSGListHead);
4147 pAhciPortTaskState->pSGListHead = NULL;
4148 }
4149 if (pAhciPortTaskState->paSGEntries)
4150 {
4151 RTMemFree(pAhciPortTaskState->paSGEntries);
4152 pAhciPortTaskState->paSGEntries = NULL;
4153 }
4154 pAhciPortTaskState->cSGListTooBig = 0;
4155 pAhciPortTaskState->cSGEntries = 1;
4156 pAhciPortTaskState->cSGListUsed = 1;
4157 pAhciPortTaskState->cSGListSize = 1;
4158 pAhciPortTaskState->cbBufferUnaligned = pAhciPortTaskState->cbSGBuffers;
4159
4160 /* Allocate new buffers and SG lists. */
4161 pAhciPortTaskState->pvBufferUnaligned = RTMemAlloc(pAhciPortTaskState->cbSGBuffers);
4162 if (!pAhciPortTaskState->pvBufferUnaligned)
4163 return VERR_NO_MEMORY;
4164
4165 pAhciPortTaskState->pSGListHead = (PPDMDATASEG)RTMemAllocZ(1 * sizeof(PDMDATASEG));
4166 if (!pAhciPortTaskState->pSGListHead)
4167 {
4168 RTMemFree(pAhciPortTaskState->pvBufferUnaligned);
4169 return VERR_NO_MEMORY;
4170 }
4171
4172 pAhciPortTaskState->paSGEntries = (PAHCIPORTTASKSTATESGENTRY)RTMemAllocZ(1 * sizeof(AHCIPORTTASKSTATESGENTRY));
4173 if (!pAhciPortTaskState->paSGEntries)
4174 {
4175 RTMemFree(pAhciPortTaskState->pvBufferUnaligned);
4176 RTMemFree(pAhciPortTaskState->pSGListHead);
4177 return VERR_NO_MEMORY;
4178 }
4179
4180 /* Set pointers. */
4181 if (pAhciPortTaskState->cbTransfer)
4182 {
4183 pAhciPortTaskState->pSGListHead[0].cbSeg = pAhciPortTaskState->cbTransfer;
4184
4185 /* Allocate a separate buffer if we have to do post processing . */
4186 if (pAhciPortTaskState->pfnPostProcess)
4187 {
4188 pAhciPortTaskState->pSGListHead[0].pvSeg = RTMemAlloc(pAhciPortTaskState->cbTransfer);
4189 if (!pAhciPortTaskState->pSGListHead[0].pvSeg)
4190 {
4191 RTMemFree(pAhciPortTaskState->paSGEntries);
4192 RTMemFree(pAhciPortTaskState->pvBufferUnaligned);
4193 RTMemFree(pAhciPortTaskState->pSGListHead);
4194 return VERR_NO_MEMORY;
4195 }
4196 }
4197 else
4198 pAhciPortTaskState->pSGListHead[0].pvSeg = pAhciPortTaskState->pvBufferUnaligned;
4199 }
4200 else
4201 {
4202 pAhciPortTaskState->pSGListHead[0].cbSeg = pAhciPortTaskState->cbBufferUnaligned;
4203 pAhciPortTaskState->pSGListHead[0].pvSeg = pAhciPortTaskState->pvBufferUnaligned;
4204 }
4205
4206 pAhciPortTaskState->paSGEntries[0].fGuestMemory = false;
4207 pAhciPortTaskState->paSGEntries[0].u.temp.cUnaligned = AHCI_CMDHDR_PRDTL_ENTRIES(pCmdHdr->u32DescInf);
4208 pAhciPortTaskState->paSGEntries[0].u.temp.GCPhysAddrBaseFirstUnaligned = AHCI_RTGCPHYS_FROM_U32(pCmdHdr->u32CmdTblAddrUp, pCmdHdr->u32CmdTblAddr) + AHCI_CMDHDR_PRDT_OFFSET;
4209 pAhciPortTaskState->paSGEntries[0].u.temp.pvBuf = pAhciPortTaskState->pvBufferUnaligned;
4210
4211 if (pAhciPortTaskState->uTxDir == PDMBLOCKTXDIR_TO_DEVICE)
4212 ahciCopyFromSGListIntoBuffer(pDevIns, &pAhciPortTaskState->paSGEntries[0]);
4213
4214 return VINF_SUCCESS;
4215}
4216
4217/**
4218 * Create scatter gather list descriptors.
4219 *
4220 * @returns VBox status code.
4221 * @param pAhciPort The ahci port.
4222 * @param pAhciPortTaskState The task state which contains the S/G list entries.
4223 * @param fReadonly If the mappings should be readonly.
4224 * @thread EMT
4225 */
4226static int ahciScatterGatherListCreate(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState, bool fReadonly)
4227{
4228 int rc = VINF_SUCCESS;
4229 CmdHdr *pCmdHdr = &pAhciPortTaskState->cmdHdr;
4230 PPDMDEVINS pDevIns = pAhciPort->CTX_SUFF(pDevIns);
4231 unsigned cActualSGEntry;
4232 unsigned cSGEntriesR3 = 0; /* Needed scatter gather list entries in R3. */
4233 unsigned cSGEntriesProcessed = 0; /* Number of SG entries procesed. */
4234 SGLEntry aSGLEntry[32]; /* Holds read sg entries from guest. Biggest seen number of entries a guest set up. */
4235 unsigned cSGLEntriesGCRead;
4236 unsigned cSGLEntriesGCLeft; /* Available scatter gather list entries in GC */
4237 RTGCPHYS GCPhysAddrPRDTLEntryStart; /* Start address to read the entries from. */
4238 uint32_t cbSegment; /* Size of the current segments in bytes. */
4239 bool fUnaligned; /* Flag whether the current buffer is unaligned. */
4240 uint32_t cbUnaligned; /* Size of the unaligned buffers. */
4241 uint32_t cUnaligned;
4242 bool fDoMapping = false;
4243 uint32_t cbSGBuffers = 0; /* Total number of bytes reserved for this request. */
4244 RTGCPHYS GCPhysAddrPRDTLUnalignedStart = NIL_RTGCPHYS;
4245 PAHCIPORTTASKSTATESGENTRY pSGInfoCurr = NULL;
4246 PAHCIPORTTASKSTATESGENTRY pSGInfoPrev = NULL;
4247 PPDMDATASEG pSGEntryCurr = NULL;
4248 PPDMDATASEG pSGEntryPrev = NULL;
4249 RTGCPHYS GCPhysBufferPageAlignedPrev = NIL_RTGCPHYS;
4250 uint8_t *pu8BufferUnalignedPos = NULL;
4251 uint32_t cbUnalignedComplete = 0;
4252
4253 STAM_PROFILE_START(&pAhciPort->StatProfileMapIntoR3, a);
4254
4255 pAhciPortTaskState->cbSGBuffers = 0;
4256
4257 /*
4258 * Create a safe mapping when doing post processing because the size of the
4259 * data to transfer and the amount of guest memory reserved can differ
4260 */
4261 if (pAhciPortTaskState->pfnPostProcess)
4262 {
4263 ahciLog(("%s: Request with post processing.\n"));
4264
4265 ahciScatterGatherListGetTotalBufferSize(pAhciPort, pAhciPortTaskState);
4266
4267 return ahciScatterGatherListCreateSafe(pAhciPort, pAhciPortTaskState, fReadonly, 0);
4268 }
4269
4270 /*
4271 * We need to calculate the number of SG list entries in R3 first because the data buffers in the guest don't need to be
4272 * page aligned. Hence the number of SG list entries in the guest can differ from the ones we need
4273 * because PDMDevHlpPhysGCPhys2CCPtr works only on a page base.
4274 * In the first pass we calculate the number of segments in R3 and in the second pass we map the guest segments into R3.
4275 */
4276 for (int i = 0; i < 2; i++)
4277 {
4278 cSGLEntriesGCLeft = AHCI_CMDHDR_PRDTL_ENTRIES(pCmdHdr->u32DescInf);
4279 ahciLog(("%s: cSGEntriesGC=%u\n", __FUNCTION__, cSGLEntriesGCLeft));
4280
4281 /* Set start address of the entries. */
4282 GCPhysAddrPRDTLEntryStart = AHCI_RTGCPHYS_FROM_U32(pCmdHdr->u32CmdTblAddrUp, pCmdHdr->u32CmdTblAddr) + AHCI_CMDHDR_PRDT_OFFSET;
4283 fUnaligned = false;
4284 cbUnaligned = 0;
4285 cUnaligned = 0;
4286 GCPhysBufferPageAlignedPrev = NIL_RTGCPHYS;
4287
4288 if (fDoMapping)
4289 {
4290 ahciLog(("%s: cSGEntriesR3=%u\n", __FUNCTION__, cSGEntriesR3));
4291 /* The number of needed SG entries in R3 is known. Allocate needed memory. */
4292 rc = ahciScatterGatherListAllocate(pAhciPortTaskState, cSGEntriesR3, cbUnalignedComplete);
4293 AssertMsgRC(rc, ("Failed to allocate scatter gather array rc=%Rrc\n", rc));
4294
4295 /* We are now able to map the pages into R3. */
4296 pSGInfoCurr = pAhciPortTaskState->paSGEntries;
4297 pSGEntryCurr = pAhciPortTaskState->pSGListHead;
4298 pSGEntryPrev = pSGEntryCurr;
4299 pSGInfoPrev = pSGInfoCurr;
4300 /* Initialize first segment to remove the need for additional if checks later in the code. */
4301 pSGEntryCurr->pvSeg = NULL;
4302 pSGEntryCurr->cbSeg = 0;
4303 pSGInfoCurr->fGuestMemory= false;
4304 pu8BufferUnalignedPos = (uint8_t *)pAhciPortTaskState->pvBufferUnaligned;
4305 pAhciPortTaskState->cSGListUsed = 0;
4306 pAhciPortTaskState->cbSGBuffers = cbSGBuffers;
4307 }
4308
4309 do
4310 {
4311 cSGLEntriesGCRead = (cSGLEntriesGCLeft < RT_ELEMENTS(aSGLEntry)) ? cSGLEntriesGCLeft : RT_ELEMENTS(aSGLEntry);
4312 cSGLEntriesGCLeft -= cSGLEntriesGCRead;
4313
4314 /* Read the SG entries. */
4315 PDMDevHlpPhysRead(pDevIns, GCPhysAddrPRDTLEntryStart, &aSGLEntry[0], cSGLEntriesGCRead * sizeof(SGLEntry));
4316
4317 for (cActualSGEntry = 0; cActualSGEntry < cSGLEntriesGCRead; cActualSGEntry++)
4318 {
4319 RTGCPHYS GCPhysAddrDataBase;
4320 uint32_t cbDataToTransfer;
4321
4322 ahciLog(("%s: cActualSGEntry=%u cSGEntriesR3=%u\n", __FUNCTION__, cActualSGEntry, cSGEntriesR3));
4323
4324 cbDataToTransfer = (aSGLEntry[cActualSGEntry].u32DescInf & SGLENTRY_DESCINF_DBC) + 1;
4325 ahciLog(("%s: cbDataToTransfer=%u\n", __FUNCTION__, cbDataToTransfer));
4326 cbSGBuffers += cbDataToTransfer;
4327
4328 /* Check if the buffer is sector aligned. */
4329 if (cbDataToTransfer % 512 != 0)
4330 {
4331 if (!fUnaligned)
4332 {
4333 /* We are not in an unaligned buffer but this is the first unaligned one. */
4334 fUnaligned = true;
4335 cbUnaligned = cbDataToTransfer;
4336 GCPhysAddrPRDTLUnalignedStart = GCPhysAddrPRDTLEntryStart + cActualSGEntry * sizeof(SGLEntry);
4337 cSGEntriesR3++;
4338 cUnaligned = 1;
4339 ahciLog(("%s: Unaligned buffer found cb=%d\n", __FUNCTION__, cbDataToTransfer));
4340 }
4341 else
4342 {
4343 /* We are already in an unaligned buffer and this one is unaligned too. */
4344 cbUnaligned += cbDataToTransfer;
4345 cUnaligned++;
4346 }
4347
4348 cbUnalignedComplete += cbDataToTransfer;
4349 }
4350 else /* Guest segment size is sector aligned. */
4351 {
4352 if (fUnaligned)
4353 {
4354 if (cbUnaligned % 512 == 0)
4355 {
4356 /*
4357 * The last buffer started at an offset
4358 * not aligned to a sector boundary but this buffer
4359 * is sector aligned. Check if the current size of all
4360 * unaligned segments is a multiple of a sector.
4361 * If that's the case we can now map the segments again into R3.
4362 */
4363 fUnaligned = false;
4364
4365 if (fDoMapping)
4366 {
4367 /* Set up the entry. */
4368 pSGInfoCurr->fGuestMemory = false;
4369 pSGInfoCurr->u.temp.GCPhysAddrBaseFirstUnaligned = GCPhysAddrPRDTLUnalignedStart;
4370 pSGInfoCurr->u.temp.cUnaligned = cUnaligned;
4371 pSGInfoCurr->u.temp.pvBuf = pu8BufferUnalignedPos;
4372
4373 pSGEntryCurr->pvSeg = pu8BufferUnalignedPos;
4374 pSGEntryCurr->cbSeg = cbUnaligned;
4375 pu8BufferUnalignedPos += cbUnaligned;
4376
4377 /*
4378 * If the transfer is to the device we need to copy the content of the not mapped guest
4379 * segments into the temporary buffer.
4380 */
4381 if (pAhciPortTaskState->uTxDir == PDMBLOCKTXDIR_TO_DEVICE)
4382 ahciCopyFromSGListIntoBuffer(pDevIns, pSGInfoCurr);
4383
4384 /* Advance to next entry saving the pointers to the current ones. */
4385 pSGEntryPrev = pSGEntryCurr;
4386 pSGInfoPrev = pSGInfoCurr;
4387 pSGInfoCurr++;
4388 pSGEntryCurr++;
4389 pAhciPortTaskState->cSGListUsed++;
4390 cSGEntriesProcessed++;
4391 }
4392 }
4393 else
4394 {
4395 cbUnaligned += cbDataToTransfer;
4396 cbUnalignedComplete += cbDataToTransfer;
4397 cUnaligned++;
4398 }
4399 }
4400 else
4401 {
4402 /*
4403 * The size of the guest segment is sector aligned but it is possible that the segment crosses
4404 * a page boundary in a way splitting the segment into parts which are not sector aligned.
4405 * We have to treat them like unaligned guest segments then.
4406 */
4407 GCPhysAddrDataBase = AHCI_RTGCPHYS_FROM_U32(aSGLEntry[cActualSGEntry].u32DBAUp, aSGLEntry[cActualSGEntry].u32DBA);
4408
4409 ahciLog(("%s: GCPhysAddrDataBase=%RGp\n", __FUNCTION__, GCPhysAddrDataBase));
4410
4411 /*
4412 * Check if the physical address is page aligned.
4413 */
4414 if (GCPhysAddrDataBase & PAGE_OFFSET_MASK)
4415 {
4416 RTGCPHYS GCPhysAddrDataNextPage = PHYS_PAGE_ADDRESS(GCPhysAddrDataBase) + PAGE_SIZE;
4417 /* Difference from the buffer start to the next page boundary. */
4418 uint32_t u32GCPhysAddrDiff = GCPhysAddrDataNextPage - GCPhysAddrDataBase;
4419
4420 if (u32GCPhysAddrDiff % 512 != 0)
4421 {
4422 if (!fUnaligned)
4423 {
4424 /* We are not in an unaligned buffer but this is the first unaligned one. */
4425 fUnaligned = true;
4426 cbUnaligned = cbDataToTransfer;
4427 GCPhysAddrPRDTLUnalignedStart = GCPhysAddrPRDTLEntryStart + cActualSGEntry * sizeof(SGLEntry);
4428 cSGEntriesR3++;
4429 cUnaligned = 1;
4430 ahciLog(("%s: Guest segment is sector aligned but crosses a page boundary cb=%d\n", __FUNCTION__, cbDataToTransfer));
4431 }
4432 else
4433 {
4434 /* We are already in an unaligned buffer and this one is unaligned too. */
4435 cbUnaligned += cbDataToTransfer;
4436 cUnaligned++;
4437 }
4438
4439 cbUnalignedComplete += cbDataToTransfer;
4440 }
4441 else
4442 {
4443 ahciLog(("%s: Align page: GCPhysAddrDataBase=%RGp GCPhysAddrDataNextPage=%RGp\n",
4444 __FUNCTION__, GCPhysAddrDataBase, GCPhysAddrDataNextPage));
4445
4446 RTGCPHYS GCPhysBufferPageAligned = PHYS_PAGE_ADDRESS(GCPhysAddrDataBase);
4447
4448 /* Check if the mapping ends at the page boundary and set segment size accordingly. */
4449 cbSegment = (cbDataToTransfer < u32GCPhysAddrDiff)
4450 ? cbDataToTransfer
4451 : u32GCPhysAddrDiff;
4452 /* Subtract size of the buffer in the actual page. */
4453 cbDataToTransfer -= cbSegment;
4454
4455 if (GCPhysBufferPageAlignedPrev != GCPhysBufferPageAligned)
4456 {
4457 /* We don't need to map the buffer if it is in the same page as the previous one. */
4458 if (fDoMapping)
4459 {
4460 uint8_t *pbMapping;
4461
4462 pSGInfoCurr->fGuestMemory = true;
4463
4464 /* Create the mapping. */
4465 if (fReadonly)
4466 rc = PDMDevHlpPhysGCPhys2CCPtrReadOnly(pDevIns, GCPhysBufferPageAligned,
4467 0, (const void **)&pbMapping,
4468 &pSGInfoCurr->u.direct.PageLock);
4469 else
4470 rc = PDMDevHlpPhysGCPhys2CCPtr(pDevIns, GCPhysBufferPageAligned,
4471 0, (void **)&pbMapping,
4472 &pSGInfoCurr->u.direct.PageLock);
4473
4474 if (RT_FAILURE(rc))
4475 {
4476 /* Mapping failed. Fall back to a bounce buffer. */
4477 ahciLog(("%s: Mapping guest physical address %RGp failed with rc=%Rrc\n",
4478 __FUNCTION__, GCPhysBufferPageAligned, rc));
4479
4480 return ahciScatterGatherListCreateSafe(pAhciPort, pAhciPortTaskState, fReadonly,
4481 cSGEntriesProcessed);
4482 }
4483
4484 if ((pbMapping + (GCPhysAddrDataBase - GCPhysBufferPageAligned) == ((uint8_t *)pSGEntryPrev->pvSeg + pSGEntryCurr->cbSeg)))
4485 {
4486 pSGEntryPrev->cbSeg += cbSegment;
4487 ahciLog(("%s: Merged mapping pbMapping=%#p into current segment pvSeg=%#p. New size is cbSeg=%d\n",
4488 __FUNCTION__, pbMapping, pSGEntryPrev->pvSeg, pSGEntryPrev->cbSeg));
4489 }
4490 else
4491 {
4492 pSGEntryCurr->cbSeg = cbSegment;
4493
4494 /* Let pvBuf point to the start of the buffer in the page. */
4495 pSGEntryCurr->pvSeg = pbMapping
4496 + (GCPhysAddrDataBase - GCPhysBufferPageAligned);
4497
4498 ahciLog(("%s: pvSegBegin=%#p pvSegEnd=%#p\n", __FUNCTION__,
4499 pSGEntryCurr->pvSeg,
4500 (uint8_t *)pSGEntryCurr->pvSeg + pSGEntryCurr->cbSeg));
4501
4502 pSGEntryPrev = pSGEntryCurr;
4503 pSGEntryCurr++;
4504 pAhciPortTaskState->cSGListUsed++;
4505 }
4506
4507 pSGInfoPrev = pSGInfoCurr;
4508 pSGInfoCurr++;
4509 cSGEntriesProcessed++;
4510 }
4511 else
4512 cSGEntriesR3++;
4513 }
4514 else if (fDoMapping)
4515 {
4516 pSGEntryPrev->cbSeg += cbSegment;
4517 ahciLog(("%s: Buffer is already in previous mapping pvSeg=%#p. New size is cbSeg=%d\n",
4518 __FUNCTION__, pSGEntryPrev->pvSeg, pSGEntryPrev->cbSeg));
4519 }
4520
4521 /* Let physical address point to the next page in the buffer. */
4522 GCPhysAddrDataBase = GCPhysAddrDataNextPage;
4523 GCPhysBufferPageAlignedPrev = GCPhysBufferPageAligned;
4524 }
4525 }
4526
4527 if (!fUnaligned)
4528 {
4529 /* The address is now page aligned. */
4530 while (cbDataToTransfer)
4531 {
4532 ahciLog(("%s: GCPhysAddrDataBase=%RGp cbDataToTransfer=%u cSGEntriesR3=%u\n",
4533 __FUNCTION__, GCPhysAddrDataBase, cbDataToTransfer, cSGEntriesR3));
4534
4535 /* Check if this is the last page the buffer is in. */
4536 cbSegment = (cbDataToTransfer < PAGE_SIZE) ? cbDataToTransfer : PAGE_SIZE;
4537 cbDataToTransfer -= cbSegment;
4538
4539 if (fDoMapping)
4540 {
4541 void *pvMapping;
4542
4543 pSGInfoCurr->fGuestMemory = true;
4544
4545 /* Create the mapping. */
4546 if (fReadonly)
4547 rc = PDMDevHlpPhysGCPhys2CCPtrReadOnly(pDevIns, GCPhysAddrDataBase, 0, (const void **)&pvMapping, &pSGInfoCurr->u.direct.PageLock);
4548 else
4549 rc = PDMDevHlpPhysGCPhys2CCPtr(pDevIns, GCPhysAddrDataBase, 0, &pvMapping, &pSGInfoCurr->u.direct.PageLock);
4550
4551 if (RT_FAILURE(rc))
4552 {
4553 /* Mapping failed. Fall back to a bounce buffer. */
4554 ahciLog(("%s: Mapping guest physical address %RGp failed with rc=%Rrc\n",
4555 __FUNCTION__, GCPhysAddrDataBase, rc));
4556
4557 return ahciScatterGatherListCreateSafe(pAhciPort, pAhciPortTaskState, fReadonly,
4558 cSGEntriesProcessed);
4559 }
4560
4561 /* Check for adjacent mappings. */
4562 if (pvMapping == ((uint8_t *)pSGEntryPrev->pvSeg + pSGEntryPrev->cbSeg)
4563 && (pSGInfoPrev->fGuestMemory == true))
4564 {
4565 /* Yes they are adjacent. Just add the size of this mapping to the previous segment. */
4566 pSGEntryPrev->cbSeg += cbSegment;
4567 ahciLog(("%s: Merged mapping pvMapping=%#p into current segment pvSeg=%#p. New size is cbSeg=%d\n",
4568 __FUNCTION__, pvMapping, pSGEntryPrev->pvSeg, pSGEntryPrev->cbSeg));
4569 }
4570 else
4571 {
4572 /* No they are not. Use a new sg entry. */
4573 pSGEntryCurr->cbSeg = cbSegment;
4574 pSGEntryCurr->pvSeg = pvMapping;
4575 ahciLog(("%s: pvSegBegin=%#p pvSegEnd=%#p\n", __FUNCTION__,
4576 pSGEntryCurr->pvSeg,
4577 (uint8_t *)pSGEntryCurr->pvSeg + pSGEntryCurr->cbSeg));
4578 pSGEntryPrev = pSGEntryCurr;
4579 pSGEntryCurr++;
4580 pAhciPortTaskState->cSGListUsed++;
4581 }
4582
4583 pSGInfoPrev = pSGInfoCurr;
4584 pSGInfoCurr++;
4585 cSGEntriesProcessed++;
4586 }
4587 else
4588 cSGEntriesR3++;
4589
4590 GCPhysBufferPageAlignedPrev = GCPhysAddrDataBase;
4591
4592 /* Go to the next page. */
4593 GCPhysAddrDataBase += PAGE_SIZE;
4594 }
4595 } /* if (!fUnaligned) */
4596 } /* if !fUnaligned */
4597 } /* if guest segment is sector aligned. */
4598 } /* for SGEntries read */
4599
4600 /* Set address to the next entries to read. */
4601 GCPhysAddrPRDTLEntryStart += cSGLEntriesGCRead * sizeof(SGLEntry);
4602
4603 } while (cSGLEntriesGCLeft);
4604
4605 fDoMapping = true;
4606
4607 } /* for passes */
4608
4609 /* Check if the last processed segment was unaligned. We need to add it now. */
4610 if (fUnaligned)
4611 {
4612 /* Set up the entry. */
4613 AssertMsg(!(cbUnaligned % 512), ("Buffer is not sector aligned\n"));
4614 pSGInfoCurr->fGuestMemory = false;
4615 pSGInfoCurr->u.temp.GCPhysAddrBaseFirstUnaligned = GCPhysAddrPRDTLUnalignedStart;
4616 pSGInfoCurr->u.temp.cUnaligned = cUnaligned;
4617 pSGInfoCurr->u.temp.pvBuf = pu8BufferUnalignedPos;
4618
4619 pSGEntryCurr->pvSeg = pu8BufferUnalignedPos;
4620 pSGEntryCurr->cbSeg = cbUnaligned;
4621 pAhciPortTaskState->cSGListUsed++;
4622
4623 /*
4624 * If the transfer is to the device we need to copy the content of the not mapped guest
4625 * segments into the temporary buffer.
4626 */
4627 if (pAhciPortTaskState->uTxDir == PDMBLOCKTXDIR_TO_DEVICE)
4628 ahciCopyFromSGListIntoBuffer(pDevIns, pSGInfoCurr);
4629 }
4630
4631 STAM_PROFILE_STOP(&pAhciPort->StatProfileMapIntoR3, a);
4632
4633 return rc;
4634}
4635
4636/**
4637 * Destroy a scatter gather list and free all occupied resources (mappings, etc.)
4638 *
4639 * @returns VBox status code.
4640 * @param pAhciPort The ahci port.
4641 * @param pAhciPortTaskState The task state which contains the S/G list entries.
4642 */
4643static int ahciScatterGatherListDestroy(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState)
4644{
4645 PAHCIPORTTASKSTATESGENTRY pSGInfoCurr = pAhciPortTaskState->paSGEntries;
4646 PPDMDEVINS pDevIns = pAhciPort->CTX_SUFF(pDevIns);
4647
4648 STAM_PROFILE_START(&pAhciPort->StatProfileDestroyScatterGatherList, a);
4649
4650 if (pAhciPortTaskState->pfnPostProcess)
4651 {
4652 int rc;
4653 rc = pAhciPortTaskState->pfnPostProcess(pAhciPortTaskState);
4654 AssertRC(rc);
4655
4656 pAhciPortTaskState->pfnPostProcess = NULL;
4657
4658 /* Free the buffer holding the unprocessed data. They are not needed anymore. */
4659 RTMemFree(pAhciPortTaskState->pSGListHead[0].pvSeg);
4660 }
4661
4662 for (unsigned cActualSGEntry = 0; cActualSGEntry < pAhciPortTaskState->cSGEntries; cActualSGEntry++)
4663 {
4664 if (pSGInfoCurr->fGuestMemory)
4665 {
4666 /* Release the lock. */
4667 PDMDevHlpPhysReleasePageMappingLock(pDevIns, &pSGInfoCurr->u.direct.PageLock);
4668 }
4669 else if (pAhciPortTaskState->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE)
4670 {
4671 /* Copy the data into the guest segments now. */
4672 ahciCopyFromBufferIntoSGList(pDevIns, pSGInfoCurr);
4673 }
4674
4675 /* Go to the next entry. */
4676 pSGInfoCurr++;
4677 }
4678
4679 /* Free allocated memory if the list was too big too many times. */
4680 if (pAhciPortTaskState->cSGListTooBig >= AHCI_NR_OF_ALLOWED_BIGGER_LISTS)
4681 {
4682 RTMemFree(pAhciPortTaskState->pSGListHead);
4683 RTMemFree(pAhciPortTaskState->paSGEntries);
4684 if (pAhciPortTaskState->pvBufferUnaligned)
4685 RTMemFree(pAhciPortTaskState->pvBufferUnaligned);
4686 pAhciPortTaskState->cSGListSize = 0;
4687 pAhciPortTaskState->cSGListTooBig = 0;
4688 pAhciPortTaskState->pSGListHead = NULL;
4689 pAhciPortTaskState->paSGEntries = NULL;
4690 pAhciPortTaskState->pvBufferUnaligned = NULL;
4691 pAhciPortTaskState->cbBufferUnaligned = 0;
4692 }
4693
4694 STAM_PROFILE_STOP(&pAhciPort->StatProfileDestroyScatterGatherList, a);
4695
4696 return VINF_SUCCESS;
4697}
4698
4699/**
4700 * Copy a temporary buffer into a part of the guest scatter gather list
4701 * described by the given descriptor entry.
4702 *
4703 * @returns nothing.
4704 * @param pDevIns Pointer to the device instance data.
4705 * @param pSGInfo Pointer to the segment info structure which describes the guest segments
4706 * to write to which are unaligned.
4707 */
4708static void ahciCopyFromBufferIntoSGList(PPDMDEVINS pDevIns, PAHCIPORTTASKSTATESGENTRY pSGInfo)
4709{
4710 uint8_t *pu8Buf = (uint8_t *)pSGInfo->u.temp.pvBuf;
4711 SGLEntry aSGLEntries[5];
4712 uint32_t cSGEntriesLeft = pSGInfo->u.temp.cUnaligned;
4713 RTGCPHYS GCPhysPRDTLStart = pSGInfo->u.temp.GCPhysAddrBaseFirstUnaligned;
4714
4715 AssertMsg(!pSGInfo->fGuestMemory, ("This is not possible\n"));
4716
4717 do
4718 {
4719 uint32_t cSGEntriesRead = (cSGEntriesLeft < RT_ELEMENTS(aSGLEntries))
4720 ? cSGEntriesLeft
4721 : RT_ELEMENTS(aSGLEntries);
4722
4723 PDMDevHlpPhysRead(pDevIns, GCPhysPRDTLStart, &aSGLEntries[0], cSGEntriesRead * sizeof(SGLEntry));
4724
4725 for (uint32_t i = 0; i < cSGEntriesRead; i++)
4726 {
4727 RTGCPHYS GCPhysAddrDataBase = AHCI_RTGCPHYS_FROM_U32(aSGLEntries[i].u32DBAUp, aSGLEntries[i].u32DBA);
4728 uint32_t cbCopied = (aSGLEntries[i].u32DescInf & SGLENTRY_DESCINF_DBC) + 1;
4729
4730 /* Copy into SG entry. */
4731 PDMDevHlpPhysWrite(pDevIns, GCPhysAddrDataBase, pu8Buf, cbCopied);
4732
4733 pu8Buf += cbCopied;
4734 }
4735
4736 GCPhysPRDTLStart += cSGEntriesRead * sizeof(SGLEntry);
4737 cSGEntriesLeft -= cSGEntriesRead;
4738 } while (cSGEntriesLeft);
4739}
4740
4741/**
4742 * Copy a part of the guest scatter gather list into a temporary buffer.
4743 *
4744 * @returns nothing.
4745 * @param pDevIns Pointer to the device instance data.
4746 * @param pSGInfo Pointer to the segment info structure which describes the guest segments
4747 * to read from which are unaligned.
4748 */
4749static void ahciCopyFromSGListIntoBuffer(PPDMDEVINS pDevIns, PAHCIPORTTASKSTATESGENTRY pSGInfo)
4750{
4751 uint8_t *pu8Buf = (uint8_t *)pSGInfo->u.temp.pvBuf;
4752 SGLEntry aSGLEntries[5];
4753 uint32_t cSGEntriesLeft = pSGInfo->u.temp.cUnaligned;
4754 RTGCPHYS GCPhysPRDTLStart = pSGInfo->u.temp.GCPhysAddrBaseFirstUnaligned;
4755
4756 AssertMsg(!pSGInfo->fGuestMemory, ("This is not possible\n"));
4757
4758 do
4759 {
4760 uint32_t cSGEntriesRead = (cSGEntriesLeft < RT_ELEMENTS(aSGLEntries))
4761 ? cSGEntriesLeft
4762 : RT_ELEMENTS(aSGLEntries);
4763
4764 PDMDevHlpPhysRead(pDevIns, GCPhysPRDTLStart, &aSGLEntries[0], cSGEntriesRead * sizeof(SGLEntry));
4765
4766 for (uint32_t i = 0; i < cSGEntriesRead; i++)
4767 {
4768 RTGCPHYS GCPhysAddrDataBase = AHCI_RTGCPHYS_FROM_U32(aSGLEntries[i].u32DBAUp, aSGLEntries[i].u32DBA);
4769 uint32_t cbCopied = (aSGLEntries[i].u32DescInf & SGLENTRY_DESCINF_DBC) + 1;
4770
4771 /* Copy into buffer. */
4772 PDMDevHlpPhysRead(pDevIns, GCPhysAddrDataBase, pu8Buf, cbCopied);
4773
4774 pu8Buf += cbCopied;
4775 }
4776
4777 GCPhysPRDTLStart += cSGEntriesRead * sizeof(SGLEntry);
4778 cSGEntriesLeft -= cSGEntriesRead;
4779 } while (cSGEntriesLeft);
4780}
4781
4782
4783/**
4784 * Copy the content of a buffer to a scatter gather list.
4785 *
4786 * @returns Number of bytes transfered.
4787 * @param pAhciPortTaskState The task state which contains the S/G list entries.
4788 * @param pvBuf Pointer to the buffer which should be copied.
4789 * @param cbBuf Size of the buffer.
4790 */
4791static int ahciScatterGatherListCopyFromBuffer(PAHCIPORTTASKSTATE pAhciPortTaskState, void *pvBuf, size_t cbBuf)
4792{
4793 unsigned cSGEntry = 0;
4794 int cbCopied = 0;
4795 PPDMDATASEG pSGEntry = &pAhciPortTaskState->pSGListHead[cSGEntry];
4796 uint8_t *pu8Buf = (uint8_t *)pvBuf;
4797
4798 while (cSGEntry < pAhciPortTaskState->cSGEntries)
4799 {
4800 size_t cbToCopy = RT_MIN(cbBuf, pSGEntry->cbSeg);
4801
4802 memcpy(pSGEntry->pvSeg, pu8Buf, cbToCopy);
4803
4804 cbBuf -= cbToCopy;
4805 cbCopied += cbToCopy;
4806
4807 /* We finished. */
4808 if (!cbBuf)
4809 break;
4810
4811 /* Advance the buffer. */
4812 pu8Buf += cbToCopy;
4813
4814 /* Go to the next entry in the list. */
4815 pSGEntry++;
4816 cSGEntry++;
4817 }
4818
4819 LogFlow(("%s: Copied %d bytes\n", __FUNCTION__, cbCopied));
4820 return cbCopied;
4821}
4822
4823/* -=-=-=-=- IBlockAsyncPort -=-=-=-=- */
4824
4825/** Makes a PAHCIPort out of a PPDMIBLOCKASYNCPORT. */
4826#define PDMIBLOCKASYNCPORT_2_PAHCIPORT(pInterface) ( (PAHCIPort)((uintptr_t)pInterface - RT_OFFSETOF(AHCIPort, IPortAsync)) )
4827
4828/**
4829 * Complete a data transfer task by freeing all occupied ressources
4830 * and notifying the guest.
4831 *
4832 * @returns VBox status code
4833 *
4834 * @param pAhciPort Pointer to the port where to request completed.
4835 * @param pAhciPortTaskState Pointer to the task which finished.
4836 */
4837static int ahciTransferComplete(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState)
4838{
4839 /* Free system resources occupied by the scatter gather list. */
4840 ahciScatterGatherListDestroy(pAhciPort, pAhciPortTaskState);
4841
4842 pAhciPortTaskState->cmdHdr.u32PRDBC = pAhciPortTaskState->cbTransfer;
4843
4844 pAhciPortTaskState->uATARegError = 0;
4845 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
4846 /* Write updated command header into memory of the guest. */
4847 PDMDevHlpPhysWrite(pAhciPort->CTX_SUFF(pDevIns), pAhciPortTaskState->GCPhysCmdHdrAddr,
4848 &pAhciPortTaskState->cmdHdr, sizeof(CmdHdr));
4849
4850 if (pAhciPortTaskState->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE)
4851 {
4852 STAM_REL_COUNTER_ADD(&pAhciPort->StatBytesRead, pAhciPortTaskState->cbTransfer);
4853 pAhciPort->Led.Actual.s.fReading = 0;
4854 }
4855 else
4856 {
4857 STAM_REL_COUNTER_ADD(&pAhciPort->StatBytesWritten, pAhciPortTaskState->cbTransfer);
4858 pAhciPort->Led.Actual.s.fWriting = 0;
4859 }
4860
4861 if (pAhciPortTaskState->fQueued)
4862 {
4863 uint32_t cOutstandingTasks;
4864
4865 ahciLog(("%s: Before decrement uActTasksActive=%u\n", __FUNCTION__, pAhciPort->uActTasksActive));
4866 cOutstandingTasks = ASMAtomicDecU32(&pAhciPort->uActTasksActive);
4867 ahciLog(("%s: After decrement uActTasksActive=%u\n", __FUNCTION__, cOutstandingTasks));
4868 ASMAtomicOrU32(&pAhciPort->u32QueuedTasksFinished, (1 << pAhciPortTaskState->uTag));
4869
4870 if (!cOutstandingTasks)
4871 ahciSendSDBFis(pAhciPort, pAhciPort->u32QueuedTasksFinished, pAhciPortTaskState, true);
4872 }
4873 else
4874 ahciSendD2HFis(pAhciPort, pAhciPortTaskState, pAhciPortTaskState->cmdFis, true);
4875
4876 /* Add the task to the cache. */
4877 pAhciPort->aCachedTasks[pAhciPortTaskState->uTag] = pAhciPortTaskState;
4878
4879 return VINF_SUCCESS;
4880}
4881
4882/**
4883 * Notification callback for a completed transfer.
4884 *
4885 * @returns VBox status code.
4886 * @param pInterface Pointer to the interface.
4887 * @param pvUser User data.
4888 */
4889static DECLCALLBACK(int) ahciTransferCompleteNotify(PPDMIBLOCKASYNCPORT pInterface, void *pvUser)
4890{
4891 PAHCIPort pAhciPort = PDMIBLOCKASYNCPORT_2_PAHCIPORT(pInterface);
4892 PAHCIPORTTASKSTATE pAhciPortTaskState = (PAHCIPORTTASKSTATE)pvUser;
4893
4894 ahciLog(("%s: pInterface=%p pvUser=%p uTag=%u\n",
4895 __FUNCTION__, pInterface, pvUser, pAhciPortTaskState->uTag));
4896
4897 int rc = ahciTransferComplete(pAhciPort, pAhciPortTaskState);
4898
4899 if (pAhciPort->uActTasksActive == 0 && pAhciPort->pAhciR3->fSignalIdle)
4900 PDMDevHlpAsyncNotificationCompleted(pAhciPort->pDevInsR3);
4901 return rc;
4902}
4903
4904/**
4905 * Process an non read/write ATA command.
4906 *
4907 * @returns The direction of the data transfer
4908 * @param pCmdHdr Pointer to the command header.
4909 */
4910static int ahciProcessCmd(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState, uint8_t *pCmdFis)
4911{
4912 int rc = PDMBLOCKTXDIR_NONE;
4913 bool fLBA48 = false;
4914 CmdHdr *pCmdHdr = &pAhciPortTaskState->cmdHdr;
4915
4916 AssertMsg(pCmdFis[AHCI_CMDFIS_TYPE] == AHCI_CMDFIS_TYPE_H2D, ("FIS is not a host to device Fis!!\n"));
4917
4918 pAhciPortTaskState->cbTransfer = 0;
4919
4920 switch (pCmdFis[AHCI_CMDFIS_CMD])
4921 {
4922 case ATA_IDENTIFY_DEVICE:
4923 {
4924 if (pAhciPort->pDrvBlock && !pAhciPort->fATAPI)
4925 {
4926 uint16_t u16Temp[256];
4927
4928 /* Fill the buffer. */
4929 ahciIdentifySS(pAhciPort, u16Temp);
4930
4931 /* Create scatter gather list. */
4932 rc = ahciScatterGatherListCreate(pAhciPort, pAhciPortTaskState, false);
4933 if (RT_FAILURE(rc))
4934 AssertMsgFailed(("Creating list failed rc=%Rrc\n", rc));
4935
4936 /* Copy the buffer. */
4937 pCmdHdr->u32PRDBC = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, &u16Temp[0], sizeof(u16Temp));
4938
4939 /* Destroy list. */
4940 rc = ahciScatterGatherListDestroy(pAhciPort, pAhciPortTaskState);
4941 if (RT_FAILURE(rc))
4942 AssertMsgFailed(("Freeing list failed rc=%Rrc\n", rc));
4943
4944 pAhciPortTaskState->uATARegError = 0;
4945 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
4946
4947 /* Write updated command header into memory of the guest. */
4948 PDMDevHlpPhysWrite(pAhciPort->CTX_SUFF(pDevIns), pAhciPortTaskState->GCPhysCmdHdrAddr, pCmdHdr, sizeof(CmdHdr));
4949 }
4950 else
4951 {
4952 pAhciPortTaskState->uATARegError = ABRT_ERR;
4953 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
4954 }
4955 break;
4956 }
4957 case ATA_READ_NATIVE_MAX_ADDRESS_EXT:
4958 case ATA_READ_NATIVE_MAX_ADDRESS:
4959 break;
4960 case ATA_SET_FEATURES:
4961 {
4962 switch (pCmdFis[AHCI_CMDFIS_FET])
4963 {
4964 case 0x02: /* write cache enable */
4965 case 0xaa: /* read look-ahead enable */
4966 case 0x55: /* read look-ahead disable */
4967 case 0xcc: /* reverting to power-on defaults enable */
4968 case 0x66: /* reverting to power-on defaults disable */
4969 pAhciPortTaskState->uATARegError = 0;
4970 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
4971 break;
4972 case 0x82: /* write cache disable */
4973 rc = pAhciPort->pDrvBlock->pfnFlush(pAhciPort->pDrvBlock);
4974 pAhciPortTaskState->uATARegError = 0;
4975 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
4976 break;
4977 case 0x03:
4978 { /* set transfer mode */
4979 Log2(("%s: transfer mode %#04x\n", __FUNCTION__, pCmdFis[AHCI_CMDFIS_SECTC]));
4980 switch (pCmdFis[AHCI_CMDFIS_SECTC] & 0xf8)
4981 {
4982 case 0x00: /* PIO default */
4983 case 0x08: /* PIO mode */
4984 break;
4985 case ATA_MODE_MDMA: /* MDMA mode */
4986 pAhciPort->uATATransferMode = (pCmdFis[AHCI_CMDFIS_SECTC] & 0xf8) | RT_MIN(pCmdFis[AHCI_CMDFIS_SECTC] & 0x07, ATA_MDMA_MODE_MAX);
4987 break;
4988 case ATA_MODE_UDMA: /* UDMA mode */
4989 pAhciPort->uATATransferMode = (pCmdFis[AHCI_CMDFIS_SECTC] & 0xf8) | RT_MIN(pCmdFis[AHCI_CMDFIS_SECTC] & 0x07, ATA_UDMA_MODE_MAX);
4990 break;
4991 }
4992 break;
4993 }
4994 default:
4995 pAhciPortTaskState->uATARegError = ABRT_ERR;
4996 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_ERR;
4997 }
4998 break;
4999 }
5000 case ATA_FLUSH_CACHE_EXT:
5001 case ATA_FLUSH_CACHE:
5002 rc = pAhciPort->pDrvBlock->pfnFlush(pAhciPort->pDrvBlock);
5003 pAhciPortTaskState->uATARegError = 0;
5004 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
5005 break;
5006 case ATA_PACKET:
5007 if (!pAhciPort->fATAPI)
5008 {
5009 pAhciPortTaskState->uATARegError = ABRT_ERR;
5010 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_ERR;
5011 }
5012 else
5013 {
5014 rc = atapiParseCmdVirtualATAPI(pAhciPort, pAhciPortTaskState);
5015 }
5016 break;
5017 case ATA_IDENTIFY_PACKET_DEVICE:
5018 if (!pAhciPort->fATAPI)
5019 {
5020 pAhciPortTaskState->uATARegError = ABRT_ERR;
5021 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_ERR;
5022 }
5023 else
5024 {
5025 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_IDENTIFY);
5026
5027 pAhciPortTaskState->uATARegError = 0;
5028 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
5029 }
5030 break;
5031 case ATA_SET_MULTIPLE_MODE:
5032 if ( pCmdFis[AHCI_CMDFIS_SECTC] != 0
5033 && ( pCmdFis[AHCI_CMDFIS_SECTC] > ATA_MAX_MULT_SECTORS
5034 || (pCmdFis[AHCI_CMDFIS_SECTC] & (pCmdFis[AHCI_CMDFIS_SECTC] - 1)) != 0))
5035 {
5036 pAhciPortTaskState->uATARegError = ABRT_ERR;
5037 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_ERR;
5038 }
5039 else
5040 {
5041 Log2(("%s: set multi sector count to %d\n", __FUNCTION__, pCmdFis[AHCI_CMDFIS_SECTC]));
5042 pAhciPort->cMultSectors = pCmdFis[AHCI_CMDFIS_SECTC];
5043 pAhciPortTaskState->uATARegError = 0;
5044 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
5045 }
5046 break;
5047 case ATA_STANDBY_IMMEDIATE:
5048 break; /* Do nothing. */
5049 case ATA_CHECK_POWER_MODE:
5050 pAhciPortTaskState->cmdFis[AHCI_CMDFIS_SECTC] = 0xff; /* drive active or idle */
5051 /* fall through */
5052 case ATA_INITIALIZE_DEVICE_PARAMETERS:
5053 case ATA_IDLE_IMMEDIATE:
5054 case ATA_RECALIBRATE:
5055 case ATA_NOP:
5056 case ATA_READ_VERIFY_SECTORS_EXT:
5057 case ATA_READ_VERIFY_SECTORS:
5058 case ATA_READ_VERIFY_SECTORS_WITHOUT_RETRIES:
5059 pAhciPortTaskState->uATARegError = 0;
5060 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
5061 break;
5062 case ATA_READ_DMA_EXT:
5063 fLBA48 = true;
5064 case ATA_READ_DMA:
5065 {
5066 pAhciPortTaskState->cbTransfer = ahciGetNSectors(pCmdFis, fLBA48) * 512;
5067 pAhciPortTaskState->uOffset = ahciGetSector(pAhciPort, pCmdFis, fLBA48) * 512;
5068 rc = PDMBLOCKTXDIR_FROM_DEVICE;
5069 break;
5070 }
5071 case ATA_WRITE_DMA_EXT:
5072 fLBA48 = true;
5073 case ATA_WRITE_DMA:
5074 {
5075 pAhciPortTaskState->cbTransfer = ahciGetNSectors(pCmdFis, fLBA48) * 512;
5076 pAhciPortTaskState->uOffset = ahciGetSector(pAhciPort, pCmdFis, fLBA48) * 512;
5077 rc = PDMBLOCKTXDIR_TO_DEVICE;
5078 break;
5079 }
5080 case ATA_READ_FPDMA_QUEUED:
5081 {
5082 pAhciPortTaskState->cbTransfer = ahciGetNSectorsQueued(pCmdFis) * 512;
5083 pAhciPortTaskState->uOffset = ahciGetSectorQueued(pCmdFis) * 512;
5084 rc = PDMBLOCKTXDIR_FROM_DEVICE;
5085 break;
5086 }
5087 case ATA_WRITE_FPDMA_QUEUED:
5088 {
5089 pAhciPortTaskState->cbTransfer = ahciGetNSectorsQueued(pCmdFis) * 512;
5090 pAhciPortTaskState->uOffset = ahciGetSectorQueued(pCmdFis) * 512;
5091 rc = PDMBLOCKTXDIR_TO_DEVICE;
5092 break;
5093 }
5094 /* All not implemented commands go below. */
5095 case ATA_SECURITY_FREEZE_LOCK:
5096 case ATA_SMART:
5097 case ATA_NV_CACHE:
5098 case ATA_SLEEP: /* Powermanagement not supported. */
5099 pAhciPortTaskState->uATARegError = ABRT_ERR;
5100 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_ERR;
5101 break;
5102 default: /* For debugging purposes. */
5103 AssertMsgFailed(("Unknown command issued\n"));
5104 pAhciPortTaskState->uATARegError = ABRT_ERR;
5105 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_ERR;
5106 }
5107
5108 return rc;
5109}
5110
5111/**
5112 * Retrieve a command FIS from guest memory.
5113 *
5114 * @returns nothing
5115 * @param pAhciPortTaskState The state of the actual task.
5116 */
5117static void ahciPortTaskGetCommandFis(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState)
5118{
5119 RTGCPHYS GCPhysAddrCmdTbl;
5120
5121 AssertMsg(pAhciPort->GCPhysAddrClb && pAhciPort->GCPhysAddrFb, ("%s: GCPhysAddrClb and/or GCPhysAddrFb are 0\n", __FUNCTION__));
5122
5123 /*
5124 * First we are reading the command header pointed to by regCLB.
5125 * From this we get the address of the command table which we are reading too.
5126 * We can process the Command FIS afterwards.
5127 */
5128 pAhciPortTaskState->GCPhysCmdHdrAddr = pAhciPort->GCPhysAddrClb + pAhciPortTaskState->uTag * sizeof(CmdHdr);
5129 LogFlow(("%s: PDMDevHlpPhysRead GCPhysAddrCmdLst=%RGp cbCmdHdr=%u\n", __FUNCTION__,
5130 pAhciPortTaskState->GCPhysCmdHdrAddr, sizeof(CmdHdr)));
5131 PDMDevHlpPhysRead(pAhciPort->CTX_SUFF(pDevIns), pAhciPortTaskState->GCPhysCmdHdrAddr, &pAhciPortTaskState->cmdHdr, sizeof(CmdHdr));
5132
5133#ifdef DEBUG
5134 /* Print some infos about the command header. */
5135 ahciDumpCmdHdrInfo(pAhciPort, &pAhciPortTaskState->cmdHdr);
5136#endif
5137
5138 GCPhysAddrCmdTbl = AHCI_RTGCPHYS_FROM_U32(pAhciPortTaskState->cmdHdr.u32CmdTblAddrUp, pAhciPortTaskState->cmdHdr.u32CmdTblAddr);
5139
5140 AssertMsg((pAhciPortTaskState->cmdHdr.u32DescInf & AHCI_CMDHDR_CFL_MASK) * sizeof(uint32_t) == AHCI_CMDFIS_TYPE_H2D_SIZE,
5141 ("This is not a command FIS!!\n"));
5142
5143 /* Read the command Fis. */
5144 LogFlow(("%s: PDMDevHlpPhysRead GCPhysAddrCmdTbl=%RGp cbCmdFis=%u\n", __FUNCTION__, GCPhysAddrCmdTbl, AHCI_CMDFIS_TYPE_H2D_SIZE));
5145 PDMDevHlpPhysRead(pAhciPort->CTX_SUFF(pDevIns), GCPhysAddrCmdTbl, &pAhciPortTaskState->cmdFis[0], AHCI_CMDFIS_TYPE_H2D_SIZE);
5146
5147 /* Set transfer direction. */
5148 pAhciPortTaskState->uTxDir = (pAhciPortTaskState->cmdHdr.u32DescInf & AHCI_CMDHDR_W) ? PDMBLOCKTXDIR_TO_DEVICE : PDMBLOCKTXDIR_FROM_DEVICE;
5149
5150 /* If this is an ATAPI command read the atapi command. */
5151 if (pAhciPortTaskState->cmdHdr.u32DescInf & AHCI_CMDHDR_A)
5152 {
5153 GCPhysAddrCmdTbl += AHCI_CMDHDR_ACMD_OFFSET;
5154 PDMDevHlpPhysRead(pAhciPort->CTX_SUFF(pDevIns), GCPhysAddrCmdTbl, &pAhciPortTaskState->aATAPICmd[0], ATAPI_PACKET_SIZE);
5155 }
5156
5157 /* We "received" the FIS. Clear the BSY bit in regTFD. */
5158 if ((pAhciPortTaskState->cmdHdr.u32DescInf & AHCI_CMDHDR_C) && (pAhciPortTaskState->fQueued))
5159 {
5160 /*
5161 * We need to send a FIS which clears the busy bit if this is a queued command so that the guest can queue other commands.
5162 * but this FIS does not assert an interrupt
5163 */
5164 ahciSendD2HFis(pAhciPort, pAhciPortTaskState, pAhciPortTaskState->cmdFis, false);
5165 pAhciPort->regTFD &= ~AHCI_PORT_TFD_BSY;
5166 }
5167
5168#ifdef DEBUG
5169 /* Print some infos about the FIS. */
5170 ahciDumpFisInfo(pAhciPort, &pAhciPortTaskState->cmdFis[0]);
5171
5172 /* Print the PRDT */
5173 RTGCPHYS GCPhysAddrPRDTLEntryStart = AHCI_RTGCPHYS_FROM_U32(pAhciPortTaskState->cmdHdr.u32CmdTblAddrUp, pAhciPortTaskState->cmdHdr.u32CmdTblAddr) + AHCI_CMDHDR_PRDT_OFFSET;
5174
5175 ahciLog(("PRDT address %RGp number of entries %u\n", GCPhysAddrPRDTLEntryStart, AHCI_CMDHDR_PRDTL_ENTRIES(pAhciPortTaskState->cmdHdr.u32DescInf)));
5176
5177 for (unsigned i = 0; i < AHCI_CMDHDR_PRDTL_ENTRIES(pAhciPortTaskState->cmdHdr.u32DescInf); i++)
5178 {
5179 SGLEntry SGEntry;
5180
5181 ahciLog(("Entry %u at address %RGp\n", i, GCPhysAddrPRDTLEntryStart));
5182 PDMDevHlpPhysRead(pAhciPort->CTX_SUFF(pDevIns), GCPhysAddrPRDTLEntryStart, &SGEntry, sizeof(SGLEntry));
5183
5184 RTGCPHYS GCPhysDataAddr = AHCI_RTGCPHYS_FROM_U32(SGEntry.u32DBAUp, SGEntry.u32DBA);
5185 ahciLog(("GCPhysAddr=%RGp Size=%u\n", GCPhysDataAddr, SGEntry.u32DescInf & SGLENTRY_DESCINF_DBC));
5186
5187 GCPhysAddrPRDTLEntryStart += sizeof(SGLEntry);
5188 }
5189#endif
5190}
5191
5192/**
5193 * Transmit queue consumer
5194 * Queue a new async task.
5195 *
5196 * @returns Success indicator.
5197 * If false the item will not be removed and the flushing will stop.
5198 * @param pDevIns The device instance.
5199 * @param pItem The item to consume. Upon return this item will be freed.
5200 */
5201static DECLCALLBACK(bool) ahciNotifyQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
5202{
5203 PDEVPORTNOTIFIERQUEUEITEM pNotifierItem = (PDEVPORTNOTIFIERQUEUEITEM)pItem;
5204 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
5205 PAHCIPort pAhciPort = &pAhci->ahciPort[pNotifierItem->iPort];
5206 int rc = VINF_SUCCESS;
5207
5208 if (!pAhciPort->fAsyncInterface)
5209 {
5210 ahciLog(("%s: Got notification from GC\n", __FUNCTION__));
5211 /* Notify the async IO thread. */
5212 rc = RTSemEventSignal(pAhciPort->AsyncIORequestSem);
5213 AssertRC(rc);
5214 }
5215 else
5216 {
5217 int iTxDir;
5218 PAHCIPORTTASKSTATE pAhciPortTaskState;
5219
5220 ahciLog(("%s: Processing command at slot %d\n", __FUNCTION__, pNotifierItem->iTask));
5221
5222 /* Check if there is already an allocated task struct in the cache.
5223 * Allocate a new task otherwise.
5224 */
5225 if (!pAhciPort->aCachedTasks[pNotifierItem->iTask])
5226 {
5227 pAhciPortTaskState = (PAHCIPORTTASKSTATE)RTMemAllocZ(sizeof(AHCIPORTTASKSTATE));
5228 AssertMsg(pAhciPortTaskState, ("%s: Cannot allocate task state memory!\n"));
5229 }
5230 else
5231 {
5232 pAhciPortTaskState = pAhciPort->aCachedTasks[pNotifierItem->iTask];
5233 }
5234
5235 /** Set current command slot */
5236 pAhciPortTaskState->uTag = pNotifierItem->iTask;
5237 pAhciPort->regCMD |= (AHCI_PORT_CMD_CCS_SHIFT(pAhciPortTaskState->uTag));
5238
5239 ahciPortTaskGetCommandFis(pAhciPort, pAhciPortTaskState);
5240
5241 /* Mark the task as processed by the HBA if this is a queued task so that it doesn't occur in the CI register anymore. */
5242 if (pNotifierItem->fQueued)
5243 {
5244 pAhciPortTaskState->fQueued = true;
5245 ASMAtomicOrU32(&pAhciPort->u32TasksFinished, (1 << pAhciPortTaskState->uTag));
5246 }
5247 else
5248 pAhciPortTaskState->fQueued = false;
5249
5250 if (!(pAhciPortTaskState->cmdFis[AHCI_CMDFIS_BITS] & AHCI_CMDFIS_C))
5251 {
5252 /* If the reset bit is set put the device into reset state. */
5253 if (pAhciPortTaskState->cmdFis[AHCI_CMDFIS_CTL] & AHCI_CMDFIS_CTL_SRST)
5254 {
5255 ahciLog(("%s: Setting device into reset state\n", __FUNCTION__));
5256 pAhciPort->fResetDevice = true;
5257 ahciSendD2HFis(pAhciPort, pAhciPortTaskState, pAhciPortTaskState->cmdFis, true);
5258 pAhciPort->aCachedTasks[pNotifierItem->iTask] = pAhciPortTaskState;
5259 return true;
5260 }
5261 else if (pAhciPort->fResetDevice) /* The bit is not set and we are in a reset state. */
5262 {
5263 ahciFinishStorageDeviceReset(pAhciPort, pAhciPortTaskState);
5264 pAhciPort->aCachedTasks[pNotifierItem->iTask] = pAhciPortTaskState;
5265 return true;
5266 }
5267 else /* We are not in a reset state update the control registers. */
5268 {
5269 AssertMsgFailed(("%s: Update the control register\n", __FUNCTION__));
5270 }
5271 }
5272
5273 iTxDir = ahciProcessCmd(pAhciPort, pAhciPortTaskState, pAhciPortTaskState->cmdFis);
5274
5275 if (iTxDir != PDMBLOCKTXDIR_NONE)
5276 {
5277 if (pAhciPortTaskState->fQueued)
5278 {
5279 ahciLog(("%s: Before increment uActTasksActive=%u\n", __FUNCTION__, pAhciPort->uActTasksActive));
5280 ASMAtomicIncU32(&pAhciPort->uActTasksActive);
5281 ahciLog(("%s: After increment uActTasksActive=%u\n", __FUNCTION__, pAhciPort->uActTasksActive));
5282 }
5283
5284 STAM_REL_COUNTER_INC(&pAhciPort->StatDMA);
5285
5286 rc = ahciScatterGatherListCreate(pAhciPort, pAhciPortTaskState, (iTxDir == PDMBLOCKTXDIR_FROM_DEVICE) ? false : true);
5287 if (RT_FAILURE(rc))
5288 AssertMsgFailed(("%s: Failed to process command %Rrc\n", __FUNCTION__, rc));
5289
5290 if (iTxDir == PDMBLOCKTXDIR_FROM_DEVICE)
5291 {
5292 pAhciPort->Led.Asserted.s.fReading = pAhciPort->Led.Actual.s.fReading = 1;
5293 rc = pAhciPort->pDrvBlockAsync->pfnStartRead(pAhciPort->pDrvBlockAsync, pAhciPortTaskState->uOffset,
5294 pAhciPortTaskState->pSGListHead, pAhciPortTaskState->cSGListUsed,
5295 pAhciPortTaskState->cbTransfer,
5296 pAhciPortTaskState);
5297 }
5298 else
5299 {
5300 pAhciPort->Led.Asserted.s.fWriting = pAhciPort->Led.Actual.s.fWriting = 1;
5301 rc = pAhciPort->pDrvBlockAsync->pfnStartWrite(pAhciPort->pDrvBlockAsync, pAhciPortTaskState->uOffset,
5302 pAhciPortTaskState->pSGListHead, pAhciPortTaskState->cSGListUsed,
5303 pAhciPortTaskState->cbTransfer,
5304 pAhciPortTaskState);
5305 }
5306 if (rc == VINF_VD_ASYNC_IO_FINISHED)
5307 rc = ahciTransferComplete(pAhciPort, pAhciPortTaskState);
5308
5309 if (RT_FAILURE(rc))
5310 AssertMsgFailed(("%s: Failed to enqueue command %Rrc\n", __FUNCTION__, rc));
5311 }
5312 else
5313 {
5314 /* There is nothing left to do. Notify the guest. */
5315 ahciSendD2HFis(pAhciPort, pAhciPortTaskState, &pAhciPortTaskState->cmdFis[0], true);
5316 /* Add the task to the cache. */
5317 pAhciPort->aCachedTasks[pAhciPortTaskState->uTag] = pAhciPortTaskState;
5318 }
5319 }
5320
5321 return true;
5322}
5323
5324/* The async IO thread for one port. */
5325static DECLCALLBACK(int) ahciAsyncIOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5326{
5327 PAHCIPort pAhciPort = (PAHCIPort)pThread->pvUser;
5328 PAHCI pAhci = pAhciPort->CTX_SUFF(pAhci);
5329 PAHCIPORTTASKSTATE pAhciPortTaskState;
5330 int rc = VINF_SUCCESS;
5331 uint64_t u64StartTime = 0;
5332 uint64_t u64StopTime = 0;
5333 uint32_t uIORequestsProcessed = 0;
5334 uint32_t uIOsPerSec = 0;
5335
5336 ahciLog(("%s: Port %d entering async IO loop.\n", __FUNCTION__, pAhciPort->iLUN));
5337
5338 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
5339 return VINF_SUCCESS;
5340
5341 /* We use only one task structure. */
5342 pAhciPortTaskState = (PAHCIPORTTASKSTATE)RTMemAllocZ(sizeof(AHCIPORTTASKSTATE));
5343 if (!pAhciPortTaskState)
5344 {
5345 AssertMsgFailed(("Failed to allocate task state memory\n"));
5346 return VERR_NO_MEMORY;
5347 }
5348
5349 while(pThread->enmState == PDMTHREADSTATE_RUNNING)
5350 {
5351 uint32_t uQueuedTasksFinished = 0;
5352
5353 /* New run to get number of I/O requests per second?. */
5354 if (!u64StartTime)
5355 u64StartTime = RTTimeMilliTS();
5356
5357 ASMAtomicXchgBool(&pAhciPort->fAsyncIOThreadIdle, true);
5358 if (pAhci->fSignalIdle)
5359 PDMDevHlpAsyncNotificationCompleted(pAhciPort->pDevInsR3);
5360
5361 rc = RTSemEventWait(pAhciPort->AsyncIORequestSem, 1000);
5362 if (rc == VERR_TIMEOUT)
5363 {
5364 /* No I/O requests inbetween. Reset statistics and wait again. */
5365 pAhciPort->StatIORequestsPerSecond.c = 0;
5366 rc = RTSemEventWait(pAhciPort->AsyncIORequestSem, RT_INDEFINITE_WAIT);
5367 }
5368
5369 if (RT_FAILURE(rc) || (pThread->enmState != PDMTHREADSTATE_RUNNING))
5370 break;
5371
5372 AssertMsg(pAhciPort->pDrvBase, ("I/O thread without attached device?!\n"));
5373
5374 ASMAtomicXchgBool(&pAhciPort->fAsyncIOThreadIdle, false);
5375
5376 /*
5377 * To maximize the throughput of the controller we try to minimize the
5378 * number of world switches during interrupts by grouping as many
5379 * I/O requests together as possible.
5380 * On the other side we want to get minimal latency if the I/O load is low.
5381 * Thatswhy the number of I/O requests per second is measured and if it is over
5382 * a threshold the thread waits for other requests from the guest.
5383 */
5384 if (uIOsPerSec >= pAhci->cHighIOThreshold)
5385 {
5386 uint8_t uActWritePosPrev = pAhciPort->uActWritePos;
5387
5388 Log(("%s: Waiting for more tasks to get queued\n", __FUNCTION__));
5389
5390 do
5391 {
5392 /* Sleep some time. */
5393 RTThreadSleep(pAhci->cMillisToSleep);
5394 /* Check if we got some new requests inbetween. */
5395 if (uActWritePosPrev != pAhciPort->uActWritePos)
5396 {
5397 uActWritePosPrev = pAhciPort->uActWritePos;
5398 /*
5399 * Check if the queue is full. If that is the case
5400 * there is no point waiting another round.
5401 */
5402 if ( ( (pAhciPort->uActReadPos < uActWritePosPrev)
5403 && (uActWritePosPrev - pAhciPort->uActReadPos) == AHCI_NR_COMMAND_SLOTS)
5404 || ( (pAhciPort->uActReadPos > uActWritePosPrev)
5405 && (RT_ELEMENTS(pAhciPort->ahciIOTasks) - pAhciPort->uActReadPos + uActWritePosPrev) == AHCI_NR_COMMAND_SLOTS) )
5406 {
5407 Log(("%s: Queue full -> leaving\n", __FUNCTION__));
5408 break;
5409 }
5410 Log(("%s: Another round\n", __FUNCTION__));
5411 }
5412 else /* No change break out of the loop. */
5413 {
5414#ifdef DEBUG
5415 uint8_t uQueuedTasks;
5416 if (pAhciPort->uActReadPos < uActWritePosPrev)
5417 uQueuedTasks = uActWritePosPrev - pAhciPort->uActReadPos;
5418 else
5419 uQueuedTasks = RT_ELEMENTS(pAhciPort->ahciIOTasks) - pAhciPort->uActReadPos + uActWritePosPrev;
5420
5421 Log(("%s: %u Tasks are queued\n", __FUNCTION__, uQueuedTasks));
5422#endif
5423 break;
5424 }
5425 } while (true);
5426 }
5427
5428 ASMAtomicXchgBool(&pAhciPort->fNotificationSend, false);
5429
5430 uint32_t cTasksToProcess = ASMAtomicXchgU32(&pAhciPort->uActTasksActive, 0);
5431
5432 ahciLog(("%s: Processing %u requests\n", __FUNCTION__, cTasksToProcess));
5433
5434 /* Process commands. */
5435 while ( (cTasksToProcess > 0)
5436 && RT_LIKELY(!pAhciPort->fPortReset))
5437 {
5438 int iTxDir;
5439 uint8_t uActTag;
5440
5441 STAM_PROFILE_START(&pAhciPort->StatProfileProcessTime, a);
5442
5443 ahciLog(("%s: uActWritePos=%u\n", __FUNCTION__, pAhciPort->uActWritePos));
5444 ahciLog(("%s: Before uActReadPos=%u\n", __FUNCTION__, pAhciPort->uActReadPos));
5445
5446 pAhciPortTaskState->uATARegStatus = 0;
5447 pAhciPortTaskState->uATARegError = 0;
5448 uActTag = pAhciPort->ahciIOTasks[pAhciPort->uActReadPos];
5449
5450 pAhciPortTaskState->uTag = AHCI_TASK_GET_TAG(uActTag);
5451 AssertMsg(pAhciPortTaskState->uTag < AHCI_NR_COMMAND_SLOTS, ("%s: Invalid Tag number!!\n", __FUNCTION__));
5452
5453 /** Set current command slot */
5454 pAhciPort->regCMD |= (AHCI_PORT_CMD_CCS_SHIFT(pAhciPortTaskState->uTag));
5455
5456 /* Mark the task as processed by the HBA if this is a queued task so that it doesn't occur in the CI register anymore. */
5457 if (AHCI_TASK_IS_QUEUED(uActTag))
5458 {
5459 pAhciPortTaskState->fQueued = true;
5460 ASMAtomicOrU32(&pAhciPort->u32TasksFinished, (1 << pAhciPortTaskState->uTag));
5461 }
5462 else
5463 {
5464 pAhciPortTaskState->fQueued = false;
5465 }
5466
5467 ahciPortTaskGetCommandFis(pAhciPort, pAhciPortTaskState);
5468
5469 ahciLog(("%s: Got command at slot %d\n", __FUNCTION__, pAhciPortTaskState->uTag));
5470
5471 if (!(pAhciPortTaskState->cmdFis[AHCI_CMDFIS_BITS] & AHCI_CMDFIS_C))
5472 {
5473 /* If the reset bit is set put the device into reset state. */
5474 if (pAhciPortTaskState->cmdFis[AHCI_CMDFIS_CTL] & AHCI_CMDFIS_CTL_SRST)
5475 {
5476 ahciLog(("%s: Setting device into reset state\n", __FUNCTION__));
5477 pAhciPort->fResetDevice = true;
5478 ahciSendD2HFis(pAhciPort, pAhciPortTaskState, &pAhciPortTaskState->cmdFis[0], true);
5479 }
5480 else if (pAhciPort->fResetDevice) /* The bit is not set and we are in a reset state. */
5481 {
5482 ahciFinishStorageDeviceReset(pAhciPort, pAhciPortTaskState);
5483 }
5484 /* TODO: We are not in a reset state update the control registers. */
5485 }
5486 else
5487 {
5488 iTxDir = ahciProcessCmd(pAhciPort, pAhciPortTaskState, &pAhciPortTaskState->cmdFis[0]);
5489
5490 if (iTxDir != PDMBLOCKTXDIR_NONE)
5491 {
5492 uint64_t uOffset;
5493 size_t cbTransfer;
5494 PPDMDATASEG pSegCurr;
5495 PAHCIPORTTASKSTATESGENTRY pSGInfoCurr;
5496
5497 rc = ahciScatterGatherListCreate(pAhciPort, pAhciPortTaskState, (iTxDir == PDMBLOCKTXDIR_FROM_DEVICE) ? false : true);
5498 if (RT_FAILURE(rc))
5499 AssertMsgFailed(("%s: Failed to get number of list elments %Rrc\n", __FUNCTION__, rc));
5500
5501 STAM_REL_COUNTER_INC(&pAhciPort->StatDMA);
5502
5503 /* Initialize all values. */
5504 uOffset = pAhciPortTaskState->uOffset;
5505 cbTransfer = pAhciPortTaskState->cbTransfer;
5506 pSegCurr = &pAhciPortTaskState->pSGListHead[0];
5507 pSGInfoCurr = pAhciPortTaskState->paSGEntries;
5508
5509 STAM_PROFILE_START(&pAhciPort->StatProfileReadWrite, b);
5510
5511 while (cbTransfer)
5512 {
5513 size_t cbProcess = (cbTransfer < pSegCurr->cbSeg) ? cbTransfer : pSegCurr->cbSeg;
5514
5515 AssertMsg(!(pSegCurr->cbSeg % 512), ("Buffer is not sector aligned cbSeg=%d\n", pSegCurr->cbSeg));
5516 AssertMsg(!(uOffset % 512), ("Offset is not sector aligned %llu\n", uOffset));
5517 AssertMsg(!(cbProcess % 512), ("Number of bytes to process is not sector aligned %lu\n", cbProcess));
5518
5519 if (iTxDir == PDMBLOCKTXDIR_FROM_DEVICE)
5520 {
5521 pAhciPort->Led.Asserted.s.fReading = pAhciPort->Led.Actual.s.fReading = 1;
5522 rc = pAhciPort->pDrvBlock->pfnRead(pAhciPort->pDrvBlock, uOffset,
5523 pSegCurr->pvSeg, cbProcess);
5524 pAhciPort->Led.Actual.s.fReading = 0;
5525 if (RT_FAILURE(rc))
5526 AssertMsgFailed(("%s: Failed to read data %Rrc\n", __FUNCTION__, rc));
5527
5528 STAM_REL_COUNTER_ADD(&pAhciPort->StatBytesRead, cbProcess);
5529 }
5530 else
5531 {
5532 pAhciPort->Led.Asserted.s.fWriting = pAhciPort->Led.Actual.s.fWriting = 1;
5533 rc = pAhciPort->pDrvBlock->pfnWrite(pAhciPort->pDrvBlock, uOffset,
5534 pSegCurr->pvSeg, cbProcess);
5535 pAhciPort->Led.Actual.s.fWriting = 0;
5536 if (RT_FAILURE(rc))
5537 AssertMsgFailed(("%s: Failed to write data %Rrc\n", __FUNCTION__, rc));
5538
5539 STAM_REL_COUNTER_ADD(&pAhciPort->StatBytesWritten, cbProcess);
5540 }
5541
5542 /* Go to the next entry. */
5543 uOffset += cbProcess;
5544 cbTransfer -= cbProcess;
5545 pSegCurr++;
5546 pSGInfoCurr++;
5547 }
5548
5549 STAM_PROFILE_STOP(&pAhciPort->StatProfileReadWrite, b);
5550
5551 /* Cleanup. */
5552 rc = ahciScatterGatherListDestroy(pAhciPort, pAhciPortTaskState);
5553 if (RT_FAILURE(rc))
5554 AssertMsgFailed(("Destroying task list failed rc=%Rrc\n", rc));
5555
5556 if (RT_LIKELY(!pAhciPort->fPortReset))
5557 {
5558 pAhciPortTaskState->cmdHdr.u32PRDBC = pAhciPortTaskState->cbTransfer;
5559 pAhciPortTaskState->uATARegError = 0;
5560 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
5561 /* Write updated command header into memory of the guest. */
5562 PDMDevHlpPhysWrite(pAhciPort->CTX_SUFF(pDevIns), pAhciPortTaskState->GCPhysCmdHdrAddr,
5563 &pAhciPortTaskState->cmdHdr, sizeof(CmdHdr));
5564
5565 if (pAhciPortTaskState->fQueued)
5566 uQueuedTasksFinished |= (1 << pAhciPortTaskState->uTag);
5567 else
5568 {
5569 /* Task is not queued send D2H FIS */
5570 ahciSendD2HFis(pAhciPort, pAhciPortTaskState, &pAhciPortTaskState->cmdFis[0], true);
5571 }
5572
5573 uIORequestsProcessed++;
5574 }
5575 }
5576 else
5577 {
5578 /* Nothing left to do. Notify the guest. */
5579 ahciSendD2HFis(pAhciPort, pAhciPortTaskState, &pAhciPortTaskState->cmdFis[0], true);
5580 }
5581
5582 STAM_PROFILE_STOP(&pAhciPort->StatProfileProcessTime, a);
5583 }
5584
5585#ifdef DEBUG
5586 /* Be paranoid. */
5587 memset(&pAhciPortTaskState->cmdHdr, 0, sizeof(CmdHdr));
5588 memset(&pAhciPortTaskState->cmdFis, 0, AHCI_CMDFIS_TYPE_H2D_SIZE);
5589 pAhciPortTaskState->GCPhysCmdHdrAddr = 0;
5590 pAhciPortTaskState->uOffset = 0;
5591 pAhciPortTaskState->cbTransfer = 0;
5592 /* Make the port number invalid making it easier to track down bugs. */
5593 pAhciPort->ahciIOTasks[pAhciPort->uActReadPos] = 0xff;
5594#endif
5595
5596 pAhciPort->uActReadPos++;
5597 pAhciPort->uActReadPos %= RT_ELEMENTS(pAhciPort->ahciIOTasks);
5598 ahciLog(("%s: After uActReadPos=%u\n", __FUNCTION__, pAhciPort->uActReadPos));
5599 cTasksToProcess--;
5600 if (!cTasksToProcess)
5601 cTasksToProcess = ASMAtomicXchgU32(&pAhciPort->uActTasksActive, 0);
5602 }
5603
5604 if (uQueuedTasksFinished && RT_LIKELY(!pAhciPort->fPortReset))
5605 ahciSendSDBFis(pAhciPort, uQueuedTasksFinished, pAhciPortTaskState, true);
5606
5607 uQueuedTasksFinished = 0;
5608
5609 u64StopTime = RTTimeMilliTS();
5610 /* Check if one second has passed. */
5611 if (u64StopTime - u64StartTime >= 1000)
5612 {
5613 /* Calculate number of I/O requests per second. */
5614 uIOsPerSec = uIORequestsProcessed / ((u64StopTime - u64StartTime) / 1000);
5615 ahciLog(("%s: Processed %u requests in %llu ms -> %u requests/s\n", __FUNCTION__, uIORequestsProcessed, u64StopTime - u64StartTime, uIOsPerSec));
5616 u64StartTime = 0;
5617 uIORequestsProcessed = 0;
5618 /* For the release statistics. There is no macro to set the counter to a specific value. */
5619 pAhciPort->StatIORequestsPerSecond.c = uIOsPerSec;
5620 }
5621 }
5622
5623 if (pAhci->fSignalIdle)
5624 PDMDevHlpAsyncNotificationCompleted(pAhciPort->pDevInsR3);
5625
5626 /* Free task state memory */
5627 if (pAhciPortTaskState->pSGListHead)
5628 RTMemFree(pAhciPortTaskState->pSGListHead);
5629 if (pAhciPortTaskState->paSGEntries)
5630 RTMemFree(pAhciPortTaskState->paSGEntries);
5631 if (pAhciPortTaskState->pvBufferUnaligned)
5632 RTMemFree(pAhciPortTaskState->pvBufferUnaligned);
5633 RTMemFree(pAhciPortTaskState);
5634
5635 ahciLog(("%s: Port %d async IO thread exiting rc=%Rrc\n", __FUNCTION__, pAhciPort->iLUN, rc));
5636 return rc;
5637}
5638
5639/**
5640 * Unblock the async I/O thread so it can respond to a state change.
5641 *
5642 * @returns VBox status code.
5643 * @param pDevIns The pcnet device instance.
5644 * @param pThread The send thread.
5645 */
5646static DECLCALLBACK(int) ahciAsyncIOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5647{
5648 PAHCIPort pAhciPort = (PAHCIPort)pThread->pvUser;
5649 return RTSemEventSignal(pAhciPort->AsyncIORequestSem);
5650}
5651
5652/**
5653 * Called when a media is mounted.
5654 *
5655 * @param pInterface Pointer to the interface structure containing the called function pointer.
5656 */
5657static DECLCALLBACK(void) ahciMountNotify(PPDMIMOUNTNOTIFY pInterface)
5658{
5659 PAHCIPort pAhciPort = PDMIMOUNTNOTIFY_2_PAHCIPORT(pInterface);
5660 Log(("%s: changing LUN#%d\n", __FUNCTION__, pAhciPort->iLUN));
5661
5662 /* Ignore the call if we're called while being attached. */
5663 if (!pAhciPort->pDrvBlock)
5664 return;
5665
5666 pAhciPort->cTotalSectors = pAhciPort->pDrvBlock->pfnGetSize(pAhciPort->pDrvBlock) / 512;
5667
5668 /*
5669 * Initialize registers
5670 */
5671 pAhciPort->regCMD |= AHCI_PORT_CMD_CPS;
5672 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_CPDS | AHCI_PORT_IS_PRCS);
5673 pAhciPort->regSERR |= AHCI_PORT_SERR_N;
5674 if (pAhciPort->regIE & AHCI_PORT_IE_CPDE)
5675 ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN);
5676}
5677
5678/**
5679 * Called when a media is unmounted
5680 * @param pInterface Pointer to the interface structure containing the called function pointer.
5681 */
5682static DECLCALLBACK(void) ahciUnmountNotify(PPDMIMOUNTNOTIFY pInterface)
5683{
5684 PAHCIPort pAhciPort = PDMIMOUNTNOTIFY_2_PAHCIPORT(pInterface);
5685 Log(("%s:\n", __FUNCTION__));
5686
5687 pAhciPort->cTotalSectors = 0;
5688
5689 /*
5690 * Inform the guest about the removed device.
5691 */
5692 pAhciPort->regSSTS = 0;
5693 pAhciPort->regCMD &= ~AHCI_PORT_CMD_CPS;
5694 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_CPDS | AHCI_PORT_IS_PRCS);
5695 pAhciPort->regSERR |= AHCI_PORT_SERR_N;
5696 if (pAhciPort->regIE & AHCI_PORT_IE_CPDE)
5697 ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN);
5698}
5699
5700/* -=-=-=-=- Helper -=-=-=-=- */
5701
5702/**
5703 * Checks if all asynchronous I/O is finished, both AHCI and IDE.
5704 *
5705 * Used by ahciR3Reset, ahciR3Suspend and ahciR3PowerOff. ahciR3SavePrep makes
5706 * use of it in strict builds (which is why it's up here).
5707 *
5708 * @returns true if quiesced, false if busy.
5709 * @param pDevIns The device instance.
5710 */
5711static bool ahciR3AllAsyncIOIsFinished(PPDMDEVINS pDevIns)
5712{
5713 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
5714
5715 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->ahciPort); i++)
5716 {
5717 PAHCIPort pThisPort = &pThis->ahciPort[i];
5718 if (pThisPort->pDrvBase)
5719 {
5720 bool fFinished;
5721 if (pThisPort->fAsyncInterface)
5722 fFinished = (pThisPort->uActTasksActive == 0);
5723 else
5724 fFinished = ((pThisPort->uActTasksActive == 0) && (pThisPort->fAsyncIOThreadIdle));
5725 if (!fFinished)
5726 return false;
5727 }
5728 }
5729
5730 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
5731 if (!ataControllerIsIdle(&pThis->aCts[i]))
5732 return false;
5733
5734 return true;
5735}
5736
5737/* -=-=-=-=- Saved State -=-=-=-=- */
5738
5739/**
5740 * @copydoc FNDEVSSMSAVEPREP
5741 */
5742static DECLCALLBACK(int) ahciR3SavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5743{
5744 Assert(ahciR3AllAsyncIOIsFinished(pDevIns));
5745 return VINF_SUCCESS;
5746}
5747
5748/**
5749 * @copydoc FNDEVSSMLOADPREP
5750 */
5751static DECLCALLBACK(int) ahciR3LoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5752{
5753 Assert(ahciR3AllAsyncIOIsFinished(pDevIns));
5754 return VINF_SUCCESS;
5755}
5756
5757/**
5758 * @copydoc FNDEVSSMLIVEEXEC
5759 */
5760static DECLCALLBACK(int) ahciR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
5761{
5762 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
5763
5764 /* config. */
5765 SSMR3PutU32(pSSM, pThis->cPortsImpl);
5766 for (uint32_t i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
5767 {
5768 SSMR3PutBool(pSSM, pThis->ahciPort[i].pDrvBase != NULL);
5769 SSMR3PutStrZ(pSSM, pThis->ahciPort[i].szSerialNumber);
5770 SSMR3PutStrZ(pSSM, pThis->ahciPort[i].szFirmwareRevision);
5771 SSMR3PutStrZ(pSSM, pThis->ahciPort[i].szModelNumber);
5772 }
5773
5774 static const char *s_apszIdeEmuPortNames[4] = { "PrimaryMaster", "PrimarySlave", "SecondaryMaster", "SecondarySlave" };
5775 for (size_t i = 0; i < RT_ELEMENTS(s_apszIdeEmuPortNames); i++)
5776 {
5777 uint32_t iPort;
5778 int rc = CFGMR3QueryU32Def(pDevIns->pCfgHandle, s_apszIdeEmuPortNames[i], &iPort, i);
5779 AssertRCReturn(rc, rc);
5780 SSMR3PutU32(pSSM, iPort);
5781 }
5782
5783 return VINF_SSM_DONT_CALL_AGAIN;
5784}
5785
5786/**
5787 * @copydoc FNDEVSSMSAVEEXEC
5788 */
5789static DECLCALLBACK(int) ahciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5790{
5791 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
5792 uint32_t i;
5793 int rc;
5794
5795 Assert(!pThis->f8ByteMMIO4BytesWrittenSuccessfully);
5796
5797 /* The config */
5798 rc = ahciR3LiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
5799 AssertRCReturn(rc, rc);
5800
5801 /* The main device structure. */
5802 SSMR3PutU32(pSSM, pThis->regHbaCap);
5803 SSMR3PutU32(pSSM, pThis->regHbaCtrl);
5804 SSMR3PutU32(pSSM, pThis->regHbaIs);
5805 SSMR3PutU32(pSSM, pThis->regHbaPi);
5806 SSMR3PutU32(pSSM, pThis->regHbaVs);
5807 SSMR3PutU32(pSSM, pThis->regHbaCccCtl);
5808 SSMR3PutU32(pSSM, pThis->regHbaCccPorts);
5809 SSMR3PutU8(pSSM, pThis->uCccPortNr);
5810 SSMR3PutU64(pSSM, pThis->uCccTimeout);
5811 SSMR3PutU32(pSSM, pThis->uCccNr);
5812 SSMR3PutU32(pSSM, pThis->uCccCurrentNr);
5813 SSMR3PutU32(pSSM, pThis->u32PortsInterrupted);
5814 SSMR3PutBool(pSSM, pThis->fReset);
5815 SSMR3PutBool(pSSM, pThis->f64BitAddr);
5816 SSMR3PutBool(pSSM, pThis->fR0Enabled);
5817 SSMR3PutBool(pSSM, pThis->fGCEnabled);
5818
5819 /* Now every port. */
5820 for (i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
5821 {
5822 Assert(pThis->ahciPort[i].uActTasksActive == 0);
5823 SSMR3PutU32(pSSM, pThis->ahciPort[i].regCLB);
5824 SSMR3PutU32(pSSM, pThis->ahciPort[i].regCLBU);
5825 SSMR3PutU32(pSSM, pThis->ahciPort[i].regFB);
5826 SSMR3PutU32(pSSM, pThis->ahciPort[i].regFBU);
5827 SSMR3PutGCPhys(pSSM, pThis->ahciPort[i].GCPhysAddrClb);
5828 SSMR3PutGCPhys(pSSM, pThis->ahciPort[i].GCPhysAddrFb);
5829 SSMR3PutU32(pSSM, pThis->ahciPort[i].regIS);
5830 SSMR3PutU32(pSSM, pThis->ahciPort[i].regIE);
5831 SSMR3PutU32(pSSM, pThis->ahciPort[i].regCMD);
5832 SSMR3PutU32(pSSM, pThis->ahciPort[i].regTFD);
5833 SSMR3PutU32(pSSM, pThis->ahciPort[i].regSIG);
5834 SSMR3PutU32(pSSM, pThis->ahciPort[i].regSSTS);
5835 SSMR3PutU32(pSSM, pThis->ahciPort[i].regSCTL);
5836 SSMR3PutU32(pSSM, pThis->ahciPort[i].regSERR);
5837 SSMR3PutU32(pSSM, pThis->ahciPort[i].regSACT);
5838 SSMR3PutU32(pSSM, pThis->ahciPort[i].regCI);
5839 SSMR3PutU32(pSSM, pThis->ahciPort[i].PCHSGeometry.cCylinders);
5840 SSMR3PutU32(pSSM, pThis->ahciPort[i].PCHSGeometry.cHeads);
5841 SSMR3PutU32(pSSM, pThis->ahciPort[i].PCHSGeometry.cSectors);
5842 SSMR3PutU64(pSSM, pThis->ahciPort[i].cTotalSectors);
5843 SSMR3PutU32(pSSM, pThis->ahciPort[i].cMultSectors);
5844 SSMR3PutU8(pSSM, pThis->ahciPort[i].uATATransferMode);
5845 SSMR3PutBool(pSSM, pThis->ahciPort[i].fResetDevice);
5846
5847 /* No need to save */
5848 SSMR3PutU8(pSSM, pThis->ahciPort[i].uActWritePos);
5849 SSMR3PutU8(pSSM, pThis->ahciPort[i].uActReadPos);
5850 SSMR3PutBool(pSSM, pThis->ahciPort[i].fPoweredOn);
5851 SSMR3PutBool(pSSM, pThis->ahciPort[i].fSpunUp);
5852 SSMR3PutU32(pSSM, pThis->ahciPort[i].u32TasksFinished);
5853 SSMR3PutU32(pSSM, pThis->ahciPort[i].u32QueuedTasksFinished);
5854 }
5855
5856 /* Now the emulated ata controllers. */
5857 for (i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
5858 {
5859 rc = ataControllerSaveExec(&pThis->aCts[i], pSSM);
5860 if (RT_FAILURE(rc))
5861 return rc;
5862 }
5863
5864 return SSMR3PutU32(pSSM, UINT32_MAX); /* sanity/terminator */
5865}
5866
5867/**
5868 * Loads a saved AHCI device state.
5869 *
5870 * @returns VBox status code.
5871 * @param pDevIns The device instance.
5872 * @param pSSM The handle to the saved state.
5873 * @param uVersion The data unit version number.
5874 * @param uPass The data pass.
5875 */
5876static DECLCALLBACK(int) ahciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5877{
5878 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
5879 uint32_t u32;
5880 int rc;
5881
5882 if ( uVersion != AHCI_SAVED_STATE_VERSION
5883 && uVersion != AHCI_SAVED_STATE_VERSION_VBOX_30)
5884 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
5885
5886 /* Verify config. */
5887 if (uVersion > AHCI_SAVED_STATE_VERSION_VBOX_30)
5888 {
5889 rc = SSMR3GetU32(pSSM, &u32);
5890 AssertRCReturn(rc, rc);
5891 if (u32 != pThis->cPortsImpl)
5892 {
5893 LogRel(("AHCI: Config mismatch: cPortsImpl - saved=%u config=%u\n", u32, pThis->cPortsImpl));
5894 if ( u32 < pThis->cPortsImpl
5895 || u32 > AHCI_MAX_NR_PORTS_IMPL)
5896 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: cPortsImpl - saved=%u config=%u"),
5897 u32, pThis->cPortsImpl);
5898 }
5899
5900 for (uint32_t i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
5901 {
5902 bool fInUse;
5903 rc = SSMR3GetBool(pSSM, &fInUse);
5904 AssertRCReturn(rc, rc);
5905 if (fInUse != (pThis->ahciPort[i].pDrvBase != NULL))
5906 return SSMR3SetCfgError(pSSM, RT_SRC_POS,
5907 N_("The %s VM is missing a device on port %u. Please make sure the source and target VMs have compatible storage configurations"),
5908 fInUse ? "target" : "source", i );
5909
5910 char szSerialNumber[AHCI_SERIAL_NUMBER_LENGTH+1];
5911 rc = SSMR3GetStrZ(pSSM, szSerialNumber, sizeof(szSerialNumber));
5912 AssertRCReturn(rc, rc);
5913 if (strcmp(szSerialNumber, pThis->ahciPort[i].szSerialNumber))
5914 LogRel(("AHCI: Port %u config mismatch: Serial number - saved='%s' config='%s'\n",
5915 i, szSerialNumber, pThis->ahciPort[i].szSerialNumber));
5916
5917 char szFirmwareRevision[AHCI_FIRMWARE_REVISION_LENGTH+1];
5918 rc = SSMR3GetStrZ(pSSM, szFirmwareRevision, sizeof(szFirmwareRevision));
5919 AssertRCReturn(rc, rc);
5920 if (strcmp(szFirmwareRevision, pThis->ahciPort[i].szFirmwareRevision))
5921 LogRel(("AHCI: Port %u config mismatch: Firmware revision - saved='%s' config='%s'\n",
5922 i, szFirmwareRevision, pThis->ahciPort[i].szFirmwareRevision));
5923
5924 char szModelNumber[AHCI_MODEL_NUMBER_LENGTH+1];
5925 rc = SSMR3GetStrZ(pSSM, szModelNumber, sizeof(szModelNumber));
5926 AssertRCReturn(rc, rc);
5927 if (strcmp(szModelNumber, pThis->ahciPort[i].szModelNumber))
5928 LogRel(("AHCI: Port %u config mismatch: Model number - saved='%s' config='%s'\n",
5929 i, szModelNumber, pThis->ahciPort[i].szModelNumber));
5930 }
5931
5932 static const char *s_apszIdeEmuPortNames[4] = { "PrimaryMaster", "PrimarySlave", "SecondaryMaster", "SecondarySlave" };
5933 for (size_t i = 0; i < RT_ELEMENTS(s_apszIdeEmuPortNames); i++)
5934 {
5935 uint32_t iPort;
5936 rc = CFGMR3QueryU32Def(pDevIns->pCfgHandle, s_apszIdeEmuPortNames[i], &iPort, i);
5937 AssertRCReturn(rc, rc);
5938
5939 uint32_t iPortSaved;
5940 rc = SSMR3GetU32(pSSM, &iPortSaved);
5941 AssertRCReturn(rc, rc);
5942
5943 if (iPortSaved != iPort)
5944 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("IDE %s config mismatch: saved=%u config=%u"),
5945 s_apszIdeEmuPortNames[i], iPortSaved, iPort);
5946 }
5947 }
5948
5949 if (uPass == SSM_PASS_FINAL)
5950 {
5951 /* Restore data. */
5952
5953 /* The main device structure. */
5954 SSMR3GetU32(pSSM, &pThis->regHbaCap);
5955 SSMR3GetU32(pSSM, &pThis->regHbaCtrl);
5956 SSMR3GetU32(pSSM, &pThis->regHbaIs);
5957 SSMR3GetU32(pSSM, &pThis->regHbaPi);
5958 SSMR3GetU32(pSSM, &pThis->regHbaVs);
5959 SSMR3GetU32(pSSM, &pThis->regHbaCccCtl);
5960 SSMR3GetU32(pSSM, &pThis->regHbaCccPorts);
5961 SSMR3GetU8(pSSM, &pThis->uCccPortNr);
5962 SSMR3GetU64(pSSM, &pThis->uCccTimeout);
5963 SSMR3GetU32(pSSM, &pThis->uCccNr);
5964 SSMR3GetU32(pSSM, &pThis->uCccCurrentNr);
5965
5966 SSMR3GetU32(pSSM, &pThis->u32PortsInterrupted);
5967 SSMR3GetBool(pSSM, &pThis->fReset);
5968 SSMR3GetBool(pSSM, &pThis->f64BitAddr);
5969 SSMR3GetBool(pSSM, &pThis->fR0Enabled);
5970 SSMR3GetBool(pSSM, &pThis->fGCEnabled);
5971
5972 /* Now every port. */
5973 for (uint32_t i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
5974 {
5975 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regCLB);
5976 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regCLBU);
5977 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regFB);
5978 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regFBU);
5979 SSMR3GetGCPhys(pSSM, (RTGCPHYS *)&pThis->ahciPort[i].GCPhysAddrClb);
5980 SSMR3GetGCPhys(pSSM, (RTGCPHYS *)&pThis->ahciPort[i].GCPhysAddrFb);
5981 SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].regIS);
5982 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regIE);
5983 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regCMD);
5984 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regTFD);
5985 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regSIG);
5986 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regSSTS);
5987 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regSCTL);
5988 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regSERR);
5989 SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].regSACT);
5990 SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].regCI);
5991 SSMR3GetU32(pSSM, &pThis->ahciPort[i].PCHSGeometry.cCylinders);
5992 SSMR3GetU32(pSSM, &pThis->ahciPort[i].PCHSGeometry.cHeads);
5993 SSMR3GetU32(pSSM, &pThis->ahciPort[i].PCHSGeometry.cSectors);
5994 SSMR3GetU64(pSSM, &pThis->ahciPort[i].cTotalSectors);
5995 SSMR3GetU32(pSSM, &pThis->ahciPort[i].cMultSectors);
5996 SSMR3GetU8(pSSM, &pThis->ahciPort[i].uATATransferMode);
5997 SSMR3GetBool(pSSM, &pThis->ahciPort[i].fResetDevice);
5998
5999 if (uVersion <= AHCI_SAVED_STATE_VERSION_VBOX_30)
6000 SSMR3Skip(pSSM, AHCI_NR_COMMAND_SLOTS * sizeof(uint8_t)); /* no active data here */
6001
6002 SSMR3GetU8(pSSM, &pThis->ahciPort[i].uActWritePos);
6003 SSMR3GetU8(pSSM, &pThis->ahciPort[i].uActReadPos);
6004 SSMR3GetBool(pSSM, &pThis->ahciPort[i].fPoweredOn);
6005 SSMR3GetBool(pSSM, &pThis->ahciPort[i].fSpunUp);
6006 SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].u32TasksFinished);
6007 SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].u32QueuedTasksFinished);
6008 }
6009
6010 /* Now the emulated ata controllers. */
6011 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
6012 {
6013 rc = ataControllerLoadExec(&pThis->aCts[i], pSSM);
6014 if (RT_FAILURE(rc))
6015 return rc;
6016 }
6017
6018 rc = SSMR3GetU32(pSSM, &u32);
6019 if (RT_FAILURE(rc))
6020 return rc;
6021 AssertMsgReturn(u32 == UINT32_MAX, ("%#x\n", u32), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
6022 }
6023
6024 return VINF_SUCCESS;
6025}
6026
6027/* -=-=-=-=- device PDM interface -=-=-=-=- */
6028
6029static DECLCALLBACK(void) ahciR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
6030{
6031 uint32_t i;
6032 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
6033
6034 pAhci->pDevInsRC += offDelta;
6035 pAhci->pHbaCccTimerRC = TMTimerRCPtr(pAhci->pHbaCccTimerR3);
6036 pAhci->pNotifierQueueRC = PDMQueueRCPtr(pAhci->pNotifierQueueR3);
6037
6038 /* Relocate every port. */
6039 for (i = 0; i < RT_ELEMENTS(pAhci->ahciPort); i++)
6040 {
6041 PAHCIPort pAhciPort = &pAhci->ahciPort[i];
6042 pAhciPort->pAhciRC += offDelta;
6043 pAhciPort->pDevInsRC += offDelta;
6044 }
6045
6046 /* Relocate emulated ATA controllers. */
6047 for (i = 0; i < RT_ELEMENTS(pAhci->aCts); i++)
6048 ataControllerRelocate(&pAhci->aCts[i], offDelta);
6049}
6050
6051/**
6052 * Destroy a driver instance.
6053 *
6054 * Most VM resources are freed by the VM. This callback is provided so that any non-VM
6055 * resources can be freed correctly.
6056 *
6057 * @param pDevIns The device instance data.
6058 */
6059static DECLCALLBACK(int) ahciR3Destruct(PPDMDEVINS pDevIns)
6060{
6061 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
6062 int rc = VINF_SUCCESS;
6063 unsigned iActPort = 0;
6064 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
6065
6066 /*
6067 * At this point the async I/O thread is suspended and will not enter
6068 * this module again. So, no coordination is needed here and PDM
6069 * will take care of terminating and cleaning up the thread.
6070 */
6071 if (PDMCritSectIsInitialized(&pAhci->lock))
6072 {
6073 TMR3TimerDestroy(pAhci->CTX_SUFF(pHbaCccTimer));
6074
6075 Log(("%s: Destruct every port\n", __FUNCTION__));
6076 for (iActPort = 0; iActPort < pAhci->cPortsImpl; iActPort++)
6077 {
6078 PAHCIPort pAhciPort = &pAhci->ahciPort[iActPort];
6079
6080 if (pAhciPort->pAsyncIOThread)
6081 {
6082 /* Destroy the event semaphore. */
6083 rc = RTSemEventDestroy(pAhciPort->AsyncIORequestSem);
6084 if (RT_FAILURE(rc))
6085 {
6086 Log(("%s: Destroying event semaphore for port %d failed rc=%Rrc\n", __FUNCTION__, iActPort, rc));
6087 }
6088 }
6089
6090 /* Free all cached tasks. */
6091 for (uint32_t i = 0; i < AHCI_NR_COMMAND_SLOTS; i++)
6092 {
6093 if (pAhciPort->aCachedTasks[i])
6094 {
6095 if (pAhciPort->aCachedTasks[i]->pSGListHead)
6096 RTMemFree(pAhciPort->aCachedTasks[i]->pSGListHead);
6097 if (pAhciPort->aCachedTasks[i]->paSGEntries)
6098 RTMemFree(pAhciPort->aCachedTasks[i]->paSGEntries);
6099
6100 RTMemFree(pAhciPort->aCachedTasks[i]);
6101 }
6102 }
6103 }
6104
6105 /* Destroy emulated ATA controllers. */
6106 for (unsigned i = 0; i < RT_ELEMENTS(pAhci->aCts); i++)
6107 ataControllerDestroy(&pAhci->aCts[i]);
6108
6109 PDMR3CritSectDelete(&pAhci->lock);
6110 }
6111
6112 return rc;
6113}
6114
6115/**
6116 * Configure the attached device for a port.
6117 *
6118 * Used by ahciR3Construct and ahciR3Attach.
6119 *
6120 * @returns VBox status code
6121 * @param pDevIns The device instance data.
6122 * @param pAhciPort The port for which the device is to be configured.
6123 */
6124static int ahciR3ConfigureLUN(PPDMDEVINS pDevIns, PAHCIPort pAhciPort)
6125{
6126 int rc = VINF_SUCCESS;
6127 PDMBLOCKTYPE enmType;
6128
6129 /*
6130 * Query the block and blockbios interfaces.
6131 */
6132 pAhciPort->pDrvBlock = PDMIBASE_QUERY_INTERFACE(pAhciPort->pDrvBase, PDMIBLOCK);
6133 if (!pAhciPort->pDrvBlock)
6134 {
6135 AssertMsgFailed(("Configuration error: LUN#%d hasn't a block interface!\n", pAhciPort->iLUN));
6136 return VERR_PDM_MISSING_INTERFACE;
6137 }
6138 pAhciPort->pDrvBlockBios = PDMIBASE_QUERY_INTERFACE(pAhciPort->pDrvBase, PDMIBLOCKBIOS);
6139 if (!pAhciPort->pDrvBlockBios)
6140 {
6141 AssertMsgFailed(("Configuration error: LUN#%d hasn't a block BIOS interface!\n", pAhciPort->iLUN));
6142 return VERR_PDM_MISSING_INTERFACE;
6143 }
6144
6145 pAhciPort->pDrvMount = PDMIBASE_QUERY_INTERFACE(pAhciPort->pDrvBase, PDMIMOUNT);
6146
6147 /* Try to get the optional async block interface. */
6148 pAhciPort->pDrvBlockAsync = PDMIBASE_QUERY_INTERFACE(pAhciPort->pDrvBase, PDMIBLOCKASYNC);
6149
6150 /*
6151 * Validate type.
6152 */
6153 enmType = pAhciPort->pDrvBlock->pfnGetType(pAhciPort->pDrvBlock);
6154
6155 if ( enmType != PDMBLOCKTYPE_HARD_DISK
6156 && enmType != PDMBLOCKTYPE_CDROM
6157 && enmType != PDMBLOCKTYPE_DVD)
6158 {
6159 AssertMsgFailed(("Configuration error: LUN#%d isn't a disk or cd/dvd. enmType=%d\n", pAhciPort->iLUN, enmType));
6160 return VERR_PDM_UNSUPPORTED_BLOCK_TYPE;
6161 }
6162
6163 if ( (enmType == PDMBLOCKTYPE_CDROM || enmType == PDMBLOCKTYPE_DVD)
6164 && !pAhciPort->pDrvMount)
6165 {
6166 AssertMsgFailed(("Internal error: CD/DVD-ROM without a mountable interface\n"));
6167 return VERR_INTERNAL_ERROR;
6168 }
6169 pAhciPort->fATAPI = (enmType == PDMBLOCKTYPE_CDROM || enmType == PDMBLOCKTYPE_DVD);
6170
6171 if (pAhciPort->fATAPI)
6172 {
6173 pAhciPort->cTotalSectors = pAhciPort->pDrvBlock->pfnGetSize(pAhciPort->pDrvBlock) / 2048;
6174 pAhciPort->PCHSGeometry.cCylinders = 0;
6175 pAhciPort->PCHSGeometry.cHeads = 0;
6176 pAhciPort->PCHSGeometry.cSectors = 0;
6177 LogRel(("AHCI LUN#%d: CD/DVD, total number of sectors %Ld\n", pAhciPort->iLUN, pAhciPort->cTotalSectors));
6178 }
6179 else
6180 {
6181 pAhciPort->cTotalSectors = pAhciPort->pDrvBlock->pfnGetSize(pAhciPort->pDrvBlock) / 512;
6182 rc = pAhciPort->pDrvBlockBios->pfnGetPCHSGeometry(pAhciPort->pDrvBlockBios,
6183 &pAhciPort->PCHSGeometry);
6184 if (rc == VERR_PDM_MEDIA_NOT_MOUNTED)
6185 {
6186 pAhciPort->PCHSGeometry.cCylinders = 0;
6187 pAhciPort->PCHSGeometry.cHeads = 16; /*??*/
6188 pAhciPort->PCHSGeometry.cSectors = 63; /*??*/
6189 }
6190 else if (rc == VERR_PDM_GEOMETRY_NOT_SET)
6191 {
6192 pAhciPort->PCHSGeometry.cCylinders = 0; /* autodetect marker */
6193 rc = VINF_SUCCESS;
6194 }
6195 AssertRC(rc);
6196
6197 if ( pAhciPort->PCHSGeometry.cCylinders == 0
6198 || pAhciPort->PCHSGeometry.cHeads == 0
6199 || pAhciPort->PCHSGeometry.cSectors == 0)
6200 {
6201 uint64_t cCylinders = pAhciPort->cTotalSectors / (16 * 63);
6202 pAhciPort->PCHSGeometry.cCylinders = RT_MAX(RT_MIN(cCylinders, 16383), 1);
6203 pAhciPort->PCHSGeometry.cHeads = 16;
6204 pAhciPort->PCHSGeometry.cSectors = 63;
6205 /* Set the disk geometry information. Ignore errors. */
6206 pAhciPort->pDrvBlockBios->pfnSetPCHSGeometry(pAhciPort->pDrvBlockBios,
6207 &pAhciPort->PCHSGeometry);
6208 rc = VINF_SUCCESS;
6209 }
6210 LogRel(("AHCI: LUN#%d: disk, PCHS=%u/%u/%u, total number of sectors %Ld\n",
6211 pAhciPort->iLUN, pAhciPort->PCHSGeometry.cCylinders,
6212 pAhciPort->PCHSGeometry.cHeads, pAhciPort->PCHSGeometry.cSectors,
6213 pAhciPort->cTotalSectors));
6214 }
6215 return rc;
6216}
6217
6218/**
6219 * Callback employed by ahciR3Suspend and ahciR3PowerOff..
6220 *
6221 * @returns true if we've quiesced, false if we're still working.
6222 * @param pDevIns The device instance.
6223 */
6224static DECLCALLBACK(bool) ahciR3IsAsyncSuspendOrPowerOffDone(PPDMDEVINS pDevIns)
6225{
6226 if (!ahciR3AllAsyncIOIsFinished(pDevIns))
6227 return false;
6228
6229 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
6230 ASMAtomicWriteBool(&pThis->fSignalIdle, false);
6231 return true;
6232}
6233
6234/**
6235 * Common worker for ahciR3Suspend and ahciR3PowerOff.
6236 */
6237static void ahciR3SuspendOrPowerOff(PPDMDEVINS pDevIns)
6238{
6239 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
6240
6241 ASMAtomicWriteBool(&pThis->fSignalIdle, true);
6242 if (!ahciR3AllAsyncIOIsFinished(pDevIns))
6243 PDMDevHlpSetAsyncNotification(pDevIns, ahciR3IsAsyncSuspendOrPowerOffDone);
6244 else
6245 ASMAtomicWriteBool(&pThis->fSignalIdle, false);
6246}
6247
6248/**
6249 * Suspend notification.
6250 *
6251 * @param pDevIns The device instance data.
6252 */
6253static DECLCALLBACK(void) ahciR3Suspend(PPDMDEVINS pDevIns)
6254{
6255 Log(("ahciR3Suspend\n"));
6256 ahciR3SuspendOrPowerOff(pDevIns);
6257}
6258
6259/**
6260 * Resume notification.
6261 *
6262 * @param pDevIns The device instance data.
6263 */
6264static DECLCALLBACK(void) ahciR3Resume(PPDMDEVINS pDevIns)
6265{
6266 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
6267
6268 Log(("%s:\n", __FUNCTION__));
6269 for (uint32_t i = 0; i < RT_ELEMENTS(pAhci->aCts); i++)
6270 ataControllerResume(&pAhci->aCts[i]);
6271 return;
6272}
6273
6274/**
6275 * Detach notification.
6276 *
6277 * One harddisk at one port has been unplugged.
6278 * The VM is suspended at this point.
6279 *
6280 * @param pDevIns The device instance.
6281 * @param iLUN The logical unit which is being detached.
6282 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
6283 */
6284static DECLCALLBACK(void) ahciR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
6285{
6286 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
6287 PAHCIPort pAhciPort = &pAhci->ahciPort[iLUN];
6288 int rc = VINF_SUCCESS;
6289
6290 Log(("%s:\n", __FUNCTION__));
6291
6292 AssertMsg(iLUN < pAhci->cPortsImpl, ("iLUN=%u", iLUN));
6293
6294 if (!pAhciPort->fAsyncInterface)
6295 {
6296 int rcThread;
6297 /* Destroy the thread. */
6298 rc = PDMR3ThreadDestroy(pAhciPort->pAsyncIOThread, &rcThread);
6299 if (RT_FAILURE(rc) || RT_FAILURE(rcThread))
6300 AssertMsgFailed(("%s Failed to destroy async IO thread rc=%Rrc rcThread=%Rrc\n", __FUNCTION__, rc, rcThread));
6301
6302 rc = RTSemEventDestroy(pAhciPort->AsyncIORequestSem);
6303 if (RT_FAILURE(rc))
6304 AssertMsgFailed(("%s: Failed to destroy the event semaphore rc=%Rrc.\n", __FUNCTION__, rc));
6305 }
6306
6307 /*
6308 * Zero some important members.
6309 */
6310 pAhciPort->pDrvBase = NULL;
6311 pAhciPort->pDrvBlock = NULL;
6312 pAhciPort->pDrvBlockAsync = NULL;
6313 pAhciPort->pDrvBlockBios = NULL;
6314}
6315
6316/**
6317 * Attach command.
6318 *
6319 * This is called when we change block driver for one port.
6320 * The VM is suspended at this point.
6321 *
6322 * @returns VBox status code.
6323 * @param pDevIns The device instance.
6324 * @param iLUN The logical unit which is being detached.
6325 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
6326 */
6327static DECLCALLBACK(int) ahciR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
6328{
6329 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
6330 PAHCIPort pAhciPort = &pAhci->ahciPort[iLUN];
6331 int rc;
6332
6333 Log(("%s:\n", __FUNCTION__));
6334
6335 /* the usual paranoia */
6336 AssertMsg(iLUN < pAhci->cPortsImpl, ("iLUN=%u", iLUN));
6337 AssertRelease(!pAhciPort->pDrvBase);
6338 AssertRelease(!pAhciPort->pDrvBlock);
6339 AssertRelease(!pAhciPort->pDrvBlockAsync);
6340 Assert(pAhciPort->iLUN == iLUN);
6341
6342 /*
6343 * Try attach the block device and get the interfaces,
6344 * required as well as optional.
6345 */
6346 rc = PDMDevHlpDriverAttach(pDevIns, pAhciPort->iLUN, &pAhciPort->IBase, &pAhciPort->pDrvBase, NULL);
6347 if (RT_SUCCESS(rc))
6348 rc = ahciR3ConfigureLUN(pDevIns, pAhciPort);
6349 else
6350 AssertMsgFailed(("Failed to attach LUN#%d. rc=%Rrc\n", pAhciPort->iLUN, rc));
6351
6352 if (RT_FAILURE(rc))
6353 {
6354 pAhciPort->pDrvBase = NULL;
6355 pAhciPort->pDrvBlock = NULL;
6356 }
6357 else
6358 {
6359 char szName[24];
6360 RTStrPrintf(szName, sizeof(szName), "Port%d", iLUN);
6361
6362 if (pAhciPort->pDrvBlockAsync)
6363 {
6364 pAhciPort->fAsyncInterface = true;
6365 }
6366 else
6367 {
6368 pAhciPort->fAsyncInterface = false;
6369
6370 /* Create event semaphore. */
6371 rc = RTSemEventCreate(&pAhciPort->AsyncIORequestSem);
6372 if (RT_FAILURE(rc))
6373 {
6374 Log(("%s: Failed to create event semaphore for %s.\n", __FUNCTION__, szName));
6375 return rc;
6376 }
6377
6378 /* Create the async IO thread. */
6379 rc = PDMDevHlpThreadCreate(pDevIns, &pAhciPort->pAsyncIOThread, pAhciPort, ahciAsyncIOLoop, ahciAsyncIOLoopWakeUp, 0,
6380 RTTHREADTYPE_IO, szName);
6381 if (RT_FAILURE(rc))
6382 {
6383 AssertMsgFailed(("%s: Async IO Thread creation for %s failed rc=%d\n", __FUNCTION__, szName, rc));
6384 return rc;
6385 }
6386 }
6387 }
6388
6389 return rc;
6390}
6391
6392/**
6393 * Common reset worker.
6394 *
6395 * @param pDevIns The device instance data.
6396 */
6397static int ahciR3ResetCommon(PPDMDEVINS pDevIns, bool fConstructor)
6398{
6399 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
6400
6401 ahciHBAReset(pAhci);
6402
6403 /* Hardware reset for the ports. */
6404 for (uint32_t i = 0; i < RT_ELEMENTS(pAhci->ahciPort); i++)
6405 ahciPortHwReset(&pAhci->ahciPort[i]);
6406
6407 for (uint32_t i = 0; i < RT_ELEMENTS(pAhci->aCts); i++)
6408 ataControllerReset(&pAhci->aCts[i]);
6409 return VINF_SUCCESS;
6410}
6411
6412/**
6413 * Callback employed by ahciR3Reset.
6414 *
6415 * @returns true if we've quiesced, false if we're still working.
6416 * @param pDevIns The device instance.
6417 */
6418static DECLCALLBACK(bool) ahciR3IsAsyncResetDone(PPDMDEVINS pDevIns)
6419{
6420 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
6421
6422 if (!ahciR3AllAsyncIOIsFinished(pDevIns))
6423 return false;
6424 ASMAtomicWriteBool(&pThis->fSignalIdle, false);
6425
6426 ahciR3ResetCommon(pDevIns, false /*fConstructor*/);
6427 return true;
6428}
6429
6430/**
6431 * Reset notification.
6432 *
6433 * @param pDevIns The device instance data.
6434 */
6435static DECLCALLBACK(void) ahciR3Reset(PPDMDEVINS pDevIns)
6436{
6437 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
6438
6439 ASMAtomicWriteBool(&pThis->fSignalIdle, true);
6440 if (!ahciR3AllAsyncIOIsFinished(pDevIns))
6441 PDMDevHlpSetAsyncNotification(pDevIns, ahciR3IsAsyncResetDone);
6442 else
6443 {
6444 ASMAtomicWriteBool(&pThis->fSignalIdle, false);
6445 ahciR3ResetCommon(pDevIns, false /*fConstructor*/);
6446 }
6447}
6448
6449/**
6450 * Poweroff notification.
6451 *
6452 * @param pDevIns Pointer to the device instance
6453 */
6454static DECLCALLBACK(void) ahciR3PowerOff(PPDMDEVINS pDevIns)
6455{
6456 Log(("achiR3PowerOff\n"));
6457 ahciR3SuspendOrPowerOff(pDevIns);
6458}
6459
6460/**
6461 * @interface_method_impl{PDMDEVREG,pfnConstruct}
6462 */
6463static DECLCALLBACK(int) ahciR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
6464{
6465 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
6466 PPDMIBASE pBase;
6467 int rc = VINF_SUCCESS;
6468 unsigned i = 0;
6469 bool fGCEnabled = false;
6470 bool fR0Enabled = false;
6471 uint32_t cbTotalBufferSize = 0;
6472 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
6473
6474 /*
6475 * Validate and read configuration.
6476 */
6477 if (!CFGMR3AreValuesValid(pCfgHandle, "GCEnabled\0"
6478 "R0Enabled\0"
6479 "PrimaryMaster\0"
6480 "PrimarySlave\0"
6481 "SecondaryMaster\0"
6482 "SecondarySlave\0"
6483 "PortCount\0"
6484 "UseAsyncInterfaceIfAvailable\0"
6485 "HighIOThreshold\0"
6486 "MillisToSleep\0"))
6487 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
6488 N_("AHCI configuration error: unknown option specified"));
6489
6490 rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
6491 if (RT_FAILURE(rc))
6492 return PDMDEV_SET_ERROR(pDevIns, rc,
6493 N_("AHCI configuration error: failed to read GCEnabled as boolean"));
6494 Log(("%s: fGCEnabled=%d\n", __FUNCTION__, fGCEnabled));
6495
6496 rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
6497 if (RT_FAILURE(rc))
6498 return PDMDEV_SET_ERROR(pDevIns, rc,
6499 N_("AHCI configuration error: failed to read R0Enabled as boolean"));
6500 Log(("%s: fR0Enabled=%d\n", __FUNCTION__, fR0Enabled));
6501
6502 rc = CFGMR3QueryU32Def(pCfgHandle, "PortCount", &pThis->cPortsImpl, AHCI_MAX_NR_PORTS_IMPL);
6503 if (RT_FAILURE(rc))
6504 return PDMDEV_SET_ERROR(pDevIns, rc,
6505 N_("AHCI configuration error: failed to read PortCount as integer"));
6506 Log(("%s: cPortsImpl=%u\n", __FUNCTION__, pThis->cPortsImpl));
6507 if (pThis->cPortsImpl > AHCI_MAX_NR_PORTS_IMPL)
6508 return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
6509 N_("AHCI configuration error: PortCount=%u should not exceed %u"),
6510 pThis->cPortsImpl, AHCI_MAX_NR_PORTS_IMPL);
6511 if (pThis->cPortsImpl < 1)
6512 return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
6513 N_("AHCI configuration error: PortCount=%u should be at least 1"),
6514 pThis->cPortsImpl);
6515
6516 rc = CFGMR3QueryBoolDef(pCfgHandle, "UseAsyncInterfaceIfAvailable", &pThis->fUseAsyncInterfaceIfAvailable, true);
6517 if (RT_FAILURE(rc))
6518 return PDMDEV_SET_ERROR(pDevIns, rc,
6519 N_("AHCI configuration error: failed to read UseAsyncInterfaceIfAvailable as boolean"));
6520 rc = CFGMR3QueryU32Def(pCfgHandle, "HighIOThreshold", &pThis->cHighIOThreshold, ~0);
6521 if (RT_FAILURE(rc))
6522 return PDMDEV_SET_ERROR(pDevIns, rc,
6523 N_("AHCI configuration error: failed to read HighIOThreshold as integer"));
6524 rc = CFGMR3QueryU32Def(pCfgHandle, "MillisToSleep", &pThis->cMillisToSleep, 0);
6525 if (RT_FAILURE(rc))
6526 return PDMDEV_SET_ERROR(pDevIns, rc,
6527 N_("AHCI configuration error: failed to read MillisToSleep as integer"));
6528
6529 pThis->fR0Enabled = fR0Enabled;
6530 pThis->fGCEnabled = fGCEnabled;
6531 pThis->pDevInsR3 = pDevIns;
6532 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
6533 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
6534
6535 PCIDevSetVendorId (&pThis->dev, 0x8086); /* Intel */
6536 PCIDevSetDeviceId (&pThis->dev, 0x2829); /* ICH-8M */
6537 PCIDevSetCommand (&pThis->dev, 0x0000);
6538 PCIDevSetRevisionId (&pThis->dev, 0x02);
6539 PCIDevSetClassProg (&pThis->dev, 0x01);
6540 PCIDevSetClassSub (&pThis->dev, 0x06);
6541 PCIDevSetClassBase (&pThis->dev, 0x01);
6542 PCIDevSetBaseAddress (&pThis->dev, 5, false, false, false, 0x00000000);
6543
6544 pThis->dev.config[0x34] = 0x80; /* Capability pointer. */
6545
6546 PCIDevSetInterruptLine(&pThis->dev, 0x00);
6547 PCIDevSetInterruptPin (&pThis->dev, 0x01);
6548
6549 pThis->dev.config[0x70] = 0x01; /* Capability ID: PCI Power Management Interface */
6550 pThis->dev.config[0x71] = 0x00;
6551 pThis->dev.config[0x72] = 0x03;
6552
6553 pThis->dev.config[0x80] = 0x05; /* Capability ID: Message Signaled Interrupts. Disabled. */
6554 pThis->dev.config[0x81] = 0x70; /* next. */
6555
6556 pThis->dev.config[0x90] = 0x40; /* AHCI mode. */
6557 pThis->dev.config[0x92] = 0x3f;
6558 pThis->dev.config[0x94] = 0x80;
6559 pThis->dev.config[0x95] = 0x01;
6560 pThis->dev.config[0x97] = 0x78;
6561
6562 /*
6563 * Register the PCI device, it's I/O regions.
6564 */
6565 rc = PDMDevHlpPCIRegister (pDevIns, &pThis->dev);
6566 if (RT_FAILURE(rc))
6567 return rc;
6568
6569 /*
6570 * Solaris 10 U5 fails to map the AHCI register space when the sets (0..5) for the legacy
6571 * IDE registers are not available.
6572 * We set up "fake" entries in the PCI configuration register.
6573 * That means they are available but read and writes from/to them have no effect.
6574 * No guest should access them anyway because the controller is marked as AHCI in the Programming interface
6575 * and we don't have an option to change to IDE emulation (real hardware provides an option in the BIOS
6576 * to switch to it which also changes device Id and other things in the PCI configuration space).
6577 */
6578 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 8, PCI_ADDRESS_SPACE_IO, ahciR3LegacyFakeIORangeMap);
6579 if (RT_FAILURE(rc))
6580 return PDMDEV_SET_ERROR(pDevIns, rc,
6581 N_("AHCI cannot register PCI I/O region"));
6582
6583 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 1, 1, PCI_ADDRESS_SPACE_IO, ahciR3LegacyFakeIORangeMap);
6584 if (RT_FAILURE(rc))
6585 return PDMDEV_SET_ERROR(pDevIns, rc,
6586 N_("AHCI cannot register PCI I/O region"));
6587
6588 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 2, 8, PCI_ADDRESS_SPACE_IO, ahciR3LegacyFakeIORangeMap);
6589 if (RT_FAILURE(rc))
6590 return PDMDEV_SET_ERROR(pDevIns, rc,
6591 N_("AHCI cannot register PCI I/O region"));
6592
6593 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 3, 1, PCI_ADDRESS_SPACE_IO, ahciR3LegacyFakeIORangeMap);
6594 if (RT_FAILURE(rc))
6595 return PDMDEV_SET_ERROR(pDevIns, rc,
6596 N_("AHCI cannot register PCI I/O region"));
6597
6598 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 4, 0x10, PCI_ADDRESS_SPACE_IO, ahciR3LegacyFakeIORangeMap);
6599 if (RT_FAILURE(rc))
6600 return PDMDEV_SET_ERROR(pDevIns, rc,
6601 N_("AHCI cannot register PCI I/O region for BMDMA"));
6602
6603 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 5, 4352, PCI_ADDRESS_SPACE_MEM, ahciR3MMIOMap);
6604 if (RT_FAILURE(rc))
6605 return PDMDEV_SET_ERROR(pDevIns, rc,
6606 N_("AHCI cannot register PCI memory region for registers"));
6607
6608 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->lock, RT_SRC_POS, "AHCI");
6609 if (RT_FAILURE(rc))
6610 {
6611 Log(("%s: Failed to create critical section.\n", __FUNCTION__));
6612 return rc;
6613 }
6614
6615 /* Create the timer for command completion coalescing feature. */
6616 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, ahciCccTimer, pThis,
6617 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, "AHCI CCC Timer", &pThis->pHbaCccTimerR3);
6618 if (RT_FAILURE(rc))
6619 {
6620 AssertMsgFailed(("pfnTMTimerCreate -> %Rrc\n", rc));
6621 return rc;
6622 }
6623 pThis->pHbaCccTimerR0 = TMTimerR0Ptr(pThis->pHbaCccTimerR3);
6624 pThis->pHbaCccTimerRC = TMTimerRCPtr(pThis->pHbaCccTimerR3);
6625
6626 /* Status LUN. */
6627 pThis->IBase.pfnQueryInterface = ahciR3Status_QueryInterface;
6628 pThis->ILeds.pfnQueryStatusLed = ahciR3Status_QueryStatusLed;
6629
6630 /*
6631 * Create the transmit queue.
6632 */
6633 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(DEVPORTNOTIFIERQUEUEITEM), 30*32 /*Maximum of 30 ports multiplied with 32 tasks each port*/, 0,
6634 ahciNotifyQueueConsumer, true, "AHCI-Xmit", &pThis->pNotifierQueueR3);
6635 if (RT_FAILURE(rc))
6636 return rc;
6637 pThis->pNotifierQueueR0 = PDMQueueR0Ptr(pThis->pNotifierQueueR3);
6638 pThis->pNotifierQueueRC = PDMQueueRCPtr(pThis->pNotifierQueueR3);
6639
6640 /* Initialize static members on every port. */
6641 for (i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
6642 {
6643 /*
6644 * Init members of the port.
6645 */
6646 PAHCIPort pAhciPort = &pThis->ahciPort[i];
6647 pAhciPort->pDevInsR3 = pDevIns;
6648 pAhciPort->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
6649 pAhciPort->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
6650 pAhciPort->iLUN = i;
6651 pAhciPort->pAhciR3 = pThis;
6652 pAhciPort->pAhciR0 = PDMINS_2_DATA_R0PTR(pDevIns);
6653 pAhciPort->pAhciRC = PDMINS_2_DATA_RCPTR(pDevIns);
6654 pAhciPort->Led.u32Magic = PDMLED_MAGIC;
6655 pAhciPort->pDrvBase = NULL;
6656
6657 /* Register statistics counter. */
6658 PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatDMA, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
6659 "Number of DMA transfers.", "/Devices/SATA%d/Port%d/DMA", iInstance, i);
6660 PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatBytesRead, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
6661 "Amount of data read.", "/Devices/SATA%d/Port%d/ReadBytes", iInstance, i);
6662 PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatBytesWritten, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
6663 "Amount of data written.", "/Devices/SATA%d/Port%d/WrittenBytes", iInstance, i);
6664 PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatIORequestsPerSecond, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
6665 "Number of processed I/O requests per second.", "/Devices/SATA%d/Port%d/IORequestsPerSecond", iInstance, i);
6666#ifdef VBOX_WITH_STATISTICS
6667 PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatProfileProcessTime, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_NS_PER_CALL,
6668 "Amount of time to process one request.", "/Devices/SATA%d/Port%d/ProfileProcessTime", iInstance, i);
6669 PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatProfileMapIntoR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_NS_PER_CALL,
6670 "Amount of time to map the guest buffers into R3.", "/Devices/SATA%d/Port%d/ProfileMapIntoR3", iInstance, i);
6671 PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatProfileReadWrite, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_NS_PER_CALL,
6672 "Amount of time for the read/write operation to complete.", "/Devices/SATA%d/Port%d/ProfileReadWrite", iInstance, i);
6673 PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatProfileDestroyScatterGatherList, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_NS_PER_CALL,
6674 "Amount of time to destroy the scatter gather list and free associated ressources.", "/Devices/SATA%d/Port%d/ProfileDestroyScatterGatherList", iInstance, i);
6675#endif
6676
6677 ahciPortHwReset(pAhciPort);
6678 }
6679
6680 /* Attach drivers to every available port. */
6681 for (i = 0; i < pThis->cPortsImpl; i++)
6682 {
6683 char szName[24];
6684 RTStrPrintf(szName, sizeof(szName), "Port%u", i);
6685
6686 PAHCIPort pAhciPort = &pThis->ahciPort[i];
6687 /*
6688 * Init interfaces.
6689 */
6690 pAhciPort->IBase.pfnQueryInterface = ahciR3PortQueryInterface;
6691 pAhciPort->IPortAsync.pfnTransferCompleteNotify = ahciTransferCompleteNotify;
6692 pAhciPort->IMountNotify.pfnMountNotify = ahciMountNotify;
6693 pAhciPort->IMountNotify.pfnUnmountNotify = ahciUnmountNotify;
6694 pAhciPort->fAsyncIOThreadIdle = true;
6695
6696 /*
6697 * Attach the block driver
6698 */
6699 rc = PDMDevHlpDriverAttach(pDevIns, pAhciPort->iLUN, &pAhciPort->IBase, &pAhciPort->pDrvBase, szName);
6700 if (RT_SUCCESS(rc))
6701 {
6702 rc = ahciR3ConfigureLUN(pDevIns, pAhciPort);
6703 if (RT_FAILURE(rc))
6704 {
6705 Log(("%s: Failed to configure the %s.\n", __FUNCTION__, szName));
6706 return rc;
6707 }
6708
6709 /* Mark that a device is present on that port */
6710 if (i < 6)
6711 pThis->dev.config[0x93] |= (1 << i);
6712
6713 /*
6714 * Init vendor product data.
6715 */
6716 /* Generate a default serial number. */
6717 char szSerial[AHCI_SERIAL_NUMBER_LENGTH+1];
6718 RTUUID Uuid;
6719 if (pAhciPort->pDrvBlock)
6720 rc = pAhciPort->pDrvBlock->pfnGetUuid(pAhciPort->pDrvBlock, &Uuid);
6721 else
6722 RTUuidClear(&Uuid);
6723
6724 if (RT_FAILURE(rc) || RTUuidIsNull(&Uuid))
6725 {
6726 /* Generate a predictable serial for drives which don't have a UUID. */
6727 RTStrPrintf(szSerial, sizeof(szSerial), "VB%x-1a2b3c4d",
6728 pAhciPort->iLUN);
6729 }
6730 else
6731 RTStrPrintf(szSerial, sizeof(szSerial), "VB%08x-%08x", Uuid.au32[0], Uuid.au32[3]);
6732
6733 /* Get user config if present using defaults otherwise. */
6734 PCFGMNODE pCfgNode = CFGMR3GetChild(pCfgHandle, szName);
6735 rc = CFGMR3QueryStringDef(pCfgNode, "SerialNumber", pAhciPort->szSerialNumber, sizeof(pAhciPort->szSerialNumber),
6736 szSerial);
6737 if (RT_FAILURE(rc))
6738 {
6739 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
6740 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
6741 N_("AHCI configuration error: \"SerialNumber\" is longer than 20 bytes"));
6742 return PDMDEV_SET_ERROR(pDevIns, rc,
6743 N_("AHCI configuration error: failed to read \"SerialNumber\" as string"));
6744 }
6745
6746 rc = CFGMR3QueryStringDef(pCfgNode, "FirmwareRevision", pAhciPort->szFirmwareRevision, sizeof(pAhciPort->szFirmwareRevision),
6747 "1.0");
6748 if (RT_FAILURE(rc))
6749 {
6750 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
6751 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
6752 N_("AHCI configuration error: \"FirmwareRevision\" is longer than 8 bytes"));
6753 return PDMDEV_SET_ERROR(pDevIns, rc,
6754 N_("AHCI configuration error: failed to read \"FirmwareRevision\" as string"));
6755 }
6756
6757 rc = CFGMR3QueryStringDef(pCfgNode, "ModelNumber", pAhciPort->szModelNumber, sizeof(pAhciPort->szModelNumber),
6758 pAhciPort->fATAPI ? "VBOX CD-ROM" : "VBOX HARDDISK");
6759 if (RT_FAILURE(rc))
6760 {
6761 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
6762 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
6763 N_("AHCI configuration error: \"ModelNumber\" is longer than 40 bytes"));
6764 return PDMDEV_SET_ERROR(pDevIns, rc,
6765 N_("AHCI configuration error: failed to read \"ModelNumber\" as string"));
6766 }
6767
6768 /* There are three other identification strings for CD drives used for INQUIRY */
6769 if (pAhciPort->fATAPI)
6770 {
6771 rc = CFGMR3QueryStringDef(pCfgNode, "ATAPIVendorId", pAhciPort->szInquiryVendorId, sizeof(pAhciPort->szInquiryVendorId),
6772 "VBOX");
6773 if (RT_FAILURE(rc))
6774 {
6775 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
6776 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
6777 N_("PIIX3 configuration error: \"ATAPIVendorId\" is longer than 16 bytes"));
6778 return PDMDEV_SET_ERROR(pDevIns, rc,
6779 N_("PIIX3 configuration error: failed to read \"ATAPIVendorId\" as string"));
6780 }
6781
6782 rc = CFGMR3QueryStringDef(pCfgNode, "ATAPIProductId", pAhciPort->szInquiryProductId, sizeof(pAhciPort->szInquiryProductId),
6783 "CD-ROM");
6784 if (RT_FAILURE(rc))
6785 {
6786 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
6787 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
6788 N_("PIIX3 configuration error: \"ATAPIProductId\" is longer than 16 bytes"));
6789 return PDMDEV_SET_ERROR(pDevIns, rc,
6790 N_("PIIX3 configuration error: failed to read \"ATAPIProductId\" as string"));
6791 }
6792
6793 rc = CFGMR3QueryStringDef(pCfgNode, "ATAPIRevision", pAhciPort->szInquiryRevision, sizeof(pAhciPort->szInquiryRevision),
6794 "1.0");
6795 if (RT_FAILURE(rc))
6796 {
6797 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
6798 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
6799 N_("PIIX3 configuration error: \"ATAPIRevision\" is longer than 4 bytes"));
6800 return PDMDEV_SET_ERROR(pDevIns, rc,
6801 N_("PIIX3 configuration error: failed to read \"ATAPIRevision\" as string"));
6802 }
6803 }
6804
6805 /*
6806 * If the new async interface is available we use a PDMQueue to transmit
6807 * the requests into R3.
6808 * Otherwise we use a event semaphore and a async I/O thread which processes them.
6809 */
6810 if (pAhciPort->pDrvBlockAsync && pThis->fUseAsyncInterfaceIfAvailable)
6811 {
6812 LogRel(("AHCI: LUN#%d: using async I/O\n", pAhciPort->iLUN));
6813 pAhciPort->fAsyncInterface = true;
6814 }
6815 else
6816 {
6817 LogRel(("AHCI: LUN#%d: using normal I/O\n", pAhciPort->iLUN));
6818 pAhciPort->fAsyncInterface = false;
6819
6820 rc = RTSemEventCreate(&pAhciPort->AsyncIORequestSem);
6821 AssertMsgRC(rc, ("Failed to create event semaphore for %s rc=%Rrc.\n", szName, rc));
6822
6823
6824 rc = PDMDevHlpThreadCreate(pDevIns, &pAhciPort->pAsyncIOThread, pAhciPort, ahciAsyncIOLoop, ahciAsyncIOLoopWakeUp, 0,
6825 RTTHREADTYPE_IO, szName);
6826 AssertMsgRC(rc, ("%s: Async IO Thread creation for %s failed rc=%Rrc\n", szName, rc));
6827 }
6828 }
6829 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
6830 {
6831 pAhciPort->pDrvBase = NULL;
6832 rc = VINF_SUCCESS;
6833 LogRel(("%s: no driver attached\n", szName));
6834 }
6835 else
6836 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
6837 N_("AHCI: Failed to attach drive to %s"), szName);
6838
6839#ifdef DEBUG
6840 for (uint32_t j = 0; j < AHCI_NR_COMMAND_SLOTS; j++)
6841 pAhciPort->ahciIOTasks[j] = 0xff;
6842#endif
6843 }
6844
6845 /*
6846 * Attach status driver (optional).
6847 */
6848 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThis->IBase, &pBase, "Status Port");
6849 if (RT_SUCCESS(rc))
6850 pThis->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
6851 else if (rc != VERR_PDM_NO_ATTACHED_DRIVER)
6852 {
6853 AssertMsgFailed(("Failed to attach to status driver. rc=%Rrc\n", rc));
6854 return PDMDEV_SET_ERROR(pDevIns, rc, N_("AHCI cannot attach to status driver"));
6855 }
6856
6857 /*
6858 * Setup IDE emulation.
6859 * We only emulate the I/O ports but not bus master DMA.
6860 * If the configuration values are not found the setup of the ports is as follows:
6861 * Primary Master: Port 0
6862 * Primary Slave: Port 1
6863 * Secondary Master: Port 2
6864 * Secondary Slave: Port 3
6865 */
6866
6867 /*
6868 * Setup I/O ports for the PCI device.
6869 */
6870 pThis->aCts[0].irq = 12;
6871 pThis->aCts[0].IOPortBase1 = 0x1e8;
6872 pThis->aCts[0].IOPortBase2 = 0x3e6;
6873 pThis->aCts[1].irq = 11;
6874 pThis->aCts[1].IOPortBase1 = 0x168;
6875 pThis->aCts[1].IOPortBase2 = 0x366;
6876
6877 for (i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
6878 {
6879 PAHCIATACONTROLLER pCtl = &pThis->aCts[i];
6880 uint32_t iPortMaster, iPortSlave;
6881 uint32_t cbSSMState = 0;
6882 static const char *s_apszDescs[RT_ELEMENTS(pThis->aCts)][RT_ELEMENTS(pCtl->aIfs)] =
6883 {
6884 { "PrimaryMaster", "PrimarySlave" },
6885 { "SecondaryMaster", "SecondarySlave" }
6886 };
6887
6888 rc = CFGMR3QueryU32Def(pCfgHandle, s_apszDescs[i][0], &iPortMaster, 2 * i);
6889 if (RT_FAILURE(rc))
6890 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
6891 N_("AHCI configuration error: failed to read %s as U32"), s_apszDescs[i][0]);
6892
6893 rc = CFGMR3QueryU32Def(pCfgHandle, s_apszDescs[i][1], &iPortSlave, 2 * i + 1);
6894 if (RT_FAILURE(rc))
6895 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
6896 N_("AHCI configuration error: failed to read %s as U32"), s_apszDescs[i][1]);
6897
6898 char szName[24];
6899 RTStrPrintf(szName, sizeof(szName), "EmulatedATA%d", i);
6900 rc = ataControllerInit(pDevIns, pCtl, pThis->ahciPort[iPortMaster].pDrvBase, pThis->ahciPort[iPortSlave].pDrvBase,
6901 &cbSSMState, szName, &pThis->ahciPort[iPortMaster].Led, &pThis->ahciPort[iPortMaster].StatBytesRead,
6902 &pThis->ahciPort[iPortMaster].StatBytesWritten);
6903 if (RT_FAILURE(rc))
6904 return rc;
6905
6906 cbTotalBufferSize += cbSSMState;
6907
6908 rc = PDMDevHlpIOPortRegister(pDevIns, pCtl->IOPortBase1, 8, (RTHCPTR)i,
6909 ahciIOPortWrite1, ahciIOPortRead1, ahciIOPortWriteStr1, ahciIOPortReadStr1, "AHCI");
6910 if (RT_FAILURE(rc))
6911 return rc;
6912
6913 if (pThis->fR0Enabled)
6914 {
6915 rc = PDMDevHlpIOPortRegisterR0(pDevIns, pCtl->IOPortBase1, 8, (RTR0PTR)i,
6916 "ahciIOPortWrite1", "ahciIOPortRead1", NULL, NULL, "AHCI R0");
6917 if (RT_FAILURE(rc))
6918 return rc;
6919 }
6920
6921 if (pThis->fGCEnabled)
6922 {
6923 rc = PDMDevHlpIOPortRegisterRC(pDevIns, pCtl->IOPortBase1, 8, (RTGCPTR)i,
6924 "ahciIOPortWrite1", "ahciIOPortRead1", NULL, NULL, "AHCI GC");
6925 if (RT_FAILURE(rc))
6926 return rc;
6927 }
6928
6929 rc = PDMDevHlpIOPortRegister(pDevIns, pCtl->IOPortBase2, 1, (RTHCPTR)i,
6930 ahciIOPortWrite2, ahciIOPortRead2, NULL, NULL, "AHCI");
6931 if (RT_FAILURE(rc))
6932 return rc;
6933
6934 if (pThis->fR0Enabled)
6935 {
6936 rc = PDMDevHlpIOPortRegisterR0(pDevIns, pCtl->IOPortBase2, 1, (RTR0PTR)i,
6937 "ahciIOPortWrite2", "ahciIOPortRead2", NULL, NULL, "AHCI R0");
6938 if (RT_FAILURE(rc))
6939 return rc;
6940 }
6941
6942 if (pThis->fGCEnabled)
6943 {
6944 rc = PDMDevHlpIOPortRegisterRC(pDevIns, pCtl->IOPortBase2, 1, (RTGCPTR)i,
6945 "ahciIOPortWrite2", "ahciIOPortRead2", NULL, NULL, "AHCI GC");
6946 if (RT_FAILURE(rc))
6947 return rc;
6948 }
6949 }
6950
6951 rc = PDMDevHlpSSMRegisterEx(pDevIns, AHCI_SAVED_STATE_VERSION, sizeof(*pThis)+cbTotalBufferSize, NULL,
6952 NULL, ahciR3LiveExec, NULL,
6953 ahciR3SavePrep, ahciR3SaveExec, NULL,
6954 ahciR3LoadPrep, ahciR3LoadExec, NULL);
6955 if (RT_FAILURE(rc))
6956 return rc;
6957
6958 return ahciR3ResetCommon(pDevIns, true /*fConstructor*/);
6959}
6960
6961/**
6962 * The device registration structure.
6963 */
6964const PDMDEVREG g_DeviceAHCI =
6965{
6966 /* u32Version */
6967 PDM_DEVREG_VERSION,
6968 /* szName */
6969 "ahci",
6970 /* szRCMod */
6971 "VBoxDDGC.gc",
6972 /* szR0Mod */
6973 "VBoxDDR0.r0",
6974 /* pszDescription */
6975 "Intel AHCI controller.\n",
6976 /* fFlags */
6977 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0 |
6978 PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION | PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION,
6979 /* fClass */
6980 PDM_DEVREG_CLASS_STORAGE,
6981 /* cMaxInstances */
6982 ~0,
6983 /* cbInstance */
6984 sizeof(AHCI),
6985 /* pfnConstruct */
6986 ahciR3Construct,
6987 /* pfnDestruct */
6988 ahciR3Destruct,
6989 /* pfnRelocate */
6990 ahciR3Relocate,
6991 /* pfnIOCtl */
6992 NULL,
6993 /* pfnPowerOn */
6994 NULL,
6995 /* pfnReset */
6996 ahciR3Reset,
6997 /* pfnSuspend */
6998 ahciR3Suspend,
6999 /* pfnResume */
7000 ahciR3Resume,
7001 /* pfnAttach */
7002 ahciR3Attach,
7003 /* pfnDetach */
7004 ahciR3Detach,
7005 /* pfnQueryInterface. */
7006 NULL,
7007 /* pfnInitComplete */
7008 NULL,
7009 /* pfnPowerOff */
7010 ahciR3PowerOff,
7011 /* pfnSoftReset */
7012 NULL,
7013 /* u32VersionEnd */
7014 PDM_DEVREG_VERSION
7015};
7016
7017#endif /* IN_RING3 */
7018#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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