VirtualBox

source: vbox/trunk/src/VBox/Devices/Storage/DevAHCI.cpp@ 34810

Last change on this file since 34810 was 34433, checked in by vboxsync, 14 years ago

Storage: Introduce interface to query the location of a medium (device + instance + LUN) in a VM to generate IDs which are constant for saved states
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 328.0 KB
Line 
1/* $Id: DevAHCI.cpp 34433 2010-11-27 11:09:38Z vboxsync $ */
2/** @file
3 * VBox storage devices: AHCI controller device (disk and cdrom).
4 * Implements the AHCI standard 1.1
5 */
6
7/*
8 * Copyright (C) 2006-2009 Oracle Corporation
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License (GPL) as published by the Free Software
14 * Foundation, in version 2 as it comes in the "COPYING" file of the
15 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17 */
18
19/** @page pg_dev_ahci AHCI - Advanced Host Controller Interface Emulation.
20 *
21 * This component implements an AHCI serial ATA controller. The device is split
22 * into two parts. The first part implements the register interface for the
23 * guest and the second one does the data transfer.
24 *
25 * The guest can access the controller in two ways. The first one is the native
26 * way implementing the registers described in the AHCI specification and is
27 * the preferred one. The second implements the I/O ports used for booting from
28 * the hard disk and for guests which don't have an AHCI SATA driver.
29 *
30 * The data is transferred in an asynchronous way using one thread per implemented
31 * port or using the new async completion interface which is still under
32 * development. [not quite up to date]
33 */
34
35/*******************************************************************************
36* Header Files *
37*******************************************************************************/
38//#define DEBUG
39#define LOG_GROUP LOG_GROUP_DEV_AHCI
40#include <VBox/pdmdev.h>
41#include <VBox/pdmqueue.h>
42#include <VBox/pdmthread.h>
43#include <VBox/pdmcritsect.h>
44#include <VBox/scsi.h>
45#include <iprt/assert.h>
46#include <iprt/asm.h>
47#include <iprt/string.h>
48#ifdef IN_RING3
49# include <iprt/param.h>
50# include <iprt/thread.h>
51# include <iprt/semaphore.h>
52# include <iprt/alloc.h>
53# include <iprt/uuid.h>
54# include <iprt/time.h>
55#endif
56
57#include "ide.h"
58#include "ATAController.h"
59#include "../Builtins.h"
60
61#define AHCI_MAX_NR_PORTS_IMPL 30
62#define AHCI_NR_COMMAND_SLOTS 32
63#define AHCI_NR_OF_ALLOWED_BIGGER_LISTS 100
64
65/** The current saved state version. */
66#define AHCI_SAVED_STATE_VERSION 4
67/** Saved state version before ATAPI support was added. */
68#define AHCI_SAVED_STATE_VERSION_PRE_ATAPI 3
69/** The saved state version use in VirtualBox 3.0 and earlier.
70 * This was before the config was added and ahciIOTasks was dropped. */
71#define AHCI_SAVED_STATE_VERSION_VBOX_30 2
72
73/**
74 * Maximum number of sectors to transfer in a READ/WRITE MULTIPLE request.
75 * Set to 1 to disable multi-sector read support. According to the ATA
76 * specification this must be a power of 2 and it must fit in an 8 bit
77 * value. Thus the only valid values are 1, 2, 4, 8, 16, 32, 64 and 128.
78 */
79#define ATA_MAX_MULT_SECTORS 128
80
81/**
82 * Fastest PIO mode supported by the drive.
83 */
84#define ATA_PIO_MODE_MAX 4
85/**
86 * Fastest MDMA mode supported by the drive.
87 */
88#define ATA_MDMA_MODE_MAX 2
89/**
90 * Fastest UDMA mode supported by the drive.
91 */
92#define ATA_UDMA_MODE_MAX 6
93
94/**
95 * Length of the configurable VPD data (without termination)
96 */
97#define AHCI_SERIAL_NUMBER_LENGTH 20
98#define AHCI_FIRMWARE_REVISION_LENGTH 8
99#define AHCI_MODEL_NUMBER_LENGTH 40
100#define AHCI_ATAPI_INQUIRY_VENDOR_ID_LENGTH 8
101#define AHCI_ATAPI_INQUIRY_PRODUCT_ID_LENGTH 16
102#define AHCI_ATAPI_INQUIRY_REVISION_LENGTH 4
103
104/* MediaEventStatus */
105#define ATA_EVENT_STATUS_UNCHANGED 0 /**< medium event status not changed */
106#define ATA_EVENT_STATUS_MEDIA_NEW 1 /**< new medium inserted */
107#define ATA_EVENT_STATUS_MEDIA_REMOVED 2 /**< medium removed */
108#define ATA_EVENT_STATUS_MEDIA_CHANGED 3 /**< medium was removed + new medium was inserted */
109#define ATA_EVENT_STATUS_MEDIA_EJECT_REQUESTED 4 /**< medium eject requested (eject button pressed) */
110
111/* Media track type */
112#define ATA_MEDIA_TYPE_UNKNOWN 0 /**< unknown CD type */
113#define ATA_MEDIA_TYPE_DATA 1 /**< Data CD */
114#define ATA_MEDIA_TYPE_CDDA 2 /**< CD-DA (audio) CD type */
115
116/** ATAPI sense info size. */
117#define ATAPI_SENSE_SIZE 64
118
119/* Command Header. */
120typedef struct
121{
122 /** Description Information. */
123 uint32_t u32DescInf;
124 /** Command status. */
125 uint32_t u32PRDBC;
126 /** Command Table Base Address. */
127 uint32_t u32CmdTblAddr;
128 /** Command Table Base Address - upper 32-bits. */
129 uint32_t u32CmdTblAddrUp;
130 /** Reserved */
131 uint32_t u32Reserved[4];
132} CmdHdr;
133AssertCompileSize(CmdHdr, 32);
134
135/* Defines for the command header. */
136#define AHCI_CMDHDR_PRDTL_MASK 0xffff0000
137#define AHCI_CMDHDR_PRDTL_ENTRIES(x) ((x & AHCI_CMDHDR_PRDTL_MASK) >> 16)
138#define AHCI_CMDHDR_C RT_BIT(10)
139#define AHCI_CMDHDR_B RT_BIT(9)
140#define AHCI_CMDHDR_R RT_BIT(8)
141#define AHCI_CMDHDR_P RT_BIT(7)
142#define AHCI_CMDHDR_W RT_BIT(6)
143#define AHCI_CMDHDR_A RT_BIT(5)
144#define AHCI_CMDHDR_CFL_MASK 0x1f
145
146#define AHCI_CMDHDR_PRDT_OFFSET 0x80
147#define AHCI_CMDHDR_ACMD_OFFSET 0x40
148
149/* Defines for the command FIS. */
150/* Defines that are used in the first double word. */
151#define AHCI_CMDFIS_TYPE 0 /* The first byte. */
152# define AHCI_CMDFIS_TYPE_H2D 0x27 /* Register - Host to Device FIS. */
153# define AHCI_CMDFIS_TYPE_H2D_SIZE 20 /* Five double words. */
154# define AHCI_CMDFIS_TYPE_D2H 0x34 /* Register - Device to Host FIS. */
155# define AHCI_CMDFIS_TYPE_D2H_SIZE 20 /* Five double words. */
156# define AHCI_CMDFIS_TYPE_SETDEVBITS 0xa1 /* Set Device Bits - Device to Host FIS. */
157# define AHCI_CMDFIS_TYPE_SETDEVBITS_SIZE 8 /* Two double words. */
158# define AHCI_CMDFIS_TYPE_DMAACTD2H 0x39 /* DMA Activate - Device to Host FIS. */
159# define AHCI_CMDFIS_TYPE_DMAACTD2H_SIZE 4 /* One double word. */
160# define AHCI_CMDFIS_TYPE_DMASETUP 0x41 /* DMA Setup - Bidirectional FIS. */
161# define AHCI_CMDFIS_TYPE_DMASETUP_SIZE 28 /* Seven double words. */
162# define AHCI_CMDFIS_TYPE_PIOSETUP 0x5f /* PIO Setup - Device to Host FIS. */
163# define AHCI_CMDFIS_TYPE_PIOSETUP_SIZE 20 /* Five double words. */
164# define AHCI_CMDFIS_TYPE_DATA 0x46 /* Data - Bidirectional FIS. */
165
166#define AHCI_CMDFIS_BITS 1 /* Interrupt and Update bit. */
167#define AHCI_CMDFIS_C RT_BIT(7) /* Host to device. */
168#define AHCI_CMDFIS_I RT_BIT(6) /* Device to Host. */
169
170#define AHCI_CMDFIS_CMD 2
171#define AHCI_CMDFIS_FET 3
172
173#define AHCI_CMDFIS_SECTN 4
174#define AHCI_CMDFIS_CYLL 5
175#define AHCI_CMDFIS_CYLH 6
176#define AHCI_CMDFIS_HEAD 7
177
178#define AHCI_CMDFIS_SECTNEXP 8
179#define AHCI_CMDFIS_CYLLEXP 9
180#define AHCI_CMDFIS_CYLHEXP 10
181#define AHCI_CMDFIS_FETEXP 11
182
183#define AHCI_CMDFIS_SECTC 12
184#define AHCI_CMDFIS_SECTCEXP 13
185#define AHCI_CMDFIS_CTL 15
186# define AHCI_CMDFIS_CTL_SRST RT_BIT(2) /* Reset device. */
187# define AHCI_CMDFIS_CTL_NIEN RT_BIT(1) /* Assert or clear interrupt. */
188
189/* For D2H FIS */
190#define AHCI_CMDFIS_STS 2
191#define AHCI_CMDFIS_ERR 3
192
193/**
194 * Scatter gather list entry data.
195 */
196typedef struct AHCIPORTTASKSTATESGENTRY
197{
198 /** Flag whether the buffer in the list is from the guest or an
199 * allocated temporary buffer because the segments in the guest
200 * are not sector aligned.
201 */
202 bool fGuestMemory;
203 /** Flag dependent data. */
204 union
205 {
206 /** Data to handle direct mappings of guest buffers. */
207 struct
208 {
209 /** The page lock. */
210 PGMPAGEMAPLOCK PageLock;
211 } direct;
212 /** Data to handle temporary buffers. */
213 struct
214 {
215 /** The first segment in the guest which is not sector aligned. */
216 RTGCPHYS GCPhysAddrBaseFirstUnaligned;
217 /** Number of unaligned buffers in the guest. */
218 uint32_t cUnaligned;
219 /** Pointer to the start of the buffer. */
220 void *pvBuf;
221 } temp;
222 } u;
223} AHCIPORTTASKSTATESGENTRY, *PAHCIPORTTASKSTATESGENTRY;
224
225/** Pointer to a pointer of a scatter gather list entry. */
226typedef PAHCIPORTTASKSTATESGENTRY *PPAHCIPORTTASKSTATESGENTRY;
227/** Pointer to a task state. */
228typedef struct AHCIPORTTASKSTATE *PAHCIPORTTASKSTATE;
229
230/**
231 * Data processing callback
232 *
233 * @returns VBox status.
234 * @param pAhciPortTaskState The task state.
235 */
236typedef DECLCALLBACK(int) FNAHCIPOSTPROCESS(PAHCIPORTTASKSTATE pAhciPortTaskState);
237/** Pointer to a FNAHCIPOSTPROCESS() function. */
238typedef FNAHCIPOSTPROCESS *PFNAHCIPOSTPROCESS;
239
240/**
241 * Transfer type.
242 */
243typedef enum AHCITXDIR
244{
245 /** Invalid */
246 AHCITXDIR_INVALID = 0,
247 /** None */
248 AHCITXDIR_NONE,
249 /** Read */
250 AHCITXDIR_READ,
251 /** Write */
252 AHCITXDIR_WRITE,
253 /** Flush */
254 AHCITXDIR_FLUSH
255} AHCITXDIR;
256
257/**
258 * A task state.
259 */
260typedef struct AHCIPORTTASKSTATE
261{
262 /** Tag of the task. */
263 uint32_t uTag;
264 /** Command is queued. */
265 bool fQueued;
266 /** The command header for this task. */
267 CmdHdr cmdHdr;
268 /** The command Fis for this task. */
269 uint8_t cmdFis[AHCI_CMDFIS_TYPE_H2D_SIZE];
270 /** The ATAPI command data. */
271 uint8_t aATAPICmd[ATAPI_PACKET_SIZE];
272 /** Size of one sector for the ATAPI transfer. */
273 size_t cbATAPISector;
274 /** Physical address of the command header. - GC */
275 RTGCPHYS GCPhysCmdHdrAddr;
276 /** Data direction. */
277 AHCITXDIR enmTxDir;
278 /** Start offset. */
279 uint64_t uOffset;
280 /** Number of bytes to transfer. */
281 uint32_t cbTransfer;
282 /** ATA error register */
283 uint8_t uATARegError;
284 /** ATA status register */
285 uint8_t uATARegStatus;
286 /** How many entries would fit into the sg list. */
287 uint32_t cSGListSize;
288 /** Number of used SG list entries. */
289 uint32_t cSGListUsed;
290 /** Pointer to the first entry of the scatter gather list. */
291 PRTSGSEG pSGListHead;
292 /** Number of scatter gather list entries. */
293 uint32_t cSGEntries;
294 /** Total number of bytes the guest reserved for this request.
295 * Sum of all SG entries. */
296 uint32_t cbSGBuffers;
297 /** Pointer to the first mapping information entry. */
298 PAHCIPORTTASKSTATESGENTRY paSGEntries;
299 /** Size of the temporary buffer for unaligned guest segments. */
300 uint32_t cbBufferUnaligned;
301 /** Pointer to the temporary buffer. */
302 void *pvBufferUnaligned;
303 /** Number of times in a row the scatter gather list was too big. */
304 uint32_t cSGListTooBig;
305 /** Post processing callback.
306 * If this is set we will use a buffer for the data
307 * and the callback copies the data to the destination. */
308 PFNAHCIPOSTPROCESS pfnPostProcess;
309#ifdef RT_STRICT
310 /** Flag whether the task state is currently active - used for debugging */
311 volatile bool fActive;
312#endif
313} AHCIPORTTASKSTATE;
314
315/**
316 * Notifier queue item.
317 */
318typedef struct DEVPORTNOTIFIERQUEUEITEM
319{
320 /** The core part owned by the queue manager. */
321 PDMQUEUEITEMCORE Core;
322 /** The port to process. */
323 uint8_t iPort;
324} DEVPORTNOTIFIERQUEUEITEM, *PDEVPORTNOTIFIERQUEUEITEM;
325
326
327/**
328 * @implements PDMIBASE
329 * @implements PDMIBLOCKPORT
330 * @implements PDMIBLOCKASYNCPORT
331 * @implements PDMIMOUNTNOTIFY
332 */
333typedef struct AHCIPort
334{
335 /** Pointer to the device instance - HC ptr */
336 PPDMDEVINSR3 pDevInsR3;
337 /** Pointer to the device instance - R0 ptr */
338 PPDMDEVINSR0 pDevInsR0;
339 /** Pointer to the device instance - RC ptr. */
340 PPDMDEVINSRC pDevInsRC;
341
342#if HC_ARCH_BITS == 64
343 uint32_t Alignment0;
344#endif
345
346 /** Pointer to the parent AHCI structure - R3 ptr. */
347 R3PTRTYPE(struct AHCI *) pAhciR3;
348 /** Pointer to the parent AHCI structure - R0 ptr. */
349 R0PTRTYPE(struct AHCI *) pAhciR0;
350 /** Pointer to the parent AHCI structure - RC ptr. */
351 RCPTRTYPE(struct AHCI *) pAhciRC;
352
353 /** Command List Base Address. */
354 uint32_t regCLB;
355 /** Command List Base Address upper bits. */
356 uint32_t regCLBU;
357 /** FIS Base Address. */
358 uint32_t regFB;
359 /** FIS Base Address upper bits. */
360 uint32_t regFBU;
361 /** Interrupt Status. */
362 volatile uint32_t regIS;
363 /** Interrupt Enable. */
364 uint32_t regIE;
365 /** Command. */
366 uint32_t regCMD;
367 /** Task File Data. */
368 uint32_t regTFD;
369 /** Signature */
370 uint32_t regSIG;
371 /** Serial ATA Status. */
372 uint32_t regSSTS;
373 /** Serial ATA Control. */
374 uint32_t regSCTL;
375 /** Serial ATA Error. */
376 uint32_t regSERR;
377 /** Serial ATA Active. */
378 volatile uint32_t regSACT;
379 /** Command Issue. */
380 uint32_t regCI;
381
382#if HC_ARCH_BITS == 64
383 uint32_t Alignment1;
384#endif
385
386 /** Command List Base Address */
387 volatile RTGCPHYS GCPhysAddrClb;
388 /** FIS Base Address */
389 volatile RTGCPHYS GCPhysAddrFb;
390 /** Current number of active tasks. */
391 volatile uint32_t cTasksActive;
392
393 /** Device is powered on. */
394 bool fPoweredOn;
395 /** Device has spun up. */
396 bool fSpunUp;
397 /** First D2H FIS was send. */
398 bool fFirstD2HFisSend;
399 /** Attached device is a CD/DVD drive. */
400 bool fATAPI;
401 /** Passthrough SCSI commands. */
402 bool fATAPIPassthrough;
403 /** Flag whether this port is in a reset state. */
404 volatile bool fPortReset;
405 /** If we use the new async interface. */
406 bool fAsyncInterface;
407 /** Flag if we are in a device reset. */
408 bool fResetDevice;
409 /** Flag whether the I/O thread idles. */
410 volatile bool fAsyncIOThreadIdle;
411 /** Flag whether the port is in redo task mode. */
412 volatile bool fRedo;
413
414#if HC_ARCH_BITS == 64
415 bool fAlignment2;
416#endif
417
418 /** Number of total sectors. */
419 uint64_t cTotalSectors;
420 /** Currently configured number of sectors in a multi-sector transfer. */
421 uint32_t cMultSectors;
422 /** Currently active transfer mode (MDMA/UDMA) and speed. */
423 uint8_t uATATransferMode;
424 /** ATAPI sense data. */
425 uint8_t abATAPISense[ATAPI_SENSE_SIZE];
426 /** HACK: Countdown till we report a newly unmounted drive as mounted. */
427 uint8_t cNotifiedMediaChange;
428 /** The same for GET_EVENT_STATUS for mechanism */
429 volatile uint32_t MediaEventStatus;
430 /** Media type if known. */
431 volatile uint32_t MediaTrackType;
432 /** The LUN. */
433 RTUINT iLUN;
434
435 /** Bitmap for finished tasks (R3 -> Guest). */
436 volatile uint32_t u32TasksFinished;
437 /** Bitmap for finished queued tasks (R3 -> Guest). */
438 volatile uint32_t u32QueuedTasksFinished;
439 /** Bitmap for new queued tasks (Guest -> R3). */
440 volatile uint32_t u32TasksNew;
441
442 /** Device specific settings (R3 only stuff). */
443 /** Pointer to the attached driver's base interface. */
444 R3PTRTYPE(PPDMIBASE) pDrvBase;
445 /** Pointer to the attached driver's block interface. */
446 R3PTRTYPE(PPDMIBLOCK) pDrvBlock;
447 /** Pointer to the attached driver's async block interface. */
448 R3PTRTYPE(PPDMIBLOCKASYNC) pDrvBlockAsync;
449 /** Pointer to the attached driver's block bios interface. */
450 R3PTRTYPE(PPDMIBLOCKBIOS) pDrvBlockBios;
451 /** Pointer to the attached driver's mount interface. */
452 R3PTRTYPE(PPDMIMOUNT) pDrvMount;
453 /** The base interface. */
454 PDMIBASE IBase;
455 /** The block port interface. */
456 PDMIBLOCKPORT IPort;
457 /** The optional block async port interface. */
458 PDMIBLOCKASYNCPORT IPortAsync;
459 /** The mount notify interface. */
460 PDMIMOUNTNOTIFY IMountNotify;
461 /** Physical geometry of this image. */
462 PDMMEDIAGEOMETRY PCHSGeometry;
463 /** The status LED state for this drive. */
464 PDMLED Led;
465
466#if HC_ARCH_BITS == 64
467 uint32_t u32Alignment3;
468#endif
469
470 /** Async IO Thread. */
471 R3PTRTYPE(PPDMTHREAD) pAsyncIOThread;
472 /** Request semaphore. */
473 RTSEMEVENT AsyncIORequestSem;
474 /**
475 * Array of cached tasks. The tag number is the index value.
476 * Only used with the async interface.
477 */
478 R3PTRTYPE(PAHCIPORTTASKSTATE) aCachedTasks[AHCI_NR_COMMAND_SLOTS];
479 /** First task throwing an error. */
480 R3PTRTYPE(volatile PAHCIPORTTASKSTATE) pTaskErr;
481
482 /** Release statistics: number of DMA commands. */
483 STAMCOUNTER StatDMA;
484 /** Release statistics: number of bytes written. */
485 STAMCOUNTER StatBytesWritten;
486 /** Release statistics: number of bytes read. */
487 STAMCOUNTER StatBytesRead;
488 /** Release statistics: Number of I/O requests processed per second. */
489 STAMCOUNTER StatIORequestsPerSecond;
490#ifdef VBOX_WITH_STATISTICS
491 /** Statistics: Time to complete one request. */
492 STAMPROFILE StatProfileProcessTime;
493 /** Statistics: Time to map requests into R3. */
494 STAMPROFILE StatProfileMapIntoR3;
495 /** Statistics: Amount of time to read/write data. */
496 STAMPROFILE StatProfileReadWrite;
497 /** Statistics: Amount of time to destroy a list. */
498 STAMPROFILE StatProfileDestroyScatterGatherList;
499#endif /* VBOX_WITH_STATISTICS */
500
501 /** The serial numnber to use for IDENTIFY DEVICE commands. */
502 char szSerialNumber[AHCI_SERIAL_NUMBER_LENGTH+1]; /** < one extra byte for termination */
503 /** The firmware revision to use for IDENTIFY DEVICE commands. */
504 char szFirmwareRevision[AHCI_FIRMWARE_REVISION_LENGTH+1]; /** < one extra byte for termination */
505 /** The model number to use for IDENTIFY DEVICE commands. */
506 char szModelNumber[AHCI_MODEL_NUMBER_LENGTH+1]; /** < one extra byte for termination */
507 /** The vendor identification string for SCSI INQUIRY commands. */
508 char szInquiryVendorId[AHCI_ATAPI_INQUIRY_VENDOR_ID_LENGTH+1];
509 /** The product identification string for SCSI INQUIRY commands. */
510 char szInquiryProductId[AHCI_ATAPI_INQUIRY_PRODUCT_ID_LENGTH+1];
511 /** The revision string for SCSI INQUIRY commands. */
512 char szInquiryRevision[AHCI_ATAPI_INQUIRY_REVISION_LENGTH+1];
513 /** Error counter */
514 uint32_t cErrors;
515
516 uint32_t u32Alignment4;
517} AHCIPort;
518/** Pointer to the state of an AHCI port. */
519typedef AHCIPort *PAHCIPort;
520
521/**
522 * Main AHCI device state.
523 *
524 * @implements PDMILEDPORTS
525 */
526typedef struct AHCI
527{
528 /** The PCI device structure. */
529 PCIDEVICE dev;
530 /** Pointer to the device instance - R3 ptr */
531 PPDMDEVINSR3 pDevInsR3;
532 /** Pointer to the device instance - R0 ptr */
533 PPDMDEVINSR0 pDevInsR0;
534 /** Pointer to the device instance - RC ptr. */
535 PPDMDEVINSRC pDevInsRC;
536
537#if HC_ARCH_BITS == 64
538 uint32_t Alignment0;
539#endif
540
541 /** Status LUN: The base interface. */
542 PDMIBASE IBase;
543 /** Status LUN: Leds interface. */
544 PDMILEDPORTS ILeds;
545 /** Status LUN: Partner of ILeds. */
546 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
547
548#if HC_ARCH_BITS == 64
549 uint32_t Alignment1[2];
550#endif
551
552 /** Base address of the MMIO region. */
553 RTGCPHYS MMIOBase;
554
555 /** Global Host Control register of the HBA */
556
557 /** HBA Capabilities - Readonly */
558 uint32_t regHbaCap;
559 /** HBA Control */
560 uint32_t regHbaCtrl;
561 /** Interrupt Status */
562 uint32_t regHbaIs;
563 /** Ports Implemented - Readonly */
564 uint32_t regHbaPi;
565 /** AHCI Version - Readonly */
566 uint32_t regHbaVs;
567 /** Command completion coalescing control */
568 uint32_t regHbaCccCtl;
569 /** Command completion coalescing ports */
570 uint32_t regHbaCccPorts;
571
572#if HC_ARCH_BITS == 64
573 uint32_t Alignment3;
574#endif
575
576 /** Countdown timer for command completion coalescing - R3 ptr */
577 PTMTIMERR3 pHbaCccTimerR3;
578 /** Countdown timer for command completion coalescing - R0 ptr */
579 PTMTIMERR0 pHbaCccTimerR0;
580 /** Countdown timer for command completion coalescing - RC ptr */
581 PTMTIMERRC pHbaCccTimerRC;
582
583#if HC_ARCH_BITS == 64
584 uint32_t Alignment4;
585#endif
586
587 /** Queue to send tasks to R3. - HC ptr */
588 R3PTRTYPE(PPDMQUEUE) pNotifierQueueR3;
589 /** Queue to send tasks to R3. - HC ptr */
590 R0PTRTYPE(PPDMQUEUE) pNotifierQueueR0;
591 /** Queue to send tasks to R3. - RC ptr */
592 RCPTRTYPE(PPDMQUEUE) pNotifierQueueRC;
593
594#if HC_ARCH_BITS == 64
595 uint32_t Alignment5;
596#endif
597
598
599 /** Which port number is used to mark an CCC interrupt */
600 uint8_t uCccPortNr;
601
602#if HC_ARCH_BITS == 64
603 uint32_t Alignment6;
604#endif
605
606 /** Timeout value */
607 uint64_t uCccTimeout;
608 /** Number of completions used to assert an interrupt */
609 uint32_t uCccNr;
610 /** Current number of completed commands */
611 uint32_t uCccCurrentNr;
612
613 /** Register structure per port */
614 AHCIPort ahciPort[AHCI_MAX_NR_PORTS_IMPL];
615
616 /** Needed values for the emulated ide channels. */
617 AHCIATACONTROLLER aCts[2];
618
619 /** The critical section. */
620 PDMCRITSECT lock;
621
622 /** Bitmask of ports which asserted an interrupt. */
623 volatile uint32_t u32PortsInterrupted;
624 /** Device is in a reset state. */
625 bool fReset;
626 /** Supports 64bit addressing */
627 bool f64BitAddr;
628 /** GC enabled. */
629 bool fGCEnabled;
630 /** R0 enabled. */
631 bool fR0Enabled;
632 /** If the new async interface is used if available. */
633 bool fUseAsyncInterfaceIfAvailable;
634 /** Indicates that PDMDevHlpAsyncNotificationCompleted should be called when
635 * a port is entering the idle state. */
636 bool volatile fSignalIdle;
637 /** Flag whether the controller has BIOS access enabled. */
638 bool fBootable;
639
640 /** Number of usable ports on this controller. */
641 uint32_t cPortsImpl;
642
643#if HC_ARCH_BITS == 64
644 uint32_t Alignment9;
645#endif
646
647 /** Flag whether we have written the first 4bytes in an 8byte MMIO write successfully. */
648 volatile bool f8ByteMMIO4BytesWrittenSuccessfully;
649
650} AHCI;
651/** Pointer to the state of an AHCI device. */
652typedef AHCI *PAHCI;
653
654/**
655 * Scatter gather list entry.
656 */
657typedef struct
658{
659 /** Data Base Address. */
660 uint32_t u32DBA;
661 /** Data Base Address - Upper 32-bits. */
662 uint32_t u32DBAUp;
663 /** Reserved */
664 uint32_t u32Reserved;
665 /** Description information. */
666 uint32_t u32DescInf;
667} SGLEntry;
668AssertCompileSize(SGLEntry, 16);
669
670/** Defines for a scatter gather list entry. */
671#define SGLENTRY_DBA_READONLY ~(RT_BIT(0))
672#define SGLENTRY_DESCINF_I RT_BIT(31)
673#define SGLENTRY_DESCINF_DBC 0x3fffff
674#define SGLENTRY_DESCINF_READONLY 0x803fffff
675
676/* Defines for the global host control registers for the HBA. */
677
678#define AHCI_HBA_GLOBAL_SIZE 0x100
679
680/* Defines for the HBA Capabilities - Readonly */
681#define AHCI_HBA_CAP_S64A RT_BIT(31)
682#define AHCI_HBA_CAP_SNCQ RT_BIT(30)
683#define AHCI_HBA_CAP_SIS RT_BIT(28)
684#define AHCI_HBA_CAP_SSS RT_BIT(27)
685#define AHCI_HBA_CAP_SALP RT_BIT(26)
686#define AHCI_HBA_CAP_SAL RT_BIT(25)
687#define AHCI_HBA_CAP_SCLO RT_BIT(24)
688#define AHCI_HBA_CAP_ISS (RT_BIT(23) | RT_BIT(22) | RT_BIT(21) | RT_BIT(20))
689# define AHCI_HBA_CAP_ISS_SHIFT(x) (((x) << 20) & AHCI_HBA_CAP_ISS)
690# define AHCI_HBA_CAP_ISS_GEN1 RT_BIT(0)
691# define AHCI_HBA_CAP_ISS_GEN2 RT_BIT(1)
692#define AHCI_HBA_CAP_SNZO RT_BIT(19)
693#define AHCI_HBA_CAP_SAM RT_BIT(18)
694#define AHCI_HBA_CAP_SPM RT_BIT(17)
695#define AHCI_HBA_CAP_PMD RT_BIT(15)
696#define AHCI_HBA_CAP_SSC RT_BIT(14)
697#define AHCI_HBA_CAP_PSC RT_BIT(13)
698#define AHCI_HBA_CAP_NCS (RT_BIT(12) | RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8))
699#define AHCI_HBA_CAP_NCS_SET(x) (((x-1) << 8) & AHCI_HBA_CAP_NCS) /* 0's based */
700#define AHCI_HBA_CAP_CCCS RT_BIT(7)
701#define AHCI_HBA_CAP_NP (RT_BIT(4) | RT_BIT(3) | RT_BIT(2) | RT_BIT(1) | RT_BIT(0))
702#define AHCI_HBA_CAP_NP_SET(x) ((x-1) & AHCI_HBA_CAP_NP) /* 0's based */
703
704/* Defines for the HBA Control register - Read/Write */
705#define AHCI_HBA_CTRL_AE RT_BIT(31)
706#define AHCI_HBA_CTRL_IE RT_BIT(1)
707#define AHCI_HBA_CTRL_HR RT_BIT(0)
708#define AHCI_HBA_CTRL_RW_MASK (RT_BIT(0) | RT_BIT(1)) /* Mask for the used bits */
709
710/* Defines for the HBA Version register - Readonly (We support AHCI 1.0) */
711#define AHCI_HBA_VS_MJR (1 << 16)
712#define AHCI_HBA_VS_MNR 0x100
713
714/* Defines for the command completion coalescing control register */
715#define AHCI_HBA_CCC_CTL_TV 0xffff0000
716#define AHCI_HBA_CCC_CTL_TV_SET(x) (x << 16)
717#define AHCI_HBA_CCC_CTL_TV_GET(x) ((x & AHCI_HBA_CCC_CTL_TV) >> 16)
718
719#define AHCI_HBA_CCC_CTL_CC 0xff00
720#define AHCI_HBA_CCC_CTL_CC_SET(x) (x << 8)
721#define AHCI_HBA_CCC_CTL_CC_GET(x) ((x & AHCI_HBA_CCC_CTL_CC) >> 8)
722
723#define AHCI_HBA_CCC_CTL_INT 0xf8
724#define AHCI_HBA_CCC_CTL_INT_SET(x) (x << 3)
725#define AHCI_HBA_CCC_CTL_INT_GET(x) ((x & AHCI_HBA_CCC_CTL_INT) >> 3)
726
727#define AHCI_HBA_CCC_CTL_EN RT_BIT(0)
728
729/* Defines for the port registers. */
730
731#define AHCI_PORT_REGISTER_SIZE 0x80
732
733#define AHCI_PORT_CLB_RESERVED 0xfffffc00 /* For masking out the reserved bits. */
734
735#define AHCI_PORT_FB_RESERVED 0x7fffff00 /* For masking out the reserved bits. */
736
737#define AHCI_PORT_IS_CPDS RT_BIT(31)
738#define AHCI_PORT_IS_TFES RT_BIT(30)
739#define AHCI_PORT_IS_HBFS RT_BIT(29)
740#define AHCI_PORT_IS_HBDS RT_BIT(28)
741#define AHCI_PORT_IS_IFS RT_BIT(27)
742#define AHCI_PORT_IS_INFS RT_BIT(26)
743#define AHCI_PORT_IS_OFS RT_BIT(24)
744#define AHCI_PORT_IS_IPMS RT_BIT(23)
745#define AHCI_PORT_IS_PRCS RT_BIT(22)
746#define AHCI_PORT_IS_DIS RT_BIT(7)
747#define AHCI_PORT_IS_PCS RT_BIT(6)
748#define AHCI_PORT_IS_DPS RT_BIT(5)
749#define AHCI_PORT_IS_UFS RT_BIT(4)
750#define AHCI_PORT_IS_SDBS RT_BIT(3)
751#define AHCI_PORT_IS_DSS RT_BIT(2)
752#define AHCI_PORT_IS_PSS RT_BIT(1)
753#define AHCI_PORT_IS_DHRS RT_BIT(0)
754#define AHCI_PORT_IS_READONLY 0xfd8000af /* Readonly mask including reserved bits. */
755
756#define AHCI_PORT_IE_CPDE RT_BIT(31)
757#define AHCI_PORT_IE_TFEE RT_BIT(30)
758#define AHCI_PORT_IE_HBFE RT_BIT(29)
759#define AHCI_PORT_IE_HBDE RT_BIT(28)
760#define AHCI_PORT_IE_IFE RT_BIT(27)
761#define AHCI_PORT_IE_INFE RT_BIT(26)
762#define AHCI_PORT_IE_OFE RT_BIT(24)
763#define AHCI_PORT_IE_IPME RT_BIT(23)
764#define AHCI_PORT_IE_PRCE RT_BIT(22)
765#define AHCI_PORT_IE_DIE RT_BIT(7) /* Not supported for now, readonly. */
766#define AHCI_PORT_IE_PCE RT_BIT(6)
767#define AHCI_PORT_IE_DPE RT_BIT(5)
768#define AHCI_PORT_IE_UFE RT_BIT(4)
769#define AHCI_PORT_IE_SDBE RT_BIT(3)
770#define AHCI_PORT_IE_DSE RT_BIT(2)
771#define AHCI_PORT_IE_PSE RT_BIT(1)
772#define AHCI_PORT_IE_DHRE RT_BIT(0)
773#define AHCI_PORT_IE_READONLY (0xfdc000ff) /* Readonly mask including reserved bits. */
774
775#define AHCI_PORT_CMD_ICC (RT_BIT(28) | RT_BIT(29) | RT_BIT(30) | RT_BIT(31))
776#define AHCI_PORT_CMD_ICC_SHIFT(x) ((x) << 28)
777# define AHCI_PORT_CMD_ICC_IDLE 0x0
778# define AHCI_PORT_CMD_ICC_ACTIVE 0x1
779# define AHCI_PORT_CMD_ICC_PARTIAL 0x2
780# define AHCI_PORT_CMD_ICC_SLUMBER 0x6
781#define AHCI_PORT_CMD_ASP RT_BIT(27) /* Not supported - Readonly */
782#define AHCI_PORT_CMD_ALPE RT_BIT(26) /* Not supported - Readonly */
783#define AHCI_PORT_CMD_DLAE RT_BIT(25)
784#define AHCI_PORT_CMD_ATAPI RT_BIT(24)
785#define AHCI_PORT_CMD_CPD RT_BIT(20)
786#define AHCI_PORT_CMD_ISP RT_BIT(19) /* Readonly */
787#define AHCI_PORT_CMD_HPCP RT_BIT(18)
788#define AHCI_PORT_CMD_PMA RT_BIT(17) /* Not supported - Readonly */
789#define AHCI_PORT_CMD_CPS RT_BIT(16)
790#define AHCI_PORT_CMD_CR RT_BIT(15) /* Readonly */
791#define AHCI_PORT_CMD_FR RT_BIT(14) /* Readonly */
792#define AHCI_PORT_CMD_ISS RT_BIT(13) /* Readonly */
793#define AHCI_PORT_CMD_CCS (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11) | RT_BIT(12))
794#define AHCI_PORT_CMD_CCS_SHIFT(x) (x << 8) /* Readonly */
795#define AHCI_PORT_CMD_FRE RT_BIT(4)
796#define AHCI_PORT_CMD_CLO RT_BIT(3)
797#define AHCI_PORT_CMD_POD RT_BIT(2)
798#define AHCI_PORT_CMD_SUD RT_BIT(1)
799#define AHCI_PORT_CMD_ST RT_BIT(0)
800#define AHCI_PORT_CMD_READONLY (0xff02001f & ~(AHCI_PORT_CMD_ASP | AHCI_PORT_CMD_ALPE | AHCI_PORT_CMD_PMA))
801
802#define AHCI_PORT_SCTL_IPM (RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8))
803#define AHCI_PORT_SCTL_IPM_GET(x) ((x & AHCI_PORT_SCTL_IPM) >> 8)
804#define AHCI_PORT_SCTL_SPD (RT_BIT(7) | RT_BIT(6) | RT_BIT(5) | RT_BIT(4))
805#define AHCI_PORT_SCTL_SPD_GET(x) ((x & AHCI_PORT_SCTL_SPD) >> 4)
806#define AHCI_PORT_SCTL_DET (RT_BIT(3) | RT_BIT(2) | RT_BIT(1) | RT_BIT(0))
807#define AHCI_PORT_SCTL_DET_GET(x) (x & AHCI_PORT_SCTL_DET)
808#define AHCI_PORT_SCTL_DET_NINIT 0
809#define AHCI_PORT_SCTL_DET_INIT 1
810#define AHCI_PORT_SCTL_DET_OFFLINE 4
811#define AHCI_PORT_SCTL_READONLY 0xfff
812
813#define AHCI_PORT_SSTS_IPM (RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8))
814#define AHCI_PORT_SSTS_IPM_GET(x) ((x & AHCI_PORT_SCTL_IPM) >> 8)
815#define AHCI_PORT_SSTS_SPD (RT_BIT(7) | RT_BIT(6) | RT_BIT(5) | RT_BIT(4))
816#define AHCI_PORT_SSTS_SPD_GET(x) ((x & AHCI_PORT_SCTL_SPD) >> 4)
817#define AHCI_PORT_SSTS_DET (RT_BIT(3) | RT_BIT(2) | RT_BIT(1) | RT_BIT(0))
818#define AHCI_PORT_SSTS_DET_GET(x) (x & AHCI_PORT_SCTL_DET)
819
820#define AHCI_PORT_TFD_BSY RT_BIT(7)
821#define AHCI_PORT_TFD_DRQ RT_BIT(3)
822#define AHCI_PORT_TFD_ERR RT_BIT(0)
823
824#define AHCI_PORT_SERR_X RT_BIT(26)
825#define AHCI_PORT_SERR_W RT_BIT(18)
826#define AHCI_PORT_SERR_N RT_BIT(16)
827
828/* Signatures for attached storage devices. */
829#define AHCI_PORT_SIG_DISK 0x00000101
830#define AHCI_PORT_SIG_ATAPI 0xeb140101
831
832/*
833 * The AHCI spec defines an area of memory where the HBA posts received FIS's from the device.
834 * regFB points to the base of this area.
835 * Every FIS type has an offset where it is posted in this area.
836 */
837#define AHCI_RECFIS_DSFIS_OFFSET 0x00 /* DMA Setup FIS */
838#define AHCI_RECFIS_PSFIS_OFFSET 0x20 /* PIO Setup FIS */
839#define AHCI_RECFIS_RFIS_OFFSET 0x40 /* D2H Register FIS */
840#define AHCI_RECFIS_SDBFIS_OFFSET 0x58 /* Set Device Bits FIS */
841#define AHCI_RECFIS_UFIS_OFFSET 0x60 /* Unknown FIS type */
842
843/**
844 * AHCI register operator.
845 */
846typedef struct ahci_opreg
847{
848 const char *pszName;
849 int (*pfnRead )(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value);
850 int (*pfnWrite)(PAHCI ahci, uint32_t iReg, uint32_t u32Value);
851} AHCIOPREG;
852
853/**
854 * AHCI port register operator.
855 */
856typedef struct pAhciPort_opreg
857{
858 const char *pszName;
859 int (*pfnRead )(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value);
860 int (*pfnWrite)(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value);
861} AHCIPORTOPREG;
862
863#ifndef VBOX_DEVICE_STRUCT_TESTCASE
864RT_C_DECLS_BEGIN
865PDMBOTHCBDECL(int) ahciMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
866PDMBOTHCBDECL(int) ahciMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
867static void ahciHBAReset(PAHCI pThis);
868PDMBOTHCBDECL(int) ahciIOPortWrite1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
869PDMBOTHCBDECL(int) ahciIOPortRead1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
870PDMBOTHCBDECL(int) ahciIOPortWrite2(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
871PDMBOTHCBDECL(int) ahciIOPortRead2(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
872PDMBOTHCBDECL(int) ahciLegacyFakeWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
873PDMBOTHCBDECL(int) ahciLegacyFakeRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
874#ifdef IN_RING3
875static int ahciPostFisIntoMemory(PAHCIPort pAhciPort, unsigned uFisType, uint8_t *cmdFis);
876static void ahciPostFirstD2HFisIntoMemory(PAHCIPort pAhciPort);
877static int ahciScatterGatherListCopyFromBuffer(PAHCIPORTTASKSTATE pAhciPortTaskState, void *pvBuf, size_t cbBuf);
878static int ahciScatterGatherListCreate(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState, bool fReadonly);
879static int ahciScatterGatherListDestroy(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState);
880static void ahciCopyFromBufferIntoSGList(PPDMDEVINS pDevIns, PAHCIPORTTASKSTATESGENTRY pSGInfo);
881static void ahciCopyFromSGListIntoBuffer(PPDMDEVINS pDevIns, PAHCIPORTTASKSTATESGENTRY pSGInfo);
882static void ahciScatterGatherListGetTotalBufferSize(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState);
883static int ahciScatterGatherListCreateSafe(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState,
884 bool fReadonly, unsigned cSGEntriesProcessed);
885#endif
886RT_C_DECLS_END
887
888#define PCIDEV_2_PAHCI(pPciDev) ( (PAHCI)(pPciDev) )
889#define PDMIMOUNT_2_PAHCIPORT(pInterface) ( (PAHCIPort)((uintptr_t)(pInterface) - RT_OFFSETOF(AHCIPort, IMount)) )
890#define PDMIMOUNTNOTIFY_2_PAHCIPORT(pInterface) ( (PAHCIPort)((uintptr_t)(pInterface) - RT_OFFSETOF(AHCIPort, IMountNotify)) )
891#define PDMIBASE_2_PAHCIPORT(pInterface) ( (PAHCIPort)((uintptr_t)(pInterface) - RT_OFFSETOF(AHCIPort, IBase)) )
892#define PDMIBLOCKPORT_2_PAHCIPORT(pInterface) ( (PAHCIPort)((uintptr_t)(pInterface) - RT_OFFSETOF(AHCIPort, IPort)) )
893#define PDMIBASE_2_PAHCI(pInterface) ( (PAHCI)((uintptr_t)(pInterface) - RT_OFFSETOF(AHCI, IBase)) )
894#define PDMILEDPORTS_2_PAHCI(pInterface) ( (PAHCI)((uintptr_t)(pInterface) - RT_OFFSETOF(AHCI, ILeds)) )
895
896#if 1
897#define AHCI_RTGCPHYS_FROM_U32(Hi, Lo) ( (RTGCPHYS)RT_MAKE_U64(Lo, Hi) )
898#else
899#define AHCI_RTGCPHYS_FROM_U32(Hi, Lo) ( (RTGCPHYS)(Lo) )
900#endif
901
902#ifdef IN_RING3
903
904# ifdef LOG_USE_C99
905# define ahciLog(a) \
906 Log(("R3 P%u: %M", pAhciPort->iLUN, _LogRelRemoveParentheseis a))
907# else
908# define ahciLog(a) \
909 do { Log(("R3 P%u: ", pAhciPort->iLUN)); Log(a); } while(0)
910# endif
911
912#elif IN_RING0
913
914# ifdef LOG_USE_C99
915# define ahciLog(a) \
916 Log(("R0 P%u: %M", pAhciPort->iLUN, _LogRelRemoveParentheseis a))
917# else
918# define ahciLog(a) \
919 do { Log(("R0 P%u: ", pAhciPort->iLUN)); Log(a); } while(0)
920# endif
921
922#elif IN_RC
923
924# ifdef LOG_USE_C99
925# define ahciLog(a) \
926 Log(("GC P%u: %M", pAhciPort->iLUN, _LogRelRemoveParentheseis a))
927# else
928# define ahciLog(a) \
929 do { Log(("GC P%u: ", pAhciPort->iLUN)); Log(a); } while(0)
930# endif
931
932#endif
933
934/**
935 * Update PCI IRQ levels
936 */
937static void ahciHbaClearInterrupt(PAHCI pAhci)
938{
939 Log(("%s: Clearing interrupt\n", __FUNCTION__));
940 PDMDevHlpPCISetIrq(pAhci->CTX_SUFF(pDevIns), 0, 0);
941}
942
943/**
944 * Updates the IRQ level and sets port bit in the global interrupt status register of the HBA.
945 */
946static int ahciHbaSetInterrupt(PAHCI pAhci, uint8_t iPort, int rcBusy)
947{
948 Log(("P%u: %s: Setting interrupt\n", iPort, __FUNCTION__));
949
950 int rc = PDMCritSectEnter(&pAhci->lock, rcBusy);
951 if (rc != VINF_SUCCESS)
952 return rc;
953
954 if (pAhci->regHbaCtrl & AHCI_HBA_CTRL_IE)
955 {
956 if ((pAhci->regHbaCccCtl & AHCI_HBA_CCC_CTL_EN) && (pAhci->regHbaCccPorts & (1 << iPort)))
957 {
958 pAhci->uCccCurrentNr++;
959 if (pAhci->uCccCurrentNr >= pAhci->uCccNr)
960 {
961 /* Reset command completion coalescing state. */
962 TMTimerSetMillies(pAhci->CTX_SUFF(pHbaCccTimer), pAhci->uCccTimeout);
963 pAhci->uCccCurrentNr = 0;
964
965 pAhci->u32PortsInterrupted |= (1 << pAhci->uCccPortNr);
966 if (!(pAhci->u32PortsInterrupted & ~(1 << pAhci->uCccPortNr)))
967 {
968 Log(("P%u: %s: Fire interrupt\n", iPort, __FUNCTION__));
969 PDMDevHlpPCISetIrq(pAhci->CTX_SUFF(pDevIns), 0, 1);
970 }
971 }
972 }
973 else
974 {
975 /* If only the bit of the actual port is set assert an interrupt
976 * because the interrupt status register was already read by the guest
977 * and we need to send a new notification.
978 * Otherwise an interrupt is still pending.
979 */
980 ASMAtomicOrU32((volatile uint32_t *)&pAhci->u32PortsInterrupted, (1 << iPort));
981 if (!(pAhci->u32PortsInterrupted & ~(1 << iPort)))
982 {
983 Log(("P%u: %s: Fire interrupt\n", iPort, __FUNCTION__));
984 PDMDevHlpPCISetIrq(pAhci->CTX_SUFF(pDevIns), 0, 1);
985 }
986 }
987 }
988
989 PDMCritSectLeave(&pAhci->lock);
990 return VINF_SUCCESS;
991}
992
993#ifdef IN_RING3
994/*
995 * Assert irq when an CCC timeout occurs
996 */
997DECLCALLBACK(void) ahciCccTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
998{
999 PAHCI pAhci = (PAHCI)pvUser;
1000
1001 int rc = ahciHbaSetInterrupt(pAhci, pAhci->uCccPortNr, VERR_IGNORED);
1002 AssertRC(rc);
1003}
1004#endif
1005
1006static int PortCmdIssue_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1007{
1008 uint32_t uCIValue;
1009
1010 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1011
1012 /* Update the CI register first. */
1013 uCIValue = ASMAtomicXchgU32(&pAhciPort->u32TasksFinished, 0);
1014 pAhciPort->regCI &= ~uCIValue;
1015
1016 if ( (pAhciPort->regCMD & AHCI_PORT_CMD_ST)
1017 && u32Value > 0)
1018 {
1019 uint32_t u32Tasks;
1020
1021 /*
1022 * Clear all tasks which are already marked as busy. The guest
1023 * shouldn't write already busy tasks actually.
1024 */
1025 u32Value &= ~pAhciPort->regCI;
1026
1027 ASMAtomicOrU32(&pAhciPort->u32TasksNew, u32Value);
1028 u32Tasks = ASMAtomicReadU32(&pAhciPort->u32TasksNew);
1029
1030 /* Send a notification to R3 if u32TasksNew was before our write. */
1031 if (!(u32Tasks ^ u32Value))
1032 {
1033 PDEVPORTNOTIFIERQUEUEITEM pItem = (PDEVPORTNOTIFIERQUEUEITEM)PDMQueueAlloc(ahci->CTX_SUFF(pNotifierQueue));
1034 AssertMsg(VALID_PTR(pItem), ("Allocating item for queue failed\n"));
1035
1036 pItem->iPort = pAhciPort->iLUN;
1037 PDMQueueInsert(ahci->CTX_SUFF(pNotifierQueue), (PPDMQUEUEITEMCORE)pItem);
1038 }
1039 }
1040
1041 pAhciPort->regCI |= u32Value;
1042
1043 return VINF_SUCCESS;
1044}
1045
1046static int PortCmdIssue_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1047{
1048 uint32_t uCIValue = 0;
1049
1050 uCIValue = ASMAtomicXchgU32(&pAhciPort->u32TasksFinished, 0);
1051
1052 ahciLog(("%s: read regCI=%#010x uCIValue=%#010x\n", __FUNCTION__, pAhciPort->regCI, uCIValue));
1053
1054 pAhciPort->regCI &= ~uCIValue;
1055
1056 *pu32Value = pAhciPort->regCI;
1057
1058 return VINF_SUCCESS;
1059}
1060
1061static int PortSActive_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1062{
1063 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1064
1065 pAhciPort->regSACT |= u32Value;
1066
1067 return VINF_SUCCESS;
1068}
1069
1070static int PortSActive_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1071{
1072 uint32_t u32TasksFinished = ASMAtomicXchgU32(&pAhciPort->u32QueuedTasksFinished, 0);
1073
1074 pAhciPort->regSACT &= ~u32TasksFinished;
1075
1076 ahciLog(("%s: read regSACT=%#010x regCI=%#010x u32TasksFinished=%#010x\n",
1077 __FUNCTION__, pAhciPort->regSACT, pAhciPort->regCI, u32TasksFinished));
1078
1079 *pu32Value = pAhciPort->regSACT;
1080
1081 return VINF_SUCCESS;
1082}
1083
1084static int PortSError_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1085{
1086 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1087
1088 if ( (u32Value & AHCI_PORT_SERR_X)
1089 && (pAhciPort->regSERR & AHCI_PORT_SERR_X))
1090 {
1091 ASMAtomicAndU32(&pAhciPort->regIS, ~AHCI_PORT_IS_PCS);
1092 pAhciPort->regTFD |= ATA_STAT_ERR;
1093 pAhciPort->regTFD &= ~(ATA_STAT_DRQ | ATA_STAT_BUSY);
1094 }
1095
1096 pAhciPort->regSERR &= ~u32Value;
1097
1098 return VINF_SUCCESS;
1099}
1100
1101static int PortSError_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1102{
1103 ahciLog(("%s: read regSERR=%#010x\n", __FUNCTION__, pAhciPort->regSERR));
1104 *pu32Value = pAhciPort->regSERR;
1105 return VINF_SUCCESS;
1106}
1107
1108static int PortSControl_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1109{
1110 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1111 ahciLog(("%s: IPM=%d SPD=%d DET=%d\n", __FUNCTION__,
1112 AHCI_PORT_SCTL_IPM_GET(u32Value), AHCI_PORT_SCTL_SPD_GET(u32Value), AHCI_PORT_SCTL_DET_GET(u32Value)));
1113
1114 if ((u32Value & AHCI_PORT_SCTL_DET) == AHCI_PORT_SCTL_DET_INIT)
1115 {
1116 ASMAtomicXchgBool(&pAhciPort->fPortReset, true);
1117 pAhciPort->regSSTS = 0;
1118 pAhciPort->regSIG = ~0;
1119 pAhciPort->regTFD = 0x7f;
1120 pAhciPort->fFirstD2HFisSend = false;
1121 }
1122 else if ((u32Value & AHCI_PORT_SCTL_DET) == AHCI_PORT_SCTL_DET_NINIT && pAhciPort->pDrvBase &&
1123 (pAhciPort->regSCTL & AHCI_PORT_SCTL_DET) == AHCI_PORT_SCTL_DET_INIT)
1124 {
1125#ifndef IN_RING3
1126 return VINF_IOM_HC_MMIO_WRITE;
1127#else
1128 if (pAhciPort->pDrvBase)
1129 {
1130 ASMAtomicXchgBool(&pAhciPort->fPortReset, false);
1131
1132 /* Signature for SATA device. */
1133 if (pAhciPort->fATAPI)
1134 pAhciPort->regSIG = AHCI_PORT_SIG_ATAPI;
1135 else
1136 pAhciPort->regSIG = AHCI_PORT_SIG_DISK;
1137
1138 pAhciPort->regSSTS = (0x01 << 8) | /* Interface is active. */
1139 (0x03 << 0); /* Device detected and communication established. */
1140
1141 /*
1142 * Use the maximum allowed speed.
1143 * (Not that it changes anything really)
1144 */
1145 switch (AHCI_PORT_SCTL_SPD_GET(pAhciPort->regSCTL))
1146 {
1147 case 0x01:
1148 pAhciPort->regSSTS |= (0x01 << 4); /* Generation 1 (1.5GBps) speed. */
1149 break;
1150 case 0x02:
1151 case 0x00:
1152 default:
1153 pAhciPort->regSSTS |= (0x02 << 4); /* Generation 2 (3.0GBps) speed. */
1154 break;
1155 }
1156
1157 /* We received a COMINIT from the device. Tell the guest. */
1158 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_PCS);
1159 pAhciPort->regSERR |= AHCI_PORT_SERR_X;
1160 pAhciPort->regTFD |= ATA_STAT_BUSY;
1161
1162 if ((pAhciPort->regCMD & AHCI_PORT_CMD_FRE) && (!pAhciPort->fFirstD2HFisSend))
1163 {
1164 ahciPostFirstD2HFisIntoMemory(pAhciPort);
1165 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_DHRS);
1166
1167 if (pAhciPort->regIE & AHCI_PORT_IE_DHRE)
1168 {
1169 int rc = ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN, VERR_IGNORED);
1170 AssertRC(rc);
1171 }
1172 }
1173 }
1174#endif
1175 }
1176
1177 pAhciPort->regSCTL = u32Value;
1178
1179 return VINF_SUCCESS;
1180}
1181
1182static int PortSControl_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1183{
1184 ahciLog(("%s: read regSCTL=%#010x\n", __FUNCTION__, pAhciPort->regSCTL));
1185 ahciLog(("%s: IPM=%d SPD=%d DET=%d\n", __FUNCTION__,
1186 AHCI_PORT_SCTL_IPM_GET(pAhciPort->regSCTL), AHCI_PORT_SCTL_SPD_GET(pAhciPort->regSCTL),
1187 AHCI_PORT_SCTL_DET_GET(pAhciPort->regSCTL)));
1188
1189 *pu32Value = pAhciPort->regSCTL;
1190 return VINF_SUCCESS;
1191}
1192
1193static int PortSStatus_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1194{
1195 ahciLog(("%s: read regSSTS=%#010x\n", __FUNCTION__, pAhciPort->regSSTS));
1196 ahciLog(("%s: IPM=%d SPD=%d DET=%d\n", __FUNCTION__,
1197 AHCI_PORT_SSTS_IPM_GET(pAhciPort->regSSTS), AHCI_PORT_SSTS_SPD_GET(pAhciPort->regSSTS),
1198 AHCI_PORT_SSTS_DET_GET(pAhciPort->regSSTS)));
1199
1200 *pu32Value = pAhciPort->regSSTS;
1201 return VINF_SUCCESS;
1202}
1203
1204static int PortSignature_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1205{
1206 ahciLog(("%s: read regSIG=%#010x\n", __FUNCTION__, pAhciPort->regSIG));
1207 *pu32Value = pAhciPort->regSIG;
1208 return VINF_SUCCESS;
1209}
1210
1211static int PortTaskFileData_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1212{
1213 ahciLog(("%s: read regTFD=%#010x\n", __FUNCTION__, pAhciPort->regTFD));
1214 ahciLog(("%s: ERR=%x BSY=%d DRQ=%d ERR=%d\n", __FUNCTION__,
1215 (pAhciPort->regTFD >> 8), (pAhciPort->regTFD & AHCI_PORT_TFD_BSY) >> 7,
1216 (pAhciPort->regTFD & AHCI_PORT_TFD_DRQ) >> 3, (pAhciPort->regTFD & AHCI_PORT_TFD_ERR)));
1217 *pu32Value = pAhciPort->regTFD;
1218 return VINF_SUCCESS;
1219}
1220
1221/**
1222 * Read from the port command register.
1223 */
1224static int PortCmd_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1225{
1226 ahciLog(("%s: read regCMD=%#010x\n", __FUNCTION__, pAhciPort->regCMD));
1227 ahciLog(("%s: ICC=%d ASP=%d ALPE=%d DLAE=%d ATAPI=%d CPD=%d ISP=%d HPCP=%d PMA=%d CPS=%d CR=%d FR=%d ISS=%d CCS=%d FRE=%d CLO=%d POD=%d SUD=%d ST=%d\n",
1228 __FUNCTION__, (pAhciPort->regCMD & AHCI_PORT_CMD_ICC) >> 28, (pAhciPort->regCMD & AHCI_PORT_CMD_ASP) >> 27,
1229 (pAhciPort->regCMD & AHCI_PORT_CMD_ALPE) >> 26, (pAhciPort->regCMD & AHCI_PORT_CMD_DLAE) >> 25,
1230 (pAhciPort->regCMD & AHCI_PORT_CMD_ATAPI) >> 24, (pAhciPort->regCMD & AHCI_PORT_CMD_CPD) >> 20,
1231 (pAhciPort->regCMD & AHCI_PORT_CMD_ISP) >> 19, (pAhciPort->regCMD & AHCI_PORT_CMD_HPCP) >> 18,
1232 (pAhciPort->regCMD & AHCI_PORT_CMD_PMA) >> 17, (pAhciPort->regCMD & AHCI_PORT_CMD_CPS) >> 16,
1233 (pAhciPort->regCMD & AHCI_PORT_CMD_CR) >> 15, (pAhciPort->regCMD & AHCI_PORT_CMD_FR) >> 14,
1234 (pAhciPort->regCMD & AHCI_PORT_CMD_ISS) >> 13, (pAhciPort->regCMD & AHCI_PORT_CMD_CCS) >> 8,
1235 (pAhciPort->regCMD & AHCI_PORT_CMD_FRE) >> 4, (pAhciPort->regCMD & AHCI_PORT_CMD_CLO) >> 3,
1236 (pAhciPort->regCMD & AHCI_PORT_CMD_POD) >> 2, (pAhciPort->regCMD & AHCI_PORT_CMD_SUD) >> 1,
1237 (pAhciPort->regCMD & AHCI_PORT_CMD_ST)));
1238 *pu32Value = pAhciPort->regCMD;
1239 return VINF_SUCCESS;
1240}
1241
1242/**
1243 * Write to the port command register.
1244 * This is the register where all the data transfer is started
1245 */
1246static int PortCmd_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1247{
1248 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1249 ahciLog(("%s: ICC=%d ASP=%d ALPE=%d DLAE=%d ATAPI=%d CPD=%d ISP=%d HPCP=%d PMA=%d CPS=%d CR=%d FR=%d ISS=%d CCS=%d FRE=%d CLO=%d POD=%d SUD=%d ST=%d\n",
1250 __FUNCTION__, (u32Value & AHCI_PORT_CMD_ICC) >> 28, (u32Value & AHCI_PORT_CMD_ASP) >> 27,
1251 (u32Value & AHCI_PORT_CMD_ALPE) >> 26, (u32Value & AHCI_PORT_CMD_DLAE) >> 25,
1252 (u32Value & AHCI_PORT_CMD_ATAPI) >> 24, (u32Value & AHCI_PORT_CMD_CPD) >> 20,
1253 (u32Value & AHCI_PORT_CMD_ISP) >> 19, (u32Value & AHCI_PORT_CMD_HPCP) >> 18,
1254 (u32Value & AHCI_PORT_CMD_PMA) >> 17, (u32Value & AHCI_PORT_CMD_CPS) >> 16,
1255 (u32Value & AHCI_PORT_CMD_CR) >> 15, (u32Value & AHCI_PORT_CMD_FR) >> 14,
1256 (u32Value & AHCI_PORT_CMD_ISS) >> 13, (u32Value & AHCI_PORT_CMD_CCS) >> 8,
1257 (u32Value & AHCI_PORT_CMD_FRE) >> 4, (u32Value & AHCI_PORT_CMD_CLO) >> 3,
1258 (u32Value & AHCI_PORT_CMD_POD) >> 2, (u32Value & AHCI_PORT_CMD_SUD) >> 1,
1259 (u32Value & AHCI_PORT_CMD_ST)));
1260
1261 if (pAhciPort->fPoweredOn && pAhciPort->fSpunUp)
1262 {
1263 if (u32Value & AHCI_PORT_CMD_CLO)
1264 {
1265 ahciLog(("%s: Command list override requested\n", __FUNCTION__));
1266 u32Value &= ~(AHCI_PORT_TFD_BSY | AHCI_PORT_TFD_DRQ);
1267 /* Clear the CLO bit. */
1268 u32Value &= ~(AHCI_PORT_CMD_CLO);
1269 }
1270
1271 if (u32Value & AHCI_PORT_CMD_ST)
1272 {
1273 ahciLog(("%s: Engine starts\n", __FUNCTION__));
1274
1275 /** Set engine state to running. */
1276 u32Value |= AHCI_PORT_CMD_CR;
1277 }
1278 else
1279 {
1280 ahciLog(("%s: Engine stops\n", __FUNCTION__));
1281 /* Clear command issue register. */
1282 pAhciPort->regCI = 0;
1283 /** Clear current command slot. */
1284 u32Value &= ~(AHCI_PORT_CMD_CCS_SHIFT(0xff));
1285 u32Value &= ~AHCI_PORT_CMD_CR;
1286 }
1287 }
1288 else if (pAhciPort->pDrvBase)
1289 {
1290 if ((u32Value & AHCI_PORT_CMD_POD) && (pAhciPort->regCMD & AHCI_PORT_CMD_CPS) && !pAhciPort->fPoweredOn)
1291 {
1292 ahciLog(("%s: Power on the device\n", __FUNCTION__));
1293 pAhciPort->fPoweredOn = true;
1294
1295 /*
1296 * Set states in the Port Signature and SStatus registers.
1297 */
1298 if (pAhciPort->fATAPI)
1299 pAhciPort->regSIG = AHCI_PORT_SIG_ATAPI;
1300 else
1301 pAhciPort->regSIG = AHCI_PORT_SIG_DISK;
1302 pAhciPort->regSSTS = (0x01 << 8) | /* Interface is active. */
1303 (0x02 << 4) | /* Generation 2 (3.0GBps) speed. */
1304 (0x03 << 0); /* Device detected and communication established. */
1305
1306 if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
1307 {
1308#ifndef IN_RING3
1309 return VINF_IOM_HC_MMIO_WRITE;
1310#else
1311 ahciPostFirstD2HFisIntoMemory(pAhciPort);
1312 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_DHRS);
1313
1314 if (pAhciPort->regIE & AHCI_PORT_IE_DHRE)
1315 {
1316 int rc = ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN, VERR_IGNORED);
1317 AssertRC(rc);
1318 }
1319#endif
1320 }
1321 }
1322
1323 if ((u32Value & AHCI_PORT_CMD_SUD) && pAhciPort->fPoweredOn && !pAhciPort->fSpunUp)
1324 {
1325 ahciLog(("%s: Spin up the device\n", __FUNCTION__));
1326 pAhciPort->fSpunUp = true;
1327 }
1328 }
1329
1330 if (u32Value & AHCI_PORT_CMD_FRE)
1331 {
1332 ahciLog(("%s: FIS receive enabled\n", __FUNCTION__));
1333
1334 u32Value |= AHCI_PORT_CMD_FR;
1335
1336 /* Send the first D2H FIS only if it wasn't already send. */
1337 if (!pAhciPort->fFirstD2HFisSend)
1338 {
1339#ifndef IN_RING3
1340 return VINF_IOM_HC_MMIO_WRITE;
1341#else
1342 ahciPostFirstD2HFisIntoMemory(pAhciPort);
1343 pAhciPort->fFirstD2HFisSend = true;
1344#endif
1345 }
1346 }
1347 else if (!(u32Value & AHCI_PORT_CMD_FRE))
1348 {
1349 ahciLog(("%s: FIS receive disabled\n", __FUNCTION__));
1350 u32Value &= ~AHCI_PORT_CMD_FR;
1351 }
1352
1353 pAhciPort->regCMD = u32Value;
1354
1355 return VINF_SUCCESS;
1356}
1357
1358/**
1359 * Read from the port interrupt enable register.
1360 */
1361static int PortIntrEnable_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1362{
1363 ahciLog(("%s: read regIE=%#010x\n", __FUNCTION__, pAhciPort->regIE));
1364 ahciLog(("%s: CPDE=%d TFEE=%d HBFE=%d HBDE=%d IFE=%d INFE=%d OFE=%d IPME=%d PRCE=%d DIE=%d PCE=%d DPE=%d UFE=%d SDBE=%d DSE=%d PSE=%d DHRE=%d\n",
1365 __FUNCTION__, (pAhciPort->regIE & AHCI_PORT_IE_CPDE) >> 31, (pAhciPort->regIE & AHCI_PORT_IE_TFEE) >> 30,
1366 (pAhciPort->regIE & AHCI_PORT_IE_HBFE) >> 29, (pAhciPort->regIE & AHCI_PORT_IE_HBDE) >> 28,
1367 (pAhciPort->regIE & AHCI_PORT_IE_IFE) >> 27, (pAhciPort->regIE & AHCI_PORT_IE_INFE) >> 26,
1368 (pAhciPort->regIE & AHCI_PORT_IE_OFE) >> 24, (pAhciPort->regIE & AHCI_PORT_IE_IPME) >> 23,
1369 (pAhciPort->regIE & AHCI_PORT_IE_PRCE) >> 22, (pAhciPort->regIE & AHCI_PORT_IE_DIE) >> 7,
1370 (pAhciPort->regIE & AHCI_PORT_IE_PCE) >> 6, (pAhciPort->regIE & AHCI_PORT_IE_DPE) >> 5,
1371 (pAhciPort->regIE & AHCI_PORT_IE_UFE) >> 4, (pAhciPort->regIE & AHCI_PORT_IE_SDBE) >> 3,
1372 (pAhciPort->regIE & AHCI_PORT_IE_DSE) >> 2, (pAhciPort->regIE & AHCI_PORT_IE_PSE) >> 1,
1373 (pAhciPort->regIE & AHCI_PORT_IE_DHRE)));
1374 *pu32Value = pAhciPort->regIE;
1375 return VINF_SUCCESS;
1376}
1377
1378/**
1379 * Write to the port interrupt enable register.
1380 */
1381static int PortIntrEnable_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1382{
1383 int rc = VINF_SUCCESS;
1384 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1385 ahciLog(("%s: CPDE=%d TFEE=%d HBFE=%d HBDE=%d IFE=%d INFE=%d OFE=%d IPME=%d PRCE=%d DIE=%d PCE=%d DPE=%d UFE=%d SDBE=%d DSE=%d PSE=%d DHRE=%d\n",
1386 __FUNCTION__, (u32Value & AHCI_PORT_IE_CPDE) >> 31, (u32Value & AHCI_PORT_IE_TFEE) >> 30,
1387 (u32Value & AHCI_PORT_IE_HBFE) >> 29, (u32Value & AHCI_PORT_IE_HBDE) >> 28,
1388 (u32Value & AHCI_PORT_IE_IFE) >> 27, (u32Value & AHCI_PORT_IE_INFE) >> 26,
1389 (u32Value & AHCI_PORT_IE_OFE) >> 24, (u32Value & AHCI_PORT_IE_IPME) >> 23,
1390 (u32Value & AHCI_PORT_IE_PRCE) >> 22, (u32Value & AHCI_PORT_IE_DIE) >> 7,
1391 (u32Value & AHCI_PORT_IE_PCE) >> 6, (u32Value & AHCI_PORT_IE_DPE) >> 5,
1392 (u32Value & AHCI_PORT_IE_UFE) >> 4, (u32Value & AHCI_PORT_IE_SDBE) >> 3,
1393 (u32Value & AHCI_PORT_IE_DSE) >> 2, (u32Value & AHCI_PORT_IE_PSE) >> 1,
1394 (u32Value & AHCI_PORT_IE_DHRE)));
1395
1396 u32Value &= AHCI_PORT_IE_READONLY;
1397
1398 /* Check if some a interrupt status bit changed*/
1399 uint32_t u32IntrStatus = ASMAtomicReadU32(&pAhciPort->regIS);
1400
1401 if (u32Value & u32IntrStatus)
1402 rc = ahciHbaSetInterrupt(ahci, pAhciPort->iLUN, VINF_IOM_HC_MMIO_WRITE);
1403
1404 if (rc == VINF_SUCCESS)
1405 pAhciPort->regIE = u32Value;
1406
1407 return rc;
1408}
1409
1410/**
1411 * Read from the port interrupt status register.
1412 */
1413static int PortIntrSts_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1414{
1415 ahciLog(("%s: read regIS=%#010x\n", __FUNCTION__, pAhciPort->regIS));
1416 ahciLog(("%s: CPDS=%d TFES=%d HBFS=%d HBDS=%d IFS=%d INFS=%d OFS=%d IPMS=%d PRCS=%d DIS=%d PCS=%d DPS=%d UFS=%d SDBS=%d DSS=%d PSS=%d DHRS=%d\n",
1417 __FUNCTION__, (pAhciPort->regIS & AHCI_PORT_IS_CPDS) >> 31, (pAhciPort->regIS & AHCI_PORT_IS_TFES) >> 30,
1418 (pAhciPort->regIS & AHCI_PORT_IS_HBFS) >> 29, (pAhciPort->regIS & AHCI_PORT_IS_HBDS) >> 28,
1419 (pAhciPort->regIS & AHCI_PORT_IS_IFS) >> 27, (pAhciPort->regIS & AHCI_PORT_IS_INFS) >> 26,
1420 (pAhciPort->regIS & AHCI_PORT_IS_OFS) >> 24, (pAhciPort->regIS & AHCI_PORT_IS_IPMS) >> 23,
1421 (pAhciPort->regIS & AHCI_PORT_IS_PRCS) >> 22, (pAhciPort->regIS & AHCI_PORT_IS_DIS) >> 7,
1422 (pAhciPort->regIS & AHCI_PORT_IS_PCS) >> 6, (pAhciPort->regIS & AHCI_PORT_IS_DPS) >> 5,
1423 (pAhciPort->regIS & AHCI_PORT_IS_UFS) >> 4, (pAhciPort->regIS & AHCI_PORT_IS_SDBS) >> 3,
1424 (pAhciPort->regIS & AHCI_PORT_IS_DSS) >> 2, (pAhciPort->regIS & AHCI_PORT_IS_PSS) >> 1,
1425 (pAhciPort->regIS & AHCI_PORT_IS_DHRS)));
1426 *pu32Value = pAhciPort->regIS;
1427 return VINF_SUCCESS;
1428}
1429
1430/**
1431 * Write to the port interrupt status register.
1432 */
1433static int PortIntrSts_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1434{
1435 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1436 ASMAtomicAndU32(&pAhciPort->regIS, ~(u32Value & AHCI_PORT_IS_READONLY));
1437
1438 return VINF_SUCCESS;
1439}
1440
1441/**
1442 * Read from the port FIS base address upper 32bit register.
1443 */
1444static int PortFisAddrUp_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1445{
1446 ahciLog(("%s: read regFBU=%#010x\n", __FUNCTION__, pAhciPort->regFBU));
1447 *pu32Value = pAhciPort->regFBU;
1448 return VINF_SUCCESS;
1449}
1450
1451/**
1452 * Write to the port FIS base address upper 32bit register.
1453 */
1454static int PortFisAddrUp_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1455{
1456 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1457
1458 pAhciPort->regFBU = u32Value;
1459 pAhciPort->GCPhysAddrFb = AHCI_RTGCPHYS_FROM_U32(pAhciPort->regFBU, pAhciPort->regFB);
1460
1461 return VINF_SUCCESS;
1462}
1463
1464/**
1465 * Read from the port FIS base address register.
1466 */
1467static int PortFisAddr_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1468{
1469 ahciLog(("%s: read regFB=%#010x\n", __FUNCTION__, pAhciPort->regFB));
1470 *pu32Value = pAhciPort->regFB;
1471 return VINF_SUCCESS;
1472}
1473
1474/**
1475 * Write to the port FIS base address register.
1476 */
1477static int PortFisAddr_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1478{
1479 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1480
1481 pAhciPort->regFB = (u32Value & AHCI_PORT_FB_RESERVED);
1482 pAhciPort->GCPhysAddrFb = AHCI_RTGCPHYS_FROM_U32(pAhciPort->regFBU, pAhciPort->regFB);
1483
1484 return VINF_SUCCESS;
1485}
1486
1487/**
1488 * Write to the port command list base address upper 32bit register.
1489 */
1490static int PortCmdLstAddrUp_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1491{
1492 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1493
1494 pAhciPort->regCLBU = u32Value;
1495 pAhciPort->GCPhysAddrClb = AHCI_RTGCPHYS_FROM_U32(pAhciPort->regCLBU, pAhciPort->regCLB);
1496
1497 return VINF_SUCCESS;
1498}
1499
1500/**
1501 * Read from the port command list base address upper 32bit register.
1502 */
1503static int PortCmdLstAddrUp_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1504{
1505 ahciLog(("%s: read regCLBU=%#010x\n", __FUNCTION__, pAhciPort->regCLBU));
1506 *pu32Value = pAhciPort->regCLBU;
1507 return VINF_SUCCESS;
1508}
1509
1510/**
1511 * Read from the port command list base address register.
1512 */
1513static int PortCmdLstAddr_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1514{
1515 ahciLog(("%s: read regCLB=%#010x\n", __FUNCTION__, pAhciPort->regCLB));
1516 *pu32Value = pAhciPort->regCLB;
1517 return VINF_SUCCESS;
1518}
1519
1520/**
1521 * Write to the port command list base address register.
1522 */
1523static int PortCmdLstAddr_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1524{
1525 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1526
1527 pAhciPort->regCLB = (u32Value & AHCI_PORT_CLB_RESERVED);
1528 pAhciPort->GCPhysAddrClb = AHCI_RTGCPHYS_FROM_U32(pAhciPort->regCLBU, pAhciPort->regCLB);
1529
1530 return VINF_SUCCESS;
1531}
1532
1533/**
1534 * Read from the global Version register.
1535 */
1536static int HbaVersion_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)
1537{
1538 Log(("%s: read regHbaVs=%#010x\n", __FUNCTION__, ahci->regHbaVs));
1539 *pu32Value = ahci->regHbaVs;
1540 return VINF_SUCCESS;
1541}
1542
1543/**
1544 * Read from the global Ports implemented register.
1545 */
1546static int HbaPortsImplemented_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)
1547{
1548 Log(("%s: read regHbaPi=%#010x\n", __FUNCTION__, ahci->regHbaPi));
1549 *pu32Value = ahci->regHbaPi;
1550 return VINF_SUCCESS;
1551}
1552
1553/**
1554 * Write to the global interrupt status register.
1555 */
1556static int HbaInterruptStatus_w(PAHCI ahci, uint32_t iReg, uint32_t u32Value)
1557{
1558 int rc;
1559 Log(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1560
1561 rc = PDMCritSectEnter(&ahci->lock, VINF_IOM_HC_MMIO_WRITE);
1562 if (rc != VINF_SUCCESS)
1563 return rc;
1564
1565 if (u32Value > 0)
1566 {
1567 /*
1568 * Clear the interrupt only if no port has signalled
1569 * an interrupt and the guest has cleared all set interrupt
1570 * notification bits.
1571 */
1572 bool fClear = true;
1573
1574 ahci->regHbaIs &= ~(u32Value);
1575
1576 fClear = !ahci->u32PortsInterrupted && !ahci->regHbaIs;
1577 if (fClear)
1578 {
1579 unsigned i = 0;
1580
1581 /* Check if the cleared ports have a interrupt status bit set. */
1582 while ((u32Value > 0) && (i < AHCI_MAX_NR_PORTS_IMPL))
1583 {
1584 if (u32Value & 0x01)
1585 {
1586 PAHCIPort pAhciPort = &ahci->ahciPort[i];
1587
1588 if (pAhciPort->regIE & pAhciPort->regIS)
1589 {
1590 Log(("%s: Interrupt status of port %u set -> Set interrupt again\n", __FUNCTION__, i));
1591 ASMAtomicOrU32(&ahci->u32PortsInterrupted, 1 << i);
1592 fClear = false;
1593 break;
1594 }
1595 }
1596 u32Value = u32Value >> 1;
1597 i++;
1598 }
1599 }
1600
1601 if (fClear)
1602 ahciHbaClearInterrupt(ahci);
1603 else
1604 {
1605 Log(("%s: Not clearing interrupt: u32PortsInterrupted=%#010x\n", __FUNCTION__, ahci->u32PortsInterrupted));
1606 /*
1607 * We need to set the interrupt again because the I/O APIC does not set it again even if the
1608 * line is still high.
1609 * We need to clear it first because the PCI bus only calls the interrupt controller if the state changes.
1610 */
1611 PDMDevHlpPCISetIrq(ahci->CTX_SUFF(pDevIns), 0, 0);
1612 PDMDevHlpPCISetIrq(ahci->CTX_SUFF(pDevIns), 0, 1);
1613 }
1614 }
1615
1616 PDMCritSectLeave(&ahci->lock);
1617 return VINF_SUCCESS;
1618}
1619
1620/**
1621 * Read from the global interrupt status register.
1622 */
1623static int HbaInterruptStatus_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)
1624{
1625 uint32_t u32PortsInterrupted;
1626 int rc;
1627
1628 rc = PDMCritSectEnter(&ahci->lock, VINF_IOM_HC_MMIO_READ);
1629 if (rc != VINF_SUCCESS)
1630 return rc;
1631
1632 u32PortsInterrupted = ASMAtomicXchgU32(&ahci->u32PortsInterrupted, 0);
1633
1634 PDMCritSectLeave(&ahci->lock);
1635 Log(("%s: read regHbaIs=%#010x u32PortsInterrupted=%#010x\n", __FUNCTION__, ahci->regHbaIs, u32PortsInterrupted));
1636
1637 ahci->regHbaIs |= u32PortsInterrupted;
1638
1639#ifdef LOG_ENABLED
1640 Log(("%s:", __FUNCTION__));
1641 unsigned i;
1642 for (i = 0; i < ahci->cPortsImpl; i++)
1643 {
1644 if ((ahci->regHbaIs >> i) & 0x01)
1645 Log((" P%d", i));
1646 }
1647 Log(("\n"));
1648#endif
1649
1650 *pu32Value = ahci->regHbaIs;
1651
1652 return VINF_SUCCESS;
1653}
1654
1655/**
1656 * Write to the global control register.
1657 */
1658static int HbaControl_w(PAHCI ahci, uint32_t iReg, uint32_t u32Value)
1659{
1660 Log(("%s: write u32Value=%#010x\n"
1661 "%s: AE=%d IE=%d HR=%d\n",
1662 __FUNCTION__, u32Value,
1663 __FUNCTION__, (u32Value & AHCI_HBA_CTRL_AE) >> 31, (u32Value & AHCI_HBA_CTRL_IE) >> 1,
1664 (u32Value & AHCI_HBA_CTRL_HR)));
1665
1666 ahci->regHbaCtrl = (u32Value & AHCI_HBA_CTRL_RW_MASK) | AHCI_HBA_CTRL_AE;
1667 if (ahci->regHbaCtrl & AHCI_HBA_CTRL_HR)
1668 ahciHBAReset(ahci);
1669 return VINF_SUCCESS;
1670}
1671
1672/**
1673 * Read the global control register.
1674 */
1675static int HbaControl_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)
1676{
1677 Log(("%s: read regHbaCtrl=%#010x\n"
1678 "%s: AE=%d IE=%d HR=%d\n",
1679 __FUNCTION__, ahci->regHbaCtrl,
1680 __FUNCTION__, (ahci->regHbaCtrl & AHCI_HBA_CTRL_AE) >> 31, (ahci->regHbaCtrl & AHCI_HBA_CTRL_IE) >> 1,
1681 (ahci->regHbaCtrl & AHCI_HBA_CTRL_HR)));
1682 *pu32Value = ahci->regHbaCtrl;
1683 return VINF_SUCCESS;
1684}
1685
1686/**
1687 * Read the global capabilities register.
1688 */
1689static int HbaCapabilities_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)
1690{
1691 Log(("%s: read regHbaCap=%#010x\n"
1692 "%s: S64A=%d SNCQ=%d SIS=%d SSS=%d SALP=%d SAL=%d SCLO=%d ISS=%d SNZO=%d SAM=%d SPM=%d PMD=%d SSC=%d PSC=%d NCS=%d NP=%d\n",
1693 __FUNCTION__, ahci->regHbaCap,
1694 __FUNCTION__, (ahci->regHbaCap & AHCI_HBA_CAP_S64A) >> 31, (ahci->regHbaCap & AHCI_HBA_CAP_SNCQ) >> 30,
1695 (ahci->regHbaCap & AHCI_HBA_CAP_SIS) >> 28, (ahci->regHbaCap & AHCI_HBA_CAP_SSS) >> 27,
1696 (ahci->regHbaCap & AHCI_HBA_CAP_SALP) >> 26, (ahci->regHbaCap & AHCI_HBA_CAP_SAL) >> 25,
1697 (ahci->regHbaCap & AHCI_HBA_CAP_SCLO) >> 24, (ahci->regHbaCap & AHCI_HBA_CAP_ISS) >> 20,
1698 (ahci->regHbaCap & AHCI_HBA_CAP_SNZO) >> 19, (ahci->regHbaCap & AHCI_HBA_CAP_SAM) >> 18,
1699 (ahci->regHbaCap & AHCI_HBA_CAP_SPM) >> 17, (ahci->regHbaCap & AHCI_HBA_CAP_PMD) >> 15,
1700 (ahci->regHbaCap & AHCI_HBA_CAP_SSC) >> 14, (ahci->regHbaCap & AHCI_HBA_CAP_PSC) >> 13,
1701 (ahci->regHbaCap & AHCI_HBA_CAP_NCS) >> 8, (ahci->regHbaCap & AHCI_HBA_CAP_NP)));
1702 *pu32Value = ahci->regHbaCap;
1703 return VINF_SUCCESS;
1704}
1705
1706/**
1707 * Write to the global command completion coalescing control register.
1708 */
1709static int HbaCccCtl_w(PAHCI ahci, uint32_t iReg, uint32_t u32Value)
1710{
1711 Log(("%s: write u32Value=%#010x\n"
1712 "%s: TV=%d CC=%d INT=%d EN=%d\n",
1713 __FUNCTION__, u32Value,
1714 __FUNCTION__, AHCI_HBA_CCC_CTL_TV_GET(u32Value), AHCI_HBA_CCC_CTL_CC_GET(u32Value),
1715 AHCI_HBA_CCC_CTL_INT_GET(u32Value), (u32Value & AHCI_HBA_CCC_CTL_EN)));
1716
1717 ahci->regHbaCccCtl = u32Value;
1718 ahci->uCccTimeout = AHCI_HBA_CCC_CTL_TV_GET(u32Value);
1719 ahci->uCccPortNr = AHCI_HBA_CCC_CTL_INT_GET(u32Value);
1720 ahci->uCccNr = AHCI_HBA_CCC_CTL_CC_GET(u32Value);
1721
1722 if (u32Value & AHCI_HBA_CCC_CTL_EN)
1723 {
1724 /* Arm the timer */
1725 TMTimerSetMillies(ahci->CTX_SUFF(pHbaCccTimer), ahci->uCccTimeout);
1726 }
1727 else
1728 {
1729 TMTimerStop(ahci->CTX_SUFF(pHbaCccTimer));
1730 }
1731
1732 return VINF_SUCCESS;
1733}
1734
1735/**
1736 * Read the global command completion coalescing control register.
1737 */
1738static int HbaCccCtl_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)
1739{
1740 Log(("%s: read regHbaCccCtl=%#010x\n"
1741 "%s: TV=%d CC=%d INT=%d EN=%d\n",
1742 __FUNCTION__, ahci->regHbaCccCtl,
1743 __FUNCTION__, AHCI_HBA_CCC_CTL_TV_GET(ahci->regHbaCccCtl), AHCI_HBA_CCC_CTL_CC_GET(ahci->regHbaCccCtl),
1744 AHCI_HBA_CCC_CTL_INT_GET(ahci->regHbaCccCtl), (ahci->regHbaCccCtl & AHCI_HBA_CCC_CTL_EN)));
1745 *pu32Value = ahci->regHbaCccCtl;
1746 return VINF_SUCCESS;
1747}
1748
1749/**
1750 * Write to the global command completion coalescing ports register.
1751 */
1752static int HbaCccPorts_w(PAHCI ahci, uint32_t iReg, uint32_t u32Value)
1753{
1754 Log(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1755
1756 ahci->regHbaCccPorts = u32Value;
1757
1758 return VINF_SUCCESS;
1759}
1760
1761/**
1762 * Read the global command completion coalescing ports register.
1763 */
1764static int HbaCccPorts_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)
1765{
1766 Log(("%s: read regHbaCccPorts=%#010x\n", __FUNCTION__, ahci->regHbaCccPorts));
1767
1768#ifdef LOG_ENABLED
1769 Log(("%s:", __FUNCTION__));
1770 unsigned i;
1771 for (i = 0; i < ahci->cPortsImpl; i++)
1772 {
1773 if ((ahci->regHbaCccPorts >> i) & 0x01)
1774 Log((" P%d", i));
1775 }
1776 Log(("\n"));
1777#endif
1778
1779 *pu32Value = ahci->regHbaCccPorts;
1780 return VINF_SUCCESS;
1781}
1782
1783/**
1784 * Invalid write to global register
1785 */
1786static int HbaInvalid_w(PAHCI ahci, uint32_t iReg, uint32_t u32Value)
1787{
1788 Log(("%s: Write denied!!! iReg=%u u32Value=%#010x\n", __FUNCTION__, iReg, u32Value));
1789 return VINF_SUCCESS;
1790}
1791
1792/**
1793 * Invalid Port write.
1794 */
1795static int PortInvalid_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1796{
1797 ahciLog(("%s: Write denied!!! iReg=%u u32Value=%#010x\n", __FUNCTION__, iReg, u32Value));
1798 return VINF_SUCCESS;
1799}
1800
1801/**
1802 * Invalid Port read.
1803 */
1804static int PortInvalid_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1805{
1806 ahciLog(("%s: Read denied!!! iReg=%u\n", __FUNCTION__, iReg));
1807 return VINF_SUCCESS;
1808}
1809
1810/**
1811 * Register descriptor table for global HBA registers
1812 */
1813static const AHCIOPREG g_aOpRegs[] =
1814{
1815 {"HbaCapabilites", HbaCapabilities_r, HbaInvalid_w}, /* Readonly */
1816 {"HbaControl" , HbaControl_r, HbaControl_w},
1817 {"HbaInterruptStatus", HbaInterruptStatus_r, HbaInterruptStatus_w},
1818 {"HbaPortsImplemented", HbaPortsImplemented_r, HbaInvalid_w}, /* Readonly */
1819 {"HbaVersion", HbaVersion_r, HbaInvalid_w}, /* ReadOnly */
1820 {"HbaCccCtl", HbaCccCtl_r, HbaCccCtl_w},
1821 {"HbaCccPorts", HbaCccPorts_r, HbaCccPorts_w},
1822};
1823
1824/**
1825 * Register descriptor table for port registers
1826 */
1827static const AHCIPORTOPREG g_aPortOpRegs[] =
1828{
1829 {"PortCmdLstAddr", PortCmdLstAddr_r, PortCmdLstAddr_w},
1830 {"PortCmdLstAddrUp", PortCmdLstAddrUp_r, PortCmdLstAddrUp_w},
1831 {"PortFisAddr", PortFisAddr_r, PortFisAddr_w},
1832 {"PortFisAddrUp", PortFisAddrUp_r, PortFisAddrUp_w},
1833 {"PortIntrSts", PortIntrSts_r, PortIntrSts_w},
1834 {"PortIntrEnable", PortIntrEnable_r, PortIntrEnable_w},
1835 {"PortCmd", PortCmd_r, PortCmd_w},
1836 {"PortReserved1", PortInvalid_r, PortInvalid_w}, /* Not used. */
1837 {"PortTaskFileData", PortTaskFileData_r, PortInvalid_w}, /* Readonly */
1838 {"PortSignature", PortSignature_r, PortInvalid_w}, /* Readonly */
1839 {"PortSStatus", PortSStatus_r, PortInvalid_w}, /* Readonly */
1840 {"PortSControl", PortSControl_r, PortSControl_w},
1841 {"PortSError", PortSError_r, PortSError_w},
1842 {"PortSActive", PortSActive_r, PortSActive_w},
1843 {"PortCmdIssue", PortCmdIssue_r, PortCmdIssue_w},
1844 {"PortReserved2", PortInvalid_r, PortInvalid_w}, /* Not used. */
1845};
1846
1847/**
1848 * Reset initiated by system software for one port.
1849 *
1850 * @param pAhciPort The port to reset.
1851 */
1852static void ahciPortSwReset(PAHCIPort pAhciPort)
1853{
1854 pAhciPort->regIS = 0;
1855 pAhciPort->regIE = 0;
1856 pAhciPort->regCMD = AHCI_PORT_CMD_CPD | /* Cold presence detection */
1857 AHCI_PORT_CMD_SUD | /* Device has spun up. */
1858 AHCI_PORT_CMD_POD; /* Port is powered on. */
1859 pAhciPort->regTFD = (1 << 8) | ATA_STAT_SEEK | ATA_STAT_WRERR;
1860 pAhciPort->regSIG = ~0;
1861 pAhciPort->regSSTS = 0;
1862 pAhciPort->regSCTL = 0;
1863 pAhciPort->regSERR = 0;
1864 pAhciPort->regSACT = 0;
1865 pAhciPort->regCI = 0;
1866
1867 pAhciPort->fResetDevice = false;
1868 pAhciPort->fPoweredOn = true;
1869 pAhciPort->fSpunUp = true;
1870 pAhciPort->cMultSectors = ATA_MAX_MULT_SECTORS;
1871 pAhciPort->uATATransferMode = ATA_MODE_UDMA | 6;
1872
1873 pAhciPort->u32TasksNew = 0;
1874 pAhciPort->u32TasksFinished = 0;
1875 pAhciPort->u32QueuedTasksFinished = 0;
1876
1877 pAhciPort->cTasksActive = 0;
1878
1879 ASMAtomicWriteU32(&pAhciPort->MediaEventStatus, ATA_EVENT_STATUS_UNCHANGED);
1880 ASMAtomicWriteU32(&pAhciPort->MediaTrackType, ATA_MEDIA_TYPE_UNKNOWN);
1881
1882 if (pAhciPort->pDrvBase)
1883 {
1884 pAhciPort->regCMD |= AHCI_PORT_CMD_CPS; /* Indicate that there is a device on that port */
1885
1886 if (pAhciPort->fPoweredOn)
1887 {
1888 /*
1889 * Set states in the Port Signature and SStatus registers.
1890 */
1891 if (pAhciPort->fATAPI)
1892 pAhciPort->regSIG = AHCI_PORT_SIG_ATAPI;
1893 else
1894 pAhciPort->regSIG = AHCI_PORT_SIG_DISK;
1895 pAhciPort->regSSTS = (0x01 << 8) | /* Interface is active. */
1896 (0x02 << 4) | /* Generation 2 (3.0GBps) speed. */
1897 (0x03 << 0); /* Device detected and communication established. */
1898 }
1899 }
1900}
1901
1902#ifdef IN_RING3
1903/**
1904 * Hardware reset used for machine power on and reset.
1905 *
1906 * @param pAhciport The port to reset.
1907 */
1908static void ahciPortHwReset(PAHCIPort pAhciPort)
1909{
1910 /* Reset the address registers. */
1911 pAhciPort->regCLB = 0;
1912 pAhciPort->regCLBU = 0;
1913 pAhciPort->regFB = 0;
1914 pAhciPort->regFBU = 0;
1915
1916 /* Reset calculated addresses. */
1917 pAhciPort->GCPhysAddrClb = 0;
1918 pAhciPort->GCPhysAddrFb = 0;
1919}
1920#endif
1921
1922/**
1923 * Create implemented ports bitmap.
1924 *
1925 * @returns 32bit bitmask with a bit set for every implemented port.
1926 * @param cPorts Number of ports.
1927 */
1928static uint32_t ahciGetPortsImplemented(unsigned cPorts)
1929{
1930 uint32_t uPortsImplemented = 0;
1931
1932 for (unsigned i = 0; i < cPorts; i++)
1933 uPortsImplemented |= (1 << i);
1934
1935 return uPortsImplemented;
1936}
1937
1938/**
1939 * Reset the entire HBA.
1940 *
1941 * @param pThis The HBA state.
1942 */
1943static void ahciHBAReset(PAHCI pThis)
1944{
1945 unsigned i;
1946 int rc = VINF_SUCCESS;
1947
1948 LogFlow(("Reset the HBA controller\n"));
1949
1950 /* Stop the CCC timer. */
1951 if (pThis->regHbaCccCtl & AHCI_HBA_CCC_CTL_EN)
1952 {
1953 rc = TMTimerStop(pThis->CTX_SUFF(pHbaCccTimer));
1954 if (RT_FAILURE(rc))
1955 AssertMsgFailed(("%s: Failed to stop timer!\n", __FUNCTION__));
1956 }
1957
1958 /* Reset every port */
1959 for (i = 0; i < pThis->cPortsImpl; i++)
1960 {
1961 PAHCIPort pAhciPort = &pThis->ahciPort[i];
1962
1963 pAhciPort->iLUN = i;
1964 ahciPortSwReset(pAhciPort);
1965 }
1966
1967 /* Init Global registers */
1968 pThis->regHbaCap = AHCI_HBA_CAP_ISS_SHIFT(AHCI_HBA_CAP_ISS_GEN2) |
1969 AHCI_HBA_CAP_S64A | /* 64bit addressing supported */
1970 AHCI_HBA_CAP_SAM | /* AHCI mode only */
1971 AHCI_HBA_CAP_SNCQ | /* Support native command queuing */
1972 AHCI_HBA_CAP_SSS | /* Staggered spin up */
1973 AHCI_HBA_CAP_CCCS | /* Support command completion coalescing */
1974 AHCI_HBA_CAP_NCS_SET(AHCI_NR_COMMAND_SLOTS) | /* Number of command slots we support */
1975 AHCI_HBA_CAP_NP_SET(pThis->cPortsImpl); /* Number of supported ports */
1976 pThis->regHbaCtrl = AHCI_HBA_CTRL_AE;
1977 pThis->regHbaIs = 0;
1978 pThis->regHbaPi = ahciGetPortsImplemented(pThis->cPortsImpl);
1979 pThis->regHbaVs = AHCI_HBA_VS_MJR | AHCI_HBA_VS_MNR;
1980 pThis->regHbaCccCtl = 0;
1981 pThis->regHbaCccPorts = 0;
1982 pThis->uCccTimeout = 0;
1983 pThis->uCccPortNr = 0;
1984 pThis->uCccNr = 0;
1985
1986 pThis->f64BitAddr = false;
1987 pThis->u32PortsInterrupted = 0;
1988 pThis->f8ByteMMIO4BytesWrittenSuccessfully = false;
1989 /* Clear the HBA Reset bit */
1990 pThis->regHbaCtrl &= ~AHCI_HBA_CTRL_HR;
1991}
1992
1993/**
1994 * Memory mapped I/O Handler for read operations.
1995 *
1996 * @returns VBox status code.
1997 *
1998 * @param pDevIns The device instance.
1999 * @param pvUser User argument.
2000 * @param GCPhysAddr Physical address (in GC) where the read starts.
2001 * @param pv Where to store the result.
2002 * @param cb Number of bytes read.
2003 */
2004PDMBOTHCBDECL(int) ahciMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2005{
2006 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
2007 int rc = VINF_SUCCESS;
2008
2009 /* Break up 64 bits reads into two dword reads. */
2010 if (cb == 8)
2011 {
2012 rc = ahciMMIORead(pDevIns, pvUser, GCPhysAddr, pv, 4);
2013 if (RT_FAILURE(rc))
2014 return rc;
2015
2016 return ahciMMIORead(pDevIns, pvUser, GCPhysAddr + 4, (uint8_t *)pv + 4, 4);
2017 }
2018
2019 Log2(("#%d ahciMMIORead: pvUser=%p:{%.*Rhxs} cb=%d GCPhysAddr=%RGp rc=%Rrc\n",
2020 pDevIns->iInstance, pv, cb, pv, cb, GCPhysAddr, rc));
2021
2022 /*
2023 * If the access offset is smaller than AHCI_HBA_GLOBAL_SIZE the guest accesses the global registers.
2024 * Otherwise it accesses the registers of a port.
2025 */
2026 uint32_t uOffset = (GCPhysAddr - pAhci->MMIOBase);
2027 uint32_t iReg;
2028
2029 if (uOffset < AHCI_HBA_GLOBAL_SIZE)
2030 {
2031 iReg = uOffset >> 2;
2032 Log3(("%s: Trying to read from global register %u\n", __FUNCTION__, iReg));
2033 if (iReg < RT_ELEMENTS(g_aOpRegs))
2034 {
2035 const AHCIOPREG *pReg = &g_aOpRegs[iReg];
2036 rc = pReg->pfnRead(pAhci, iReg, (uint32_t *)pv);
2037 }
2038 else
2039 {
2040 Log3(("%s: Trying to read global register %u/%u!!!\n", __FUNCTION__, iReg, RT_ELEMENTS(g_aOpRegs)));
2041 *(uint32_t *)pv = 0;
2042 }
2043 }
2044 else
2045 {
2046 uint32_t iRegOffset;
2047 uint32_t iPort;
2048
2049 /* Calculate accessed port. */
2050 uOffset -= AHCI_HBA_GLOBAL_SIZE;
2051 iPort = uOffset / AHCI_PORT_REGISTER_SIZE;
2052 iRegOffset = (uOffset % AHCI_PORT_REGISTER_SIZE);
2053 iReg = iRegOffset >> 2;
2054
2055 Log3(("%s: Trying to read from port %u and register %u\n", __FUNCTION__, iPort, iReg));
2056
2057 if (RT_LIKELY( iPort < pAhci->cPortsImpl
2058 && iReg < RT_ELEMENTS(g_aPortOpRegs)))
2059 {
2060 const AHCIPORTOPREG *pPortReg = &g_aPortOpRegs[iReg];
2061 rc = pPortReg->pfnRead(pAhci, &pAhci->ahciPort[iPort], iReg, (uint32_t *)pv);
2062 }
2063 else
2064 {
2065 Log3(("%s: Trying to read port %u register %u/%u!!!\n", __FUNCTION__, iPort, iReg, RT_ELEMENTS(g_aPortOpRegs)));
2066 rc = VINF_IOM_MMIO_UNUSED_00;
2067 }
2068
2069 /*
2070 * Windows Vista tries to read one byte from some registers instead of four.
2071 * Correct the value according to the read size.
2072 */
2073 if (RT_SUCCESS(rc) && cb != sizeof(uint32_t))
2074 {
2075 switch (cb)
2076 {
2077 case 1:
2078 {
2079 uint8_t uNewValue;
2080 uint8_t *p = (uint8_t *)pv;
2081
2082 iRegOffset &= 3;
2083 Log3(("%s: iRegOffset=%u\n", __FUNCTION__, iRegOffset));
2084 uNewValue = p[iRegOffset];
2085 /* Clear old value */
2086 *(uint32_t *)pv = 0;
2087 *(uint8_t *)pv = uNewValue;
2088 break;
2089 }
2090 default:
2091 AssertMsgFailed(("%s: unsupported access width cb=%d uOffset=%x iPort=%x iRegOffset=%x iReg=%x!!!\n", __FUNCTION__, cb, uOffset, iPort, iRegOffset, iReg));
2092 }
2093 }
2094 }
2095
2096 Log2(("#%d ahciMMIORead: return pvUser=%p:{%.*Rhxs} cb=%d GCPhysAddr=%RGp rc=%Rrc\n",
2097 pDevIns->iInstance, pv, cb, pv, cb, GCPhysAddr, rc));
2098 return rc;
2099}
2100
2101
2102/**
2103 * Memory mapped I/O Handler for write operations.
2104 *
2105 * @returns VBox status code.
2106 *
2107 * @param pDevIns The device instance.
2108 * @param pvUser User argument.
2109 * @param GCPhysAddr Physical address (in GC) where the read starts.
2110 * @param pv Where to fetch the result.
2111 * @param cb Number of bytes to write.
2112 */
2113PDMBOTHCBDECL(int) ahciMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2114{
2115 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
2116 int rc = VINF_SUCCESS;
2117
2118 /* Break up 64 bits writes into two dword writes. */
2119 if (cb == 8)
2120 {
2121 /*
2122 * Only write the first 4 bytes if they weren't already.
2123 * It is possible that the last write to the register caused a world
2124 * switch and we entered this function again.
2125 * Writing the first 4 bytes again could cause indeterminate behavior
2126 * which can cause errors in the guest.
2127 */
2128 if (!pAhci->f8ByteMMIO4BytesWrittenSuccessfully)
2129 {
2130 rc = ahciMMIOWrite(pDevIns, pvUser, GCPhysAddr, pv, 4);
2131 if (rc != VINF_SUCCESS)
2132 return rc;
2133
2134 pAhci->f8ByteMMIO4BytesWrittenSuccessfully = true;
2135 }
2136
2137 rc = ahciMMIOWrite(pDevIns, pvUser, GCPhysAddr + 4, (uint8_t *)pv + 4, 4);
2138 /*
2139 * Reset flag again so that the first 4 bytes are written again on the next
2140 * 8byte MMIO access.
2141 */
2142 if (rc == VINF_SUCCESS)
2143 pAhci->f8ByteMMIO4BytesWrittenSuccessfully = false;
2144
2145 return rc;
2146 }
2147
2148 Log2(("#%d ahciMMIOWrite: pvUser=%p:{%.*Rhxs} cb=%d GCPhysAddr=%RGp\n",
2149 pDevIns->iInstance, pv, cb, pv, cb, GCPhysAddr));
2150
2151 /* Validate access. */
2152 if (cb != sizeof(uint32_t))
2153 {
2154 Log2(("%s: Bad write size!!! GCPhysAddr=%RGp cb=%d\n", __FUNCTION__, GCPhysAddr, cb));
2155 return VINF_SUCCESS;
2156 }
2157 if (GCPhysAddr & 0x3)
2158 {
2159 Log2(("%s: Unaligned write!!! GCPhysAddr=%RGp cb=%d\n", __FUNCTION__, GCPhysAddr, cb));
2160 return VINF_SUCCESS;
2161 }
2162
2163 /*
2164 * If the access offset is smaller than 100h the guest accesses the global registers.
2165 * Otherwise it accesses the registers of a port.
2166 */
2167 uint32_t uOffset = (GCPhysAddr - pAhci->MMIOBase);
2168 uint32_t iReg;
2169 if (uOffset < AHCI_HBA_GLOBAL_SIZE)
2170 {
2171 Log3(("Write global HBA register\n"));
2172 iReg = uOffset >> 2;
2173 if (iReg < RT_ELEMENTS(g_aOpRegs))
2174 {
2175 const AHCIOPREG *pReg = &g_aOpRegs[iReg];
2176 rc = pReg->pfnWrite(pAhci, iReg, *(uint32_t *)pv);
2177 }
2178 else
2179 {
2180 Log3(("%s: Trying to write global register %u/%u!!!\n", __FUNCTION__, iReg, RT_ELEMENTS(g_aOpRegs)));
2181 rc = VINF_SUCCESS;
2182 }
2183 }
2184 else
2185 {
2186 uint32_t iPort;
2187 Log3(("Write Port register\n"));
2188 /* Calculate accessed port. */
2189 uOffset -= AHCI_HBA_GLOBAL_SIZE;
2190 iPort = uOffset / AHCI_PORT_REGISTER_SIZE;
2191 iReg = (uOffset % AHCI_PORT_REGISTER_SIZE) >> 2;
2192 Log3(("%s: Trying to write to port %u and register %u\n", __FUNCTION__, iPort, iReg));
2193 if (RT_LIKELY( iPort < pAhci->cPortsImpl
2194 && iReg < RT_ELEMENTS(g_aPortOpRegs)))
2195 {
2196 const AHCIPORTOPREG *pPortReg = &g_aPortOpRegs[iReg];
2197 rc = pPortReg->pfnWrite(pAhci, &pAhci->ahciPort[iPort], iReg, *(uint32_t *)pv);
2198 }
2199 else
2200 {
2201 Log3(("%s: Trying to write port %u register %u/%u!!!\n", __FUNCTION__, iPort, iReg, RT_ELEMENTS(g_aPortOpRegs)));
2202 rc = VINF_SUCCESS;
2203 }
2204 }
2205
2206 return rc;
2207}
2208
2209PDMBOTHCBDECL(int) ahciIOPortWrite1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2210{
2211 uint32_t iChannel = (uint32_t)(uintptr_t)pvUser;
2212 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
2213 PAHCIATACONTROLLER pCtl = &pAhci->aCts[iChannel];
2214
2215 Assert(iChannel < 2);
2216
2217 return ataControllerIOPortWrite1(pCtl, Port, u32, cb);
2218}
2219
2220PDMBOTHCBDECL(int) ahciIOPortRead1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
2221{
2222 uint32_t iChannel = (uint32_t)(uintptr_t)pvUser;
2223 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
2224 PAHCIATACONTROLLER pCtl = &pAhci->aCts[iChannel];
2225
2226 Assert(iChannel < 2);
2227
2228 return ataControllerIOPortRead1(pCtl, Port, pu32, cb);
2229}
2230
2231PDMBOTHCBDECL(int) ahciIOPortWrite2(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2232{
2233 uint32_t iChannel = (uint32_t)(uintptr_t)pvUser;
2234 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
2235 PAHCIATACONTROLLER pCtl = &pAhci->aCts[iChannel];
2236
2237 Assert(iChannel < 2);
2238
2239 return ataControllerIOPortWrite2(pCtl, Port, u32, cb);
2240}
2241
2242PDMBOTHCBDECL(int) ahciIOPortRead2(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
2243{
2244 uint32_t iChannel = (uint32_t)(uintptr_t)pvUser;
2245 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
2246 PAHCIATACONTROLLER pCtl = &pAhci->aCts[iChannel];
2247
2248 Assert(iChannel < 2);
2249
2250 return ataControllerIOPortRead2(pCtl, Port, pu32, cb);
2251}
2252
2253PDMBOTHCBDECL(int) ahciLegacyFakeWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2254{
2255 AssertMsgFailed(("Should not happen\n"));
2256 return VINF_SUCCESS;
2257}
2258
2259PDMBOTHCBDECL(int) ahciLegacyFakeRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
2260{
2261 AssertMsgFailed(("Should not happen\n"));
2262 return VINF_SUCCESS;
2263}
2264
2265#ifndef IN_RING0
2266/**
2267 * Port I/O Handler for primary port range IN string operations.
2268 * @see FNIOMIOPORTINSTRING for details.
2269 */
2270PDMBOTHCBDECL(int) ahciIOPortReadStr1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrDst, PRTGCUINTREG pcTransfer, unsigned cb)
2271{
2272 uint32_t iChannel = (uint32_t)(uintptr_t)pvUser;
2273 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
2274 PAHCIATACONTROLLER pCtl = &pAhci->aCts[iChannel];
2275
2276 Assert(iChannel < 2);
2277
2278 return ataControllerIOPortReadStr1(pCtl, Port, pGCPtrDst, pcTransfer, cb);
2279}
2280
2281
2282/**
2283 * Port I/O Handler for primary port range OUT string operations.
2284 * @see FNIOMIOPORTOUTSTRING for details.
2285 */
2286PDMBOTHCBDECL(int) ahciIOPortWriteStr1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrSrc, PRTGCUINTREG pcTransfer, unsigned cb)
2287{
2288 uint32_t iChannel = (uint32_t)(uintptr_t)pvUser;
2289 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
2290 PAHCIATACONTROLLER pCtl = &pAhci->aCts[iChannel];
2291
2292 Assert(iChannel < 2);
2293
2294 return ataControllerIOPortReadStr1(pCtl, Port, pGCPtrSrc, pcTransfer, cb);
2295}
2296#endif /* !IN_RING0 */
2297
2298#ifdef IN_RING3
2299
2300static DECLCALLBACK(int) ahciR3MMIOMap(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
2301{
2302 PAHCI pThis = PCIDEV_2_PAHCI(pPciDev);
2303 PPDMDEVINS pDevIns = pPciDev->pDevIns;
2304 int rc = VINF_SUCCESS;
2305
2306 Log2(("%s: registering MMIO area at GCPhysAddr=%RGp cb=%u\n", __FUNCTION__, GCPhysAddress, cb));
2307
2308 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
2309 Assert(cb >= 4352);
2310
2311 /* We use the assigned size here, because we currently only support page aligned MMIO ranges. */
2312 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL,
2313 ahciMMIOWrite, ahciMMIORead, NULL, "AHCI");
2314 if (RT_FAILURE(rc))
2315 return rc;
2316
2317 if (pThis->fR0Enabled)
2318 {
2319 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, 0,
2320 "ahciMMIOWrite", "ahciMMIORead", NULL);
2321 if (RT_FAILURE(rc))
2322 return rc;
2323 }
2324
2325 if (pThis->fGCEnabled)
2326 {
2327 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, 0,
2328 "ahciMMIOWrite", "ahciMMIORead", NULL);
2329 if (RT_FAILURE(rc))
2330 return rc;
2331 }
2332
2333 pThis->MMIOBase = GCPhysAddress;
2334 return rc;
2335}
2336
2337/**
2338 * Map the legacy I/O port ranges to make Solaris work with the controller.
2339 */
2340static DECLCALLBACK(int) ahciR3LegacyFakeIORangeMap(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
2341{
2342 PAHCI pThis = PCIDEV_2_PAHCI(pPciDev);
2343 PPDMDEVINS pDevIns = pPciDev->pDevIns;
2344 int rc = VINF_SUCCESS;
2345
2346 Log2(("%s: registering fake I/O area at GCPhysAddr=%RGp cb=%u\n", __FUNCTION__, GCPhysAddress, cb));
2347
2348 Assert(enmType == PCI_ADDRESS_SPACE_IO);
2349
2350 /* We use the assigned size here, because we currently only support page aligned MMIO ranges. */
2351 rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, NULL,
2352 ahciLegacyFakeWrite, ahciLegacyFakeRead, NULL, NULL, "AHCI Fake");
2353 if (RT_FAILURE(rc))
2354 return rc;
2355
2356 if (pThis->fR0Enabled)
2357 {
2358 rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
2359 "ahciLegacyFakeWrite", "ahciLegacyFakeRead", NULL, NULL, "AHCI Fake");
2360 if (RT_FAILURE(rc))
2361 return rc;
2362 }
2363
2364 if (pThis->fGCEnabled)
2365 {
2366 rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
2367 "ahciLegacyFakeWrite", "ahciLegacyFakeRead", NULL, NULL, "AHCI Fake");
2368 if (RT_FAILURE(rc))
2369 return rc;
2370 }
2371
2372 return rc;
2373}
2374
2375/* -=-=-=-=-=- PAHCI::ILeds -=-=-=-=-=- */
2376
2377/**
2378 * Gets the pointer to the status LED of a unit.
2379 *
2380 * @returns VBox status code.
2381 * @param pInterface Pointer to the interface structure containing the called function pointer.
2382 * @param iLUN The unit which status LED we desire.
2383 * @param ppLed Where to store the LED pointer.
2384 */
2385static DECLCALLBACK(int) ahciR3Status_QueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
2386{
2387 PAHCI pAhci = PDMILEDPORTS_2_PAHCI(pInterface);
2388 if (iLUN < AHCI_MAX_NR_PORTS_IMPL)
2389 {
2390 *ppLed = &pAhci->ahciPort[iLUN].Led;
2391 Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
2392 return VINF_SUCCESS;
2393 }
2394 return VERR_PDM_LUN_NOT_FOUND;
2395}
2396
2397/**
2398 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2399 */
2400static DECLCALLBACK(void *) ahciR3Status_QueryInterface(PPDMIBASE pInterface, const char *pszIID)
2401{
2402 PAHCI pThis = PDMIBASE_2_PAHCI(pInterface);
2403 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
2404 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
2405 return NULL;
2406}
2407
2408/**
2409 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2410 */
2411static DECLCALLBACK(void *) ahciR3PortQueryInterface(PPDMIBASE pInterface, const char *pszIID)
2412{
2413 PAHCIPort pAhciPort = PDMIBASE_2_PAHCIPORT(pInterface);
2414 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pAhciPort->IBase);
2415 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBLOCKPORT, &pAhciPort->IPort);
2416 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBLOCKASYNCPORT, &pAhciPort->IPortAsync);
2417 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIMOUNTNOTIFY, &pAhciPort->IMountNotify);
2418 return NULL;
2419}
2420
2421static DECLCALLBACK(int) ahciR3PortQueryDeviceLocation(PPDMIBLOCKPORT pInterface, const char **ppcszController,
2422 uint32_t *piInstance, uint32_t *piLUN)
2423{
2424 PAHCIPort pAhciPort = PDMIBLOCKPORT_2_PAHCIPORT(pInterface);
2425 PPDMDEVINS pDevIns = pAhciPort->CTX_SUFF(pDevIns);
2426
2427 AssertPtrReturn(ppcszController, VERR_INVALID_POINTER);
2428 AssertPtrReturn(piInstance, VERR_INVALID_POINTER);
2429 AssertPtrReturn(piLUN, VERR_INVALID_POINTER);
2430
2431 *ppcszController = pDevIns->pReg->szName;
2432 *piInstance = pDevIns->iInstance;
2433 *piLUN = pAhciPort->iLUN;
2434
2435 return VINF_SUCCESS;
2436}
2437
2438#ifdef DEBUG
2439
2440/**
2441 * Dump info about the FIS
2442 *
2443 * @returns nothing
2444 * @param pAhciPort The port the command FIS was read from.
2445 * @param cmdFis The FIS to print info from.
2446 */
2447static void ahciDumpFisInfo(PAHCIPort pAhciPort, uint8_t *cmdFis)
2448{
2449 ahciLog(("%s: *** Begin FIS info dump. ***\n", __FUNCTION__));
2450 /* Print FIS type. */
2451 switch (cmdFis[AHCI_CMDFIS_TYPE])
2452 {
2453 case AHCI_CMDFIS_TYPE_H2D:
2454 {
2455 ahciLog(("%s: Command Fis type: H2D\n", __FUNCTION__));
2456 ahciLog(("%s: Command Fis size: %d bytes\n", __FUNCTION__, AHCI_CMDFIS_TYPE_H2D_SIZE));
2457 if (cmdFis[AHCI_CMDFIS_BITS] & AHCI_CMDFIS_C)
2458 {
2459 ahciLog(("%s: Command register update\n", __FUNCTION__));
2460 }
2461 else
2462 {
2463 ahciLog(("%s: Control register update\n", __FUNCTION__));
2464 }
2465 ahciLog(("%s: CMD=%#04x \"%s\"\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CMD], ATACmdText(cmdFis[AHCI_CMDFIS_CMD])));
2466 ahciLog(("%s: FEAT=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_FET]));
2467 ahciLog(("%s: SECTN=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_SECTN]));
2468 ahciLog(("%s: CYLL=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CYLL]));
2469 ahciLog(("%s: CYLH=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CYLH]));
2470 ahciLog(("%s: HEAD=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_HEAD]));
2471
2472 ahciLog(("%s: SECTNEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_SECTNEXP]));
2473 ahciLog(("%s: CYLLEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CYLLEXP]));
2474 ahciLog(("%s: CYLHEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CYLHEXP]));
2475 ahciLog(("%s: FETEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_FETEXP]));
2476
2477 ahciLog(("%s: SECTC=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_SECTC]));
2478 ahciLog(("%s: SECTCEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_SECTCEXP]));
2479 ahciLog(("%s: CTL=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CTL]));
2480 if (cmdFis[AHCI_CMDFIS_CTL] & AHCI_CMDFIS_CTL_SRST)
2481 {
2482 ahciLog(("%s: Reset bit is set\n", __FUNCTION__));
2483 }
2484 }
2485 break;
2486 case AHCI_CMDFIS_TYPE_D2H:
2487 {
2488 ahciLog(("%s: Command Fis type D2H\n", __FUNCTION__));
2489 ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_D2H_SIZE));
2490 }
2491 break;
2492 case AHCI_CMDFIS_TYPE_SETDEVBITS:
2493 {
2494 ahciLog(("%s: Command Fis type Set Device Bits\n", __FUNCTION__));
2495 ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_SETDEVBITS_SIZE));
2496 }
2497 break;
2498 case AHCI_CMDFIS_TYPE_DMAACTD2H:
2499 {
2500 ahciLog(("%s: Command Fis type DMA Activate H2D\n", __FUNCTION__));
2501 ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_DMAACTD2H_SIZE));
2502 }
2503 break;
2504 case AHCI_CMDFIS_TYPE_DMASETUP:
2505 {
2506 ahciLog(("%s: Command Fis type DMA Setup\n", __FUNCTION__));
2507 ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_DMASETUP_SIZE));
2508 }
2509 break;
2510 case AHCI_CMDFIS_TYPE_PIOSETUP:
2511 {
2512 ahciLog(("%s: Command Fis type PIO Setup\n", __FUNCTION__));
2513 ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_PIOSETUP_SIZE));
2514 }
2515 break;
2516 case AHCI_CMDFIS_TYPE_DATA:
2517 {
2518 ahciLog(("%s: Command Fis type Data\n", __FUNCTION__));
2519 }
2520 break;
2521 default:
2522 ahciLog(("%s: ERROR Unknown command FIS type\n", __FUNCTION__));
2523 break;
2524 }
2525 ahciLog(("%s: *** End FIS info dump. ***\n", __FUNCTION__));
2526}
2527
2528/**
2529 * Dump info about the command header
2530 *
2531 * @returns nothing
2532 * @param pAhciPort Pointer to the port the command header was read from.
2533 * @param pCmdHdr The command header to print info from.
2534 */
2535static void ahciDumpCmdHdrInfo(PAHCIPort pAhciPort, CmdHdr *pCmdHdr)
2536{
2537 ahciLog(("%s: *** Begin command header info dump. ***\n", __FUNCTION__));
2538 ahciLog(("%s: Number of Scatter/Gatther List entries: %u\n", __FUNCTION__, AHCI_CMDHDR_PRDTL_ENTRIES(pCmdHdr->u32DescInf)));
2539 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_C)
2540 ahciLog(("%s: Clear busy upon R_OK\n", __FUNCTION__));
2541 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_B)
2542 ahciLog(("%s: BIST Fis\n", __FUNCTION__));
2543 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_R)
2544 ahciLog(("%s: Device Reset Fis\n", __FUNCTION__));
2545 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_P)
2546 ahciLog(("%s: Command prefetchable\n", __FUNCTION__));
2547 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_W)
2548 ahciLog(("%s: Device write\n", __FUNCTION__));
2549 else
2550 ahciLog(("%s: Device read\n", __FUNCTION__));
2551 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_A)
2552 ahciLog(("%s: ATAPI command\n", __FUNCTION__));
2553 else
2554 ahciLog(("%s: ATA command\n", __FUNCTION__));
2555
2556 ahciLog(("%s: Command FIS length %u DW\n", __FUNCTION__, (pCmdHdr->u32DescInf & AHCI_CMDHDR_CFL_MASK)));
2557 ahciLog(("%s: *** End command header info dump. ***\n", __FUNCTION__));
2558}
2559#endif /* DEBUG */
2560
2561/**
2562 * Post the first D2H FIS from the device into guest memory.
2563 *
2564 * @returns nothing
2565 * @param pAhciPort Pointer to the port which "receives" the FIS.
2566 */
2567static void ahciPostFirstD2HFisIntoMemory(PAHCIPort pAhciPort)
2568{
2569 uint8_t d2hFis[AHCI_CMDFIS_TYPE_D2H_SIZE];
2570
2571 pAhciPort->fFirstD2HFisSend = true;
2572
2573 ahciLog(("%s: Sending First D2H FIS from FIFO\n", __FUNCTION__));
2574 memset(&d2hFis[0], 0, sizeof(d2hFis));
2575 d2hFis[AHCI_CMDFIS_TYPE] = AHCI_CMDFIS_TYPE_D2H;
2576 d2hFis[AHCI_CMDFIS_ERR] = 0x01;
2577
2578 d2hFis[AHCI_CMDFIS_STS] = 0x00;
2579
2580 /* Set the signature based on the device type. */
2581 if (pAhciPort->fATAPI)
2582 {
2583 d2hFis[AHCI_CMDFIS_CYLL] = 0x14;
2584 d2hFis[AHCI_CMDFIS_CYLH] = 0xeb;
2585 }
2586 else
2587 {
2588 d2hFis[AHCI_CMDFIS_CYLL] = 0x00;
2589 d2hFis[AHCI_CMDFIS_CYLH] = 0x00;
2590 }
2591
2592 d2hFis[AHCI_CMDFIS_HEAD] = 0x00;
2593 d2hFis[AHCI_CMDFIS_SECTN] = 0x01;
2594 d2hFis[AHCI_CMDFIS_SECTC] = 0x01;
2595
2596 pAhciPort->regTFD = (1 << 8) | ATA_STAT_SEEK | ATA_STAT_WRERR;
2597 if (!pAhciPort->fATAPI)
2598 pAhciPort->regTFD |= ATA_STAT_READY;
2599
2600 ahciPostFisIntoMemory(pAhciPort, AHCI_CMDFIS_TYPE_D2H, d2hFis);
2601}
2602
2603/**
2604 * Post the FIS in the memory area allocated by the guest and set interrupt if necessary.
2605 *
2606 * @returns VBox status code
2607 * @param pAhciPort The port which "receives" the FIS.
2608 * @param uFisType The type of the FIS.
2609 * @param pCmdFis Pointer to the FIS which is to be posted into memory.
2610 */
2611static int ahciPostFisIntoMemory(PAHCIPort pAhciPort, unsigned uFisType, uint8_t *pCmdFis)
2612{
2613 int rc = VINF_SUCCESS;
2614 RTGCPHYS GCPhysAddrRecFis = pAhciPort->GCPhysAddrFb;
2615 unsigned cbFis = 0;
2616
2617 ahciLog(("%s: pAhciPort=%p uFisType=%u pCmdFis=%p\n", __FUNCTION__, pAhciPort, uFisType, pCmdFis));
2618
2619 if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
2620 {
2621 AssertMsg(GCPhysAddrRecFis, ("%s: GCPhysAddrRecFis is 0\n", __FUNCTION__));
2622
2623 /* Determine the offset and size of the FIS based on uFisType. */
2624 switch (uFisType)
2625 {
2626 case AHCI_CMDFIS_TYPE_D2H:
2627 {
2628 GCPhysAddrRecFis += AHCI_RECFIS_RFIS_OFFSET;
2629 cbFis = AHCI_CMDFIS_TYPE_D2H_SIZE;
2630 }
2631 break;
2632 case AHCI_CMDFIS_TYPE_SETDEVBITS:
2633 {
2634 GCPhysAddrRecFis += AHCI_RECFIS_SDBFIS_OFFSET;
2635 cbFis = AHCI_CMDFIS_TYPE_SETDEVBITS_SIZE;
2636 }
2637 break;
2638 case AHCI_CMDFIS_TYPE_DMASETUP:
2639 {
2640 GCPhysAddrRecFis += AHCI_RECFIS_DSFIS_OFFSET;
2641 cbFis = AHCI_CMDFIS_TYPE_DMASETUP_SIZE;
2642 }
2643 break;
2644 case AHCI_CMDFIS_TYPE_PIOSETUP:
2645 {
2646 GCPhysAddrRecFis += AHCI_RECFIS_PSFIS_OFFSET;
2647 cbFis = AHCI_CMDFIS_TYPE_PIOSETUP_SIZE;
2648 }
2649 break;
2650 default:
2651 /*
2652 * We should post the unknown FIS into memory too but this never happens because
2653 * we know which FIS types we generate. ;)
2654 */
2655 AssertMsgFailed(("%s: Unknown FIS type!\n", __FUNCTION__));
2656 }
2657
2658 /* Post the FIS into memory. */
2659 ahciLog(("%s: PDMDevHlpPhysWrite GCPhysAddrRecFis=%RGp cbFis=%u\n", __FUNCTION__, GCPhysAddrRecFis, cbFis));
2660 PDMDevHlpPhysWrite(pAhciPort->CTX_SUFF(pDevIns), GCPhysAddrRecFis, pCmdFis, cbFis);
2661 }
2662
2663 return rc;
2664}
2665
2666DECLINLINE(void) ataH2BE_U16(uint8_t *pbBuf, uint16_t val)
2667{
2668 pbBuf[0] = val >> 8;
2669 pbBuf[1] = val;
2670}
2671
2672
2673DECLINLINE(void) ataH2BE_U24(uint8_t *pbBuf, uint32_t val)
2674{
2675 pbBuf[0] = val >> 16;
2676 pbBuf[1] = val >> 8;
2677 pbBuf[2] = val;
2678}
2679
2680
2681DECLINLINE(void) ataH2BE_U32(uint8_t *pbBuf, uint32_t val)
2682{
2683 pbBuf[0] = val >> 24;
2684 pbBuf[1] = val >> 16;
2685 pbBuf[2] = val >> 8;
2686 pbBuf[3] = val;
2687}
2688
2689
2690DECLINLINE(uint16_t) ataBE2H_U16(const uint8_t *pbBuf)
2691{
2692 return (pbBuf[0] << 8) | pbBuf[1];
2693}
2694
2695
2696DECLINLINE(uint32_t) ataBE2H_U24(const uint8_t *pbBuf)
2697{
2698 return (pbBuf[0] << 16) | (pbBuf[1] << 8) | pbBuf[2];
2699}
2700
2701
2702DECLINLINE(uint32_t) ataBE2H_U32(const uint8_t *pbBuf)
2703{
2704 return (pbBuf[0] << 24) | (pbBuf[1] << 16) | (pbBuf[2] << 8) | pbBuf[3];
2705}
2706
2707
2708DECLINLINE(void) ataLBA2MSF(uint8_t *pbBuf, uint32_t iATAPILBA)
2709{
2710 iATAPILBA += 150;
2711 pbBuf[0] = (iATAPILBA / 75) / 60;
2712 pbBuf[1] = (iATAPILBA / 75) % 60;
2713 pbBuf[2] = iATAPILBA % 75;
2714}
2715
2716
2717DECLINLINE(uint32_t) ataMSF2LBA(const uint8_t *pbBuf)
2718{
2719 return (pbBuf[0] * 60 + pbBuf[1]) * 75 + pbBuf[2];
2720}
2721
2722static void atapiCmdOK(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState)
2723{
2724 pAhciPortTaskState->uATARegError = 0;
2725 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
2726 pAhciPortTaskState->cmdFis[AHCI_CMDFIS_SECTN] = (pAhciPortTaskState->cmdFis[AHCI_CMDFIS_SECTN] & ~7)
2727 | ((pAhciPortTaskState->enmTxDir != AHCITXDIR_WRITE) ? ATAPI_INT_REASON_IO : 0)
2728 | (!pAhciPortTaskState->cbTransfer ? ATAPI_INT_REASON_CD : 0);
2729 memset(pAhciPort->abATAPISense, '\0', sizeof(pAhciPort->abATAPISense));
2730 pAhciPort->abATAPISense[0] = 0x70;
2731 pAhciPort->abATAPISense[7] = 10;
2732}
2733
2734static void atapiCmdError(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState, const uint8_t *pabATAPISense, size_t cbATAPISense)
2735{
2736 Log(("%s: sense=%#x (%s) asc=%#x ascq=%#x (%s)\n", __FUNCTION__, pabATAPISense[2] & 0x0f, SCSISenseText(pabATAPISense[2] & 0x0f),
2737 pabATAPISense[12], pabATAPISense[13], SCSISenseExtText(pabATAPISense[12], pabATAPISense[13])));
2738 pAhciPortTaskState->uATARegError = pabATAPISense[2] << 4;
2739 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_ERR;
2740 pAhciPortTaskState->cmdFis[AHCI_CMDFIS_SECTN] = (pAhciPortTaskState->cmdFis[AHCI_CMDFIS_SECTN] & ~7) |
2741 ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
2742 memset(pAhciPort->abATAPISense, '\0', sizeof(pAhciPort->abATAPISense));
2743 memcpy(pAhciPort->abATAPISense, pabATAPISense, RT_MIN(cbATAPISense, sizeof(pAhciPort->abATAPISense)));
2744}
2745
2746/** @todo deprecated function - doesn't provide enough info. Replace by direct
2747 * calls to atapiCmdError() with full data. */
2748static void atapiCmdErrorSimple(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState, uint8_t uATAPISenseKey, uint8_t uATAPIASC)
2749{
2750 uint8_t abATAPISense[ATAPI_SENSE_SIZE];
2751 memset(abATAPISense, '\0', sizeof(abATAPISense));
2752 abATAPISense[0] = 0x70 | (1 << 7);
2753 abATAPISense[2] = uATAPISenseKey & 0x0f;
2754 abATAPISense[7] = 10;
2755 abATAPISense[12] = uATAPIASC;
2756 atapiCmdError(pAhciPort, pAhciPortTaskState, abATAPISense, sizeof(abATAPISense));
2757}
2758
2759static void ataSCSIPadStr(uint8_t *pbDst, const char *pbSrc, uint32_t cbSize)
2760{
2761 for (uint32_t i = 0; i < cbSize; i++)
2762 {
2763 if (*pbSrc)
2764 pbDst[i] = *pbSrc++;
2765 else
2766 pbDst[i] = ' ';
2767 }
2768}
2769
2770static void ataPadString(uint8_t *pbDst, const char *pbSrc, uint32_t cbSize)
2771{
2772 for (uint32_t i = 0; i < cbSize; i++)
2773 {
2774 if (*pbSrc)
2775 pbDst[i ^ 1] = *pbSrc++;
2776 else
2777 pbDst[i ^ 1] = ' ';
2778 }
2779}
2780
2781static uint32_t ataChecksum(void* ptr, size_t count)
2782{
2783 uint8_t u8Sum = 0xa5, *p = (uint8_t*)ptr;
2784 size_t i;
2785
2786 for (i = 0; i < count; i++)
2787 {
2788 u8Sum += *p++;
2789 }
2790
2791 return (uint8_t)-(int32_t)u8Sum;
2792}
2793
2794static int ahciIdentifySS(PAHCIPort pAhciPort, void *pvBuf)
2795{
2796 uint16_t *p;
2797 int rc = VINF_SUCCESS;
2798
2799 p = (uint16_t *)pvBuf;
2800 memset(p, 0, 512);
2801 p[0] = RT_H2LE_U16(0x0040);
2802 p[1] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383));
2803 p[3] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cHeads);
2804 /* Block size; obsolete, but required for the BIOS. */
2805 p[5] = RT_H2LE_U16(512);
2806 p[6] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cSectors);
2807 ataPadString((uint8_t *)(p + 10), pAhciPort->szSerialNumber, AHCI_SERIAL_NUMBER_LENGTH); /* serial number */
2808 p[20] = RT_H2LE_U16(3); /* XXX: retired, cache type */
2809 p[21] = RT_H2LE_U16(512); /* XXX: retired, cache size in sectors */
2810 p[22] = RT_H2LE_U16(0); /* ECC bytes per sector */
2811 ataPadString((uint8_t *)(p + 23), pAhciPort->szFirmwareRevision, AHCI_FIRMWARE_REVISION_LENGTH); /* firmware version */
2812 ataPadString((uint8_t *)(p + 27), pAhciPort->szModelNumber, AHCI_MODEL_NUMBER_LENGTH); /* model */
2813#if ATA_MAX_MULT_SECTORS > 1
2814 p[47] = RT_H2LE_U16(0x8000 | ATA_MAX_MULT_SECTORS);
2815#endif
2816 p[48] = RT_H2LE_U16(1); /* dword I/O, used by the BIOS */
2817 p[49] = RT_H2LE_U16(1 << 11 | 1 << 9 | 1 << 8); /* DMA and LBA supported */
2818 p[50] = RT_H2LE_U16(1 << 14); /* No drive specific standby timer minimum */
2819 p[51] = RT_H2LE_U16(240); /* PIO transfer cycle */
2820 p[52] = RT_H2LE_U16(240); /* DMA transfer cycle */
2821 p[53] = RT_H2LE_U16(1 | 1 << 1 | 1 << 2); /* words 54-58,64-70,88 valid */
2822 p[54] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383));
2823 p[55] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cHeads);
2824 p[56] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cSectors);
2825 p[57] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383) * pAhciPort->PCHSGeometry.cHeads * pAhciPort->PCHSGeometry.cSectors);
2826 p[58] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383) * pAhciPort->PCHSGeometry.cHeads * pAhciPort->PCHSGeometry.cSectors >> 16);
2827 if (pAhciPort->cMultSectors)
2828 p[59] = RT_H2LE_U16(0x100 | pAhciPort->cMultSectors);
2829 if (pAhciPort->cTotalSectors <= (1 << 28) - 1)
2830 {
2831 p[60] = RT_H2LE_U16(pAhciPort->cTotalSectors);
2832 p[61] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 16);
2833 }
2834 else
2835 {
2836 /* Report maximum number of sectors possible with LBA28 */
2837 p[60] = RT_H2LE_U16(((1 << 28) - 1) & 0xffff);
2838 p[61] = RT_H2LE_U16(((1 << 28) - 1) >> 16);
2839 }
2840 p[63] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_MDMA, ATA_MDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* MDMA modes supported / mode enabled */
2841 p[64] = RT_H2LE_U16(ATA_PIO_MODE_MAX > 2 ? (1 << (ATA_PIO_MODE_MAX - 2)) - 1 : 0); /* PIO modes beyond PIO2 supported */
2842 p[65] = RT_H2LE_U16(120); /* minimum DMA multiword tx cycle time */
2843 p[66] = RT_H2LE_U16(120); /* recommended DMA multiword tx cycle time */
2844 p[67] = RT_H2LE_U16(120); /* minimum PIO cycle time without flow control */
2845 p[68] = RT_H2LE_U16(120); /* minimum PIO cycle time with IORDY flow control */
2846 p[80] = RT_H2LE_U16(0x7e); /* support everything up to ATA/ATAPI-6 */
2847 p[81] = RT_H2LE_U16(0x22); /* conforms to ATA/ATAPI-6 */
2848 p[82] = RT_H2LE_U16(1 << 3 | 1 << 5 | 1 << 6); /* supports power management, write cache and look-ahead */
2849 p[83] = RT_H2LE_U16(1 << 14 | 1 << 10 | 1 << 12 | 1 << 13); /* supports LBA48, FLUSH CACHE and FLUSH CACHE EXT */
2850 p[84] = RT_H2LE_U16(1 << 14);
2851 p[85] = RT_H2LE_U16(1 << 3 | 1 << 5 | 1 << 6); /* enabled power management, write cache and look-ahead */
2852 p[86] = RT_H2LE_U16(1 << 10 | 1 << 12 | 1 << 13); /* enabled LBA48, FLUSH CACHE and FLUSH CACHE EXT */
2853 p[87] = RT_H2LE_U16(1 << 14);
2854 p[88] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_UDMA, ATA_UDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* UDMA modes supported / mode enabled */
2855 p[93] = RT_H2LE_U16(0x00);
2856 p[100] = RT_H2LE_U16(pAhciPort->cTotalSectors);
2857 p[101] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 16);
2858 p[102] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 32);
2859 p[103] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 48);
2860
2861 /* The following are SATA specific */
2862 p[75] = RT_H2LE_U16(31); /* We support 32 commands */
2863 p[76] = RT_H2LE_U16((1 << 8) | (1 << 2)); /* Native command queuing and Serial ATA Gen2 (3.0 Gbps) speed supported */
2864
2865 uint32_t uCsum = ataChecksum(p, 510);
2866 p[255] = RT_H2LE_U16(0xa5 | (uCsum << 8)); /* Integrity word */
2867
2868 return VINF_SUCCESS;
2869}
2870
2871typedef int (*PAtapiFunc)(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2872
2873static int atapiGetConfigurationSS(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2874static int atapiGetEventStatusNotificationSS(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2875static int atapiIdentifySS(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2876static int atapiInquirySS(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2877static int atapiMechanismStatusSS(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2878static int atapiModeSenseErrorRecoverySS(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2879static int atapiModeSenseCDStatusSS(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2880static int atapiReadCapacitySS(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2881static int atapiReadDiscInformationSS(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2882static int atapiReadTOCNormalSS(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2883static int atapiReadTOCMultiSS(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2884static int atapiReadTOCRawSS(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2885static int atapiReadTrackInformationSS(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2886static int atapiRequestSenseSS(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2887static int atapiPassthroughSS(PAHCIPORTTASKSTATE, PAHCIPort, int *);
2888
2889/**
2890 * Source/sink function indexes for g_apfnAtapiFuncs.
2891 */
2892typedef enum ATAPIFN
2893{
2894 ATAFN_SS_NULL = 0,
2895 ATAFN_SS_ATAPI_GET_CONFIGURATION,
2896 ATAFN_SS_ATAPI_GET_EVENT_STATUS_NOTIFICATION,
2897 ATAFN_SS_ATAPI_IDENTIFY,
2898 ATAFN_SS_ATAPI_INQUIRY,
2899 ATAFN_SS_ATAPI_MECHANISM_STATUS,
2900 ATAFN_SS_ATAPI_MODE_SENSE_ERROR_RECOVERY,
2901 ATAFN_SS_ATAPI_MODE_SENSE_CD_STATUS,
2902 ATAFN_SS_ATAPI_READ_CAPACITY,
2903 ATAFN_SS_ATAPI_READ_DISC_INFORMATION,
2904 ATAFN_SS_ATAPI_READ_TOC_NORMAL,
2905 ATAFN_SS_ATAPI_READ_TOC_MULTI,
2906 ATAFN_SS_ATAPI_READ_TOC_RAW,
2907 ATAFN_SS_ATAPI_READ_TRACK_INFORMATION,
2908 ATAFN_SS_ATAPI_REQUEST_SENSE,
2909 ATAFN_SS_ATAPI_PASSTHROUGH,
2910 ATAFN_SS_MAX
2911} ATAPIFN;
2912
2913/**
2914 * Array of source/sink functions, the index is ATAFNSS.
2915 * Make sure ATAFNSS and this array match!
2916 */
2917static const PAtapiFunc g_apfnAtapiFuncs[ATAFN_SS_MAX] =
2918{
2919 NULL,
2920 atapiGetConfigurationSS,
2921 atapiGetEventStatusNotificationSS,
2922 atapiIdentifySS,
2923 atapiInquirySS,
2924 atapiMechanismStatusSS,
2925 atapiModeSenseErrorRecoverySS,
2926 atapiModeSenseCDStatusSS,
2927 atapiReadCapacitySS,
2928 atapiReadDiscInformationSS,
2929 atapiReadTOCNormalSS,
2930 atapiReadTOCMultiSS,
2931 atapiReadTOCRawSS,
2932 atapiReadTrackInformationSS,
2933 atapiRequestSenseSS,
2934 atapiPassthroughSS
2935};
2936
2937static int atapiIdentifySS(PAHCIPORTTASKSTATE pAhciPortTaskState, PAHCIPort pAhciPort, int *pcbData)
2938{
2939 uint16_t p[256];
2940
2941 memset(p, 0, 512);
2942 /* Removable CDROM, 50us response, 12 byte packets */
2943 p[0] = RT_H2LE_U16(2 << 14 | 5 << 8 | 1 << 7 | 2 << 5 | 0 << 0);
2944 ataPadString((uint8_t *)(p + 10), pAhciPort->szSerialNumber, AHCI_SERIAL_NUMBER_LENGTH); /* serial number */
2945 p[20] = RT_H2LE_U16(3); /* XXX: retired, cache type */
2946 p[21] = RT_H2LE_U16(512); /* XXX: retired, cache size in sectors */
2947 ataPadString((uint8_t *)(p + 23), pAhciPort->szFirmwareRevision, AHCI_FIRMWARE_REVISION_LENGTH); /* firmware version */
2948 ataPadString((uint8_t *)(p + 27), pAhciPort->szModelNumber, AHCI_MODEL_NUMBER_LENGTH); /* model */
2949 p[49] = RT_H2LE_U16(1 << 11 | 1 << 9 | 1 << 8); /* DMA and LBA supported */
2950 p[50] = RT_H2LE_U16(1 << 14); /* No drive specific standby timer minimum */
2951 p[51] = RT_H2LE_U16(240); /* PIO transfer cycle */
2952 p[52] = RT_H2LE_U16(240); /* DMA transfer cycle */
2953 p[53] = RT_H2LE_U16(1 << 1 | 1 << 2); /* words 64-70,88 are valid */
2954 p[63] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_MDMA, ATA_MDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* MDMA modes supported / mode enabled */
2955 p[64] = RT_H2LE_U16(ATA_PIO_MODE_MAX > 2 ? (1 << (ATA_PIO_MODE_MAX - 2)) - 1 : 0); /* PIO modes beyond PIO2 supported */
2956 p[65] = RT_H2LE_U16(120); /* minimum DMA multiword tx cycle time */
2957 p[66] = RT_H2LE_U16(120); /* recommended DMA multiword tx cycle time */
2958 p[67] = RT_H2LE_U16(120); /* minimum PIO cycle time without flow control */
2959 p[68] = RT_H2LE_U16(120); /* minimum PIO cycle time with IORDY flow control */
2960 p[73] = RT_H2LE_U16(0x003e); /* ATAPI CDROM major */
2961 p[74] = RT_H2LE_U16(9); /* ATAPI CDROM minor */
2962 p[80] = RT_H2LE_U16(0x7e); /* support everything up to ATA/ATAPI-6 */
2963 p[81] = RT_H2LE_U16(0x22); /* conforms to ATA/ATAPI-6 */
2964 p[82] = RT_H2LE_U16(1 << 4 | 1 << 9); /* supports packet command set and DEVICE RESET */
2965 p[83] = RT_H2LE_U16(1 << 14);
2966 p[84] = RT_H2LE_U16(1 << 14);
2967 p[85] = RT_H2LE_U16(1 << 4 | 1 << 9); /* enabled packet command set and DEVICE RESET */
2968 p[86] = RT_H2LE_U16(0);
2969 p[87] = RT_H2LE_U16(1 << 14);
2970 p[88] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_UDMA, ATA_UDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* UDMA modes supported / mode enabled */
2971 p[93] = RT_H2LE_U16((1 | 1 << 1) << ((pAhciPort->iLUN & 1) == 0 ? 0 : 8) | 1 << 13 | 1 << 14);
2972
2973 /* The following are SATA specific */
2974 p[75] = RT_H2LE_U16(31); /* We support 32 commands */
2975 p[76] = RT_H2LE_U16((1 << 8) | (1 << 2)); /* Native command queuing and Serial ATA Gen2 (3.0 Gbps) speed supported */
2976
2977 /* Copy the buffer in to the scatter gather list. */
2978 *pcbData = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, (void *)&p[0], sizeof(p));
2979
2980 atapiCmdOK(pAhciPort, pAhciPortTaskState);
2981 return VINF_SUCCESS;
2982}
2983
2984static int atapiReadCapacitySS(PAHCIPORTTASKSTATE pAhciPortTaskState, PAHCIPort pAhciPort, int *pcbData)
2985{
2986 uint8_t aBuf[8];
2987
2988 ataH2BE_U32(aBuf, pAhciPort->cTotalSectors - 1);
2989 ataH2BE_U32(aBuf + 4, 2048);
2990
2991 /* Copy the buffer in to the scatter gather list. */
2992 *pcbData = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, (void *)&aBuf[0], sizeof(aBuf));
2993
2994 atapiCmdOK(pAhciPort, pAhciPortTaskState);
2995 return VINF_SUCCESS;
2996}
2997
2998
2999static int atapiReadDiscInformationSS(PAHCIPORTTASKSTATE pAhciPortTaskState, PAHCIPort pAhciPort, int *pcbData)
3000{
3001 uint8_t aBuf[34];
3002
3003 memset(aBuf, '\0', 34);
3004 ataH2BE_U16(aBuf, 32);
3005 aBuf[2] = (0 << 4) | (3 << 2) | (2 << 0); /* not erasable, complete session, complete disc */
3006 aBuf[3] = 1; /* number of first track */
3007 aBuf[4] = 1; /* number of sessions (LSB) */
3008 aBuf[5] = 1; /* first track number in last session (LSB) */
3009 aBuf[6] = 1; /* last track number in last session (LSB) */
3010 aBuf[7] = (0 << 7) | (0 << 6) | (1 << 5) | (0 << 2) | (0 << 0); /* disc id not valid, disc bar code not valid, unrestricted use, not dirty, not RW medium */
3011 aBuf[8] = 0; /* disc type = CD-ROM */
3012 aBuf[9] = 0; /* number of sessions (MSB) */
3013 aBuf[10] = 0; /* number of sessions (MSB) */
3014 aBuf[11] = 0; /* number of sessions (MSB) */
3015 ataH2BE_U32(aBuf + 16, 0x00ffffff); /* last session lead-in start time is not available */
3016 ataH2BE_U32(aBuf + 20, 0x00ffffff); /* last possible start time for lead-out is not available */
3017
3018 /* Copy the buffer in to the scatter gather list. */
3019 *pcbData = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, (void *)&aBuf[0], sizeof(aBuf));
3020
3021 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3022 return VINF_SUCCESS;
3023}
3024
3025
3026static int atapiReadTrackInformationSS(PAHCIPORTTASKSTATE pAhciPortTaskState, PAHCIPort pAhciPort, int *pcbData)
3027{
3028 uint8_t aBuf[36];
3029
3030 /* Accept address/number type of 1 only, and only track 1 exists. */
3031 if ((pAhciPortTaskState->aATAPICmd[1] & 0x03) != 1 || ataBE2H_U32(&pAhciPortTaskState->aATAPICmd[2]) != 1)
3032 {
3033 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
3034 return VINF_SUCCESS;
3035 }
3036 memset(aBuf, '\0', 36);
3037 ataH2BE_U16(aBuf, 34);
3038 aBuf[2] = 1; /* track number (LSB) */
3039 aBuf[3] = 1; /* session number (LSB) */
3040 aBuf[5] = (0 << 5) | (0 << 4) | (4 << 0); /* not damaged, primary copy, data track */
3041 aBuf[6] = (0 << 7) | (0 << 6) | (0 << 5) | (0 << 6) | (1 << 0); /* not reserved track, not blank, not packet writing, not fixed packet, data mode 1 */
3042 aBuf[7] = (0 << 1) | (0 << 0); /* last recorded address not valid, next recordable address not valid */
3043 ataH2BE_U32(aBuf + 8, 0); /* track start address is 0 */
3044 ataH2BE_U32(aBuf + 24, pAhciPort->cTotalSectors); /* track size */
3045 aBuf[32] = 0; /* track number (MSB) */
3046 aBuf[33] = 0; /* session number (MSB) */
3047
3048 /* Copy the buffer in to the scatter gather list. */
3049 *pcbData = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, (void *)&aBuf[0], sizeof(aBuf));
3050
3051 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3052 return VINF_SUCCESS;
3053}
3054
3055
3056static int atapiGetConfigurationSS(PAHCIPORTTASKSTATE pAhciPortTaskState, PAHCIPort pAhciPort, int *pcbData)
3057{
3058 uint8_t aBuf[32];
3059
3060 /* Accept valid request types only, and only starting feature 0. */
3061 if ((pAhciPortTaskState->aATAPICmd[1] & 0x03) == 3 || ataBE2H_U16(&pAhciPortTaskState->aATAPICmd[2]) != 0)
3062 {
3063 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
3064 return VINF_SUCCESS;
3065 }
3066 memset(aBuf, '\0', 32);
3067 ataH2BE_U32(aBuf, 16);
3068 /** @todo implement switching between CD-ROM and DVD-ROM profile (the only
3069 * way to differentiate them right now is based on the image size). Also
3070 * implement signalling "no current profile" if no medium is loaded. */
3071 ataH2BE_U16(aBuf + 6, 0x08); /* current profile: read-only CD */
3072
3073 ataH2BE_U16(aBuf + 8, 0); /* feature 0: list of profiles supported */
3074 aBuf[10] = (0 << 2) | (1 << 1) | (1 || 0); /* version 0, persistent, current */
3075 aBuf[11] = 8; /* additional bytes for profiles */
3076 /* The MMC-3 spec says that DVD-ROM read capability should be reported
3077 * before CD-ROM read capability. */
3078 ataH2BE_U16(aBuf + 12, 0x10); /* profile: read-only DVD */
3079 aBuf[14] = (0 << 0); /* NOT current profile */
3080 ataH2BE_U16(aBuf + 16, 0x08); /* profile: read only CD */
3081 aBuf[18] = (1 << 0); /* current profile */
3082
3083 /* Copy the buffer in to the scatter gather list. */
3084 *pcbData = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, (void *)&aBuf[0], sizeof(aBuf));
3085
3086 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3087 return VINF_SUCCESS;
3088}
3089
3090
3091static int atapiGetEventStatusNotificationSS(PAHCIPORTTASKSTATE pAhciPortTaskState, PAHCIPort pAhciPort, int *pcbData)
3092{
3093 uint8_t abBuf[8];
3094
3095 Assert(pAhciPortTaskState->enmTxDir == AHCITXDIR_READ);
3096 Assert(pAhciPortTaskState->cbTransfer <= 8);
3097
3098 if (!(pAhciPortTaskState->aATAPICmd[1] & 1))
3099 {
3100 /* no asynchronous operation supported */
3101 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
3102 return VINF_SUCCESS;
3103 }
3104
3105 uint32_t OldStatus, NewStatus;
3106 do
3107 {
3108 OldStatus = ASMAtomicReadU32(&pAhciPort->MediaEventStatus);
3109 NewStatus = ATA_EVENT_STATUS_UNCHANGED;
3110 switch (OldStatus)
3111 {
3112 case ATA_EVENT_STATUS_MEDIA_NEW:
3113 /* mount */
3114 ataH2BE_U16(abBuf + 0, 6);
3115 abBuf[2] = 0x04; /* media */
3116 abBuf[3] = 0x5e; /* supported = busy|media|external|power|operational */
3117 abBuf[4] = 0x02; /* new medium */
3118 abBuf[5] = 0x02; /* medium present / door closed */
3119 abBuf[6] = 0x00;
3120 abBuf[7] = 0x00;
3121 break;
3122
3123 case ATA_EVENT_STATUS_MEDIA_CHANGED:
3124 case ATA_EVENT_STATUS_MEDIA_REMOVED:
3125 /* umount */
3126 ataH2BE_U16(abBuf + 0, 6);
3127 abBuf[2] = 0x04; /* media */
3128 abBuf[3] = 0x5e; /* supported = busy|media|external|power|operational */
3129 abBuf[4] = 0x03; /* media removal */
3130 abBuf[5] = 0x00; /* medium absent / door closed */
3131 abBuf[6] = 0x00;
3132 abBuf[7] = 0x00;
3133 if (OldStatus == ATA_EVENT_STATUS_MEDIA_CHANGED)
3134 NewStatus = ATA_EVENT_STATUS_MEDIA_NEW;
3135 break;
3136
3137 case ATA_EVENT_STATUS_MEDIA_EJECT_REQUESTED: /* currently unused */
3138 ataH2BE_U16(abBuf + 0, 6);
3139 abBuf[2] = 0x04; /* media */
3140 abBuf[3] = 0x5e; /* supported = busy|media|external|power|operational */
3141 abBuf[4] = 0x01; /* eject requested (eject button pressed) */
3142 abBuf[5] = 0x02; /* medium present / door closed */
3143 abBuf[6] = 0x00;
3144 abBuf[7] = 0x00;
3145 break;
3146
3147 case ATA_EVENT_STATUS_UNCHANGED:
3148 default:
3149 ataH2BE_U16(abBuf + 0, 6);
3150 abBuf[2] = 0x01; /* operational change request / notification */
3151 abBuf[3] = 0x5e; /* supported = busy|media|external|power|operational */
3152 abBuf[4] = 0x00;
3153 abBuf[5] = 0x00;
3154 abBuf[6] = 0x00;
3155 abBuf[7] = 0x00;
3156 break;
3157 }
3158 } while (!ASMAtomicCmpXchgU32(&pAhciPort->MediaEventStatus, NewStatus, OldStatus));
3159
3160 *pcbData = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, (void *)&abBuf[0], sizeof(abBuf));
3161
3162 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3163 return VINF_SUCCESS;
3164}
3165
3166
3167static int atapiInquirySS(PAHCIPORTTASKSTATE pAhciPortTaskState, PAHCIPort pAhciPort, int *pcbData)
3168{
3169 uint8_t aBuf[36];
3170
3171 aBuf[0] = 0x05; /* CD-ROM */
3172 aBuf[1] = 0x80; /* removable */
3173 aBuf[2] = 0x00; /* ISO */
3174 aBuf[3] = 0x21; /* ATAPI-2 (XXX: put ATAPI-4 ?) */
3175 aBuf[4] = 31; /* additional length */
3176 aBuf[5] = 0; /* reserved */
3177 aBuf[6] = 0; /* reserved */
3178 aBuf[7] = 0; /* reserved */
3179 ataSCSIPadStr(aBuf + 8, pAhciPort->szInquiryVendorId, 8);
3180 ataSCSIPadStr(aBuf + 16, pAhciPort->szInquiryProductId, 16);
3181 ataSCSIPadStr(aBuf + 32, pAhciPort->szInquiryRevision, 4);
3182
3183 /* Copy the buffer in to the scatter gather list. */
3184 *pcbData = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, (void *)&aBuf[0], sizeof(aBuf));
3185
3186 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3187 return VINF_SUCCESS;
3188}
3189
3190
3191static int atapiModeSenseErrorRecoverySS(PAHCIPORTTASKSTATE pAhciPortTaskState, PAHCIPort pAhciPort, int *pcbData)
3192{
3193 uint8_t aBuf[16];
3194
3195 ataH2BE_U16(&aBuf[0], 16 + 6);
3196 aBuf[2] = 0x70;
3197 aBuf[3] = 0;
3198 aBuf[4] = 0;
3199 aBuf[5] = 0;
3200 aBuf[6] = 0;
3201 aBuf[7] = 0;
3202
3203 aBuf[8] = 0x01;
3204 aBuf[9] = 0x06;
3205 aBuf[10] = 0x00;
3206 aBuf[11] = 0x05;
3207 aBuf[12] = 0x00;
3208 aBuf[13] = 0x00;
3209 aBuf[14] = 0x00;
3210 aBuf[15] = 0x00;
3211
3212 /* Copy the buffer in to the scatter gather list. */
3213 *pcbData = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, (void *)&aBuf[0], sizeof(aBuf));
3214
3215 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3216 return VINF_SUCCESS;
3217}
3218
3219
3220static int atapiModeSenseCDStatusSS(PAHCIPORTTASKSTATE pAhciPortTaskState, PAHCIPort pAhciPort, int *pcbData)
3221{
3222 uint8_t aBuf[40];
3223
3224 ataH2BE_U16(&aBuf[0], 38);
3225 aBuf[2] = 0x70;
3226 aBuf[3] = 0;
3227 aBuf[4] = 0;
3228 aBuf[5] = 0;
3229 aBuf[6] = 0;
3230 aBuf[7] = 0;
3231
3232 aBuf[8] = 0x2a;
3233 aBuf[9] = 30; /* page length */
3234 aBuf[10] = 0x08; /* DVD-ROM read support */
3235 aBuf[11] = 0x00; /* no write support */
3236 /* The following claims we support audio play. This is obviously false,
3237 * but the Linux generic CDROM support makes many features depend on this
3238 * capability. If it's not set, this causes many things to be disabled. */
3239 aBuf[12] = 0x71; /* multisession support, mode 2 form 1/2 support, audio play */
3240 aBuf[13] = 0x00; /* no subchannel reads supported */
3241 aBuf[14] = (1 << 0) | (1 << 3) | (1 << 5); /* lock supported, eject supported, tray type loading mechanism */
3242 if (pAhciPort->pDrvMount->pfnIsLocked(pAhciPort->pDrvMount))
3243 aBuf[14] |= 1 << 1; /* report lock state */
3244 aBuf[15] = 0; /* no subchannel reads supported, no separate audio volume control, no changer etc. */
3245 ataH2BE_U16(&aBuf[16], 5632); /* (obsolete) claim 32x speed support */
3246 ataH2BE_U16(&aBuf[18], 2); /* number of audio volume levels */
3247 ataH2BE_U16(&aBuf[20], 128); /* buffer size supported in Kbyte - We don't have a buffer because we write directly into guest memory.
3248 Just write the value DevATA is using. */
3249 ataH2BE_U16(&aBuf[22], 5632); /* (obsolete) current read speed 32x */
3250 aBuf[24] = 0; /* reserved */
3251 aBuf[25] = 0; /* reserved for digital audio (see idx 15) */
3252 ataH2BE_U16(&aBuf[26], 0); /* (obsolete) maximum write speed */
3253 ataH2BE_U16(&aBuf[28], 0); /* (obsolete) current write speed */
3254 ataH2BE_U16(&aBuf[30], 0); /* copy management revision supported 0=no CSS */
3255 aBuf[32] = 0; /* reserved */
3256 aBuf[33] = 0; /* reserved */
3257 aBuf[34] = 0; /* reserved */
3258 aBuf[35] = 1; /* rotation control CAV */
3259 ataH2BE_U16(&aBuf[36], 0); /* current write speed */
3260 ataH2BE_U16(&aBuf[38], 0); /* number of write speed performance descriptors */
3261
3262 /* Copy the buffer in to the scatter gather list. */
3263 *pcbData = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, (void *)&aBuf[0], sizeof(aBuf));
3264
3265 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3266 return VINF_SUCCESS;
3267}
3268
3269
3270static int atapiRequestSenseSS(PAHCIPORTTASKSTATE pAhciPortTaskState, PAHCIPort pAhciPort, int *pcbData)
3271{
3272 /* Copy the buffer in to the scatter gather list. */
3273 *pcbData = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, pAhciPort->abATAPISense, sizeof(pAhciPort->abATAPISense));
3274
3275 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3276 return VINF_SUCCESS;
3277}
3278
3279
3280static int atapiMechanismStatusSS(PAHCIPORTTASKSTATE pAhciPortTaskState, PAHCIPort pAhciPort, int *pcbData)
3281{
3282 uint8_t aBuf[8];
3283
3284 ataH2BE_U16(&aBuf[0], 0);
3285 /* no current LBA */
3286 aBuf[2] = 0;
3287 aBuf[3] = 0;
3288 aBuf[4] = 0;
3289 aBuf[5] = 1;
3290 ataH2BE_U16(aBuf + 6, 0);
3291
3292 /* Copy the buffer in to the scatter gather list. */
3293 *pcbData = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, (void *)&aBuf[0], sizeof(aBuf));
3294
3295 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3296 return VINF_SUCCESS;
3297}
3298
3299
3300static int atapiReadTOCNormalSS(PAHCIPORTTASKSTATE pAhciPortTaskState, PAHCIPort pAhciPort, int *pcbData)
3301{
3302 uint8_t aBuf[20], *q, iStartTrack;
3303 bool fMSF;
3304 uint32_t cbSize;
3305
3306 fMSF = (pAhciPortTaskState->aATAPICmd[1] >> 1) & 1;
3307 iStartTrack = pAhciPortTaskState->aATAPICmd[6];
3308 if (iStartTrack > 1 && iStartTrack != 0xaa)
3309 {
3310 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
3311 return VINF_SUCCESS;
3312 }
3313 q = aBuf + 2;
3314 *q++ = 1; /* first session */
3315 *q++ = 1; /* last session */
3316 if (iStartTrack <= 1)
3317 {
3318 *q++ = 0; /* reserved */
3319 *q++ = 0x14; /* ADR, control */
3320 *q++ = 1; /* track number */
3321 *q++ = 0; /* reserved */
3322 if (fMSF)
3323 {
3324 *q++ = 0; /* reserved */
3325 ataLBA2MSF(q, 0);
3326 q += 3;
3327 }
3328 else
3329 {
3330 /* sector 0 */
3331 ataH2BE_U32(q, 0);
3332 q += 4;
3333 }
3334 }
3335 /* lead out track */
3336 *q++ = 0; /* reserved */
3337 *q++ = 0x14; /* ADR, control */
3338 *q++ = 0xaa; /* track number */
3339 *q++ = 0; /* reserved */
3340 if (fMSF)
3341 {
3342 *q++ = 0; /* reserved */
3343 ataLBA2MSF(q, pAhciPort->cTotalSectors);
3344 q += 3;
3345 }
3346 else
3347 {
3348 ataH2BE_U32(q, pAhciPort->cTotalSectors);
3349 q += 4;
3350 }
3351 cbSize = q - aBuf;
3352 ataH2BE_U16(aBuf, cbSize - 2);
3353
3354 /* Copy the buffer in to the scatter gather list. */
3355 *pcbData = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, (void *)&aBuf[0], cbSize);
3356
3357 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3358 return VINF_SUCCESS;
3359}
3360
3361
3362static int atapiReadTOCMultiSS(PAHCIPORTTASKSTATE pAhciPortTaskState, PAHCIPort pAhciPort, int *pcbData)
3363{
3364 uint8_t aBuf[12];
3365 bool fMSF;
3366
3367 fMSF = (pAhciPortTaskState->aATAPICmd[1] >> 1) & 1;
3368 /* multi session: only a single session defined */
3369/** @todo double-check this stuff against what a real drive says for a CD-ROM (not a CD-R) with only a single data session. Maybe solve the problem with "cdrdao read-toc" not being able to figure out whether numbers are in BCD or hex. */
3370 memset(aBuf, 0, 12);
3371 aBuf[1] = 0x0a;
3372 aBuf[2] = 0x01;
3373 aBuf[3] = 0x01;
3374 aBuf[5] = 0x14; /* ADR, control */
3375 aBuf[6] = 1; /* first track in last complete session */
3376 if (fMSF)
3377 {
3378 aBuf[8] = 0; /* reserved */
3379 ataLBA2MSF(&aBuf[9], 0);
3380 }
3381 else
3382 {
3383 /* sector 0 */
3384 ataH2BE_U32(aBuf + 8, 0);
3385 }
3386
3387 /* Copy the buffer in to the scatter gather list. */
3388 *pcbData = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, (void *)&aBuf[0], sizeof(aBuf));
3389
3390 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3391 return VINF_SUCCESS;
3392}
3393
3394
3395static int atapiReadTOCRawSS(PAHCIPORTTASKSTATE pAhciPortTaskState, PAHCIPort pAhciPort, int *pcbData)
3396{
3397 uint8_t aBuf[50]; /* Counted a maximum of 45 bytes but better be on the safe side. */
3398 uint8_t *q, iStartTrack;
3399 bool fMSF;
3400 uint32_t cbSize;
3401
3402 fMSF = (pAhciPortTaskState->aATAPICmd[1] >> 1) & 1;
3403 iStartTrack = pAhciPortTaskState->aATAPICmd[6];
3404
3405 q = aBuf + 2;
3406 *q++ = 1; /* first session */
3407 *q++ = 1; /* last session */
3408
3409 *q++ = 1; /* session number */
3410 *q++ = 0x14; /* data track */
3411 *q++ = 0; /* track number */
3412 *q++ = 0xa0; /* first track in program area */
3413 *q++ = 0; /* min */
3414 *q++ = 0; /* sec */
3415 *q++ = 0; /* frame */
3416 *q++ = 0;
3417 *q++ = 1; /* first track */
3418 *q++ = 0x00; /* disk type CD-DA or CD data */
3419 *q++ = 0;
3420
3421 *q++ = 1; /* session number */
3422 *q++ = 0x14; /* data track */
3423 *q++ = 0; /* track number */
3424 *q++ = 0xa1; /* last track in program area */
3425 *q++ = 0; /* min */
3426 *q++ = 0; /* sec */
3427 *q++ = 0; /* frame */
3428 *q++ = 0;
3429 *q++ = 1; /* last track */
3430 *q++ = 0;
3431 *q++ = 0;
3432
3433 *q++ = 1; /* session number */
3434 *q++ = 0x14; /* data track */
3435 *q++ = 0; /* track number */
3436 *q++ = 0xa2; /* lead-out */
3437 *q++ = 0; /* min */
3438 *q++ = 0; /* sec */
3439 *q++ = 0; /* frame */
3440 if (fMSF)
3441 {
3442 *q++ = 0; /* reserved */
3443 ataLBA2MSF(q, pAhciPort->cTotalSectors);
3444 q += 3;
3445 }
3446 else
3447 {
3448 ataH2BE_U32(q, pAhciPort->cTotalSectors);
3449 q += 4;
3450 }
3451
3452 *q++ = 1; /* session number */
3453 *q++ = 0x14; /* ADR, control */
3454 *q++ = 0; /* track number */
3455 *q++ = 1; /* point */
3456 *q++ = 0; /* min */
3457 *q++ = 0; /* sec */
3458 *q++ = 0; /* frame */
3459 if (fMSF)
3460 {
3461 *q++ = 0; /* reserved */
3462 ataLBA2MSF(q, 0);
3463 q += 3;
3464 }
3465 else
3466 {
3467 /* sector 0 */
3468 ataH2BE_U32(q, 0);
3469 q += 4;
3470 }
3471
3472 cbSize = q - aBuf;
3473 ataH2BE_U16(aBuf, cbSize - 2);
3474
3475 /* Copy the buffer in to the scatter gather list. */
3476 *pcbData = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, (void *)&aBuf[0], cbSize);
3477
3478 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3479 return VINF_SUCCESS;
3480}
3481
3482/**
3483 * Sets the given media track type.
3484 */
3485static uint32_t ataMediumTypeSet(PAHCIPort pAhciPort, uint32_t MediaTrackType)
3486{
3487 return ASMAtomicXchgU32(&pAhciPort->MediaTrackType, MediaTrackType);
3488}
3489
3490static int atapiPassthroughSS(PAHCIPORTTASKSTATE pAhciPortTaskState, PAHCIPort pAhciPort, int *pcbData)
3491{
3492 int rc = VINF_SUCCESS;
3493 uint8_t abATAPISense[ATAPI_SENSE_SIZE];
3494 uint32_t cbTransfer;
3495
3496 cbTransfer = pAhciPortTaskState->cbTransfer;
3497
3498 /* Simple heuristics: if there is at least one sector of data
3499 * to transfer, it's worth updating the LEDs. */
3500 if (cbTransfer >= 2048)
3501 {
3502 if (pAhciPortTaskState->enmTxDir != AHCITXDIR_WRITE)
3503 pAhciPort->Led.Asserted.s.fReading = pAhciPort->Led.Actual.s.fReading = 1;
3504 else
3505 pAhciPort->Led.Asserted.s.fWriting = pAhciPort->Led.Actual.s.fWriting = 1;
3506 }
3507
3508 if (cbTransfer > SCSI_MAX_BUFFER_SIZE)
3509 {
3510 /* Linux accepts commands with up to 100KB of data, but expects
3511 * us to handle commands with up to 128KB of data. The usual
3512 * imbalance of powers. */
3513 uint8_t aATAPICmd[ATAPI_PACKET_SIZE];
3514 uint32_t iATAPILBA, cSectors, cReqSectors, cbCurrTX;
3515 uint8_t *pbBuf = (uint8_t *)pAhciPortTaskState->pSGListHead[0].pvSeg;
3516
3517 Assert(pAhciPortTaskState->cSGListUsed == 1);
3518
3519 switch (pAhciPortTaskState->aATAPICmd[0])
3520 {
3521 case SCSI_READ_10:
3522 case SCSI_WRITE_10:
3523 case SCSI_WRITE_AND_VERIFY_10:
3524 iATAPILBA = ataBE2H_U32(pAhciPortTaskState->aATAPICmd + 2);
3525 cSectors = ataBE2H_U16(pAhciPortTaskState->aATAPICmd + 7);
3526 break;
3527 case SCSI_READ_12:
3528 case SCSI_WRITE_12:
3529 iATAPILBA = ataBE2H_U32(pAhciPortTaskState->aATAPICmd + 2);
3530 cSectors = ataBE2H_U32(pAhciPortTaskState->aATAPICmd + 6);
3531 break;
3532 case SCSI_READ_CD:
3533 iATAPILBA = ataBE2H_U32(pAhciPortTaskState->aATAPICmd + 2);
3534 cSectors = ataBE2H_U24(pAhciPortTaskState->aATAPICmd + 6);
3535 break;
3536 case SCSI_READ_CD_MSF:
3537 iATAPILBA = ataMSF2LBA(pAhciPortTaskState->aATAPICmd + 3);
3538 cSectors = ataMSF2LBA(pAhciPortTaskState->aATAPICmd + 6) - iATAPILBA;
3539 break;
3540 default:
3541 AssertMsgFailed(("Don't know how to split command %#04x\n", pAhciPortTaskState->aATAPICmd[0]));
3542 if (pAhciPort->cErrors++ < MAX_LOG_REL_ERRORS)
3543 LogRel(("AHCI: LUN#%d: CD-ROM passthrough split error\n", pAhciPort->iLUN));
3544 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE);
3545 return false;
3546 }
3547 memcpy(aATAPICmd, pAhciPortTaskState->aATAPICmd, ATAPI_PACKET_SIZE);
3548 cReqSectors = 0;
3549 for (uint32_t i = cSectors; i > 0; i -= cReqSectors)
3550 {
3551 if (i * pAhciPortTaskState->cbATAPISector > SCSI_MAX_BUFFER_SIZE)
3552 cReqSectors = SCSI_MAX_BUFFER_SIZE / pAhciPortTaskState->cbATAPISector;
3553 else
3554 cReqSectors = i;
3555 cbCurrTX = pAhciPortTaskState->cbATAPISector * cReqSectors;
3556 switch (pAhciPortTaskState->aATAPICmd[0])
3557 {
3558 case SCSI_READ_10:
3559 case SCSI_WRITE_10:
3560 case SCSI_WRITE_AND_VERIFY_10:
3561 ataH2BE_U32(aATAPICmd + 2, iATAPILBA);
3562 ataH2BE_U16(aATAPICmd + 7, cReqSectors);
3563 break;
3564 case SCSI_READ_12:
3565 case SCSI_WRITE_12:
3566 ataH2BE_U32(aATAPICmd + 2, iATAPILBA);
3567 ataH2BE_U32(aATAPICmd + 6, cReqSectors);
3568 break;
3569 case SCSI_READ_CD:
3570 ataH2BE_U32(aATAPICmd + 2, iATAPILBA);
3571 ataH2BE_U24(aATAPICmd + 6, cReqSectors);
3572 break;
3573 case SCSI_READ_CD_MSF:
3574 ataLBA2MSF(aATAPICmd + 3, iATAPILBA);
3575 ataLBA2MSF(aATAPICmd + 6, iATAPILBA + cReqSectors);
3576 break;
3577 }
3578 rc = pAhciPort->pDrvBlock->pfnSendCmd(pAhciPort->pDrvBlock,
3579 aATAPICmd,
3580 pAhciPortTaskState->enmTxDir == AHCITXDIR_READ
3581 ? PDMBLOCKTXDIR_FROM_DEVICE
3582 : PDMBLOCKTXDIR_TO_DEVICE,
3583 pbBuf,
3584 &cbCurrTX,
3585 abATAPISense,
3586 sizeof(abATAPISense),
3587 30000 /**< @todo timeout */);
3588 if (rc != VINF_SUCCESS)
3589 break;
3590 iATAPILBA += cReqSectors;
3591 pbBuf += pAhciPortTaskState->cbATAPISector * cReqSectors;
3592 }
3593 }
3594 else
3595 {
3596 PDMBLOCKTXDIR enmBlockTxDir = PDMBLOCKTXDIR_NONE;
3597
3598 if (pAhciPortTaskState->enmTxDir == AHCITXDIR_READ)
3599 enmBlockTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3600 else if (pAhciPortTaskState->enmTxDir == AHCITXDIR_WRITE)
3601 enmBlockTxDir = PDMBLOCKTXDIR_TO_DEVICE;
3602 else if (pAhciPortTaskState->enmTxDir == AHCITXDIR_NONE)
3603 enmBlockTxDir = PDMBLOCKTXDIR_NONE;
3604 else
3605 AssertMsgFailed(("Invalid transfer direction %d\n", pAhciPortTaskState->enmTxDir));
3606
3607 rc = pAhciPort->pDrvBlock->pfnSendCmd(pAhciPort->pDrvBlock,
3608 pAhciPortTaskState->aATAPICmd,
3609 enmBlockTxDir,
3610 pAhciPortTaskState->pSGListHead[0].pvSeg,
3611 &cbTransfer,
3612 abATAPISense,
3613 sizeof(abATAPISense),
3614 30000 /**< @todo timeout */);
3615 }
3616
3617 /* Update the LEDs and the read/write statistics. */
3618 if (cbTransfer >= 2048)
3619 {
3620 if (pAhciPortTaskState->enmTxDir != AHCITXDIR_WRITE)
3621 {
3622 pAhciPort->Led.Actual.s.fReading = 0;
3623 STAM_REL_COUNTER_ADD(&pAhciPort->StatBytesRead, cbTransfer);
3624 }
3625 else
3626 {
3627 pAhciPort->Led.Actual.s.fWriting = 0;
3628 STAM_REL_COUNTER_ADD(&pAhciPort->StatBytesWritten, cbTransfer);
3629 }
3630 }
3631
3632 if (RT_SUCCESS(rc))
3633 {
3634 Assert(cbTransfer <= pAhciPortTaskState->cbTransfer);
3635 /* Reply with the same amount of data as the real drive. */
3636 *pcbData = cbTransfer;
3637
3638 if (pAhciPortTaskState->enmTxDir == AHCITXDIR_READ)
3639 {
3640 if (pAhciPortTaskState->aATAPICmd[0] == SCSI_INQUIRY)
3641 {
3642 /* Make sure that the real drive cannot be identified.
3643 * Motivation: changing the VM configuration should be as
3644 * invisible as possible to the guest. */
3645 ataSCSIPadStr((uint8_t *)pAhciPortTaskState->pSGListHead[0].pvSeg + 8, "VBOX", 8);
3646 ataSCSIPadStr((uint8_t *)pAhciPortTaskState->pSGListHead[0].pvSeg + 16, "CD-ROM", 16);
3647 ataSCSIPadStr((uint8_t *)pAhciPortTaskState->pSGListHead[0].pvSeg + 32, "1.0", 4);
3648 }
3649 else if (pAhciPortTaskState->aATAPICmd[0] == SCSI_READ_TOC_PMA_ATIP)
3650 {
3651 /* Set the media type if we can detect it. */
3652 uint8_t *pbBuf = (uint8_t *)pAhciPortTaskState->pSGListHead[0].pvSeg;
3653
3654 /** @todo: Implemented only for formatted TOC now. */
3655 if ( (pAhciPortTaskState->aATAPICmd[1] & 0xf) == 0
3656 && cbTransfer >= 6)
3657 {
3658 uint32_t NewMediaType;
3659 uint32_t OldMediaType;
3660
3661 if (pbBuf[5] & 0x4)
3662 NewMediaType = ATA_MEDIA_TYPE_DATA;
3663 else
3664 NewMediaType = ATA_MEDIA_TYPE_CDDA;
3665
3666 OldMediaType = ataMediumTypeSet(pAhciPort, NewMediaType);
3667
3668 if (OldMediaType != NewMediaType)
3669 LogRel(("AHCI: LUN#%d: CD-ROM passthrough, detected %s CD\n",
3670 pAhciPort->iLUN,
3671 NewMediaType == ATA_MEDIA_TYPE_DATA
3672 ? "data"
3673 : "audio"));
3674 }
3675 else /* Play safe and set to unknown. */
3676 ataMediumTypeSet(pAhciPort, ATA_MEDIA_TYPE_UNKNOWN);
3677 }
3678 if (cbTransfer)
3679 Log3(("ATAPI PT data read (%d): %.*Rhxs\n", cbTransfer, cbTransfer, (uint8_t *)pAhciPortTaskState->pSGListHead[0].pvSeg));
3680 }
3681 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3682 }
3683 else
3684 {
3685 if (pAhciPort->cErrors < MAX_LOG_REL_ERRORS)
3686 {
3687 uint8_t u8Cmd = pAhciPortTaskState->aATAPICmd[0];
3688 do
3689 {
3690 /* don't log superfluous errors */
3691 if ( rc == VERR_DEV_IO_ERROR
3692 && ( u8Cmd == SCSI_TEST_UNIT_READY
3693 || u8Cmd == SCSI_READ_CAPACITY
3694 || u8Cmd == SCSI_READ_DVD_STRUCTURE
3695 || u8Cmd == SCSI_READ_TOC_PMA_ATIP))
3696 break;
3697 pAhciPort->cErrors++;
3698 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM passthrough cmd=%#04x sense=%d ASC=%#02x ASCQ=%#02x %Rrc\n",
3699 pAhciPort->iLUN, u8Cmd, abATAPISense[2] & 0x0f, abATAPISense[12], abATAPISense[13], rc));
3700 } while (0);
3701 }
3702 atapiCmdError(pAhciPort, pAhciPortTaskState, abATAPISense, sizeof(abATAPISense));
3703 }
3704 return false;
3705}
3706
3707static int atapiDoTransfer(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState, ATAPIFN iSourceSink)
3708{
3709 int cbTransfered = 0;
3710 int rc, rcSourceSink;
3711
3712 /*
3713 * Create scatter gather list. We use a safe mapping here because it is
3714 * possible that the buffer is not a multiple of 512. The normal
3715 * creator would assert later here.
3716 */
3717 ahciScatterGatherListGetTotalBufferSize(pAhciPort, pAhciPortTaskState);
3718 if (pAhciPortTaskState->cbSGBuffers)
3719 {
3720 rc = ahciScatterGatherListCreateSafe(pAhciPort, pAhciPortTaskState, false, 0);
3721 AssertRC(rc);
3722 }
3723
3724 rcSourceSink = g_apfnAtapiFuncs[iSourceSink](pAhciPortTaskState, pAhciPort, &cbTransfered);
3725
3726 pAhciPortTaskState->cmdHdr.u32PRDBC = cbTransfered;
3727
3728 LogFlow(("cbTransfered=%d\n", cbTransfered));
3729
3730 if (pAhciPortTaskState->cbSGBuffers)
3731 {
3732 rc = ahciScatterGatherListDestroy(pAhciPort, pAhciPortTaskState);
3733 AssertRC(rc);
3734 }
3735
3736 /* Write updated command header into memory of the guest. */
3737 PDMDevHlpPhysWrite(pAhciPort->CTX_SUFF(pDevIns), pAhciPortTaskState->GCPhysCmdHdrAddr, &pAhciPortTaskState->cmdHdr, sizeof(CmdHdr));
3738
3739 return rcSourceSink;
3740}
3741
3742static int atapiReadSectors2352PostProcess(PAHCIPORTTASKSTATE pAhciPortTaskState)
3743{
3744 uint32_t cSectors = pAhciPortTaskState->cbTransfer / 2048;
3745 uint32_t iATAPILBA = pAhciPortTaskState->uOffset / 2048;
3746 uint8_t *pbBufDst = (uint8_t *)pAhciPortTaskState->pvBufferUnaligned;
3747 uint8_t *pbBufSrc = (uint8_t *)pAhciPortTaskState->pSGListHead[0].pvSeg;
3748
3749 for (uint32_t i = iATAPILBA; i < iATAPILBA + cSectors; i++)
3750 {
3751 /* sync bytes */
3752 *pbBufDst++ = 0x00;
3753 memset(pbBufDst, 0xff, 11);
3754 pbBufDst += 11;
3755 /* MSF */
3756 ataLBA2MSF(pbBufDst, i);
3757 pbBufDst += 3;
3758 *pbBufDst++ = 0x01; /* mode 1 data */
3759 /* data */
3760 memcpy(pbBufDst, pbBufSrc, 2048);
3761 pbBufDst += 2048;
3762 pbBufSrc += 2048;
3763 /* ECC */
3764 memset(pbBufDst, 0, 288);
3765 pbBufDst += 288;
3766 }
3767
3768 return VINF_SUCCESS;
3769}
3770
3771static int atapiReadSectors(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState, uint32_t iATAPILBA, uint32_t cSectors, uint32_t cbSector)
3772{
3773 Log(("%s: %d sectors at LBA %d\n", __FUNCTION__, cSectors, iATAPILBA));
3774
3775 switch (cbSector)
3776 {
3777 case 2048:
3778 pAhciPortTaskState->uOffset = iATAPILBA * cbSector;
3779 pAhciPortTaskState->cbTransfer = cSectors * cbSector;
3780 break;
3781 case 2352:
3782 {
3783 pAhciPortTaskState->pfnPostProcess = atapiReadSectors2352PostProcess;
3784 pAhciPortTaskState->uOffset = iATAPILBA * 2048;
3785 pAhciPortTaskState->cbTransfer = cSectors * 2048;
3786 break;
3787 }
3788 default:
3789 AssertMsgFailed(("Unsupported sectors size\n"));
3790 break;
3791 }
3792
3793 return VINF_SUCCESS;
3794}
3795
3796static AHCITXDIR atapiParseCmdVirtualATAPI(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState)
3797{
3798 AHCITXDIR rc = AHCITXDIR_NONE;
3799 const uint8_t *pbPacket;
3800 uint32_t cbMax;
3801
3802 pbPacket = pAhciPortTaskState->aATAPICmd;
3803
3804 ahciLog(("%s: ATAPI CMD=%#04x \"%s\"\n", __FUNCTION__, pbPacket[0], SCSICmdText(pbPacket[0])));
3805
3806 switch (pbPacket[0])
3807 {
3808 case SCSI_TEST_UNIT_READY:
3809 if (pAhciPort->cNotifiedMediaChange > 0)
3810 {
3811 if (pAhciPort->cNotifiedMediaChange-- > 2)
3812 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3813 else
3814 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3815 }
3816 else if (pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
3817 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3818 else
3819 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3820 break;
3821 case SCSI_GET_EVENT_STATUS_NOTIFICATION:
3822 cbMax = ataBE2H_U16(pbPacket + 7);
3823 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_GET_EVENT_STATUS_NOTIFICATION);
3824 break;
3825 case SCSI_MODE_SENSE_10:
3826 {
3827 uint8_t uPageControl, uPageCode;
3828 cbMax = ataBE2H_U16(pbPacket + 7);
3829 uPageControl = pbPacket[2] >> 6;
3830 uPageCode = pbPacket[2] & 0x3f;
3831 switch (uPageControl)
3832 {
3833 case SCSI_PAGECONTROL_CURRENT:
3834 switch (uPageCode)
3835 {
3836 case SCSI_MODEPAGE_ERROR_RECOVERY:
3837 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_MODE_SENSE_ERROR_RECOVERY);
3838 break;
3839 case SCSI_MODEPAGE_CD_STATUS:
3840 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_MODE_SENSE_CD_STATUS);
3841 break;
3842 default:
3843 goto error_cmd;
3844 }
3845 break;
3846 case SCSI_PAGECONTROL_CHANGEABLE:
3847 goto error_cmd;
3848 case SCSI_PAGECONTROL_DEFAULT:
3849 goto error_cmd;
3850 default:
3851 case SCSI_PAGECONTROL_SAVED:
3852 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_SAVING_PARAMETERS_NOT_SUPPORTED);
3853 break;
3854 }
3855 }
3856 break;
3857 case SCSI_REQUEST_SENSE:
3858 cbMax = pbPacket[4];
3859 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_REQUEST_SENSE);
3860 break;
3861 case SCSI_PREVENT_ALLOW_MEDIUM_REMOVAL:
3862 if (pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
3863 {
3864 if (pbPacket[4] & 1)
3865 pAhciPort->pDrvMount->pfnLock(pAhciPort->pDrvMount);
3866 else
3867 pAhciPort->pDrvMount->pfnUnlock(pAhciPort->pDrvMount);
3868 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3869 }
3870 else
3871 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3872 break;
3873 case SCSI_READ_10:
3874 case SCSI_READ_12:
3875 {
3876 uint32_t cSectors, iATAPILBA;
3877
3878 if (pAhciPort->cNotifiedMediaChange > 0)
3879 {
3880 pAhciPort->cNotifiedMediaChange-- ;
3881 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3882 break;
3883 }
3884 else if (!pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
3885 {
3886 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3887 break;
3888 }
3889 if (pbPacket[0] == SCSI_READ_10)
3890 cSectors = ataBE2H_U16(pbPacket + 7);
3891 else
3892 cSectors = ataBE2H_U32(pbPacket + 6);
3893 iATAPILBA = ataBE2H_U32(pbPacket + 2);
3894 if (cSectors == 0)
3895 {
3896 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3897 break;
3898 }
3899 if ((uint64_t)iATAPILBA + cSectors > pAhciPort->cTotalSectors)
3900 {
3901 /* Rate limited logging, one log line per second. For
3902 * guests that insist on reading from places outside the
3903 * valid area this often generates too many release log
3904 * entries otherwise. */
3905 static uint64_t uLastLogTS = 0;
3906 if (RTTimeMilliTS() >= uLastLogTS + 1000)
3907 {
3908 LogRel(("AHCI ATAPI: LUN#%d: CD-ROM block number %Ld invalid (READ)\n", pAhciPort->iLUN, (uint64_t)iATAPILBA + cSectors));
3909 uLastLogTS = RTTimeMilliTS();
3910 }
3911 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_LOGICAL_BLOCK_OOR);
3912 break;
3913 }
3914 atapiReadSectors(pAhciPort, pAhciPortTaskState, iATAPILBA, cSectors, 2048);
3915 rc = AHCITXDIR_READ;
3916 }
3917 break;
3918 case SCSI_READ_CD:
3919 {
3920 uint32_t cSectors, iATAPILBA;
3921
3922 if (pAhciPort->cNotifiedMediaChange > 0)
3923 {
3924 pAhciPort->cNotifiedMediaChange-- ;
3925 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3926 break;
3927 }
3928 else if (!pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
3929 {
3930 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3931 break;
3932 }
3933 cSectors = (pbPacket[6] << 16) | (pbPacket[7] << 8) | pbPacket[8];
3934 iATAPILBA = ataBE2H_U32(pbPacket + 2);
3935 if (cSectors == 0)
3936 {
3937 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3938 break;
3939 }
3940 if ((uint64_t)iATAPILBA + cSectors > pAhciPort->cTotalSectors)
3941 {
3942 /* Rate limited logging, one log line per second. For
3943 * guests that insist on reading from places outside the
3944 * valid area this often generates too many release log
3945 * entries otherwise. */
3946 static uint64_t uLastLogTS = 0;
3947 if (RTTimeMilliTS() >= uLastLogTS + 1000)
3948 {
3949 LogRel(("AHCI ATA: LUN#%d: CD-ROM block number %Ld invalid (READ CD)\n", pAhciPort->iLUN, (uint64_t)iATAPILBA + cSectors));
3950 uLastLogTS = RTTimeMilliTS();
3951 }
3952 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_LOGICAL_BLOCK_OOR);
3953 break;
3954 }
3955 switch (pbPacket[9] & 0xf8)
3956 {
3957 case 0x00:
3958 /* nothing */
3959 atapiCmdOK(pAhciPort, pAhciPortTaskState);
3960 break;
3961 case 0x10:
3962 /* normal read */
3963 atapiReadSectors(pAhciPort, pAhciPortTaskState, iATAPILBA, cSectors, 2048);
3964 rc = AHCITXDIR_READ;
3965 break;
3966 case 0xf8:
3967 /* read all data */
3968 atapiReadSectors(pAhciPort, pAhciPortTaskState, iATAPILBA, cSectors, 2352);
3969 rc = AHCITXDIR_READ;
3970 break;
3971 default:
3972 LogRel(("AHCI ATAPI: LUN#%d: CD-ROM sector format not supported\n", pAhciPort->iLUN));
3973 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
3974 break;
3975 }
3976 }
3977 break;
3978 case SCSI_SEEK_10:
3979 {
3980 uint32_t iATAPILBA;
3981 if (pAhciPort->cNotifiedMediaChange > 0)
3982 {
3983 pAhciPort->cNotifiedMediaChange-- ;
3984 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3985 break;
3986 }
3987 else if (!pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
3988 {
3989 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3990 break;
3991 }
3992 iATAPILBA = ataBE2H_U32(pbPacket + 2);
3993 if (iATAPILBA > pAhciPort->cTotalSectors)
3994 {
3995 /* Rate limited logging, one log line per second. For
3996 * guests that insist on seeking to places outside the
3997 * valid area this often generates too many release log
3998 * entries otherwise. */
3999 static uint64_t uLastLogTS = 0;
4000 if (RTTimeMilliTS() >= uLastLogTS + 1000)
4001 {
4002 LogRel(("AHCI ATAPI: LUN#%d: CD-ROM block number %Ld invalid (SEEK)\n", pAhciPort->iLUN, (uint64_t)iATAPILBA));
4003 uLastLogTS = RTTimeMilliTS();
4004 }
4005 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_LOGICAL_BLOCK_OOR);
4006 break;
4007 }
4008 atapiCmdOK(pAhciPort, pAhciPortTaskState);
4009 pAhciPortTaskState->uATARegStatus |= ATA_STAT_SEEK; /* Linux expects this. */
4010 }
4011 break;
4012 case SCSI_START_STOP_UNIT:
4013 {
4014 int rc2 = VINF_SUCCESS;
4015 switch (pbPacket[4] & 3)
4016 {
4017 case 0: /* 00 - Stop motor */
4018 case 1: /* 01 - Start motor */
4019 break;
4020 case 2: /* 10 - Eject media */
4021 /* This must be done from EMT. */
4022 {
4023 PAHCI pAhci = pAhciPort->CTX_SUFF(pAhci);
4024 PPDMDEVINS pDevIns = pAhci->CTX_SUFF(pDevIns);
4025
4026 rc2 = VMR3ReqCallWait(PDMDevHlpGetVM(pDevIns), VMCPUID_ANY,
4027 (PFNRT)pAhciPort->pDrvMount->pfnUnmount, 2, pAhciPort->pDrvMount, false);
4028 Assert(RT_SUCCESS(rc2) || (rc == VERR_PDM_MEDIA_LOCKED));
4029 }
4030 break;
4031 case 3: /* 11 - Load media */
4032 /** @todo rc = s->pDrvMount->pfnLoadMedia(s->pDrvMount) */
4033 break;
4034 }
4035 if (RT_SUCCESS(rc2))
4036 atapiCmdOK(pAhciPort, pAhciPortTaskState);
4037 else
4038 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIA_LOAD_OR_EJECT_FAILED);
4039 }
4040 break;
4041 case SCSI_MECHANISM_STATUS:
4042 {
4043 cbMax = ataBE2H_U16(pbPacket + 8);
4044 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_MECHANISM_STATUS);
4045 }
4046 break;
4047 case SCSI_READ_TOC_PMA_ATIP:
4048 {
4049 uint8_t format;
4050
4051 if (pAhciPort->cNotifiedMediaChange > 0)
4052 {
4053 pAhciPort->cNotifiedMediaChange-- ;
4054 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
4055 break;
4056 }
4057 else if (!pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
4058 {
4059 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
4060 break;
4061 }
4062 cbMax = ataBE2H_U16(pbPacket + 7);
4063 /* SCSI MMC-3 spec says format is at offset 2 (lower 4 bits),
4064 * but Linux kernel uses offset 9 (topmost 2 bits). Hope that
4065 * the other field is clear... */
4066 format = (pbPacket[2] & 0xf) | (pbPacket[9] >> 6);
4067 switch (format)
4068 {
4069 case 0:
4070 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_READ_TOC_NORMAL);
4071 break;
4072 case 1:
4073 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_READ_TOC_MULTI);
4074 break;
4075 case 2:
4076 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_READ_TOC_RAW);
4077 break;
4078 default:
4079 error_cmd:
4080 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
4081 break;
4082 }
4083 }
4084 break;
4085 case SCSI_READ_CAPACITY:
4086 if (pAhciPort->cNotifiedMediaChange > 0)
4087 {
4088 pAhciPort->cNotifiedMediaChange-- ;
4089 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
4090 break;
4091 }
4092 else if (!pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
4093 {
4094 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
4095 break;
4096 }
4097 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_READ_CAPACITY);
4098 break;
4099 case SCSI_READ_DISC_INFORMATION:
4100 if (pAhciPort->cNotifiedMediaChange > 0)
4101 {
4102 pAhciPort->cNotifiedMediaChange-- ;
4103 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
4104 break;
4105 }
4106 else if (!pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
4107 {
4108 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
4109 break;
4110 }
4111 cbMax = ataBE2H_U16(pbPacket + 7);
4112 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_READ_DISC_INFORMATION);
4113 break;
4114 case SCSI_READ_TRACK_INFORMATION:
4115 if (pAhciPort->cNotifiedMediaChange > 0)
4116 {
4117 pAhciPort->cNotifiedMediaChange-- ;
4118 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
4119 break;
4120 }
4121 else if (!pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
4122 {
4123 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
4124 break;
4125 }
4126 cbMax = ataBE2H_U16(pbPacket + 7);
4127 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_READ_TRACK_INFORMATION);
4128 break;
4129 case SCSI_GET_CONFIGURATION:
4130 /* No media change stuff here, it can confuse Linux guests. */
4131 cbMax = ataBE2H_U16(pbPacket + 7);
4132 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_GET_CONFIGURATION);
4133 break;
4134 case SCSI_INQUIRY:
4135 cbMax = pbPacket[4];
4136 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_INQUIRY);
4137 break;
4138 default:
4139 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE);
4140 break;
4141 }
4142
4143 return rc;
4144}
4145
4146/*
4147 * Parse ATAPI commands, passing them directly to the CD/DVD drive.
4148 */
4149static AHCITXDIR atapiParseCmdPassthrough(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState)
4150{
4151 const uint8_t *pbPacket;
4152 uint32_t cSectors, iATAPILBA;
4153 uint32_t cbTransfer = 0;
4154 AHCITXDIR enmTxDir = AHCITXDIR_NONE;
4155
4156 pbPacket = pAhciPortTaskState->aATAPICmd;
4157 switch (pbPacket[0])
4158 {
4159 case SCSI_BLANK:
4160 goto sendcmd;
4161 case SCSI_CLOSE_TRACK_SESSION:
4162 goto sendcmd;
4163 case SCSI_ERASE_10:
4164 iATAPILBA = ataBE2H_U32(pbPacket + 2);
4165 cbTransfer = ataBE2H_U16(pbPacket + 7);
4166 Log2(("ATAPI PT: lba %d\n", iATAPILBA));
4167 enmTxDir = AHCITXDIR_WRITE;
4168 goto sendcmd;
4169 case SCSI_FORMAT_UNIT:
4170 cbTransfer = pAhciPortTaskState->cmdFis[AHCI_CMDFIS_CYLL] | (pAhciPortTaskState->cmdFis[AHCI_CMDFIS_CYLH] << 8); /* use ATAPI transfer length */
4171 enmTxDir = AHCITXDIR_WRITE;
4172 goto sendcmd;
4173 case SCSI_GET_CONFIGURATION:
4174 cbTransfer = ataBE2H_U16(pbPacket + 7);
4175 enmTxDir = AHCITXDIR_READ;
4176 goto sendcmd;
4177 case SCSI_GET_EVENT_STATUS_NOTIFICATION:
4178 cbTransfer = ataBE2H_U16(pbPacket + 7);
4179 if (ASMAtomicReadU32(&pAhciPort->MediaEventStatus) != ATA_EVENT_STATUS_UNCHANGED)
4180 {
4181 pAhciPortTaskState->cbTransfer = RT_MIN(cbTransfer, 8);
4182 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_GET_EVENT_STATUS_NOTIFICATION);
4183 break;
4184 }
4185 enmTxDir = AHCITXDIR_READ;
4186 goto sendcmd;
4187 case SCSI_GET_PERFORMANCE:
4188 cbTransfer = pAhciPortTaskState->cmdFis[AHCI_CMDFIS_CYLL] | (pAhciPortTaskState->cmdFis[AHCI_CMDFIS_CYLH] << 8); /* use ATAPI transfer length */
4189 enmTxDir = AHCITXDIR_READ;
4190 goto sendcmd;
4191 case SCSI_INQUIRY:
4192 cbTransfer = ataBE2H_U16(pbPacket + 3);
4193 enmTxDir = AHCITXDIR_READ;
4194 goto sendcmd;
4195 case SCSI_LOAD_UNLOAD_MEDIUM:
4196 goto sendcmd;
4197 case SCSI_MECHANISM_STATUS:
4198 cbTransfer = ataBE2H_U16(pbPacket + 8);
4199 enmTxDir = AHCITXDIR_READ;
4200 goto sendcmd;
4201 case SCSI_MODE_SELECT_10:
4202 cbTransfer = ataBE2H_U16(pbPacket + 7);
4203 enmTxDir = AHCITXDIR_WRITE;
4204 goto sendcmd;
4205 case SCSI_MODE_SENSE_10:
4206 cbTransfer = ataBE2H_U16(pbPacket + 7);
4207 enmTxDir = AHCITXDIR_READ;
4208 goto sendcmd;
4209 case SCSI_PAUSE_RESUME:
4210 goto sendcmd;
4211 case SCSI_PLAY_AUDIO_10:
4212 goto sendcmd;
4213 case SCSI_PLAY_AUDIO_12:
4214 goto sendcmd;
4215 case SCSI_PLAY_AUDIO_MSF:
4216 goto sendcmd;
4217 case SCSI_PREVENT_ALLOW_MEDIUM_REMOVAL:
4218 /** @todo do not forget to unlock when a VM is shut down */
4219 goto sendcmd;
4220 case SCSI_READ_10:
4221 iATAPILBA = ataBE2H_U32(pbPacket + 2);
4222 cSectors = ataBE2H_U16(pbPacket + 7);
4223 Log2(("ATAPI PT: lba %d sectors %d\n", iATAPILBA, cSectors));
4224 pAhciPortTaskState->cbATAPISector = 2048; /**< @todo this size is not always correct */
4225 cbTransfer = cSectors * pAhciPortTaskState->cbATAPISector;
4226 enmTxDir = AHCITXDIR_READ;
4227 goto sendcmd;
4228 case SCSI_READ_12:
4229 iATAPILBA = ataBE2H_U32(pbPacket + 2);
4230 cSectors = ataBE2H_U32(pbPacket + 6);
4231 Log2(("ATAPI PT: lba %d sectors %d\n", iATAPILBA, cSectors));
4232 pAhciPortTaskState->cbATAPISector = 2048; /**< @todo this size is not always correct */
4233 cbTransfer = cSectors * pAhciPortTaskState->cbATAPISector;
4234 enmTxDir = AHCITXDIR_READ;
4235 goto sendcmd;
4236 case SCSI_READ_BUFFER:
4237 cbTransfer = ataBE2H_U24(pbPacket + 6);
4238 enmTxDir = AHCITXDIR_READ;
4239 goto sendcmd;
4240 case SCSI_READ_BUFFER_CAPACITY:
4241 cbTransfer = ataBE2H_U16(pbPacket + 7);
4242 enmTxDir = AHCITXDIR_READ;
4243 goto sendcmd;
4244 case SCSI_READ_CAPACITY:
4245 cbTransfer = 8;
4246 enmTxDir = AHCITXDIR_READ;
4247 goto sendcmd;
4248 case SCSI_READ_CD:
4249 {
4250 /* Get sector size based on the expected sector type field. */
4251 switch ((pbPacket[1] >> 2) & 0x7)
4252 {
4253 case 0x0: /* All types. */
4254 if (ASMAtomicReadU32(&pAhciPort->MediaTrackType) == ATA_MEDIA_TYPE_CDDA)
4255 pAhciPortTaskState->cbATAPISector = 2352;
4256 else
4257 pAhciPortTaskState->cbATAPISector = 2048; /* Might be incorrect if we couldn't determine the type. */
4258 break;
4259 case 0x1: /* CD-DA */
4260 pAhciPortTaskState->cbATAPISector = 2352;
4261 break;
4262 case 0x2: /* Mode 1 */
4263 pAhciPortTaskState->cbATAPISector = 2048;
4264 break;
4265 case 0x3: /* Mode 2 formless */
4266 pAhciPortTaskState->cbATAPISector = 2336;
4267 break;
4268 case 0x4: /* Mode 2 form 1 */
4269 pAhciPortTaskState->cbATAPISector = 2048;
4270 break;
4271 case 0x5: /* Mode 2 form 2 */
4272 pAhciPortTaskState->cbATAPISector = 2324;
4273 break;
4274 default: /* Reserved */
4275 AssertMsgFailed(("Unknown sector type\n"));
4276 pAhciPortTaskState->cbATAPISector = 0; /** @todo we should probably fail the command here already. */
4277 }
4278
4279 cbTransfer = ataBE2H_U24(pbPacket + 6) * pAhciPortTaskState->cbATAPISector;
4280 enmTxDir = AHCITXDIR_READ;
4281 goto sendcmd;
4282 }
4283 case SCSI_READ_CD_MSF:
4284 cSectors = ataMSF2LBA(pbPacket + 6) - ataMSF2LBA(pbPacket + 3);
4285 if (cSectors > 32)
4286 cSectors = 32; /* Limit transfer size to 64~74K. Safety first. In any case this can only harm software doing CDDA extraction. */
4287 pAhciPortTaskState->cbATAPISector = 2048; /**< @todo this size is not always correct */
4288 cbTransfer = cSectors * pAhciPortTaskState->cbATAPISector;
4289 enmTxDir = AHCITXDIR_READ;
4290 goto sendcmd;
4291 case SCSI_READ_DISC_INFORMATION:
4292 cbTransfer = ataBE2H_U16(pbPacket + 7);
4293 enmTxDir = AHCITXDIR_READ;
4294 goto sendcmd;
4295 case SCSI_READ_DVD_STRUCTURE:
4296 cbTransfer = ataBE2H_U16(pbPacket + 8);
4297 enmTxDir = AHCITXDIR_READ;
4298 goto sendcmd;
4299 case SCSI_READ_FORMAT_CAPACITIES:
4300 cbTransfer = ataBE2H_U16(pbPacket + 7);
4301 enmTxDir = AHCITXDIR_READ;
4302 goto sendcmd;
4303 case SCSI_READ_SUBCHANNEL:
4304 cbTransfer = ataBE2H_U16(pbPacket + 7);
4305 enmTxDir = AHCITXDIR_READ;
4306 goto sendcmd;
4307 case SCSI_READ_TOC_PMA_ATIP:
4308 cbTransfer = ataBE2H_U16(pbPacket + 7);
4309 enmTxDir = AHCITXDIR_READ;
4310 goto sendcmd;
4311 case SCSI_READ_TRACK_INFORMATION:
4312 cbTransfer = ataBE2H_U16(pbPacket + 7);
4313 enmTxDir = AHCITXDIR_READ;
4314 goto sendcmd;
4315 case SCSI_REPAIR_TRACK:
4316 goto sendcmd;
4317 case SCSI_REPORT_KEY:
4318 cbTransfer = ataBE2H_U16(pbPacket + 8);
4319 enmTxDir = AHCITXDIR_READ;
4320 goto sendcmd;
4321 case SCSI_REQUEST_SENSE:
4322 cbTransfer = pbPacket[4];
4323 if ((pAhciPort->abATAPISense[2] & 0x0f) != SCSI_SENSE_NONE)
4324 {
4325 pAhciPortTaskState->cbTransfer = cbTransfer;
4326 pAhciPortTaskState->enmTxDir = AHCITXDIR_READ;
4327 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_REQUEST_SENSE);
4328 break;
4329 }
4330 enmTxDir = AHCITXDIR_READ;
4331 goto sendcmd;
4332 case SCSI_RESERVE_TRACK:
4333 goto sendcmd;
4334 case SCSI_SCAN:
4335 goto sendcmd;
4336 case SCSI_SEEK_10:
4337 goto sendcmd;
4338 case SCSI_SEND_CUE_SHEET:
4339 cbTransfer = ataBE2H_U24(pbPacket + 6);
4340 enmTxDir = AHCITXDIR_WRITE;
4341 goto sendcmd;
4342 case SCSI_SEND_DVD_STRUCTURE:
4343 cbTransfer = ataBE2H_U16(pbPacket + 8);
4344 enmTxDir = AHCITXDIR_WRITE;
4345 goto sendcmd;
4346 case SCSI_SEND_EVENT:
4347 cbTransfer = ataBE2H_U16(pbPacket + 8);
4348 enmTxDir = AHCITXDIR_WRITE;
4349 goto sendcmd;
4350 case SCSI_SEND_KEY:
4351 cbTransfer = ataBE2H_U16(pbPacket + 8);
4352 enmTxDir = AHCITXDIR_WRITE;
4353 goto sendcmd;
4354 case SCSI_SEND_OPC_INFORMATION:
4355 cbTransfer = ataBE2H_U16(pbPacket + 7);
4356 enmTxDir = AHCITXDIR_WRITE;
4357 goto sendcmd;
4358 case SCSI_SET_CD_SPEED:
4359 goto sendcmd;
4360 case SCSI_SET_READ_AHEAD:
4361 goto sendcmd;
4362 case SCSI_SET_STREAMING:
4363 cbTransfer = ataBE2H_U16(pbPacket + 9);
4364 enmTxDir = AHCITXDIR_WRITE;
4365 goto sendcmd;
4366 case SCSI_START_STOP_UNIT:
4367 goto sendcmd;
4368 case SCSI_STOP_PLAY_SCAN:
4369 goto sendcmd;
4370 case SCSI_SYNCHRONIZE_CACHE:
4371 goto sendcmd;
4372 case SCSI_TEST_UNIT_READY:
4373 goto sendcmd;
4374 case SCSI_VERIFY_10:
4375 goto sendcmd;
4376 case SCSI_WRITE_10:
4377 iATAPILBA = ataBE2H_U32(pbPacket + 2);
4378 cSectors = ataBE2H_U16(pbPacket + 7);
4379 Log2(("ATAPI PT: lba %d sectors %d\n", iATAPILBA, cSectors));
4380 pAhciPortTaskState->cbATAPISector = 2048; /**< @todo this size is not always correct */
4381 cbTransfer = cSectors * pAhciPortTaskState->cbATAPISector;
4382 enmTxDir = AHCITXDIR_WRITE;
4383 goto sendcmd;
4384 case SCSI_WRITE_12:
4385 iATAPILBA = ataBE2H_U32(pbPacket + 2);
4386 cSectors = ataBE2H_U32(pbPacket + 6);
4387 Log2(("ATAPI PT: lba %d sectors %d\n", iATAPILBA, cSectors));
4388 pAhciPortTaskState->cbATAPISector = 2048; /**< @todo this size is not always correct */
4389 cbTransfer = cSectors * pAhciPortTaskState->cbATAPISector;
4390 enmTxDir = AHCITXDIR_WRITE;
4391 goto sendcmd;
4392 case SCSI_WRITE_AND_VERIFY_10:
4393 iATAPILBA = ataBE2H_U32(pbPacket + 2);
4394 cSectors = ataBE2H_U16(pbPacket + 7);
4395 Log2(("ATAPI PT: lba %d sectors %d\n", iATAPILBA, cSectors));
4396 /* The sector size is determined by the async I/O thread. */
4397 pAhciPortTaskState->cbATAPISector = 0;
4398 /* Preliminary, will be corrected once the sector size is known. */
4399 cbTransfer = cSectors;
4400 enmTxDir = AHCITXDIR_WRITE;
4401 goto sendcmd;
4402 case SCSI_WRITE_BUFFER:
4403 switch (pbPacket[1] & 0x1f)
4404 {
4405 case 0x04: /* download microcode */
4406 case 0x05: /* download microcode and save */
4407 case 0x06: /* download microcode with offsets */
4408 case 0x07: /* download microcode with offsets and save */
4409 case 0x0e: /* download microcode with offsets and defer activation */
4410 case 0x0f: /* activate deferred microcode */
4411 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM passthrough command attempted to update firmware, blocked\n", pAhciPort->iLUN));
4412 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
4413 break;
4414 default:
4415 cbTransfer = ataBE2H_U16(pbPacket + 6);
4416 enmTxDir = AHCITXDIR_WRITE;
4417 goto sendcmd;
4418 }
4419 break;
4420 case SCSI_REPORT_LUNS: /* Not part of MMC-3, but used by Windows. */
4421 cbTransfer = ataBE2H_U32(pbPacket + 6);
4422 enmTxDir = AHCITXDIR_READ;
4423 goto sendcmd;
4424 case SCSI_REZERO_UNIT:
4425 /* Obsolete command used by cdrecord. What else would one expect?
4426 * This command is not sent to the drive, it is handled internally,
4427 * as the Linux kernel doesn't like it (message "scsi: unknown
4428 * opcode 0x01" in syslog) and replies with a sense code of 0,
4429 * which sends cdrecord to an endless loop. */
4430 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE);
4431 break;
4432 default:
4433 LogRel(("AHCI: LUN#%d: passthrough unimplemented for command %#x\n", pAhciPort->iLUN, pbPacket[0]));
4434 atapiCmdErrorSimple(pAhciPort, pAhciPortTaskState, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE);
4435 break;
4436 sendcmd:
4437 /* Send a command to the drive, passing data in/out as required. */
4438 Log2(("ATAPI PT: max size %d\n", cbTransfer));
4439 if (cbTransfer == 0)
4440 enmTxDir = AHCITXDIR_NONE;
4441 pAhciPortTaskState->enmTxDir = enmTxDir;
4442 pAhciPortTaskState->cbTransfer = cbTransfer;
4443 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_PASSTHROUGH);
4444 }
4445
4446 return AHCITXDIR_NONE;
4447}
4448
4449static AHCITXDIR atapiParseCmd(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState)
4450{
4451 AHCITXDIR enmTxDir = AHCITXDIR_NONE;
4452 const uint8_t *pbPacket;
4453
4454 pbPacket = pAhciPortTaskState->aATAPICmd;
4455#ifdef DEBUG
4456 Log(("%s: LUN#%d CMD=%#04x \"%s\"\n", __FUNCTION__, pAhciPort->iLUN, pbPacket[0], SCSICmdText(pbPacket[0])));
4457#else /* !DEBUG */
4458 Log(("%s: LUN#%d CMD=%#04x\n", __FUNCTION__, pAhciPort->iLUN, pbPacket[0]));
4459#endif /* !DEBUG */
4460 Log2(("%s: limit=%#x packet: %.*Rhxs\n", __FUNCTION__, pAhciPortTaskState->cmdFis[AHCI_CMDFIS_CYLL] | (pAhciPortTaskState->cmdFis[AHCI_CMDFIS_CYLH] << 8), ATAPI_PACKET_SIZE, pbPacket));
4461
4462 if (pAhciPort->fATAPIPassthrough)
4463 enmTxDir = atapiParseCmdPassthrough(pAhciPort, pAhciPortTaskState);
4464 else
4465 enmTxDir = atapiParseCmdVirtualATAPI(pAhciPort, pAhciPortTaskState);
4466
4467 return enmTxDir;
4468}
4469
4470/**
4471 * Reset all values after a reset of the attached storage device.
4472 *
4473 * @returns nothing
4474 * @param pAhciPort The port the device is attached to.
4475 * @param pAhciPortTaskState The state to get the tag number from.
4476 */
4477static void ahciFinishStorageDeviceReset(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState)
4478{
4479 int rc;
4480
4481 /* Send a status good D2H FIS. */
4482 ASMAtomicWriteU32(&pAhciPort->MediaEventStatus, ATA_EVENT_STATUS_UNCHANGED);
4483 pAhciPort->fResetDevice = false;
4484 if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
4485 ahciPostFirstD2HFisIntoMemory(pAhciPort);
4486
4487 /* As this is the first D2H FIS after the reset update the signature in the SIG register of the port. */
4488 if (pAhciPort->fATAPI)
4489 pAhciPort->regSIG = AHCI_PORT_SIG_ATAPI;
4490 else
4491 pAhciPort->regSIG = AHCI_PORT_SIG_DISK;
4492 ASMAtomicOrU32(&pAhciPort->u32TasksFinished, (1 << pAhciPortTaskState->uTag));
4493
4494 rc = ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN, VERR_IGNORED);
4495 AssertRC(rc);
4496}
4497
4498/**
4499 * Initiates a device reset caused by ATA_DEVICE_RESET (ATAPI only).
4500 *
4501 * @returns nothing.
4502 * @param pAhciPort The device to reset.
4503 * @param pAhciPortTaskState The task state.
4504 */
4505static void ahciDeviceReset(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState)
4506{
4507 ASMAtomicWriteBool(&pAhciPort->fResetDevice, true);
4508
4509 /*
4510 * Because this ATAPI only and ATAPI can't have
4511 * more than one command active at a time the task counter should be 0
4512 * and it is possible to finish the reset now.
4513 */
4514 Assert(ASMAtomicReadU32(&pAhciPort->cTasksActive) == 0);
4515 ahciFinishStorageDeviceReset(pAhciPort, pAhciPortTaskState);
4516}
4517
4518/**
4519 * Build a D2H FIS and post into the memory area of the guest.
4520 *
4521 * @returns Nothing
4522 * @param pAhciPort The port of the SATA controller.
4523 * @param pAhciPortTaskState The state of the task.
4524 * @param pCmdFis Pointer to the command FIS from the guest.
4525 * @param fInterrupt If an interrupt should be send to the guest.
4526 */
4527static void ahciSendD2HFis(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState, uint8_t *pCmdFis, bool fInterrupt)
4528{
4529 uint8_t d2hFis[20];
4530 bool fAssertIntr = false;
4531 PAHCI pAhci = pAhciPort->CTX_SUFF(pAhci);
4532
4533 ahciLog(("%s: building D2H Fis\n", __FUNCTION__));
4534
4535 if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
4536 {
4537 memset(&d2hFis[0], 0, sizeof(d2hFis));
4538 d2hFis[AHCI_CMDFIS_TYPE] = AHCI_CMDFIS_TYPE_D2H;
4539 d2hFis[AHCI_CMDFIS_BITS] = (fInterrupt ? AHCI_CMDFIS_I : 0);
4540 d2hFis[AHCI_CMDFIS_STS] = pAhciPortTaskState->uATARegStatus;
4541 d2hFis[AHCI_CMDFIS_ERR] = pAhciPortTaskState->uATARegError;
4542 d2hFis[AHCI_CMDFIS_SECTN] = pCmdFis[AHCI_CMDFIS_SECTN];
4543 d2hFis[AHCI_CMDFIS_CYLL] = pCmdFis[AHCI_CMDFIS_CYLL];
4544 d2hFis[AHCI_CMDFIS_CYLH] = pCmdFis[AHCI_CMDFIS_CYLH];
4545 d2hFis[AHCI_CMDFIS_HEAD] = pCmdFis[AHCI_CMDFIS_HEAD];
4546 d2hFis[AHCI_CMDFIS_SECTNEXP] = pCmdFis[AHCI_CMDFIS_SECTNEXP];
4547 d2hFis[AHCI_CMDFIS_CYLLEXP] = pCmdFis[AHCI_CMDFIS_CYLLEXP];
4548 d2hFis[AHCI_CMDFIS_CYLHEXP] = pCmdFis[AHCI_CMDFIS_CYLHEXP];
4549 d2hFis[AHCI_CMDFIS_SECTC] = pCmdFis[AHCI_CMDFIS_SECTC];
4550 d2hFis[AHCI_CMDFIS_SECTCEXP] = pCmdFis[AHCI_CMDFIS_SECTCEXP];
4551
4552 /* Update registers. */
4553 pAhciPort->regTFD = (pAhciPortTaskState->uATARegError << 8) | pAhciPortTaskState->uATARegStatus;
4554
4555 ahciPostFisIntoMemory(pAhciPort, AHCI_CMDFIS_TYPE_D2H, d2hFis);
4556
4557 if (pAhciPortTaskState->uATARegStatus & ATA_STAT_ERR)
4558 {
4559 /* Error bit is set. */
4560 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_TFES);
4561 if (pAhciPort->regIE & AHCI_PORT_IE_TFEE)
4562 fAssertIntr = true;
4563 }
4564
4565 if (fInterrupt)
4566 {
4567 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_DHRS);
4568 /* Check if we should assert an interrupt */
4569 if (pAhciPort->regIE & AHCI_PORT_IE_DHRE)
4570 fAssertIntr = true;
4571 }
4572
4573 ASMAtomicOrU32(&pAhciPort->u32TasksFinished, (1 << pAhciPortTaskState->uTag));
4574
4575 if (fAssertIntr)
4576 {
4577 int rc = ahciHbaSetInterrupt(pAhci, pAhciPort->iLUN, VERR_IGNORED);
4578 AssertRC(rc);
4579 }
4580 }
4581}
4582
4583/**
4584 * Build a SDB Fis and post it into the memory area of the guest.
4585 *
4586 * @returns Nothing
4587 * @param pAhciPort The port for which the SDB Fis is send.
4588 * @param uFinishedTasks Bitmask of finished tasks.
4589 * @param fInterrupt If an interrupt should be asserted.
4590 */
4591static void ahciSendSDBFis(PAHCIPort pAhciPort, uint32_t uFinishedTasks, bool fInterrupt)
4592{
4593 uint32_t sdbFis[2];
4594 bool fAssertIntr = false;
4595 PAHCI pAhci = pAhciPort->CTX_SUFF(pAhci);
4596 PAHCIPORTTASKSTATE pTaskErr = ASMAtomicReadPtrT(&pAhciPort->pTaskErr, PAHCIPORTTASKSTATE);
4597
4598 ahciLog(("%s: Building SDB FIS\n", __FUNCTION__));
4599
4600 if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
4601 {
4602 memset(&sdbFis[0], 0, sizeof(sdbFis));
4603 sdbFis[0] = AHCI_CMDFIS_TYPE_SETDEVBITS;
4604 sdbFis[0] |= (fInterrupt ? (1 << 14) : 0);
4605 if (RT_UNLIKELY(pTaskErr))
4606 {
4607 sdbFis[0] = pTaskErr->uATARegError;
4608 sdbFis[0] |= (pTaskErr->uATARegStatus & 0x77) << 16; /* Some bits are marked as reserved and thus are masked out. */
4609
4610 /* Update registers. */
4611 pAhciPort->regTFD = (pTaskErr->uATARegError << 8) | pTaskErr->uATARegStatus;
4612 }
4613 else
4614 {
4615 sdbFis[0] = 0;
4616 sdbFis[0] |= (ATA_STAT_READY | ATA_STAT_SEEK) << 16;
4617 pAhciPort->regTFD = ATA_STAT_READY | ATA_STAT_SEEK;
4618 }
4619
4620 sdbFis[1] = pAhciPort->u32QueuedTasksFinished | uFinishedTasks;
4621
4622 ahciPostFisIntoMemory(pAhciPort, AHCI_CMDFIS_TYPE_SETDEVBITS, (uint8_t *)sdbFis);
4623
4624 if (RT_UNLIKELY(pTaskErr))
4625 {
4626 /* Error bit is set. */
4627 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_TFES);
4628 if (pAhciPort->regIE & AHCI_PORT_IE_TFEE)
4629 fAssertIntr = true;
4630 }
4631
4632 if (fInterrupt)
4633 {
4634 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_SDBS);
4635 /* Check if we should assert an interrupt */
4636 if (pAhciPort->regIE & AHCI_PORT_IE_SDBE)
4637 fAssertIntr = true;
4638 }
4639
4640 ASMAtomicOrU32(&pAhciPort->u32QueuedTasksFinished, uFinishedTasks);
4641
4642 if (fAssertIntr)
4643 {
4644 int rc = ahciHbaSetInterrupt(pAhci, pAhciPort->iLUN, VERR_IGNORED);
4645 AssertRC(rc);
4646 }
4647 }
4648}
4649
4650static uint32_t ahciGetNSectors(uint8_t *pCmdFis, bool fLBA48)
4651{
4652 /* 0 means either 256 (LBA28) or 65536 (LBA48) sectors. */
4653 if (fLBA48)
4654 {
4655 if (!pCmdFis[AHCI_CMDFIS_SECTC] && !pCmdFis[AHCI_CMDFIS_SECTCEXP])
4656 return 65536;
4657 else
4658 return pCmdFis[AHCI_CMDFIS_SECTCEXP] << 8 | pCmdFis[AHCI_CMDFIS_SECTC];
4659 }
4660 else
4661 {
4662 if (!pCmdFis[AHCI_CMDFIS_SECTC])
4663 return 256;
4664 else
4665 return pCmdFis[AHCI_CMDFIS_SECTC];
4666 }
4667}
4668
4669static uint64_t ahciGetSector(PAHCIPort pAhciPort, uint8_t *pCmdFis, bool fLBA48)
4670{
4671 uint64_t iLBA;
4672 if (pCmdFis[AHCI_CMDFIS_HEAD] & 0x40)
4673 {
4674 /* any LBA variant */
4675 if (fLBA48)
4676 {
4677 /* LBA48 */
4678 iLBA = ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLHEXP] << 40) |
4679 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLLEXP] << 32) |
4680 ((uint64_t)pCmdFis[AHCI_CMDFIS_SECTNEXP] << 24) |
4681 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLH] << 16) |
4682 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLL] << 8) |
4683 pCmdFis[AHCI_CMDFIS_SECTN];
4684 }
4685 else
4686 {
4687 /* LBA */
4688 iLBA = ((pCmdFis[AHCI_CMDFIS_HEAD] & 0x0f) << 24) | (pCmdFis[AHCI_CMDFIS_CYLH] << 16) |
4689 (pCmdFis[AHCI_CMDFIS_CYLL] << 8) | pCmdFis[AHCI_CMDFIS_SECTN];
4690 }
4691 }
4692 else
4693 {
4694 /* CHS */
4695 iLBA = ((pCmdFis[AHCI_CMDFIS_CYLH] << 8) | pCmdFis[AHCI_CMDFIS_CYLL]) * pAhciPort->PCHSGeometry.cHeads * pAhciPort->PCHSGeometry.cSectors +
4696 (pCmdFis[AHCI_CMDFIS_HEAD] & 0x0f) * pAhciPort->PCHSGeometry.cSectors +
4697 (pCmdFis[AHCI_CMDFIS_SECTN] - 1);
4698 }
4699 return iLBA;
4700}
4701
4702static uint64_t ahciGetSectorQueued(uint8_t *pCmdFis)
4703{
4704 uint64_t uLBA;
4705
4706 uLBA = ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLHEXP] << 40) |
4707 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLLEXP] << 32) |
4708 ((uint64_t)pCmdFis[AHCI_CMDFIS_SECTNEXP] << 24) |
4709 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLH] << 16) |
4710 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLL] << 8) |
4711 pCmdFis[AHCI_CMDFIS_SECTN];
4712
4713 return uLBA;
4714}
4715
4716DECLINLINE(uint32_t) ahciGetNSectorsQueued(uint8_t *pCmdFis)
4717{
4718 if (!pCmdFis[AHCI_CMDFIS_FETEXP] && !pCmdFis[AHCI_CMDFIS_FET])
4719 return 65536;
4720 else
4721 return pCmdFis[AHCI_CMDFIS_FETEXP] << 8 | pCmdFis[AHCI_CMDFIS_FET];
4722}
4723
4724DECLINLINE(uint8_t) ahciGetTagQueued(uint8_t *pCmdFis)
4725{
4726 return pCmdFis[AHCI_CMDFIS_SECTC] >> 3;
4727}
4728
4729static void ahciScatterGatherListGetTotalBufferSize(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState)
4730{
4731 CmdHdr *pCmdHdr = &pAhciPortTaskState->cmdHdr;
4732 PPDMDEVINS pDevIns = pAhciPort->CTX_SUFF(pDevIns);
4733 unsigned cActualSGEntry;
4734 SGLEntry aSGLEntry[32]; /* Holds read sg entries from guest. Biggest seen number of entries a guest set up. */
4735 unsigned cSGLEntriesGCRead;
4736 unsigned cSGLEntriesGCLeft; /* Available scatter gather list entries in GC */
4737 RTGCPHYS GCPhysAddrPRDTLEntryStart; /* Start address to read the entries from. */
4738 uint32_t cbSGBuffers = 0; /* Total number of bytes reserved for this request. */
4739
4740 /* Retrieve the total number of bytes reserved for this request. */
4741 cSGLEntriesGCLeft = AHCI_CMDHDR_PRDTL_ENTRIES(pCmdHdr->u32DescInf);
4742 ahciLog(("%s: cSGEntriesGC=%u\n", __FUNCTION__, cSGLEntriesGCLeft));
4743
4744 if (cSGLEntriesGCLeft)
4745 {
4746 /* Set start address of the entries. */
4747 GCPhysAddrPRDTLEntryStart = AHCI_RTGCPHYS_FROM_U32(pCmdHdr->u32CmdTblAddrUp, pCmdHdr->u32CmdTblAddr) + AHCI_CMDHDR_PRDT_OFFSET;
4748
4749 do
4750 {
4751 cSGLEntriesGCRead = (cSGLEntriesGCLeft < RT_ELEMENTS(aSGLEntry)) ? cSGLEntriesGCLeft : RT_ELEMENTS(aSGLEntry);
4752 cSGLEntriesGCLeft -= cSGLEntriesGCRead;
4753
4754 /* Read the SG entries. */
4755 PDMDevHlpPhysRead(pDevIns, GCPhysAddrPRDTLEntryStart, &aSGLEntry[0], cSGLEntriesGCRead * sizeof(SGLEntry));
4756
4757 for (cActualSGEntry = 0; cActualSGEntry < cSGLEntriesGCRead; cActualSGEntry++)
4758 cbSGBuffers += (aSGLEntry[cActualSGEntry].u32DescInf & SGLENTRY_DESCINF_DBC) + 1;
4759
4760 /* Set address to the next entries to read. */
4761 GCPhysAddrPRDTLEntryStart += cSGLEntriesGCRead * sizeof(SGLEntry);
4762 } while (cSGLEntriesGCLeft);
4763 }
4764
4765 pAhciPortTaskState->cbSGBuffers = cbSGBuffers;
4766}
4767
4768static int ahciScatterGatherListAllocate(PAHCIPORTTASKSTATE pAhciPortTaskState, uint32_t cSGList, uint32_t cbUnaligned)
4769{
4770 if (pAhciPortTaskState->cSGListSize < cSGList)
4771 {
4772 /* The entries are not allocated yet or the number is too small. */
4773 if (pAhciPortTaskState->cSGListSize)
4774 {
4775 RTMemFree(pAhciPortTaskState->pSGListHead);
4776 RTMemFree(pAhciPortTaskState->paSGEntries);
4777 }
4778
4779 /* Allocate R3 scatter gather list. */
4780 pAhciPortTaskState->pSGListHead = (PRTSGSEG)RTMemAllocZ(cSGList * sizeof(RTSGSEG));
4781 if (!pAhciPortTaskState->pSGListHead)
4782 return VERR_NO_MEMORY;
4783
4784 pAhciPortTaskState->paSGEntries = (PAHCIPORTTASKSTATESGENTRY)RTMemAllocZ(cSGList * sizeof(AHCIPORTTASKSTATESGENTRY));
4785 if (!pAhciPortTaskState->paSGEntries)
4786 return VERR_NO_MEMORY;
4787
4788 /* Reset usage statistics. */
4789 pAhciPortTaskState->cSGListSize = cSGList;
4790 pAhciPortTaskState->cSGListTooBig = 0;
4791 }
4792 else if (pAhciPortTaskState->cSGListSize > cSGList)
4793 {
4794 /*
4795 * The list is too big. Increment counter.
4796 * So that the destroying function can free
4797 * the list if it is too big too many times
4798 * in a row.
4799 */
4800 pAhciPortTaskState->cSGListTooBig++;
4801 }
4802 else
4803 {
4804 /*
4805 * Needed entries matches current size.
4806 * Reset counter.
4807 */
4808 pAhciPortTaskState->cSGListTooBig = 0;
4809 }
4810
4811 pAhciPortTaskState->cSGEntries = cSGList;
4812
4813 if (pAhciPortTaskState->cbBufferUnaligned < cbUnaligned)
4814 {
4815 if (pAhciPortTaskState->pvBufferUnaligned)
4816 RTMemPageFree(pAhciPortTaskState->pvBufferUnaligned, pAhciPortTaskState->cbBufferUnaligned);
4817
4818 Log(("%s: Allocating buffer for unaligned segments cbUnaligned=%u\n", __FUNCTION__, cbUnaligned));
4819
4820 pAhciPortTaskState->pvBufferUnaligned = RTMemPageAlloc(cbUnaligned);
4821 if (!pAhciPortTaskState->pvBufferUnaligned)
4822 return VERR_NO_MEMORY;
4823
4824 pAhciPortTaskState->cbBufferUnaligned = cbUnaligned;
4825 }
4826
4827 /* Make debugging easier. */
4828#ifdef DEBUG
4829 memset(pAhciPortTaskState->pSGListHead, 0, pAhciPortTaskState->cSGListSize * sizeof(RTSGSEG));
4830 memset(pAhciPortTaskState->paSGEntries, 0, pAhciPortTaskState->cSGListSize * sizeof(AHCIPORTTASKSTATESGENTRY));
4831 if (pAhciPortTaskState->pvBufferUnaligned)
4832 memset(pAhciPortTaskState->pvBufferUnaligned, 0, pAhciPortTaskState->cbBufferUnaligned);
4833#endif
4834
4835 return VINF_SUCCESS;
4836}
4837
4838/**
4839 * Fallback scatter gather list creator.
4840 * Used if the normal one fails in PDMDevHlpPhysGCPhys2CCPtr() or
4841 * PDMDevHlpPhysGCPhys2CCPtrReadonly() or post processing
4842 * is used.
4843 *
4844 * returns VBox status code.
4845 * @param pAhciPort The ahci port.
4846 * @param pAhciPortTaskState The task state which contains the S/G list entries.
4847 * @param fReadonly If the mappings should be readonly.
4848 * @param cSGEntriesProcessed Number of entries the normal creator processed
4849 * before an error occurred. Used to free
4850 * any resources allocated before.
4851 * @thread EMT
4852 */
4853static int ahciScatterGatherListCreateSafe(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState,
4854 bool fReadonly, unsigned cSGEntriesProcessed)
4855{
4856 CmdHdr *pCmdHdr = &pAhciPortTaskState->cmdHdr;
4857 PPDMDEVINS pDevIns = pAhciPort->CTX_SUFF(pDevIns);
4858 PAHCIPORTTASKSTATESGENTRY pSGInfoCurr = pAhciPortTaskState->paSGEntries;
4859
4860 Assert(VALID_PTR(pAhciPortTaskState->pSGListHead) || !cSGEntriesProcessed);
4861 Assert(VALID_PTR(pAhciPortTaskState->paSGEntries) || !cSGEntriesProcessed);
4862
4863 for (unsigned cSGEntryCurr = 0; cSGEntryCurr < cSGEntriesProcessed; cSGEntryCurr++)
4864 {
4865 if (pSGInfoCurr->fGuestMemory)
4866 {
4867 /* Release the lock. */
4868 PDMDevHlpPhysReleasePageMappingLock(pDevIns, &pSGInfoCurr->u.direct.PageLock);
4869 }
4870
4871 /* Go to the next entry. */
4872 pSGInfoCurr++;
4873 }
4874
4875 if (pAhciPortTaskState->pvBufferUnaligned)
4876 {
4877 RTMemPageFree(pAhciPortTaskState->pvBufferUnaligned, pAhciPortTaskState->cbBufferUnaligned);
4878 pAhciPortTaskState->pvBufferUnaligned = NULL;
4879 }
4880 if (pAhciPortTaskState->pSGListHead)
4881 {
4882 RTMemFree(pAhciPortTaskState->pSGListHead);
4883 pAhciPortTaskState->pSGListHead = NULL;
4884 }
4885 if (pAhciPortTaskState->paSGEntries)
4886 {
4887 RTMemFree(pAhciPortTaskState->paSGEntries);
4888 pAhciPortTaskState->paSGEntries = NULL;
4889 }
4890 pAhciPortTaskState->cSGListTooBig = 0;
4891 pAhciPortTaskState->cSGEntries = 1;
4892 pAhciPortTaskState->cSGListUsed = 1;
4893 pAhciPortTaskState->cSGListSize = 1;
4894 pAhciPortTaskState->cbBufferUnaligned = pAhciPortTaskState->cbSGBuffers;
4895
4896 /* Allocate new buffers and SG lists. */
4897 pAhciPortTaskState->pvBufferUnaligned = RTMemPageAlloc(pAhciPortTaskState->cbSGBuffers);
4898 if (!pAhciPortTaskState->pvBufferUnaligned)
4899 return VERR_NO_MEMORY;
4900
4901 pAhciPortTaskState->pSGListHead = (PRTSGSEG)RTMemAllocZ(1 * sizeof(RTSGSEG));
4902 if (!pAhciPortTaskState->pSGListHead)
4903 {
4904 RTMemPageFree(pAhciPortTaskState->pvBufferUnaligned, pAhciPortTaskState->cbBufferUnaligned);
4905 return VERR_NO_MEMORY;
4906 }
4907
4908 pAhciPortTaskState->paSGEntries = (PAHCIPORTTASKSTATESGENTRY)RTMemAllocZ(1 * sizeof(AHCIPORTTASKSTATESGENTRY));
4909 if (!pAhciPortTaskState->paSGEntries)
4910 {
4911 RTMemPageFree(pAhciPortTaskState->pvBufferUnaligned, pAhciPortTaskState->cbBufferUnaligned);
4912 RTMemFree(pAhciPortTaskState->pSGListHead);
4913 return VERR_NO_MEMORY;
4914 }
4915
4916 /* Set pointers. */
4917 if (pAhciPortTaskState->cbTransfer)
4918 {
4919 pAhciPortTaskState->pSGListHead[0].cbSeg = pAhciPortTaskState->cbTransfer;
4920
4921 /* Allocate a separate buffer if we have to do post processing . */
4922 if (pAhciPortTaskState->pfnPostProcess)
4923 {
4924 pAhciPortTaskState->pSGListHead[0].pvSeg = RTMemAlloc(pAhciPortTaskState->cbTransfer);
4925 if (!pAhciPortTaskState->pSGListHead[0].pvSeg)
4926 {
4927 RTMemFree(pAhciPortTaskState->paSGEntries);
4928 RTMemPageFree(pAhciPortTaskState->pvBufferUnaligned, pAhciPortTaskState->cbBufferUnaligned);
4929 RTMemFree(pAhciPortTaskState->pSGListHead);
4930 return VERR_NO_MEMORY;
4931 }
4932 }
4933 else
4934 pAhciPortTaskState->pSGListHead[0].pvSeg = pAhciPortTaskState->pvBufferUnaligned;
4935 }
4936 else
4937 {
4938 pAhciPortTaskState->pSGListHead[0].cbSeg = pAhciPortTaskState->cbBufferUnaligned;
4939 pAhciPortTaskState->pSGListHead[0].pvSeg = pAhciPortTaskState->pvBufferUnaligned;
4940 }
4941
4942 pAhciPortTaskState->paSGEntries[0].fGuestMemory = false;
4943 pAhciPortTaskState->paSGEntries[0].u.temp.cUnaligned = AHCI_CMDHDR_PRDTL_ENTRIES(pCmdHdr->u32DescInf);
4944 pAhciPortTaskState->paSGEntries[0].u.temp.GCPhysAddrBaseFirstUnaligned = AHCI_RTGCPHYS_FROM_U32(pCmdHdr->u32CmdTblAddrUp, pCmdHdr->u32CmdTblAddr) + AHCI_CMDHDR_PRDT_OFFSET;
4945 pAhciPortTaskState->paSGEntries[0].u.temp.pvBuf = pAhciPortTaskState->pvBufferUnaligned;
4946
4947 if (pAhciPortTaskState->enmTxDir == AHCITXDIR_WRITE)
4948 ahciCopyFromSGListIntoBuffer(pDevIns, &pAhciPortTaskState->paSGEntries[0]);
4949
4950 return VINF_SUCCESS;
4951}
4952
4953/**
4954 * Create scatter gather list descriptors.
4955 *
4956 * @returns VBox status code.
4957 * @param pAhciPort The ahci port.
4958 * @param pAhciPortTaskState The task state which contains the S/G list entries.
4959 * @param fReadonly If the mappings should be readonly.
4960 * @thread EMT
4961 */
4962static int ahciScatterGatherListCreate(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState, bool fReadonly)
4963{
4964 int rc = VINF_SUCCESS;
4965 CmdHdr *pCmdHdr = &pAhciPortTaskState->cmdHdr;
4966 PPDMDEVINS pDevIns = pAhciPort->CTX_SUFF(pDevIns);
4967 unsigned cActualSGEntry;
4968 unsigned cSGEntriesR3 = 0; /* Needed scatter gather list entries in R3. */
4969 unsigned cSGEntriesProcessed = 0; /* Number of SG entries processed. */
4970 SGLEntry aSGLEntry[32]; /* Holds read sg entries from guest. Biggest seen number of entries a guest set up. */
4971 unsigned cSGLEntriesGCRead;
4972 unsigned cSGLEntriesGCLeft; /* Available scatter gather list entries in GC */
4973 RTGCPHYS GCPhysAddrPRDTLEntryStart; /* Start address to read the entries from. */
4974 uint32_t cbSegment; /* Size of the current segments in bytes. */
4975 bool fUnaligned; /* Flag whether the current buffer is unaligned. */
4976 uint32_t cbUnaligned; /* Size of the unaligned buffers. */
4977 uint32_t cUnaligned;
4978 bool fDoMapping = false;
4979 uint32_t cbSGBuffers = 0; /* Total number of bytes reserved for this request. */
4980 RTGCPHYS GCPhysAddrPRDTLUnalignedStart = NIL_RTGCPHYS;
4981 PAHCIPORTTASKSTATESGENTRY pSGInfoCurr = NULL;
4982 PAHCIPORTTASKSTATESGENTRY pSGInfoPrev = NULL;
4983 PRTSGSEG pSGEntryCurr = NULL;
4984 PRTSGSEG pSGEntryPrev = NULL;
4985 RTGCPHYS GCPhysBufferPageAlignedPrev = NIL_RTGCPHYS;
4986 uint8_t *pu8BufferUnalignedPos = NULL;
4987 uint32_t cbUnalignedComplete = 0;
4988
4989 STAM_PROFILE_START(&pAhciPort->StatProfileMapIntoR3, a);
4990
4991 pAhciPortTaskState->cbSGBuffers = 0;
4992
4993 /*
4994 * Create a safe mapping when doing post processing because the size of the
4995 * data to transfer and the amount of guest memory reserved can differ.
4996 *
4997 * @fixme: Read performance is really bad on OS X hosts because there is no
4998 * S/G support and the I/O manager has to create a newrequest
4999 * for every segment. The default limit of active requests is 16 on OS X
5000 * which causes a the bad read performance (writes are not affected
5001 * because of the writeback cache).
5002 * For now we will always use an intermediate buffer until
5003 * there is support for host S/G operations.
5004 */
5005 if (pAhciPortTaskState->pfnPostProcess || true)
5006 {
5007 ahciLog(("%s: Request with post processing.\n", __FUNCTION__));
5008
5009 ahciScatterGatherListGetTotalBufferSize(pAhciPort, pAhciPortTaskState);
5010
5011 return ahciScatterGatherListCreateSafe(pAhciPort, pAhciPortTaskState, fReadonly, 0);
5012 }
5013
5014 /*
5015 * We need to calculate the number of SG list entries in R3 first because the data buffers in the guest don't need to be
5016 * page aligned. Hence the number of SG list entries in the guest can differ from the ones we need
5017 * because PDMDevHlpPhysGCPhys2CCPtr works only on a page base.
5018 * In the first pass we calculate the number of segments in R3 and in the second pass we map the guest segments into R3.
5019 */
5020 for (int i = 0; i < 2; i++)
5021 {
5022 cSGLEntriesGCLeft = AHCI_CMDHDR_PRDTL_ENTRIES(pCmdHdr->u32DescInf);
5023 ahciLog(("%s: cSGEntriesGC=%u\n", __FUNCTION__, cSGLEntriesGCLeft));
5024
5025 /* Set start address of the entries. */
5026 GCPhysAddrPRDTLEntryStart = AHCI_RTGCPHYS_FROM_U32(pCmdHdr->u32CmdTblAddrUp, pCmdHdr->u32CmdTblAddr) + AHCI_CMDHDR_PRDT_OFFSET;
5027 fUnaligned = false;
5028 cbUnaligned = 0;
5029 cUnaligned = 0;
5030 GCPhysBufferPageAlignedPrev = NIL_RTGCPHYS;
5031
5032 if (fDoMapping)
5033 {
5034 ahciLog(("%s: cSGEntriesR3=%u\n", __FUNCTION__, cSGEntriesR3));
5035 /* The number of needed SG entries in R3 is known. Allocate needed memory. */
5036 rc = ahciScatterGatherListAllocate(pAhciPortTaskState, cSGEntriesR3, cbUnalignedComplete);
5037 AssertMsgRC(rc, ("Failed to allocate scatter gather array rc=%Rrc\n", rc));
5038
5039 /* We are now able to map the pages into R3. */
5040 pSGInfoCurr = pAhciPortTaskState->paSGEntries;
5041 pSGEntryCurr = pAhciPortTaskState->pSGListHead;
5042 pSGEntryPrev = pSGEntryCurr;
5043 pSGInfoPrev = pSGInfoCurr;
5044 /* Initialize first segment to remove the need for additional if checks later in the code. */
5045 pSGEntryCurr->pvSeg = NULL;
5046 pSGEntryCurr->cbSeg = 0;
5047 pSGInfoCurr->fGuestMemory= false;
5048 pu8BufferUnalignedPos = (uint8_t *)pAhciPortTaskState->pvBufferUnaligned;
5049 pAhciPortTaskState->cSGListUsed = 0;
5050 pAhciPortTaskState->cbSGBuffers = cbSGBuffers;
5051 }
5052
5053 do
5054 {
5055 cSGLEntriesGCRead = (cSGLEntriesGCLeft < RT_ELEMENTS(aSGLEntry)) ? cSGLEntriesGCLeft : RT_ELEMENTS(aSGLEntry);
5056 cSGLEntriesGCLeft -= cSGLEntriesGCRead;
5057
5058 /* Read the SG entries. */
5059 PDMDevHlpPhysRead(pDevIns, GCPhysAddrPRDTLEntryStart, &aSGLEntry[0], cSGLEntriesGCRead * sizeof(SGLEntry));
5060
5061 for (cActualSGEntry = 0; cActualSGEntry < cSGLEntriesGCRead; cActualSGEntry++)
5062 {
5063 RTGCPHYS GCPhysAddrDataBase;
5064 uint32_t cbDataToTransfer;
5065
5066 ahciLog(("%s: cActualSGEntry=%u cSGEntriesR3=%u\n", __FUNCTION__, cActualSGEntry, cSGEntriesR3));
5067
5068 cbDataToTransfer = (aSGLEntry[cActualSGEntry].u32DescInf & SGLENTRY_DESCINF_DBC) + 1;
5069 ahciLog(("%s: cbDataToTransfer=%u\n", __FUNCTION__, cbDataToTransfer));
5070 cbSGBuffers += cbDataToTransfer;
5071
5072 /* Check if the buffer is sector aligned. */
5073 if (cbDataToTransfer % 512 != 0)
5074 {
5075 if (!fUnaligned)
5076 {
5077 /* We are not in an unaligned buffer but this is the first unaligned one. */
5078 fUnaligned = true;
5079 cbUnaligned = cbDataToTransfer;
5080 GCPhysAddrPRDTLUnalignedStart = GCPhysAddrPRDTLEntryStart + cActualSGEntry * sizeof(SGLEntry);
5081 cSGEntriesR3++;
5082 cUnaligned = 1;
5083 ahciLog(("%s: Unaligned buffer found cb=%d\n", __FUNCTION__, cbDataToTransfer));
5084 }
5085 else
5086 {
5087 /* We are already in an unaligned buffer and this one is unaligned too. */
5088 cbUnaligned += cbDataToTransfer;
5089 cUnaligned++;
5090 }
5091
5092 cbUnalignedComplete += cbDataToTransfer;
5093 }
5094 else /* Guest segment size is sector aligned. */
5095 {
5096 if (fUnaligned)
5097 {
5098 if (cbUnaligned % 512 == 0)
5099 {
5100 /*
5101 * The last buffer started at an offset
5102 * not aligned to a sector boundary but this buffer
5103 * is sector aligned. Check if the current size of all
5104 * unaligned segments is a multiple of a sector.
5105 * If that's the case we can now map the segments again into R3.
5106 */
5107 fUnaligned = false;
5108
5109 if (fDoMapping)
5110 {
5111 /* Set up the entry. */
5112 pSGInfoCurr->fGuestMemory = false;
5113 pSGInfoCurr->u.temp.GCPhysAddrBaseFirstUnaligned = GCPhysAddrPRDTLUnalignedStart;
5114 pSGInfoCurr->u.temp.cUnaligned = cUnaligned;
5115 pSGInfoCurr->u.temp.pvBuf = pu8BufferUnalignedPos;
5116
5117 pSGEntryCurr->pvSeg = pu8BufferUnalignedPos;
5118 pSGEntryCurr->cbSeg = cbUnaligned;
5119 pu8BufferUnalignedPos += cbUnaligned;
5120
5121 /*
5122 * If the transfer is to the device we need to copy the content of the not mapped guest
5123 * segments into the temporary buffer.
5124 */
5125 if (pAhciPortTaskState->enmTxDir == AHCITXDIR_WRITE)
5126 ahciCopyFromSGListIntoBuffer(pDevIns, pSGInfoCurr);
5127
5128 /* Advance to next entry saving the pointers to the current ones. */
5129 pSGEntryPrev = pSGEntryCurr;
5130 pSGInfoPrev = pSGInfoCurr;
5131 pSGInfoCurr++;
5132 pSGEntryCurr++;
5133 pAhciPortTaskState->cSGListUsed++;
5134 cSGEntriesProcessed++;
5135 }
5136 }
5137 else
5138 {
5139 cbUnaligned += cbDataToTransfer;
5140 cbUnalignedComplete += cbDataToTransfer;
5141 cUnaligned++;
5142 }
5143 }
5144 else
5145 {
5146 /*
5147 * The size of the guest segment is sector aligned but it is possible that the segment crosses
5148 * a page boundary in a way splitting the segment into parts which are not sector aligned.
5149 * We have to treat them like unaligned guest segments then.
5150 */
5151 GCPhysAddrDataBase = AHCI_RTGCPHYS_FROM_U32(aSGLEntry[cActualSGEntry].u32DBAUp, aSGLEntry[cActualSGEntry].u32DBA);
5152
5153 ahciLog(("%s: GCPhysAddrDataBase=%RGp\n", __FUNCTION__, GCPhysAddrDataBase));
5154
5155 /*
5156 * Check if the physical address is page aligned.
5157 */
5158 if (GCPhysAddrDataBase & PAGE_OFFSET_MASK)
5159 {
5160 RTGCPHYS GCPhysAddrDataNextPage = PHYS_PAGE_ADDRESS(GCPhysAddrDataBase) + PAGE_SIZE;
5161 /* Difference from the buffer start to the next page boundary. */
5162 uint32_t u32GCPhysAddrDiff = GCPhysAddrDataNextPage - GCPhysAddrDataBase;
5163
5164 if (u32GCPhysAddrDiff % 512 != 0)
5165 {
5166 if (!fUnaligned)
5167 {
5168 /* We are not in an unaligned buffer but this is the first unaligned one. */
5169 fUnaligned = true;
5170 cbUnaligned = cbDataToTransfer;
5171 GCPhysAddrPRDTLUnalignedStart = GCPhysAddrPRDTLEntryStart + cActualSGEntry * sizeof(SGLEntry);
5172 cSGEntriesR3++;
5173 cUnaligned = 1;
5174 ahciLog(("%s: Guest segment is sector aligned but crosses a page boundary cb=%d\n", __FUNCTION__, cbDataToTransfer));
5175 }
5176 else
5177 {
5178 /* We are already in an unaligned buffer and this one is unaligned too. */
5179 cbUnaligned += cbDataToTransfer;
5180 cUnaligned++;
5181 }
5182
5183 cbUnalignedComplete += cbDataToTransfer;
5184 }
5185 else
5186 {
5187 ahciLog(("%s: Align page: GCPhysAddrDataBase=%RGp GCPhysAddrDataNextPage=%RGp\n",
5188 __FUNCTION__, GCPhysAddrDataBase, GCPhysAddrDataNextPage));
5189
5190 RTGCPHYS GCPhysBufferPageAligned = PHYS_PAGE_ADDRESS(GCPhysAddrDataBase);
5191
5192 /* Check if the mapping ends at the page boundary and set segment size accordingly. */
5193 cbSegment = (cbDataToTransfer < u32GCPhysAddrDiff)
5194 ? cbDataToTransfer
5195 : u32GCPhysAddrDiff;
5196 /* Subtract size of the buffer in the actual page. */
5197 cbDataToTransfer -= cbSegment;
5198
5199 if (GCPhysBufferPageAlignedPrev != GCPhysBufferPageAligned)
5200 {
5201 /* We don't need to map the buffer if it is in the same page as the previous one. */
5202 if (fDoMapping)
5203 {
5204 uint8_t *pbMapping;
5205
5206 pSGInfoCurr->fGuestMemory = true;
5207
5208 /* Create the mapping. */
5209 if (fReadonly)
5210 rc = PDMDevHlpPhysGCPhys2CCPtrReadOnly(pDevIns, GCPhysBufferPageAligned,
5211 0, (const void **)&pbMapping,
5212 &pSGInfoCurr->u.direct.PageLock);
5213 else
5214 rc = PDMDevHlpPhysGCPhys2CCPtr(pDevIns, GCPhysBufferPageAligned,
5215 0, (void **)&pbMapping,
5216 &pSGInfoCurr->u.direct.PageLock);
5217
5218 if (RT_FAILURE(rc))
5219 {
5220 /* Mapping failed. Fall back to a bounce buffer. */
5221 ahciLog(("%s: Mapping guest physical address %RGp failed with rc=%Rrc\n",
5222 __FUNCTION__, GCPhysBufferPageAligned, rc));
5223
5224 return ahciScatterGatherListCreateSafe(pAhciPort, pAhciPortTaskState, fReadonly,
5225 cSGEntriesProcessed);
5226 }
5227
5228 if ((pbMapping + (GCPhysAddrDataBase - GCPhysBufferPageAligned) == ((uint8_t *)pSGEntryPrev->pvSeg + pSGEntryCurr->cbSeg)))
5229 {
5230 pSGEntryPrev->cbSeg += cbSegment;
5231 ahciLog(("%s: Merged mapping pbMapping=%#p into current segment pvSeg=%#p. New size is cbSeg=%d\n",
5232 __FUNCTION__, pbMapping, pSGEntryPrev->pvSeg, pSGEntryPrev->cbSeg));
5233 }
5234 else
5235 {
5236 pSGEntryCurr->cbSeg = cbSegment;
5237
5238 /* Let pvBuf point to the start of the buffer in the page. */
5239 pSGEntryCurr->pvSeg = pbMapping
5240 + (GCPhysAddrDataBase - GCPhysBufferPageAligned);
5241
5242 ahciLog(("%s: pvSegBegin=%#p pvSegEnd=%#p\n", __FUNCTION__,
5243 pSGEntryCurr->pvSeg,
5244 (uint8_t *)pSGEntryCurr->pvSeg + pSGEntryCurr->cbSeg));
5245
5246 pSGEntryPrev = pSGEntryCurr;
5247 pSGEntryCurr++;
5248 pAhciPortTaskState->cSGListUsed++;
5249 }
5250
5251 pSGInfoPrev = pSGInfoCurr;
5252 pSGInfoCurr++;
5253 cSGEntriesProcessed++;
5254 }
5255 else
5256 cSGEntriesR3++;
5257 }
5258 else if (fDoMapping)
5259 {
5260 pSGEntryPrev->cbSeg += cbSegment;
5261 ahciLog(("%s: Buffer is already in previous mapping pvSeg=%#p. New size is cbSeg=%d\n",
5262 __FUNCTION__, pSGEntryPrev->pvSeg, pSGEntryPrev->cbSeg));
5263 }
5264
5265 /* Let physical address point to the next page in the buffer. */
5266 GCPhysAddrDataBase = GCPhysAddrDataNextPage;
5267 GCPhysBufferPageAlignedPrev = GCPhysBufferPageAligned;
5268 }
5269 }
5270
5271 if (!fUnaligned)
5272 {
5273 /* The address is now page aligned. */
5274 while (cbDataToTransfer)
5275 {
5276 ahciLog(("%s: GCPhysAddrDataBase=%RGp cbDataToTransfer=%u cSGEntriesR3=%u\n",
5277 __FUNCTION__, GCPhysAddrDataBase, cbDataToTransfer, cSGEntriesR3));
5278
5279 /* Check if this is the last page the buffer is in. */
5280 cbSegment = (cbDataToTransfer < PAGE_SIZE) ? cbDataToTransfer : PAGE_SIZE;
5281 cbDataToTransfer -= cbSegment;
5282
5283 if (fDoMapping)
5284 {
5285 void *pvMapping;
5286
5287 pSGInfoCurr->fGuestMemory = true;
5288
5289 /* Create the mapping. */
5290 if (fReadonly)
5291 rc = PDMDevHlpPhysGCPhys2CCPtrReadOnly(pDevIns, GCPhysAddrDataBase, 0, (const void **)&pvMapping, &pSGInfoCurr->u.direct.PageLock);
5292 else
5293 rc = PDMDevHlpPhysGCPhys2CCPtr(pDevIns, GCPhysAddrDataBase, 0, &pvMapping, &pSGInfoCurr->u.direct.PageLock);
5294
5295 if (RT_FAILURE(rc))
5296 {
5297 /* Mapping failed. Fall back to a bounce buffer. */
5298 ahciLog(("%s: Mapping guest physical address %RGp failed with rc=%Rrc\n",
5299 __FUNCTION__, GCPhysAddrDataBase, rc));
5300
5301 return ahciScatterGatherListCreateSafe(pAhciPort, pAhciPortTaskState, fReadonly,
5302 cSGEntriesProcessed);
5303 }
5304
5305 /* Check for adjacent mappings. */
5306 if (pvMapping == ((uint8_t *)pSGEntryPrev->pvSeg + pSGEntryPrev->cbSeg)
5307 && (pSGInfoPrev->fGuestMemory == true))
5308 {
5309 /* Yes they are adjacent. Just add the size of this mapping to the previous segment. */
5310 pSGEntryPrev->cbSeg += cbSegment;
5311 ahciLog(("%s: Merged mapping pvMapping=%#p into current segment pvSeg=%#p. New size is cbSeg=%d\n",
5312 __FUNCTION__, pvMapping, pSGEntryPrev->pvSeg, pSGEntryPrev->cbSeg));
5313 }
5314 else
5315 {
5316 /* No they are not. Use a new sg entry. */
5317 pSGEntryCurr->cbSeg = cbSegment;
5318 pSGEntryCurr->pvSeg = pvMapping;
5319 ahciLog(("%s: pvSegBegin=%#p pvSegEnd=%#p\n", __FUNCTION__,
5320 pSGEntryCurr->pvSeg,
5321 (uint8_t *)pSGEntryCurr->pvSeg + pSGEntryCurr->cbSeg));
5322 pSGEntryPrev = pSGEntryCurr;
5323 pSGEntryCurr++;
5324 pAhciPortTaskState->cSGListUsed++;
5325 }
5326
5327 pSGInfoPrev = pSGInfoCurr;
5328 pSGInfoCurr++;
5329 cSGEntriesProcessed++;
5330 }
5331 else
5332 cSGEntriesR3++;
5333
5334 GCPhysBufferPageAlignedPrev = GCPhysAddrDataBase;
5335
5336 /* Go to the next page. */
5337 GCPhysAddrDataBase += PAGE_SIZE;
5338 }
5339 } /* if (!fUnaligned) */
5340 } /* if !fUnaligned */
5341 } /* if guest segment is sector aligned. */
5342 } /* for SGEntries read */
5343
5344 /* Set address to the next entries to read. */
5345 GCPhysAddrPRDTLEntryStart += cSGLEntriesGCRead * sizeof(SGLEntry);
5346
5347 } while (cSGLEntriesGCLeft);
5348
5349 fDoMapping = true;
5350
5351 } /* for passes */
5352
5353 /* Check if the last processed segment was unaligned. We need to add it now. */
5354 if (fUnaligned)
5355 {
5356 /* Set up the entry. */
5357 AssertMsg(!(cbUnaligned % 512), ("Buffer is not sector aligned\n"));
5358 pSGInfoCurr->fGuestMemory = false;
5359 pSGInfoCurr->u.temp.GCPhysAddrBaseFirstUnaligned = GCPhysAddrPRDTLUnalignedStart;
5360 pSGInfoCurr->u.temp.cUnaligned = cUnaligned;
5361 pSGInfoCurr->u.temp.pvBuf = pu8BufferUnalignedPos;
5362
5363 pSGEntryCurr->pvSeg = pu8BufferUnalignedPos;
5364 pSGEntryCurr->cbSeg = cbUnaligned;
5365 pAhciPortTaskState->cSGListUsed++;
5366
5367 /*
5368 * If the transfer is to the device we need to copy the content of the not mapped guest
5369 * segments into the temporary buffer.
5370 */
5371 if (pAhciPortTaskState->enmTxDir == AHCITXDIR_WRITE)
5372 ahciCopyFromSGListIntoBuffer(pDevIns, pSGInfoCurr);
5373 }
5374
5375 STAM_PROFILE_STOP(&pAhciPort->StatProfileMapIntoR3, a);
5376
5377 return rc;
5378}
5379
5380/**
5381 * Destroy a scatter gather list and free all occupied resources (mappings, etc.)
5382 *
5383 * @returns VBox status code.
5384 * @param pAhciPort The ahci port.
5385 * @param pAhciPortTaskState The task state which contains the S/G list entries.
5386 */
5387static int ahciScatterGatherListDestroy(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState)
5388{
5389 PAHCIPORTTASKSTATESGENTRY pSGInfoCurr = pAhciPortTaskState->paSGEntries;
5390 PPDMDEVINS pDevIns = pAhciPort->CTX_SUFF(pDevIns);
5391
5392 STAM_PROFILE_START(&pAhciPort->StatProfileDestroyScatterGatherList, a);
5393
5394 if (pAhciPortTaskState->pfnPostProcess)
5395 {
5396 int rc;
5397 rc = pAhciPortTaskState->pfnPostProcess(pAhciPortTaskState);
5398 AssertRC(rc);
5399
5400 pAhciPortTaskState->pfnPostProcess = NULL;
5401
5402 /* Free the buffer holding the unprocessed data. They are not needed anymore. */
5403 RTMemFree(pAhciPortTaskState->pSGListHead[0].pvSeg);
5404 }
5405
5406 for (unsigned cActualSGEntry = 0; cActualSGEntry < pAhciPortTaskState->cSGEntries; cActualSGEntry++)
5407 {
5408 if (pSGInfoCurr->fGuestMemory)
5409 {
5410 /* Release the lock. */
5411 PDMDevHlpPhysReleasePageMappingLock(pDevIns, &pSGInfoCurr->u.direct.PageLock);
5412 }
5413 else if (pAhciPortTaskState->enmTxDir == AHCITXDIR_READ)
5414 {
5415 /* Copy the data into the guest segments now. */
5416 ahciCopyFromBufferIntoSGList(pDevIns, pSGInfoCurr);
5417 }
5418
5419 /* Go to the next entry. */
5420 pSGInfoCurr++;
5421 }
5422
5423 /* Free allocated memory if the list was too big too many times. */
5424 if (pAhciPortTaskState->cSGListTooBig >= AHCI_NR_OF_ALLOWED_BIGGER_LISTS)
5425 {
5426 RTMemFree(pAhciPortTaskState->pSGListHead);
5427 RTMemFree(pAhciPortTaskState->paSGEntries);
5428 if (pAhciPortTaskState->pvBufferUnaligned)
5429 RTMemPageFree(pAhciPortTaskState->pvBufferUnaligned, pAhciPortTaskState->cbBufferUnaligned);
5430 pAhciPortTaskState->cSGListSize = 0;
5431 pAhciPortTaskState->cSGListTooBig = 0;
5432 pAhciPortTaskState->pSGListHead = NULL;
5433 pAhciPortTaskState->paSGEntries = NULL;
5434 pAhciPortTaskState->pvBufferUnaligned = NULL;
5435 pAhciPortTaskState->cbBufferUnaligned = 0;
5436 }
5437
5438 STAM_PROFILE_STOP(&pAhciPort->StatProfileDestroyScatterGatherList, a);
5439
5440 return VINF_SUCCESS;
5441}
5442
5443/**
5444 * Copy a temporary buffer into a part of the guest scatter gather list
5445 * described by the given descriptor entry.
5446 *
5447 * @returns nothing.
5448 * @param pDevIns Pointer to the device instance data.
5449 * @param pSGInfo Pointer to the segment info structure which describes the guest segments
5450 * to write to which are unaligned.
5451 */
5452static void ahciCopyFromBufferIntoSGList(PPDMDEVINS pDevIns, PAHCIPORTTASKSTATESGENTRY pSGInfo)
5453{
5454 uint8_t *pu8Buf = (uint8_t *)pSGInfo->u.temp.pvBuf;
5455 SGLEntry aSGLEntries[5];
5456 uint32_t cSGEntriesLeft = pSGInfo->u.temp.cUnaligned;
5457 RTGCPHYS GCPhysPRDTLStart = pSGInfo->u.temp.GCPhysAddrBaseFirstUnaligned;
5458
5459 AssertMsg(!pSGInfo->fGuestMemory, ("This is not possible\n"));
5460
5461 do
5462 {
5463 uint32_t cSGEntriesRead = (cSGEntriesLeft < RT_ELEMENTS(aSGLEntries))
5464 ? cSGEntriesLeft
5465 : RT_ELEMENTS(aSGLEntries);
5466
5467 PDMDevHlpPhysRead(pDevIns, GCPhysPRDTLStart, &aSGLEntries[0], cSGEntriesRead * sizeof(SGLEntry));
5468
5469 for (uint32_t i = 0; i < cSGEntriesRead; i++)
5470 {
5471 RTGCPHYS GCPhysAddrDataBase = AHCI_RTGCPHYS_FROM_U32(aSGLEntries[i].u32DBAUp, aSGLEntries[i].u32DBA);
5472 uint32_t cbCopied = (aSGLEntries[i].u32DescInf & SGLENTRY_DESCINF_DBC) + 1;
5473
5474 /* Copy into SG entry. */
5475 PDMDevHlpPhysWrite(pDevIns, GCPhysAddrDataBase, pu8Buf, cbCopied);
5476
5477 pu8Buf += cbCopied;
5478 }
5479
5480 GCPhysPRDTLStart += cSGEntriesRead * sizeof(SGLEntry);
5481 cSGEntriesLeft -= cSGEntriesRead;
5482 } while (cSGEntriesLeft);
5483}
5484
5485/**
5486 * Copy a part of the guest scatter gather list into a temporary buffer.
5487 *
5488 * @returns nothing.
5489 * @param pDevIns Pointer to the device instance data.
5490 * @param pSGInfo Pointer to the segment info structure which describes the guest segments
5491 * to read from which are unaligned.
5492 */
5493static void ahciCopyFromSGListIntoBuffer(PPDMDEVINS pDevIns, PAHCIPORTTASKSTATESGENTRY pSGInfo)
5494{
5495 uint8_t *pu8Buf = (uint8_t *)pSGInfo->u.temp.pvBuf;
5496 SGLEntry aSGLEntries[5];
5497 uint32_t cSGEntriesLeft = pSGInfo->u.temp.cUnaligned;
5498 RTGCPHYS GCPhysPRDTLStart = pSGInfo->u.temp.GCPhysAddrBaseFirstUnaligned;
5499
5500 AssertMsg(!pSGInfo->fGuestMemory, ("This is not possible\n"));
5501
5502 do
5503 {
5504 uint32_t cSGEntriesRead = (cSGEntriesLeft < RT_ELEMENTS(aSGLEntries))
5505 ? cSGEntriesLeft
5506 : RT_ELEMENTS(aSGLEntries);
5507
5508 PDMDevHlpPhysRead(pDevIns, GCPhysPRDTLStart, &aSGLEntries[0], cSGEntriesRead * sizeof(SGLEntry));
5509
5510 for (uint32_t i = 0; i < cSGEntriesRead; i++)
5511 {
5512 RTGCPHYS GCPhysAddrDataBase = AHCI_RTGCPHYS_FROM_U32(aSGLEntries[i].u32DBAUp, aSGLEntries[i].u32DBA);
5513 uint32_t cbCopied = (aSGLEntries[i].u32DescInf & SGLENTRY_DESCINF_DBC) + 1;
5514
5515 /* Copy into buffer. */
5516 PDMDevHlpPhysRead(pDevIns, GCPhysAddrDataBase, pu8Buf, cbCopied);
5517
5518 pu8Buf += cbCopied;
5519 }
5520
5521 GCPhysPRDTLStart += cSGEntriesRead * sizeof(SGLEntry);
5522 cSGEntriesLeft -= cSGEntriesRead;
5523 } while (cSGEntriesLeft);
5524}
5525
5526
5527/**
5528 * Copy the content of a buffer to a scatter gather list.
5529 *
5530 * @returns Number of bytes transferred.
5531 * @param pAhciPortTaskState The task state which contains the S/G list entries.
5532 * @param pvBuf Pointer to the buffer which should be copied.
5533 * @param cbBuf Size of the buffer.
5534 */
5535static int ahciScatterGatherListCopyFromBuffer(PAHCIPORTTASKSTATE pAhciPortTaskState, void *pvBuf, size_t cbBuf)
5536{
5537 unsigned cSGEntry = 0;
5538 size_t cbCopied = 0;
5539 PRTSGSEG pSGEntry = &pAhciPortTaskState->pSGListHead[cSGEntry];
5540 uint8_t *pu8Buf = (uint8_t *)pvBuf;
5541
5542 while (cSGEntry < pAhciPortTaskState->cSGEntries)
5543 {
5544 size_t cbToCopy = RT_MIN(cbBuf, pSGEntry->cbSeg);
5545
5546 memcpy(pSGEntry->pvSeg, pu8Buf, cbToCopy);
5547
5548 cbBuf -= cbToCopy;
5549 cbCopied += cbToCopy;
5550
5551 /* We finished. */
5552 if (!cbBuf)
5553 break;
5554
5555 /* Advance the buffer. */
5556 pu8Buf += cbToCopy;
5557
5558 /* Go to the next entry in the list. */
5559 pSGEntry++;
5560 cSGEntry++;
5561 }
5562
5563 LogFlow(("%s: Copied %d bytes\n", __FUNCTION__, cbCopied));
5564 return cbCopied;
5565}
5566
5567/* -=-=-=-=- IBlockAsyncPort -=-=-=-=- */
5568
5569/** Makes a PAHCIPort out of a PPDMIBLOCKASYNCPORT. */
5570#define PDMIBLOCKASYNCPORT_2_PAHCIPORT(pInterface) ( (PAHCIPort)((uintptr_t)pInterface - RT_OFFSETOF(AHCIPort, IPortAsync)) )
5571
5572static void ahciWarningDiskFull(PPDMDEVINS pDevIns)
5573{
5574 int rc;
5575 LogRel(("AHCI: Host disk full\n"));
5576 rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND | VMSETRTERR_FLAGS_NO_WAIT, "DevAHCI_DISKFULL",
5577 N_("Host system reported disk full. VM execution is suspended. You can resume after freeing some space"));
5578 AssertRC(rc);
5579}
5580
5581static void ahciWarningFileTooBig(PPDMDEVINS pDevIns)
5582{
5583 int rc;
5584 LogRel(("AHCI: File too big\n"));
5585 rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND | VMSETRTERR_FLAGS_NO_WAIT, "DevAHCI_FILETOOBIG",
5586 N_("Host system reported that the file size limit of the host file system has been exceeded. VM execution is suspended. You need to move your virtual hard disk to a filesystem which allows bigger files"));
5587 AssertRC(rc);
5588}
5589
5590static void ahciWarningISCSI(PPDMDEVINS pDevIns)
5591{
5592 int rc;
5593 LogRel(("AHCI: iSCSI target unavailable\n"));
5594 rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND | VMSETRTERR_FLAGS_NO_WAIT, "DevAHCI_ISCSIDOWN",
5595 N_("The iSCSI target has stopped responding. VM execution is suspended. You can resume when it is available again"));
5596 AssertRC(rc);
5597}
5598
5599bool ahciIsRedoSetWarning(PAHCIPort pAhciPort, int rc)
5600{
5601 if (rc == VERR_DISK_FULL)
5602 {
5603 if (ASMAtomicCmpXchgBool(&pAhciPort->fRedo, true, false))
5604 ahciWarningDiskFull(pAhciPort->CTX_SUFF(pDevIns));
5605 return true;
5606 }
5607 if (rc == VERR_FILE_TOO_BIG)
5608 {
5609 if (ASMAtomicCmpXchgBool(&pAhciPort->fRedo, true, false))
5610 ahciWarningFileTooBig(pAhciPort->CTX_SUFF(pDevIns));
5611 return true;
5612 }
5613 if (rc == VERR_BROKEN_PIPE || rc == VERR_NET_CONNECTION_REFUSED)
5614 {
5615 /* iSCSI connection abort (first error) or failure to reestablish
5616 * connection (second error). Pause VM. On resume we'll retry. */
5617 if (ASMAtomicCmpXchgBool(&pAhciPort->fRedo, true, false))
5618 ahciWarningISCSI(pAhciPort->CTX_SUFF(pDevIns));
5619 return true;
5620 }
5621 return false;
5622}
5623
5624/**
5625 * Complete a data transfer task by freeing all occupied resources
5626 * and notifying the guest.
5627 *
5628 * @returns VBox status code
5629 *
5630 * @param pAhciPort Pointer to the port where to request completed.
5631 * @param pAhciPortTaskState Pointer to the task which finished.
5632 * @param rcReq IPRT status code of the completed request.
5633 */
5634static int ahciTransferComplete(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState, int rcReq)
5635{
5636 bool fRedo = false;
5637
5638 /* Free system resources occupied by the scatter gather list. */
5639 if (pAhciPortTaskState->enmTxDir != AHCITXDIR_FLUSH)
5640 ahciScatterGatherListDestroy(pAhciPort, pAhciPortTaskState);
5641
5642 if (pAhciPortTaskState->enmTxDir == AHCITXDIR_READ)
5643 {
5644 STAM_REL_COUNTER_ADD(&pAhciPort->StatBytesRead, pAhciPortTaskState->cbTransfer);
5645 pAhciPort->Led.Actual.s.fReading = 0;
5646 }
5647 else if (pAhciPortTaskState->enmTxDir == AHCITXDIR_WRITE)
5648 {
5649 STAM_REL_COUNTER_ADD(&pAhciPort->StatBytesWritten, pAhciPortTaskState->cbTransfer);
5650 pAhciPort->Led.Actual.s.fWriting = 0;
5651 }
5652
5653 if (RT_FAILURE(rcReq))
5654 {
5655 /* Log the error. */
5656 if (pAhciPort->cErrors++ < MAX_LOG_REL_ERRORS)
5657 {
5658 if (pAhciPortTaskState->enmTxDir == AHCITXDIR_FLUSH)
5659 LogRel(("AHCI#%u: Flush returned rc=%Rrc\n",
5660 pAhciPort->iLUN, rcReq));
5661 else
5662 LogRel(("AHCI#%u: %s at offset %llu (%u bytes left) returned rc=%Rrc\n",
5663 pAhciPort->iLUN,
5664 pAhciPortTaskState->enmTxDir == AHCITXDIR_READ
5665 ? "Read"
5666 : "Write",
5667 pAhciPortTaskState->uOffset,
5668 pAhciPortTaskState->cbTransfer, rcReq));
5669 }
5670
5671 fRedo = ahciIsRedoSetWarning(pAhciPort, rcReq);
5672 if (!fRedo)
5673 {
5674 pAhciPortTaskState->cmdHdr.u32PRDBC = 0;
5675 pAhciPortTaskState->uATARegError = ID_ERR;
5676 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_ERR;
5677 ASMAtomicCmpXchgPtr(&pAhciPort->pTaskErr, pAhciPortTaskState, NULL);
5678 }
5679 else
5680 ASMAtomicOrU32(&pAhciPort->u32TasksNew, (1 << pAhciPortTaskState->uTag));
5681 }
5682 else
5683 {
5684 pAhciPortTaskState->cmdHdr.u32PRDBC = pAhciPortTaskState->cbTransfer;
5685
5686 pAhciPortTaskState->uATARegError = 0;
5687 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
5688
5689 /* Write updated command header into memory of the guest. */
5690 PDMDevHlpPhysWrite(pAhciPort->CTX_SUFF(pDevIns), pAhciPortTaskState->GCPhysCmdHdrAddr,
5691 &pAhciPortTaskState->cmdHdr, sizeof(CmdHdr));
5692 }
5693
5694#ifdef RT_STRICT
5695 bool fXchg = ASMAtomicCmpXchgBool(&pAhciPortTaskState->fActive, false, true);
5696 AssertMsg(fXchg, ("Task is not active\n"));
5697#endif
5698
5699 /* Add the task to the cache. */
5700 ASMAtomicWritePtr(&pAhciPort->aCachedTasks[pAhciPortTaskState->uTag], pAhciPortTaskState);
5701 ASMAtomicDecU32(&pAhciPort->cTasksActive);
5702
5703 if (!fRedo)
5704 {
5705 if (pAhciPortTaskState->fQueued)
5706 {
5707 if (RT_SUCCESS(rcReq) && !ASMAtomicReadPtrT(&pAhciPort->pTaskErr, PAHCIPORTTASKSTATE))
5708 ASMAtomicOrU32(&pAhciPort->u32QueuedTasksFinished, (1 << pAhciPortTaskState->uTag));
5709
5710 /*
5711 * Always raise an interrupt after task completion; delaying
5712 * this (interrupt coalescing) increases latency and has a significant
5713 * impact on performance (see #5071)
5714 */
5715 ahciSendSDBFis(pAhciPort, 0, true);
5716 }
5717 else
5718 ahciSendD2HFis(pAhciPort, pAhciPortTaskState, pAhciPortTaskState->cmdFis, true);
5719 }
5720
5721 return VINF_SUCCESS;
5722}
5723
5724/**
5725 * Notification callback for a completed transfer.
5726 *
5727 * @returns VBox status code.
5728 * @param pInterface Pointer to the interface.
5729 * @param pvUser User data.
5730 * @param rcReq IPRT Status code of the completed request.
5731 */
5732static DECLCALLBACK(int) ahciTransferCompleteNotify(PPDMIBLOCKASYNCPORT pInterface, void *pvUser, int rcReq)
5733{
5734 PAHCIPort pAhciPort = PDMIBLOCKASYNCPORT_2_PAHCIPORT(pInterface);
5735 PAHCIPORTTASKSTATE pAhciPortTaskState = (PAHCIPORTTASKSTATE)pvUser;
5736
5737 ahciLog(("%s: pInterface=%p pvUser=%p uTag=%u\n",
5738 __FUNCTION__, pInterface, pvUser, pAhciPortTaskState->uTag));
5739
5740 int rc = ahciTransferComplete(pAhciPort, pAhciPortTaskState, rcReq);
5741
5742 if (pAhciPort->cTasksActive == 0 && pAhciPort->pAhciR3->fSignalIdle)
5743 PDMDevHlpAsyncNotificationCompleted(pAhciPort->pDevInsR3);
5744 return rc;
5745}
5746
5747/**
5748 * Process an non read/write ATA command.
5749 *
5750 * @returns The direction of the data transfer
5751 * @param pCmdHdr Pointer to the command header.
5752 */
5753static AHCITXDIR ahciProcessCmd(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState, uint8_t *pCmdFis)
5754{
5755 AHCITXDIR rc = AHCITXDIR_NONE;
5756 bool fLBA48 = false;
5757 CmdHdr *pCmdHdr = &pAhciPortTaskState->cmdHdr;
5758
5759 AssertMsg(pCmdFis[AHCI_CMDFIS_TYPE] == AHCI_CMDFIS_TYPE_H2D, ("FIS is not a host to device Fis!!\n"));
5760
5761 pAhciPortTaskState->cbTransfer = 0;
5762
5763 switch (pCmdFis[AHCI_CMDFIS_CMD])
5764 {
5765 case ATA_IDENTIFY_DEVICE:
5766 {
5767 if (pAhciPort->pDrvBlock && !pAhciPort->fATAPI)
5768 {
5769 int rc2;
5770 uint16_t u16Temp[256];
5771
5772 /* Fill the buffer. */
5773 ahciIdentifySS(pAhciPort, u16Temp);
5774
5775 /* Create scatter gather list. */
5776 rc2 = ahciScatterGatherListCreate(pAhciPort, pAhciPortTaskState, false);
5777 if (RT_FAILURE(rc2))
5778 AssertMsgFailed(("Creating list failed rc=%Rrc\n", rc2));
5779
5780 /* Copy the buffer. */
5781 pCmdHdr->u32PRDBC = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, &u16Temp[0], sizeof(u16Temp));
5782
5783 /* Destroy list. */
5784 rc2 = ahciScatterGatherListDestroy(pAhciPort, pAhciPortTaskState);
5785 if (RT_FAILURE(rc2))
5786 AssertMsgFailed(("Freeing list failed rc=%Rrc\n", rc2));
5787
5788 pAhciPortTaskState->uATARegError = 0;
5789 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
5790
5791 /* Write updated command header into memory of the guest. */
5792 PDMDevHlpPhysWrite(pAhciPort->CTX_SUFF(pDevIns), pAhciPortTaskState->GCPhysCmdHdrAddr, pCmdHdr, sizeof(CmdHdr));
5793 }
5794 else
5795 {
5796 pAhciPortTaskState->uATARegError = ABRT_ERR;
5797 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
5798 }
5799 break;
5800 }
5801 case ATA_READ_NATIVE_MAX_ADDRESS_EXT:
5802 case ATA_READ_NATIVE_MAX_ADDRESS:
5803 break;
5804 case ATA_SET_FEATURES:
5805 {
5806 switch (pCmdFis[AHCI_CMDFIS_FET])
5807 {
5808 case 0x02: /* write cache enable */
5809 case 0xaa: /* read look-ahead enable */
5810 case 0x55: /* read look-ahead disable */
5811 case 0xcc: /* reverting to power-on defaults enable */
5812 case 0x66: /* reverting to power-on defaults disable */
5813 pAhciPortTaskState->uATARegError = 0;
5814 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
5815 break;
5816 case 0x82: /* write cache disable */
5817 rc = AHCITXDIR_FLUSH;
5818 break;
5819 case 0x03:
5820 { /* set transfer mode */
5821 Log2(("%s: transfer mode %#04x\n", __FUNCTION__, pCmdFis[AHCI_CMDFIS_SECTC]));
5822 switch (pCmdFis[AHCI_CMDFIS_SECTC] & 0xf8)
5823 {
5824 case 0x00: /* PIO default */
5825 case 0x08: /* PIO mode */
5826 break;
5827 case ATA_MODE_MDMA: /* MDMA mode */
5828 pAhciPort->uATATransferMode = (pCmdFis[AHCI_CMDFIS_SECTC] & 0xf8) | RT_MIN(pCmdFis[AHCI_CMDFIS_SECTC] & 0x07, ATA_MDMA_MODE_MAX);
5829 break;
5830 case ATA_MODE_UDMA: /* UDMA mode */
5831 pAhciPort->uATATransferMode = (pCmdFis[AHCI_CMDFIS_SECTC] & 0xf8) | RT_MIN(pCmdFis[AHCI_CMDFIS_SECTC] & 0x07, ATA_UDMA_MODE_MAX);
5832 break;
5833 }
5834 break;
5835 }
5836 default:
5837 pAhciPortTaskState->uATARegError = ABRT_ERR;
5838 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_ERR;
5839 }
5840 break;
5841 }
5842 case ATA_DEVICE_RESET:
5843 {
5844 if (!pAhciPort->fATAPI)
5845 {
5846 pAhciPortTaskState->uATARegError = ABRT_ERR;
5847 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_ERR;
5848 }
5849 else
5850 {
5851 /* Reset the device. */
5852 ahciDeviceReset(pAhciPort, pAhciPortTaskState);
5853 }
5854 break;
5855 }
5856 case ATA_FLUSH_CACHE_EXT:
5857 case ATA_FLUSH_CACHE:
5858 rc = AHCITXDIR_FLUSH;
5859 break;
5860 case ATA_PACKET:
5861 if (!pAhciPort->fATAPI)
5862 {
5863 pAhciPortTaskState->uATARegError = ABRT_ERR;
5864 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_ERR;
5865 }
5866 else
5867 rc = atapiParseCmd(pAhciPort, pAhciPortTaskState);
5868 break;
5869 case ATA_IDENTIFY_PACKET_DEVICE:
5870 if (!pAhciPort->fATAPI)
5871 {
5872 pAhciPortTaskState->uATARegError = ABRT_ERR;
5873 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_ERR;
5874 }
5875 else
5876 {
5877 atapiDoTransfer(pAhciPort, pAhciPortTaskState, ATAFN_SS_ATAPI_IDENTIFY);
5878
5879 pAhciPortTaskState->uATARegError = 0;
5880 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
5881 }
5882 break;
5883 case ATA_SET_MULTIPLE_MODE:
5884 if ( pCmdFis[AHCI_CMDFIS_SECTC] != 0
5885 && ( pCmdFis[AHCI_CMDFIS_SECTC] > ATA_MAX_MULT_SECTORS
5886 || (pCmdFis[AHCI_CMDFIS_SECTC] & (pCmdFis[AHCI_CMDFIS_SECTC] - 1)) != 0))
5887 {
5888 pAhciPortTaskState->uATARegError = ABRT_ERR;
5889 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_ERR;
5890 }
5891 else
5892 {
5893 Log2(("%s: set multi sector count to %d\n", __FUNCTION__, pCmdFis[AHCI_CMDFIS_SECTC]));
5894 pAhciPort->cMultSectors = pCmdFis[AHCI_CMDFIS_SECTC];
5895 pAhciPortTaskState->uATARegError = 0;
5896 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
5897 }
5898 break;
5899 case ATA_STANDBY_IMMEDIATE:
5900 break; /* Do nothing. */
5901 case ATA_CHECK_POWER_MODE:
5902 pAhciPortTaskState->cmdFis[AHCI_CMDFIS_SECTC] = 0xff; /* drive active or idle */
5903 /* fall through */
5904 case ATA_INITIALIZE_DEVICE_PARAMETERS:
5905 case ATA_IDLE_IMMEDIATE:
5906 case ATA_RECALIBRATE:
5907 case ATA_NOP:
5908 case ATA_READ_VERIFY_SECTORS_EXT:
5909 case ATA_READ_VERIFY_SECTORS:
5910 case ATA_READ_VERIFY_SECTORS_WITHOUT_RETRIES:
5911 case ATA_SLEEP:
5912 pAhciPortTaskState->uATARegError = 0;
5913 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
5914 break;
5915 case ATA_READ_DMA_EXT:
5916 fLBA48 = true;
5917 case ATA_READ_DMA:
5918 {
5919 pAhciPortTaskState->cbTransfer = ahciGetNSectors(pCmdFis, fLBA48) * 512;
5920 pAhciPortTaskState->uOffset = ahciGetSector(pAhciPort, pCmdFis, fLBA48) * 512;
5921 rc = AHCITXDIR_READ;
5922 break;
5923 }
5924 case ATA_WRITE_DMA_EXT:
5925 fLBA48 = true;
5926 case ATA_WRITE_DMA:
5927 {
5928 pAhciPortTaskState->cbTransfer = ahciGetNSectors(pCmdFis, fLBA48) * 512;
5929 pAhciPortTaskState->uOffset = ahciGetSector(pAhciPort, pCmdFis, fLBA48) * 512;
5930 rc = AHCITXDIR_WRITE;
5931 break;
5932 }
5933 case ATA_READ_FPDMA_QUEUED:
5934 {
5935 pAhciPortTaskState->cbTransfer = ahciGetNSectorsQueued(pCmdFis) * 512;
5936 pAhciPortTaskState->uOffset = ahciGetSectorQueued(pCmdFis) * 512;
5937 rc = AHCITXDIR_READ;
5938 break;
5939 }
5940 case ATA_WRITE_FPDMA_QUEUED:
5941 {
5942 pAhciPortTaskState->cbTransfer = ahciGetNSectorsQueued(pCmdFis) * 512;
5943 pAhciPortTaskState->uOffset = ahciGetSectorQueued(pCmdFis) * 512;
5944 rc = AHCITXDIR_WRITE;
5945 break;
5946 }
5947 case ATA_READ_LOG_EXT:
5948 {
5949 size_t cbLogRead = ((pCmdFis[AHCI_CMDFIS_SECTCEXP] << 8) | pCmdFis[AHCI_CMDFIS_SECTC]) * 512;
5950 unsigned offLogRead = ((pCmdFis[AHCI_CMDFIS_CYLLEXP] << 8) | pCmdFis[AHCI_CMDFIS_CYLL]) * 512;
5951 unsigned iPage = pCmdFis[AHCI_CMDFIS_SECTN];
5952
5953 LogFlow(("Trying to read %zu bytes starting at offset %u from page %u\n", cbLogRead, offLogRead, iPage));
5954
5955 uint8_t aBuf[512];
5956
5957 memset(aBuf, 0, sizeof(aBuf));
5958
5959 if (offLogRead + cbLogRead <= sizeof(aBuf))
5960 {
5961 switch (iPage)
5962 {
5963 case 0x10:
5964 {
5965 LogFlow(("Reading error page\n"));
5966 PAHCIPORTTASKSTATE pTaskErr = ASMAtomicXchgPtrT(&pAhciPort->pTaskErr, NULL, PAHCIPORTTASKSTATE);
5967 if (pTaskErr)
5968 {
5969 aBuf[0] = pTaskErr->fQueued ? pTaskErr->uTag : (1 << 7);
5970 aBuf[2] = pTaskErr->uATARegStatus;
5971 aBuf[3] = pTaskErr->uATARegError;
5972 aBuf[4] = pTaskErr->cmdFis[AHCI_CMDFIS_SECTN];
5973 aBuf[5] = pTaskErr->cmdFis[AHCI_CMDFIS_CYLL];
5974 aBuf[6] = pTaskErr->cmdFis[AHCI_CMDFIS_CYLH];
5975 aBuf[7] = pTaskErr->cmdFis[AHCI_CMDFIS_HEAD];
5976 aBuf[8] = pTaskErr->cmdFis[AHCI_CMDFIS_SECTNEXP];
5977 aBuf[9] = pTaskErr->cmdFis[AHCI_CMDFIS_CYLLEXP];
5978 aBuf[10] = pTaskErr->cmdFis[AHCI_CMDFIS_CYLHEXP];
5979 aBuf[12] = pTaskErr->cmdFis[AHCI_CMDFIS_SECTC];
5980 aBuf[13] = pTaskErr->cmdFis[AHCI_CMDFIS_SECTCEXP];
5981
5982 /* Calculate checksum */
5983 uint8_t uChkSum = 0;
5984 for (unsigned i = 0; i < RT_ELEMENTS(aBuf)-1; i++)
5985 uChkSum += aBuf[i];
5986
5987 aBuf[511] = (uint8_t)-(int8_t)uChkSum;
5988
5989 /*
5990 * Reading this log page results in an abort of all outstanding commands
5991 * and clearing the SActive register and TaskFile register.
5992 */
5993 ahciSendSDBFis(pAhciPort, 0xffffffff, true);
5994 }
5995 break;
5996 }
5997 }
5998
5999 /* Create scatter gather list. */
6000 int rc2 = ahciScatterGatherListCreate(pAhciPort, pAhciPortTaskState, false);
6001 if (RT_FAILURE(rc2))
6002 AssertMsgFailed(("Creating list failed rc=%Rrc\n", rc2));
6003
6004 /* Copy the buffer. */
6005 pCmdHdr->u32PRDBC = ahciScatterGatherListCopyFromBuffer(pAhciPortTaskState, &aBuf[offLogRead], cbLogRead);
6006
6007 /* Destroy list. */
6008 rc2 = ahciScatterGatherListDestroy(pAhciPort, pAhciPortTaskState);
6009 if (RT_FAILURE(rc2))
6010 AssertMsgFailed(("Freeing list failed rc=%Rrc\n", rc2));
6011
6012 pAhciPortTaskState->uATARegError = 0;
6013 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
6014
6015 /* Write updated command header into memory of the guest. */
6016 PDMDevHlpPhysWrite(pAhciPort->CTX_SUFF(pDevIns), pAhciPortTaskState->GCPhysCmdHdrAddr, pCmdHdr, sizeof(CmdHdr));
6017 }
6018
6019 break;
6020 }
6021 /* All not implemented commands go below. */
6022 case ATA_SECURITY_FREEZE_LOCK:
6023 case ATA_SMART:
6024 case ATA_NV_CACHE:
6025 case ATA_IDLE:
6026 pAhciPortTaskState->uATARegError = ABRT_ERR;
6027 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_ERR;
6028 break;
6029 default: /* For debugging purposes. */
6030 AssertMsgFailed(("Unknown command issued\n"));
6031 pAhciPortTaskState->uATARegError = ABRT_ERR;
6032 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_ERR;
6033 }
6034
6035 return rc;
6036}
6037
6038/**
6039 * Retrieve a command FIS from guest memory.
6040 *
6041 * @returns nothing
6042 * @param pAhciPortTaskState The state of the actual task.
6043 */
6044static void ahciPortTaskGetCommandFis(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState)
6045{
6046 RTGCPHYS GCPhysAddrCmdTbl;
6047
6048 AssertMsg(pAhciPort->GCPhysAddrClb && pAhciPort->GCPhysAddrFb, ("%s: GCPhysAddrClb and/or GCPhysAddrFb are 0\n", __FUNCTION__));
6049
6050 /*
6051 * First we are reading the command header pointed to by regCLB.
6052 * From this we get the address of the command table which we are reading too.
6053 * We can process the Command FIS afterwards.
6054 */
6055 pAhciPortTaskState->GCPhysCmdHdrAddr = pAhciPort->GCPhysAddrClb + pAhciPortTaskState->uTag * sizeof(CmdHdr);
6056 LogFlow(("%s: PDMDevHlpPhysRead GCPhysAddrCmdLst=%RGp cbCmdHdr=%u\n", __FUNCTION__,
6057 pAhciPortTaskState->GCPhysCmdHdrAddr, sizeof(CmdHdr)));
6058 PDMDevHlpPhysRead(pAhciPort->CTX_SUFF(pDevIns), pAhciPortTaskState->GCPhysCmdHdrAddr, &pAhciPortTaskState->cmdHdr, sizeof(CmdHdr));
6059
6060#ifdef DEBUG
6061 /* Print some infos about the command header. */
6062 ahciDumpCmdHdrInfo(pAhciPort, &pAhciPortTaskState->cmdHdr);
6063#endif
6064
6065 GCPhysAddrCmdTbl = AHCI_RTGCPHYS_FROM_U32(pAhciPortTaskState->cmdHdr.u32CmdTblAddrUp, pAhciPortTaskState->cmdHdr.u32CmdTblAddr);
6066
6067 AssertMsg((pAhciPortTaskState->cmdHdr.u32DescInf & AHCI_CMDHDR_CFL_MASK) * sizeof(uint32_t) == AHCI_CMDFIS_TYPE_H2D_SIZE,
6068 ("This is not a command FIS!!\n"));
6069
6070 /* Read the command Fis. */
6071 LogFlow(("%s: PDMDevHlpPhysRead GCPhysAddrCmdTbl=%RGp cbCmdFis=%u\n", __FUNCTION__, GCPhysAddrCmdTbl, AHCI_CMDFIS_TYPE_H2D_SIZE));
6072 PDMDevHlpPhysRead(pAhciPort->CTX_SUFF(pDevIns), GCPhysAddrCmdTbl, &pAhciPortTaskState->cmdFis[0], AHCI_CMDFIS_TYPE_H2D_SIZE);
6073
6074 /* Set transfer direction. */
6075 pAhciPortTaskState->enmTxDir = (pAhciPortTaskState->cmdHdr.u32DescInf & AHCI_CMDHDR_W) ? AHCITXDIR_WRITE : AHCITXDIR_READ;
6076
6077 /* If this is an ATAPI command read the atapi command. */
6078 if (pAhciPortTaskState->cmdHdr.u32DescInf & AHCI_CMDHDR_A)
6079 {
6080 GCPhysAddrCmdTbl += AHCI_CMDHDR_ACMD_OFFSET;
6081 PDMDevHlpPhysRead(pAhciPort->CTX_SUFF(pDevIns), GCPhysAddrCmdTbl, &pAhciPortTaskState->aATAPICmd[0], ATAPI_PACKET_SIZE);
6082 }
6083
6084 /* We "received" the FIS. Clear the BSY bit in regTFD. */
6085 if ((pAhciPortTaskState->cmdHdr.u32DescInf & AHCI_CMDHDR_C) && (pAhciPortTaskState->fQueued))
6086 {
6087 /*
6088 * We need to send a FIS which clears the busy bit if this is a queued command so that the guest can queue other commands.
6089 * but this FIS does not assert an interrupt
6090 */
6091 ahciSendD2HFis(pAhciPort, pAhciPortTaskState, pAhciPortTaskState->cmdFis, false);
6092 pAhciPort->regTFD &= ~AHCI_PORT_TFD_BSY;
6093 }
6094
6095#ifdef DEBUG
6096 /* Print some infos about the FIS. */
6097 ahciDumpFisInfo(pAhciPort, &pAhciPortTaskState->cmdFis[0]);
6098
6099 /* Print the PRDT */
6100 RTGCPHYS GCPhysAddrPRDTLEntryStart = AHCI_RTGCPHYS_FROM_U32(pAhciPortTaskState->cmdHdr.u32CmdTblAddrUp, pAhciPortTaskState->cmdHdr.u32CmdTblAddr) + AHCI_CMDHDR_PRDT_OFFSET;
6101
6102 ahciLog(("PRDT address %RGp number of entries %u\n", GCPhysAddrPRDTLEntryStart, AHCI_CMDHDR_PRDTL_ENTRIES(pAhciPortTaskState->cmdHdr.u32DescInf)));
6103
6104 for (unsigned i = 0; i < AHCI_CMDHDR_PRDTL_ENTRIES(pAhciPortTaskState->cmdHdr.u32DescInf); i++)
6105 {
6106 SGLEntry SGEntry;
6107
6108 ahciLog(("Entry %u at address %RGp\n", i, GCPhysAddrPRDTLEntryStart));
6109 PDMDevHlpPhysRead(pAhciPort->CTX_SUFF(pDevIns), GCPhysAddrPRDTLEntryStart, &SGEntry, sizeof(SGLEntry));
6110
6111 RTGCPHYS GCPhysDataAddr = AHCI_RTGCPHYS_FROM_U32(SGEntry.u32DBAUp, SGEntry.u32DBA);
6112 ahciLog(("GCPhysAddr=%RGp Size=%u\n", GCPhysDataAddr, SGEntry.u32DescInf & SGLENTRY_DESCINF_DBC));
6113
6114 GCPhysAddrPRDTLEntryStart += sizeof(SGLEntry);
6115 }
6116#endif
6117}
6118
6119/**
6120 * Transmit queue consumer
6121 * Queue a new async task.
6122 *
6123 * @returns Success indicator.
6124 * If false the item will not be removed and the flushing will stop.
6125 * @param pDevIns The device instance.
6126 * @param pItem The item to consume. Upon return this item will be freed.
6127 */
6128static DECLCALLBACK(bool) ahciNotifyQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
6129{
6130 PDEVPORTNOTIFIERQUEUEITEM pNotifierItem = (PDEVPORTNOTIFIERQUEUEITEM)pItem;
6131 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
6132 PAHCIPort pAhciPort = &pAhci->ahciPort[pNotifierItem->iPort];
6133 int rc = VINF_SUCCESS;
6134
6135 if (!pAhciPort->fAsyncInterface)
6136 {
6137 ahciLog(("%s: Got notification from GC\n", __FUNCTION__));
6138 /* Notify the async IO thread. */
6139 rc = RTSemEventSignal(pAhciPort->AsyncIORequestSem);
6140 AssertRC(rc);
6141 }
6142 else
6143 {
6144 unsigned idx = 0;
6145 uint32_t u32Tasks = ASMAtomicXchgU32(&pAhciPort->u32TasksNew, 0);
6146
6147 idx = ASMBitFirstSetU32(u32Tasks);
6148 while (idx)
6149 {
6150 AHCITXDIR enmTxDir;
6151 PAHCIPORTTASKSTATE pAhciPortTaskState;
6152
6153 /* Decrement to get the slot number. */
6154 idx--;
6155 ahciLog(("%s: Processing command at slot %d\n", __FUNCTION__, idx));
6156
6157 /*
6158 * Check if there is already an allocated task struct in the cache.
6159 * Allocate a new task otherwise.
6160 */
6161 if (!pAhciPort->aCachedTasks[idx])
6162 {
6163 pAhciPortTaskState = (PAHCIPORTTASKSTATE)RTMemAllocZ(sizeof(AHCIPORTTASKSTATE));
6164 AssertMsg(pAhciPortTaskState, ("%s: Cannot allocate task state memory!\n"));
6165 }
6166 else
6167 pAhciPortTaskState = pAhciPort->aCachedTasks[idx];
6168
6169#ifdef RT_STRICT
6170 bool fXchg = ASMAtomicCmpXchgBool(&pAhciPortTaskState->fActive, true, false);
6171 AssertMsg(fXchg, ("Task is already active\n"));
6172#endif
6173
6174 pAhciPortTaskState->uATARegStatus = 0;
6175 pAhciPortTaskState->uATARegError = 0;
6176
6177 /* Set current command slot */
6178 pAhciPortTaskState->uTag = idx;
6179 pAhciPort->regCMD |= (AHCI_PORT_CMD_CCS_SHIFT(pAhciPortTaskState->uTag));
6180
6181 ahciPortTaskGetCommandFis(pAhciPort, pAhciPortTaskState);
6182
6183 /* Mark the task as processed by the HBA if this is a queued task so that it doesn't occur in the CI register anymore. */
6184 if (pAhciPort->regSACT & (1 << idx))
6185 {
6186 pAhciPortTaskState->fQueued = true;
6187 ASMAtomicOrU32(&pAhciPort->u32TasksFinished, (1 << pAhciPortTaskState->uTag));
6188 }
6189 else
6190 pAhciPortTaskState->fQueued = false;
6191
6192 if (!(pAhciPortTaskState->cmdFis[AHCI_CMDFIS_BITS] & AHCI_CMDFIS_C))
6193 {
6194 /* If the reset bit is set put the device into reset state. */
6195 if (pAhciPortTaskState->cmdFis[AHCI_CMDFIS_CTL] & AHCI_CMDFIS_CTL_SRST)
6196 {
6197 ahciLog(("%s: Setting device into reset state\n", __FUNCTION__));
6198 pAhciPort->fResetDevice = true;
6199 ahciSendD2HFis(pAhciPort, pAhciPortTaskState, pAhciPortTaskState->cmdFis, true);
6200 pAhciPort->aCachedTasks[idx] = pAhciPortTaskState;
6201#ifdef RT_STRICT
6202 fXchg = ASMAtomicCmpXchgBool(&pAhciPortTaskState->fActive, false, true);
6203 AssertMsg(fXchg, ("Task is not active\n"));
6204#endif
6205 return true;
6206 }
6207 else if (pAhciPort->fResetDevice) /* The bit is not set and we are in a reset state. */
6208 {
6209 ahciFinishStorageDeviceReset(pAhciPort, pAhciPortTaskState);
6210 pAhciPort->aCachedTasks[idx] = pAhciPortTaskState;
6211#ifdef RT_STRICT
6212 fXchg = ASMAtomicCmpXchgBool(&pAhciPortTaskState->fActive, false, true);
6213 AssertMsg(fXchg, ("Task is not active\n"));
6214#endif
6215 return true;
6216 }
6217 else /* We are not in a reset state update the control registers. */
6218 AssertMsgFailed(("%s: Update the control register\n", __FUNCTION__));
6219 }
6220 else
6221 {
6222 enmTxDir = ahciProcessCmd(pAhciPort, pAhciPortTaskState, pAhciPortTaskState->cmdFis);
6223
6224 if (enmTxDir != AHCITXDIR_NONE)
6225 {
6226 pAhciPortTaskState->enmTxDir = enmTxDir;
6227
6228 ASMAtomicIncU32(&pAhciPort->cTasksActive);
6229
6230 if (enmTxDir != AHCITXDIR_FLUSH)
6231 {
6232 STAM_REL_COUNTER_INC(&pAhciPort->StatDMA);
6233
6234 rc = ahciScatterGatherListCreate(pAhciPort, pAhciPortTaskState, (enmTxDir == AHCITXDIR_READ) ? false : true);
6235 if (RT_FAILURE(rc))
6236 AssertMsgFailed(("%s: Failed to process command %Rrc\n", __FUNCTION__, rc));
6237 }
6238
6239 if (enmTxDir == AHCITXDIR_FLUSH)
6240 {
6241 rc = pAhciPort->pDrvBlockAsync->pfnStartFlush(pAhciPort->pDrvBlockAsync,
6242 pAhciPortTaskState);
6243 }
6244 else if (enmTxDir == AHCITXDIR_READ)
6245 {
6246 pAhciPort->Led.Asserted.s.fReading = pAhciPort->Led.Actual.s.fReading = 1;
6247 rc = pAhciPort->pDrvBlockAsync->pfnStartRead(pAhciPort->pDrvBlockAsync, pAhciPortTaskState->uOffset,
6248 pAhciPortTaskState->pSGListHead, pAhciPortTaskState->cSGListUsed,
6249 pAhciPortTaskState->cbTransfer,
6250 pAhciPortTaskState);
6251 }
6252 else
6253 {
6254 pAhciPort->Led.Asserted.s.fWriting = pAhciPort->Led.Actual.s.fWriting = 1;
6255 rc = pAhciPort->pDrvBlockAsync->pfnStartWrite(pAhciPort->pDrvBlockAsync, pAhciPortTaskState->uOffset,
6256 pAhciPortTaskState->pSGListHead, pAhciPortTaskState->cSGListUsed,
6257 pAhciPortTaskState->cbTransfer,
6258 pAhciPortTaskState);
6259 }
6260 if (rc == VINF_VD_ASYNC_IO_FINISHED)
6261 rc = ahciTransferComplete(pAhciPort, pAhciPortTaskState, VINF_SUCCESS);
6262 else if (RT_FAILURE(rc) && rc != VERR_VD_ASYNC_IO_IN_PROGRESS)
6263 rc = ahciTransferComplete(pAhciPort, pAhciPortTaskState, rc);
6264 }
6265 else
6266 {
6267#ifdef RT_STRICT
6268 fXchg = ASMAtomicCmpXchgBool(&pAhciPortTaskState->fActive, false, true);
6269 AssertMsg(fXchg, ("Task is not active\n"));
6270#endif
6271
6272 /* There is nothing left to do. Notify the guest. */
6273 ahciSendD2HFis(pAhciPort, pAhciPortTaskState, &pAhciPortTaskState->cmdFis[0], true);
6274 /* Add the task to the cache. */
6275 pAhciPort->aCachedTasks[pAhciPortTaskState->uTag] = pAhciPortTaskState;
6276 }
6277 } /* Command */
6278
6279 u32Tasks &= ~(1 << idx); /* Clear task bit. */
6280 idx = ASMBitFirstSetU32(u32Tasks);
6281 } /* while tasks available */
6282 } /* fUseAsyncInterface */
6283
6284 return true;
6285}
6286
6287/* The async IO thread for one port. */
6288static DECLCALLBACK(int) ahciAsyncIOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
6289{
6290 PAHCIPort pAhciPort = (PAHCIPort)pThread->pvUser;
6291 PAHCI pAhci = pAhciPort->CTX_SUFF(pAhci);
6292 PAHCIPORTTASKSTATE pAhciPortTaskState;
6293 int rc = VINF_SUCCESS;
6294 uint64_t u64StartTime = 0;
6295 uint64_t u64StopTime = 0;
6296 uint32_t uIORequestsProcessed = 0;
6297 uint32_t uIOsPerSec = 0;
6298 uint32_t fTasksToProcess = 0;
6299 unsigned idx = 0;
6300
6301 ahciLog(("%s: Port %d entering async IO loop.\n", __FUNCTION__, pAhciPort->iLUN));
6302
6303 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
6304 return VINF_SUCCESS;
6305
6306 /* We use only one task structure. */
6307 pAhciPortTaskState = (PAHCIPORTTASKSTATE)RTMemAllocZ(sizeof(AHCIPORTTASKSTATE));
6308 if (!pAhciPortTaskState)
6309 {
6310 AssertMsgFailed(("Failed to allocate task state memory\n"));
6311 return VERR_NO_MEMORY;
6312 }
6313
6314 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
6315 {
6316 /* New run to get number of I/O requests per second?. */
6317 if (!u64StartTime)
6318 u64StartTime = RTTimeMilliTS();
6319
6320 ASMAtomicXchgBool(&pAhciPort->fAsyncIOThreadIdle, true);
6321 if (pAhci->fSignalIdle)
6322 PDMDevHlpAsyncNotificationCompleted(pAhciPort->pDevInsR3);
6323
6324 rc = RTSemEventWait(pAhciPort->AsyncIORequestSem, 1000);
6325 if (rc == VERR_TIMEOUT)
6326 {
6327 /* No I/O requests in-between. Reset statistics and wait again. */
6328 pAhciPort->StatIORequestsPerSecond.c = 0;
6329 rc = RTSemEventWait(pAhciPort->AsyncIORequestSem, RT_INDEFINITE_WAIT);
6330 }
6331
6332 if (RT_FAILURE(rc) || (pThread->enmState != PDMTHREADSTATE_RUNNING))
6333 break;
6334
6335 /* Go to sleep again if we are in redo mode. */
6336 if (RT_UNLIKELY(pAhciPort->fRedo))
6337 continue;
6338
6339 AssertMsg(pAhciPort->pDrvBase, ("I/O thread without attached device?!\n"));
6340
6341 ASMAtomicXchgBool(&pAhciPort->fAsyncIOThreadIdle, false);
6342 fTasksToProcess = ASMAtomicXchgU32(&pAhciPort->u32TasksNew, 0);
6343
6344 idx = ASMBitFirstSetU32(fTasksToProcess);
6345
6346 /* Process commands. */
6347 while ( idx
6348 && RT_LIKELY(!pAhciPort->fPortReset))
6349 {
6350 AHCITXDIR enmTxDir;
6351
6352 idx--;
6353 STAM_PROFILE_START(&pAhciPort->StatProfileProcessTime, a);
6354
6355 pAhciPortTaskState->uATARegStatus = 0;
6356 pAhciPortTaskState->uATARegError = 0;
6357 pAhciPortTaskState->uTag = idx;
6358 AssertMsg(pAhciPortTaskState->uTag < AHCI_NR_COMMAND_SLOTS, ("%s: Invalid Tag number %u!!\n", __FUNCTION__, pAhciPortTaskState->uTag));
6359
6360 /* Set current command slot */
6361 pAhciPort->regCMD |= (AHCI_PORT_CMD_CCS_SHIFT(pAhciPortTaskState->uTag));
6362
6363 /* Mark the task as processed by the HBA if this is a queued task so that it doesn't occur in the CI register anymore. */
6364 if (pAhciPort->regSACT & (1 << idx))
6365 {
6366 pAhciPortTaskState->fQueued = true;
6367 ASMAtomicOrU32(&pAhciPort->u32TasksFinished, (1 << pAhciPortTaskState->uTag));
6368 }
6369 else
6370 pAhciPortTaskState->fQueued = false;
6371
6372 ahciPortTaskGetCommandFis(pAhciPort, pAhciPortTaskState);
6373
6374 ahciLog(("%s: Got command at slot %d\n", __FUNCTION__, pAhciPortTaskState->uTag));
6375
6376 if (!(pAhciPortTaskState->cmdFis[AHCI_CMDFIS_BITS] & AHCI_CMDFIS_C))
6377 {
6378 /* If the reset bit is set put the device into reset state. */
6379 if (pAhciPortTaskState->cmdFis[AHCI_CMDFIS_CTL] & AHCI_CMDFIS_CTL_SRST)
6380 {
6381 ahciLog(("%s: Setting device into reset state\n", __FUNCTION__));
6382 pAhciPort->fResetDevice = true;
6383 ahciSendD2HFis(pAhciPort, pAhciPortTaskState, &pAhciPortTaskState->cmdFis[0], true);
6384 }
6385 else if (pAhciPort->fResetDevice) /* The bit is not set and we are in a reset state. */
6386 {
6387 ahciFinishStorageDeviceReset(pAhciPort, pAhciPortTaskState);
6388 }
6389 /* TODO: We are not in a reset state update the control registers. */
6390 }
6391 else
6392 {
6393 enmTxDir = ahciProcessCmd(pAhciPort, pAhciPortTaskState, &pAhciPortTaskState->cmdFis[0]);
6394
6395 if (enmTxDir == AHCITXDIR_FLUSH)
6396 {
6397 rc = pAhciPort->pDrvBlock->pfnFlush(pAhciPort->pDrvBlock);
6398
6399 /* Log the error. */
6400 if ( RT_FAILURE(rc)
6401 && pAhciPort->cErrors++ < MAX_LOG_REL_ERRORS)
6402 {
6403 LogRel(("AHCI#%u: Flush returned rc=%Rrc\n",
6404 pAhciPort->iLUN, rc));
6405 }
6406
6407 if (RT_FAILURE(rc))
6408 {
6409 if (!ahciIsRedoSetWarning(pAhciPort, rc))
6410 {
6411 pAhciPortTaskState->uATARegError = ID_ERR;
6412 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_ERR;
6413 }
6414 else
6415 {
6416 /* Add the task to the mask again. */
6417 ASMAtomicOrU32(&pAhciPort->u32TasksNew, (1 << pAhciPortTaskState->uTag));
6418 }
6419 }
6420 else
6421 {
6422 pAhciPortTaskState->uATARegError = 0;
6423 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
6424 }
6425
6426 if (!pAhciPort->fRedo)
6427 {
6428 if (pAhciPortTaskState->fQueued)
6429 ASMAtomicOrU32(&pAhciPort->u32QueuedTasksFinished, (1 << pAhciPortTaskState->uTag));
6430 else
6431 {
6432 /* Task is not queued send D2H FIS */
6433 ahciSendD2HFis(pAhciPort, pAhciPortTaskState, &pAhciPortTaskState->cmdFis[0], true);
6434 }
6435 }
6436 }
6437 else if (enmTxDir != AHCITXDIR_NONE)
6438 {
6439 uint64_t uOffset;
6440 size_t cbTransfer;
6441 PRTSGSEG pSegCurr;
6442 PAHCIPORTTASKSTATESGENTRY pSGInfoCurr;
6443
6444 rc = ahciScatterGatherListCreate(pAhciPort, pAhciPortTaskState, (enmTxDir == AHCITXDIR_READ) ? false : true);
6445 if (RT_FAILURE(rc))
6446 AssertMsgFailed(("%s: Failed to get number of list elments %Rrc\n", __FUNCTION__, rc));
6447
6448 STAM_REL_COUNTER_INC(&pAhciPort->StatDMA);
6449
6450 /* Initialize all values. */
6451 uOffset = pAhciPortTaskState->uOffset;
6452 cbTransfer = pAhciPortTaskState->cbTransfer;
6453 pSegCurr = &pAhciPortTaskState->pSGListHead[0];
6454 pSGInfoCurr = pAhciPortTaskState->paSGEntries;
6455
6456 STAM_PROFILE_START(&pAhciPort->StatProfileReadWrite, b);
6457
6458 while (cbTransfer)
6459 {
6460 size_t cbProcess = (cbTransfer < pSegCurr->cbSeg) ? cbTransfer : pSegCurr->cbSeg;
6461
6462 AssertMsg(!(pSegCurr->cbSeg % 512), ("Buffer is not sector aligned cbSeg=%d\n", pSegCurr->cbSeg));
6463 AssertMsg(!(uOffset % 512), ("Offset is not sector aligned %llu\n", uOffset));
6464 AssertMsg(!(cbProcess % 512), ("Number of bytes to process is not sector aligned %lu\n", cbProcess));
6465
6466 if (enmTxDir == AHCITXDIR_READ)
6467 {
6468 pAhciPort->Led.Asserted.s.fReading = pAhciPort->Led.Actual.s.fReading = 1;
6469 rc = pAhciPort->pDrvBlock->pfnRead(pAhciPort->pDrvBlock, uOffset,
6470 pSegCurr->pvSeg, cbProcess);
6471 pAhciPort->Led.Actual.s.fReading = 0;
6472 if (RT_FAILURE(rc))
6473 break;
6474
6475 STAM_REL_COUNTER_ADD(&pAhciPort->StatBytesRead, cbProcess);
6476 }
6477 else
6478 {
6479 pAhciPort->Led.Asserted.s.fWriting = pAhciPort->Led.Actual.s.fWriting = 1;
6480 rc = pAhciPort->pDrvBlock->pfnWrite(pAhciPort->pDrvBlock, uOffset,
6481 pSegCurr->pvSeg, cbProcess);
6482 pAhciPort->Led.Actual.s.fWriting = 0;
6483 if (RT_FAILURE(rc))
6484 break;
6485
6486 STAM_REL_COUNTER_ADD(&pAhciPort->StatBytesWritten, cbProcess);
6487 }
6488
6489 /* Go to the next entry. */
6490 uOffset += cbProcess;
6491 cbTransfer -= cbProcess;
6492 pSegCurr++;
6493 pSGInfoCurr++;
6494 }
6495
6496 STAM_PROFILE_STOP(&pAhciPort->StatProfileReadWrite, b);
6497
6498 /* Log the error. */
6499 if ( RT_FAILURE(rc)
6500 && pAhciPort->cErrors++ < MAX_LOG_REL_ERRORS)
6501 {
6502 LogRel(("AHCI#%u: %s at offset %llu (%u bytes left) returned rc=%Rrc\n",
6503 pAhciPort->iLUN,
6504 enmTxDir == AHCITXDIR_READ
6505 ? "Read"
6506 : "Write",
6507 uOffset, cbTransfer, rc));
6508 }
6509
6510 /* Cleanup. */
6511 int rc2 = ahciScatterGatherListDestroy(pAhciPort, pAhciPortTaskState);
6512 if (RT_FAILURE(rc2))
6513 AssertMsgFailed(("Destroying task list failed rc=%Rrc\n", rc));
6514
6515 if (RT_LIKELY(!pAhciPort->fPortReset))
6516 {
6517 pAhciPortTaskState->cmdHdr.u32PRDBC = pAhciPortTaskState->cbTransfer - cbTransfer;
6518 if (RT_FAILURE(rc))
6519 {
6520 if (!ahciIsRedoSetWarning(pAhciPort, rc))
6521 {
6522 pAhciPortTaskState->uATARegError = ID_ERR;
6523 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_ERR;
6524 }
6525 else
6526 {
6527 /* Add the task to the mask again. */
6528 ASMAtomicOrU32(&pAhciPort->u32TasksNew, (1 << pAhciPortTaskState->uTag));
6529 }
6530 }
6531 else
6532 {
6533 pAhciPortTaskState->uATARegError = 0;
6534 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
6535 }
6536
6537 if (!pAhciPort->fRedo)
6538 {
6539 /* Write updated command header into memory of the guest. */
6540 PDMDevHlpPhysWrite(pAhciPort->CTX_SUFF(pDevIns), pAhciPortTaskState->GCPhysCmdHdrAddr,
6541 &pAhciPortTaskState->cmdHdr, sizeof(CmdHdr));
6542
6543 if (pAhciPortTaskState->fQueued)
6544 ASMAtomicOrU32(&pAhciPort->u32QueuedTasksFinished, (1 << pAhciPortTaskState->uTag));
6545 else
6546 {
6547 /* Task is not queued send D2H FIS */
6548 ahciSendD2HFis(pAhciPort, pAhciPortTaskState, &pAhciPortTaskState->cmdFis[0], true);
6549 }
6550
6551 uIORequestsProcessed++;
6552 }
6553 }
6554 }
6555 else
6556 {
6557 /* Nothing left to do. Notify the guest. */
6558 ahciSendD2HFis(pAhciPort, pAhciPortTaskState, &pAhciPortTaskState->cmdFis[0], true);
6559 }
6560
6561 STAM_PROFILE_STOP(&pAhciPort->StatProfileProcessTime, a);
6562 }
6563
6564 if (!pAhciPort->fRedo)
6565 {
6566#ifdef DEBUG
6567 /* Be paranoid. */
6568 memset(&pAhciPortTaskState->cmdHdr, 0, sizeof(CmdHdr));
6569 memset(&pAhciPortTaskState->cmdFis, 0, AHCI_CMDFIS_TYPE_H2D_SIZE);
6570 pAhciPortTaskState->GCPhysCmdHdrAddr = 0;
6571 pAhciPortTaskState->uOffset = 0;
6572 pAhciPortTaskState->cbTransfer = 0;
6573#endif
6574
6575 /* If we encountered an error notify the guest and continue with the next task. */
6576 if (RT_FAILURE(rc))
6577 {
6578 if ( ASMAtomicReadU32(&pAhciPort->u32QueuedTasksFinished) != 0
6579 && RT_LIKELY(!pAhciPort->fPortReset))
6580 ahciSendSDBFis(pAhciPort, 0, true);
6581 }
6582 }
6583 fTasksToProcess &= ~(1 << idx);
6584 idx = ASMBitFirstSetU32(fTasksToProcess);
6585 } /* while tasks to process */
6586
6587 if ( ASMAtomicReadU32(&pAhciPort->u32QueuedTasksFinished) != 0
6588 && RT_LIKELY(!pAhciPort->fPortReset)
6589 && RT_LIKELY(!pAhciPort->fRedo))
6590 ahciSendSDBFis(pAhciPort, 0, true);
6591
6592 u64StopTime = RTTimeMilliTS();
6593 /* Check if one second has passed. */
6594 if (u64StopTime - u64StartTime >= 1000)
6595 {
6596 /* Calculate number of I/O requests per second. */
6597 uIOsPerSec = uIORequestsProcessed / ((u64StopTime - u64StartTime) / 1000);
6598 ahciLog(("%s: Processed %u requests in %llu ms -> %u requests/s\n", __FUNCTION__, uIORequestsProcessed, u64StopTime - u64StartTime, uIOsPerSec));
6599 u64StartTime = 0;
6600 uIORequestsProcessed = 0;
6601 /* For the release statistics. There is no macro to set the counter to a specific value. */
6602 pAhciPort->StatIORequestsPerSecond.c = uIOsPerSec;
6603 }
6604 } /* While running */
6605
6606 if (pAhci->fSignalIdle)
6607 PDMDevHlpAsyncNotificationCompleted(pAhciPort->pDevInsR3);
6608
6609 /* Free task state memory */
6610 if (pAhciPortTaskState->pSGListHead)
6611 RTMemFree(pAhciPortTaskState->pSGListHead);
6612 if (pAhciPortTaskState->paSGEntries)
6613 RTMemFree(pAhciPortTaskState->paSGEntries);
6614 if (pAhciPortTaskState->pvBufferUnaligned)
6615 RTMemPageFree(pAhciPortTaskState->pvBufferUnaligned, pAhciPortTaskState->cbBufferUnaligned);
6616 RTMemFree(pAhciPortTaskState);
6617
6618 ahciLog(("%s: Port %d async IO thread exiting\n", __FUNCTION__, pAhciPort->iLUN));
6619 return VINF_SUCCESS;
6620}
6621
6622/**
6623 * Unblock the async I/O thread so it can respond to a state change.
6624 *
6625 * @returns VBox status code.
6626 * @param pDevIns The pcnet device instance.
6627 * @param pThread The send thread.
6628 */
6629static DECLCALLBACK(int) ahciAsyncIOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
6630{
6631 PAHCIPort pAhciPort = (PAHCIPort)pThread->pvUser;
6632 return RTSemEventSignal(pAhciPort->AsyncIORequestSem);
6633}
6634
6635/* -=-=-=-=- DBGF -=-=-=-=- */
6636
6637/**
6638 * LsiLogic status info callback.
6639 *
6640 * @param pDevIns The device instance.
6641 * @param pHlp The output helpers.
6642 * @param pszArgs The arguments.
6643 */
6644static DECLCALLBACK(void) ahciR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6645{
6646 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
6647
6648 /*
6649 * Show info.
6650 */
6651 pHlp->pfnPrintf(pHlp,
6652 "%s#%d: mmio=%RGp ports=%u GC=%RTbool R0=%RTbool\n",
6653 pDevIns->pReg->szName,
6654 pDevIns->iInstance,
6655 pThis->MMIOBase,
6656 pThis->cPortsImpl,
6657 pThis->fGCEnabled ? true : false,
6658 pThis->fR0Enabled ? true : false);
6659
6660 /*
6661 * Show global registers.
6662 */
6663 pHlp->pfnPrintf(pHlp, "HbaCap=%#x\n", pThis->regHbaCap);
6664 pHlp->pfnPrintf(pHlp, "HbaCtrl=%#x\n", pThis->regHbaCtrl);
6665 pHlp->pfnPrintf(pHlp, "HbaIs=%#x\n", pThis->regHbaIs);
6666 pHlp->pfnPrintf(pHlp, "HbaPi=%#x", pThis->regHbaPi);
6667 pHlp->pfnPrintf(pHlp, "HbaVs=%#x\n", pThis->regHbaVs);
6668 pHlp->pfnPrintf(pHlp, "HbaCccCtl=%#x\n", pThis->regHbaCccCtl);
6669 pHlp->pfnPrintf(pHlp, "HbaCccPorts=%#x\n", pThis->regHbaCccPorts);
6670 pHlp->pfnPrintf(pHlp, "PortsInterrupted=%#x\n", pThis->u32PortsInterrupted);
6671
6672 /*
6673 * Per port data.
6674 */
6675 for (unsigned i = 0; i < pThis->cPortsImpl; i++)
6676 {
6677 PAHCIPort pThisPort = &pThis->ahciPort[i];
6678
6679 pHlp->pfnPrintf(pHlp, "Port %d: async=%RTbool device-attached=%RTbool\n",
6680 pThisPort->iLUN, pThisPort->fAsyncInterface, pThisPort->pDrvBase != NULL);
6681 pHlp->pfnPrintf(pHlp, "PortClb=%#x\n", pThisPort->regCLB);
6682 pHlp->pfnPrintf(pHlp, "PortClbU=%#x\n", pThisPort->regCLBU);
6683 pHlp->pfnPrintf(pHlp, "PortFb=%#x\n", pThisPort->regFB);
6684 pHlp->pfnPrintf(pHlp, "PortFbU=%#x\n", pThisPort->regFBU);
6685 pHlp->pfnPrintf(pHlp, "PortIs=%#x\n", pThisPort->regIS);
6686 pHlp->pfnPrintf(pHlp, "PortIe=%#x\n", pThisPort->regIE);
6687 pHlp->pfnPrintf(pHlp, "PortCmd=%#x\n", pThisPort->regCMD);
6688 pHlp->pfnPrintf(pHlp, "PortTfd=%#x\n", pThisPort->regTFD);
6689 pHlp->pfnPrintf(pHlp, "PortSig=%#x\n", pThisPort->regSIG);
6690 pHlp->pfnPrintf(pHlp, "PortSSts=%#x\n", pThisPort->regSSTS);
6691 pHlp->pfnPrintf(pHlp, "PortSCtl=%#x\n", pThisPort->regSCTL);
6692 pHlp->pfnPrintf(pHlp, "PortSErr=%#x\n", pThisPort->regSERR);
6693 pHlp->pfnPrintf(pHlp, "PortSAct=%#x\n", pThisPort->regSACT);
6694 pHlp->pfnPrintf(pHlp, "PortCi=%#x\n", pThisPort->regCI);
6695 pHlp->pfnPrintf(pHlp, "PortPhysClb=%RGp\n", pThisPort->GCPhysAddrClb);
6696 pHlp->pfnPrintf(pHlp, "PortPhysFb=%RGp\n", pThisPort->GCPhysAddrFb);
6697 pHlp->pfnPrintf(pHlp, "PortActTasksActive=%u\n", pThisPort->cTasksActive);
6698 pHlp->pfnPrintf(pHlp, "PortPoweredOn=%RTbool\n", pThisPort->fPoweredOn);
6699 pHlp->pfnPrintf(pHlp, "PortSpunUp=%RTbool\n", pThisPort->fSpunUp);
6700 pHlp->pfnPrintf(pHlp, "PortFirstD2HFisSend=%RTbool\n", pThisPort->fFirstD2HFisSend);
6701 pHlp->pfnPrintf(pHlp, "PortATAPI=%RTbool\n", pThisPort->fATAPI);
6702 pHlp->pfnPrintf(pHlp, "PortTasksFinished=%#x\n", pThisPort->u32TasksFinished);
6703 pHlp->pfnPrintf(pHlp, "PortQueuedTasksFinished=%#x\n", pThisPort->u32QueuedTasksFinished);
6704 pHlp->pfnPrintf(pHlp, "PortAsyncIoThreadIdle=%RTbool\n", pThisPort->fAsyncIOThreadIdle);
6705 pHlp->pfnPrintf(pHlp, "\n");
6706 }
6707}
6708
6709/* -=-=-=-=- Helper -=-=-=-=- */
6710
6711/**
6712 * Checks if all asynchronous I/O is finished, both AHCI and IDE.
6713 *
6714 * Used by ahciR3Reset, ahciR3Suspend and ahciR3PowerOff. ahciR3SavePrep makes
6715 * use of it in strict builds (which is why it's up here).
6716 *
6717 * @returns true if quiesced, false if busy.
6718 * @param pDevIns The device instance.
6719 */
6720static bool ahciR3AllAsyncIOIsFinished(PPDMDEVINS pDevIns)
6721{
6722 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
6723
6724 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->ahciPort); i++)
6725 {
6726 PAHCIPort pThisPort = &pThis->ahciPort[i];
6727 if (pThisPort->pDrvBase)
6728 {
6729 bool fFinished;
6730 if (pThisPort->fAsyncInterface)
6731 fFinished = (pThisPort->cTasksActive == 0);
6732 else
6733 fFinished = ((pThisPort->cTasksActive == 0) && (pThisPort->fAsyncIOThreadIdle));
6734 if (!fFinished)
6735 return false;
6736 }
6737 }
6738
6739 if (pThis->fBootable)
6740 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
6741 if (!ataControllerIsIdle(&pThis->aCts[i]))
6742 return false;
6743
6744 return true;
6745}
6746
6747/* -=-=-=-=- Saved State -=-=-=-=- */
6748
6749/**
6750 * @copydoc FNDEVSSMSAVEPREP
6751 */
6752static DECLCALLBACK(int) ahciR3SavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6753{
6754 Assert(ahciR3AllAsyncIOIsFinished(pDevIns));
6755 return VINF_SUCCESS;
6756}
6757
6758/**
6759 * @copydoc FNDEVSSMLOADPREP
6760 */
6761static DECLCALLBACK(int) ahciR3LoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6762{
6763 Assert(ahciR3AllAsyncIOIsFinished(pDevIns));
6764 return VINF_SUCCESS;
6765}
6766
6767/**
6768 * @copydoc FNDEVSSMLIVEEXEC
6769 */
6770static DECLCALLBACK(int) ahciR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
6771{
6772 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
6773
6774 /* config. */
6775 SSMR3PutU32(pSSM, pThis->cPortsImpl);
6776 for (uint32_t i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
6777 {
6778 SSMR3PutBool(pSSM, pThis->ahciPort[i].pDrvBase != NULL);
6779 SSMR3PutStrZ(pSSM, pThis->ahciPort[i].szSerialNumber);
6780 SSMR3PutStrZ(pSSM, pThis->ahciPort[i].szFirmwareRevision);
6781 SSMR3PutStrZ(pSSM, pThis->ahciPort[i].szModelNumber);
6782 }
6783
6784 static const char *s_apszIdeEmuPortNames[4] = { "PrimaryMaster", "PrimarySlave", "SecondaryMaster", "SecondarySlave" };
6785 for (size_t i = 0; i < RT_ELEMENTS(s_apszIdeEmuPortNames); i++)
6786 {
6787 uint32_t iPort;
6788 int rc = CFGMR3QueryU32Def(pDevIns->pCfg, s_apszIdeEmuPortNames[i], &iPort, i);
6789 AssertRCReturn(rc, rc);
6790 SSMR3PutU32(pSSM, iPort);
6791 }
6792
6793 return VINF_SSM_DONT_CALL_AGAIN;
6794}
6795
6796/**
6797 * @copydoc FNDEVSSMSAVEEXEC
6798 */
6799static DECLCALLBACK(int) ahciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6800{
6801 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
6802 uint32_t i;
6803 int rc;
6804
6805 Assert(!pThis->f8ByteMMIO4BytesWrittenSuccessfully);
6806
6807 /* The config */
6808 rc = ahciR3LiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
6809 AssertRCReturn(rc, rc);
6810
6811 /* The main device structure. */
6812 SSMR3PutU32(pSSM, pThis->regHbaCap);
6813 SSMR3PutU32(pSSM, pThis->regHbaCtrl);
6814 SSMR3PutU32(pSSM, pThis->regHbaIs);
6815 SSMR3PutU32(pSSM, pThis->regHbaPi);
6816 SSMR3PutU32(pSSM, pThis->regHbaVs);
6817 SSMR3PutU32(pSSM, pThis->regHbaCccCtl);
6818 SSMR3PutU32(pSSM, pThis->regHbaCccPorts);
6819 SSMR3PutU8(pSSM, pThis->uCccPortNr);
6820 SSMR3PutU64(pSSM, pThis->uCccTimeout);
6821 SSMR3PutU32(pSSM, pThis->uCccNr);
6822 SSMR3PutU32(pSSM, pThis->uCccCurrentNr);
6823 SSMR3PutU32(pSSM, pThis->u32PortsInterrupted);
6824 SSMR3PutBool(pSSM, pThis->fReset);
6825 SSMR3PutBool(pSSM, pThis->f64BitAddr);
6826 SSMR3PutBool(pSSM, pThis->fR0Enabled);
6827 SSMR3PutBool(pSSM, pThis->fGCEnabled);
6828
6829 /* Now every port. */
6830 for (i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
6831 {
6832 Assert(pThis->ahciPort[i].cTasksActive == 0);
6833 SSMR3PutU32(pSSM, pThis->ahciPort[i].regCLB);
6834 SSMR3PutU32(pSSM, pThis->ahciPort[i].regCLBU);
6835 SSMR3PutU32(pSSM, pThis->ahciPort[i].regFB);
6836 SSMR3PutU32(pSSM, pThis->ahciPort[i].regFBU);
6837 SSMR3PutGCPhys(pSSM, pThis->ahciPort[i].GCPhysAddrClb);
6838 SSMR3PutGCPhys(pSSM, pThis->ahciPort[i].GCPhysAddrFb);
6839 SSMR3PutU32(pSSM, pThis->ahciPort[i].regIS);
6840 SSMR3PutU32(pSSM, pThis->ahciPort[i].regIE);
6841 SSMR3PutU32(pSSM, pThis->ahciPort[i].regCMD);
6842 SSMR3PutU32(pSSM, pThis->ahciPort[i].regTFD);
6843 SSMR3PutU32(pSSM, pThis->ahciPort[i].regSIG);
6844 SSMR3PutU32(pSSM, pThis->ahciPort[i].regSSTS);
6845 SSMR3PutU32(pSSM, pThis->ahciPort[i].regSCTL);
6846 SSMR3PutU32(pSSM, pThis->ahciPort[i].regSERR);
6847 SSMR3PutU32(pSSM, pThis->ahciPort[i].regSACT);
6848 SSMR3PutU32(pSSM, pThis->ahciPort[i].regCI);
6849 SSMR3PutU32(pSSM, pThis->ahciPort[i].PCHSGeometry.cCylinders);
6850 SSMR3PutU32(pSSM, pThis->ahciPort[i].PCHSGeometry.cHeads);
6851 SSMR3PutU32(pSSM, pThis->ahciPort[i].PCHSGeometry.cSectors);
6852 SSMR3PutU64(pSSM, pThis->ahciPort[i].cTotalSectors);
6853 SSMR3PutU32(pSSM, pThis->ahciPort[i].cMultSectors);
6854 SSMR3PutU8(pSSM, pThis->ahciPort[i].uATATransferMode);
6855 SSMR3PutBool(pSSM, pThis->ahciPort[i].fResetDevice);
6856
6857 /* No need to save but to avoid changing the SSM format they are still written. */
6858 SSMR3PutU8(pSSM, 0); /* Prev: Write position in the FIFO. */
6859 SSMR3PutU8(pSSM, 0); /* Prev: Read position in the FIFO. */
6860
6861 SSMR3PutBool(pSSM, pThis->ahciPort[i].fPoweredOn);
6862 SSMR3PutBool(pSSM, pThis->ahciPort[i].fSpunUp);
6863 SSMR3PutU32(pSSM, pThis->ahciPort[i].u32TasksFinished);
6864 SSMR3PutU32(pSSM, pThis->ahciPort[i].u32QueuedTasksFinished);
6865
6866 /* ATAPI saved state. */
6867 SSMR3PutBool(pSSM, pThis->ahciPort[i].fATAPI);
6868 SSMR3PutMem(pSSM, &pThis->ahciPort[i].abATAPISense[0], sizeof(pThis->ahciPort[i].abATAPISense));
6869 SSMR3PutU8(pSSM, pThis->ahciPort[i].cNotifiedMediaChange);
6870 SSMR3PutU32(pSSM, pThis->ahciPort[i].MediaEventStatus);
6871 }
6872
6873 /* Now the emulated ata controllers. */
6874 for (i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
6875 {
6876 rc = ataControllerSaveExec(&pThis->aCts[i], pSSM);
6877 if (RT_FAILURE(rc))
6878 return rc;
6879 }
6880
6881 return SSMR3PutU32(pSSM, UINT32_MAX); /* sanity/terminator */
6882}
6883
6884/**
6885 * Loads a saved AHCI device state.
6886 *
6887 * @returns VBox status code.
6888 * @param pDevIns The device instance.
6889 * @param pSSM The handle to the saved state.
6890 * @param uVersion The data unit version number.
6891 * @param uPass The data pass.
6892 */
6893static DECLCALLBACK(int) ahciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
6894{
6895 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
6896 uint32_t u32;
6897 int rc;
6898
6899 if ( uVersion != AHCI_SAVED_STATE_VERSION
6900 && uVersion != AHCI_SAVED_STATE_VERSION_PRE_ATAPI
6901 && uVersion != AHCI_SAVED_STATE_VERSION_VBOX_30)
6902 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
6903
6904 /* Verify config. */
6905 if (uVersion > AHCI_SAVED_STATE_VERSION_VBOX_30)
6906 {
6907 rc = SSMR3GetU32(pSSM, &u32);
6908 AssertRCReturn(rc, rc);
6909 if (u32 != pThis->cPortsImpl)
6910 {
6911 LogRel(("AHCI: Config mismatch: cPortsImpl - saved=%u config=%u\n", u32, pThis->cPortsImpl));
6912 if ( u32 < pThis->cPortsImpl
6913 || u32 > AHCI_MAX_NR_PORTS_IMPL)
6914 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: cPortsImpl - saved=%u config=%u"),
6915 u32, pThis->cPortsImpl);
6916 }
6917
6918 for (uint32_t i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
6919 {
6920 bool fInUse;
6921 rc = SSMR3GetBool(pSSM, &fInUse);
6922 AssertRCReturn(rc, rc);
6923 if (fInUse != (pThis->ahciPort[i].pDrvBase != NULL))
6924 return SSMR3SetCfgError(pSSM, RT_SRC_POS,
6925 N_("The %s VM is missing a device on port %u. Please make sure the source and target VMs have compatible storage configurations"),
6926 fInUse ? "target" : "source", i );
6927
6928 char szSerialNumber[AHCI_SERIAL_NUMBER_LENGTH+1];
6929 rc = SSMR3GetStrZ(pSSM, szSerialNumber, sizeof(szSerialNumber));
6930 AssertRCReturn(rc, rc);
6931 if (strcmp(szSerialNumber, pThis->ahciPort[i].szSerialNumber))
6932 LogRel(("AHCI: Port %u config mismatch: Serial number - saved='%s' config='%s'\n",
6933 i, szSerialNumber, pThis->ahciPort[i].szSerialNumber));
6934
6935 char szFirmwareRevision[AHCI_FIRMWARE_REVISION_LENGTH+1];
6936 rc = SSMR3GetStrZ(pSSM, szFirmwareRevision, sizeof(szFirmwareRevision));
6937 AssertRCReturn(rc, rc);
6938 if (strcmp(szFirmwareRevision, pThis->ahciPort[i].szFirmwareRevision))
6939 LogRel(("AHCI: Port %u config mismatch: Firmware revision - saved='%s' config='%s'\n",
6940 i, szFirmwareRevision, pThis->ahciPort[i].szFirmwareRevision));
6941
6942 char szModelNumber[AHCI_MODEL_NUMBER_LENGTH+1];
6943 rc = SSMR3GetStrZ(pSSM, szModelNumber, sizeof(szModelNumber));
6944 AssertRCReturn(rc, rc);
6945 if (strcmp(szModelNumber, pThis->ahciPort[i].szModelNumber))
6946 LogRel(("AHCI: Port %u config mismatch: Model number - saved='%s' config='%s'\n",
6947 i, szModelNumber, pThis->ahciPort[i].szModelNumber));
6948 }
6949
6950 static const char *s_apszIdeEmuPortNames[4] = { "PrimaryMaster", "PrimarySlave", "SecondaryMaster", "SecondarySlave" };
6951 for (size_t i = 0; i < RT_ELEMENTS(s_apszIdeEmuPortNames); i++)
6952 {
6953 uint32_t iPort;
6954 rc = CFGMR3QueryU32Def(pDevIns->pCfg, s_apszIdeEmuPortNames[i], &iPort, i);
6955 AssertRCReturn(rc, rc);
6956
6957 uint32_t iPortSaved;
6958 rc = SSMR3GetU32(pSSM, &iPortSaved);
6959 AssertRCReturn(rc, rc);
6960
6961 if (iPortSaved != iPort)
6962 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("IDE %s config mismatch: saved=%u config=%u"),
6963 s_apszIdeEmuPortNames[i], iPortSaved, iPort);
6964 }
6965 }
6966
6967 if (uPass == SSM_PASS_FINAL)
6968 {
6969 /* Restore data. */
6970
6971 /* The main device structure. */
6972 SSMR3GetU32(pSSM, &pThis->regHbaCap);
6973 SSMR3GetU32(pSSM, &pThis->regHbaCtrl);
6974 SSMR3GetU32(pSSM, &pThis->regHbaIs);
6975 SSMR3GetU32(pSSM, &pThis->regHbaPi);
6976 SSMR3GetU32(pSSM, &pThis->regHbaVs);
6977 SSMR3GetU32(pSSM, &pThis->regHbaCccCtl);
6978 SSMR3GetU32(pSSM, &pThis->regHbaCccPorts);
6979 SSMR3GetU8(pSSM, &pThis->uCccPortNr);
6980 SSMR3GetU64(pSSM, &pThis->uCccTimeout);
6981 SSMR3GetU32(pSSM, &pThis->uCccNr);
6982 SSMR3GetU32(pSSM, &pThis->uCccCurrentNr);
6983
6984 SSMR3GetU32(pSSM, (uint32_t *)&pThis->u32PortsInterrupted);
6985 SSMR3GetBool(pSSM, &pThis->fReset);
6986 SSMR3GetBool(pSSM, &pThis->f64BitAddr);
6987 SSMR3GetBool(pSSM, &pThis->fR0Enabled);
6988 SSMR3GetBool(pSSM, &pThis->fGCEnabled);
6989
6990 /* Now every port. */
6991 for (uint32_t i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
6992 {
6993 uint8_t u8;
6994 PAHCIPort pAhciPort = &pThis->ahciPort[i];
6995
6996 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regCLB);
6997 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regCLBU);
6998 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regFB);
6999 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regFBU);
7000 SSMR3GetGCPhys(pSSM, (RTGCPHYS *)&pThis->ahciPort[i].GCPhysAddrClb);
7001 SSMR3GetGCPhys(pSSM, (RTGCPHYS *)&pThis->ahciPort[i].GCPhysAddrFb);
7002 SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].regIS);
7003 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regIE);
7004 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regCMD);
7005 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regTFD);
7006 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regSIG);
7007 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regSSTS);
7008 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regSCTL);
7009 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regSERR);
7010 SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].regSACT);
7011 SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].regCI);
7012 SSMR3GetU32(pSSM, &pThis->ahciPort[i].PCHSGeometry.cCylinders);
7013 SSMR3GetU32(pSSM, &pThis->ahciPort[i].PCHSGeometry.cHeads);
7014 SSMR3GetU32(pSSM, &pThis->ahciPort[i].PCHSGeometry.cSectors);
7015 SSMR3GetU64(pSSM, &pThis->ahciPort[i].cTotalSectors);
7016 SSMR3GetU32(pSSM, &pThis->ahciPort[i].cMultSectors);
7017 SSMR3GetU8(pSSM, &pThis->ahciPort[i].uATATransferMode);
7018 SSMR3GetBool(pSSM, &pThis->ahciPort[i].fResetDevice);
7019
7020 if (uVersion <= AHCI_SAVED_STATE_VERSION_VBOX_30)
7021 SSMR3Skip(pSSM, AHCI_NR_COMMAND_SLOTS * sizeof(uint8_t)); /* no active data here */
7022
7023 SSMR3GetU8(pSSM, &u8);
7024 SSMR3GetU8(pSSM, &u8);
7025 SSMR3GetBool(pSSM, &pThis->ahciPort[i].fPoweredOn);
7026 SSMR3GetBool(pSSM, &pThis->ahciPort[i].fSpunUp);
7027 SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].u32TasksFinished);
7028 SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].u32QueuedTasksFinished);
7029
7030 if (uVersion > AHCI_SAVED_STATE_VERSION_PRE_ATAPI)
7031 {
7032 SSMR3GetBool(pSSM, &pThis->ahciPort[i].fATAPI);
7033 SSMR3GetMem(pSSM, pThis->ahciPort[i].abATAPISense, sizeof(pThis->ahciPort[i].abATAPISense));
7034 SSMR3GetU8(pSSM, &pThis->ahciPort[i].cNotifiedMediaChange);
7035 SSMR3GetU32(pSSM, (uint32_t*)&pThis->ahciPort[i].MediaEventStatus);
7036 }
7037 else if (pThis->ahciPort[i].fATAPI)
7038 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: atapi - saved=%false config=true"));
7039
7040 /* Check if we have tasks pending. */
7041 uint32_t fTasksOutstanding = pAhciPort->regCI & ~pAhciPort->u32TasksFinished;
7042 uint32_t fQueuedTasksOutstanding = pAhciPort->regSACT & ~pAhciPort->u32QueuedTasksFinished;
7043
7044 pAhciPort->u32TasksNew = fTasksOutstanding | fQueuedTasksOutstanding;
7045
7046 if (pAhciPort->u32TasksNew)
7047 {
7048 /*
7049 * There are tasks pending. The VM was saved after a task failed
7050 * because of non-fatal error. Set the redo flag.
7051 */
7052 pAhciPort->fRedo = true;
7053 }
7054 }
7055
7056 /* Now the emulated ata controllers. */
7057 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
7058 {
7059 rc = ataControllerLoadExec(&pThis->aCts[i], pSSM);
7060 if (RT_FAILURE(rc))
7061 return rc;
7062 }
7063
7064 rc = SSMR3GetU32(pSSM, &u32);
7065 if (RT_FAILURE(rc))
7066 return rc;
7067 AssertMsgReturn(u32 == UINT32_MAX, ("%#x\n", u32), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
7068 }
7069
7070 return VINF_SUCCESS;
7071}
7072
7073/* -=-=-=-=- device PDM interface -=-=-=-=- */
7074
7075static DECLCALLBACK(void) ahciR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
7076{
7077 uint32_t i;
7078 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
7079
7080 pAhci->pDevInsRC += offDelta;
7081 pAhci->pHbaCccTimerRC = TMTimerRCPtr(pAhci->pHbaCccTimerR3);
7082 pAhci->pNotifierQueueRC = PDMQueueRCPtr(pAhci->pNotifierQueueR3);
7083
7084 /* Relocate every port. */
7085 for (i = 0; i < RT_ELEMENTS(pAhci->ahciPort); i++)
7086 {
7087 PAHCIPort pAhciPort = &pAhci->ahciPort[i];
7088 pAhciPort->pAhciRC += offDelta;
7089 pAhciPort->pDevInsRC += offDelta;
7090 }
7091
7092 /* Relocate emulated ATA controllers. */
7093 for (i = 0; i < RT_ELEMENTS(pAhci->aCts); i++)
7094 ataControllerRelocate(&pAhci->aCts[i], offDelta);
7095}
7096
7097/**
7098 * Destroy a driver instance.
7099 *
7100 * Most VM resources are freed by the VM. This callback is provided so that any non-VM
7101 * resources can be freed correctly.
7102 *
7103 * @param pDevIns The device instance data.
7104 */
7105static DECLCALLBACK(int) ahciR3Destruct(PPDMDEVINS pDevIns)
7106{
7107 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
7108 int rc = VINF_SUCCESS;
7109 unsigned iActPort = 0;
7110 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
7111
7112 /*
7113 * At this point the async I/O thread is suspended and will not enter
7114 * this module again. So, no coordination is needed here and PDM
7115 * will take care of terminating and cleaning up the thread.
7116 */
7117 if (PDMCritSectIsInitialized(&pAhci->lock))
7118 {
7119 TMR3TimerDestroy(pAhci->CTX_SUFF(pHbaCccTimer));
7120
7121 Log(("%s: Destruct every port\n", __FUNCTION__));
7122 for (iActPort = 0; iActPort < pAhci->cPortsImpl; iActPort++)
7123 {
7124 PAHCIPort pAhciPort = &pAhci->ahciPort[iActPort];
7125
7126 if (pAhciPort->pAsyncIOThread)
7127 {
7128 /* Destroy the event semaphore. */
7129 rc = RTSemEventDestroy(pAhciPort->AsyncIORequestSem);
7130 if (RT_FAILURE(rc))
7131 {
7132 Log(("%s: Destroying event semaphore for port %d failed rc=%Rrc\n", __FUNCTION__, iActPort, rc));
7133 }
7134 }
7135
7136 /* Free all cached tasks. */
7137 for (uint32_t i = 0; i < AHCI_NR_COMMAND_SLOTS; i++)
7138 {
7139 if (pAhciPort->aCachedTasks[i])
7140 {
7141 if (pAhciPort->aCachedTasks[i]->pSGListHead)
7142 RTMemFree(pAhciPort->aCachedTasks[i]->pSGListHead);
7143 if (pAhciPort->aCachedTasks[i]->paSGEntries)
7144 RTMemFree(pAhciPort->aCachedTasks[i]->paSGEntries);
7145
7146 RTMemFree(pAhciPort->aCachedTasks[i]);
7147 }
7148 }
7149 }
7150
7151 /* Destroy emulated ATA controllers. */
7152 for (unsigned i = 0; i < RT_ELEMENTS(pAhci->aCts); i++)
7153 ataControllerDestroy(&pAhci->aCts[i]);
7154
7155 PDMR3CritSectDelete(&pAhci->lock);
7156 }
7157
7158 return rc;
7159}
7160
7161/**
7162 * SCSI_GET_EVENT_STATUS_NOTIFICATION should return "medium removed" event
7163 * from now on, regardless if there was a medium inserted or not.
7164 */
7165static void ahciMediumRemoved(PAHCIPort pAhciPort)
7166{
7167 ASMAtomicWriteU32(&pAhciPort->MediaEventStatus, ATA_EVENT_STATUS_MEDIA_REMOVED);
7168}
7169
7170
7171/**
7172 * SCSI_GET_EVENT_STATUS_NOTIFICATION should return "medium inserted". If
7173 * there was already a medium inserted, don't forget to send the "medium
7174 * removed" event first.
7175 */
7176static void ahciMediumInserted(PAHCIPort pAhciPort)
7177{
7178 uint32_t OldStatus, NewStatus;
7179 do
7180 {
7181 OldStatus = ASMAtomicReadU32(&pAhciPort->MediaEventStatus);
7182 switch (OldStatus)
7183 {
7184 case ATA_EVENT_STATUS_MEDIA_CHANGED:
7185 case ATA_EVENT_STATUS_MEDIA_REMOVED:
7186 /* no change, we will send "medium removed" + "medium inserted" */
7187 NewStatus = ATA_EVENT_STATUS_MEDIA_CHANGED;
7188 break;
7189 default:
7190 NewStatus = ATA_EVENT_STATUS_MEDIA_NEW;
7191 break;
7192 }
7193 } while (!ASMAtomicCmpXchgU32(&pAhciPort->MediaEventStatus, NewStatus, OldStatus));
7194}
7195
7196/**
7197 * Called when a media is mounted.
7198 *
7199 * @param pInterface Pointer to the interface structure containing the called function pointer.
7200 */
7201static DECLCALLBACK(void) ahciMountNotify(PPDMIMOUNTNOTIFY pInterface)
7202{
7203 PAHCIPort pAhciPort = PDMIMOUNTNOTIFY_2_PAHCIPORT(pInterface);
7204 Log(("%s: changing LUN#%d\n", __FUNCTION__, pAhciPort->iLUN));
7205
7206 /* Ignore the call if we're called while being attached. */
7207 if (!pAhciPort->pDrvBlock)
7208 return;
7209
7210 if (pAhciPort->fATAPI)
7211 {
7212 pAhciPort->cTotalSectors = pAhciPort->pDrvBlock->pfnGetSize(pAhciPort->pDrvBlock) / 2048;
7213
7214 LogRel(("AHCI: LUN#%d: CD/DVD, total number of sectors %Ld, passthrough unchanged\n", pAhciPort->iLUN, pAhciPort->cTotalSectors));
7215
7216 /* Report media changed in TEST UNIT and other (probably incorrect) places. */
7217 if (pAhciPort->cNotifiedMediaChange < 2)
7218 pAhciPort->cNotifiedMediaChange = 2;
7219 ahciMediumInserted(pAhciPort);
7220 ataMediumTypeSet(pAhciPort, ATA_MEDIA_TYPE_UNKNOWN);
7221 }
7222 else
7223 {
7224 pAhciPort->cTotalSectors = pAhciPort->pDrvBlock->pfnGetSize(pAhciPort->pDrvBlock) / 512;
7225
7226 /*
7227 * Initialize registers
7228 */
7229 pAhciPort->regCMD |= AHCI_PORT_CMD_CPS;
7230 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_CPDS | AHCI_PORT_IS_PRCS);
7231 pAhciPort->regSERR |= AHCI_PORT_SERR_N;
7232 if (pAhciPort->regIE & AHCI_PORT_IE_CPDE)
7233 {
7234 int rc = ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN, VERR_IGNORED);
7235 AssertRC(rc);
7236 }
7237 }
7238}
7239
7240/**
7241 * Called when a media is unmounted
7242 * @param pInterface Pointer to the interface structure containing the called function pointer.
7243 */
7244static DECLCALLBACK(void) ahciUnmountNotify(PPDMIMOUNTNOTIFY pInterface)
7245{
7246 PAHCIPort pAhciPort = PDMIMOUNTNOTIFY_2_PAHCIPORT(pInterface);
7247 Log(("%s:\n", __FUNCTION__));
7248
7249 pAhciPort->cTotalSectors = 0;
7250
7251 if (pAhciPort->fATAPI)
7252 {
7253 /*
7254 * Whatever I do, XP will not use the GET MEDIA STATUS nor the EVENT stuff.
7255 * However, it will respond to TEST UNIT with a 0x6 0x28 (media changed) sense code.
7256 * So, we'll give it 4 TEST UNIT command to catch up, two which the media is not
7257 * present and 2 in which it is changed.
7258 */
7259 pAhciPort->cNotifiedMediaChange = 4;
7260 ahciMediumRemoved(pAhciPort);
7261 ataMediumTypeSet(pAhciPort, ATA_MEDIA_TYPE_UNKNOWN);
7262 }
7263 else
7264 {
7265 /*
7266 * Inform the guest about the removed device.
7267 */
7268 pAhciPort->regSSTS = 0;
7269 pAhciPort->regCMD &= ~AHCI_PORT_CMD_CPS;
7270 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_CPDS | AHCI_PORT_IS_PRCS);
7271 pAhciPort->regSERR |= AHCI_PORT_SERR_N;
7272 if (pAhciPort->regIE & AHCI_PORT_IE_CPDE)
7273 {
7274 int rc = ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN, VERR_IGNORED);
7275 AssertRC(rc);
7276 }
7277 }
7278}
7279
7280/**
7281 * Configure the attached device for a port.
7282 *
7283 * Used by ahciR3Construct and ahciR3Attach.
7284 *
7285 * @returns VBox status code
7286 * @param pDevIns The device instance data.
7287 * @param pAhciPort The port for which the device is to be configured.
7288 */
7289static int ahciR3ConfigureLUN(PPDMDEVINS pDevIns, PAHCIPort pAhciPort)
7290{
7291 int rc = VINF_SUCCESS;
7292 PDMBLOCKTYPE enmType;
7293
7294 /*
7295 * Query the block and blockbios interfaces.
7296 */
7297 pAhciPort->pDrvBlock = PDMIBASE_QUERY_INTERFACE(pAhciPort->pDrvBase, PDMIBLOCK);
7298 if (!pAhciPort->pDrvBlock)
7299 {
7300 AssertMsgFailed(("Configuration error: LUN#%d hasn't a block interface!\n", pAhciPort->iLUN));
7301 return VERR_PDM_MISSING_INTERFACE;
7302 }
7303 pAhciPort->pDrvBlockBios = PDMIBASE_QUERY_INTERFACE(pAhciPort->pDrvBase, PDMIBLOCKBIOS);
7304 if (!pAhciPort->pDrvBlockBios)
7305 {
7306 AssertMsgFailed(("Configuration error: LUN#%d hasn't a block BIOS interface!\n", pAhciPort->iLUN));
7307 return VERR_PDM_MISSING_INTERFACE;
7308 }
7309
7310 pAhciPort->pDrvMount = PDMIBASE_QUERY_INTERFACE(pAhciPort->pDrvBase, PDMIMOUNT);
7311
7312 /* Try to get the optional async block interface. */
7313 pAhciPort->pDrvBlockAsync = PDMIBASE_QUERY_INTERFACE(pAhciPort->pDrvBase, PDMIBLOCKASYNC);
7314
7315 /*
7316 * Validate type.
7317 */
7318 enmType = pAhciPort->pDrvBlock->pfnGetType(pAhciPort->pDrvBlock);
7319
7320 if ( enmType != PDMBLOCKTYPE_HARD_DISK
7321 && enmType != PDMBLOCKTYPE_CDROM
7322 && enmType != PDMBLOCKTYPE_DVD)
7323 {
7324 AssertMsgFailed(("Configuration error: LUN#%d isn't a disk or cd/dvd. enmType=%d\n", pAhciPort->iLUN, enmType));
7325 return VERR_PDM_UNSUPPORTED_BLOCK_TYPE;
7326 }
7327
7328 if ( (enmType == PDMBLOCKTYPE_CDROM || enmType == PDMBLOCKTYPE_DVD)
7329 && !pAhciPort->pDrvMount)
7330 {
7331 AssertMsgFailed(("Internal error: CD/DVD-ROM without a mountable interface\n"));
7332 return VERR_INTERNAL_ERROR;
7333 }
7334 pAhciPort->fATAPI = (enmType == PDMBLOCKTYPE_CDROM || enmType == PDMBLOCKTYPE_DVD);
7335 pAhciPort->fATAPIPassthrough = pAhciPort->fATAPI ? (pAhciPort->pDrvBlock->pfnSendCmd != NULL) : false;
7336
7337 if (pAhciPort->fATAPI)
7338 {
7339 pAhciPort->cTotalSectors = pAhciPort->pDrvBlock->pfnGetSize(pAhciPort->pDrvBlock) / 2048;
7340 pAhciPort->PCHSGeometry.cCylinders = 0;
7341 pAhciPort->PCHSGeometry.cHeads = 0;
7342 pAhciPort->PCHSGeometry.cSectors = 0;
7343 LogRel(("AHCI LUN#%d: CD/DVD, total number of sectors %Ld, passthrough %s\n", pAhciPort->iLUN, pAhciPort->cTotalSectors, (pAhciPort->fATAPIPassthrough ? "enabled" : "disabled")));
7344 }
7345 else
7346 {
7347 pAhciPort->cTotalSectors = pAhciPort->pDrvBlock->pfnGetSize(pAhciPort->pDrvBlock) / 512;
7348 rc = pAhciPort->pDrvBlockBios->pfnGetPCHSGeometry(pAhciPort->pDrvBlockBios,
7349 &pAhciPort->PCHSGeometry);
7350 if (rc == VERR_PDM_MEDIA_NOT_MOUNTED)
7351 {
7352 pAhciPort->PCHSGeometry.cCylinders = 0;
7353 pAhciPort->PCHSGeometry.cHeads = 16; /*??*/
7354 pAhciPort->PCHSGeometry.cSectors = 63; /*??*/
7355 }
7356 else if (rc == VERR_PDM_GEOMETRY_NOT_SET)
7357 {
7358 pAhciPort->PCHSGeometry.cCylinders = 0; /* autodetect marker */
7359 rc = VINF_SUCCESS;
7360 }
7361 AssertRC(rc);
7362
7363 if ( pAhciPort->PCHSGeometry.cCylinders == 0
7364 || pAhciPort->PCHSGeometry.cHeads == 0
7365 || pAhciPort->PCHSGeometry.cSectors == 0)
7366 {
7367 uint64_t cCylinders = pAhciPort->cTotalSectors / (16 * 63);
7368 pAhciPort->PCHSGeometry.cCylinders = RT_MAX(RT_MIN(cCylinders, 16383), 1);
7369 pAhciPort->PCHSGeometry.cHeads = 16;
7370 pAhciPort->PCHSGeometry.cSectors = 63;
7371 /* Set the disk geometry information. Ignore errors. */
7372 pAhciPort->pDrvBlockBios->pfnSetPCHSGeometry(pAhciPort->pDrvBlockBios,
7373 &pAhciPort->PCHSGeometry);
7374 rc = VINF_SUCCESS;
7375 }
7376 LogRel(("AHCI: LUN#%d: disk, PCHS=%u/%u/%u, total number of sectors %Ld\n",
7377 pAhciPort->iLUN, pAhciPort->PCHSGeometry.cCylinders,
7378 pAhciPort->PCHSGeometry.cHeads, pAhciPort->PCHSGeometry.cSectors,
7379 pAhciPort->cTotalSectors));
7380 }
7381 return rc;
7382}
7383
7384/**
7385 * Callback employed by ahciR3Suspend and ahciR3PowerOff..
7386 *
7387 * @returns true if we've quiesced, false if we're still working.
7388 * @param pDevIns The device instance.
7389 */
7390static DECLCALLBACK(bool) ahciR3IsAsyncSuspendOrPowerOffDone(PPDMDEVINS pDevIns)
7391{
7392 if (!ahciR3AllAsyncIOIsFinished(pDevIns))
7393 return false;
7394
7395 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
7396 ASMAtomicWriteBool(&pThis->fSignalIdle, false);
7397 return true;
7398}
7399
7400/**
7401 * Common worker for ahciR3Suspend and ahciR3PowerOff.
7402 */
7403static void ahciR3SuspendOrPowerOff(PPDMDEVINS pDevIns)
7404{
7405 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
7406
7407 ASMAtomicWriteBool(&pThis->fSignalIdle, true);
7408 if (!ahciR3AllAsyncIOIsFinished(pDevIns))
7409 PDMDevHlpSetAsyncNotification(pDevIns, ahciR3IsAsyncSuspendOrPowerOffDone);
7410 else
7411 ASMAtomicWriteBool(&pThis->fSignalIdle, false);
7412}
7413
7414/**
7415 * Suspend notification.
7416 *
7417 * @param pDevIns The device instance data.
7418 */
7419static DECLCALLBACK(void) ahciR3Suspend(PPDMDEVINS pDevIns)
7420{
7421 Log(("ahciR3Suspend\n"));
7422 ahciR3SuspendOrPowerOff(pDevIns);
7423}
7424
7425/**
7426 * Resume notification.
7427 *
7428 * @param pDevIns The device instance data.
7429 */
7430static DECLCALLBACK(void) ahciR3Resume(PPDMDEVINS pDevIns)
7431{
7432 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
7433
7434 /*
7435 * Check if one of the ports has pending tasks.
7436 * Queue a notification item again in this case.
7437 */
7438 for (unsigned i = 0; i < RT_ELEMENTS(pAhci->ahciPort); i++)
7439 {
7440 PAHCIPort pAhciPort = &pAhci->ahciPort[i];
7441
7442 if (pAhciPort->u32TasksNew)
7443 {
7444 PDEVPORTNOTIFIERQUEUEITEM pItem = (PDEVPORTNOTIFIERQUEUEITEM)PDMQueueAlloc(pAhci->CTX_SUFF(pNotifierQueue));
7445 AssertMsg(pItem, ("Allocating item for queue failed\n"));
7446
7447 Assert(pAhciPort->fRedo);
7448 pAhciPort->fRedo = false;
7449
7450 pItem->iPort = pAhci->ahciPort[i].iLUN;
7451 PDMQueueInsert(pAhci->CTX_SUFF(pNotifierQueue), (PPDMQUEUEITEMCORE)pItem);
7452 }
7453 }
7454
7455 Log(("%s:\n", __FUNCTION__));
7456 if (pAhci->fBootable)
7457 for (uint32_t i = 0; i < RT_ELEMENTS(pAhci->aCts); i++)
7458 ataControllerResume(&pAhci->aCts[i]);
7459 return;
7460}
7461
7462/**
7463 * Detach notification.
7464 *
7465 * One harddisk at one port has been unplugged.
7466 * The VM is suspended at this point.
7467 *
7468 * @param pDevIns The device instance.
7469 * @param iLUN The logical unit which is being detached.
7470 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
7471 */
7472static DECLCALLBACK(void) ahciR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
7473{
7474 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
7475 PAHCIPort pAhciPort = &pAhci->ahciPort[iLUN];
7476 int rc = VINF_SUCCESS;
7477
7478 Log(("%s:\n", __FUNCTION__));
7479
7480 AssertMsg(iLUN < pAhci->cPortsImpl, ("iLUN=%u", iLUN));
7481
7482 if (!pAhciPort->fAsyncInterface)
7483 {
7484 int rcThread;
7485 /* Destroy the thread. */
7486 rc = PDMR3ThreadDestroy(pAhciPort->pAsyncIOThread, &rcThread);
7487 if (RT_FAILURE(rc) || RT_FAILURE(rcThread))
7488 AssertMsgFailed(("%s Failed to destroy async IO thread rc=%Rrc rcThread=%Rrc\n", __FUNCTION__, rc, rcThread));
7489
7490 pAhciPort->pAsyncIOThread = NULL;
7491
7492 rc = RTSemEventDestroy(pAhciPort->AsyncIORequestSem);
7493 if (RT_FAILURE(rc))
7494 AssertMsgFailed(("%s: Failed to destroy the event semaphore rc=%Rrc.\n", __FUNCTION__, rc));
7495 }
7496
7497 /* Check if the changed port uses IDE emulation. */
7498 bool fMaster = false;
7499 PAHCIATACONTROLLER pCtl = NULL;
7500
7501 for (unsigned i = 0; i < RT_ELEMENTS(pAhci->aCts); i++)
7502 for (unsigned j = 0; j < RT_ELEMENTS(pAhci->aCts[0].aIfs); j++)
7503 {
7504 PAHCIATACONTROLLER pTmp = &pAhci->aCts[i];
7505 if (pTmp->aIfs[j].iLUN == iLUN)
7506 {
7507 pCtl = pTmp;
7508 fMaster = j == 0 ? true : false;
7509 }
7510 }
7511
7512 if (pCtl)
7513 ataControllerDetach(pCtl, fMaster);
7514
7515 if (pAhciPort->fATAPI)
7516 ahciMediumRemoved(pAhciPort);
7517
7518 /*
7519 * Zero some important members.
7520 */
7521 pAhciPort->pDrvBase = NULL;
7522 pAhciPort->pDrvBlock = NULL;
7523 pAhciPort->pDrvBlockAsync = NULL;
7524 pAhciPort->pDrvBlockBios = NULL;
7525}
7526
7527/**
7528 * Attach command.
7529 *
7530 * This is called when we change block driver for one port.
7531 * The VM is suspended at this point.
7532 *
7533 * @returns VBox status code.
7534 * @param pDevIns The device instance.
7535 * @param iLUN The logical unit which is being detached.
7536 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
7537 */
7538static DECLCALLBACK(int) ahciR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
7539{
7540 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
7541 PAHCIPort pAhciPort = &pAhci->ahciPort[iLUN];
7542 int rc;
7543
7544 Log(("%s:\n", __FUNCTION__));
7545
7546 /* the usual paranoia */
7547 AssertMsg(iLUN < pAhci->cPortsImpl, ("iLUN=%u", iLUN));
7548 AssertRelease(!pAhciPort->pDrvBase);
7549 AssertRelease(!pAhciPort->pDrvBlock);
7550 AssertRelease(!pAhciPort->pDrvBlockAsync);
7551 Assert(pAhciPort->iLUN == iLUN);
7552
7553 /*
7554 * Try attach the block device and get the interfaces,
7555 * required as well as optional.
7556 */
7557 rc = PDMDevHlpDriverAttach(pDevIns, pAhciPort->iLUN, &pAhciPort->IBase, &pAhciPort->pDrvBase, NULL);
7558 if (RT_SUCCESS(rc))
7559 rc = ahciR3ConfigureLUN(pDevIns, pAhciPort);
7560 else
7561 AssertMsgFailed(("Failed to attach LUN#%d. rc=%Rrc\n", pAhciPort->iLUN, rc));
7562
7563 if (RT_FAILURE(rc))
7564 {
7565 pAhciPort->pDrvBase = NULL;
7566 pAhciPort->pDrvBlock = NULL;
7567 }
7568 else
7569 {
7570 /* Check if the changed port uses IDE emulation. */
7571 bool fMaster = false;
7572 PAHCIATACONTROLLER pCtl = NULL;
7573
7574 for (unsigned i = 0; i < RT_ELEMENTS(pAhci->aCts); i++)
7575 for (unsigned j = 0; j < RT_ELEMENTS(pAhci->aCts[0].aIfs); j++)
7576 {
7577 PAHCIATACONTROLLER pTmp = &pAhci->aCts[i];
7578 if (pTmp->aIfs[j].iLUN == iLUN)
7579 {
7580 pCtl = pTmp;
7581 fMaster = j == 0 ? true : false;
7582 }
7583 }
7584
7585 /* Attach to the controller if available */
7586 if (pCtl)
7587 rc = ataControllerAttach(pCtl, pAhciPort->pDrvBase, fMaster);
7588
7589 if (RT_SUCCESS(rc))
7590 {
7591 if ( pAhciPort->pDrvBlockAsync
7592 && !pAhciPort->fATAPI)
7593 {
7594 pAhciPort->fAsyncInterface = true;
7595 }
7596 else
7597 {
7598 char szName[24];
7599 RTStrPrintf(szName, sizeof(szName), "Port%d", iLUN);
7600
7601 pAhciPort->fAsyncInterface = false;
7602
7603 /* Create event semaphore. */
7604 rc = RTSemEventCreate(&pAhciPort->AsyncIORequestSem);
7605 if (RT_FAILURE(rc))
7606 {
7607 Log(("%s: Failed to create event semaphore for %s.\n", __FUNCTION__, szName));
7608 return rc;
7609 }
7610
7611 /* Create the async IO thread. */
7612 rc = PDMDevHlpThreadCreate(pDevIns, &pAhciPort->pAsyncIOThread, pAhciPort, ahciAsyncIOLoop, ahciAsyncIOLoopWakeUp, 0,
7613 RTTHREADTYPE_IO, szName);
7614 if (RT_FAILURE(rc))
7615 {
7616 AssertMsgFailed(("%s: Async IO Thread creation for %s failed rc=%d\n", __FUNCTION__, szName, rc));
7617 return rc;
7618 }
7619 }
7620
7621 if (RT_SUCCESS(rc) && pAhciPort->fATAPI)
7622 ahciMediumInserted(pAhciPort);
7623 }
7624 }
7625
7626 return rc;
7627}
7628
7629/**
7630 * Common reset worker.
7631 *
7632 * @param pDevIns The device instance data.
7633 */
7634static int ahciR3ResetCommon(PPDMDEVINS pDevIns, bool fConstructor)
7635{
7636 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
7637
7638 ahciHBAReset(pAhci);
7639
7640 /* Hardware reset for the ports. */
7641 for (uint32_t i = 0; i < RT_ELEMENTS(pAhci->ahciPort); i++)
7642 ahciPortHwReset(&pAhci->ahciPort[i]);
7643
7644 if (pAhci->fBootable)
7645 for (uint32_t i = 0; i < RT_ELEMENTS(pAhci->aCts); i++)
7646 ataControllerReset(&pAhci->aCts[i]);
7647 return VINF_SUCCESS;
7648}
7649
7650/**
7651 * Callback employed by ahciR3Reset.
7652 *
7653 * @returns true if we've quiesced, false if we're still working.
7654 * @param pDevIns The device instance.
7655 */
7656static DECLCALLBACK(bool) ahciR3IsAsyncResetDone(PPDMDEVINS pDevIns)
7657{
7658 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
7659
7660 if (!ahciR3AllAsyncIOIsFinished(pDevIns))
7661 return false;
7662 ASMAtomicWriteBool(&pThis->fSignalIdle, false);
7663
7664 ahciR3ResetCommon(pDevIns, false /*fConstructor*/);
7665 return true;
7666}
7667
7668/**
7669 * Reset notification.
7670 *
7671 * @param pDevIns The device instance data.
7672 */
7673static DECLCALLBACK(void) ahciR3Reset(PPDMDEVINS pDevIns)
7674{
7675 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
7676
7677 ASMAtomicWriteBool(&pThis->fSignalIdle, true);
7678 if (!ahciR3AllAsyncIOIsFinished(pDevIns))
7679 PDMDevHlpSetAsyncNotification(pDevIns, ahciR3IsAsyncResetDone);
7680 else
7681 {
7682 ASMAtomicWriteBool(&pThis->fSignalIdle, false);
7683 ahciR3ResetCommon(pDevIns, false /*fConstructor*/);
7684 }
7685}
7686
7687/**
7688 * Poweroff notification.
7689 *
7690 * @param pDevIns Pointer to the device instance
7691 */
7692static DECLCALLBACK(void) ahciR3PowerOff(PPDMDEVINS pDevIns)
7693{
7694 Log(("achiR3PowerOff\n"));
7695 ahciR3SuspendOrPowerOff(pDevIns);
7696}
7697
7698/**
7699 * @interface_method_impl{PDMDEVREG,pfnConstruct}
7700 */
7701static DECLCALLBACK(int) ahciR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
7702{
7703 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
7704 PPDMIBASE pBase;
7705 int rc = VINF_SUCCESS;
7706 unsigned i = 0;
7707 bool fGCEnabled = false;
7708 bool fR0Enabled = false;
7709 uint32_t cbTotalBufferSize = 0;
7710 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
7711
7712 /*
7713 * Validate and read configuration.
7714 */
7715 if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0"
7716 "R0Enabled\0"
7717 "PrimaryMaster\0"
7718 "PrimarySlave\0"
7719 "SecondaryMaster\0"
7720 "SecondarySlave\0"
7721 "PortCount\0"
7722 "UseAsyncInterfaceIfAvailable\0"
7723 "Bootable\0"))
7724 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
7725 N_("AHCI configuration error: unknown option specified"));
7726
7727 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
7728 if (RT_FAILURE(rc))
7729 return PDMDEV_SET_ERROR(pDevIns, rc,
7730 N_("AHCI configuration error: failed to read GCEnabled as boolean"));
7731 Log(("%s: fGCEnabled=%d\n", __FUNCTION__, fGCEnabled));
7732
7733 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
7734 if (RT_FAILURE(rc))
7735 return PDMDEV_SET_ERROR(pDevIns, rc,
7736 N_("AHCI configuration error: failed to read R0Enabled as boolean"));
7737 Log(("%s: fR0Enabled=%d\n", __FUNCTION__, fR0Enabled));
7738
7739 rc = CFGMR3QueryU32Def(pCfg, "PortCount", &pThis->cPortsImpl, AHCI_MAX_NR_PORTS_IMPL);
7740 if (RT_FAILURE(rc))
7741 return PDMDEV_SET_ERROR(pDevIns, rc,
7742 N_("AHCI configuration error: failed to read PortCount as integer"));
7743 Log(("%s: cPortsImpl=%u\n", __FUNCTION__, pThis->cPortsImpl));
7744 if (pThis->cPortsImpl > AHCI_MAX_NR_PORTS_IMPL)
7745 return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
7746 N_("AHCI configuration error: PortCount=%u should not exceed %u"),
7747 pThis->cPortsImpl, AHCI_MAX_NR_PORTS_IMPL);
7748 if (pThis->cPortsImpl < 1)
7749 return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
7750 N_("AHCI configuration error: PortCount=%u should be at least 1"),
7751 pThis->cPortsImpl);
7752
7753 rc = CFGMR3QueryBoolDef(pCfg, "UseAsyncInterfaceIfAvailable", &pThis->fUseAsyncInterfaceIfAvailable, true);
7754 if (RT_FAILURE(rc))
7755 return PDMDEV_SET_ERROR(pDevIns, rc,
7756 N_("AHCI configuration error: failed to read UseAsyncInterfaceIfAvailable as boolean"));
7757
7758 rc = CFGMR3QueryBoolDef(pCfg, "Bootable", &pThis->fBootable, true);
7759 if (RT_FAILURE(rc))
7760 return PDMDEV_SET_ERROR(pDevIns, rc,
7761 N_("AHCI configuration error: failed to read Bootable as boolean"));
7762
7763 pThis->fR0Enabled = fR0Enabled;
7764 pThis->fGCEnabled = fGCEnabled;
7765 pThis->pDevInsR3 = pDevIns;
7766 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
7767 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
7768
7769 PCIDevSetVendorId (&pThis->dev, 0x8086); /* Intel */
7770 PCIDevSetDeviceId (&pThis->dev, 0x2829); /* ICH-8M */
7771 PCIDevSetCommand (&pThis->dev, 0x0000);
7772#ifdef VBOX_WITH_MSI_DEVICES
7773 PCIDevSetStatus (&pThis->dev, VBOX_PCI_STATUS_CAP_LIST);
7774 PCIDevSetCapabilityList(&pThis->dev, 0xa0);
7775#else
7776 PCIDevSetCapabilityList(&pThis->dev, 0x70);
7777#endif
7778 PCIDevSetRevisionId (&pThis->dev, 0x02);
7779 PCIDevSetClassProg (&pThis->dev, 0x01);
7780 PCIDevSetClassSub (&pThis->dev, 0x06);
7781 PCIDevSetClassBase (&pThis->dev, 0x01);
7782 PCIDevSetBaseAddress (&pThis->dev, 5, false, false, false, 0x00000000);
7783
7784 PCIDevSetInterruptLine(&pThis->dev, 0x00);
7785 PCIDevSetInterruptPin (&pThis->dev, 0x01);
7786
7787 pThis->dev.config[0x70] = VBOX_PCI_CAP_ID_PM; /* Capability ID: PCI Power Management Interface */
7788 pThis->dev.config[0x71] = 0x00; /* next */
7789 pThis->dev.config[0x72] = 0x03; /* version ? */
7790
7791 pThis->dev.config[0x90] = 0x40; /* AHCI mode. */
7792 pThis->dev.config[0x92] = 0x3f;
7793 pThis->dev.config[0x94] = 0x80;
7794 pThis->dev.config[0x95] = 0x01;
7795 pThis->dev.config[0x97] = 0x78;
7796
7797 /*
7798 * Register the PCI device, it's I/O regions.
7799 */
7800 rc = PDMDevHlpPCIRegister (pDevIns, &pThis->dev);
7801 if (RT_FAILURE(rc))
7802 return rc;
7803
7804#ifdef VBOX_WITH_MSI_DEVICES
7805 PDMMSIREG aMsiReg;
7806
7807 RT_ZERO(aMsiReg);
7808 aMsiReg.cMsiVectors = 1;
7809 aMsiReg.iMsiCapOffset = 0xa0;
7810 aMsiReg.iMsiNextOffset = 0x70;
7811 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &aMsiReg);
7812 if (RT_FAILURE (rc))
7813 {
7814 LogRel(("Chipset cannot do MSI: %Rrc\n", rc));
7815 PCIDevSetCapabilityList(&pThis->dev, 0x70);
7816 /* That's OK, we can work without MSI */
7817 }
7818#endif
7819
7820 /*
7821 * Solaris 10 U5 fails to map the AHCI register space when the sets (0..5) for the legacy
7822 * IDE registers are not available.
7823 * We set up "fake" entries in the PCI configuration register.
7824 * That means they are available but read and writes from/to them have no effect.
7825 * No guest should access them anyway because the controller is marked as AHCI in the Programming interface
7826 * and we don't have an option to change to IDE emulation (real hardware provides an option in the BIOS
7827 * to switch to it which also changes device Id and other things in the PCI configuration space).
7828 */
7829 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 8, PCI_ADDRESS_SPACE_IO, ahciR3LegacyFakeIORangeMap);
7830 if (RT_FAILURE(rc))
7831 return PDMDEV_SET_ERROR(pDevIns, rc,
7832 N_("AHCI cannot register PCI I/O region"));
7833
7834 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 1, 1, PCI_ADDRESS_SPACE_IO, ahciR3LegacyFakeIORangeMap);
7835 if (RT_FAILURE(rc))
7836 return PDMDEV_SET_ERROR(pDevIns, rc,
7837 N_("AHCI cannot register PCI I/O region"));
7838
7839 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 2, 8, PCI_ADDRESS_SPACE_IO, ahciR3LegacyFakeIORangeMap);
7840 if (RT_FAILURE(rc))
7841 return PDMDEV_SET_ERROR(pDevIns, rc,
7842 N_("AHCI cannot register PCI I/O region"));
7843
7844 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 3, 1, PCI_ADDRESS_SPACE_IO, ahciR3LegacyFakeIORangeMap);
7845 if (RT_FAILURE(rc))
7846 return PDMDEV_SET_ERROR(pDevIns, rc,
7847 N_("AHCI cannot register PCI I/O region"));
7848
7849 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 4, 0x10, PCI_ADDRESS_SPACE_IO, ahciR3LegacyFakeIORangeMap);
7850 if (RT_FAILURE(rc))
7851 return PDMDEV_SET_ERROR(pDevIns, rc,
7852 N_("AHCI cannot register PCI I/O region for BMDMA"));
7853
7854 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 5, 4352, PCI_ADDRESS_SPACE_MEM, ahciR3MMIOMap);
7855 if (RT_FAILURE(rc))
7856 return PDMDEV_SET_ERROR(pDevIns, rc,
7857 N_("AHCI cannot register PCI memory region for registers"));
7858
7859 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->lock, RT_SRC_POS, "AHCI%d", pDevIns->iInstance);
7860 if (RT_FAILURE(rc))
7861 {
7862 Log(("%s: Failed to create critical section.\n", __FUNCTION__));
7863 return rc;
7864 }
7865
7866 /* Create the timer for command completion coalescing feature. */
7867 /** @todo r=bird: Using the virtual sync clock needs some justification.
7868 * Currently not an issue as this feature isn't used by any guest
7869 * yet. */
7870 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, ahciCccTimer, pThis,
7871 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, "AHCI CCC Timer", &pThis->pHbaCccTimerR3);
7872 if (RT_FAILURE(rc))
7873 {
7874 AssertMsgFailed(("pfnTMTimerCreate -> %Rrc\n", rc));
7875 return rc;
7876 }
7877 pThis->pHbaCccTimerR0 = TMTimerR0Ptr(pThis->pHbaCccTimerR3);
7878 pThis->pHbaCccTimerRC = TMTimerRCPtr(pThis->pHbaCccTimerR3);
7879
7880 /* Status LUN. */
7881 pThis->IBase.pfnQueryInterface = ahciR3Status_QueryInterface;
7882 pThis->ILeds.pfnQueryStatusLed = ahciR3Status_QueryStatusLed;
7883
7884 /*
7885 * Create the notification queue.
7886 *
7887 * We need 2 items for every port because of SMP races.
7888 */
7889 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(DEVPORTNOTIFIERQUEUEITEM), AHCI_MAX_NR_PORTS_IMPL*2, 0,
7890 ahciNotifyQueueConsumer, true, "AHCI-Xmit", &pThis->pNotifierQueueR3);
7891 if (RT_FAILURE(rc))
7892 return rc;
7893 pThis->pNotifierQueueR0 = PDMQueueR0Ptr(pThis->pNotifierQueueR3);
7894 pThis->pNotifierQueueRC = PDMQueueRCPtr(pThis->pNotifierQueueR3);
7895
7896 /* Initialize static members on every port. */
7897 for (i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
7898 {
7899 /*
7900 * Init members of the port.
7901 */
7902 PAHCIPort pAhciPort = &pThis->ahciPort[i];
7903 pAhciPort->pDevInsR3 = pDevIns;
7904 pAhciPort->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
7905 pAhciPort->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
7906 pAhciPort->iLUN = i;
7907 pAhciPort->pAhciR3 = pThis;
7908 pAhciPort->pAhciR0 = PDMINS_2_DATA_R0PTR(pDevIns);
7909 pAhciPort->pAhciRC = PDMINS_2_DATA_RCPTR(pDevIns);
7910 pAhciPort->Led.u32Magic = PDMLED_MAGIC;
7911 pAhciPort->pDrvBase = NULL;
7912
7913 /* Register statistics counter. */
7914 PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatDMA, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
7915 "Number of DMA transfers.", "/Devices/SATA%d/Port%d/DMA", iInstance, i);
7916 PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatBytesRead, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_BYTES,
7917 "Amount of data read.", "/Devices/SATA%d/Port%d/ReadBytes", iInstance, i);
7918 PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatBytesWritten, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_BYTES,
7919 "Amount of data written.", "/Devices/SATA%d/Port%d/WrittenBytes", iInstance, i);
7920 PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatIORequestsPerSecond, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
7921 "Number of processed I/O requests per second.", "/Devices/SATA%d/Port%d/IORequestsPerSecond", iInstance, i);
7922#ifdef VBOX_WITH_STATISTICS
7923 PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatProfileProcessTime, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_NS_PER_CALL,
7924 "Amount of time to process one request.", "/Devices/SATA%d/Port%d/ProfileProcessTime", iInstance, i);
7925 PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatProfileMapIntoR3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_NS_PER_CALL,
7926 "Amount of time to map the guest buffers into R3.", "/Devices/SATA%d/Port%d/ProfileMapIntoR3", iInstance, i);
7927 PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatProfileReadWrite, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_NS_PER_CALL,
7928 "Amount of time for the read/write operation to complete.", "/Devices/SATA%d/Port%d/ProfileReadWrite", iInstance, i);
7929 PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatProfileDestroyScatterGatherList, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_NS_PER_CALL,
7930 "Amount of time to destroy the scatter gather list and free associated resources.", "/Devices/SATA%d/Port%d/ProfileDestroyScatterGatherList", iInstance, i);
7931#endif
7932
7933 ahciPortHwReset(pAhciPort);
7934 }
7935
7936 /* Attach drivers to every available port. */
7937 for (i = 0; i < pThis->cPortsImpl; i++)
7938 {
7939 char szName[24];
7940 RTStrPrintf(szName, sizeof(szName), "Port%u", i);
7941
7942 PAHCIPort pAhciPort = &pThis->ahciPort[i];
7943 /*
7944 * Init interfaces.
7945 */
7946 pAhciPort->IBase.pfnQueryInterface = ahciR3PortQueryInterface;
7947 pAhciPort->IPortAsync.pfnTransferCompleteNotify = ahciTransferCompleteNotify;
7948 pAhciPort->IPort.pfnQueryDeviceLocation = ahciR3PortQueryDeviceLocation;
7949 pAhciPort->IMountNotify.pfnMountNotify = ahciMountNotify;
7950 pAhciPort->IMountNotify.pfnUnmountNotify = ahciUnmountNotify;
7951 pAhciPort->fAsyncIOThreadIdle = true;
7952
7953 /*
7954 * Attach the block driver
7955 */
7956 rc = PDMDevHlpDriverAttach(pDevIns, pAhciPort->iLUN, &pAhciPort->IBase, &pAhciPort->pDrvBase, szName);
7957 if (RT_SUCCESS(rc))
7958 {
7959 rc = ahciR3ConfigureLUN(pDevIns, pAhciPort);
7960 if (RT_FAILURE(rc))
7961 {
7962 Log(("%s: Failed to configure the %s.\n", __FUNCTION__, szName));
7963 return rc;
7964 }
7965
7966 /* Mark that a device is present on that port */
7967 if (i < 6)
7968 pThis->dev.config[0x93] |= (1 << i);
7969
7970 /*
7971 * Init vendor product data.
7972 */
7973 /* Generate a default serial number. */
7974 char szSerial[AHCI_SERIAL_NUMBER_LENGTH+1];
7975 RTUUID Uuid;
7976 if (pAhciPort->pDrvBlock)
7977 rc = pAhciPort->pDrvBlock->pfnGetUuid(pAhciPort->pDrvBlock, &Uuid);
7978 else
7979 RTUuidClear(&Uuid);
7980
7981 if (RT_FAILURE(rc) || RTUuidIsNull(&Uuid))
7982 {
7983 /* Generate a predictable serial for drives which don't have a UUID. */
7984 RTStrPrintf(szSerial, sizeof(szSerial), "VB%x-1a2b3c4d",
7985 pAhciPort->iLUN);
7986 }
7987 else
7988 RTStrPrintf(szSerial, sizeof(szSerial), "VB%08x-%08x", Uuid.au32[0], Uuid.au32[3]);
7989
7990 /* Get user config if present using defaults otherwise. */
7991 PCFGMNODE pCfgNode = CFGMR3GetChild(pCfg, szName);
7992 rc = CFGMR3QueryStringDef(pCfgNode, "SerialNumber", pAhciPort->szSerialNumber, sizeof(pAhciPort->szSerialNumber),
7993 szSerial);
7994 if (RT_FAILURE(rc))
7995 {
7996 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
7997 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
7998 N_("AHCI configuration error: \"SerialNumber\" is longer than 20 bytes"));
7999 return PDMDEV_SET_ERROR(pDevIns, rc,
8000 N_("AHCI configuration error: failed to read \"SerialNumber\" as string"));
8001 }
8002
8003 rc = CFGMR3QueryStringDef(pCfgNode, "FirmwareRevision", pAhciPort->szFirmwareRevision, sizeof(pAhciPort->szFirmwareRevision),
8004 "1.0");
8005 if (RT_FAILURE(rc))
8006 {
8007 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
8008 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
8009 N_("AHCI configuration error: \"FirmwareRevision\" is longer than 8 bytes"));
8010 return PDMDEV_SET_ERROR(pDevIns, rc,
8011 N_("AHCI configuration error: failed to read \"FirmwareRevision\" as string"));
8012 }
8013
8014 rc = CFGMR3QueryStringDef(pCfgNode, "ModelNumber", pAhciPort->szModelNumber, sizeof(pAhciPort->szModelNumber),
8015 pAhciPort->fATAPI ? "VBOX CD-ROM" : "VBOX HARDDISK");
8016 if (RT_FAILURE(rc))
8017 {
8018 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
8019 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
8020 N_("AHCI configuration error: \"ModelNumber\" is longer than 40 bytes"));
8021 return PDMDEV_SET_ERROR(pDevIns, rc,
8022 N_("AHCI configuration error: failed to read \"ModelNumber\" as string"));
8023 }
8024
8025 /* There are three other identification strings for CD drives used for INQUIRY */
8026 if (pAhciPort->fATAPI)
8027 {
8028 rc = CFGMR3QueryStringDef(pCfgNode, "ATAPIVendorId", pAhciPort->szInquiryVendorId, sizeof(pAhciPort->szInquiryVendorId),
8029 "VBOX");
8030 if (RT_FAILURE(rc))
8031 {
8032 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
8033 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
8034 N_("PIIX3 configuration error: \"ATAPIVendorId\" is longer than 16 bytes"));
8035 return PDMDEV_SET_ERROR(pDevIns, rc,
8036 N_("PIIX3 configuration error: failed to read \"ATAPIVendorId\" as string"));
8037 }
8038
8039 rc = CFGMR3QueryStringDef(pCfgNode, "ATAPIProductId", pAhciPort->szInquiryProductId, sizeof(pAhciPort->szInquiryProductId),
8040 "CD-ROM");
8041 if (RT_FAILURE(rc))
8042 {
8043 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
8044 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
8045 N_("PIIX3 configuration error: \"ATAPIProductId\" is longer than 16 bytes"));
8046 return PDMDEV_SET_ERROR(pDevIns, rc,
8047 N_("PIIX3 configuration error: failed to read \"ATAPIProductId\" as string"));
8048 }
8049
8050 rc = CFGMR3QueryStringDef(pCfgNode, "ATAPIRevision", pAhciPort->szInquiryRevision, sizeof(pAhciPort->szInquiryRevision),
8051 "1.0");
8052 if (RT_FAILURE(rc))
8053 {
8054 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
8055 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
8056 N_("PIIX3 configuration error: \"ATAPIRevision\" is longer than 4 bytes"));
8057 return PDMDEV_SET_ERROR(pDevIns, rc,
8058 N_("PIIX3 configuration error: failed to read \"ATAPIRevision\" as string"));
8059 }
8060 }
8061
8062 /*
8063 * If the new async interface is available we use a PDMQueue to transmit
8064 * the requests into R3.
8065 * Otherwise we use a event semaphore and a async I/O thread which processes them.
8066 */
8067 if (pAhciPort->pDrvBlockAsync && pThis->fUseAsyncInterfaceIfAvailable)
8068 {
8069 LogRel(("AHCI: LUN#%d: using async I/O\n", pAhciPort->iLUN));
8070 pAhciPort->fAsyncInterface = true;
8071 }
8072 else
8073 {
8074 LogRel(("AHCI: LUN#%d: using normal I/O\n", pAhciPort->iLUN));
8075 pAhciPort->fAsyncInterface = false;
8076
8077 rc = RTSemEventCreate(&pAhciPort->AsyncIORequestSem);
8078 AssertMsgRC(rc, ("Failed to create event semaphore for %s rc=%Rrc.\n", szName, rc));
8079
8080
8081 rc = PDMDevHlpThreadCreate(pDevIns, &pAhciPort->pAsyncIOThread, pAhciPort, ahciAsyncIOLoop, ahciAsyncIOLoopWakeUp, 0,
8082 RTTHREADTYPE_IO, szName);
8083 AssertMsgRC(rc, ("%s: Async IO Thread creation for %s failed rc=%Rrc\n", szName, rc));
8084 }
8085 }
8086 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
8087 {
8088 pAhciPort->pDrvBase = NULL;
8089 rc = VINF_SUCCESS;
8090 LogRel(("%s: no driver attached\n", szName));
8091 }
8092 else
8093 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
8094 N_("AHCI: Failed to attach drive to %s"), szName);
8095 }
8096
8097 /*
8098 * Attach status driver (optional).
8099 */
8100 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThis->IBase, &pBase, "Status Port");
8101 if (RT_SUCCESS(rc))
8102 pThis->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
8103 else if (rc != VERR_PDM_NO_ATTACHED_DRIVER)
8104 {
8105 AssertMsgFailed(("Failed to attach to status driver. rc=%Rrc\n", rc));
8106 return PDMDEV_SET_ERROR(pDevIns, rc, N_("AHCI cannot attach to status driver"));
8107 }
8108
8109 if (pThis->fBootable)
8110 {
8111 /*
8112 * Setup IDE emulation.
8113 * We only emulate the I/O ports but not bus master DMA.
8114 * If the configuration values are not found the setup of the ports is as follows:
8115 * Primary Master: Port 0
8116 * Primary Slave: Port 1
8117 * Secondary Master: Port 2
8118 * Secondary Slave: Port 3
8119 */
8120
8121 /*
8122 * Setup I/O ports for the PCI device.
8123 */
8124 pThis->aCts[0].irq = 12;
8125 pThis->aCts[0].IOPortBase1 = 0x1e8;
8126 pThis->aCts[0].IOPortBase2 = 0x3e6;
8127 pThis->aCts[1].irq = 11;
8128 pThis->aCts[1].IOPortBase1 = 0x168;
8129 pThis->aCts[1].IOPortBase2 = 0x366;
8130
8131 for (i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
8132 {
8133 PAHCIATACONTROLLER pCtl = &pThis->aCts[i];
8134 uint32_t iPortMaster, iPortSlave;
8135 uint32_t cbSSMState = 0;
8136 static const char *s_apszDescs[RT_ELEMENTS(pThis->aCts)][RT_ELEMENTS(pCtl->aIfs)] =
8137 {
8138 { "PrimaryMaster", "PrimarySlave" },
8139 { "SecondaryMaster", "SecondarySlave" }
8140 };
8141
8142 rc = CFGMR3QueryU32Def(pCfg, s_apszDescs[i][0], &iPortMaster, 2 * i);
8143 if (RT_FAILURE(rc))
8144 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
8145 N_("AHCI configuration error: failed to read %s as U32"), s_apszDescs[i][0]);
8146
8147 rc = CFGMR3QueryU32Def(pCfg, s_apszDescs[i][1], &iPortSlave, 2 * i + 1);
8148 if (RT_FAILURE(rc))
8149 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
8150 N_("AHCI configuration error: failed to read %s as U32"), s_apszDescs[i][1]);
8151
8152 char szName[24];
8153 RTStrPrintf(szName, sizeof(szName), "EmulatedATA%d", i);
8154 rc = ataControllerInit(pDevIns, pCtl,
8155 iPortMaster, pThis->ahciPort[iPortMaster].pDrvBase,
8156 iPortSlave, pThis->ahciPort[iPortSlave].pDrvBase,
8157 &cbSSMState, szName, &pThis->ahciPort[iPortMaster].Led,
8158 &pThis->ahciPort[iPortMaster].StatBytesRead,
8159 &pThis->ahciPort[iPortMaster].StatBytesWritten);
8160 if (RT_FAILURE(rc))
8161 return rc;
8162
8163 cbTotalBufferSize += cbSSMState;
8164
8165 rc = PDMDevHlpIOPortRegister(pDevIns, pCtl->IOPortBase1, 8, (RTHCPTR)i,
8166 ahciIOPortWrite1, ahciIOPortRead1, ahciIOPortWriteStr1, ahciIOPortReadStr1, "AHCI");
8167 if (RT_FAILURE(rc))
8168 return rc;
8169
8170 if (pThis->fR0Enabled)
8171 {
8172 rc = PDMDevHlpIOPortRegisterR0(pDevIns, pCtl->IOPortBase1, 8, (RTR0PTR)i,
8173 "ahciIOPortWrite1", "ahciIOPortRead1", NULL, NULL, "AHCI R0");
8174 if (RT_FAILURE(rc))
8175 return rc;
8176 }
8177
8178 if (pThis->fGCEnabled)
8179 {
8180 rc = PDMDevHlpIOPortRegisterRC(pDevIns, pCtl->IOPortBase1, 8, (RTGCPTR)i,
8181 "ahciIOPortWrite1", "ahciIOPortRead1", NULL, NULL, "AHCI GC");
8182 if (RT_FAILURE(rc))
8183 return rc;
8184 }
8185
8186 rc = PDMDevHlpIOPortRegister(pDevIns, pCtl->IOPortBase2, 1, (RTHCPTR)i,
8187 ahciIOPortWrite2, ahciIOPortRead2, NULL, NULL, "AHCI");
8188 if (RT_FAILURE(rc))
8189 return rc;
8190
8191 if (pThis->fR0Enabled)
8192 {
8193 rc = PDMDevHlpIOPortRegisterR0(pDevIns, pCtl->IOPortBase2, 1, (RTR0PTR)i,
8194 "ahciIOPortWrite2", "ahciIOPortRead2", NULL, NULL, "AHCI R0");
8195 if (RT_FAILURE(rc))
8196 return rc;
8197 }
8198
8199 if (pThis->fGCEnabled)
8200 {
8201 rc = PDMDevHlpIOPortRegisterRC(pDevIns, pCtl->IOPortBase2, 1, (RTGCPTR)i,
8202 "ahciIOPortWrite2", "ahciIOPortRead2", NULL, NULL, "AHCI GC");
8203 if (RT_FAILURE(rc))
8204 return rc;
8205 }
8206 }
8207 }
8208
8209 rc = PDMDevHlpSSMRegisterEx(pDevIns, AHCI_SAVED_STATE_VERSION, sizeof(*pThis)+cbTotalBufferSize, NULL,
8210 NULL, ahciR3LiveExec, NULL,
8211 ahciR3SavePrep, ahciR3SaveExec, NULL,
8212 ahciR3LoadPrep, ahciR3LoadExec, NULL);
8213 if (RT_FAILURE(rc))
8214 return rc;
8215
8216 /*
8217 * Register the info item.
8218 */
8219 char szTmp[128];
8220 RTStrPrintf(szTmp, sizeof(szTmp), "%s%d", pDevIns->pReg->szName, pDevIns->iInstance);
8221 PDMDevHlpDBGFInfoRegister(pDevIns, szTmp, "AHCI info", ahciR3Info);
8222
8223 return ahciR3ResetCommon(pDevIns, true /*fConstructor*/);
8224}
8225
8226/**
8227 * The device registration structure.
8228 */
8229const PDMDEVREG g_DeviceAHCI =
8230{
8231 /* u32Version */
8232 PDM_DEVREG_VERSION,
8233 /* szName */
8234 "ahci",
8235 /* szRCMod */
8236 "VBoxDDGC.gc",
8237 /* szR0Mod */
8238 "VBoxDDR0.r0",
8239 /* pszDescription */
8240 "Intel AHCI controller.\n",
8241 /* fFlags */
8242 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0 |
8243 PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION | PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION,
8244 /* fClass */
8245 PDM_DEVREG_CLASS_STORAGE,
8246 /* cMaxInstances */
8247 ~0,
8248 /* cbInstance */
8249 sizeof(AHCI),
8250 /* pfnConstruct */
8251 ahciR3Construct,
8252 /* pfnDestruct */
8253 ahciR3Destruct,
8254 /* pfnRelocate */
8255 ahciR3Relocate,
8256 /* pfnIOCtl */
8257 NULL,
8258 /* pfnPowerOn */
8259 NULL,
8260 /* pfnReset */
8261 ahciR3Reset,
8262 /* pfnSuspend */
8263 ahciR3Suspend,
8264 /* pfnResume */
8265 ahciR3Resume,
8266 /* pfnAttach */
8267 ahciR3Attach,
8268 /* pfnDetach */
8269 ahciR3Detach,
8270 /* pfnQueryInterface. */
8271 NULL,
8272 /* pfnInitComplete */
8273 NULL,
8274 /* pfnPowerOff */
8275 ahciR3PowerOff,
8276 /* pfnSoftReset */
8277 NULL,
8278 /* u32VersionEnd */
8279 PDM_DEVREG_VERSION
8280};
8281
8282#endif /* IN_RING3 */
8283#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
Note: See TracBrowser for help on using the repository browser.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette