VirtualBox

source: vbox/trunk/src/VBox/Devices/Storage/DevAHCI.cpp@ 64373

Last change on this file since 64373 was 64373, checked in by vboxsync, 8 years ago

PDM,Devices: Support for multiple PCI devices/function in a single PDM device.
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1/* $Id: DevAHCI.cpp 64373 2016-10-23 19:03:39Z vboxsync $ */
2/** @file
3 * DevAHCI - AHCI controller device (disk and cdrom).
4 *
5 * Implements the AHCI standard 1.1
6 */
7
8/*
9 * Copyright (C) 2006-2016 Oracle Corporation
10 *
11 * This file is part of VirtualBox Open Source Edition (OSE), as
12 * available from http://www.virtualbox.org. This file is free software;
13 * you can redistribute it and/or modify it under the terms of the GNU
14 * General Public License (GPL) as published by the Free Software
15 * Foundation, in version 2 as it comes in the "COPYING" file of the
16 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18 */
19
20/** @page pg_dev_ahci AHCI - Advanced Host Controller Interface Emulation.
21 *
22 * This component implements an AHCI serial ATA controller. The device is split
23 * into two parts. The first part implements the register interface for the
24 * guest and the second one does the data transfer.
25 *
26 * The guest can access the controller in two ways. The first one is the native
27 * way implementing the registers described in the AHCI specification and is
28 * the preferred one. The second implements the I/O ports used for booting from
29 * the hard disk and for guests which don't have an AHCI SATA driver.
30 *
31 * The data is transfered using the extended media interface, asynchronously if
32 * it is supported by the driver below otherwise it weill be done synchronous.
33 * Either way a thread is used to process new requests from the guest.
34 */
35
36
37/*********************************************************************************************************************************
38* Header Files *
39*********************************************************************************************************************************/
40#define LOG_GROUP LOG_GROUP_DEV_AHCI
41#include <VBox/vmm/pdmdev.h>
42#include <VBox/vmm/pdmstorageifs.h>
43#include <VBox/vmm/pdmqueue.h>
44#include <VBox/vmm/pdmthread.h>
45#include <VBox/vmm/pdmcritsect.h>
46#include <VBox/sup.h>
47#include <VBox/scsi.h>
48#include <iprt/assert.h>
49#include <iprt/asm.h>
50#include <iprt/string.h>
51#include <iprt/list.h>
52#ifdef IN_RING3
53# include <iprt/param.h>
54# include <iprt/thread.h>
55# include <iprt/semaphore.h>
56# include <iprt/alloc.h>
57# include <iprt/uuid.h>
58# include <iprt/time.h>
59#endif
60#include "PIIX3ATABmDma.h"
61#include "ide.h"
62#include "VBoxDD.h"
63
64#if defined(VBOX_WITH_DTRACE) \
65 && defined(IN_RING3) \
66 && !defined(VBOX_DEVICE_STRUCT_TESTCASE)
67# include "dtrace/VBoxDD.h"
68#else
69# define VBOXDD_AHCI_REQ_SUBMIT(a,b,c,d) do { } while (0)
70# define VBOXDD_AHCI_REQ_COMPLETED(a,b,c,d) do { } while (0)
71#endif
72
73/** Maximum number of ports available.
74 * Spec defines 32 but we have one allocated for command completion coalescing
75 * and another for a reserved future feature.
76 */
77#define AHCI_MAX_NR_PORTS_IMPL 30
78/** Maximum number of command slots available. */
79#define AHCI_NR_COMMAND_SLOTS 32
80
81/** The current saved state version. */
82#define AHCI_SAVED_STATE_VERSION 9
83/** The saved state version before the ATAPI emulation was removed and the generic SCSI driver was used. */
84#define AHCI_SAVED_STATE_VERSION_PRE_ATAPI_REMOVE 8
85/** The saved state version before changing the port reset logic in an incompatible way. */
86#define AHCI_SAVED_STATE_VERSION_PRE_PORT_RESET_CHANGES 7
87/** Saved state version before the per port hotplug port was added. */
88#define AHCI_SAVED_STATE_VERSION_PRE_HOTPLUG_FLAG 6
89/** Saved state version before legacy ATA emulation was dropped. */
90#define AHCI_SAVED_STATE_VERSION_IDE_EMULATION 5
91/** Saved state version before ATAPI support was added. */
92#define AHCI_SAVED_STATE_VERSION_PRE_ATAPI 3
93/** The saved state version use in VirtualBox 3.0 and earlier.
94 * This was before the config was added and ahciIOTasks was dropped. */
95#define AHCI_SAVED_STATE_VERSION_VBOX_30 2
96/* for Older ATA state Read handling */
97#define ATA_CTL_SAVED_STATE_VERSION 3
98#define ATA_CTL_SAVED_STATE_VERSION_WITHOUT_FULL_SENSE 1
99#define ATA_CTL_SAVED_STATE_VERSION_WITHOUT_EVENT_STATUS 2
100
101/** The maximum number of release log entries per device. */
102#define MAX_LOG_REL_ERRORS 1024
103
104/**
105 * Maximum number of sectors to transfer in a READ/WRITE MULTIPLE request.
106 * Set to 1 to disable multi-sector read support. According to the ATA
107 * specification this must be a power of 2 and it must fit in an 8 bit
108 * value. Thus the only valid values are 1, 2, 4, 8, 16, 32, 64 and 128.
109 */
110#define ATA_MAX_MULT_SECTORS 128
111
112/**
113 * Fastest PIO mode supported by the drive.
114 */
115#define ATA_PIO_MODE_MAX 4
116/**
117 * Fastest MDMA mode supported by the drive.
118 */
119#define ATA_MDMA_MODE_MAX 2
120/**
121 * Fastest UDMA mode supported by the drive.
122 */
123#define ATA_UDMA_MODE_MAX 6
124
125/**
126 * Length of the configurable VPD data (without termination)
127 */
128#define AHCI_SERIAL_NUMBER_LENGTH 20
129#define AHCI_FIRMWARE_REVISION_LENGTH 8
130#define AHCI_MODEL_NUMBER_LENGTH 40
131
132/** ATAPI sense info size. */
133#define ATAPI_SENSE_SIZE 64
134
135/**
136 * Command Header.
137 */
138#pragma pack(1)
139typedef struct
140{
141 /** Description Information. */
142 uint32_t u32DescInf;
143 /** Command status. */
144 uint32_t u32PRDBC;
145 /** Command Table Base Address. */
146 uint32_t u32CmdTblAddr;
147 /** Command Table Base Address - upper 32-bits. */
148 uint32_t u32CmdTblAddrUp;
149 /** Reserved */
150 uint32_t u32Reserved[4];
151} CmdHdr;
152#pragma pack()
153AssertCompileSize(CmdHdr, 32);
154
155/* Defines for the command header. */
156#define AHCI_CMDHDR_PRDTL_MASK 0xffff0000
157#define AHCI_CMDHDR_PRDTL_ENTRIES(x) ((x & AHCI_CMDHDR_PRDTL_MASK) >> 16)
158#define AHCI_CMDHDR_C RT_BIT(10)
159#define AHCI_CMDHDR_B RT_BIT(9)
160#define AHCI_CMDHDR_R RT_BIT(8)
161#define AHCI_CMDHDR_P RT_BIT(7)
162#define AHCI_CMDHDR_W RT_BIT(6)
163#define AHCI_CMDHDR_A RT_BIT(5)
164#define AHCI_CMDHDR_CFL_MASK 0x1f
165
166#define AHCI_CMDHDR_PRDT_OFFSET 0x80
167#define AHCI_CMDHDR_ACMD_OFFSET 0x40
168
169/* Defines for the command FIS. */
170/* Defines that are used in the first double word. */
171#define AHCI_CMDFIS_TYPE 0 /* The first byte. */
172# define AHCI_CMDFIS_TYPE_H2D 0x27 /* Register - Host to Device FIS. */
173# define AHCI_CMDFIS_TYPE_H2D_SIZE 20 /* Five double words. */
174# define AHCI_CMDFIS_TYPE_D2H 0x34 /* Register - Device to Host FIS. */
175# define AHCI_CMDFIS_TYPE_D2H_SIZE 20 /* Five double words. */
176# define AHCI_CMDFIS_TYPE_SETDEVBITS 0xa1 /* Set Device Bits - Device to Host FIS. */
177# define AHCI_CMDFIS_TYPE_SETDEVBITS_SIZE 8 /* Two double words. */
178# define AHCI_CMDFIS_TYPE_DMAACTD2H 0x39 /* DMA Activate - Device to Host FIS. */
179# define AHCI_CMDFIS_TYPE_DMAACTD2H_SIZE 4 /* One double word. */
180# define AHCI_CMDFIS_TYPE_DMASETUP 0x41 /* DMA Setup - Bidirectional FIS. */
181# define AHCI_CMDFIS_TYPE_DMASETUP_SIZE 28 /* Seven double words. */
182# define AHCI_CMDFIS_TYPE_PIOSETUP 0x5f /* PIO Setup - Device to Host FIS. */
183# define AHCI_CMDFIS_TYPE_PIOSETUP_SIZE 20 /* Five double words. */
184# define AHCI_CMDFIS_TYPE_DATA 0x46 /* Data - Bidirectional FIS. */
185
186#define AHCI_CMDFIS_BITS 1 /* Interrupt and Update bit. */
187#define AHCI_CMDFIS_C RT_BIT(7) /* Host to device. */
188#define AHCI_CMDFIS_I RT_BIT(6) /* Device to Host. */
189#define AHCI_CMDFIS_D RT_BIT(5)
190
191#define AHCI_CMDFIS_CMD 2
192#define AHCI_CMDFIS_FET 3
193
194#define AHCI_CMDFIS_SECTN 4
195#define AHCI_CMDFIS_CYLL 5
196#define AHCI_CMDFIS_CYLH 6
197#define AHCI_CMDFIS_HEAD 7
198
199#define AHCI_CMDFIS_SECTNEXP 8
200#define AHCI_CMDFIS_CYLLEXP 9
201#define AHCI_CMDFIS_CYLHEXP 10
202#define AHCI_CMDFIS_FETEXP 11
203
204#define AHCI_CMDFIS_SECTC 12
205#define AHCI_CMDFIS_SECTCEXP 13
206#define AHCI_CMDFIS_CTL 15
207# define AHCI_CMDFIS_CTL_SRST RT_BIT(2) /* Reset device. */
208# define AHCI_CMDFIS_CTL_NIEN RT_BIT(1) /* Assert or clear interrupt. */
209
210/* For D2H FIS */
211#define AHCI_CMDFIS_STS 2
212#define AHCI_CMDFIS_ERR 3
213
214/** Pointer to a task state. */
215typedef struct AHCIREQ *PAHCIREQ;
216
217/**
218 * Data processing callback
219 *
220 * @returns VBox status code.
221 * @param pAhciReq The task state.
222 * @param pSgBuf Buffer holding the data to process.
223 * @param cbBuf Size of the buffer.
224 * @param offBuf Offset into the guest buffer.
225 * @param ppvProc Where to store the pointer to the buffer holding the processed data on success.
226 * Must be freed with RTMemFree().
227 * @param pcbProc Where to store the size of the buffer on success.
228 */
229typedef DECLCALLBACK(int) FNAHCIPOSTPROCESS(PAHCIREQ pAhciReq, PRTSGBUF pSgBuf, size_t cbBuf,
230 uint32_t offBuf, void **ppvProc, size_t *pcbProc);
231/** Pointer to a FNAHCIPOSTPROCESS() function. */
232typedef FNAHCIPOSTPROCESS *PFNAHCIPOSTPROCESS;
233
234/** Task encountered a buffer overflow. */
235#define AHCI_REQ_OVERFLOW RT_BIT_32(0)
236/** Request is a PIO data command, if this flag is not set it either is
237 * a command which does not transfer data or a DMA command based on the transfer size. */
238#define AHCI_REQ_PIO_DATA RT_BIT_32(1)
239/** The request has the SACT register set. */
240#define AHCI_REQ_CLEAR_SACT RT_BIT_32(2)
241/** Flag whether the request is queued. */
242#define AHCI_REQ_IS_QUEUED RT_BIT_32(3)
243/** Flag whether the request is stored on the stack. */
244#define AHCI_REQ_IS_ON_STACK RT_BIT_32(4)
245/** Flag whether this request transfers data from the device to the HBA or
246 * the other way around .*/
247#define AHCI_REQ_XFER_2_HOST RT_BIT_32(5)
248
249/**
250 * A task state.
251 */
252typedef struct AHCIREQ
253{
254 /** The I/O request handle from the driver below associated with this request. */
255 PDMMEDIAEXIOREQ hIoReq;
256 /** Tag of the task. */
257 uint32_t uTag;
258 /** The command Fis for this task. */
259 uint8_t cmdFis[AHCI_CMDFIS_TYPE_H2D_SIZE];
260 /** The ATAPI command data. */
261 uint8_t aATAPICmd[ATAPI_PACKET_SIZE];
262 /** Size of one sector for the ATAPI transfer. */
263 uint32_t cbATAPISector;
264 /** Physical address of the command header. - GC */
265 RTGCPHYS GCPhysCmdHdrAddr;
266 /** Physical address of the PRDT */
267 RTGCPHYS GCPhysPrdtl;
268 /** Number of entries in the PRDTL. */
269 unsigned cPrdtlEntries;
270 /** Data direction. */
271 PDMMEDIAEXIOREQTYPE enmType;
272 /** Start offset. */
273 uint64_t uOffset;
274 /** Number of bytes to transfer. */
275 size_t cbTransfer;
276 /** Flags for this task. */
277 uint32_t fFlags;
278 /** SCSI status code. */
279 uint8_t u8ScsiSts;
280 /** Post processing callback.
281 * If this is set we will use a buffer for the data
282 * and the callback returns a buffer with the final data. */
283 PFNAHCIPOSTPROCESS pfnPostProcess;
284} AHCIREQ;
285
286/**
287 * Notifier queue item.
288 */
289typedef struct DEVPORTNOTIFIERQUEUEITEM
290{
291 /** The core part owned by the queue manager. */
292 PDMQUEUEITEMCORE Core;
293 /** The port to process. */
294 uint8_t iPort;
295} DEVPORTNOTIFIERQUEUEITEM, *PDEVPORTNOTIFIERQUEUEITEM;
296
297
298/**
299 * @implements PDMIBASE
300 * @implements PDMIMEDIAPORT
301 * @implements PDMIMEDIAEXPORT
302 */
303typedef struct AHCIPort
304{
305 /** Pointer to the device instance - HC ptr */
306 PPDMDEVINSR3 pDevInsR3;
307 /** Pointer to the device instance - R0 ptr */
308 PPDMDEVINSR0 pDevInsR0;
309 /** Pointer to the device instance - RC ptr. */
310 PPDMDEVINSRC pDevInsRC;
311
312#if HC_ARCH_BITS == 64
313 uint32_t Alignment0;
314#endif
315
316 /** Pointer to the parent AHCI structure - R3 ptr. */
317 R3PTRTYPE(struct AHCI *) pAhciR3;
318 /** Pointer to the parent AHCI structure - R0 ptr. */
319 R0PTRTYPE(struct AHCI *) pAhciR0;
320 /** Pointer to the parent AHCI structure - RC ptr. */
321 RCPTRTYPE(struct AHCI *) pAhciRC;
322
323 /** Command List Base Address. */
324 uint32_t regCLB;
325 /** Command List Base Address upper bits. */
326 uint32_t regCLBU;
327 /** FIS Base Address. */
328 uint32_t regFB;
329 /** FIS Base Address upper bits. */
330 uint32_t regFBU;
331 /** Interrupt Status. */
332 volatile uint32_t regIS;
333 /** Interrupt Enable. */
334 uint32_t regIE;
335 /** Command. */
336 uint32_t regCMD;
337 /** Task File Data. */
338 uint32_t regTFD;
339 /** Signature */
340 uint32_t regSIG;
341 /** Serial ATA Status. */
342 uint32_t regSSTS;
343 /** Serial ATA Control. */
344 uint32_t regSCTL;
345 /** Serial ATA Error. */
346 uint32_t regSERR;
347 /** Serial ATA Active. */
348 volatile uint32_t regSACT;
349 /** Command Issue. */
350 uint32_t regCI;
351
352 /** Current number of active tasks. */
353 volatile uint32_t cTasksActive;
354 /** Command List Base Address */
355 volatile RTGCPHYS GCPhysAddrClb;
356 /** FIS Base Address */
357 volatile RTGCPHYS GCPhysAddrFb;
358
359 /** Device is powered on. */
360 bool fPoweredOn;
361 /** Device has spun up. */
362 bool fSpunUp;
363 /** First D2H FIS was send. */
364 bool fFirstD2HFisSend;
365 /** Attached device is a CD/DVD drive. */
366 bool fATAPI;
367 /** Flag whether this port is in a reset state. */
368 volatile bool fPortReset;
369 /** Flag whether TRIM is supported. */
370 bool fTrimEnabled;
371 /** Flag if we are in a device reset. */
372 bool fResetDevice;
373 /** Flag whether this port is hot plug capable. */
374 bool fHotpluggable;
375 /** Flag whether the port is in redo task mode. */
376 volatile bool fRedo;
377 /** Flag whether the worker thread is sleeping. */
378 volatile bool fWrkThreadSleeping;
379
380 bool afAlignment[4];
381
382 /** Number of total sectors. */
383 uint64_t cTotalSectors;
384 /** Size of one sector. */
385 uint32_t cbSector;
386 /** Currently configured number of sectors in a multi-sector transfer. */
387 uint32_t cMultSectors;
388 /** Currently active transfer mode (MDMA/UDMA) and speed. */
389 uint8_t uATATransferMode;
390 /** ATAPI sense data. */
391 uint8_t abATAPISense[ATAPI_SENSE_SIZE];
392 /** Exponent of logical sectors in a physical sector, number of logical sectors is 2^exp. */
393 uint8_t cLogSectorsPerPhysicalExp;
394 /** The LUN. */
395 RTUINT iLUN;
396
397 /** Bitmap for finished tasks (R3 -> Guest). */
398 volatile uint32_t u32TasksFinished;
399 /** Bitmap for finished queued tasks (R3 -> Guest). */
400 volatile uint32_t u32QueuedTasksFinished;
401 /** Bitmap for new queued tasks (Guest -> R3). */
402 volatile uint32_t u32TasksNew;
403 /** Bitmap of tasks which must be redone because of a non fatal error. */
404 volatile uint32_t u32TasksRedo;
405
406 /** Current command slot processed.
407 * Accessed by the guest by reading the CMD register.
408 * Holds the command slot of the command processed at the moment. */
409 volatile uint32_t u32CurrentCommandSlot;
410
411#if HC_ARCH_BITS == 64
412 uint32_t u32Alignment2;
413#endif
414
415 /** Device specific settings (R3 only stuff). */
416 /** Pointer to the attached driver's base interface. */
417 R3PTRTYPE(PPDMIBASE) pDrvBase;
418 /** Pointer to the attached driver's block interface. */
419 R3PTRTYPE(PPDMIMEDIA) pDrvMedia;
420 /** Pointer to the attached driver's extended interface. */
421 R3PTRTYPE(PPDMIMEDIAEX) pDrvMediaEx;
422 /** The base interface. */
423 PDMIBASE IBase;
424 /** The block port interface. */
425 PDMIMEDIAPORT IPort;
426 /** The extended media port interface. */
427 PDMIMEDIAEXPORT IMediaExPort;
428 /** Physical geometry of this image. */
429 PDMMEDIAGEOMETRY PCHSGeometry;
430 /** The status LED state for this drive. */
431 PDMLED Led;
432
433 uint32_t u32Alignment3;
434
435 /** Async IO Thread. */
436 R3PTRTYPE(PPDMTHREAD) pAsyncIOThread;
437 /** First task throwing an error. */
438 R3PTRTYPE(volatile PAHCIREQ) pTaskErr;
439
440 /** The event semaphore the processing thread waits on. */
441 SUPSEMEVENT hEvtProcess;
442
443 /** Release statistics: number of DMA commands. */
444 STAMCOUNTER StatDMA;
445 /** Release statistics: number of bytes written. */
446 STAMCOUNTER StatBytesWritten;
447 /** Release statistics: number of bytes read. */
448 STAMCOUNTER StatBytesRead;
449 /** Release statistics: Number of I/O requests processed per second. */
450 STAMCOUNTER StatIORequestsPerSecond;
451#ifdef VBOX_WITH_STATISTICS
452 /** Statistics: Time to complete one request. */
453 STAMPROFILE StatProfileProcessTime;
454 /** Statistics: Amount of time to read/write data. */
455 STAMPROFILE StatProfileReadWrite;
456#endif /* VBOX_WITH_STATISTICS */
457
458 /** The serial numnber to use for IDENTIFY DEVICE commands. */
459 char szSerialNumber[AHCI_SERIAL_NUMBER_LENGTH+1]; /** < one extra byte for termination */
460 /** The firmware revision to use for IDENTIFY DEVICE commands. */
461 char szFirmwareRevision[AHCI_FIRMWARE_REVISION_LENGTH+1]; /** < one extra byte for termination */
462 /** The model number to use for IDENTIFY DEVICE commands. */
463 char szModelNumber[AHCI_MODEL_NUMBER_LENGTH+1]; /** < one extra byte for termination */
464 /** Error counter */
465 uint32_t cErrors;
466
467 uint32_t u32Alignment5;
468
469} AHCIPort;
470/** Pointer to the state of an AHCI port. */
471typedef AHCIPort *PAHCIPort;
472
473AssertCompileMemberAlignment(AHCIPort, StatDMA, 8);
474AssertCompileSizeAlignment(AHCIPort, 8);
475
476/**
477 * Main AHCI device state.
478 *
479 * @implements PDMILEDPORTS
480 */
481typedef struct AHCI
482{
483 /** The PCI device structure. */
484 PCIDEVICE dev;
485 /** Pointer to the device instance - R3 ptr */
486 PPDMDEVINSR3 pDevInsR3;
487 /** Pointer to the device instance - R0 ptr */
488 PPDMDEVINSR0 pDevInsR0;
489 /** Pointer to the device instance - RC ptr. */
490 PPDMDEVINSRC pDevInsRC;
491
492#if HC_ARCH_BITS == 64
493 uint32_t Alignment0;
494#endif
495
496 /** Status LUN: The base interface. */
497 PDMIBASE IBase;
498 /** Status LUN: Leds interface. */
499 PDMILEDPORTS ILeds;
500 /** Status LUN: Partner of ILeds. */
501 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
502 /** Status LUN: Media Notifys. */
503 R3PTRTYPE(PPDMIMEDIANOTIFY) pMediaNotify;
504
505#if HC_ARCH_BITS == 32
506 uint32_t Alignment1;
507#endif
508
509 /** Base address of the MMIO region. */
510 RTGCPHYS MMIOBase;
511 /** Base address of the I/O port region for Idx/Data. */
512 RTIOPORT IOPortBase;
513
514 /** Global Host Control register of the HBA */
515
516 /** HBA Capabilities - Readonly */
517 uint32_t regHbaCap;
518 /** HBA Control */
519 uint32_t regHbaCtrl;
520 /** Interrupt Status */
521 uint32_t regHbaIs;
522 /** Ports Implemented - Readonly */
523 uint32_t regHbaPi;
524 /** AHCI Version - Readonly */
525 uint32_t regHbaVs;
526 /** Command completion coalescing control */
527 uint32_t regHbaCccCtl;
528 /** Command completion coalescing ports */
529 uint32_t regHbaCccPorts;
530
531 /** Index register for BIOS access. */
532 uint32_t regIdx;
533
534#if HC_ARCH_BITS == 64
535 uint32_t Alignment3;
536#endif
537
538 /** Countdown timer for command completion coalescing - R3 ptr */
539 PTMTIMERR3 pHbaCccTimerR3;
540 /** Countdown timer for command completion coalescing - R0 ptr */
541 PTMTIMERR0 pHbaCccTimerR0;
542 /** Countdown timer for command completion coalescing - RC ptr */
543 PTMTIMERRC pHbaCccTimerRC;
544
545#if HC_ARCH_BITS == 64
546 uint32_t Alignment4;
547#endif
548
549 /** Queue to send tasks to R3. - HC ptr */
550 R3PTRTYPE(PPDMQUEUE) pNotifierQueueR3;
551 /** Queue to send tasks to R3. - HC ptr */
552 R0PTRTYPE(PPDMQUEUE) pNotifierQueueR0;
553 /** Queue to send tasks to R3. - RC ptr */
554 RCPTRTYPE(PPDMQUEUE) pNotifierQueueRC;
555
556#if HC_ARCH_BITS == 64
557 uint32_t Alignment5;
558#endif
559
560
561 /** Which port number is used to mark an CCC interrupt */
562 uint8_t uCccPortNr;
563
564#if HC_ARCH_BITS == 64
565 uint32_t Alignment6;
566#endif
567
568 /** Timeout value */
569 uint64_t uCccTimeout;
570 /** Number of completions used to assert an interrupt */
571 uint32_t uCccNr;
572 /** Current number of completed commands */
573 uint32_t uCccCurrentNr;
574
575 /** Register structure per port */
576 AHCIPort ahciPort[AHCI_MAX_NR_PORTS_IMPL];
577
578 /** The critical section. */
579 PDMCRITSECT lock;
580
581 /** Bitmask of ports which asserted an interrupt. */
582 volatile uint32_t u32PortsInterrupted;
583 /** Number of I/O threads currently active - used for async controller reset handling. */
584 volatile uint32_t cThreadsActive;
585 /** Device is in a reset state. */
586 bool fReset;
587 /** Supports 64bit addressing */
588 bool f64BitAddr;
589 /** GC enabled. */
590 bool fGCEnabled;
591 /** R0 enabled. */
592 bool fR0Enabled;
593 /** Indicates that PDMDevHlpAsyncNotificationCompleted should be called when
594 * a port is entering the idle state. */
595 bool volatile fSignalIdle;
596 /** Flag whether the controller has BIOS access enabled. */
597 bool fBootable;
598 /** Flag whether the legacy port reset method should be used to make it work with saved states. */
599 bool fLegacyPortResetMethod;
600
601 /** Number of usable ports on this controller. */
602 uint32_t cPortsImpl;
603 /** Number of usable command slots for each port. */
604 uint32_t cCmdSlotsAvail;
605
606 /** Flag whether we have written the first 4bytes in an 8byte MMIO write successfully. */
607 volatile bool f8ByteMMIO4BytesWrittenSuccessfully;
608
609#if HC_ARCH_BITS == 64
610 uint32_t Alignment7;
611#endif
612
613 /** The support driver session handle. */
614 R3R0PTRTYPE(PSUPDRVSESSION) pSupDrvSession;
615} AHCI;
616/** Pointer to the state of an AHCI device. */
617typedef AHCI *PAHCI;
618
619AssertCompileMemberAlignment(AHCI, ahciPort, 8);
620
621/**
622 * Scatter gather list entry.
623 */
624typedef struct
625{
626 /** Data Base Address. */
627 uint32_t u32DBA;
628 /** Data Base Address - Upper 32-bits. */
629 uint32_t u32DBAUp;
630 /** Reserved */
631 uint32_t u32Reserved;
632 /** Description information. */
633 uint32_t u32DescInf;
634} SGLEntry;
635AssertCompileSize(SGLEntry, 16);
636
637#ifdef IN_RING3
638/**
639 * Memory buffer callback.
640 *
641 * @returns nothing.
642 * @param pThis The NVME controller instance.
643 * @param GCPhys The guest physical address of the memory buffer.
644 * @param pSgBuf The pointer to the host R3 S/G buffer.
645 * @param cbCopy How many bytes to copy between the two buffers.
646 * @param pcbSkip Initially contains the amount of bytes to skip
647 * starting from the guest physical address before
648 * accessing the S/G buffer and start copying data.
649 * On return this contains the remaining amount if
650 * cbCopy < *pcbSkip or 0 otherwise.
651 */
652typedef DECLCALLBACK(void) AHCIR3MEMCOPYCALLBACK(PAHCI pThis, RTGCPHYS GCPhys, PRTSGBUF pSgBuf, size_t cbCopy,
653 size_t *pcbSkip);
654/** Pointer to a memory copy buffer callback. */
655typedef AHCIR3MEMCOPYCALLBACK *PAHCIR3MEMCOPYCALLBACK;
656#endif
657
658/** Defines for a scatter gather list entry. */
659#define SGLENTRY_DBA_READONLY ~(RT_BIT(0))
660#define SGLENTRY_DESCINF_I RT_BIT(31)
661#define SGLENTRY_DESCINF_DBC 0x3fffff
662#define SGLENTRY_DESCINF_READONLY 0x803fffff
663
664/* Defines for the global host control registers for the HBA. */
665
666#define AHCI_HBA_GLOBAL_SIZE 0x100
667
668/* Defines for the HBA Capabilities - Readonly */
669#define AHCI_HBA_CAP_S64A RT_BIT(31)
670#define AHCI_HBA_CAP_SNCQ RT_BIT(30)
671#define AHCI_HBA_CAP_SIS RT_BIT(28)
672#define AHCI_HBA_CAP_SSS RT_BIT(27)
673#define AHCI_HBA_CAP_SALP RT_BIT(26)
674#define AHCI_HBA_CAP_SAL RT_BIT(25)
675#define AHCI_HBA_CAP_SCLO RT_BIT(24)
676#define AHCI_HBA_CAP_ISS (RT_BIT(23) | RT_BIT(22) | RT_BIT(21) | RT_BIT(20))
677# define AHCI_HBA_CAP_ISS_SHIFT(x) (((x) << 20) & AHCI_HBA_CAP_ISS)
678# define AHCI_HBA_CAP_ISS_GEN1 RT_BIT(0)
679# define AHCI_HBA_CAP_ISS_GEN2 RT_BIT(1)
680#define AHCI_HBA_CAP_SNZO RT_BIT(19)
681#define AHCI_HBA_CAP_SAM RT_BIT(18)
682#define AHCI_HBA_CAP_SPM RT_BIT(17)
683#define AHCI_HBA_CAP_PMD RT_BIT(15)
684#define AHCI_HBA_CAP_SSC RT_BIT(14)
685#define AHCI_HBA_CAP_PSC RT_BIT(13)
686#define AHCI_HBA_CAP_NCS (RT_BIT(12) | RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8))
687#define AHCI_HBA_CAP_NCS_SET(x) (((x-1) << 8) & AHCI_HBA_CAP_NCS) /* 0's based */
688#define AHCI_HBA_CAP_CCCS RT_BIT(7)
689#define AHCI_HBA_CAP_NP (RT_BIT(4) | RT_BIT(3) | RT_BIT(2) | RT_BIT(1) | RT_BIT(0))
690#define AHCI_HBA_CAP_NP_SET(x) ((x-1) & AHCI_HBA_CAP_NP) /* 0's based */
691
692/* Defines for the HBA Control register - Read/Write */
693#define AHCI_HBA_CTRL_AE RT_BIT(31)
694#define AHCI_HBA_CTRL_IE RT_BIT(1)
695#define AHCI_HBA_CTRL_HR RT_BIT(0)
696#define AHCI_HBA_CTRL_RW_MASK (RT_BIT(0) | RT_BIT(1)) /* Mask for the used bits */
697
698/* Defines for the HBA Version register - Readonly (We support AHCI 1.0) */
699#define AHCI_HBA_VS_MJR (1 << 16)
700#define AHCI_HBA_VS_MNR 0x100
701
702/* Defines for the command completion coalescing control register */
703#define AHCI_HBA_CCC_CTL_TV 0xffff0000
704#define AHCI_HBA_CCC_CTL_TV_SET(x) (x << 16)
705#define AHCI_HBA_CCC_CTL_TV_GET(x) ((x & AHCI_HBA_CCC_CTL_TV) >> 16)
706
707#define AHCI_HBA_CCC_CTL_CC 0xff00
708#define AHCI_HBA_CCC_CTL_CC_SET(x) (x << 8)
709#define AHCI_HBA_CCC_CTL_CC_GET(x) ((x & AHCI_HBA_CCC_CTL_CC) >> 8)
710
711#define AHCI_HBA_CCC_CTL_INT 0xf8
712#define AHCI_HBA_CCC_CTL_INT_SET(x) (x << 3)
713#define AHCI_HBA_CCC_CTL_INT_GET(x) ((x & AHCI_HBA_CCC_CTL_INT) >> 3)
714
715#define AHCI_HBA_CCC_CTL_EN RT_BIT(0)
716
717/* Defines for the port registers. */
718
719#define AHCI_PORT_REGISTER_SIZE 0x80
720
721#define AHCI_PORT_CLB_RESERVED 0xfffffc00 /* For masking out the reserved bits. */
722
723#define AHCI_PORT_FB_RESERVED 0xffffff00 /* For masking out the reserved bits. */
724
725#define AHCI_PORT_IS_CPDS RT_BIT(31)
726#define AHCI_PORT_IS_TFES RT_BIT(30)
727#define AHCI_PORT_IS_HBFS RT_BIT(29)
728#define AHCI_PORT_IS_HBDS RT_BIT(28)
729#define AHCI_PORT_IS_IFS RT_BIT(27)
730#define AHCI_PORT_IS_INFS RT_BIT(26)
731#define AHCI_PORT_IS_OFS RT_BIT(24)
732#define AHCI_PORT_IS_IPMS RT_BIT(23)
733#define AHCI_PORT_IS_PRCS RT_BIT(22)
734#define AHCI_PORT_IS_DIS RT_BIT(7)
735#define AHCI_PORT_IS_PCS RT_BIT(6)
736#define AHCI_PORT_IS_DPS RT_BIT(5)
737#define AHCI_PORT_IS_UFS RT_BIT(4)
738#define AHCI_PORT_IS_SDBS RT_BIT(3)
739#define AHCI_PORT_IS_DSS RT_BIT(2)
740#define AHCI_PORT_IS_PSS RT_BIT(1)
741#define AHCI_PORT_IS_DHRS RT_BIT(0)
742#define AHCI_PORT_IS_READONLY 0xfd8000af /* Readonly mask including reserved bits. */
743
744#define AHCI_PORT_IE_CPDE RT_BIT(31)
745#define AHCI_PORT_IE_TFEE RT_BIT(30)
746#define AHCI_PORT_IE_HBFE RT_BIT(29)
747#define AHCI_PORT_IE_HBDE RT_BIT(28)
748#define AHCI_PORT_IE_IFE RT_BIT(27)
749#define AHCI_PORT_IE_INFE RT_BIT(26)
750#define AHCI_PORT_IE_OFE RT_BIT(24)
751#define AHCI_PORT_IE_IPME RT_BIT(23)
752#define AHCI_PORT_IE_PRCE RT_BIT(22)
753#define AHCI_PORT_IE_DIE RT_BIT(7) /* Not supported for now, readonly. */
754#define AHCI_PORT_IE_PCE RT_BIT(6)
755#define AHCI_PORT_IE_DPE RT_BIT(5)
756#define AHCI_PORT_IE_UFE RT_BIT(4)
757#define AHCI_PORT_IE_SDBE RT_BIT(3)
758#define AHCI_PORT_IE_DSE RT_BIT(2)
759#define AHCI_PORT_IE_PSE RT_BIT(1)
760#define AHCI_PORT_IE_DHRE RT_BIT(0)
761#define AHCI_PORT_IE_READONLY (0xfdc000ff) /* Readonly mask including reserved bits. */
762
763#define AHCI_PORT_CMD_ICC (RT_BIT(28) | RT_BIT(29) | RT_BIT(30) | RT_BIT(31))
764#define AHCI_PORT_CMD_ICC_SHIFT(x) ((x) << 28)
765# define AHCI_PORT_CMD_ICC_IDLE 0x0
766# define AHCI_PORT_CMD_ICC_ACTIVE 0x1
767# define AHCI_PORT_CMD_ICC_PARTIAL 0x2
768# define AHCI_PORT_CMD_ICC_SLUMBER 0x6
769#define AHCI_PORT_CMD_ASP RT_BIT(27) /* Not supported - Readonly */
770#define AHCI_PORT_CMD_ALPE RT_BIT(26) /* Not supported - Readonly */
771#define AHCI_PORT_CMD_DLAE RT_BIT(25)
772#define AHCI_PORT_CMD_ATAPI RT_BIT(24)
773#define AHCI_PORT_CMD_CPD RT_BIT(20)
774#define AHCI_PORT_CMD_ISP RT_BIT(19) /* Readonly */
775#define AHCI_PORT_CMD_HPCP RT_BIT(18)
776#define AHCI_PORT_CMD_PMA RT_BIT(17) /* Not supported - Readonly */
777#define AHCI_PORT_CMD_CPS RT_BIT(16)
778#define AHCI_PORT_CMD_CR RT_BIT(15) /* Readonly */
779#define AHCI_PORT_CMD_FR RT_BIT(14) /* Readonly */
780#define AHCI_PORT_CMD_ISS RT_BIT(13) /* Readonly */
781#define AHCI_PORT_CMD_CCS (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11) | RT_BIT(12))
782#define AHCI_PORT_CMD_CCS_SHIFT(x) (x << 8) /* Readonly */
783#define AHCI_PORT_CMD_FRE RT_BIT(4)
784#define AHCI_PORT_CMD_CLO RT_BIT(3)
785#define AHCI_PORT_CMD_POD RT_BIT(2)
786#define AHCI_PORT_CMD_SUD RT_BIT(1)
787#define AHCI_PORT_CMD_ST RT_BIT(0)
788#define AHCI_PORT_CMD_READONLY (0xff02001f & ~(AHCI_PORT_CMD_ASP | AHCI_PORT_CMD_ALPE | AHCI_PORT_CMD_PMA))
789
790#define AHCI_PORT_SCTL_IPM (RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8))
791#define AHCI_PORT_SCTL_IPM_GET(x) ((x & AHCI_PORT_SCTL_IPM) >> 8)
792#define AHCI_PORT_SCTL_SPD (RT_BIT(7) | RT_BIT(6) | RT_BIT(5) | RT_BIT(4))
793#define AHCI_PORT_SCTL_SPD_GET(x) ((x & AHCI_PORT_SCTL_SPD) >> 4)
794#define AHCI_PORT_SCTL_DET (RT_BIT(3) | RT_BIT(2) | RT_BIT(1) | RT_BIT(0))
795#define AHCI_PORT_SCTL_DET_GET(x) (x & AHCI_PORT_SCTL_DET)
796#define AHCI_PORT_SCTL_DET_NINIT 0
797#define AHCI_PORT_SCTL_DET_INIT 1
798#define AHCI_PORT_SCTL_DET_OFFLINE 4
799#define AHCI_PORT_SCTL_READONLY 0xfff
800
801#define AHCI_PORT_SSTS_IPM (RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8))
802#define AHCI_PORT_SSTS_IPM_GET(x) ((x & AHCI_PORT_SCTL_IPM) >> 8)
803#define AHCI_PORT_SSTS_SPD (RT_BIT(7) | RT_BIT(6) | RT_BIT(5) | RT_BIT(4))
804#define AHCI_PORT_SSTS_SPD_GET(x) ((x & AHCI_PORT_SCTL_SPD) >> 4)
805#define AHCI_PORT_SSTS_DET (RT_BIT(3) | RT_BIT(2) | RT_BIT(1) | RT_BIT(0))
806#define AHCI_PORT_SSTS_DET_GET(x) (x & AHCI_PORT_SCTL_DET)
807
808#define AHCI_PORT_TFD_BSY RT_BIT(7)
809#define AHCI_PORT_TFD_DRQ RT_BIT(3)
810#define AHCI_PORT_TFD_ERR RT_BIT(0)
811
812#define AHCI_PORT_SERR_X RT_BIT(26)
813#define AHCI_PORT_SERR_W RT_BIT(18)
814#define AHCI_PORT_SERR_N RT_BIT(16)
815
816/* Signatures for attached storage devices. */
817#define AHCI_PORT_SIG_DISK 0x00000101
818#define AHCI_PORT_SIG_ATAPI 0xeb140101
819
820/*
821 * The AHCI spec defines an area of memory where the HBA posts received FIS's from the device.
822 * regFB points to the base of this area.
823 * Every FIS type has an offset where it is posted in this area.
824 */
825#define AHCI_RECFIS_DSFIS_OFFSET 0x00 /* DMA Setup FIS */
826#define AHCI_RECFIS_PSFIS_OFFSET 0x20 /* PIO Setup FIS */
827#define AHCI_RECFIS_RFIS_OFFSET 0x40 /* D2H Register FIS */
828#define AHCI_RECFIS_SDBFIS_OFFSET 0x58 /* Set Device Bits FIS */
829#define AHCI_RECFIS_UFIS_OFFSET 0x60 /* Unknown FIS type */
830
831/** Mask to get the LBA value from a LBA range. */
832#define AHCI_RANGE_LBA_MASK UINT64_C(0xffffffffffff)
833/** Mas to get the length value from a LBA range. */
834#define AHCI_RANGE_LENGTH_MASK UINT64_C(0xffff000000000000)
835/** Returns the length of the range in sectors. */
836#define AHCI_RANGE_LENGTH_GET(val) (((val) & AHCI_RANGE_LENGTH_MASK) >> 48)
837
838/**
839 * AHCI register operator.
840 */
841typedef struct ahci_opreg
842{
843 const char *pszName;
844 int (*pfnRead )(PAHCI pAhci, uint32_t iReg, uint32_t *pu32Value);
845 int (*pfnWrite)(PAHCI pAhci, uint32_t iReg, uint32_t u32Value);
846} AHCIOPREG;
847
848/**
849 * AHCI port register operator.
850 */
851typedef struct pAhciPort_opreg
852{
853 const char *pszName;
854 int (*pfnRead )(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value);
855 int (*pfnWrite)(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value);
856} AHCIPORTOPREG;
857
858#ifndef VBOX_DEVICE_STRUCT_TESTCASE
859RT_C_DECLS_BEGIN
860#ifdef IN_RING3
861static void ahciHBAReset(PAHCI pThis);
862static int ahciPostFisIntoMemory(PAHCIPort pAhciPort, unsigned uFisType, uint8_t *cmdFis);
863static void ahciPostFirstD2HFisIntoMemory(PAHCIPort pAhciPort);
864static size_t ahciR3CopyBufferToPrdtl(PAHCI pThis, PAHCIREQ pAhciReq, const void *pvSrc,
865 size_t cbSrc, size_t cbSkip);
866static bool ahciCancelActiveTasks(PAHCIPort pAhciPort);
867#endif
868RT_C_DECLS_END
869
870#define PCIDEV_2_PAHCI(pPciDev) ( (PAHCI)(pPciDev) )
871#define PDMIBASE_2_PAHCIPORT(pInterface) ( (PAHCIPort)((uintptr_t)(pInterface) - RT_OFFSETOF(AHCIPort, IBase)) )
872#define PDMIMEDIAPORT_2_PAHCIPORT(pInterface) ( (PAHCIPort)((uintptr_t)(pInterface) - RT_OFFSETOF(AHCIPort, IPort)) )
873#define PDMIBASE_2_PAHCI(pInterface) ( (PAHCI)((uintptr_t)(pInterface) - RT_OFFSETOF(AHCI, IBase)) )
874#define PDMILEDPORTS_2_PAHCI(pInterface) ( (PAHCI)((uintptr_t)(pInterface) - RT_OFFSETOF(AHCI, ILeds)) )
875
876#define AHCI_RTGCPHYS_FROM_U32(Hi, Lo) ( (RTGCPHYS)RT_MAKE_U64(Lo, Hi) )
877
878#ifdef IN_RING3
879
880# ifdef LOG_USE_C99
881# define ahciLog(a) \
882 Log(("R3 P%u: %M", pAhciPort->iLUN, _LogRelRemoveParentheseis a))
883# else
884# define ahciLog(a) \
885 do { Log(("R3 P%u: ", pAhciPort->iLUN)); Log(a); } while(0)
886# endif
887
888#elif defined(IN_RING0)
889
890# ifdef LOG_USE_C99
891# define ahciLog(a) \
892 Log(("R0 P%u: %M", pAhciPort->iLUN, _LogRelRemoveParentheseis a))
893# else
894# define ahciLog(a) \
895 do { Log(("R0 P%u: ", pAhciPort->iLUN)); Log(a); } while(0)
896# endif
897
898#elif defined(IN_RC)
899
900# ifdef LOG_USE_C99
901# define ahciLog(a) \
902 Log(("GC P%u: %M", pAhciPort->iLUN, _LogRelRemoveParentheseis a))
903# else
904# define ahciLog(a) \
905 do { Log(("GC P%u: ", pAhciPort->iLUN)); Log(a); } while(0)
906# endif
907
908#endif
909
910/**
911 * Update PCI IRQ levels
912 */
913static void ahciHbaClearInterrupt(PAHCI pAhci)
914{
915 Log(("%s: Clearing interrupt\n", __FUNCTION__));
916 PDMDevHlpPCISetIrq(pAhci->CTX_SUFF(pDevIns), 0, 0);
917}
918
919/**
920 * Updates the IRQ level and sets port bit in the global interrupt status register of the HBA.
921 */
922static int ahciHbaSetInterrupt(PAHCI pAhci, uint8_t iPort, int rcBusy)
923{
924 Log(("P%u: %s: Setting interrupt\n", iPort, __FUNCTION__));
925
926 int rc = PDMCritSectEnter(&pAhci->lock, rcBusy);
927 if (rc != VINF_SUCCESS)
928 return rc;
929
930 if (pAhci->regHbaCtrl & AHCI_HBA_CTRL_IE)
931 {
932 if ((pAhci->regHbaCccCtl & AHCI_HBA_CCC_CTL_EN) && (pAhci->regHbaCccPorts & (1 << iPort)))
933 {
934 pAhci->uCccCurrentNr++;
935 if (pAhci->uCccCurrentNr >= pAhci->uCccNr)
936 {
937 /* Reset command completion coalescing state. */
938 TMTimerSetMillies(pAhci->CTX_SUFF(pHbaCccTimer), pAhci->uCccTimeout);
939 pAhci->uCccCurrentNr = 0;
940
941 pAhci->u32PortsInterrupted |= (1 << pAhci->uCccPortNr);
942 if (!(pAhci->u32PortsInterrupted & ~(1 << pAhci->uCccPortNr)))
943 {
944 Log(("P%u: %s: Fire interrupt\n", iPort, __FUNCTION__));
945 PDMDevHlpPCISetIrq(pAhci->CTX_SUFF(pDevIns), 0, 1);
946 }
947 }
948 }
949 else
950 {
951 /* If only the bit of the actual port is set assert an interrupt
952 * because the interrupt status register was already read by the guest
953 * and we need to send a new notification.
954 * Otherwise an interrupt is still pending.
955 */
956 ASMAtomicOrU32((volatile uint32_t *)&pAhci->u32PortsInterrupted, (1 << iPort));
957 if (!(pAhci->u32PortsInterrupted & ~(1 << iPort)))
958 {
959 Log(("P%u: %s: Fire interrupt\n", iPort, __FUNCTION__));
960 PDMDevHlpPCISetIrq(pAhci->CTX_SUFF(pDevIns), 0, 1);
961 }
962 }
963 }
964
965 PDMCritSectLeave(&pAhci->lock);
966 return VINF_SUCCESS;
967}
968
969#ifdef IN_RING3
970
971/*
972 * Assert irq when an CCC timeout occurs
973 */
974static DECLCALLBACK(void) ahciCccTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
975{
976 RT_NOREF(pDevIns, pTimer);
977 PAHCI pAhci = (PAHCI)pvUser;
978
979 int rc = ahciHbaSetInterrupt(pAhci, pAhci->uCccPortNr, VERR_IGNORED);
980 AssertRC(rc);
981}
982
983/**
984 * Finishes the port reset of the given port.
985 *
986 * @returns nothing.
987 * @param pAhciPort The port to finish the reset on.
988 */
989static void ahciPortResetFinish(PAHCIPort pAhciPort)
990{
991 /* Cancel all tasks first. */
992 bool fAllTasksCanceled = ahciCancelActiveTasks(pAhciPort);
993 Assert(fAllTasksCanceled); NOREF(fAllTasksCanceled);
994
995 /* Signature for SATA device. */
996 if (pAhciPort->fATAPI)
997 pAhciPort->regSIG = AHCI_PORT_SIG_ATAPI;
998 else
999 pAhciPort->regSIG = AHCI_PORT_SIG_DISK;
1000
1001 /* We received a COMINIT from the device. Tell the guest. */
1002 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_PCS);
1003 pAhciPort->regSERR |= AHCI_PORT_SERR_X;
1004 pAhciPort->regTFD |= ATA_STAT_BUSY;
1005
1006 if ((pAhciPort->regCMD & AHCI_PORT_CMD_FRE) && (!pAhciPort->fFirstD2HFisSend))
1007 {
1008 ahciPostFirstD2HFisIntoMemory(pAhciPort);
1009 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_DHRS);
1010
1011 if (pAhciPort->regIE & AHCI_PORT_IE_DHRE)
1012 {
1013 int rc = ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN, VERR_IGNORED);
1014 AssertRC(rc);
1015 }
1016 }
1017
1018 pAhciPort->regSSTS = (0x01 << 8) | /* Interface is active. */
1019 (0x03 << 0); /* Device detected and communication established. */
1020
1021 /*
1022 * Use the maximum allowed speed.
1023 * (Not that it changes anything really)
1024 */
1025 switch (AHCI_PORT_SCTL_SPD_GET(pAhciPort->regSCTL))
1026 {
1027 case 0x01:
1028 pAhciPort->regSSTS |= (0x01 << 4); /* Generation 1 (1.5GBps) speed. */
1029 break;
1030 case 0x02:
1031 case 0x00:
1032 default:
1033 pAhciPort->regSSTS |= (0x02 << 4); /* Generation 2 (3.0GBps) speed. */
1034 break;
1035 }
1036
1037 ASMAtomicXchgBool(&pAhciPort->fPortReset, false);
1038}
1039
1040#endif /* IN_RING3 */
1041
1042/**
1043 * Kicks the I/O thread from RC or R0.
1044 *
1045 * @returns nothing.
1046 * @param pAhci The AHCI controller instance.
1047 * @param pAhciPort The port to kick.
1048 */
1049static void ahciIoThreadKick(PAHCI pAhci, PAHCIPort pAhciPort)
1050{
1051#ifdef IN_RC
1052 PDEVPORTNOTIFIERQUEUEITEM pItem = (PDEVPORTNOTIFIERQUEUEITEM)PDMQueueAlloc(pAhci->CTX_SUFF(pNotifierQueue));
1053 AssertMsg(VALID_PTR(pItem), ("Allocating item for queue failed\n"));
1054
1055 if (pItem)
1056 {
1057 pItem->iPort = pAhciPort->iLUN;
1058 PDMQueueInsert(pAhci->CTX_SUFF(pNotifierQueue), (PPDMQUEUEITEMCORE)pItem);
1059 }
1060#else
1061 LogFlowFunc(("Signal event semaphore\n"));
1062 int rc = SUPSemEventSignal(pAhci->pSupDrvSession, pAhciPort->hEvtProcess);
1063 AssertRC(rc);
1064#endif
1065}
1066
1067static int PortCmdIssue_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1068{
1069 RT_NOREF1(iReg);
1070 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1071
1072 /* Update the CI register first. */
1073 uint32_t uCIValue = ASMAtomicXchgU32(&pAhciPort->u32TasksFinished, 0);
1074 pAhciPort->regCI &= ~uCIValue;
1075
1076 if ( (pAhciPort->regCMD & AHCI_PORT_CMD_CR)
1077 && u32Value > 0)
1078 {
1079 /*
1080 * Clear all tasks which are already marked as busy. The guest
1081 * shouldn't write already busy tasks actually.
1082 */
1083 u32Value &= ~pAhciPort->regCI;
1084
1085 ASMAtomicOrU32(&pAhciPort->u32TasksNew, u32Value);
1086
1087 /* Send a notification to R3 if u32TasksNew was 0 before our write. */
1088 if (ASMAtomicReadBool(&pAhciPort->fWrkThreadSleeping))
1089 ahciIoThreadKick(pAhci, pAhciPort);
1090 }
1091
1092 pAhciPort->regCI |= u32Value;
1093
1094 return VINF_SUCCESS;
1095}
1096
1097static int PortCmdIssue_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1098{
1099 RT_NOREF2(pAhci, iReg);
1100
1101 uint32_t uCIValue = ASMAtomicXchgU32(&pAhciPort->u32TasksFinished, 0);
1102 ahciLog(("%s: read regCI=%#010x uCIValue=%#010x\n", __FUNCTION__, pAhciPort->regCI, uCIValue));
1103
1104 pAhciPort->regCI &= ~uCIValue;
1105 *pu32Value = pAhciPort->regCI;
1106
1107 return VINF_SUCCESS;
1108}
1109
1110static int PortSActive_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1111{
1112 RT_NOREF2(pAhci, iReg);
1113 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1114
1115 pAhciPort->regSACT |= u32Value;
1116
1117 return VINF_SUCCESS;
1118}
1119
1120static int PortSActive_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1121{
1122 RT_NOREF2(pAhci, iReg);
1123
1124 uint32_t u32TasksFinished = ASMAtomicXchgU32(&pAhciPort->u32QueuedTasksFinished, 0);
1125 pAhciPort->regSACT &= ~u32TasksFinished;
1126
1127 ahciLog(("%s: read regSACT=%#010x regCI=%#010x u32TasksFinished=%#010x\n",
1128 __FUNCTION__, pAhciPort->regSACT, pAhciPort->regCI, u32TasksFinished));
1129
1130 *pu32Value = pAhciPort->regSACT;
1131
1132 return VINF_SUCCESS;
1133}
1134
1135static int PortSError_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1136{
1137 RT_NOREF2(pAhci, iReg);
1138 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1139
1140 if ( (u32Value & AHCI_PORT_SERR_X)
1141 && (pAhciPort->regSERR & AHCI_PORT_SERR_X))
1142 {
1143 ASMAtomicAndU32(&pAhciPort->regIS, ~AHCI_PORT_IS_PCS);
1144 pAhciPort->regTFD |= ATA_STAT_ERR;
1145 pAhciPort->regTFD &= ~(ATA_STAT_DRQ | ATA_STAT_BUSY);
1146 }
1147
1148 if ( (u32Value & AHCI_PORT_SERR_N)
1149 && (pAhciPort->regSERR & AHCI_PORT_SERR_N))
1150 ASMAtomicAndU32(&pAhciPort->regIS, ~AHCI_PORT_IS_PRCS);
1151
1152 pAhciPort->regSERR &= ~u32Value;
1153
1154 return VINF_SUCCESS;
1155}
1156
1157static int PortSError_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1158{
1159 RT_NOREF2(pAhci, iReg);
1160 ahciLog(("%s: read regSERR=%#010x\n", __FUNCTION__, pAhciPort->regSERR));
1161 *pu32Value = pAhciPort->regSERR;
1162 return VINF_SUCCESS;
1163}
1164
1165static int PortSControl_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1166{
1167 RT_NOREF2(pAhci, iReg);
1168 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1169 ahciLog(("%s: IPM=%d SPD=%d DET=%d\n", __FUNCTION__,
1170 AHCI_PORT_SCTL_IPM_GET(u32Value), AHCI_PORT_SCTL_SPD_GET(u32Value), AHCI_PORT_SCTL_DET_GET(u32Value)));
1171
1172#ifndef IN_RING3
1173 RT_NOREF2(pAhciPort, u32Value);
1174 return VINF_IOM_R3_MMIO_WRITE;
1175#else
1176 if ((u32Value & AHCI_PORT_SCTL_DET) == AHCI_PORT_SCTL_DET_INIT)
1177 {
1178 if (!ASMAtomicXchgBool(&pAhciPort->fPortReset, true))
1179 LogRel(("AHCI#%u: Port %d reset\n", pAhci->CTX_SUFF(pDevIns)->iInstance,
1180 pAhciPort->iLUN));
1181
1182 pAhciPort->regSSTS = 0;
1183 pAhciPort->regSIG = UINT32_MAX;
1184 pAhciPort->regTFD = 0x7f;
1185 pAhciPort->fFirstD2HFisSend = false;
1186 pAhciPort->regSCTL = u32Value;
1187 }
1188 else if ( (u32Value & AHCI_PORT_SCTL_DET) == AHCI_PORT_SCTL_DET_NINIT
1189 && (pAhciPort->regSCTL & AHCI_PORT_SCTL_DET) == AHCI_PORT_SCTL_DET_INIT
1190 && pAhciPort->pDrvBase)
1191 {
1192 /* Do the port reset here, so the guest sees the new status immediately. */
1193 if (pAhci->fLegacyPortResetMethod)
1194 {
1195 ahciPortResetFinish(pAhciPort);
1196 pAhciPort->regSCTL = u32Value; /* Update after finishing the reset, so the I/O thread doesn't get a chance to do the reset. */
1197 }
1198 else
1199 {
1200 pAhciPort->regSSTS = 0x1; /* Indicate device presence detected but communication not established. */
1201 pAhciPort->regSCTL = u32Value; /* Update before kicking the I/O thread. */
1202
1203 /* Kick the thread to finish the reset. */
1204 ahciIoThreadKick(pAhci, pAhciPort);
1205 }
1206 }
1207 else /* Just update the value if there is no device attached. */
1208 pAhciPort->regSCTL = u32Value;
1209
1210 return VINF_SUCCESS;
1211#endif
1212}
1213
1214static int PortSControl_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1215{
1216 RT_NOREF2(pAhci, iReg);
1217 ahciLog(("%s: read regSCTL=%#010x\n", __FUNCTION__, pAhciPort->regSCTL));
1218 ahciLog(("%s: IPM=%d SPD=%d DET=%d\n", __FUNCTION__,
1219 AHCI_PORT_SCTL_IPM_GET(pAhciPort->regSCTL), AHCI_PORT_SCTL_SPD_GET(pAhciPort->regSCTL),
1220 AHCI_PORT_SCTL_DET_GET(pAhciPort->regSCTL)));
1221
1222 *pu32Value = pAhciPort->regSCTL;
1223 return VINF_SUCCESS;
1224}
1225
1226static int PortSStatus_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1227{
1228 RT_NOREF2(pAhci, iReg);
1229 ahciLog(("%s: read regSSTS=%#010x\n", __FUNCTION__, pAhciPort->regSSTS));
1230 ahciLog(("%s: IPM=%d SPD=%d DET=%d\n", __FUNCTION__,
1231 AHCI_PORT_SSTS_IPM_GET(pAhciPort->regSSTS), AHCI_PORT_SSTS_SPD_GET(pAhciPort->regSSTS),
1232 AHCI_PORT_SSTS_DET_GET(pAhciPort->regSSTS)));
1233
1234 *pu32Value = pAhciPort->regSSTS;
1235 return VINF_SUCCESS;
1236}
1237
1238static int PortSignature_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1239{
1240 RT_NOREF2(pAhci, iReg);
1241 ahciLog(("%s: read regSIG=%#010x\n", __FUNCTION__, pAhciPort->regSIG));
1242 *pu32Value = pAhciPort->regSIG;
1243 return VINF_SUCCESS;
1244}
1245
1246static int PortTaskFileData_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1247{
1248 RT_NOREF2(pAhci, iReg);
1249 ahciLog(("%s: read regTFD=%#010x\n", __FUNCTION__, pAhciPort->regTFD));
1250 ahciLog(("%s: ERR=%x BSY=%d DRQ=%d ERR=%d\n", __FUNCTION__,
1251 (pAhciPort->regTFD >> 8), (pAhciPort->regTFD & AHCI_PORT_TFD_BSY) >> 7,
1252 (pAhciPort->regTFD & AHCI_PORT_TFD_DRQ) >> 3, (pAhciPort->regTFD & AHCI_PORT_TFD_ERR)));
1253 *pu32Value = pAhciPort->regTFD;
1254 return VINF_SUCCESS;
1255}
1256
1257/**
1258 * Read from the port command register.
1259 */
1260static int PortCmd_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1261{
1262 RT_NOREF2(pAhci, iReg);
1263 ahciLog(("%s: read regCMD=%#010x\n", __FUNCTION__, pAhciPort->regCMD | AHCI_PORT_CMD_CCS_SHIFT(pAhciPort->u32CurrentCommandSlot)));
1264 ahciLog(("%s: ICC=%d ASP=%d ALPE=%d DLAE=%d ATAPI=%d CPD=%d ISP=%d HPCP=%d PMA=%d CPS=%d CR=%d FR=%d ISS=%d CCS=%d FRE=%d CLO=%d POD=%d SUD=%d ST=%d\n",
1265 __FUNCTION__, (pAhciPort->regCMD & AHCI_PORT_CMD_ICC) >> 28, (pAhciPort->regCMD & AHCI_PORT_CMD_ASP) >> 27,
1266 (pAhciPort->regCMD & AHCI_PORT_CMD_ALPE) >> 26, (pAhciPort->regCMD & AHCI_PORT_CMD_DLAE) >> 25,
1267 (pAhciPort->regCMD & AHCI_PORT_CMD_ATAPI) >> 24, (pAhciPort->regCMD & AHCI_PORT_CMD_CPD) >> 20,
1268 (pAhciPort->regCMD & AHCI_PORT_CMD_ISP) >> 19, (pAhciPort->regCMD & AHCI_PORT_CMD_HPCP) >> 18,
1269 (pAhciPort->regCMD & AHCI_PORT_CMD_PMA) >> 17, (pAhciPort->regCMD & AHCI_PORT_CMD_CPS) >> 16,
1270 (pAhciPort->regCMD & AHCI_PORT_CMD_CR) >> 15, (pAhciPort->regCMD & AHCI_PORT_CMD_FR) >> 14,
1271 (pAhciPort->regCMD & AHCI_PORT_CMD_ISS) >> 13, pAhciPort->u32CurrentCommandSlot,
1272 (pAhciPort->regCMD & AHCI_PORT_CMD_FRE) >> 4, (pAhciPort->regCMD & AHCI_PORT_CMD_CLO) >> 3,
1273 (pAhciPort->regCMD & AHCI_PORT_CMD_POD) >> 2, (pAhciPort->regCMD & AHCI_PORT_CMD_SUD) >> 1,
1274 (pAhciPort->regCMD & AHCI_PORT_CMD_ST)));
1275 *pu32Value = pAhciPort->regCMD | AHCI_PORT_CMD_CCS_SHIFT(pAhciPort->u32CurrentCommandSlot);
1276 return VINF_SUCCESS;
1277}
1278
1279/**
1280 * Write to the port command register.
1281 * This is the register where all the data transfer is started
1282 */
1283static int PortCmd_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1284{
1285 RT_NOREF1(iReg);
1286 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1287 ahciLog(("%s: ICC=%d ASP=%d ALPE=%d DLAE=%d ATAPI=%d CPD=%d ISP=%d HPCP=%d PMA=%d CPS=%d CR=%d FR=%d ISS=%d CCS=%d FRE=%d CLO=%d POD=%d SUD=%d ST=%d\n",
1288 __FUNCTION__, (u32Value & AHCI_PORT_CMD_ICC) >> 28, (u32Value & AHCI_PORT_CMD_ASP) >> 27,
1289 (u32Value & AHCI_PORT_CMD_ALPE) >> 26, (u32Value & AHCI_PORT_CMD_DLAE) >> 25,
1290 (u32Value & AHCI_PORT_CMD_ATAPI) >> 24, (u32Value & AHCI_PORT_CMD_CPD) >> 20,
1291 (u32Value & AHCI_PORT_CMD_ISP) >> 19, (u32Value & AHCI_PORT_CMD_HPCP) >> 18,
1292 (u32Value & AHCI_PORT_CMD_PMA) >> 17, (u32Value & AHCI_PORT_CMD_CPS) >> 16,
1293 (u32Value & AHCI_PORT_CMD_CR) >> 15, (u32Value & AHCI_PORT_CMD_FR) >> 14,
1294 (u32Value & AHCI_PORT_CMD_ISS) >> 13, (u32Value & AHCI_PORT_CMD_CCS) >> 8,
1295 (u32Value & AHCI_PORT_CMD_FRE) >> 4, (u32Value & AHCI_PORT_CMD_CLO) >> 3,
1296 (u32Value & AHCI_PORT_CMD_POD) >> 2, (u32Value & AHCI_PORT_CMD_SUD) >> 1,
1297 (u32Value & AHCI_PORT_CMD_ST)));
1298
1299 /* The PxCMD.CCS bits are R/O and maintained separately. */
1300 u32Value &= ~AHCI_PORT_CMD_CCS;
1301
1302 if (pAhciPort->fPoweredOn && pAhciPort->fSpunUp)
1303 {
1304 if (u32Value & AHCI_PORT_CMD_CLO)
1305 {
1306 ahciLog(("%s: Command list override requested\n", __FUNCTION__));
1307 u32Value &= ~(AHCI_PORT_TFD_BSY | AHCI_PORT_TFD_DRQ);
1308 /* Clear the CLO bit. */
1309 u32Value &= ~(AHCI_PORT_CMD_CLO);
1310 }
1311
1312 if (u32Value & AHCI_PORT_CMD_ST)
1313 {
1314 /*
1315 * Set engine state to running if there is a device attached and
1316 * IS.PCS is clear.
1317 */
1318 if ( pAhciPort->pDrvBase
1319 && !(pAhciPort->regIS & AHCI_PORT_IS_PCS))
1320 {
1321 ahciLog(("%s: Engine starts\n", __FUNCTION__));
1322 u32Value |= AHCI_PORT_CMD_CR;
1323
1324 /* If there is something in CI, kick the I/O thread. */
1325 if ( pAhciPort->regCI > 0
1326 && ASMAtomicReadBool(&pAhciPort->fWrkThreadSleeping))
1327 {
1328 ASMAtomicOrU32(&pAhciPort->u32TasksNew, pAhciPort->regCI);
1329#ifdef IN_RC
1330 PDEVPORTNOTIFIERQUEUEITEM pItem = (PDEVPORTNOTIFIERQUEUEITEM)PDMQueueAlloc(pAhci->CTX_SUFF(pNotifierQueue));
1331 AssertMsg(VALID_PTR(pItem), ("Allocating item for queue failed\n"));
1332
1333 pItem->iPort = pAhciPort->iLUN;
1334 PDMQueueInsert(pAhci->CTX_SUFF(pNotifierQueue), (PPDMQUEUEITEMCORE)pItem);
1335#else
1336 LogFlowFunc(("Signal event semaphore\n"));
1337 int rc = SUPSemEventSignal(pAhci->pSupDrvSession, pAhciPort->hEvtProcess);
1338 AssertRC(rc);
1339#endif
1340 }
1341 }
1342 else
1343 u32Value &= ~AHCI_PORT_CMD_CR;
1344 }
1345 else
1346 {
1347 ahciLog(("%s: Engine stops\n", __FUNCTION__));
1348 /* Clear command issue register. */
1349 pAhciPort->regCI = 0;
1350 pAhciPort->regSACT = 0;
1351 /* Clear current command slot. */
1352 pAhciPort->u32CurrentCommandSlot = 0;
1353 u32Value &= ~AHCI_PORT_CMD_CR;
1354 }
1355 }
1356 else if (pAhciPort->pDrvBase)
1357 {
1358 if ((u32Value & AHCI_PORT_CMD_POD) && (pAhciPort->regCMD & AHCI_PORT_CMD_CPS) && !pAhciPort->fPoweredOn)
1359 {
1360 ahciLog(("%s: Power on the device\n", __FUNCTION__));
1361 pAhciPort->fPoweredOn = true;
1362
1363 /*
1364 * Set states in the Port Signature and SStatus registers.
1365 */
1366 if (pAhciPort->fATAPI)
1367 pAhciPort->regSIG = AHCI_PORT_SIG_ATAPI;
1368 else
1369 pAhciPort->regSIG = AHCI_PORT_SIG_DISK;
1370 pAhciPort->regSSTS = (0x01 << 8) | /* Interface is active. */
1371 (0x02 << 4) | /* Generation 2 (3.0GBps) speed. */
1372 (0x03 << 0); /* Device detected and communication established. */
1373
1374 if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
1375 {
1376#ifndef IN_RING3
1377 return VINF_IOM_R3_MMIO_WRITE;
1378#else
1379 ahciPostFirstD2HFisIntoMemory(pAhciPort);
1380 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_DHRS);
1381
1382 if (pAhciPort->regIE & AHCI_PORT_IE_DHRE)
1383 {
1384 int rc = ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN, VERR_IGNORED);
1385 AssertRC(rc);
1386 }
1387#endif
1388 }
1389 }
1390
1391 if ((u32Value & AHCI_PORT_CMD_SUD) && pAhciPort->fPoweredOn && !pAhciPort->fSpunUp)
1392 {
1393 ahciLog(("%s: Spin up the device\n", __FUNCTION__));
1394 pAhciPort->fSpunUp = true;
1395 }
1396 }
1397
1398 if (u32Value & AHCI_PORT_CMD_FRE)
1399 {
1400 ahciLog(("%s: FIS receive enabled\n", __FUNCTION__));
1401
1402 u32Value |= AHCI_PORT_CMD_FR;
1403
1404 /* Send the first D2H FIS only if it wasn't already send. */
1405 if ( !pAhciPort->fFirstD2HFisSend
1406 && pAhciPort->pDrvBase)
1407 {
1408#ifndef IN_RING3
1409 return VINF_IOM_R3_MMIO_WRITE;
1410#else
1411 ahciPostFirstD2HFisIntoMemory(pAhciPort);
1412 pAhciPort->fFirstD2HFisSend = true;
1413#endif
1414 }
1415 }
1416 else if (!(u32Value & AHCI_PORT_CMD_FRE))
1417 {
1418 ahciLog(("%s: FIS receive disabled\n", __FUNCTION__));
1419 u32Value &= ~AHCI_PORT_CMD_FR;
1420 }
1421
1422 pAhciPort->regCMD = u32Value;
1423
1424 return VINF_SUCCESS;
1425}
1426
1427/**
1428 * Read from the port interrupt enable register.
1429 */
1430static int PortIntrEnable_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1431{
1432 RT_NOREF2(pAhci, iReg);
1433 ahciLog(("%s: read regIE=%#010x\n", __FUNCTION__, pAhciPort->regIE));
1434 ahciLog(("%s: CPDE=%d TFEE=%d HBFE=%d HBDE=%d IFE=%d INFE=%d OFE=%d IPME=%d PRCE=%d DIE=%d PCE=%d DPE=%d UFE=%d SDBE=%d DSE=%d PSE=%d DHRE=%d\n",
1435 __FUNCTION__, (pAhciPort->regIE & AHCI_PORT_IE_CPDE) >> 31, (pAhciPort->regIE & AHCI_PORT_IE_TFEE) >> 30,
1436 (pAhciPort->regIE & AHCI_PORT_IE_HBFE) >> 29, (pAhciPort->regIE & AHCI_PORT_IE_HBDE) >> 28,
1437 (pAhciPort->regIE & AHCI_PORT_IE_IFE) >> 27, (pAhciPort->regIE & AHCI_PORT_IE_INFE) >> 26,
1438 (pAhciPort->regIE & AHCI_PORT_IE_OFE) >> 24, (pAhciPort->regIE & AHCI_PORT_IE_IPME) >> 23,
1439 (pAhciPort->regIE & AHCI_PORT_IE_PRCE) >> 22, (pAhciPort->regIE & AHCI_PORT_IE_DIE) >> 7,
1440 (pAhciPort->regIE & AHCI_PORT_IE_PCE) >> 6, (pAhciPort->regIE & AHCI_PORT_IE_DPE) >> 5,
1441 (pAhciPort->regIE & AHCI_PORT_IE_UFE) >> 4, (pAhciPort->regIE & AHCI_PORT_IE_SDBE) >> 3,
1442 (pAhciPort->regIE & AHCI_PORT_IE_DSE) >> 2, (pAhciPort->regIE & AHCI_PORT_IE_PSE) >> 1,
1443 (pAhciPort->regIE & AHCI_PORT_IE_DHRE)));
1444 *pu32Value = pAhciPort->regIE;
1445 return VINF_SUCCESS;
1446}
1447
1448/**
1449 * Write to the port interrupt enable register.
1450 */
1451static int PortIntrEnable_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1452{
1453 RT_NOREF1(iReg);
1454 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1455 ahciLog(("%s: CPDE=%d TFEE=%d HBFE=%d HBDE=%d IFE=%d INFE=%d OFE=%d IPME=%d PRCE=%d DIE=%d PCE=%d DPE=%d UFE=%d SDBE=%d DSE=%d PSE=%d DHRE=%d\n",
1456 __FUNCTION__, (u32Value & AHCI_PORT_IE_CPDE) >> 31, (u32Value & AHCI_PORT_IE_TFEE) >> 30,
1457 (u32Value & AHCI_PORT_IE_HBFE) >> 29, (u32Value & AHCI_PORT_IE_HBDE) >> 28,
1458 (u32Value & AHCI_PORT_IE_IFE) >> 27, (u32Value & AHCI_PORT_IE_INFE) >> 26,
1459 (u32Value & AHCI_PORT_IE_OFE) >> 24, (u32Value & AHCI_PORT_IE_IPME) >> 23,
1460 (u32Value & AHCI_PORT_IE_PRCE) >> 22, (u32Value & AHCI_PORT_IE_DIE) >> 7,
1461 (u32Value & AHCI_PORT_IE_PCE) >> 6, (u32Value & AHCI_PORT_IE_DPE) >> 5,
1462 (u32Value & AHCI_PORT_IE_UFE) >> 4, (u32Value & AHCI_PORT_IE_SDBE) >> 3,
1463 (u32Value & AHCI_PORT_IE_DSE) >> 2, (u32Value & AHCI_PORT_IE_PSE) >> 1,
1464 (u32Value & AHCI_PORT_IE_DHRE)));
1465
1466 u32Value &= AHCI_PORT_IE_READONLY;
1467
1468 /* Check if some a interrupt status bit changed*/
1469 uint32_t u32IntrStatus = ASMAtomicReadU32(&pAhciPort->regIS);
1470
1471 int rc = VINF_SUCCESS;
1472 if (u32Value & u32IntrStatus)
1473 rc = ahciHbaSetInterrupt(pAhci, pAhciPort->iLUN, VINF_IOM_R3_MMIO_WRITE);
1474
1475 if (rc == VINF_SUCCESS)
1476 pAhciPort->regIE = u32Value;
1477
1478 return rc;
1479}
1480
1481/**
1482 * Read from the port interrupt status register.
1483 */
1484static int PortIntrSts_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1485{
1486 RT_NOREF2(pAhci, iReg);
1487 ahciLog(("%s: read regIS=%#010x\n", __FUNCTION__, pAhciPort->regIS));
1488 ahciLog(("%s: CPDS=%d TFES=%d HBFS=%d HBDS=%d IFS=%d INFS=%d OFS=%d IPMS=%d PRCS=%d DIS=%d PCS=%d DPS=%d UFS=%d SDBS=%d DSS=%d PSS=%d DHRS=%d\n",
1489 __FUNCTION__, (pAhciPort->regIS & AHCI_PORT_IS_CPDS) >> 31, (pAhciPort->regIS & AHCI_PORT_IS_TFES) >> 30,
1490 (pAhciPort->regIS & AHCI_PORT_IS_HBFS) >> 29, (pAhciPort->regIS & AHCI_PORT_IS_HBDS) >> 28,
1491 (pAhciPort->regIS & AHCI_PORT_IS_IFS) >> 27, (pAhciPort->regIS & AHCI_PORT_IS_INFS) >> 26,
1492 (pAhciPort->regIS & AHCI_PORT_IS_OFS) >> 24, (pAhciPort->regIS & AHCI_PORT_IS_IPMS) >> 23,
1493 (pAhciPort->regIS & AHCI_PORT_IS_PRCS) >> 22, (pAhciPort->regIS & AHCI_PORT_IS_DIS) >> 7,
1494 (pAhciPort->regIS & AHCI_PORT_IS_PCS) >> 6, (pAhciPort->regIS & AHCI_PORT_IS_DPS) >> 5,
1495 (pAhciPort->regIS & AHCI_PORT_IS_UFS) >> 4, (pAhciPort->regIS & AHCI_PORT_IS_SDBS) >> 3,
1496 (pAhciPort->regIS & AHCI_PORT_IS_DSS) >> 2, (pAhciPort->regIS & AHCI_PORT_IS_PSS) >> 1,
1497 (pAhciPort->regIS & AHCI_PORT_IS_DHRS)));
1498 *pu32Value = pAhciPort->regIS;
1499 return VINF_SUCCESS;
1500}
1501
1502/**
1503 * Write to the port interrupt status register.
1504 */
1505static int PortIntrSts_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1506{
1507 RT_NOREF2(pAhci, iReg);
1508 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1509 ASMAtomicAndU32(&pAhciPort->regIS, ~(u32Value & AHCI_PORT_IS_READONLY));
1510
1511 return VINF_SUCCESS;
1512}
1513
1514/**
1515 * Read from the port FIS base address upper 32bit register.
1516 */
1517static int PortFisAddrUp_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1518{
1519 RT_NOREF2(pAhci, iReg);
1520 ahciLog(("%s: read regFBU=%#010x\n", __FUNCTION__, pAhciPort->regFBU));
1521 *pu32Value = pAhciPort->regFBU;
1522 return VINF_SUCCESS;
1523}
1524
1525/**
1526 * Write to the port FIS base address upper 32bit register.
1527 */
1528static int PortFisAddrUp_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1529{
1530 RT_NOREF2(pAhci, iReg);
1531 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1532
1533 pAhciPort->regFBU = u32Value;
1534 pAhciPort->GCPhysAddrFb = AHCI_RTGCPHYS_FROM_U32(pAhciPort->regFBU, pAhciPort->regFB);
1535
1536 return VINF_SUCCESS;
1537}
1538
1539/**
1540 * Read from the port FIS base address register.
1541 */
1542static int PortFisAddr_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1543{
1544 RT_NOREF2(pAhci, iReg);
1545 ahciLog(("%s: read regFB=%#010x\n", __FUNCTION__, pAhciPort->regFB));
1546 *pu32Value = pAhciPort->regFB;
1547 return VINF_SUCCESS;
1548}
1549
1550/**
1551 * Write to the port FIS base address register.
1552 */
1553static int PortFisAddr_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1554{
1555 RT_NOREF2(pAhci, iReg);
1556 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1557
1558 Assert(!(u32Value & ~AHCI_PORT_FB_RESERVED));
1559
1560 pAhciPort->regFB = (u32Value & AHCI_PORT_FB_RESERVED);
1561 pAhciPort->GCPhysAddrFb = AHCI_RTGCPHYS_FROM_U32(pAhciPort->regFBU, pAhciPort->regFB);
1562
1563 return VINF_SUCCESS;
1564}
1565
1566/**
1567 * Write to the port command list base address upper 32bit register.
1568 */
1569static int PortCmdLstAddrUp_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1570{
1571 RT_NOREF2(pAhci, iReg);
1572 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1573
1574 pAhciPort->regCLBU = u32Value;
1575 pAhciPort->GCPhysAddrClb = AHCI_RTGCPHYS_FROM_U32(pAhciPort->regCLBU, pAhciPort->regCLB);
1576
1577 return VINF_SUCCESS;
1578}
1579
1580/**
1581 * Read from the port command list base address upper 32bit register.
1582 */
1583static int PortCmdLstAddrUp_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1584{
1585 RT_NOREF2(pAhci, iReg);
1586 ahciLog(("%s: read regCLBU=%#010x\n", __FUNCTION__, pAhciPort->regCLBU));
1587 *pu32Value = pAhciPort->regCLBU;
1588 return VINF_SUCCESS;
1589}
1590
1591/**
1592 * Read from the port command list base address register.
1593 */
1594static int PortCmdLstAddr_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1595{
1596 RT_NOREF2(pAhci, iReg);
1597 ahciLog(("%s: read regCLB=%#010x\n", __FUNCTION__, pAhciPort->regCLB));
1598 *pu32Value = pAhciPort->regCLB;
1599 return VINF_SUCCESS;
1600}
1601
1602/**
1603 * Write to the port command list base address register.
1604 */
1605static int PortCmdLstAddr_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1606{
1607 RT_NOREF2(pAhci, iReg);
1608 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1609
1610 Assert(!(u32Value & ~AHCI_PORT_CLB_RESERVED));
1611
1612 pAhciPort->regCLB = (u32Value & AHCI_PORT_CLB_RESERVED);
1613 pAhciPort->GCPhysAddrClb = AHCI_RTGCPHYS_FROM_U32(pAhciPort->regCLBU, pAhciPort->regCLB);
1614
1615 return VINF_SUCCESS;
1616}
1617
1618/**
1619 * Read from the global Version register.
1620 */
1621static int HbaVersion_r(PAHCI pAhci, uint32_t iReg, uint32_t *pu32Value)
1622{
1623 RT_NOREF1(iReg);
1624 Log(("%s: read regHbaVs=%#010x\n", __FUNCTION__, pAhci->regHbaVs));
1625 *pu32Value = pAhci->regHbaVs;
1626 return VINF_SUCCESS;
1627}
1628
1629/**
1630 * Read from the global Ports implemented register.
1631 */
1632static int HbaPortsImplemented_r(PAHCI pAhci, uint32_t iReg, uint32_t *pu32Value)
1633{
1634 RT_NOREF1(iReg);
1635 Log(("%s: read regHbaPi=%#010x\n", __FUNCTION__, pAhci->regHbaPi));
1636 *pu32Value = pAhci->regHbaPi;
1637 return VINF_SUCCESS;
1638}
1639
1640/**
1641 * Write to the global interrupt status register.
1642 */
1643static int HbaInterruptStatus_w(PAHCI pAhci, uint32_t iReg, uint32_t u32Value)
1644{
1645 RT_NOREF1(iReg);
1646 Log(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1647
1648 int rc = PDMCritSectEnter(&pAhci->lock, VINF_IOM_R3_MMIO_WRITE);
1649 if (rc != VINF_SUCCESS)
1650 return rc;
1651
1652 pAhci->regHbaIs &= ~(u32Value);
1653
1654 /*
1655 * Update interrupt status register and check for ports who
1656 * set the interrupt inbetween.
1657 */
1658 bool fClear = true;
1659 pAhci->regHbaIs |= ASMAtomicXchgU32(&pAhci->u32PortsInterrupted, 0);
1660 if (!pAhci->regHbaIs)
1661 {
1662 unsigned i = 0;
1663
1664 /* Check if the cleared ports have a interrupt status bit set. */
1665 while ((u32Value > 0) && (i < AHCI_MAX_NR_PORTS_IMPL))
1666 {
1667 if (u32Value & 0x01)
1668 {
1669 PAHCIPort pAhciPort = &pAhci->ahciPort[i];
1670
1671 if (pAhciPort->regIE & pAhciPort->regIS)
1672 {
1673 Log(("%s: Interrupt status of port %u set -> Set interrupt again\n", __FUNCTION__, i));
1674 ASMAtomicOrU32(&pAhci->u32PortsInterrupted, 1 << i);
1675 fClear = false;
1676 break;
1677 }
1678 }
1679 u32Value >>= 1;
1680 i++;
1681 }
1682 }
1683 else
1684 fClear = false;
1685
1686 if (fClear)
1687 ahciHbaClearInterrupt(pAhci);
1688 else
1689 {
1690 Log(("%s: Not clearing interrupt: u32PortsInterrupted=%#010x\n", __FUNCTION__, pAhci->u32PortsInterrupted));
1691 /*
1692 * We need to set the interrupt again because the I/O APIC does not set it again even if the
1693 * line is still high.
1694 * We need to clear it first because the PCI bus only calls the interrupt controller if the state changes.
1695 */
1696 PDMDevHlpPCISetIrq(pAhci->CTX_SUFF(pDevIns), 0, 0);
1697 PDMDevHlpPCISetIrq(pAhci->CTX_SUFF(pDevIns), 0, 1);
1698 }
1699
1700 PDMCritSectLeave(&pAhci->lock);
1701 return VINF_SUCCESS;
1702}
1703
1704/**
1705 * Read from the global interrupt status register.
1706 */
1707static int HbaInterruptStatus_r(PAHCI pAhci, uint32_t iReg, uint32_t *pu32Value)
1708{
1709 RT_NOREF1(iReg);
1710
1711 int rc = PDMCritSectEnter(&pAhci->lock, VINF_IOM_R3_MMIO_READ);
1712 if (rc != VINF_SUCCESS)
1713 return rc;
1714
1715 uint32_t u32PortsInterrupted = ASMAtomicXchgU32(&pAhci->u32PortsInterrupted, 0);
1716
1717 PDMCritSectLeave(&pAhci->lock);
1718 Log(("%s: read regHbaIs=%#010x u32PortsInterrupted=%#010x\n", __FUNCTION__, pAhci->regHbaIs, u32PortsInterrupted));
1719
1720 pAhci->regHbaIs |= u32PortsInterrupted;
1721
1722#ifdef LOG_ENABLED
1723 Log(("%s:", __FUNCTION__));
1724 unsigned i;
1725 for (i = 0; i < pAhci->cPortsImpl; i++)
1726 {
1727 if ((pAhci->regHbaIs >> i) & 0x01)
1728 Log((" P%d", i));
1729 }
1730 Log(("\n"));
1731#endif
1732
1733 *pu32Value = pAhci->regHbaIs;
1734
1735 return VINF_SUCCESS;
1736}
1737
1738/**
1739 * Write to the global control register.
1740 */
1741static int HbaControl_w(PAHCI pAhci, uint32_t iReg, uint32_t u32Value)
1742{
1743 RT_NOREF1(iReg);
1744 Log(("%s: write u32Value=%#010x\n"
1745 "%s: AE=%d IE=%d HR=%d\n",
1746 __FUNCTION__, u32Value,
1747 __FUNCTION__, (u32Value & AHCI_HBA_CTRL_AE) >> 31, (u32Value & AHCI_HBA_CTRL_IE) >> 1,
1748 (u32Value & AHCI_HBA_CTRL_HR)));
1749
1750#ifndef IN_RING3
1751 RT_NOREF2(pAhci, u32Value);
1752 return VINF_IOM_R3_MMIO_WRITE;
1753#else
1754 /*
1755 * Increase the active thread counter because we might set the host controller
1756 * reset bit.
1757 */
1758 ASMAtomicIncU32(&pAhci->cThreadsActive);
1759 ASMAtomicWriteU32(&pAhci->regHbaCtrl, (u32Value & AHCI_HBA_CTRL_RW_MASK) | AHCI_HBA_CTRL_AE);
1760
1761 /*
1762 * Do the HBA reset if requested and there is no other active thread at the moment,
1763 * the work is deferred to the last active thread otherwise.
1764 */
1765 uint32_t cThreadsActive = ASMAtomicDecU32(&pAhci->cThreadsActive);
1766 if ( (u32Value & AHCI_HBA_CTRL_HR)
1767 && !cThreadsActive)
1768 ahciHBAReset(pAhci);
1769
1770 return VINF_SUCCESS;
1771#endif
1772}
1773
1774/**
1775 * Read the global control register.
1776 */
1777static int HbaControl_r(PAHCI pAhci, uint32_t iReg, uint32_t *pu32Value)
1778{
1779 RT_NOREF1(iReg);
1780 Log(("%s: read regHbaCtrl=%#010x\n"
1781 "%s: AE=%d IE=%d HR=%d\n",
1782 __FUNCTION__, pAhci->regHbaCtrl,
1783 __FUNCTION__, (pAhci->regHbaCtrl & AHCI_HBA_CTRL_AE) >> 31, (pAhci->regHbaCtrl & AHCI_HBA_CTRL_IE) >> 1,
1784 (pAhci->regHbaCtrl & AHCI_HBA_CTRL_HR)));
1785 *pu32Value = pAhci->regHbaCtrl;
1786 return VINF_SUCCESS;
1787}
1788
1789/**
1790 * Read the global capabilities register.
1791 */
1792static int HbaCapabilities_r(PAHCI pAhci, uint32_t iReg, uint32_t *pu32Value)
1793{
1794 RT_NOREF1(iReg);
1795 Log(("%s: read regHbaCap=%#010x\n"
1796 "%s: S64A=%d SNCQ=%d SIS=%d SSS=%d SALP=%d SAL=%d SCLO=%d ISS=%d SNZO=%d SAM=%d SPM=%d PMD=%d SSC=%d PSC=%d NCS=%d NP=%d\n",
1797 __FUNCTION__, pAhci->regHbaCap,
1798 __FUNCTION__, (pAhci->regHbaCap & AHCI_HBA_CAP_S64A) >> 31, (pAhci->regHbaCap & AHCI_HBA_CAP_SNCQ) >> 30,
1799 (pAhci->regHbaCap & AHCI_HBA_CAP_SIS) >> 28, (pAhci->regHbaCap & AHCI_HBA_CAP_SSS) >> 27,
1800 (pAhci->regHbaCap & AHCI_HBA_CAP_SALP) >> 26, (pAhci->regHbaCap & AHCI_HBA_CAP_SAL) >> 25,
1801 (pAhci->regHbaCap & AHCI_HBA_CAP_SCLO) >> 24, (pAhci->regHbaCap & AHCI_HBA_CAP_ISS) >> 20,
1802 (pAhci->regHbaCap & AHCI_HBA_CAP_SNZO) >> 19, (pAhci->regHbaCap & AHCI_HBA_CAP_SAM) >> 18,
1803 (pAhci->regHbaCap & AHCI_HBA_CAP_SPM) >> 17, (pAhci->regHbaCap & AHCI_HBA_CAP_PMD) >> 15,
1804 (pAhci->regHbaCap & AHCI_HBA_CAP_SSC) >> 14, (pAhci->regHbaCap & AHCI_HBA_CAP_PSC) >> 13,
1805 (pAhci->regHbaCap & AHCI_HBA_CAP_NCS) >> 8, (pAhci->regHbaCap & AHCI_HBA_CAP_NP)));
1806 *pu32Value = pAhci->regHbaCap;
1807 return VINF_SUCCESS;
1808}
1809
1810/**
1811 * Write to the global command completion coalescing control register.
1812 */
1813static int HbaCccCtl_w(PAHCI pAhci, uint32_t iReg, uint32_t u32Value)
1814{
1815 RT_NOREF1(iReg);
1816 Log(("%s: write u32Value=%#010x\n"
1817 "%s: TV=%d CC=%d INT=%d EN=%d\n",
1818 __FUNCTION__, u32Value,
1819 __FUNCTION__, AHCI_HBA_CCC_CTL_TV_GET(u32Value), AHCI_HBA_CCC_CTL_CC_GET(u32Value),
1820 AHCI_HBA_CCC_CTL_INT_GET(u32Value), (u32Value & AHCI_HBA_CCC_CTL_EN)));
1821
1822 pAhci->regHbaCccCtl = u32Value;
1823 pAhci->uCccTimeout = AHCI_HBA_CCC_CTL_TV_GET(u32Value);
1824 pAhci->uCccPortNr = AHCI_HBA_CCC_CTL_INT_GET(u32Value);
1825 pAhci->uCccNr = AHCI_HBA_CCC_CTL_CC_GET(u32Value);
1826
1827 if (u32Value & AHCI_HBA_CCC_CTL_EN)
1828 TMTimerSetMillies(pAhci->CTX_SUFF(pHbaCccTimer), pAhci->uCccTimeout); /* Arm the timer */
1829 else
1830 TMTimerStop(pAhci->CTX_SUFF(pHbaCccTimer));
1831
1832 return VINF_SUCCESS;
1833}
1834
1835/**
1836 * Read the global command completion coalescing control register.
1837 */
1838static int HbaCccCtl_r(PAHCI pAhci, uint32_t iReg, uint32_t *pu32Value)
1839{
1840 RT_NOREF1(iReg);
1841 Log(("%s: read regHbaCccCtl=%#010x\n"
1842 "%s: TV=%d CC=%d INT=%d EN=%d\n",
1843 __FUNCTION__, pAhci->regHbaCccCtl,
1844 __FUNCTION__, AHCI_HBA_CCC_CTL_TV_GET(pAhci->regHbaCccCtl), AHCI_HBA_CCC_CTL_CC_GET(pAhci->regHbaCccCtl),
1845 AHCI_HBA_CCC_CTL_INT_GET(pAhci->regHbaCccCtl), (pAhci->regHbaCccCtl & AHCI_HBA_CCC_CTL_EN)));
1846 *pu32Value = pAhci->regHbaCccCtl;
1847 return VINF_SUCCESS;
1848}
1849
1850/**
1851 * Write to the global command completion coalescing ports register.
1852 */
1853static int HbaCccPorts_w(PAHCI pAhci, uint32_t iReg, uint32_t u32Value)
1854{
1855 RT_NOREF1(iReg);
1856 Log(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1857
1858 pAhci->regHbaCccPorts = u32Value;
1859
1860 return VINF_SUCCESS;
1861}
1862
1863/**
1864 * Read the global command completion coalescing ports register.
1865 */
1866static int HbaCccPorts_r(PAHCI pAhci, uint32_t iReg, uint32_t *pu32Value)
1867{
1868 RT_NOREF1(iReg);
1869 Log(("%s: read regHbaCccPorts=%#010x\n", __FUNCTION__, pAhci->regHbaCccPorts));
1870
1871#ifdef LOG_ENABLED
1872 Log(("%s:", __FUNCTION__));
1873 unsigned i;
1874 for (i = 0; i < pAhci->cPortsImpl; i++)
1875 {
1876 if ((pAhci->regHbaCccPorts >> i) & 0x01)
1877 Log((" P%d", i));
1878 }
1879 Log(("\n"));
1880#endif
1881
1882 *pu32Value = pAhci->regHbaCccPorts;
1883 return VINF_SUCCESS;
1884}
1885
1886/**
1887 * Invalid write to global register
1888 */
1889static int HbaInvalid_w(PAHCI pAhci, uint32_t iReg, uint32_t u32Value)
1890{
1891 RT_NOREF3(pAhci, iReg, u32Value);
1892 Log(("%s: Write denied!!! iReg=%u u32Value=%#010x\n", __FUNCTION__, iReg, u32Value));
1893 return VINF_SUCCESS;
1894}
1895
1896/**
1897 * Invalid Port write.
1898 */
1899static int PortInvalid_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1900{
1901 RT_NOREF4(pAhci, pAhciPort, iReg, u32Value);
1902 ahciLog(("%s: Write denied!!! iReg=%u u32Value=%#010x\n", __FUNCTION__, iReg, u32Value));
1903 return VINF_SUCCESS;
1904}
1905
1906/**
1907 * Invalid Port read.
1908 */
1909static int PortInvalid_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1910{
1911 RT_NOREF4(pAhci, pAhciPort, iReg, pu32Value);
1912 ahciLog(("%s: Read denied!!! iReg=%u\n", __FUNCTION__, iReg));
1913 return VINF_SUCCESS;
1914}
1915
1916/**
1917 * Register descriptor table for global HBA registers
1918 */
1919static const AHCIOPREG g_aOpRegs[] =
1920{
1921 {"HbaCapabilites", HbaCapabilities_r, HbaInvalid_w}, /* Readonly */
1922 {"HbaControl" , HbaControl_r, HbaControl_w},
1923 {"HbaInterruptStatus", HbaInterruptStatus_r, HbaInterruptStatus_w},
1924 {"HbaPortsImplemented", HbaPortsImplemented_r, HbaInvalid_w}, /* Readonly */
1925 {"HbaVersion", HbaVersion_r, HbaInvalid_w}, /* ReadOnly */
1926 {"HbaCccCtl", HbaCccCtl_r, HbaCccCtl_w},
1927 {"HbaCccPorts", HbaCccPorts_r, HbaCccPorts_w},
1928};
1929
1930/**
1931 * Register descriptor table for port registers
1932 */
1933static const AHCIPORTOPREG g_aPortOpRegs[] =
1934{
1935 {"PortCmdLstAddr", PortCmdLstAddr_r, PortCmdLstAddr_w},
1936 {"PortCmdLstAddrUp", PortCmdLstAddrUp_r, PortCmdLstAddrUp_w},
1937 {"PortFisAddr", PortFisAddr_r, PortFisAddr_w},
1938 {"PortFisAddrUp", PortFisAddrUp_r, PortFisAddrUp_w},
1939 {"PortIntrSts", PortIntrSts_r, PortIntrSts_w},
1940 {"PortIntrEnable", PortIntrEnable_r, PortIntrEnable_w},
1941 {"PortCmd", PortCmd_r, PortCmd_w},
1942 {"PortReserved1", PortInvalid_r, PortInvalid_w}, /* Not used. */
1943 {"PortTaskFileData", PortTaskFileData_r, PortInvalid_w}, /* Readonly */
1944 {"PortSignature", PortSignature_r, PortInvalid_w}, /* Readonly */
1945 {"PortSStatus", PortSStatus_r, PortInvalid_w}, /* Readonly */
1946 {"PortSControl", PortSControl_r, PortSControl_w},
1947 {"PortSError", PortSError_r, PortSError_w},
1948 {"PortSActive", PortSActive_r, PortSActive_w},
1949 {"PortCmdIssue", PortCmdIssue_r, PortCmdIssue_w},
1950 {"PortReserved2", PortInvalid_r, PortInvalid_w}, /* Not used. */
1951};
1952
1953#ifdef IN_RING3
1954/**
1955 * Reset initiated by system software for one port.
1956 *
1957 * @param pAhciPort The port to reset.
1958 */
1959static void ahciPortSwReset(PAHCIPort pAhciPort)
1960{
1961 bool fAllTasksCanceled;
1962
1963 /* Cancel all tasks first. */
1964 fAllTasksCanceled = ahciCancelActiveTasks(pAhciPort);
1965 Assert(fAllTasksCanceled);
1966
1967 Assert(pAhciPort->cTasksActive == 0);
1968
1969 pAhciPort->regIS = 0;
1970 pAhciPort->regIE = 0;
1971 pAhciPort->regCMD = AHCI_PORT_CMD_CPD | /* Cold presence detection */
1972 AHCI_PORT_CMD_SUD | /* Device has spun up. */
1973 AHCI_PORT_CMD_POD; /* Port is powered on. */
1974
1975 /* Hotplugging supported?. */
1976 if (pAhciPort->fHotpluggable)
1977 pAhciPort->regCMD |= AHCI_PORT_CMD_HPCP;
1978
1979 pAhciPort->regTFD = (1 << 8) | ATA_STAT_SEEK | ATA_STAT_WRERR;
1980 pAhciPort->regSIG = UINT32_MAX;
1981 pAhciPort->regSSTS = 0;
1982 pAhciPort->regSCTL = 0;
1983 pAhciPort->regSERR = 0;
1984 pAhciPort->regSACT = 0;
1985 pAhciPort->regCI = 0;
1986
1987 pAhciPort->fResetDevice = false;
1988 pAhciPort->fPoweredOn = true;
1989 pAhciPort->fSpunUp = true;
1990 pAhciPort->cMultSectors = ATA_MAX_MULT_SECTORS;
1991 pAhciPort->uATATransferMode = ATA_MODE_UDMA | 6;
1992
1993 pAhciPort->u32TasksNew = 0;
1994 pAhciPort->u32TasksRedo = 0;
1995 pAhciPort->u32TasksFinished = 0;
1996 pAhciPort->u32QueuedTasksFinished = 0;
1997 pAhciPort->u32CurrentCommandSlot = 0;
1998
1999 if (pAhciPort->pDrvBase)
2000 {
2001 pAhciPort->regCMD |= AHCI_PORT_CMD_CPS; /* Indicate that there is a device on that port */
2002
2003 if (pAhciPort->fPoweredOn)
2004 {
2005 /*
2006 * Set states in the Port Signature and SStatus registers.
2007 */
2008 if (pAhciPort->fATAPI)
2009 pAhciPort->regSIG = AHCI_PORT_SIG_ATAPI;
2010 else
2011 pAhciPort->regSIG = AHCI_PORT_SIG_DISK;
2012 pAhciPort->regSSTS = (0x01 << 8) | /* Interface is active. */
2013 (0x02 << 4) | /* Generation 2 (3.0GBps) speed. */
2014 (0x03 << 0); /* Device detected and communication established. */
2015 }
2016 }
2017}
2018
2019/**
2020 * Hardware reset used for machine power on and reset.
2021 *
2022 * @param pAhciPort The port to reset.
2023 */
2024static void ahciPortHwReset(PAHCIPort pAhciPort)
2025{
2026 /* Reset the address registers. */
2027 pAhciPort->regCLB = 0;
2028 pAhciPort->regCLBU = 0;
2029 pAhciPort->regFB = 0;
2030 pAhciPort->regFBU = 0;
2031
2032 /* Reset calculated addresses. */
2033 pAhciPort->GCPhysAddrClb = 0;
2034 pAhciPort->GCPhysAddrFb = 0;
2035}
2036
2037/**
2038 * Create implemented ports bitmap.
2039 *
2040 * @returns 32bit bitmask with a bit set for every implemented port.
2041 * @param cPorts Number of ports.
2042 */
2043static uint32_t ahciGetPortsImplemented(unsigned cPorts)
2044{
2045 uint32_t uPortsImplemented = 0;
2046
2047 for (unsigned i = 0; i < cPorts; i++)
2048 uPortsImplemented |= (1 << i);
2049
2050 return uPortsImplemented;
2051}
2052
2053/**
2054 * Reset the entire HBA.
2055 *
2056 * @param pThis The HBA state.
2057 */
2058static void ahciHBAReset(PAHCI pThis)
2059{
2060 unsigned i;
2061 int rc = VINF_SUCCESS;
2062
2063 LogRel(("AHCI#%u: Reset the HBA\n", pThis->CTX_SUFF(pDevIns)->iInstance));
2064
2065 /* Stop the CCC timer. */
2066 if (pThis->regHbaCccCtl & AHCI_HBA_CCC_CTL_EN)
2067 {
2068 rc = TMTimerStop(pThis->CTX_SUFF(pHbaCccTimer));
2069 if (RT_FAILURE(rc))
2070 AssertMsgFailed(("%s: Failed to stop timer!\n", __FUNCTION__));
2071 }
2072
2073 /* Reset every port */
2074 for (i = 0; i < pThis->cPortsImpl; i++)
2075 {
2076 PAHCIPort pAhciPort = &pThis->ahciPort[i];
2077
2078 pAhciPort->iLUN = i;
2079 ahciPortSwReset(pAhciPort);
2080 }
2081
2082 /* Init Global registers */
2083 pThis->regHbaCap = AHCI_HBA_CAP_ISS_SHIFT(AHCI_HBA_CAP_ISS_GEN2) |
2084 AHCI_HBA_CAP_S64A | /* 64bit addressing supported */
2085 AHCI_HBA_CAP_SAM | /* AHCI mode only */
2086 AHCI_HBA_CAP_SNCQ | /* Support native command queuing */
2087 AHCI_HBA_CAP_SSS | /* Staggered spin up */
2088 AHCI_HBA_CAP_CCCS | /* Support command completion coalescing */
2089 AHCI_HBA_CAP_NCS_SET(pThis->cCmdSlotsAvail) | /* Number of command slots we support */
2090 AHCI_HBA_CAP_NP_SET(pThis->cPortsImpl); /* Number of supported ports */
2091 pThis->regHbaCtrl = AHCI_HBA_CTRL_AE;
2092 pThis->regHbaPi = ahciGetPortsImplemented(pThis->cPortsImpl);
2093 pThis->regHbaVs = AHCI_HBA_VS_MJR | AHCI_HBA_VS_MNR;
2094 pThis->regHbaCccCtl = 0;
2095 pThis->regHbaCccPorts = 0;
2096 pThis->uCccTimeout = 0;
2097 pThis->uCccPortNr = 0;
2098 pThis->uCccNr = 0;
2099
2100 /* Clear pending interrupts. */
2101 pThis->regHbaIs = 0;
2102 pThis->u32PortsInterrupted = 0;
2103 ahciHbaClearInterrupt(pThis);
2104
2105 pThis->f64BitAddr = false;
2106 pThis->u32PortsInterrupted = 0;
2107 pThis->f8ByteMMIO4BytesWrittenSuccessfully = false;
2108 /* Clear the HBA Reset bit */
2109 pThis->regHbaCtrl &= ~AHCI_HBA_CTRL_HR;
2110}
2111#endif
2112
2113/**
2114 * Reads from a AHCI controller register.
2115 *
2116 * @returns VBox status code.
2117 *
2118 * @param pAhci The AHCI instance.
2119 * @param uReg The register to write.
2120 * @param pv Where to store the result.
2121 * @param cb Number of bytes read.
2122 */
2123static int ahciRegisterRead(PAHCI pAhci, uint32_t uReg, void *pv, unsigned cb)
2124{
2125 int rc = VINF_SUCCESS;
2126 uint32_t iReg;
2127
2128 /*
2129 * If the access offset is smaller than AHCI_HBA_GLOBAL_SIZE the guest accesses the global registers.
2130 * Otherwise it accesses the registers of a port.
2131 */
2132 if (uReg < AHCI_HBA_GLOBAL_SIZE)
2133 {
2134 iReg = uReg >> 2;
2135 Log3(("%s: Trying to read from global register %u\n", __FUNCTION__, iReg));
2136 if (iReg < RT_ELEMENTS(g_aOpRegs))
2137 {
2138 const AHCIOPREG *pReg = &g_aOpRegs[iReg];
2139 rc = pReg->pfnRead(pAhci, iReg, (uint32_t *)pv);
2140 }
2141 else
2142 {
2143 Log3(("%s: Trying to read global register %u/%u!!!\n", __FUNCTION__, iReg, RT_ELEMENTS(g_aOpRegs)));
2144 *(uint32_t *)pv = 0;
2145 }
2146 }
2147 else
2148 {
2149 uint32_t iRegOffset;
2150 uint32_t iPort;
2151
2152 /* Calculate accessed port. */
2153 uReg -= AHCI_HBA_GLOBAL_SIZE;
2154 iPort = uReg / AHCI_PORT_REGISTER_SIZE;
2155 iRegOffset = (uReg % AHCI_PORT_REGISTER_SIZE);
2156 iReg = iRegOffset >> 2;
2157
2158 Log3(("%s: Trying to read from port %u and register %u\n", __FUNCTION__, iPort, iReg));
2159
2160 if (RT_LIKELY( iPort < pAhci->cPortsImpl
2161 && iReg < RT_ELEMENTS(g_aPortOpRegs)))
2162 {
2163 const AHCIPORTOPREG *pPortReg = &g_aPortOpRegs[iReg];
2164 rc = pPortReg->pfnRead(pAhci, &pAhci->ahciPort[iPort], iReg, (uint32_t *)pv);
2165 }
2166 else
2167 {
2168 Log3(("%s: Trying to read port %u register %u/%u!!!\n", __FUNCTION__, iPort, iReg, RT_ELEMENTS(g_aPortOpRegs)));
2169 rc = VINF_IOM_MMIO_UNUSED_00;
2170 }
2171
2172 /*
2173 * Windows Vista tries to read one byte from some registers instead of four.
2174 * Correct the value according to the read size.
2175 */
2176 if (RT_SUCCESS(rc) && cb != sizeof(uint32_t))
2177 {
2178 switch (cb)
2179 {
2180 case 1:
2181 {
2182 uint8_t uNewValue;
2183 uint8_t *p = (uint8_t *)pv;
2184
2185 iRegOffset &= 3;
2186 Log3(("%s: iRegOffset=%u\n", __FUNCTION__, iRegOffset));
2187 uNewValue = p[iRegOffset];
2188 /* Clear old value */
2189 *(uint32_t *)pv = 0;
2190 *(uint8_t *)pv = uNewValue;
2191 break;
2192 }
2193 default:
2194 AssertMsgFailed(("%s: unsupported access width cb=%d iPort=%x iRegOffset=%x iReg=%x!!!\n",
2195 __FUNCTION__, cb, iPort, iRegOffset, iReg));
2196 }
2197 }
2198 }
2199
2200 return rc;
2201}
2202
2203/**
2204 * Writes a value to one of the AHCI controller registers.
2205 *
2206 * @returns VBox status code.
2207 *
2208 * @param pAhci The AHCI instance.
2209 * @param offReg The offset of the register to write to.
2210 * @param u32Value The value to write.
2211 */
2212static int ahciRegisterWrite(PAHCI pAhci, uint32_t offReg, uint32_t u32Value)
2213{
2214 int rc;
2215 uint32_t iReg;
2216
2217 /*
2218 * If the access offset is smaller than 100h the guest accesses the global registers.
2219 * Otherwise it accesses the registers of a port.
2220 */
2221 if (offReg < AHCI_HBA_GLOBAL_SIZE)
2222 {
2223 Log3(("Write global HBA register\n"));
2224 iReg = offReg >> 2;
2225 if (iReg < RT_ELEMENTS(g_aOpRegs))
2226 {
2227 const AHCIOPREG *pReg = &g_aOpRegs[iReg];
2228 rc = pReg->pfnWrite(pAhci, iReg, u32Value);
2229 }
2230 else
2231 {
2232 Log3(("%s: Trying to write global register %u/%u!!!\n", __FUNCTION__, iReg, RT_ELEMENTS(g_aOpRegs)));
2233 rc = VINF_SUCCESS;
2234 }
2235 }
2236 else
2237 {
2238 uint32_t iPort;
2239 Log3(("Write Port register\n"));
2240 /* Calculate accessed port. */
2241 offReg -= AHCI_HBA_GLOBAL_SIZE;
2242 iPort = offReg / AHCI_PORT_REGISTER_SIZE;
2243 iReg = (offReg % AHCI_PORT_REGISTER_SIZE) >> 2;
2244 Log3(("%s: Trying to write to port %u and register %u\n", __FUNCTION__, iPort, iReg));
2245 if (RT_LIKELY( iPort < pAhci->cPortsImpl
2246 && iReg < RT_ELEMENTS(g_aPortOpRegs)))
2247 {
2248 const AHCIPORTOPREG *pPortReg = &g_aPortOpRegs[iReg];
2249 rc = pPortReg->pfnWrite(pAhci, &pAhci->ahciPort[iPort], iReg, u32Value);
2250 }
2251 else
2252 {
2253 Log3(("%s: Trying to write port %u register %u/%u!!!\n", __FUNCTION__, iPort, iReg, RT_ELEMENTS(g_aPortOpRegs)));
2254 rc = VINF_SUCCESS;
2255 }
2256 }
2257
2258 return rc;
2259}
2260
2261/**
2262 * Memory mapped I/O Handler for read operations.
2263 *
2264 * @returns VBox status code.
2265 *
2266 * @param pDevIns The device instance.
2267 * @param pvUser User argument.
2268 * @param GCPhysAddr Physical address (in GC) where the read starts.
2269 * @param pv Where to store the result.
2270 * @param cb Number of bytes read.
2271 */
2272PDMBOTHCBDECL(int) ahciMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2273{
2274 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
2275 Log2(("#%d ahciMMIORead: pvUser=%p:{%.*Rhxs} cb=%d GCPhysAddr=%RGp\n", pDevIns->iInstance, pv, cb, pv, cb, GCPhysAddr));
2276 RT_NOREF1(pvUser);
2277
2278 int rc = ahciRegisterRead(pAhci, GCPhysAddr - pAhci->MMIOBase, pv, cb);
2279
2280 Log2(("#%d ahciMMIORead: return pvUser=%p:{%.*Rhxs} cb=%d GCPhysAddr=%RGp rc=%Rrc\n",
2281 pDevIns->iInstance, pv, cb, pv, cb, GCPhysAddr, rc));
2282 return rc;
2283}
2284
2285
2286/**
2287 * Memory mapped I/O Handler for write operations.
2288 *
2289 * @returns VBox status code.
2290 *
2291 * @param pDevIns The device instance.
2292 * @param pvUser User argument.
2293 * @param GCPhysAddr Physical address (in GC) where the read starts.
2294 * @param pv Where to fetch the result.
2295 * @param cb Number of bytes to write.
2296 */
2297PDMBOTHCBDECL(int) ahciMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
2298{
2299 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
2300 Assert(cb == 4 || cb == 8);
2301 Assert(!(GCPhysAddr & (cb - 1)));
2302
2303 /* Break up 64 bits writes into two dword writes. */
2304 /** @todo Eliminate this code once the IOM/EM starts taking care of these
2305 * situations. */
2306 if (cb == 8)
2307 {
2308 /*
2309 * Only write the first 4 bytes if they weren't already.
2310 * It is possible that the last write to the register caused a world
2311 * switch and we entered this function again.
2312 * Writing the first 4 bytes again could cause indeterminate behavior
2313 * which can cause errors in the guest.
2314 */
2315 int rc = VINF_SUCCESS;
2316 if (!pAhci->f8ByteMMIO4BytesWrittenSuccessfully)
2317 {
2318 rc = ahciMMIOWrite(pDevIns, pvUser, GCPhysAddr, pv, 4);
2319 if (rc != VINF_SUCCESS)
2320 return rc;
2321
2322 pAhci->f8ByteMMIO4BytesWrittenSuccessfully = true;
2323 }
2324
2325 rc = ahciMMIOWrite(pDevIns, pvUser, GCPhysAddr + 4, (uint8_t *)pv + 4, 4);
2326 /*
2327 * Reset flag again so that the first 4 bytes are written again on the next
2328 * 8byte MMIO access.
2329 */
2330 if (rc == VINF_SUCCESS)
2331 pAhci->f8ByteMMIO4BytesWrittenSuccessfully = false;
2332
2333 return rc;
2334 }
2335
2336 /* Do the access. */
2337 Log2(("#%d ahciMMIOWrite: pvUser=%p:{%.*Rhxs} cb=%d GCPhysAddr=%RGp\n", pDevIns->iInstance, pv, cb, pv, cb, GCPhysAddr));
2338 return ahciRegisterWrite(pAhci, GCPhysAddr - pAhci->MMIOBase, *(uint32_t const *)pv);
2339}
2340
2341PDMBOTHCBDECL(int) ahciLegacyFakeWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2342{
2343 RT_NOREF5(pDevIns, pvUser, Port, u32, cb);
2344 AssertMsgFailed(("Should not happen\n"));
2345 return VINF_SUCCESS;
2346}
2347
2348PDMBOTHCBDECL(int) ahciLegacyFakeRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
2349{
2350 RT_NOREF5(pDevIns, pvUser, Port, pu32, cb);
2351 AssertMsgFailed(("Should not happen\n"));
2352 return VINF_SUCCESS;
2353}
2354
2355/**
2356 * I/O port handler for writes to the index/data register pair.
2357 *
2358 * @returns VBox status code.
2359 *
2360 * @param pDevIns The device instance.
2361 * @param pvUser User argument.
2362 * @param Port Port address where the write starts.
2363 * @param u32 Where to fetch the result.
2364 * @param cb Number of bytes to write.
2365 */
2366PDMBOTHCBDECL(int) ahciIdxDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2367{
2368 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
2369 int rc = VINF_SUCCESS;
2370 RT_NOREF2(pvUser, cb);
2371
2372 if (Port - pAhci->IOPortBase >= 8)
2373 {
2374 unsigned iReg = (Port - pAhci->IOPortBase - 8) / 4;
2375
2376 Assert(cb == 4);
2377
2378 if (iReg == 0)
2379 {
2380 /* Write the index register. */
2381 pAhci->regIdx = u32;
2382 }
2383 else
2384 {
2385 /** @todo range check? */
2386 Assert(iReg == 1);
2387 rc = ahciRegisterWrite(pAhci, pAhci->regIdx, u32);
2388 if (rc == VINF_IOM_R3_MMIO_WRITE)
2389 rc = VINF_IOM_R3_IOPORT_WRITE;
2390 }
2391 }
2392 /* else: ignore */
2393
2394 Log2(("#%d ahciIdxDataWrite: pu32=%p:{%.*Rhxs} cb=%d Port=%#x rc=%Rrc\n",
2395 pDevIns->iInstance, &u32, cb, &u32, cb, Port, rc));
2396 return rc;
2397}
2398
2399/**
2400 * I/O port handler for reads from the index/data register pair.
2401 *
2402 * @returns VBox status code.
2403 *
2404 * @param pDevIns The device instance.
2405 * @param pvUser User argument.
2406 * @param Port Port address where the read starts.
2407 * @param pu32 Where to fetch the result.
2408 * @param cb Number of bytes to write.
2409 */
2410PDMBOTHCBDECL(int) ahciIdxDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
2411{
2412 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
2413 int rc = VINF_SUCCESS;
2414 RT_NOREF1(pvUser);
2415
2416 if (Port - pAhci->IOPortBase >= 8)
2417 {
2418 unsigned iReg = (Port - pAhci->IOPortBase - 8) / 4;
2419
2420 Assert(cb == 4);
2421
2422 if (iReg == 0)
2423 {
2424 /* Read the index register. */
2425 *pu32 = pAhci->regIdx;
2426 }
2427 else
2428 {
2429 Assert(iReg == 1);
2430 /** @todo range check? */
2431 rc = ahciRegisterRead(pAhci, pAhci->regIdx, pu32, cb);
2432 if (rc == VINF_IOM_R3_MMIO_READ)
2433 rc = VINF_IOM_R3_IOPORT_READ;
2434 else if (rc == VINF_IOM_MMIO_UNUSED_00)
2435 rc = VERR_IOM_IOPORT_UNUSED;
2436 }
2437 }
2438 else
2439 *pu32 = UINT32_C(0xffffffff);
2440
2441 Log2(("#%d ahciIdxDataRead: pu32=%p:{%.*Rhxs} cb=%d Port=%#x rc=%Rrc\n",
2442 pDevIns->iInstance, pu32, cb, pu32, cb, Port, rc));
2443 return rc;
2444}
2445
2446#ifdef IN_RING3
2447
2448/**
2449 * @callback_method_impl{FNPCIIOREGIONMAP}
2450 */
2451static DECLCALLBACK(int) ahciR3MMIOMap(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, uint32_t iRegion,
2452 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
2453{
2454 RT_NOREF(iRegion, enmType);
2455 PAHCI pThis = PCIDEV_2_PAHCI(pPciDev);
2456
2457 Log2(("%s: registering MMIO area at GCPhysAddr=%RGp cb=%RGp\n", __FUNCTION__, GCPhysAddress, cb));
2458
2459 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
2460 Assert(cb >= 4352);
2461
2462 /* We use the assigned size here, because we currently only support page aligned MMIO ranges. */
2463 /** @todo change this to IOMMMIO_FLAGS_WRITE_ONLY_DWORD once EM/IOM starts
2464 * handling 2nd DWORD failures on split accesses correctly. */
2465 int rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
2466 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_ONLY_DWORD_QWORD,
2467 ahciMMIOWrite, ahciMMIORead, "AHCI");
2468 if (RT_FAILURE(rc))
2469 return rc;
2470
2471 if (pThis->fR0Enabled)
2472 {
2473 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/, "ahciMMIOWrite", "ahciMMIORead");
2474 if (RT_FAILURE(rc))
2475 return rc;
2476 }
2477
2478 if (pThis->fGCEnabled)
2479 {
2480 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/, "ahciMMIOWrite", "ahciMMIORead");
2481 if (RT_FAILURE(rc))
2482 return rc;
2483 }
2484
2485 pThis->MMIOBase = GCPhysAddress;
2486 return rc;
2487}
2488
2489
2490/**
2491 * @callback_method_impl{FNPCIIOREGIONMAP,
2492 * Map the legacy I/O port ranges to make Solaris work with the
2493 * controller.}
2494 */
2495static DECLCALLBACK(int) ahciR3LegacyFakeIORangeMap(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, uint32_t iRegion,
2496 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
2497{
2498 RT_NOREF(iRegion, enmType);
2499 PAHCI pThis = PCIDEV_2_PAHCI(pPciDev);
2500 int rc = VINF_SUCCESS;
2501
2502 Log2(("%s: registering fake I/O area at GCPhysAddr=%RGp cb=%RGp\n", __FUNCTION__, GCPhysAddress, cb));
2503
2504 Assert(enmType == PCI_ADDRESS_SPACE_IO);
2505
2506 /* We use the assigned size here, because we currently only support page aligned MMIO ranges. */
2507 rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, NULL,
2508 ahciLegacyFakeWrite, ahciLegacyFakeRead, NULL, NULL, "AHCI Fake");
2509 if (RT_FAILURE(rc))
2510 return rc;
2511
2512 if (pThis->fR0Enabled)
2513 {
2514 rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
2515 "ahciLegacyFakeWrite", "ahciLegacyFakeRead", NULL, NULL, "AHCI Fake");
2516 if (RT_FAILURE(rc))
2517 return rc;
2518 }
2519
2520 if (pThis->fGCEnabled)
2521 {
2522 rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
2523 "ahciLegacyFakeWrite", "ahciLegacyFakeRead", NULL, NULL, "AHCI Fake");
2524 if (RT_FAILURE(rc))
2525 return rc;
2526 }
2527
2528 return rc;
2529}
2530
2531/**
2532 * @callback_method_impl{FNPCIIOREGIONMAP,
2533 * Map the BMDMA I/O port range (used for the Index/Data pair register access)}
2534 */
2535static DECLCALLBACK(int) ahciR3IdxDataIORangeMap(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, uint32_t iRegion,
2536 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
2537{
2538 RT_NOREF(iRegion, enmType);
2539 PAHCI pThis = PCIDEV_2_PAHCI(pPciDev);
2540 int rc = VINF_SUCCESS;
2541
2542 Log2(("%s: registering fake I/O area at GCPhysAddr=%RGp cb=%RGp\n", __FUNCTION__, GCPhysAddress, cb));
2543
2544 Assert(enmType == PCI_ADDRESS_SPACE_IO);
2545
2546 /* We use the assigned size here, because we currently only support page aligned MMIO ranges. */
2547 rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, NULL,
2548 ahciIdxDataWrite, ahciIdxDataRead, NULL, NULL, "AHCI IDX/DATA");
2549 if (RT_FAILURE(rc))
2550 return rc;
2551
2552 if (pThis->fR0Enabled)
2553 {
2554 rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
2555 "ahciIdxDataWrite", "ahciIdxDataRead", NULL, NULL, "AHCI IDX/DATA");
2556 if (RT_FAILURE(rc))
2557 return rc;
2558 }
2559
2560 if (pThis->fGCEnabled)
2561 {
2562 rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
2563 "ahciIdxDataWrite", "ahciIdxDataRead", NULL, NULL, "AHCI IDX/DATA");
2564 if (RT_FAILURE(rc))
2565 return rc;
2566 }
2567
2568 pThis->IOPortBase = (RTIOPORT)GCPhysAddress;
2569 return rc;
2570}
2571
2572/* -=-=-=-=-=- PAHCI::ILeds -=-=-=-=-=- */
2573
2574/**
2575 * Gets the pointer to the status LED of a unit.
2576 *
2577 * @returns VBox status code.
2578 * @param pInterface Pointer to the interface structure containing the called function pointer.
2579 * @param iLUN The unit which status LED we desire.
2580 * @param ppLed Where to store the LED pointer.
2581 */
2582static DECLCALLBACK(int) ahciR3Status_QueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
2583{
2584 PAHCI pAhci = PDMILEDPORTS_2_PAHCI(pInterface);
2585 if (iLUN < AHCI_MAX_NR_PORTS_IMPL)
2586 {
2587 *ppLed = &pAhci->ahciPort[iLUN].Led;
2588 Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
2589 return VINF_SUCCESS;
2590 }
2591 return VERR_PDM_LUN_NOT_FOUND;
2592}
2593
2594/**
2595 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2596 */
2597static DECLCALLBACK(void *) ahciR3Status_QueryInterface(PPDMIBASE pInterface, const char *pszIID)
2598{
2599 PAHCI pThis = PDMIBASE_2_PAHCI(pInterface);
2600 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
2601 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
2602 return NULL;
2603}
2604
2605/**
2606 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2607 */
2608static DECLCALLBACK(void *) ahciR3PortQueryInterface(PPDMIBASE pInterface, const char *pszIID)
2609{
2610 PAHCIPort pAhciPort = PDMIBASE_2_PAHCIPORT(pInterface);
2611 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pAhciPort->IBase);
2612 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIMEDIAPORT, &pAhciPort->IPort);
2613 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIMEDIAEXPORT, &pAhciPort->IMediaExPort);
2614 return NULL;
2615}
2616
2617/**
2618 * @interface_method_impl{PDMIMEDIAPORT,pfnQueryDeviceLocation}
2619 */
2620static DECLCALLBACK(int) ahciR3PortQueryDeviceLocation(PPDMIMEDIAPORT pInterface, const char **ppcszController,
2621 uint32_t *piInstance, uint32_t *piLUN)
2622{
2623 PAHCIPort pAhciPort = PDMIMEDIAPORT_2_PAHCIPORT(pInterface);
2624 PPDMDEVINS pDevIns = pAhciPort->CTX_SUFF(pDevIns);
2625
2626 AssertPtrReturn(ppcszController, VERR_INVALID_POINTER);
2627 AssertPtrReturn(piInstance, VERR_INVALID_POINTER);
2628 AssertPtrReturn(piLUN, VERR_INVALID_POINTER);
2629
2630 *ppcszController = pDevIns->pReg->szName;
2631 *piInstance = pDevIns->iInstance;
2632 *piLUN = pAhciPort->iLUN;
2633
2634 return VINF_SUCCESS;
2635}
2636
2637#ifdef LOG_ENABLED
2638
2639/**
2640 * Dump info about the FIS
2641 *
2642 * @returns nothing
2643 * @param pAhciPort The port the command FIS was read from.
2644 * @param cmdFis The FIS to print info from.
2645 */
2646static void ahciDumpFisInfo(PAHCIPort pAhciPort, uint8_t *cmdFis)
2647{
2648 ahciLog(("%s: *** Begin FIS info dump. ***\n", __FUNCTION__));
2649 /* Print FIS type. */
2650 switch (cmdFis[AHCI_CMDFIS_TYPE])
2651 {
2652 case AHCI_CMDFIS_TYPE_H2D:
2653 {
2654 ahciLog(("%s: Command Fis type: H2D\n", __FUNCTION__));
2655 ahciLog(("%s: Command Fis size: %d bytes\n", __FUNCTION__, AHCI_CMDFIS_TYPE_H2D_SIZE));
2656 if (cmdFis[AHCI_CMDFIS_BITS] & AHCI_CMDFIS_C)
2657 ahciLog(("%s: Command register update\n", __FUNCTION__));
2658 else
2659 ahciLog(("%s: Control register update\n", __FUNCTION__));
2660 ahciLog(("%s: CMD=%#04x \"%s\"\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CMD], ATACmdText(cmdFis[AHCI_CMDFIS_CMD])));
2661 ahciLog(("%s: FEAT=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_FET]));
2662 ahciLog(("%s: SECTN=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_SECTN]));
2663 ahciLog(("%s: CYLL=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CYLL]));
2664 ahciLog(("%s: CYLH=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CYLH]));
2665 ahciLog(("%s: HEAD=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_HEAD]));
2666
2667 ahciLog(("%s: SECTNEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_SECTNEXP]));
2668 ahciLog(("%s: CYLLEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CYLLEXP]));
2669 ahciLog(("%s: CYLHEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CYLHEXP]));
2670 ahciLog(("%s: FETEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_FETEXP]));
2671
2672 ahciLog(("%s: SECTC=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_SECTC]));
2673 ahciLog(("%s: SECTCEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_SECTCEXP]));
2674 ahciLog(("%s: CTL=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CTL]));
2675 if (cmdFis[AHCI_CMDFIS_CTL] & AHCI_CMDFIS_CTL_SRST)
2676 ahciLog(("%s: Reset bit is set\n", __FUNCTION__));
2677 break;
2678 }
2679 case AHCI_CMDFIS_TYPE_D2H:
2680 {
2681 ahciLog(("%s: Command Fis type D2H\n", __FUNCTION__));
2682 ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_D2H_SIZE));
2683 break;
2684 }
2685 case AHCI_CMDFIS_TYPE_SETDEVBITS:
2686 {
2687 ahciLog(("%s: Command Fis type Set Device Bits\n", __FUNCTION__));
2688 ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_SETDEVBITS_SIZE));
2689 break;
2690 }
2691 case AHCI_CMDFIS_TYPE_DMAACTD2H:
2692 {
2693 ahciLog(("%s: Command Fis type DMA Activate H2D\n", __FUNCTION__));
2694 ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_DMAACTD2H_SIZE));
2695 break;
2696 }
2697 case AHCI_CMDFIS_TYPE_DMASETUP:
2698 {
2699 ahciLog(("%s: Command Fis type DMA Setup\n", __FUNCTION__));
2700 ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_DMASETUP_SIZE));
2701 break;
2702 }
2703 case AHCI_CMDFIS_TYPE_PIOSETUP:
2704 {
2705 ahciLog(("%s: Command Fis type PIO Setup\n", __FUNCTION__));
2706 ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_PIOSETUP_SIZE));
2707 break;
2708 }
2709 case AHCI_CMDFIS_TYPE_DATA:
2710 {
2711 ahciLog(("%s: Command Fis type Data\n", __FUNCTION__));
2712 break;
2713 }
2714 default:
2715 ahciLog(("%s: ERROR Unknown command FIS type\n", __FUNCTION__));
2716 break;
2717 }
2718 ahciLog(("%s: *** End FIS info dump. ***\n", __FUNCTION__));
2719}
2720
2721/**
2722 * Dump info about the command header
2723 *
2724 * @returns nothing
2725 * @param pAhciPort Pointer to the port the command header was read from.
2726 * @param pCmdHdr The command header to print info from.
2727 */
2728static void ahciDumpCmdHdrInfo(PAHCIPort pAhciPort, CmdHdr *pCmdHdr)
2729{
2730 ahciLog(("%s: *** Begin command header info dump. ***\n", __FUNCTION__));
2731 ahciLog(("%s: Number of Scatter/Gatther List entries: %u\n", __FUNCTION__, AHCI_CMDHDR_PRDTL_ENTRIES(pCmdHdr->u32DescInf)));
2732 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_C)
2733 ahciLog(("%s: Clear busy upon R_OK\n", __FUNCTION__));
2734 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_B)
2735 ahciLog(("%s: BIST Fis\n", __FUNCTION__));
2736 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_R)
2737 ahciLog(("%s: Device Reset Fis\n", __FUNCTION__));
2738 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_P)
2739 ahciLog(("%s: Command prefetchable\n", __FUNCTION__));
2740 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_W)
2741 ahciLog(("%s: Device write\n", __FUNCTION__));
2742 else
2743 ahciLog(("%s: Device read\n", __FUNCTION__));
2744 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_A)
2745 ahciLog(("%s: ATAPI command\n", __FUNCTION__));
2746 else
2747 ahciLog(("%s: ATA command\n", __FUNCTION__));
2748
2749 ahciLog(("%s: Command FIS length %u DW\n", __FUNCTION__, (pCmdHdr->u32DescInf & AHCI_CMDHDR_CFL_MASK)));
2750 ahciLog(("%s: *** End command header info dump. ***\n", __FUNCTION__));
2751}
2752
2753#endif /* LOG_ENABLED */
2754
2755/**
2756 * Post the first D2H FIS from the device into guest memory.
2757 *
2758 * @returns nothing
2759 * @param pAhciPort Pointer to the port which "receives" the FIS.
2760 */
2761static void ahciPostFirstD2HFisIntoMemory(PAHCIPort pAhciPort)
2762{
2763 uint8_t d2hFis[AHCI_CMDFIS_TYPE_D2H_SIZE];
2764
2765 pAhciPort->fFirstD2HFisSend = true;
2766
2767 ahciLog(("%s: Sending First D2H FIS from FIFO\n", __FUNCTION__));
2768 memset(&d2hFis[0], 0, sizeof(d2hFis));
2769 d2hFis[AHCI_CMDFIS_TYPE] = AHCI_CMDFIS_TYPE_D2H;
2770 d2hFis[AHCI_CMDFIS_ERR] = 0x01;
2771
2772 d2hFis[AHCI_CMDFIS_STS] = 0x00;
2773
2774 /* Set the signature based on the device type. */
2775 if (pAhciPort->fATAPI)
2776 {
2777 d2hFis[AHCI_CMDFIS_CYLL] = 0x14;
2778 d2hFis[AHCI_CMDFIS_CYLH] = 0xeb;
2779 }
2780 else
2781 {
2782 d2hFis[AHCI_CMDFIS_CYLL] = 0x00;
2783 d2hFis[AHCI_CMDFIS_CYLH] = 0x00;
2784 }
2785
2786 d2hFis[AHCI_CMDFIS_HEAD] = 0x00;
2787 d2hFis[AHCI_CMDFIS_SECTN] = 0x01;
2788 d2hFis[AHCI_CMDFIS_SECTC] = 0x01;
2789
2790 pAhciPort->regTFD = (1 << 8) | ATA_STAT_SEEK | ATA_STAT_WRERR;
2791 if (!pAhciPort->fATAPI)
2792 pAhciPort->regTFD |= ATA_STAT_READY;
2793
2794 ahciPostFisIntoMemory(pAhciPort, AHCI_CMDFIS_TYPE_D2H, d2hFis);
2795}
2796
2797/**
2798 * Post the FIS in the memory area allocated by the guest and set interrupt if necessary.
2799 *
2800 * @returns VBox status code
2801 * @param pAhciPort The port which "receives" the FIS.
2802 * @param uFisType The type of the FIS.
2803 * @param pCmdFis Pointer to the FIS which is to be posted into memory.
2804 */
2805static int ahciPostFisIntoMemory(PAHCIPort pAhciPort, unsigned uFisType, uint8_t *pCmdFis)
2806{
2807 int rc = VINF_SUCCESS;
2808 RTGCPHYS GCPhysAddrRecFis = pAhciPort->GCPhysAddrFb;
2809 unsigned cbFis = 0;
2810
2811 ahciLog(("%s: pAhciPort=%p uFisType=%u pCmdFis=%p\n", __FUNCTION__, pAhciPort, uFisType, pCmdFis));
2812
2813 if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
2814 {
2815 AssertMsg(GCPhysAddrRecFis, ("%s: GCPhysAddrRecFis is 0\n", __FUNCTION__));
2816
2817 /* Determine the offset and size of the FIS based on uFisType. */
2818 switch (uFisType)
2819 {
2820 case AHCI_CMDFIS_TYPE_D2H:
2821 {
2822 GCPhysAddrRecFis += AHCI_RECFIS_RFIS_OFFSET;
2823 cbFis = AHCI_CMDFIS_TYPE_D2H_SIZE;
2824 break;
2825 }
2826 case AHCI_CMDFIS_TYPE_SETDEVBITS:
2827 {
2828 GCPhysAddrRecFis += AHCI_RECFIS_SDBFIS_OFFSET;
2829 cbFis = AHCI_CMDFIS_TYPE_SETDEVBITS_SIZE;
2830 break;
2831 }
2832 case AHCI_CMDFIS_TYPE_DMASETUP:
2833 {
2834 GCPhysAddrRecFis += AHCI_RECFIS_DSFIS_OFFSET;
2835 cbFis = AHCI_CMDFIS_TYPE_DMASETUP_SIZE;
2836 break;
2837 }
2838 case AHCI_CMDFIS_TYPE_PIOSETUP:
2839 {
2840 GCPhysAddrRecFis += AHCI_RECFIS_PSFIS_OFFSET;
2841 cbFis = AHCI_CMDFIS_TYPE_PIOSETUP_SIZE;
2842 break;
2843 }
2844 default:
2845 /*
2846 * We should post the unknown FIS into memory too but this never happens because
2847 * we know which FIS types we generate. ;)
2848 */
2849 AssertMsgFailed(("%s: Unknown FIS type!\n", __FUNCTION__));
2850 }
2851
2852 /* Post the FIS into memory. */
2853 ahciLog(("%s: PDMDevHlpPCIPhysWrite GCPhysAddrRecFis=%RGp cbFis=%u\n", __FUNCTION__, GCPhysAddrRecFis, cbFis));
2854 PDMDevHlpPCIPhysWrite(pAhciPort->CTX_SUFF(pDevIns), GCPhysAddrRecFis, pCmdFis, cbFis);
2855 }
2856
2857 return rc;
2858}
2859
2860DECLINLINE(void) ahciReqSetStatus(PAHCIREQ pAhciReq, uint8_t u8Error, uint8_t u8Status)
2861{
2862 pAhciReq->cmdFis[AHCI_CMDFIS_ERR] = u8Error;
2863 pAhciReq->cmdFis[AHCI_CMDFIS_STS] = u8Status;
2864}
2865
2866static void ataPadString(uint8_t *pbDst, const char *pbSrc, uint32_t cbSize)
2867{
2868 for (uint32_t i = 0; i < cbSize; i++)
2869 {
2870 if (*pbSrc)
2871 pbDst[i ^ 1] = *pbSrc++;
2872 else
2873 pbDst[i ^ 1] = ' ';
2874 }
2875}
2876
2877static uint32_t ataChecksum(void* ptr, size_t count)
2878{
2879 uint8_t u8Sum = 0xa5, *p = (uint8_t*)ptr;
2880 size_t i;
2881
2882 for (i = 0; i < count; i++)
2883 {
2884 u8Sum += *p++;
2885 }
2886
2887 return (uint8_t)-(int32_t)u8Sum;
2888}
2889
2890static int ahciIdentifySS(PAHCIPort pAhciPort, void *pvBuf)
2891{
2892 uint16_t *p = (uint16_t *)pvBuf;
2893 memset(p, 0, 512);
2894 p[0] = RT_H2LE_U16(0x0040);
2895 p[1] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383));
2896 p[3] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cHeads);
2897 /* Block size; obsolete, but required for the BIOS. */
2898 p[5] = RT_H2LE_U16(512);
2899 p[6] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cSectors);
2900 ataPadString((uint8_t *)(p + 10), pAhciPort->szSerialNumber, AHCI_SERIAL_NUMBER_LENGTH); /* serial number */
2901 p[20] = RT_H2LE_U16(3); /* XXX: retired, cache type */
2902 p[21] = RT_H2LE_U16(512); /* XXX: retired, cache size in sectors */
2903 p[22] = RT_H2LE_U16(0); /* ECC bytes per sector */
2904 ataPadString((uint8_t *)(p + 23), pAhciPort->szFirmwareRevision, AHCI_FIRMWARE_REVISION_LENGTH); /* firmware version */
2905 ataPadString((uint8_t *)(p + 27), pAhciPort->szModelNumber, AHCI_MODEL_NUMBER_LENGTH); /* model */
2906#if ATA_MAX_MULT_SECTORS > 1
2907 p[47] = RT_H2LE_U16(0x8000 | ATA_MAX_MULT_SECTORS);
2908#endif
2909 p[48] = RT_H2LE_U16(1); /* dword I/O, used by the BIOS */
2910 p[49] = RT_H2LE_U16(1 << 11 | 1 << 9 | 1 << 8); /* DMA and LBA supported */
2911 p[50] = RT_H2LE_U16(1 << 14); /* No drive specific standby timer minimum */
2912 p[51] = RT_H2LE_U16(240); /* PIO transfer cycle */
2913 p[52] = RT_H2LE_U16(240); /* DMA transfer cycle */
2914 p[53] = RT_H2LE_U16(1 | 1 << 1 | 1 << 2); /* words 54-58,64-70,88 valid */
2915 p[54] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383));
2916 p[55] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cHeads);
2917 p[56] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cSectors);
2918 p[57] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383) * pAhciPort->PCHSGeometry.cHeads * pAhciPort->PCHSGeometry.cSectors);
2919 p[58] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383) * pAhciPort->PCHSGeometry.cHeads * pAhciPort->PCHSGeometry.cSectors >> 16);
2920 if (pAhciPort->cMultSectors)
2921 p[59] = RT_H2LE_U16(0x100 | pAhciPort->cMultSectors);
2922 if (pAhciPort->cTotalSectors <= (1 << 28) - 1)
2923 {
2924 p[60] = RT_H2LE_U16(pAhciPort->cTotalSectors);
2925 p[61] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 16);
2926 }
2927 else
2928 {
2929 /* Report maximum number of sectors possible with LBA28 */
2930 p[60] = RT_H2LE_U16(((1 << 28) - 1) & 0xffff);
2931 p[61] = RT_H2LE_U16(((1 << 28) - 1) >> 16);
2932 }
2933 p[63] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_MDMA, ATA_MDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* MDMA modes supported / mode enabled */
2934 p[64] = RT_H2LE_U16(ATA_PIO_MODE_MAX > 2 ? (1 << (ATA_PIO_MODE_MAX - 2)) - 1 : 0); /* PIO modes beyond PIO2 supported */
2935 p[65] = RT_H2LE_U16(120); /* minimum DMA multiword tx cycle time */
2936 p[66] = RT_H2LE_U16(120); /* recommended DMA multiword tx cycle time */
2937 p[67] = RT_H2LE_U16(120); /* minimum PIO cycle time without flow control */
2938 p[68] = RT_H2LE_U16(120); /* minimum PIO cycle time with IORDY flow control */
2939 if ( pAhciPort->fTrimEnabled
2940 || pAhciPort->cbSector != 512
2941 || pAhciPort->pDrvMedia->pfnIsNonRotational(pAhciPort->pDrvMedia))
2942 {
2943 p[80] = RT_H2LE_U16(0x1f0); /* support everything up to ATA/ATAPI-8 ACS */
2944 p[81] = RT_H2LE_U16(0x28); /* conforms to ATA/ATAPI-8 ACS */
2945 }
2946 else
2947 {
2948 p[80] = RT_H2LE_U16(0x7e); /* support everything up to ATA/ATAPI-6 */
2949 p[81] = RT_H2LE_U16(0x22); /* conforms to ATA/ATAPI-6 */
2950 }
2951 p[82] = RT_H2LE_U16(1 << 3 | 1 << 5 | 1 << 6); /* supports power management, write cache and look-ahead */
2952 p[83] = RT_H2LE_U16(1 << 14 | 1 << 10 | 1 << 12 | 1 << 13); /* supports LBA48, FLUSH CACHE and FLUSH CACHE EXT */
2953 p[84] = RT_H2LE_U16(1 << 14);
2954 p[85] = RT_H2LE_U16(1 << 3 | 1 << 5 | 1 << 6); /* enabled power management, write cache and look-ahead */
2955 p[86] = RT_H2LE_U16(1 << 10 | 1 << 12 | 1 << 13); /* enabled LBA48, FLUSH CACHE and FLUSH CACHE EXT */
2956 p[87] = RT_H2LE_U16(1 << 14);
2957 p[88] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_UDMA, ATA_UDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* UDMA modes supported / mode enabled */
2958 p[93] = RT_H2LE_U16(0x00);
2959 p[100] = RT_H2LE_U16(pAhciPort->cTotalSectors);
2960 p[101] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 16);
2961 p[102] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 32);
2962 p[103] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 48);
2963
2964 /* valid information, more than one logical sector per physical sector, 2^cLogSectorsPerPhysicalExp logical sectors per physical sector */
2965 if (pAhciPort->cLogSectorsPerPhysicalExp)
2966 p[106] = RT_H2LE_U16(RT_BIT(14) | RT_BIT(13) | pAhciPort->cLogSectorsPerPhysicalExp);
2967
2968 if (pAhciPort->cbSector != 512)
2969 {
2970 uint32_t cSectorSizeInWords = pAhciPort->cbSector / sizeof(uint16_t);
2971 /* Enable reporting of logical sector size. */
2972 p[106] |= RT_H2LE_U16(RT_BIT(12) | RT_BIT(14));
2973 p[117] = RT_H2LE_U16(cSectorSizeInWords);
2974 p[118] = RT_H2LE_U16(cSectorSizeInWords >> 16);
2975 }
2976
2977 if (pAhciPort->pDrvMedia->pfnIsNonRotational(pAhciPort->pDrvMedia))
2978 p[217] = RT_H2LE_U16(1); /* Non-rotational medium */
2979
2980 if (pAhciPort->fTrimEnabled) /** @todo Set bit 14 in word 69 too? (Deterministic read after TRIM). */
2981 p[169] = RT_H2LE_U16(1); /* DATA SET MANAGEMENT command supported. */
2982
2983 /* The following are SATA specific */
2984 p[75] = RT_H2LE_U16(pAhciPort->CTX_SUFF(pAhci)->cCmdSlotsAvail-1); /* Number of commands we support, 0's based */
2985 p[76] = RT_H2LE_U16((1 << 8) | (1 << 2)); /* Native command queuing and Serial ATA Gen2 (3.0 Gbps) speed supported */
2986
2987 uint32_t uCsum = ataChecksum(p, 510);
2988 p[255] = RT_H2LE_U16(0xa5 | (uCsum << 8)); /* Integrity word */
2989
2990 return VINF_SUCCESS;
2991}
2992
2993static int ahciR3AtapiIdentify(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
2994{
2995 uint16_t p[256];
2996
2997 memset(p, 0, 512);
2998 /* Removable CDROM, 50us response, 12 byte packets */
2999 p[0] = RT_H2LE_U16(2 << 14 | 5 << 8 | 1 << 7 | 2 << 5 | 0 << 0);
3000 ataPadString((uint8_t *)(p + 10), pAhciPort->szSerialNumber, AHCI_SERIAL_NUMBER_LENGTH); /* serial number */
3001 p[20] = RT_H2LE_U16(3); /* XXX: retired, cache type */
3002 p[21] = RT_H2LE_U16(512); /* XXX: retired, cache size in sectors */
3003 ataPadString((uint8_t *)(p + 23), pAhciPort->szFirmwareRevision, AHCI_FIRMWARE_REVISION_LENGTH); /* firmware version */
3004 ataPadString((uint8_t *)(p + 27), pAhciPort->szModelNumber, AHCI_MODEL_NUMBER_LENGTH); /* model */
3005 p[49] = RT_H2LE_U16(1 << 11 | 1 << 9 | 1 << 8); /* DMA and LBA supported */
3006 p[50] = RT_H2LE_U16(1 << 14); /* No drive specific standby timer minimum */
3007 p[51] = RT_H2LE_U16(240); /* PIO transfer cycle */
3008 p[52] = RT_H2LE_U16(240); /* DMA transfer cycle */
3009 p[53] = RT_H2LE_U16(1 << 1 | 1 << 2); /* words 64-70,88 are valid */
3010 p[63] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_MDMA, ATA_MDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* MDMA modes supported / mode enabled */
3011 p[64] = RT_H2LE_U16(ATA_PIO_MODE_MAX > 2 ? (1 << (ATA_PIO_MODE_MAX - 2)) - 1 : 0); /* PIO modes beyond PIO2 supported */
3012 p[65] = RT_H2LE_U16(120); /* minimum DMA multiword tx cycle time */
3013 p[66] = RT_H2LE_U16(120); /* recommended DMA multiword tx cycle time */
3014 p[67] = RT_H2LE_U16(120); /* minimum PIO cycle time without flow control */
3015 p[68] = RT_H2LE_U16(120); /* minimum PIO cycle time with IORDY flow control */
3016 p[73] = RT_H2LE_U16(0x003e); /* ATAPI CDROM major */
3017 p[74] = RT_H2LE_U16(9); /* ATAPI CDROM minor */
3018 p[80] = RT_H2LE_U16(0x7e); /* support everything up to ATA/ATAPI-6 */
3019 p[81] = RT_H2LE_U16(0x22); /* conforms to ATA/ATAPI-6 */
3020 p[82] = RT_H2LE_U16(1 << 4 | 1 << 9); /* supports packet command set and DEVICE RESET */
3021 p[83] = RT_H2LE_U16(1 << 14);
3022 p[84] = RT_H2LE_U16(1 << 14);
3023 p[85] = RT_H2LE_U16(1 << 4 | 1 << 9); /* enabled packet command set and DEVICE RESET */
3024 p[86] = RT_H2LE_U16(0);
3025 p[87] = RT_H2LE_U16(1 << 14);
3026 p[88] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_UDMA, ATA_UDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* UDMA modes supported / mode enabled */
3027 p[93] = RT_H2LE_U16((1 | 1 << 1) << ((pAhciPort->iLUN & 1) == 0 ? 0 : 8) | 1 << 13 | 1 << 14);
3028
3029 /* The following are SATA specific */
3030 p[75] = RT_H2LE_U16(31); /* We support 32 commands */
3031 p[76] = RT_H2LE_U16((1 << 8) | (1 << 2)); /* Native command queuing and Serial ATA Gen2 (3.0 Gbps) speed supported */
3032
3033 /* Copy the buffer in to the scatter gather list. */
3034 *pcbData = ahciR3CopyBufferToPrdtl(pAhciPort->CTX_SUFF(pAhci), pAhciReq, (void *)&p[0],
3035 RT_MIN(cbData, sizeof(p)), 0 /* cbSkip */);
3036 return VINF_SUCCESS;
3037}
3038
3039/**
3040 * Reset all values after a reset of the attached storage device.
3041 *
3042 * @returns nothing
3043 * @param pAhciPort The port the device is attached to.
3044 * @param pAhciReq The state to get the tag number from.
3045 */
3046static void ahciFinishStorageDeviceReset(PAHCIPort pAhciPort, PAHCIREQ pAhciReq)
3047{
3048 int rc;
3049
3050 /* Send a status good D2H FIS. */
3051 pAhciPort->fResetDevice = false;
3052 if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
3053 ahciPostFirstD2HFisIntoMemory(pAhciPort);
3054
3055 /* As this is the first D2H FIS after the reset update the signature in the SIG register of the port. */
3056 if (pAhciPort->fATAPI)
3057 pAhciPort->regSIG = AHCI_PORT_SIG_ATAPI;
3058 else
3059 pAhciPort->regSIG = AHCI_PORT_SIG_DISK;
3060 ASMAtomicOrU32(&pAhciPort->u32TasksFinished, (1 << pAhciReq->uTag));
3061
3062 rc = ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN, VERR_IGNORED);
3063 AssertRC(rc);
3064}
3065
3066/**
3067 * Initiates a device reset caused by ATA_DEVICE_RESET (ATAPI only).
3068 *
3069 * @returns nothing.
3070 * @param pAhciPort The device to reset.
3071 * @param pAhciReq The task state.
3072 */
3073static void ahciDeviceReset(PAHCIPort pAhciPort, PAHCIREQ pAhciReq)
3074{
3075 ASMAtomicWriteBool(&pAhciPort->fResetDevice, true);
3076
3077 /*
3078 * Because this ATAPI only and ATAPI can't have
3079 * more than one command active at a time the task counter should be 0
3080 * and it is possible to finish the reset now.
3081 */
3082 Assert(ASMAtomicReadU32(&pAhciPort->cTasksActive) == 0);
3083 ahciFinishStorageDeviceReset(pAhciPort, pAhciReq);
3084}
3085
3086/**
3087 * Create a PIO setup FIS and post it into the memory area of the guest.
3088 *
3089 * @returns nothing.
3090 * @param pAhciPort The port of the SATA controller.
3091 * @param cbTransfer Transfer size of the request.
3092 * @param pCmdFis Pointer to the command FIS from the guest.
3093 * @param fRead Flag whether this is a read request.
3094 * @param fInterrupt If an interrupt should be send to the guest.
3095 */
3096static void ahciSendPioSetupFis(PAHCIPort pAhciPort, size_t cbTransfer, uint8_t *pCmdFis,
3097 bool fRead, bool fInterrupt)
3098{
3099 uint8_t abPioSetupFis[20];
3100 bool fAssertIntr = false;
3101 PAHCI pAhci = pAhciPort->CTX_SUFF(pAhci);
3102
3103 ahciLog(("%s: building PIO setup Fis\n", __FUNCTION__));
3104
3105 AssertMsg( cbTransfer > 0
3106 && cbTransfer <= 65534,
3107 ("Can't send PIO setup FIS for requests with 0 bytes to transfer or greater than 65534\n"));
3108
3109 if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
3110 {
3111 memset(&abPioSetupFis[0], 0, sizeof(abPioSetupFis));
3112 abPioSetupFis[AHCI_CMDFIS_TYPE] = AHCI_CMDFIS_TYPE_PIOSETUP;
3113 abPioSetupFis[AHCI_CMDFIS_BITS] = (fInterrupt ? AHCI_CMDFIS_I : 0);
3114 if (fRead)
3115 abPioSetupFis[AHCI_CMDFIS_BITS] |= AHCI_CMDFIS_D;
3116 abPioSetupFis[AHCI_CMDFIS_STS] = pCmdFis[AHCI_CMDFIS_STS];
3117 abPioSetupFis[AHCI_CMDFIS_ERR] = pCmdFis[AHCI_CMDFIS_ERR];
3118 abPioSetupFis[AHCI_CMDFIS_SECTN] = pCmdFis[AHCI_CMDFIS_SECTN];
3119 abPioSetupFis[AHCI_CMDFIS_CYLL] = pCmdFis[AHCI_CMDFIS_CYLL];
3120 abPioSetupFis[AHCI_CMDFIS_CYLH] = pCmdFis[AHCI_CMDFIS_CYLH];
3121 abPioSetupFis[AHCI_CMDFIS_HEAD] = pCmdFis[AHCI_CMDFIS_HEAD];
3122 abPioSetupFis[AHCI_CMDFIS_SECTNEXP] = pCmdFis[AHCI_CMDFIS_SECTNEXP];
3123 abPioSetupFis[AHCI_CMDFIS_CYLLEXP] = pCmdFis[AHCI_CMDFIS_CYLLEXP];
3124 abPioSetupFis[AHCI_CMDFIS_CYLHEXP] = pCmdFis[AHCI_CMDFIS_CYLHEXP];
3125 abPioSetupFis[AHCI_CMDFIS_SECTC] = pCmdFis[AHCI_CMDFIS_SECTC];
3126 abPioSetupFis[AHCI_CMDFIS_SECTCEXP] = pCmdFis[AHCI_CMDFIS_SECTCEXP];
3127
3128 /* Set transfer count. */
3129 abPioSetupFis[16] = (cbTransfer >> 8) & 0xff;
3130 abPioSetupFis[17] = cbTransfer & 0xff;
3131
3132 /* Update registers. */
3133 pAhciPort->regTFD = (pCmdFis[AHCI_CMDFIS_ERR] << 8) | pCmdFis[AHCI_CMDFIS_STS];
3134
3135 ahciPostFisIntoMemory(pAhciPort, AHCI_CMDFIS_TYPE_PIOSETUP, abPioSetupFis);
3136
3137 if (fInterrupt)
3138 {
3139 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_PSS);
3140 /* Check if we should assert an interrupt */
3141 if (pAhciPort->regIE & AHCI_PORT_IE_PSE)
3142 fAssertIntr = true;
3143 }
3144
3145 if (fAssertIntr)
3146 {
3147 int rc = ahciHbaSetInterrupt(pAhci, pAhciPort->iLUN, VERR_IGNORED);
3148 AssertRC(rc);
3149 }
3150 }
3151}
3152
3153/**
3154 * Build a D2H FIS and post into the memory area of the guest.
3155 *
3156 * @returns Nothing
3157 * @param pAhciPort The port of the SATA controller.
3158 * @param uTag The tag of the request.
3159 * @param pCmdFis Pointer to the command FIS from the guest.
3160 * @param fInterrupt If an interrupt should be send to the guest.
3161 */
3162static void ahciSendD2HFis(PAHCIPort pAhciPort, uint32_t uTag, uint8_t *pCmdFis, bool fInterrupt)
3163{
3164 uint8_t d2hFis[20];
3165 bool fAssertIntr = false;
3166 PAHCI pAhci = pAhciPort->CTX_SUFF(pAhci);
3167
3168 ahciLog(("%s: building D2H Fis\n", __FUNCTION__));
3169
3170 if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
3171 {
3172 memset(&d2hFis[0], 0, sizeof(d2hFis));
3173 d2hFis[AHCI_CMDFIS_TYPE] = AHCI_CMDFIS_TYPE_D2H;
3174 d2hFis[AHCI_CMDFIS_BITS] = (fInterrupt ? AHCI_CMDFIS_I : 0);
3175 d2hFis[AHCI_CMDFIS_STS] = pCmdFis[AHCI_CMDFIS_STS];
3176 d2hFis[AHCI_CMDFIS_ERR] = pCmdFis[AHCI_CMDFIS_ERR];
3177 d2hFis[AHCI_CMDFIS_SECTN] = pCmdFis[AHCI_CMDFIS_SECTN];
3178 d2hFis[AHCI_CMDFIS_CYLL] = pCmdFis[AHCI_CMDFIS_CYLL];
3179 d2hFis[AHCI_CMDFIS_CYLH] = pCmdFis[AHCI_CMDFIS_CYLH];
3180 d2hFis[AHCI_CMDFIS_HEAD] = pCmdFis[AHCI_CMDFIS_HEAD];
3181 d2hFis[AHCI_CMDFIS_SECTNEXP] = pCmdFis[AHCI_CMDFIS_SECTNEXP];
3182 d2hFis[AHCI_CMDFIS_CYLLEXP] = pCmdFis[AHCI_CMDFIS_CYLLEXP];
3183 d2hFis[AHCI_CMDFIS_CYLHEXP] = pCmdFis[AHCI_CMDFIS_CYLHEXP];
3184 d2hFis[AHCI_CMDFIS_SECTC] = pCmdFis[AHCI_CMDFIS_SECTC];
3185 d2hFis[AHCI_CMDFIS_SECTCEXP] = pCmdFis[AHCI_CMDFIS_SECTCEXP];
3186
3187 /* Update registers. */
3188 pAhciPort->regTFD = (pCmdFis[AHCI_CMDFIS_ERR] << 8) | pCmdFis[AHCI_CMDFIS_STS];
3189
3190 ahciPostFisIntoMemory(pAhciPort, AHCI_CMDFIS_TYPE_D2H, d2hFis);
3191
3192 if (pCmdFis[AHCI_CMDFIS_STS] & ATA_STAT_ERR)
3193 {
3194 /* Error bit is set. */
3195 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_TFES);
3196 if (pAhciPort->regIE & AHCI_PORT_IE_TFEE)
3197 fAssertIntr = true;
3198 /*
3199 * Don't mark the command slot as completed because the guest
3200 * needs it to identify the failed command.
3201 */
3202 }
3203 else if (fInterrupt)
3204 {
3205 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_DHRS);
3206 /* Check if we should assert an interrupt */
3207 if (pAhciPort->regIE & AHCI_PORT_IE_DHRE)
3208 fAssertIntr = true;
3209
3210 /* Mark command as completed. */
3211 ASMAtomicOrU32(&pAhciPort->u32TasksFinished, RT_BIT_32(uTag));
3212 }
3213
3214 if (fAssertIntr)
3215 {
3216 int rc = ahciHbaSetInterrupt(pAhci, pAhciPort->iLUN, VERR_IGNORED);
3217 AssertRC(rc);
3218 }
3219 }
3220}
3221
3222/**
3223 * Build a SDB Fis and post it into the memory area of the guest.
3224 *
3225 * @returns Nothing
3226 * @param pAhciPort The port for which the SDB Fis is send.
3227 * @param uFinishedTasks Bitmask of finished tasks.
3228 * @param fInterrupt If an interrupt should be asserted.
3229 */
3230static void ahciSendSDBFis(PAHCIPort pAhciPort, uint32_t uFinishedTasks, bool fInterrupt)
3231{
3232 uint32_t sdbFis[2];
3233 bool fAssertIntr = false;
3234 PAHCI pAhci = pAhciPort->CTX_SUFF(pAhci);
3235 PAHCIREQ pTaskErr = ASMAtomicReadPtrT(&pAhciPort->pTaskErr, PAHCIREQ);
3236
3237 ahciLog(("%s: Building SDB FIS\n", __FUNCTION__));
3238
3239 if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
3240 {
3241 memset(&sdbFis[0], 0, sizeof(sdbFis));
3242 sdbFis[0] = AHCI_CMDFIS_TYPE_SETDEVBITS;
3243 sdbFis[0] |= (fInterrupt ? (1 << 14) : 0);
3244 if (RT_UNLIKELY(pTaskErr))
3245 {
3246 sdbFis[0] = pTaskErr->cmdFis[AHCI_CMDFIS_ERR];
3247 sdbFis[0] |= (pTaskErr->cmdFis[AHCI_CMDFIS_STS] & 0x77) << 16; /* Some bits are marked as reserved and thus are masked out. */
3248
3249 /* Update registers. */
3250 pAhciPort->regTFD = (pTaskErr->cmdFis[AHCI_CMDFIS_ERR] << 8) | pTaskErr->cmdFis[AHCI_CMDFIS_STS];
3251 }
3252 else
3253 {
3254 sdbFis[0] = 0;
3255 sdbFis[0] |= (ATA_STAT_READY | ATA_STAT_SEEK) << 16;
3256 pAhciPort->regTFD = ATA_STAT_READY | ATA_STAT_SEEK;
3257 }
3258
3259 sdbFis[1] = pAhciPort->u32QueuedTasksFinished | uFinishedTasks;
3260
3261 ahciPostFisIntoMemory(pAhciPort, AHCI_CMDFIS_TYPE_SETDEVBITS, (uint8_t *)sdbFis);
3262
3263 if (RT_UNLIKELY(pTaskErr))
3264 {
3265 /* Error bit is set. */
3266 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_TFES);
3267 if (pAhciPort->regIE & AHCI_PORT_IE_TFEE)
3268 fAssertIntr = true;
3269 }
3270
3271 if (fInterrupt)
3272 {
3273 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_SDBS);
3274 /* Check if we should assert an interrupt */
3275 if (pAhciPort->regIE & AHCI_PORT_IE_SDBE)
3276 fAssertIntr = true;
3277 }
3278
3279 ASMAtomicOrU32(&pAhciPort->u32QueuedTasksFinished, uFinishedTasks);
3280
3281 if (fAssertIntr)
3282 {
3283 int rc = ahciHbaSetInterrupt(pAhci, pAhciPort->iLUN, VERR_IGNORED);
3284 AssertRC(rc);
3285 }
3286 }
3287}
3288
3289static uint32_t ahciGetNSectors(uint8_t *pCmdFis, bool fLBA48)
3290{
3291 /* 0 means either 256 (LBA28) or 65536 (LBA48) sectors. */
3292 if (fLBA48)
3293 {
3294 if (!pCmdFis[AHCI_CMDFIS_SECTC] && !pCmdFis[AHCI_CMDFIS_SECTCEXP])
3295 return 65536;
3296 else
3297 return pCmdFis[AHCI_CMDFIS_SECTCEXP] << 8 | pCmdFis[AHCI_CMDFIS_SECTC];
3298 }
3299 else
3300 {
3301 if (!pCmdFis[AHCI_CMDFIS_SECTC])
3302 return 256;
3303 else
3304 return pCmdFis[AHCI_CMDFIS_SECTC];
3305 }
3306}
3307
3308static uint64_t ahciGetSector(PAHCIPort pAhciPort, uint8_t *pCmdFis, bool fLBA48)
3309{
3310 uint64_t iLBA;
3311 if (pCmdFis[AHCI_CMDFIS_HEAD] & 0x40)
3312 {
3313 /* any LBA variant */
3314 if (fLBA48)
3315 {
3316 /* LBA48 */
3317 iLBA = ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLHEXP] << 40) |
3318 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLLEXP] << 32) |
3319 ((uint64_t)pCmdFis[AHCI_CMDFIS_SECTNEXP] << 24) |
3320 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLH] << 16) |
3321 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLL] << 8) |
3322 pCmdFis[AHCI_CMDFIS_SECTN];
3323 }
3324 else
3325 {
3326 /* LBA */
3327 iLBA = ((pCmdFis[AHCI_CMDFIS_HEAD] & 0x0f) << 24) | (pCmdFis[AHCI_CMDFIS_CYLH] << 16) |
3328 (pCmdFis[AHCI_CMDFIS_CYLL] << 8) | pCmdFis[AHCI_CMDFIS_SECTN];
3329 }
3330 }
3331 else
3332 {
3333 /* CHS */
3334 iLBA = ((pCmdFis[AHCI_CMDFIS_CYLH] << 8) | pCmdFis[AHCI_CMDFIS_CYLL]) * pAhciPort->PCHSGeometry.cHeads * pAhciPort->PCHSGeometry.cSectors +
3335 (pCmdFis[AHCI_CMDFIS_HEAD] & 0x0f) * pAhciPort->PCHSGeometry.cSectors +
3336 (pCmdFis[AHCI_CMDFIS_SECTN] - 1);
3337 }
3338 return iLBA;
3339}
3340
3341static uint64_t ahciGetSectorQueued(uint8_t *pCmdFis)
3342{
3343 uint64_t uLBA;
3344
3345 uLBA = ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLHEXP] << 40) |
3346 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLLEXP] << 32) |
3347 ((uint64_t)pCmdFis[AHCI_CMDFIS_SECTNEXP] << 24) |
3348 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLH] << 16) |
3349 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLL] << 8) |
3350 pCmdFis[AHCI_CMDFIS_SECTN];
3351
3352 return uLBA;
3353}
3354
3355DECLINLINE(uint32_t) ahciGetNSectorsQueued(uint8_t *pCmdFis)
3356{
3357 if (!pCmdFis[AHCI_CMDFIS_FETEXP] && !pCmdFis[AHCI_CMDFIS_FET])
3358 return 65536;
3359 else
3360 return pCmdFis[AHCI_CMDFIS_FETEXP] << 8 | pCmdFis[AHCI_CMDFIS_FET];
3361}
3362
3363/**
3364 * Copy from guest to host memory worker.
3365 *
3366 * @copydoc{AHCIR3MEMCOPYCALLBACK}
3367 */
3368static DECLCALLBACK(void) ahciR3CopyBufferFromGuestWorker(PAHCI pThis, RTGCPHYS GCPhys, PRTSGBUF pSgBuf,
3369 size_t cbCopy, size_t *pcbSkip)
3370{
3371 size_t cbSkipped = RT_MIN(cbCopy, *pcbSkip);
3372 cbCopy -= cbSkipped;
3373 GCPhys += cbSkipped;
3374 *pcbSkip -= cbSkipped;
3375
3376 while (cbCopy)
3377 {
3378 size_t cbSeg = cbCopy;
3379 void *pvSeg = RTSgBufGetNextSegment(pSgBuf, &cbSeg);
3380
3381 AssertPtr(pvSeg);
3382 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, pvSeg, cbSeg);
3383 GCPhys += cbSeg;
3384 cbCopy -= cbSeg;
3385 }
3386}
3387
3388/**
3389 * Copy from host to guest memory worker.
3390 *
3391 * @copydoc{AHCIR3MEMCOPYCALLBACK}
3392 */
3393static DECLCALLBACK(void) ahciR3CopyBufferToGuestWorker(PAHCI pThis, RTGCPHYS GCPhys, PRTSGBUF pSgBuf,
3394 size_t cbCopy, size_t *pcbSkip)
3395{
3396 size_t cbSkipped = RT_MIN(cbCopy, *pcbSkip);
3397 cbCopy -= cbSkipped;
3398 GCPhys += cbSkipped;
3399 *pcbSkip -= cbSkipped;
3400
3401 while (cbCopy)
3402 {
3403 size_t cbSeg = cbCopy;
3404 void *pvSeg = RTSgBufGetNextSegment(pSgBuf, &cbSeg);
3405
3406 AssertPtr(pvSeg);
3407 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhys, pvSeg, cbSeg);
3408 GCPhys += cbSeg;
3409 cbCopy -= cbSeg;
3410 }
3411}
3412
3413/**
3414 * Walks the PRDTL list copying data between the guest and host memory buffers.
3415 *
3416 * @returns Amount of bytes copied.
3417 * @param pThis The AHCI controller device instance.
3418 * @param pAhciReq AHCI request structure.
3419 * @param pfnCopyWorker The copy method to apply for each guest buffer.
3420 * @param pSgBuf The host S/G buffer.
3421 * @param cbSkip How many bytes to skip in advance before starting to copy.
3422 * @param cbCopy How many bytes to copy.
3423 */
3424static size_t ahciR3PrdtlWalk(PAHCI pThis, PAHCIREQ pAhciReq,
3425 PAHCIR3MEMCOPYCALLBACK pfnCopyWorker,
3426 PRTSGBUF pSgBuf, size_t cbSkip, size_t cbCopy)
3427{
3428 RTGCPHYS GCPhysPrdtl = pAhciReq->GCPhysPrdtl;
3429 unsigned cPrdtlEntries = pAhciReq->cPrdtlEntries;
3430 size_t cbCopied = 0;
3431
3432 /*
3433 * Add the amount to skip to the host buffer size to avoid a
3434 * few conditionals later on.
3435 */
3436 cbCopy += cbSkip;
3437
3438 AssertMsgReturn(cPrdtlEntries > 0, ("Copying 0 bytes is not possible\n"), 0);
3439
3440 do
3441 {
3442 SGLEntry aPrdtlEntries[32];
3443 uint32_t cPrdtlEntriesRead = cPrdtlEntries < RT_ELEMENTS(aPrdtlEntries)
3444 ? cPrdtlEntries
3445 : RT_ELEMENTS(aPrdtlEntries);
3446
3447 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhysPrdtl, &aPrdtlEntries[0],
3448 cPrdtlEntriesRead * sizeof(SGLEntry));
3449
3450 for (uint32_t i = 0; (i < cPrdtlEntriesRead) && cbCopy; i++)
3451 {
3452 RTGCPHYS GCPhysAddrDataBase = AHCI_RTGCPHYS_FROM_U32(aPrdtlEntries[i].u32DBAUp, aPrdtlEntries[i].u32DBA);
3453 uint32_t cbThisCopy = (aPrdtlEntries[i].u32DescInf & SGLENTRY_DESCINF_DBC) + 1;
3454
3455 cbThisCopy = (uint32_t)RT_MIN(cbThisCopy, cbCopy);
3456
3457 /* Copy into SG entry. */
3458 pfnCopyWorker(pThis, GCPhysAddrDataBase, pSgBuf, cbThisCopy, &cbSkip);
3459
3460 cbCopy -= cbThisCopy;
3461 cbCopied += cbThisCopy;
3462 }
3463
3464 GCPhysPrdtl += cPrdtlEntriesRead * sizeof(SGLEntry);
3465 cPrdtlEntries -= cPrdtlEntriesRead;
3466 } while (cPrdtlEntries && cbCopy);
3467
3468 if (cbCopied < cbCopy)
3469 pAhciReq->fFlags |= AHCI_REQ_OVERFLOW;
3470
3471 return cbCopied;
3472}
3473
3474/**
3475 * Copies a data buffer into the S/G buffer set up by the guest.
3476 *
3477 * @returns Amount of bytes copied to the PRDTL.
3478 * @param pThis The AHCI controller device instance.
3479 * @param pAhciReq AHCI request structure.
3480 * @param pSgBuf The S/G buffer to copy from.
3481 * @param cbSkip How many bytes to skip in advance before starting to copy.
3482 * @param cbCopy How many bytes to copy.
3483 */
3484static size_t ahciR3CopySgBufToPrdtl(PAHCI pThis, PAHCIREQ pAhciReq, PRTSGBUF pSgBuf,
3485 size_t cbSkip, size_t cbCopy)
3486{
3487 return ahciR3PrdtlWalk(pThis, pAhciReq, ahciR3CopyBufferToGuestWorker,
3488 pSgBuf, cbSkip, cbCopy);
3489}
3490
3491/**
3492 * Copies the S/G buffer into a data buffer.
3493 *
3494 * @returns Amount of bytes copied from the PRDTL.
3495 * @param pThis The AHCI controller device instance.
3496 * @param pAhciReq AHCI request structure.
3497 * @param pSgBuf The S/G buffer to copy into.
3498 * @param cbSkip How many bytes to skip in advance before starting to copy.
3499 * @param cbCopy How many bytes to copy.
3500 */
3501static size_t ahciR3CopySgBufFromPrdtl(PAHCI pThis, PAHCIREQ pAhciReq, PRTSGBUF pSgBuf,
3502 size_t cbSkip, size_t cbCopy)
3503{
3504 return ahciR3PrdtlWalk(pThis, pAhciReq, ahciR3CopyBufferFromGuestWorker,
3505 pSgBuf, cbSkip, cbCopy);
3506}
3507
3508/**
3509 * Copy a simple memory buffer to the guest memory buffer.
3510 *
3511 * @returns Amount of bytes copied from the PRDTL.
3512 * @param pThis The AHCI controller device instance.
3513 * @param pAhciReq AHCI request structure.
3514 * @param pvSrc The buffer to copy from.
3515 * @param cbSrc How many bytes to copy.
3516 * @param cbSkip How many bytes to skip initially.
3517 */
3518static size_t ahciR3CopyBufferToPrdtl(PAHCI pThis, PAHCIREQ pAhciReq, const void *pvSrc,
3519 size_t cbSrc, size_t cbSkip)
3520{
3521 RTSGSEG Seg;
3522 RTSGBUF SgBuf;
3523 Seg.pvSeg = (void *)pvSrc;
3524 Seg.cbSeg = cbSrc;
3525 RTSgBufInit(&SgBuf, &Seg, 1);
3526 return ahciR3CopySgBufToPrdtl(pThis, pAhciReq, &SgBuf, cbSkip, cbSrc);
3527}
3528
3529/**
3530 * Calculates the size of the guest buffer described by the PRDT.
3531 *
3532 * @returns VBox status code.
3533 * @param pThis The AHCI controller device instance.
3534 * @param pAhciReq AHCI request structure.
3535 * @param pcbPrdt Where to store the size of the guest buffer.
3536 */
3537static int ahciR3PrdtQuerySize(PAHCI pThis, PAHCIREQ pAhciReq, size_t *pcbPrdt)
3538{
3539 RTGCPHYS GCPhysPrdtl = pAhciReq->GCPhysPrdtl;
3540 unsigned cPrdtlEntries = pAhciReq->cPrdtlEntries;
3541 size_t cbPrdt = 0;
3542
3543 do
3544 {
3545 SGLEntry aPrdtlEntries[32];
3546 uint32_t cPrdtlEntriesRead = cPrdtlEntries < RT_ELEMENTS(aPrdtlEntries)
3547 ? cPrdtlEntries
3548 : RT_ELEMENTS(aPrdtlEntries);
3549
3550 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhysPrdtl, &aPrdtlEntries[0],
3551 cPrdtlEntriesRead * sizeof(SGLEntry));
3552
3553 for (uint32_t i = 0; i < cPrdtlEntriesRead; i++)
3554 cbPrdt += (aPrdtlEntries[i].u32DescInf & SGLENTRY_DESCINF_DBC) + 1;
3555
3556 GCPhysPrdtl += cPrdtlEntriesRead * sizeof(SGLEntry);
3557 cPrdtlEntries -= cPrdtlEntriesRead;
3558 } while (cPrdtlEntries);
3559
3560 *pcbPrdt = cbPrdt;
3561 return VINF_SUCCESS;
3562}
3563
3564/**
3565 * Cancels all active tasks on the port.
3566 *
3567 * @returns Whether all active tasks were canceled.
3568 * @param pAhciPort The AHCI port.
3569 */
3570static bool ahciCancelActiveTasks(PAHCIPort pAhciPort)
3571{
3572 if (pAhciPort->pDrvMediaEx)
3573 {
3574 int rc = pAhciPort->pDrvMediaEx->pfnIoReqCancelAll(pAhciPort->pDrvMediaEx);
3575 AssertRC(rc);
3576 }
3577 return true; /* always true for now because tasks don't use guest memory as the buffer which makes canceling a task impossible. */
3578}
3579
3580/**
3581 * Creates the array of ranges to trim.
3582 *
3583 * @returns VBox status code.
3584 * @param pAhciPort AHCI port state.
3585 * @param pAhciReq The request handling the TRIM request.
3586 * @param idxRangeStart Index of the first range to start copying.
3587 * @param paRanges Where to store the ranges.
3588 * @param cRanges Number of ranges fitting into the array.
3589 * @param pcRanges Where to store the amount of ranges actually copied on success.
3590 */
3591static int ahciTrimRangesCreate(PAHCIPort pAhciPort, PAHCIREQ pAhciReq, uint32_t idxRangeStart,
3592 PRTRANGE paRanges, uint32_t cRanges, uint32_t *pcRanges)
3593{
3594 SGLEntry aPrdtlEntries[32];
3595 uint64_t aRanges[64];
3596 uint32_t cPrdtlEntries = pAhciReq->cPrdtlEntries;
3597 RTGCPHYS GCPhysPrdtl = pAhciReq->GCPhysPrdtl;
3598 PPDMDEVINS pDevIns = pAhciPort->CTX_SUFF(pDevIns);
3599 int rc = VERR_PDM_MEDIAEX_IOBUF_OVERFLOW;
3600 uint32_t idxRange = 0;
3601
3602 LogFlowFunc(("pAhciPort=%#p pAhciReq=%#p\n", pAhciPort, pAhciReq));
3603
3604 AssertMsgReturn(pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_DISCARD, ("This is not a trim request\n"), VERR_INVALID_PARAMETER);
3605
3606 if (!cPrdtlEntries)
3607 pAhciReq->fFlags |= AHCI_REQ_OVERFLOW;
3608
3609 /* Convert the ranges from ATA to our format. */
3610 while ( cPrdtlEntries
3611 && idxRange < cRanges)
3612 {
3613 uint32_t cPrdtlEntriesRead = RT_MIN(cPrdtlEntries, RT_ELEMENTS(aPrdtlEntries));
3614
3615 rc = VINF_SUCCESS;
3616 PDMDevHlpPhysRead(pDevIns, GCPhysPrdtl, &aPrdtlEntries[0], cPrdtlEntriesRead * sizeof(SGLEntry));
3617
3618 for (uint32_t i = 0; i < cPrdtlEntriesRead && idxRange < cRanges; i++)
3619 {
3620 RTGCPHYS GCPhysAddrDataBase = AHCI_RTGCPHYS_FROM_U32(aPrdtlEntries[i].u32DBAUp, aPrdtlEntries[i].u32DBA);
3621 uint32_t cbThisCopy = (aPrdtlEntries[i].u32DescInf & SGLENTRY_DESCINF_DBC) + 1;
3622
3623 cbThisCopy = RT_MIN(cbThisCopy, sizeof(aRanges));
3624
3625 /* Copy into buffer. */
3626 PDMDevHlpPhysRead(pDevIns, GCPhysAddrDataBase, aRanges, cbThisCopy);
3627
3628 for (unsigned idxRangeSrc = 0; idxRangeSrc < RT_ELEMENTS(aRanges) && idxRange < cRanges; idxRangeSrc++)
3629 {
3630 /* Skip range if told to do so. */
3631 if (!idxRangeStart)
3632 {
3633 aRanges[idxRangeSrc] = RT_H2LE_U64(aRanges[idxRangeSrc]);
3634 if (AHCI_RANGE_LENGTH_GET(aRanges[idxRangeSrc]) != 0)
3635 {
3636 paRanges[idxRange].offStart = (aRanges[idxRangeSrc] & AHCI_RANGE_LBA_MASK) * pAhciPort->cbSector;
3637 paRanges[idxRange].cbRange = AHCI_RANGE_LENGTH_GET(aRanges[idxRangeSrc]) * pAhciPort->cbSector;
3638 idxRange++;
3639 }
3640 else
3641 break;
3642 }
3643 else
3644 idxRangeStart--;
3645 }
3646 }
3647
3648 GCPhysPrdtl += cPrdtlEntriesRead * sizeof(SGLEntry);
3649 cPrdtlEntries -= cPrdtlEntriesRead;
3650 }
3651
3652 *pcRanges = idxRange;
3653
3654 LogFlowFunc(("returns rc=%Rrc\n", rc));
3655 return rc;
3656}
3657
3658/**
3659 * Allocates a new AHCI request.
3660 *
3661 * @returns A new AHCI request structure or NULL if out of memory.
3662 * @param pAhciPort The AHCI port.
3663 * @param uTag The tag to assign.
3664 */
3665static PAHCIREQ ahciR3ReqAlloc(PAHCIPort pAhciPort, uint32_t uTag)
3666{
3667 PAHCIREQ pAhciReq = NULL;
3668 PDMMEDIAEXIOREQ hIoReq = NULL;
3669
3670 int rc = pAhciPort->pDrvMediaEx->pfnIoReqAlloc(pAhciPort->pDrvMediaEx, &hIoReq, (void **)&pAhciReq,
3671 uTag, PDMIMEDIAEX_F_SUSPEND_ON_RECOVERABLE_ERR);
3672 if (RT_SUCCESS(rc))
3673 {
3674 pAhciReq->hIoReq = hIoReq;
3675 pAhciReq->pfnPostProcess = NULL;
3676 }
3677 else
3678 pAhciReq = NULL;
3679 return pAhciReq;
3680}
3681
3682/**
3683 * Frees a given AHCI request structure.
3684 *
3685 * @returns nothing.
3686 * @param pAhciPort The AHCI port.
3687 * @param pAhciReq The request to free.
3688 */
3689static void ahciR3ReqFree(PAHCIPort pAhciPort, PAHCIREQ pAhciReq)
3690{
3691 if ( pAhciReq
3692 && !(pAhciReq->fFlags & AHCI_REQ_IS_ON_STACK))
3693 {
3694 int rc = pAhciPort->pDrvMediaEx->pfnIoReqFree(pAhciPort->pDrvMediaEx, pAhciReq->hIoReq);
3695 AssertRC(rc);
3696 }
3697}
3698
3699/**
3700 * Complete a data transfer task by freeing all occupied resources
3701 * and notifying the guest.
3702 *
3703 * @returns Flag whether the given request was canceled inbetween;
3704 *
3705 * @param pAhciPort Pointer to the port where to request completed.
3706 * @param pAhciReq Pointer to the task which finished.
3707 * @param rcReq IPRT status code of the completed request.
3708 */
3709static bool ahciTransferComplete(PAHCIPort pAhciPort, PAHCIREQ pAhciReq, int rcReq)
3710{
3711 bool fCanceled = false;
3712
3713 LogFlowFunc(("pAhciPort=%p pAhciReq=%p rcReq=%d\n",
3714 pAhciPort, pAhciReq, rcReq));
3715
3716 VBOXDD_AHCI_REQ_COMPLETED(pAhciReq, rcReq, pAhciReq->uOffset, pAhciReq->cbTransfer);
3717
3718 if (rcReq != VERR_PDM_MEDIAEX_IOREQ_CANCELED)
3719 {
3720 if (pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_READ)
3721 {
3722 STAM_REL_COUNTER_ADD(&pAhciPort->StatBytesRead, pAhciReq->cbTransfer);
3723 pAhciPort->Led.Actual.s.fReading = 0;
3724 }
3725 else if (pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_WRITE)
3726 {
3727 STAM_REL_COUNTER_ADD(&pAhciPort->StatBytesWritten, pAhciReq->cbTransfer);
3728 pAhciPort->Led.Actual.s.fWriting = 0;
3729 }
3730 else if (pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_DISCARD)
3731 pAhciPort->Led.Actual.s.fWriting = 0;
3732 else if (pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_SCSI)
3733 {
3734 pAhciPort->Led.Actual.s.fWriting = 0;
3735 pAhciPort->Led.Actual.s.fReading = 0;
3736 }
3737
3738 if (RT_FAILURE(rcReq))
3739 {
3740 /* Log the error. */
3741 if (pAhciPort->cErrors++ < MAX_LOG_REL_ERRORS)
3742 {
3743 if (pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_FLUSH)
3744 LogRel(("AHCI#%uP%u: Flush returned rc=%Rrc\n",
3745 pAhciPort->CTX_SUFF(pDevIns)->iInstance, pAhciPort->iLUN, rcReq));
3746 else if (pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_DISCARD)
3747 LogRel(("AHCI#%uP%u: Trim returned rc=%Rrc\n",
3748 pAhciPort->CTX_SUFF(pDevIns)->iInstance, pAhciPort->iLUN, rcReq));
3749 else
3750 LogRel(("AHCI#%uP%u: %s at offset %llu (%zu bytes left) returned rc=%Rrc\n",
3751 pAhciPort->CTX_SUFF(pDevIns)->iInstance, pAhciPort->iLUN,
3752 pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_READ
3753 ? "Read"
3754 : "Write",
3755 pAhciReq->uOffset,
3756 pAhciReq->cbTransfer, rcReq));
3757 }
3758
3759 ahciReqSetStatus(pAhciReq, ID_ERR, ATA_STAT_READY | ATA_STAT_ERR);
3760 /*
3761 * We have to duplicate the request here as the underlying I/O
3762 * request will be freed later.
3763 */
3764 PAHCIREQ pReqDup = (PAHCIREQ)RTMemDup(pAhciReq, sizeof(AHCIREQ));
3765 if ( pReqDup
3766 && !ASMAtomicCmpXchgPtr(&pAhciPort->pTaskErr, pReqDup, NULL))
3767 RTMemFree(pReqDup);
3768 }
3769 else
3770 {
3771 /* Status will be set already for non I/O requests. */
3772 if (pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_SCSI)
3773 {
3774 if (pAhciReq->u8ScsiSts == SCSI_STATUS_OK)
3775 {
3776 ahciReqSetStatus(pAhciReq, 0, ATA_STAT_READY | ATA_STAT_SEEK);
3777 pAhciReq->cmdFis[AHCI_CMDFIS_SECTN] = (pAhciReq->cmdFis[AHCI_CMDFIS_SECTN] & ~7)
3778 | ((pAhciReq->fFlags & AHCI_REQ_XFER_2_HOST) ? ATAPI_INT_REASON_IO : 0)
3779 | (!pAhciReq->cbTransfer ? ATAPI_INT_REASON_CD : 0);
3780 }
3781 else
3782 {
3783 ahciReqSetStatus(pAhciReq, pAhciPort->abATAPISense[2] << 4, ATA_STAT_READY | ATA_STAT_ERR);
3784 pAhciReq->cmdFis[AHCI_CMDFIS_SECTN] = (pAhciReq->cmdFis[AHCI_CMDFIS_SECTN] & ~7) |
3785 ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
3786 pAhciReq->cbTransfer = 0;
3787 LogFlowFunc(("SCSI request completed with %u status\n", pAhciReq->u8ScsiSts));
3788 }
3789 }
3790 else if (pAhciReq->enmType != PDMMEDIAEXIOREQTYPE_INVALID)
3791 ahciReqSetStatus(pAhciReq, 0, ATA_STAT_READY | ATA_STAT_SEEK);
3792
3793 /* Write updated command header into memory of the guest. */
3794 uint32_t u32PRDBC = (uint32_t)pAhciReq->cbTransfer;
3795 PDMDevHlpPCIPhysWrite(pAhciPort->CTX_SUFF(pDevIns), pAhciReq->GCPhysCmdHdrAddr + RT_OFFSETOF(CmdHdr, u32PRDBC),
3796 &u32PRDBC, sizeof(u32PRDBC));
3797
3798 if (pAhciReq->fFlags & AHCI_REQ_OVERFLOW)
3799 {
3800 /*
3801 * The guest tried to transfer more data than there is space in the buffer.
3802 * Terminate task and set the overflow bit.
3803 */
3804 /* Notify the guest. */
3805 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_OFS);
3806 if (pAhciPort->regIE & AHCI_PORT_IE_OFE)
3807 ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN, VERR_IGNORED);
3808 }
3809 }
3810
3811 /*
3812 * Make a copy of the required data now and free the request. Otherwise the guest
3813 * might issue a new request with the same tag and we run into a conflict when allocating
3814 * a new request with the same tag later on.
3815 */
3816 uint32_t fFlags = pAhciReq->fFlags;
3817 uint32_t uTag = pAhciReq->uTag;
3818 size_t cbTransfer = pAhciReq->cbTransfer;
3819 bool fRead = pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_READ;
3820 uint8_t cmdFis[AHCI_CMDFIS_TYPE_H2D_SIZE];
3821 memcpy(&cmdFis[0], &pAhciReq->cmdFis[0], sizeof(cmdFis));
3822
3823 ahciR3ReqFree(pAhciPort, pAhciReq);
3824
3825 /* Post a PIO setup FIS first if this is a PIO command which transfers data. */
3826 if (fFlags & AHCI_REQ_PIO_DATA)
3827 ahciSendPioSetupFis(pAhciPort, cbTransfer, &cmdFis[0], fRead, false /* fInterrupt */);
3828
3829 if (fFlags & AHCI_REQ_CLEAR_SACT)
3830 {
3831 if (RT_SUCCESS(rcReq) && !ASMAtomicReadPtrT(&pAhciPort->pTaskErr, PAHCIREQ))
3832 ASMAtomicOrU32(&pAhciPort->u32QueuedTasksFinished, RT_BIT_32(uTag));
3833 }
3834
3835 if (fFlags & AHCI_REQ_IS_QUEUED)
3836 {
3837 /*
3838 * Always raise an interrupt after task completion; delaying
3839 * this (interrupt coalescing) increases latency and has a significant
3840 * impact on performance (see @bugref{5071})
3841 */
3842 ahciSendSDBFis(pAhciPort, 0, true);
3843 }
3844 else
3845 ahciSendD2HFis(pAhciPort, uTag, &cmdFis[0], true);
3846 }
3847 else
3848 {
3849 /*
3850 * Task was canceled, do the cleanup but DO NOT access the guest memory!
3851 * The guest might use it for other things now because it doesn't know about that task anymore.
3852 */
3853 fCanceled = true;
3854
3855 /* Leave a log message about the canceled request. */
3856 if (pAhciPort->cErrors++ < MAX_LOG_REL_ERRORS)
3857 {
3858 if (pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_FLUSH)
3859 LogRel(("AHCI#%uP%u: Canceled flush returned rc=%Rrc\n",
3860 pAhciPort->CTX_SUFF(pDevIns)->iInstance, pAhciPort->iLUN, rcReq));
3861 else if (pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_DISCARD)
3862 LogRel(("AHCI#%uP%u: Canceled trim returned rc=%Rrc\n",
3863 pAhciPort->CTX_SUFF(pDevIns)->iInstance,pAhciPort->iLUN, rcReq));
3864 else
3865 LogRel(("AHCI#%uP%u: Canceled %s at offset %llu (%zu bytes left) returned rc=%Rrc\n",
3866 pAhciPort->CTX_SUFF(pDevIns)->iInstance, pAhciPort->iLUN,
3867 pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_READ
3868 ? "read"
3869 : "write",
3870 pAhciReq->uOffset,
3871 pAhciReq->cbTransfer, rcReq));
3872 }
3873
3874 ahciR3ReqFree(pAhciPort, pAhciReq);
3875 }
3876
3877 /*
3878 * Decrement the active task counter as the last step or we might run into a
3879 * hang during power off otherwise (see @bugref{7859}).
3880 * Before it could happen that we signal PDM that we are done while we still have to
3881 * copy the data to the guest but EMT might be busy destroying the driver chains
3882 * below us while we have to delegate copying data to EMT instead of doing it
3883 * on this thread.
3884 */
3885 ASMAtomicDecU32(&pAhciPort->cTasksActive);
3886
3887 if (pAhciPort->cTasksActive == 0 && pAhciPort->pAhciR3->fSignalIdle)
3888 PDMDevHlpAsyncNotificationCompleted(pAhciPort->pDevInsR3);
3889
3890 return fCanceled;
3891}
3892
3893/**
3894 * @interface_method_impl{PDMIMEDIAEXPORT,pfnIoReqCopyFromBuf}
3895 */
3896static DECLCALLBACK(int) ahciR3IoReqCopyFromBuf(PPDMIMEDIAEXPORT pInterface, PDMMEDIAEXIOREQ hIoReq,
3897 void *pvIoReqAlloc, uint32_t offDst, PRTSGBUF pSgBuf,
3898 size_t cbCopy)
3899{
3900 RT_NOREF1(hIoReq);
3901 PAHCIPort pAhciPort = RT_FROM_MEMBER(pInterface, AHCIPort, IMediaExPort);
3902 int rc = VINF_SUCCESS;
3903 PAHCIREQ pIoReq = (PAHCIREQ)pvIoReqAlloc;
3904
3905 if (!pIoReq->pfnPostProcess)
3906 ahciR3CopySgBufToPrdtl(pAhciPort->CTX_SUFF(pAhci), pIoReq, pSgBuf, offDst, cbCopy);
3907 else
3908 {
3909 /* Post process data and copy afterwards. */
3910 void *pv = NULL;
3911 size_t cb = 0;
3912 rc = pIoReq->pfnPostProcess(pIoReq, pSgBuf, cbCopy, offDst, &pv, &cb);
3913 if (RT_SUCCESS(rc))
3914 {
3915 ahciR3CopyBufferToPrdtl(pAhciPort->CTX_SUFF(pAhci), pIoReq, pv, cb, offDst);
3916 RTMemFree(pv);
3917 }
3918 }
3919
3920 if (pIoReq->fFlags & AHCI_REQ_OVERFLOW)
3921 rc = VERR_PDM_MEDIAEX_IOBUF_OVERFLOW;
3922
3923 if (pIoReq->enmType == PDMMEDIAEXIOREQTYPE_SCSI)
3924 pIoReq->cbTransfer += cbCopy;
3925
3926 return rc;
3927}
3928
3929/**
3930 * @interface_method_impl{PDMIMEDIAEXPORT,pfnIoReqCopyToBuf}
3931 */
3932static DECLCALLBACK(int) ahciR3IoReqCopyToBuf(PPDMIMEDIAEXPORT pInterface, PDMMEDIAEXIOREQ hIoReq,
3933 void *pvIoReqAlloc, uint32_t offSrc, PRTSGBUF pSgBuf,
3934 size_t cbCopy)
3935{
3936 RT_NOREF1(hIoReq);
3937 PAHCIPort pAhciPort = RT_FROM_MEMBER(pInterface, AHCIPort, IMediaExPort);
3938 int rc = VINF_SUCCESS;
3939 PAHCIREQ pIoReq = (PAHCIREQ)pvIoReqAlloc;
3940
3941 ahciR3CopySgBufFromPrdtl(pAhciPort->CTX_SUFF(pAhci), pIoReq, pSgBuf, offSrc, cbCopy);
3942 if (pIoReq->fFlags & AHCI_REQ_OVERFLOW)
3943 rc = VERR_PDM_MEDIAEX_IOBUF_UNDERRUN;
3944
3945 return rc;
3946}
3947
3948/**
3949 * @interface_method_impl{PDMIMEDIAEXPORT,pfnIoReqQueryDiscardRanges}
3950 */
3951static DECLCALLBACK(int) ahciR3IoReqQueryDiscardRanges(PPDMIMEDIAEXPORT pInterface, PDMMEDIAEXIOREQ hIoReq,
3952 void *pvIoReqAlloc, uint32_t idxRangeStart,
3953 uint32_t cRanges, PRTRANGE paRanges,
3954 uint32_t *pcRanges)
3955{
3956 RT_NOREF1(hIoReq);
3957 PAHCIPort pAhciPort = RT_FROM_MEMBER(pInterface, AHCIPort, IMediaExPort);
3958 PAHCIREQ pIoReq = (PAHCIREQ)pvIoReqAlloc;
3959
3960 return ahciTrimRangesCreate(pAhciPort, pIoReq, idxRangeStart, paRanges, cRanges, pcRanges);
3961}
3962
3963/**
3964 * @interface_method_impl{PDMIMEDIAEXPORT,pfnIoReqCompleteNotify}
3965 */
3966static DECLCALLBACK(int) ahciR3IoReqCompleteNotify(PPDMIMEDIAEXPORT pInterface, PDMMEDIAEXIOREQ hIoReq,
3967 void *pvIoReqAlloc, int rcReq)
3968{
3969 RT_NOREF(hIoReq);
3970 PAHCIPort pAhciPort = RT_FROM_MEMBER(pInterface, AHCIPort, IMediaExPort);
3971 ahciTransferComplete(pAhciPort, (PAHCIREQ)pvIoReqAlloc, rcReq);
3972 return VINF_SUCCESS;
3973}
3974
3975/**
3976 * @interface_method_impl{PDMIMEDIAEXPORT,pfnIoReqStateChanged}
3977 */
3978static DECLCALLBACK(void) ahciR3IoReqStateChanged(PPDMIMEDIAEXPORT pInterface, PDMMEDIAEXIOREQ hIoReq,
3979 void *pvIoReqAlloc, PDMMEDIAEXIOREQSTATE enmState)
3980{
3981 RT_NOREF2(hIoReq, pvIoReqAlloc);
3982 PAHCIPort pAhciPort = RT_FROM_MEMBER(pInterface, AHCIPort, IMediaExPort);
3983
3984 switch (enmState)
3985 {
3986 case PDMMEDIAEXIOREQSTATE_SUSPENDED:
3987 {
3988 /* Make sure the request is not accounted for so the VM can suspend successfully. */
3989 uint32_t cTasksActive = ASMAtomicDecU32(&pAhciPort->cTasksActive);
3990 if (!cTasksActive && pAhciPort->pAhciR3->fSignalIdle)
3991 PDMDevHlpAsyncNotificationCompleted(pAhciPort->pDevInsR3);
3992 break;
3993 }
3994 case PDMMEDIAEXIOREQSTATE_ACTIVE:
3995 /* Make sure the request is accounted for so the VM suspends only when the request is complete. */
3996 ASMAtomicIncU32(&pAhciPort->cTasksActive);
3997 break;
3998 default:
3999 AssertMsgFailed(("Invalid request state given %u\n", enmState));
4000 }
4001}
4002
4003/**
4004 * @interface_method_impl{PDMIMEDIAEXPORT,pfnMediumEjected}
4005 */
4006static DECLCALLBACK(void) ahciR3MediumEjected(PPDMIMEDIAEXPORT pInterface)
4007{
4008 PAHCIPort pAhciPort = RT_FROM_MEMBER(pInterface, AHCIPort, IMediaExPort);
4009 PAHCI pThis = pAhciPort->CTX_SUFF(pAhci);
4010
4011 if (pThis->pMediaNotify)
4012 {
4013 int rc = VMR3ReqCallNoWait(PDMDevHlpGetVM(pThis->CTX_SUFF(pDevIns)), VMCPUID_ANY,
4014 (PFNRT)pThis->pMediaNotify->pfnEjected, 2,
4015 pThis->pMediaNotify, pAhciPort->iLUN);
4016 AssertRC(rc);
4017 }
4018}
4019
4020/**
4021 * Process an non read/write ATA command.
4022 *
4023 * @returns The direction of the data transfer
4024 * @param pAhciPort The AHCI port of the request.
4025 * @param pAhciReq The AHCI request state.
4026 * @param pCmdFis Pointer to the command FIS.
4027 */
4028static PDMMEDIAEXIOREQTYPE ahciProcessCmd(PAHCIPort pAhciPort, PAHCIREQ pAhciReq, uint8_t *pCmdFis)
4029{
4030 PDMMEDIAEXIOREQTYPE enmType = PDMMEDIAEXIOREQTYPE_INVALID;
4031 bool fLBA48 = false;
4032
4033 AssertMsg(pCmdFis[AHCI_CMDFIS_TYPE] == AHCI_CMDFIS_TYPE_H2D, ("FIS is not a host to device Fis!!\n"));
4034
4035 pAhciReq->cbTransfer = 0;
4036
4037 switch (pCmdFis[AHCI_CMDFIS_CMD])
4038 {
4039 case ATA_IDENTIFY_DEVICE:
4040 {
4041 if (pAhciPort->pDrvMedia && !pAhciPort->fATAPI)
4042 {
4043 uint16_t u16Temp[256];
4044
4045 /* Fill the buffer. */
4046 ahciIdentifySS(pAhciPort, u16Temp);
4047
4048 /* Copy the buffer. */
4049 size_t cbCopied = ahciR3CopyBufferToPrdtl(pAhciPort->CTX_SUFF(pAhci), pAhciReq,
4050 &u16Temp[0], sizeof(u16Temp), 0 /* cbSkip */);
4051
4052 pAhciReq->fFlags |= AHCI_REQ_PIO_DATA;
4053 pAhciReq->cbTransfer = cbCopied;
4054 ahciReqSetStatus(pAhciReq, 0, ATA_STAT_READY | ATA_STAT_SEEK);
4055 }
4056 else
4057 ahciReqSetStatus(pAhciReq, ABRT_ERR, ATA_STAT_READY | ATA_STAT_SEEK | ATA_STAT_ERR);
4058 break;
4059 }
4060 case ATA_READ_NATIVE_MAX_ADDRESS_EXT:
4061 case ATA_READ_NATIVE_MAX_ADDRESS:
4062 break;
4063 case ATA_SET_FEATURES:
4064 {
4065 switch (pCmdFis[AHCI_CMDFIS_FET])
4066 {
4067 case 0x02: /* write cache enable */
4068 case 0xaa: /* read look-ahead enable */
4069 case 0x55: /* read look-ahead disable */
4070 case 0xcc: /* reverting to power-on defaults enable */
4071 case 0x66: /* reverting to power-on defaults disable */
4072 ahciReqSetStatus(pAhciReq, 0, ATA_STAT_READY | ATA_STAT_SEEK);
4073 break;
4074 case 0x82: /* write cache disable */
4075 enmType = PDMMEDIAEXIOREQTYPE_FLUSH;
4076 break;
4077 case 0x03:
4078 {
4079 /* set transfer mode */
4080 Log2(("%s: transfer mode %#04x\n", __FUNCTION__, pCmdFis[AHCI_CMDFIS_SECTC]));
4081 switch (pCmdFis[AHCI_CMDFIS_SECTC] & 0xf8)
4082 {
4083 case 0x00: /* PIO default */
4084 case 0x08: /* PIO mode */
4085 break;
4086 case ATA_MODE_MDMA: /* MDMA mode */
4087 pAhciPort->uATATransferMode = (pCmdFis[AHCI_CMDFIS_SECTC] & 0xf8) | RT_MIN(pCmdFis[AHCI_CMDFIS_SECTC] & 0x07, ATA_MDMA_MODE_MAX);
4088 break;
4089 case ATA_MODE_UDMA: /* UDMA mode */
4090 pAhciPort->uATATransferMode = (pCmdFis[AHCI_CMDFIS_SECTC] & 0xf8) | RT_MIN(pCmdFis[AHCI_CMDFIS_SECTC] & 0x07, ATA_UDMA_MODE_MAX);
4091 break;
4092 }
4093 ahciReqSetStatus(pAhciReq, 0, ATA_STAT_READY | ATA_STAT_SEEK);
4094 break;
4095 }
4096 default:
4097 ahciReqSetStatus(pAhciReq, ABRT_ERR, ATA_STAT_READY | ATA_STAT_ERR);
4098 }
4099 break;
4100 }
4101 case ATA_DEVICE_RESET:
4102 {
4103 if (!pAhciPort->fATAPI)
4104 ahciReqSetStatus(pAhciReq, ABRT_ERR, ATA_STAT_READY | ATA_STAT_ERR);
4105 else
4106 {
4107 /* Reset the device. */
4108 ahciDeviceReset(pAhciPort, pAhciReq);
4109 }
4110 break;
4111 }
4112 case ATA_FLUSH_CACHE_EXT:
4113 case ATA_FLUSH_CACHE:
4114 enmType = PDMMEDIAEXIOREQTYPE_FLUSH;
4115 break;
4116 case ATA_PACKET:
4117 if (!pAhciPort->fATAPI)
4118 ahciReqSetStatus(pAhciReq, ABRT_ERR, ATA_STAT_READY | ATA_STAT_ERR);
4119 else
4120 enmType = PDMMEDIAEXIOREQTYPE_SCSI;
4121 break;
4122 case ATA_IDENTIFY_PACKET_DEVICE:
4123 if (!pAhciPort->fATAPI)
4124 ahciReqSetStatus(pAhciReq, ABRT_ERR, ATA_STAT_READY | ATA_STAT_ERR);
4125 else
4126 {
4127 size_t cbData;
4128 ahciR3AtapiIdentify(pAhciReq, pAhciPort, 512, &cbData);
4129
4130 pAhciReq->fFlags |= AHCI_REQ_PIO_DATA;
4131 pAhciReq->cbTransfer = cbData;
4132 pAhciReq->cmdFis[AHCI_CMDFIS_SECTN] = (pAhciReq->cmdFis[AHCI_CMDFIS_SECTN] & ~7)
4133 | ((pAhciReq->fFlags & AHCI_REQ_XFER_2_HOST) ? ATAPI_INT_REASON_IO : 0)
4134 | (!pAhciReq->cbTransfer ? ATAPI_INT_REASON_CD : 0);
4135
4136 ahciReqSetStatus(pAhciReq, 0, ATA_STAT_READY | ATA_STAT_SEEK);
4137 }
4138 break;
4139 case ATA_SET_MULTIPLE_MODE:
4140 if ( pCmdFis[AHCI_CMDFIS_SECTC] != 0
4141 && ( pCmdFis[AHCI_CMDFIS_SECTC] > ATA_MAX_MULT_SECTORS
4142 || (pCmdFis[AHCI_CMDFIS_SECTC] & (pCmdFis[AHCI_CMDFIS_SECTC] - 1)) != 0))
4143 ahciReqSetStatus(pAhciReq, ABRT_ERR, ATA_STAT_READY | ATA_STAT_ERR);
4144 else
4145 {
4146 Log2(("%s: set multi sector count to %d\n", __FUNCTION__, pCmdFis[AHCI_CMDFIS_SECTC]));
4147 pAhciPort->cMultSectors = pCmdFis[AHCI_CMDFIS_SECTC];
4148 ahciReqSetStatus(pAhciReq, 0, ATA_STAT_READY | ATA_STAT_SEEK);
4149 }
4150 break;
4151 case ATA_STANDBY_IMMEDIATE:
4152 break; /* Do nothing. */
4153 case ATA_CHECK_POWER_MODE:
4154 pAhciReq->cmdFis[AHCI_CMDFIS_SECTC] = 0xff; /* drive active or idle */
4155 /* fall through */
4156 case ATA_INITIALIZE_DEVICE_PARAMETERS:
4157 case ATA_IDLE_IMMEDIATE:
4158 case ATA_RECALIBRATE:
4159 case ATA_NOP:
4160 case ATA_READ_VERIFY_SECTORS_EXT:
4161 case ATA_READ_VERIFY_SECTORS:
4162 case ATA_READ_VERIFY_SECTORS_WITHOUT_RETRIES:
4163 case ATA_SLEEP:
4164 ahciReqSetStatus(pAhciReq, 0, ATA_STAT_READY | ATA_STAT_SEEK);
4165 break;
4166 case ATA_READ_DMA_EXT:
4167 fLBA48 = true;
4168 case ATA_READ_DMA:
4169 {
4170 pAhciReq->cbTransfer = ahciGetNSectors(pCmdFis, fLBA48) * pAhciPort->cbSector;
4171 pAhciReq->uOffset = ahciGetSector(pAhciPort, pCmdFis, fLBA48) * pAhciPort->cbSector;
4172 enmType = PDMMEDIAEXIOREQTYPE_READ;
4173 break;
4174 }
4175 case ATA_WRITE_DMA_EXT:
4176 fLBA48 = true;
4177 case ATA_WRITE_DMA:
4178 {
4179 pAhciReq->cbTransfer = ahciGetNSectors(pCmdFis, fLBA48) * pAhciPort->cbSector;
4180 pAhciReq->uOffset = ahciGetSector(pAhciPort, pCmdFis, fLBA48) * pAhciPort->cbSector;
4181 enmType = PDMMEDIAEXIOREQTYPE_WRITE;
4182 break;
4183 }
4184 case ATA_READ_FPDMA_QUEUED:
4185 {
4186 pAhciReq->cbTransfer = ahciGetNSectorsQueued(pCmdFis) * pAhciPort->cbSector;
4187 pAhciReq->uOffset = ahciGetSectorQueued(pCmdFis) * pAhciPort->cbSector;
4188 pAhciReq->fFlags |= AHCI_REQ_IS_QUEUED;
4189 enmType = PDMMEDIAEXIOREQTYPE_READ;
4190 break;
4191 }
4192 case ATA_WRITE_FPDMA_QUEUED:
4193 {
4194 pAhciReq->cbTransfer = ahciGetNSectorsQueued(pCmdFis) * pAhciPort->cbSector;
4195 pAhciReq->uOffset = ahciGetSectorQueued(pCmdFis) * pAhciPort->cbSector;
4196 pAhciReq->fFlags |= AHCI_REQ_IS_QUEUED;
4197 enmType = PDMMEDIAEXIOREQTYPE_WRITE;
4198 break;
4199 }
4200 case ATA_READ_LOG_EXT:
4201 {
4202 size_t cbLogRead = ((pCmdFis[AHCI_CMDFIS_SECTCEXP] << 8) | pCmdFis[AHCI_CMDFIS_SECTC]) * 512;
4203 unsigned offLogRead = ((pCmdFis[AHCI_CMDFIS_CYLLEXP] << 8) | pCmdFis[AHCI_CMDFIS_CYLL]) * 512;
4204 unsigned iPage = pCmdFis[AHCI_CMDFIS_SECTN];
4205
4206 LogFlow(("Trying to read %zu bytes starting at offset %u from page %u\n", cbLogRead, offLogRead, iPage));
4207
4208 uint8_t aBuf[512];
4209
4210 memset(aBuf, 0, sizeof(aBuf));
4211
4212 if (offLogRead + cbLogRead <= sizeof(aBuf))
4213 {
4214 switch (iPage)
4215 {
4216 case 0x10:
4217 {
4218 LogFlow(("Reading error page\n"));
4219 PAHCIREQ pTaskErr = ASMAtomicXchgPtrT(&pAhciPort->pTaskErr, NULL, PAHCIREQ);
4220 if (pTaskErr)
4221 {
4222 aBuf[0] = (pTaskErr->fFlags & AHCI_REQ_IS_QUEUED) ? pTaskErr->uTag : (1 << 7);
4223 aBuf[2] = pTaskErr->cmdFis[AHCI_CMDFIS_STS];
4224 aBuf[3] = pTaskErr->cmdFis[AHCI_CMDFIS_ERR];
4225 aBuf[4] = pTaskErr->cmdFis[AHCI_CMDFIS_SECTN];
4226 aBuf[5] = pTaskErr->cmdFis[AHCI_CMDFIS_CYLL];
4227 aBuf[6] = pTaskErr->cmdFis[AHCI_CMDFIS_CYLH];
4228 aBuf[7] = pTaskErr->cmdFis[AHCI_CMDFIS_HEAD];
4229 aBuf[8] = pTaskErr->cmdFis[AHCI_CMDFIS_SECTNEXP];
4230 aBuf[9] = pTaskErr->cmdFis[AHCI_CMDFIS_CYLLEXP];
4231 aBuf[10] = pTaskErr->cmdFis[AHCI_CMDFIS_CYLHEXP];
4232 aBuf[12] = pTaskErr->cmdFis[AHCI_CMDFIS_SECTC];
4233 aBuf[13] = pTaskErr->cmdFis[AHCI_CMDFIS_SECTCEXP];
4234
4235 /* Calculate checksum */
4236 uint8_t uChkSum = 0;
4237 for (unsigned i = 0; i < RT_ELEMENTS(aBuf)-1; i++)
4238 uChkSum += aBuf[i];
4239
4240 aBuf[511] = (uint8_t)-(int8_t)uChkSum;
4241
4242 /* Finally free the error task state structure because it is completely unused now. */
4243 RTMemFree(pTaskErr);
4244 }
4245
4246 /*
4247 * Reading this log page results in an abort of all outstanding commands
4248 * and clearing the SActive register and TaskFile register.
4249 *
4250 * See SATA2 1.2 spec chapter 4.2.3.4
4251 */
4252 bool fAbortedAll = ahciCancelActiveTasks(pAhciPort);
4253 Assert(fAbortedAll); NOREF(fAbortedAll);
4254 ahciSendSDBFis(pAhciPort, 0xffffffff, true);
4255
4256 break;
4257 }
4258 }
4259
4260 /* Copy the buffer. */
4261 size_t cbCopied = ahciR3CopyBufferToPrdtl(pAhciPort->CTX_SUFF(pAhci), pAhciReq,
4262 &aBuf[offLogRead], cbLogRead, 0 /* cbSkip */);
4263
4264 pAhciReq->fFlags |= AHCI_REQ_PIO_DATA;
4265 pAhciReq->cbTransfer = cbCopied;
4266 }
4267
4268 break;
4269 }
4270 case ATA_DATA_SET_MANAGEMENT:
4271 {
4272 if (pAhciPort->fTrimEnabled)
4273 {
4274 /* Check that the trim bit is set and all other bits are 0. */
4275 if ( !(pAhciReq->cmdFis[AHCI_CMDFIS_FET] & UINT16_C(0x01))
4276 || (pAhciReq->cmdFis[AHCI_CMDFIS_FET] & ~UINT16_C(0x1)))
4277 ahciReqSetStatus(pAhciReq, ABRT_ERR, ATA_STAT_READY | ATA_STAT_ERR);
4278 else
4279 enmType = PDMMEDIAEXIOREQTYPE_DISCARD;
4280 break;
4281 }
4282 /* else: fall through and report error to the guest. */
4283 }
4284 /* All not implemented commands go below. */
4285 case ATA_SECURITY_FREEZE_LOCK:
4286 case ATA_SMART:
4287 case ATA_NV_CACHE:
4288 case ATA_IDLE:
4289 case ATA_TRUSTED_RECEIVE_DMA: /* Windows 8+ */
4290 ahciReqSetStatus(pAhciReq, ABRT_ERR, ATA_STAT_READY | ATA_STAT_ERR);
4291 break;
4292 default: /* For debugging purposes. */
4293 AssertMsgFailed(("Unknown command issued (%#x)\n", pCmdFis[AHCI_CMDFIS_CMD]));
4294 ahciReqSetStatus(pAhciReq, ABRT_ERR, ATA_STAT_READY | ATA_STAT_ERR);
4295 }
4296
4297 return enmType;
4298}
4299
4300/**
4301 * Retrieve a command FIS from guest memory.
4302 *
4303 * @returns whether the H2D FIS was successfully read from the guest memory.
4304 * @param pAhciPort The AHCI port of the request.
4305 * @param pAhciReq The state of the actual task.
4306 */
4307static bool ahciPortTaskGetCommandFis(PAHCIPort pAhciPort, PAHCIREQ pAhciReq)
4308{
4309 AssertMsgReturn(pAhciPort->GCPhysAddrClb && pAhciPort->GCPhysAddrFb,
4310 ("%s: GCPhysAddrClb and/or GCPhysAddrFb are 0\n", __FUNCTION__),
4311 false);
4312
4313 /*
4314 * First we are reading the command header pointed to by regCLB.
4315 * From this we get the address of the command table which we are reading too.
4316 * We can process the Command FIS afterwards.
4317 */
4318 CmdHdr cmdHdr;
4319 pAhciReq->GCPhysCmdHdrAddr = pAhciPort->GCPhysAddrClb + pAhciReq->uTag * sizeof(CmdHdr);
4320 LogFlow(("%s: PDMDevHlpPhysRead GCPhysAddrCmdLst=%RGp cbCmdHdr=%u\n", __FUNCTION__,
4321 pAhciReq->GCPhysCmdHdrAddr, sizeof(CmdHdr)));
4322 PDMDevHlpPhysRead(pAhciPort->CTX_SUFF(pDevIns), pAhciReq->GCPhysCmdHdrAddr, &cmdHdr, sizeof(CmdHdr));
4323
4324#ifdef LOG_ENABLED
4325 /* Print some infos about the command header. */
4326 ahciDumpCmdHdrInfo(pAhciPort, &cmdHdr);
4327#endif
4328
4329 RTGCPHYS GCPhysAddrCmdTbl = AHCI_RTGCPHYS_FROM_U32(cmdHdr.u32CmdTblAddrUp, cmdHdr.u32CmdTblAddr);
4330
4331 AssertMsgReturn((cmdHdr.u32DescInf & AHCI_CMDHDR_CFL_MASK) * sizeof(uint32_t) == AHCI_CMDFIS_TYPE_H2D_SIZE,
4332 ("This is not a command FIS!!\n"),
4333 false);
4334
4335 /* Read the command Fis. */
4336 LogFlow(("%s: PDMDevHlpPhysRead GCPhysAddrCmdTbl=%RGp cbCmdFis=%u\n", __FUNCTION__, GCPhysAddrCmdTbl, AHCI_CMDFIS_TYPE_H2D_SIZE));
4337 PDMDevHlpPhysRead(pAhciPort->CTX_SUFF(pDevIns), GCPhysAddrCmdTbl, &pAhciReq->cmdFis[0], AHCI_CMDFIS_TYPE_H2D_SIZE);
4338
4339 AssertMsgReturn(pAhciReq->cmdFis[AHCI_CMDFIS_TYPE] == AHCI_CMDFIS_TYPE_H2D,
4340 ("This is not a command FIS\n"),
4341 false);
4342
4343 /* Set transfer direction. */
4344 pAhciReq->fFlags |= (cmdHdr.u32DescInf & AHCI_CMDHDR_W) ? 0 : AHCI_REQ_XFER_2_HOST;
4345
4346 /* If this is an ATAPI command read the atapi command. */
4347 if (cmdHdr.u32DescInf & AHCI_CMDHDR_A)
4348 {
4349 GCPhysAddrCmdTbl += AHCI_CMDHDR_ACMD_OFFSET;
4350 PDMDevHlpPhysRead(pAhciPort->CTX_SUFF(pDevIns), GCPhysAddrCmdTbl, &pAhciReq->aATAPICmd[0], ATAPI_PACKET_SIZE);
4351 }
4352
4353 /* We "received" the FIS. Clear the BSY bit in regTFD. */
4354 if ((cmdHdr.u32DescInf & AHCI_CMDHDR_C) && (pAhciReq->fFlags & AHCI_REQ_CLEAR_SACT))
4355 {
4356 /*
4357 * We need to send a FIS which clears the busy bit if this is a queued command so that the guest can queue other commands.
4358 * but this FIS does not assert an interrupt
4359 */
4360 ahciSendD2HFis(pAhciPort, pAhciReq->uTag, pAhciReq->cmdFis, false);
4361 pAhciPort->regTFD &= ~AHCI_PORT_TFD_BSY;
4362 }
4363
4364 pAhciReq->GCPhysPrdtl = AHCI_RTGCPHYS_FROM_U32(cmdHdr.u32CmdTblAddrUp, cmdHdr.u32CmdTblAddr) + AHCI_CMDHDR_PRDT_OFFSET;
4365 pAhciReq->cPrdtlEntries = AHCI_CMDHDR_PRDTL_ENTRIES(cmdHdr.u32DescInf);
4366
4367#ifdef LOG_ENABLED
4368 /* Print some infos about the FIS. */
4369 ahciDumpFisInfo(pAhciPort, &pAhciReq->cmdFis[0]);
4370
4371 /* Print the PRDT */
4372 ahciLog(("PRDT address %RGp number of entries %u\n", pAhciReq->GCPhysPrdtl, pAhciReq->cPrdtlEntries));
4373 RTGCPHYS GCPhysPrdtl = pAhciReq->GCPhysPrdtl;
4374
4375 for (unsigned i = 0; i < pAhciReq->cPrdtlEntries; i++)
4376 {
4377 SGLEntry SGEntry;
4378
4379 ahciLog(("Entry %u at address %RGp\n", i, GCPhysPrdtl));
4380 PDMDevHlpPhysRead(pAhciPort->CTX_SUFF(pDevIns), GCPhysPrdtl, &SGEntry, sizeof(SGLEntry));
4381
4382 RTGCPHYS GCPhysDataAddr = AHCI_RTGCPHYS_FROM_U32(SGEntry.u32DBAUp, SGEntry.u32DBA);
4383 ahciLog(("GCPhysAddr=%RGp Size=%u\n", GCPhysDataAddr, SGEntry.u32DescInf & SGLENTRY_DESCINF_DBC));
4384
4385 GCPhysPrdtl += sizeof(SGLEntry);
4386 }
4387#endif
4388
4389 return true;
4390}
4391
4392/**
4393 * Submits a given request for execution.
4394 *
4395 * @returns Flag whether the request was canceled inbetween.
4396 * @param pAhciPort The port the request is for.
4397 * @param pAhciReq The request to submit.
4398 * @param enmType The request type.
4399 */
4400static bool ahciR3ReqSubmit(PAHCIPort pAhciPort, PAHCIREQ pAhciReq, PDMMEDIAEXIOREQTYPE enmType)
4401{
4402 int rc = VINF_SUCCESS;
4403 bool fReqCanceled = false;
4404
4405 VBOXDD_AHCI_REQ_SUBMIT(pAhciReq, pAhciReq->enmType, pAhciReq->uOffset, pAhciReq->cbTransfer);
4406
4407 if (enmType == PDMMEDIAEXIOREQTYPE_FLUSH)
4408 rc = pAhciPort->pDrvMediaEx->pfnIoReqFlush(pAhciPort->pDrvMediaEx, pAhciReq->hIoReq);
4409 else if (enmType == PDMMEDIAEXIOREQTYPE_DISCARD)
4410 {
4411 uint32_t cRangesMax;
4412
4413 /* The data buffer contains LBA range entries. Each range is 8 bytes big. */
4414 if (!pAhciReq->cmdFis[AHCI_CMDFIS_SECTC] && !pAhciReq->cmdFis[AHCI_CMDFIS_SECTCEXP])
4415 cRangesMax = 65536 * 512 / 8;
4416 else
4417 cRangesMax = pAhciReq->cmdFis[AHCI_CMDFIS_SECTC] * 512 / 8;
4418
4419 pAhciPort->Led.Asserted.s.fWriting = pAhciPort->Led.Actual.s.fWriting = 1;
4420 rc = pAhciPort->pDrvMediaEx->pfnIoReqDiscard(pAhciPort->pDrvMediaEx, pAhciReq->hIoReq,
4421 cRangesMax);
4422 }
4423 else if (enmType == PDMMEDIAEXIOREQTYPE_READ)
4424 {
4425 pAhciPort->Led.Asserted.s.fReading = pAhciPort->Led.Actual.s.fReading = 1;
4426 rc = pAhciPort->pDrvMediaEx->pfnIoReqRead(pAhciPort->pDrvMediaEx, pAhciReq->hIoReq,
4427 pAhciReq->uOffset, pAhciReq->cbTransfer);
4428 }
4429 else if (enmType == PDMMEDIAEXIOREQTYPE_WRITE)
4430 {
4431 pAhciPort->Led.Asserted.s.fWriting = pAhciPort->Led.Actual.s.fWriting = 1;
4432 rc = pAhciPort->pDrvMediaEx->pfnIoReqWrite(pAhciPort->pDrvMediaEx, pAhciReq->hIoReq,
4433 pAhciReq->uOffset, pAhciReq->cbTransfer);
4434 }
4435 else if (enmType == PDMMEDIAEXIOREQTYPE_SCSI)
4436 {
4437 size_t cbBuf = 0;
4438
4439 if (pAhciReq->cPrdtlEntries)
4440 rc = ahciR3PrdtQuerySize(pAhciPort->CTX_SUFF(pAhci), pAhciReq, &cbBuf);
4441 if (RT_SUCCESS(rc))
4442 {
4443 if (cbBuf && (pAhciReq->fFlags & AHCI_REQ_XFER_2_HOST))
4444 pAhciPort->Led.Asserted.s.fReading = pAhciPort->Led.Actual.s.fReading = 1;
4445 else if (cbBuf)
4446 pAhciPort->Led.Asserted.s.fWriting = pAhciPort->Led.Actual.s.fWriting = 1;
4447 rc = pAhciPort->pDrvMediaEx->pfnIoReqSendScsiCmd(pAhciPort->pDrvMediaEx, pAhciReq->hIoReq,
4448 0, &pAhciReq->aATAPICmd[0], ATAPI_PACKET_SIZE,
4449 PDMMEDIAEXIOREQSCSITXDIR_UNKNOWN, cbBuf,
4450 &pAhciPort->abATAPISense[0], sizeof(pAhciPort->abATAPISense),
4451 &pAhciReq->u8ScsiSts, 30 * RT_MS_1SEC);
4452 }
4453 }
4454
4455 if (rc == VINF_SUCCESS)
4456 fReqCanceled = ahciTransferComplete(pAhciPort, pAhciReq, VINF_SUCCESS);
4457 else if (rc != VINF_PDM_MEDIAEX_IOREQ_IN_PROGRESS)
4458 fReqCanceled = ahciTransferComplete(pAhciPort, pAhciReq, rc);
4459
4460 return fReqCanceled;
4461}
4462
4463/**
4464 * Prepares the command for execution coping it from guest memory and doing a few
4465 * validation checks on it.
4466 *
4467 * @returns Whether the command was successfully fetched from guest memory and
4468 * can be continued.
4469 * @param pAhciPort The AHCI port the request is for.
4470 * @param pAhciReq Request structure to copy the command to.
4471 */
4472static bool ahciR3CmdPrepare(PAHCIPort pAhciPort, PAHCIREQ pAhciReq)
4473{
4474 /* Set current command slot */
4475 ASMAtomicWriteU32(&pAhciPort->u32CurrentCommandSlot, pAhciReq->uTag);
4476
4477 bool fContinue = ahciPortTaskGetCommandFis(pAhciPort, pAhciReq);
4478 if (fContinue)
4479 {
4480 /* Mark the task as processed by the HBA if this is a queued task so that it doesn't occur in the CI register anymore. */
4481 if (pAhciPort->regSACT & RT_BIT_32(pAhciReq->uTag))
4482 {
4483 pAhciReq->fFlags |= AHCI_REQ_CLEAR_SACT;
4484 ASMAtomicOrU32(&pAhciPort->u32TasksFinished, RT_BIT_32(pAhciReq->uTag));
4485 }
4486
4487 if (pAhciReq->cmdFis[AHCI_CMDFIS_BITS] & AHCI_CMDFIS_C)
4488 {
4489 /*
4490 * It is possible that the request counter can get one higher than the maximum because
4491 * the request counter is decremented after the guest was notified about the completed
4492 * request (see @bugref{7859}). If the completing thread is preempted in between the
4493 * guest might already issue another request before the request counter is decremented
4494 * which would trigger the following assertion incorrectly in the past.
4495 */
4496 AssertLogRelMsg(ASMAtomicReadU32(&pAhciPort->cTasksActive) <= AHCI_NR_COMMAND_SLOTS,
4497 ("AHCI#%uP%u: There are more than %u (+1) requests active",
4498 pAhciPort->CTX_SUFF(pDevIns)->iInstance, pAhciPort->iLUN,
4499 AHCI_NR_COMMAND_SLOTS));
4500 ASMAtomicIncU32(&pAhciPort->cTasksActive);
4501 }
4502 else
4503 {
4504 /* If the reset bit is set put the device into reset state. */
4505 if (pAhciReq->cmdFis[AHCI_CMDFIS_CTL] & AHCI_CMDFIS_CTL_SRST)
4506 {
4507 ahciLog(("%s: Setting device into reset state\n", __FUNCTION__));
4508 pAhciPort->fResetDevice = true;
4509 ahciSendD2HFis(pAhciPort, pAhciReq->uTag, pAhciReq->cmdFis, true);
4510 }
4511 else if (pAhciPort->fResetDevice) /* The bit is not set and we are in a reset state. */
4512 ahciFinishStorageDeviceReset(pAhciPort, pAhciReq);
4513 else /* We are not in a reset state update the control registers. */
4514 AssertMsgFailed(("%s: Update the control register\n", __FUNCTION__));
4515
4516 fContinue = false;
4517 }
4518 }
4519 else
4520 {
4521 /*
4522 * Couldn't find anything in either the AHCI or SATA spec which
4523 * indicates what should be done if the FIS is not read successfully.
4524 * The closest thing is in the state machine, stating that the device
4525 * should go into idle state again (SATA spec 1.0 chapter 8.7.1).
4526 * Do the same here and ignore any corrupt FIS types, after all
4527 * the guest messed up everything and this behavior is undefined.
4528 */
4529 fContinue = false;
4530 }
4531
4532 return fContinue;
4533}
4534
4535/**
4536 * Transmit queue consumer
4537 * Queue a new async task.
4538 *
4539 * @returns Success indicator.
4540 * If false the item will not be removed and the flushing will stop.
4541 * @param pDevIns The device instance.
4542 * @param pItem The item to consume. Upon return this item will be freed.
4543 */
4544static DECLCALLBACK(bool) ahciNotifyQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
4545{
4546 PDEVPORTNOTIFIERQUEUEITEM pNotifierItem = (PDEVPORTNOTIFIERQUEUEITEM)pItem;
4547 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
4548 PAHCIPort pAhciPort = &pThis->ahciPort[pNotifierItem->iPort];
4549 int rc = VINF_SUCCESS;
4550
4551 ahciLog(("%s: Got notification from GC\n", __FUNCTION__));
4552 /* Notify the async IO thread. */
4553 rc = SUPSemEventSignal(pThis->pSupDrvSession, pAhciPort->hEvtProcess);
4554 AssertRC(rc);
4555
4556 return true;
4557}
4558
4559/* The async IO thread for one port. */
4560static DECLCALLBACK(int) ahciAsyncIOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4561{
4562 RT_NOREF(pDevIns);
4563 PAHCIPort pAhciPort = (PAHCIPort)pThread->pvUser;
4564 PAHCI pAhci = pAhciPort->CTX_SUFF(pAhci);
4565 int rc = VINF_SUCCESS;
4566
4567 ahciLog(("%s: Port %d entering async IO loop.\n", __FUNCTION__, pAhciPort->iLUN));
4568
4569 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
4570 return VINF_SUCCESS;
4571
4572 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4573 {
4574 unsigned idx = 0;
4575 uint32_t u32Tasks = 0;
4576 uint32_t u32RegHbaCtrl = 0;
4577
4578 ASMAtomicWriteBool(&pAhciPort->fWrkThreadSleeping, true);
4579 u32Tasks = ASMAtomicXchgU32(&pAhciPort->u32TasksNew, 0);
4580 if (!u32Tasks)
4581 {
4582 Assert(ASMAtomicReadBool(&pAhciPort->fWrkThreadSleeping));
4583 rc = SUPSemEventWaitNoResume(pAhci->pSupDrvSession, pAhciPort->hEvtProcess, RT_INDEFINITE_WAIT);
4584 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
4585 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
4586 break;
4587 LogFlowFunc(("Woken up with rc=%Rrc\n", rc));
4588 u32Tasks = ASMAtomicXchgU32(&pAhciPort->u32TasksNew, 0);
4589 }
4590
4591 ASMAtomicWriteBool(&pAhciPort->fWrkThreadSleeping, false);
4592 ASMAtomicIncU32(&pAhci->cThreadsActive);
4593
4594 /* Check whether the thread should be suspended. */
4595 if (pAhci->fSignalIdle)
4596 {
4597 if (!ASMAtomicDecU32(&pAhci->cThreadsActive))
4598 PDMDevHlpAsyncNotificationCompleted(pAhciPort->pDevInsR3);
4599 continue;
4600 }
4601
4602 /*
4603 * Check whether the global host controller bit is set and go to sleep immediately again
4604 * if it is set.
4605 */
4606 u32RegHbaCtrl = ASMAtomicReadU32(&pAhci->regHbaCtrl);
4607 if ( u32RegHbaCtrl & AHCI_HBA_CTRL_HR
4608 && !ASMAtomicDecU32(&pAhci->cThreadsActive))
4609 {
4610 ahciHBAReset(pAhci);
4611 if (pAhci->fSignalIdle)
4612 PDMDevHlpAsyncNotificationCompleted(pAhciPort->pDevInsR3);
4613 continue;
4614 }
4615
4616 idx = ASMBitFirstSetU32(u32Tasks);
4617 while ( idx
4618 && !pAhciPort->fPortReset)
4619 {
4620 bool fReqCanceled = false;
4621
4622 /* Decrement to get the slot number. */
4623 idx--;
4624 ahciLog(("%s: Processing command at slot %d\n", __FUNCTION__, idx));
4625
4626 PAHCIREQ pAhciReq = ahciR3ReqAlloc(pAhciPort, idx);
4627 if (RT_LIKELY(pAhciReq))
4628 {
4629 pAhciReq->uTag = idx;
4630 pAhciReq->fFlags = 0;
4631
4632 bool fContinue = ahciR3CmdPrepare(pAhciPort, pAhciReq);
4633 if (fContinue)
4634 {
4635 PDMMEDIAEXIOREQTYPE enmType = ahciProcessCmd(pAhciPort, pAhciReq, pAhciReq->cmdFis);
4636 pAhciReq->enmType = enmType;
4637
4638 if (enmType != PDMMEDIAEXIOREQTYPE_INVALID)
4639 fReqCanceled = ahciR3ReqSubmit(pAhciPort, pAhciReq, enmType);
4640 else
4641 fReqCanceled = ahciTransferComplete(pAhciPort, pAhciReq, VINF_SUCCESS);
4642 } /* Command */
4643 else
4644 ahciR3ReqFree(pAhciPort, pAhciReq);
4645 }
4646 else /* !Request allocated, use on stack variant to signal the error. */
4647 {
4648 AHCIREQ Req;
4649 Req.uTag = idx;
4650 Req.fFlags = AHCI_REQ_IS_ON_STACK;
4651
4652 bool fContinue = ahciR3CmdPrepare(pAhciPort, &Req);
4653 if (fContinue)
4654 fReqCanceled = ahciTransferComplete(pAhciPort, &Req, VERR_NO_MEMORY);
4655 }
4656
4657 /*
4658 * Don't process other requests if the last one was canceled,
4659 * the others are not valid anymore.
4660 */
4661 if (fReqCanceled)
4662 break;
4663
4664 u32Tasks &= ~RT_BIT_32(idx); /* Clear task bit. */
4665 idx = ASMBitFirstSetU32(u32Tasks);
4666 } /* while tasks available */
4667
4668 /* Check whether a port reset was active. */
4669 if ( ASMAtomicReadBool(&pAhciPort->fPortReset)
4670 && (pAhciPort->regSCTL & AHCI_PORT_SCTL_DET) == AHCI_PORT_SCTL_DET_NINIT)
4671 ahciPortResetFinish(pAhciPort);
4672
4673 /*
4674 * Check whether a host controller reset is pending and execute the reset
4675 * if this is the last active thread.
4676 */
4677 u32RegHbaCtrl = ASMAtomicReadU32(&pAhci->regHbaCtrl);
4678 uint32_t cThreadsActive = ASMAtomicDecU32(&pAhci->cThreadsActive);
4679 if ( (u32RegHbaCtrl & AHCI_HBA_CTRL_HR)
4680 && !cThreadsActive)
4681 ahciHBAReset(pAhci);
4682
4683 if (!cThreadsActive && pAhci->fSignalIdle)
4684 PDMDevHlpAsyncNotificationCompleted(pAhciPort->pDevInsR3);
4685 } /* While running */
4686
4687 ahciLog(("%s: Port %d async IO thread exiting\n", __FUNCTION__, pAhciPort->iLUN));
4688 return VINF_SUCCESS;
4689}
4690
4691/**
4692 * Unblock the async I/O thread so it can respond to a state change.
4693 *
4694 * @returns VBox status code.
4695 * @param pDevIns The device instance.
4696 * @param pThread The send thread.
4697 */
4698static DECLCALLBACK(int) ahciAsyncIOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4699{
4700 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
4701 PAHCIPort pAhciPort = (PAHCIPort)pThread->pvUser;
4702 return SUPSemEventSignal(pThis->pSupDrvSession, pAhciPort->hEvtProcess);
4703}
4704
4705/* -=-=-=-=- DBGF -=-=-=-=- */
4706
4707/**
4708 * AHCI status info callback.
4709 *
4710 * @param pDevIns The device instance.
4711 * @param pHlp The output helpers.
4712 * @param pszArgs The arguments.
4713 */
4714static DECLCALLBACK(void) ahciR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4715{
4716 RT_NOREF(pszArgs);
4717 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
4718
4719 /*
4720 * Show info.
4721 */
4722 pHlp->pfnPrintf(pHlp,
4723 "%s#%d: mmio=%RGp ports=%u GC=%RTbool R0=%RTbool\n",
4724 pDevIns->pReg->szName,
4725 pDevIns->iInstance,
4726 pThis->MMIOBase,
4727 pThis->cPortsImpl,
4728 pThis->fGCEnabled ? true : false,
4729 pThis->fR0Enabled ? true : false);
4730
4731 /*
4732 * Show global registers.
4733 */
4734 pHlp->pfnPrintf(pHlp, "HbaCap=%#x\n", pThis->regHbaCap);
4735 pHlp->pfnPrintf(pHlp, "HbaCtrl=%#x\n", pThis->regHbaCtrl);
4736 pHlp->pfnPrintf(pHlp, "HbaIs=%#x\n", pThis->regHbaIs);
4737 pHlp->pfnPrintf(pHlp, "HbaPi=%#x", pThis->regHbaPi);
4738 pHlp->pfnPrintf(pHlp, "HbaVs=%#x\n", pThis->regHbaVs);
4739 pHlp->pfnPrintf(pHlp, "HbaCccCtl=%#x\n", pThis->regHbaCccCtl);
4740 pHlp->pfnPrintf(pHlp, "HbaCccPorts=%#x\n", pThis->regHbaCccPorts);
4741 pHlp->pfnPrintf(pHlp, "PortsInterrupted=%#x\n", pThis->u32PortsInterrupted);
4742
4743 /*
4744 * Per port data.
4745 */
4746 for (unsigned i = 0; i < pThis->cPortsImpl; i++)
4747 {
4748 PAHCIPort pThisPort = &pThis->ahciPort[i];
4749
4750 pHlp->pfnPrintf(pHlp, "Port %d: device-attached=%RTbool\n",
4751 pThisPort->iLUN, pThisPort->pDrvBase != NULL);
4752 pHlp->pfnPrintf(pHlp, "PortClb=%#x\n", pThisPort->regCLB);
4753 pHlp->pfnPrintf(pHlp, "PortClbU=%#x\n", pThisPort->regCLBU);
4754 pHlp->pfnPrintf(pHlp, "PortFb=%#x\n", pThisPort->regFB);
4755 pHlp->pfnPrintf(pHlp, "PortFbU=%#x\n", pThisPort->regFBU);
4756 pHlp->pfnPrintf(pHlp, "PortIs=%#x\n", pThisPort->regIS);
4757 pHlp->pfnPrintf(pHlp, "PortIe=%#x\n", pThisPort->regIE);
4758 pHlp->pfnPrintf(pHlp, "PortCmd=%#x\n", pThisPort->regCMD);
4759 pHlp->pfnPrintf(pHlp, "PortTfd=%#x\n", pThisPort->regTFD);
4760 pHlp->pfnPrintf(pHlp, "PortSig=%#x\n", pThisPort->regSIG);
4761 pHlp->pfnPrintf(pHlp, "PortSSts=%#x\n", pThisPort->regSSTS);
4762 pHlp->pfnPrintf(pHlp, "PortSCtl=%#x\n", pThisPort->regSCTL);
4763 pHlp->pfnPrintf(pHlp, "PortSErr=%#x\n", pThisPort->regSERR);
4764 pHlp->pfnPrintf(pHlp, "PortSAct=%#x\n", pThisPort->regSACT);
4765 pHlp->pfnPrintf(pHlp, "PortCi=%#x\n", pThisPort->regCI);
4766 pHlp->pfnPrintf(pHlp, "PortPhysClb=%RGp\n", pThisPort->GCPhysAddrClb);
4767 pHlp->pfnPrintf(pHlp, "PortPhysFb=%RGp\n", pThisPort->GCPhysAddrFb);
4768 pHlp->pfnPrintf(pHlp, "PortActTasksActive=%u\n", pThisPort->cTasksActive);
4769 pHlp->pfnPrintf(pHlp, "PortPoweredOn=%RTbool\n", pThisPort->fPoweredOn);
4770 pHlp->pfnPrintf(pHlp, "PortSpunUp=%RTbool\n", pThisPort->fSpunUp);
4771 pHlp->pfnPrintf(pHlp, "PortFirstD2HFisSend=%RTbool\n", pThisPort->fFirstD2HFisSend);
4772 pHlp->pfnPrintf(pHlp, "PortATAPI=%RTbool\n", pThisPort->fATAPI);
4773 pHlp->pfnPrintf(pHlp, "PortTasksFinished=%#x\n", pThisPort->u32TasksFinished);
4774 pHlp->pfnPrintf(pHlp, "PortQueuedTasksFinished=%#x\n", pThisPort->u32QueuedTasksFinished);
4775 pHlp->pfnPrintf(pHlp, "PortTasksNew=%#x\n", pThisPort->u32TasksNew);
4776 pHlp->pfnPrintf(pHlp, "\n");
4777 }
4778}
4779
4780/* -=-=-=-=- Helper -=-=-=-=- */
4781
4782/**
4783 * Checks if all asynchronous I/O is finished, both AHCI and IDE.
4784 *
4785 * Used by ahciR3Reset, ahciR3Suspend and ahciR3PowerOff. ahciR3SavePrep makes
4786 * use of it in strict builds (which is why it's up here).
4787 *
4788 * @returns true if quiesced, false if busy.
4789 * @param pDevIns The device instance.
4790 */
4791static bool ahciR3AllAsyncIOIsFinished(PPDMDEVINS pDevIns)
4792{
4793 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
4794
4795 if (pThis->cThreadsActive)
4796 return false;
4797
4798 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->ahciPort); i++)
4799 {
4800 PAHCIPort pThisPort = &pThis->ahciPort[i];
4801 if (pThisPort->pDrvBase)
4802 {
4803 if ( (pThisPort->cTasksActive != 0)
4804 || (pThisPort->u32TasksNew != 0))
4805 return false;
4806 }
4807 }
4808 return true;
4809}
4810
4811/* -=-=-=-=- Saved State -=-=-=-=- */
4812
4813/**
4814 * @callback_method_impl{FNSSMDEVSAVEPREP}
4815 */
4816static DECLCALLBACK(int) ahciR3SavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4817{
4818 RT_NOREF(pDevIns, pSSM);
4819 Assert(ahciR3AllAsyncIOIsFinished(pDevIns));
4820 return VINF_SUCCESS;
4821}
4822
4823/**
4824 * @callback_method_impl{FNSSMDEVLOADPREP}
4825 */
4826static DECLCALLBACK(int) ahciR3LoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4827{
4828 RT_NOREF(pDevIns, pSSM);
4829 Assert(ahciR3AllAsyncIOIsFinished(pDevIns));
4830 return VINF_SUCCESS;
4831}
4832
4833/**
4834 * @callback_method_impl{FNSSMDEVLIVEEXEC}
4835 */
4836static DECLCALLBACK(int) ahciR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
4837{
4838 RT_NOREF(uPass);
4839 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
4840
4841 /* config. */
4842 SSMR3PutU32(pSSM, pThis->cPortsImpl);
4843 for (uint32_t i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
4844 {
4845 SSMR3PutBool(pSSM, pThis->ahciPort[i].pDrvBase != NULL);
4846 SSMR3PutBool(pSSM, pThis->ahciPort[i].fHotpluggable);
4847 SSMR3PutStrZ(pSSM, pThis->ahciPort[i].szSerialNumber);
4848 SSMR3PutStrZ(pSSM, pThis->ahciPort[i].szFirmwareRevision);
4849 SSMR3PutStrZ(pSSM, pThis->ahciPort[i].szModelNumber);
4850 }
4851
4852 static const char *s_apszIdeEmuPortNames[4] = { "PrimaryMaster", "PrimarySlave", "SecondaryMaster", "SecondarySlave" };
4853 for (uint32_t i = 0; i < RT_ELEMENTS(s_apszIdeEmuPortNames); i++)
4854 {
4855 uint32_t iPort;
4856 int rc = CFGMR3QueryU32Def(pDevIns->pCfg, s_apszIdeEmuPortNames[i], &iPort, i);
4857 AssertRCReturn(rc, rc);
4858 SSMR3PutU32(pSSM, iPort);
4859 }
4860
4861 return VINF_SSM_DONT_CALL_AGAIN;
4862}
4863
4864/**
4865 * @callback_method_impl{FNSSMDEVSAVEEXEC}
4866 */
4867static DECLCALLBACK(int) ahciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4868{
4869 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
4870 uint32_t i;
4871 int rc;
4872
4873 Assert(!pThis->f8ByteMMIO4BytesWrittenSuccessfully);
4874
4875 /* The config */
4876 rc = ahciR3LiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
4877 AssertRCReturn(rc, rc);
4878
4879 /* The main device structure. */
4880 SSMR3PutU32(pSSM, pThis->regHbaCap);
4881 SSMR3PutU32(pSSM, pThis->regHbaCtrl);
4882 SSMR3PutU32(pSSM, pThis->regHbaIs);
4883 SSMR3PutU32(pSSM, pThis->regHbaPi);
4884 SSMR3PutU32(pSSM, pThis->regHbaVs);
4885 SSMR3PutU32(pSSM, pThis->regHbaCccCtl);
4886 SSMR3PutU32(pSSM, pThis->regHbaCccPorts);
4887 SSMR3PutU8(pSSM, pThis->uCccPortNr);
4888 SSMR3PutU64(pSSM, pThis->uCccTimeout);
4889 SSMR3PutU32(pSSM, pThis->uCccNr);
4890 SSMR3PutU32(pSSM, pThis->uCccCurrentNr);
4891 SSMR3PutU32(pSSM, pThis->u32PortsInterrupted);
4892 SSMR3PutBool(pSSM, pThis->fReset);
4893 SSMR3PutBool(pSSM, pThis->f64BitAddr);
4894 SSMR3PutBool(pSSM, pThis->fR0Enabled);
4895 SSMR3PutBool(pSSM, pThis->fGCEnabled);
4896 SSMR3PutBool(pSSM, pThis->fLegacyPortResetMethod);
4897
4898 /* Now every port. */
4899 for (i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
4900 {
4901 Assert(pThis->ahciPort[i].cTasksActive == 0);
4902 SSMR3PutU32(pSSM, pThis->ahciPort[i].regCLB);
4903 SSMR3PutU32(pSSM, pThis->ahciPort[i].regCLBU);
4904 SSMR3PutU32(pSSM, pThis->ahciPort[i].regFB);
4905 SSMR3PutU32(pSSM, pThis->ahciPort[i].regFBU);
4906 SSMR3PutGCPhys(pSSM, pThis->ahciPort[i].GCPhysAddrClb);
4907 SSMR3PutGCPhys(pSSM, pThis->ahciPort[i].GCPhysAddrFb);
4908 SSMR3PutU32(pSSM, pThis->ahciPort[i].regIS);
4909 SSMR3PutU32(pSSM, pThis->ahciPort[i].regIE);
4910 SSMR3PutU32(pSSM, pThis->ahciPort[i].regCMD);
4911 SSMR3PutU32(pSSM, pThis->ahciPort[i].regTFD);
4912 SSMR3PutU32(pSSM, pThis->ahciPort[i].regSIG);
4913 SSMR3PutU32(pSSM, pThis->ahciPort[i].regSSTS);
4914 SSMR3PutU32(pSSM, pThis->ahciPort[i].regSCTL);
4915 SSMR3PutU32(pSSM, pThis->ahciPort[i].regSERR);
4916 SSMR3PutU32(pSSM, pThis->ahciPort[i].regSACT);
4917 SSMR3PutU32(pSSM, pThis->ahciPort[i].regCI);
4918 SSMR3PutU32(pSSM, pThis->ahciPort[i].PCHSGeometry.cCylinders);
4919 SSMR3PutU32(pSSM, pThis->ahciPort[i].PCHSGeometry.cHeads);
4920 SSMR3PutU32(pSSM, pThis->ahciPort[i].PCHSGeometry.cSectors);
4921 SSMR3PutU64(pSSM, pThis->ahciPort[i].cTotalSectors);
4922 SSMR3PutU32(pSSM, pThis->ahciPort[i].cMultSectors);
4923 SSMR3PutU8(pSSM, pThis->ahciPort[i].uATATransferMode);
4924 SSMR3PutBool(pSSM, pThis->ahciPort[i].fResetDevice);
4925 SSMR3PutBool(pSSM, pThis->ahciPort[i].fPoweredOn);
4926 SSMR3PutBool(pSSM, pThis->ahciPort[i].fSpunUp);
4927 SSMR3PutU32(pSSM, pThis->ahciPort[i].u32TasksFinished);
4928 SSMR3PutU32(pSSM, pThis->ahciPort[i].u32QueuedTasksFinished);
4929 SSMR3PutU32(pSSM, pThis->ahciPort[i].u32CurrentCommandSlot);
4930
4931 /* ATAPI saved state. */
4932 SSMR3PutBool(pSSM, pThis->ahciPort[i].fATAPI);
4933 SSMR3PutMem(pSSM, &pThis->ahciPort[i].abATAPISense[0], sizeof(pThis->ahciPort[i].abATAPISense));
4934 }
4935
4936 return SSMR3PutU32(pSSM, UINT32_MAX); /* sanity/terminator */
4937}
4938
4939/**
4940 * Loads a saved legacy ATA emulated device state.
4941 *
4942 * @returns VBox status code.
4943 * @param pSSM The handle to the saved state.
4944 */
4945static int ahciR3LoadLegacyEmulationState(PSSMHANDLE pSSM)
4946{
4947 int rc;
4948 uint32_t u32Version;
4949 uint32_t u32;
4950 uint32_t u32IOBuffer;
4951
4952 /* Test for correct version. */
4953 rc = SSMR3GetU32(pSSM, &u32Version);
4954 AssertRCReturn(rc, rc);
4955 LogFlow(("LoadOldSavedStates u32Version = %d\n", u32Version));
4956
4957 if ( u32Version != ATA_CTL_SAVED_STATE_VERSION
4958 && u32Version != ATA_CTL_SAVED_STATE_VERSION_WITHOUT_FULL_SENSE
4959 && u32Version != ATA_CTL_SAVED_STATE_VERSION_WITHOUT_EVENT_STATUS)
4960 {
4961 AssertMsgFailed(("u32Version=%d\n", u32Version));
4962 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
4963 }
4964
4965 SSMR3Skip(pSSM, 19 + 5 * sizeof(bool) + sizeof(BMDMAState));
4966
4967 for (uint32_t j = 0; j < 2; j++)
4968 {
4969 SSMR3Skip(pSSM, 88 + 5 * sizeof(bool) );
4970
4971 if (u32Version > ATA_CTL_SAVED_STATE_VERSION_WITHOUT_FULL_SENSE)
4972 SSMR3Skip(pSSM, 64);
4973 else
4974 SSMR3Skip(pSSM, 2);
4975 /** @todo triple-check this hack after passthrough is working */
4976 SSMR3Skip(pSSM, 1);
4977
4978 if (u32Version > ATA_CTL_SAVED_STATE_VERSION_WITHOUT_EVENT_STATUS)
4979 SSMR3Skip(pSSM, 4);
4980
4981 SSMR3Skip(pSSM, sizeof(PDMLED));
4982 SSMR3GetU32(pSSM, &u32IOBuffer);
4983 if (u32IOBuffer)
4984 SSMR3Skip(pSSM, u32IOBuffer);
4985 }
4986
4987 rc = SSMR3GetU32(pSSM, &u32);
4988 if (RT_FAILURE(rc))
4989 return rc;
4990 if (u32 != ~0U)
4991 {
4992 AssertMsgFailed(("u32=%#x expected ~0\n", u32));
4993 rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4994 return rc;
4995 }
4996
4997 return VINF_SUCCESS;
4998}
4999
5000/**
5001 * @callback_method_impl{FNSSMDEVLOADEXEC}
5002 */
5003static DECLCALLBACK(int) ahciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5004{
5005 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
5006 uint32_t u32;
5007 int rc;
5008
5009 if ( uVersion > AHCI_SAVED_STATE_VERSION
5010 || uVersion < AHCI_SAVED_STATE_VERSION_VBOX_30)
5011 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
5012
5013 /* Deal with the priod after removing the saved IDE bits where the saved
5014 state version remained unchanged. */
5015 if ( uVersion == AHCI_SAVED_STATE_VERSION_IDE_EMULATION
5016 && SSMR3HandleRevision(pSSM) >= 79045
5017 && SSMR3HandleRevision(pSSM) < 79201)
5018 uVersion++;
5019
5020 /*
5021 * Check whether we have to resort to the legacy port reset method to
5022 * prevent older BIOS versions from failing after a reset.
5023 */
5024 if (uVersion <= AHCI_SAVED_STATE_VERSION_PRE_PORT_RESET_CHANGES)
5025 pThis->fLegacyPortResetMethod = true;
5026
5027 /* Verify config. */
5028 if (uVersion > AHCI_SAVED_STATE_VERSION_VBOX_30)
5029 {
5030 rc = SSMR3GetU32(pSSM, &u32);
5031 AssertRCReturn(rc, rc);
5032 if (u32 != pThis->cPortsImpl)
5033 {
5034 LogRel(("AHCI: Config mismatch: cPortsImpl - saved=%u config=%u\n", u32, pThis->cPortsImpl));
5035 if ( u32 < pThis->cPortsImpl
5036 || u32 > AHCI_MAX_NR_PORTS_IMPL)
5037 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: cPortsImpl - saved=%u config=%u"),
5038 u32, pThis->cPortsImpl);
5039 }
5040
5041 for (uint32_t i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
5042 {
5043 bool fInUse;
5044 rc = SSMR3GetBool(pSSM, &fInUse);
5045 AssertRCReturn(rc, rc);
5046 if (fInUse != (pThis->ahciPort[i].pDrvBase != NULL))
5047 return SSMR3SetCfgError(pSSM, RT_SRC_POS,
5048 N_("The %s VM is missing a device on port %u. Please make sure the source and target VMs have compatible storage configurations"),
5049 fInUse ? "target" : "source", i );
5050
5051 if (uVersion > AHCI_SAVED_STATE_VERSION_PRE_HOTPLUG_FLAG)
5052 {
5053 bool fHotpluggable;
5054 rc = SSMR3GetBool(pSSM, &fHotpluggable);
5055 AssertRCReturn(rc, rc);
5056 if (fHotpluggable != pThis->ahciPort[i].fHotpluggable)
5057 return SSMR3SetCfgError(pSSM, RT_SRC_POS,
5058 N_("AHCI: Port %u config mismatch: Hotplug flag - saved=%RTbool config=%RTbool\n"),
5059 i, fHotpluggable, pThis->ahciPort[i].fHotpluggable);
5060 }
5061 else
5062 Assert(pThis->ahciPort[i].fHotpluggable);
5063
5064 char szSerialNumber[AHCI_SERIAL_NUMBER_LENGTH+1];
5065 rc = SSMR3GetStrZ(pSSM, szSerialNumber, sizeof(szSerialNumber));
5066 AssertRCReturn(rc, rc);
5067 if (strcmp(szSerialNumber, pThis->ahciPort[i].szSerialNumber))
5068 LogRel(("AHCI: Port %u config mismatch: Serial number - saved='%s' config='%s'\n",
5069 i, szSerialNumber, pThis->ahciPort[i].szSerialNumber));
5070
5071 char szFirmwareRevision[AHCI_FIRMWARE_REVISION_LENGTH+1];
5072 rc = SSMR3GetStrZ(pSSM, szFirmwareRevision, sizeof(szFirmwareRevision));
5073 AssertRCReturn(rc, rc);
5074 if (strcmp(szFirmwareRevision, pThis->ahciPort[i].szFirmwareRevision))
5075 LogRel(("AHCI: Port %u config mismatch: Firmware revision - saved='%s' config='%s'\n",
5076 i, szFirmwareRevision, pThis->ahciPort[i].szFirmwareRevision));
5077
5078 char szModelNumber[AHCI_MODEL_NUMBER_LENGTH+1];
5079 rc = SSMR3GetStrZ(pSSM, szModelNumber, sizeof(szModelNumber));
5080 AssertRCReturn(rc, rc);
5081 if (strcmp(szModelNumber, pThis->ahciPort[i].szModelNumber))
5082 LogRel(("AHCI: Port %u config mismatch: Model number - saved='%s' config='%s'\n",
5083 i, szModelNumber, pThis->ahciPort[i].szModelNumber));
5084 }
5085
5086 static const char *s_apszIdeEmuPortNames[4] = { "PrimaryMaster", "PrimarySlave", "SecondaryMaster", "SecondarySlave" };
5087 for (uint32_t i = 0; i < RT_ELEMENTS(s_apszIdeEmuPortNames); i++)
5088 {
5089 uint32_t iPort;
5090 rc = CFGMR3QueryU32Def(pDevIns->pCfg, s_apszIdeEmuPortNames[i], &iPort, i);
5091 AssertRCReturn(rc, rc);
5092
5093 uint32_t iPortSaved;
5094 rc = SSMR3GetU32(pSSM, &iPortSaved);
5095 AssertRCReturn(rc, rc);
5096
5097 if (iPortSaved != iPort)
5098 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("IDE %s config mismatch: saved=%u config=%u"),
5099 s_apszIdeEmuPortNames[i], iPortSaved, iPort);
5100 }
5101 }
5102
5103 if (uPass == SSM_PASS_FINAL)
5104 {
5105 /* Restore data. */
5106
5107 /* The main device structure. */
5108 SSMR3GetU32(pSSM, &pThis->regHbaCap);
5109 SSMR3GetU32(pSSM, &pThis->regHbaCtrl);
5110 SSMR3GetU32(pSSM, &pThis->regHbaIs);
5111 SSMR3GetU32(pSSM, &pThis->regHbaPi);
5112 SSMR3GetU32(pSSM, &pThis->regHbaVs);
5113 SSMR3GetU32(pSSM, &pThis->regHbaCccCtl);
5114 SSMR3GetU32(pSSM, &pThis->regHbaCccPorts);
5115 SSMR3GetU8(pSSM, &pThis->uCccPortNr);
5116 SSMR3GetU64(pSSM, &pThis->uCccTimeout);
5117 SSMR3GetU32(pSSM, &pThis->uCccNr);
5118 SSMR3GetU32(pSSM, &pThis->uCccCurrentNr);
5119
5120 SSMR3GetU32(pSSM, (uint32_t *)&pThis->u32PortsInterrupted);
5121 SSMR3GetBool(pSSM, &pThis->fReset);
5122 SSMR3GetBool(pSSM, &pThis->f64BitAddr);
5123 SSMR3GetBool(pSSM, &pThis->fR0Enabled);
5124 SSMR3GetBool(pSSM, &pThis->fGCEnabled);
5125 if (uVersion > AHCI_SAVED_STATE_VERSION_PRE_PORT_RESET_CHANGES)
5126 SSMR3GetBool(pSSM, &pThis->fLegacyPortResetMethod);
5127
5128 /* Now every port. */
5129 for (uint32_t i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
5130 {
5131 PAHCIPort pAhciPort = &pThis->ahciPort[i];
5132
5133 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regCLB);
5134 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regCLBU);
5135 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regFB);
5136 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regFBU);
5137 SSMR3GetGCPhys(pSSM, (RTGCPHYS *)&pThis->ahciPort[i].GCPhysAddrClb);
5138 SSMR3GetGCPhys(pSSM, (RTGCPHYS *)&pThis->ahciPort[i].GCPhysAddrFb);
5139 SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].regIS);
5140 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regIE);
5141 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regCMD);
5142 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regTFD);
5143 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regSIG);
5144 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regSSTS);
5145 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regSCTL);
5146 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regSERR);
5147 SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].regSACT);
5148 SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].regCI);
5149 SSMR3GetU32(pSSM, &pThis->ahciPort[i].PCHSGeometry.cCylinders);
5150 SSMR3GetU32(pSSM, &pThis->ahciPort[i].PCHSGeometry.cHeads);
5151 SSMR3GetU32(pSSM, &pThis->ahciPort[i].PCHSGeometry.cSectors);
5152 SSMR3GetU64(pSSM, &pThis->ahciPort[i].cTotalSectors);
5153 SSMR3GetU32(pSSM, &pThis->ahciPort[i].cMultSectors);
5154 SSMR3GetU8(pSSM, &pThis->ahciPort[i].uATATransferMode);
5155 SSMR3GetBool(pSSM, &pThis->ahciPort[i].fResetDevice);
5156
5157 if (uVersion <= AHCI_SAVED_STATE_VERSION_VBOX_30)
5158 SSMR3Skip(pSSM, AHCI_NR_COMMAND_SLOTS * sizeof(uint8_t)); /* no active data here */
5159
5160 if (uVersion < AHCI_SAVED_STATE_VERSION_IDE_EMULATION)
5161 {
5162 /* The old positions in the FIFO, not required. */
5163 SSMR3Skip(pSSM, 2*sizeof(uint8_t));
5164 }
5165 SSMR3GetBool(pSSM, &pThis->ahciPort[i].fPoweredOn);
5166 SSMR3GetBool(pSSM, &pThis->ahciPort[i].fSpunUp);
5167 SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].u32TasksFinished);
5168 SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].u32QueuedTasksFinished);
5169
5170 if (uVersion >= AHCI_SAVED_STATE_VERSION_IDE_EMULATION)
5171 SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].u32CurrentCommandSlot);
5172
5173 if (uVersion > AHCI_SAVED_STATE_VERSION_PRE_ATAPI)
5174 {
5175 SSMR3GetBool(pSSM, &pThis->ahciPort[i].fATAPI);
5176 SSMR3GetMem(pSSM, pThis->ahciPort[i].abATAPISense, sizeof(pThis->ahciPort[i].abATAPISense));
5177 if (uVersion <= AHCI_SAVED_STATE_VERSION_PRE_ATAPI_REMOVE)
5178 {
5179 SSMR3Skip(pSSM, 1); /* cNotifiedMediaChange. */
5180 SSMR3Skip(pSSM, 4); /* MediaEventStatus */
5181 }
5182 }
5183 else if (pThis->ahciPort[i].fATAPI)
5184 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: atapi - saved=false config=true"));
5185
5186 /* Check if we have tasks pending. */
5187 uint32_t fTasksOutstanding = pAhciPort->regCI & ~pAhciPort->u32TasksFinished;
5188 uint32_t fQueuedTasksOutstanding = pAhciPort->regSACT & ~pAhciPort->u32QueuedTasksFinished;
5189
5190 pAhciPort->u32TasksNew = fTasksOutstanding | fQueuedTasksOutstanding;
5191
5192 if (pAhciPort->u32TasksNew)
5193 {
5194 /*
5195 * There are tasks pending. The VM was saved after a task failed
5196 * because of non-fatal error. Set the redo flag.
5197 */
5198 pAhciPort->fRedo = true;
5199 }
5200 }
5201
5202 if (uVersion <= AHCI_SAVED_STATE_VERSION_IDE_EMULATION)
5203 {
5204 for (uint32_t i = 0; i < 2; i++)
5205 {
5206 rc = ahciR3LoadLegacyEmulationState(pSSM);
5207 if(RT_FAILURE(rc))
5208 return rc;
5209 }
5210 }
5211
5212 rc = SSMR3GetU32(pSSM, &u32);
5213 if (RT_FAILURE(rc))
5214 return rc;
5215 AssertMsgReturn(u32 == UINT32_MAX, ("%#x\n", u32), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5216 }
5217
5218 return VINF_SUCCESS;
5219}
5220
5221/* -=-=-=-=- device PDM interface -=-=-=-=- */
5222
5223static DECLCALLBACK(void) ahciR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
5224{
5225 uint32_t i;
5226 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
5227
5228 pAhci->pDevInsRC += offDelta;
5229 pAhci->pHbaCccTimerRC = TMTimerRCPtr(pAhci->pHbaCccTimerR3);
5230 pAhci->pNotifierQueueRC = PDMQueueRCPtr(pAhci->pNotifierQueueR3);
5231
5232 /* Relocate every port. */
5233 for (i = 0; i < RT_ELEMENTS(pAhci->ahciPort); i++)
5234 {
5235 PAHCIPort pAhciPort = &pAhci->ahciPort[i];
5236 pAhciPort->pAhciRC += offDelta;
5237 pAhciPort->pDevInsRC += offDelta;
5238 }
5239}
5240
5241/**
5242 * Configure the attached device for a port.
5243 *
5244 * Used by ahciR3Construct and ahciR3Attach.
5245 *
5246 * @returns VBox status code
5247 * @param pDevIns The device instance data.
5248 * @param pAhciPort The port for which the device is to be configured.
5249 */
5250static int ahciR3ConfigureLUN(PPDMDEVINS pDevIns, PAHCIPort pAhciPort)
5251{
5252 /* Query the media interface. */
5253 pAhciPort->pDrvMedia = PDMIBASE_QUERY_INTERFACE(pAhciPort->pDrvBase, PDMIMEDIA);
5254 AssertMsgReturn(VALID_PTR(pAhciPort->pDrvMedia),
5255 ("AHCI configuration error: LUN#%d misses the basic media interface!\n", pAhciPort->iLUN),
5256 VERR_PDM_MISSING_INTERFACE);
5257
5258 /* Get the extended media interface. */
5259 pAhciPort->pDrvMediaEx = PDMIBASE_QUERY_INTERFACE(pAhciPort->pDrvBase, PDMIMEDIAEX);
5260 AssertMsgReturn(VALID_PTR(pAhciPort->pDrvMediaEx),
5261 ("AHCI configuration error: LUN#%d misses the extended media interface!\n", pAhciPort->iLUN),
5262 VERR_PDM_MISSING_INTERFACE);
5263
5264 /*
5265 * Validate type.
5266 */
5267 PDMMEDIATYPE enmType = pAhciPort->pDrvMedia->pfnGetType(pAhciPort->pDrvMedia);
5268 AssertMsgReturn(enmType == PDMMEDIATYPE_HARD_DISK || enmType == PDMMEDIATYPE_CDROM || enmType == PDMMEDIATYPE_DVD,
5269 ("AHCI configuration error: LUN#%d isn't a disk or cd/dvd. enmType=%u\n", pAhciPort->iLUN, enmType),
5270 VERR_PDM_UNSUPPORTED_BLOCK_TYPE);
5271
5272 int rc = pAhciPort->pDrvMediaEx->pfnIoReqAllocSizeSet(pAhciPort->pDrvMediaEx, sizeof(AHCIREQ));
5273 if (RT_FAILURE(rc))
5274 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
5275 N_("AHCI configuration error: LUN#%u: Failed to set I/O request size!"),
5276 pAhciPort->iLUN);
5277
5278 uint32_t fFeatures = 0;
5279 rc = pAhciPort->pDrvMediaEx->pfnQueryFeatures(pAhciPort->pDrvMediaEx, &fFeatures);
5280 if (RT_FAILURE(rc))
5281 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
5282 N_("AHCI configuration error: LUN#%u: Failed to query features of device"),
5283 pAhciPort->iLUN);
5284
5285 if (fFeatures & PDMIMEDIAEX_FEATURE_F_DISCARD)
5286 pAhciPort->fTrimEnabled = true;
5287
5288 pAhciPort->fATAPI = (enmType == PDMMEDIATYPE_CDROM || enmType == PDMMEDIATYPE_DVD)
5289 && RT_BOOL(fFeatures & PDMIMEDIAEX_FEATURE_F_RAWSCSICMD);
5290 if (pAhciPort->fATAPI)
5291 {
5292 pAhciPort->PCHSGeometry.cCylinders = 0;
5293 pAhciPort->PCHSGeometry.cHeads = 0;
5294 pAhciPort->PCHSGeometry.cSectors = 0;
5295 LogRel(("AHCI: LUN#%d: CD/DVD\n", pAhciPort->iLUN));
5296 }
5297 else
5298 {
5299 pAhciPort->cbSector = pAhciPort->pDrvMedia->pfnGetSectorSize(pAhciPort->pDrvMedia);
5300 pAhciPort->cTotalSectors = pAhciPort->pDrvMedia->pfnGetSize(pAhciPort->pDrvMedia) / pAhciPort->cbSector;
5301 rc = pAhciPort->pDrvMedia->pfnBiosGetPCHSGeometry(pAhciPort->pDrvMedia, &pAhciPort->PCHSGeometry);
5302 if (rc == VERR_PDM_MEDIA_NOT_MOUNTED)
5303 {
5304 pAhciPort->PCHSGeometry.cCylinders = 0;
5305 pAhciPort->PCHSGeometry.cHeads = 16; /*??*/
5306 pAhciPort->PCHSGeometry.cSectors = 63; /*??*/
5307 }
5308 else if (rc == VERR_PDM_GEOMETRY_NOT_SET)
5309 {
5310 pAhciPort->PCHSGeometry.cCylinders = 0; /* autodetect marker */
5311 rc = VINF_SUCCESS;
5312 }
5313 AssertRC(rc);
5314
5315 if ( pAhciPort->PCHSGeometry.cCylinders == 0
5316 || pAhciPort->PCHSGeometry.cHeads == 0
5317 || pAhciPort->PCHSGeometry.cSectors == 0)
5318 {
5319 uint64_t cCylinders = pAhciPort->cTotalSectors / (16 * 63);
5320 pAhciPort->PCHSGeometry.cCylinders = RT_MAX(RT_MIN(cCylinders, 16383), 1);
5321 pAhciPort->PCHSGeometry.cHeads = 16;
5322 pAhciPort->PCHSGeometry.cSectors = 63;
5323 /* Set the disk geometry information. Ignore errors. */
5324 pAhciPort->pDrvMedia->pfnBiosSetPCHSGeometry(pAhciPort->pDrvMedia, &pAhciPort->PCHSGeometry);
5325 rc = VINF_SUCCESS;
5326 }
5327 LogRel(("AHCI: LUN#%d: disk, PCHS=%u/%u/%u, total number of sectors %Ld\n",
5328 pAhciPort->iLUN, pAhciPort->PCHSGeometry.cCylinders,
5329 pAhciPort->PCHSGeometry.cHeads, pAhciPort->PCHSGeometry.cSectors,
5330 pAhciPort->cTotalSectors));
5331 if (pAhciPort->fTrimEnabled)
5332 LogRel(("AHCI: LUN#%d: Enabled TRIM support\n", pAhciPort->iLUN));
5333 }
5334 return rc;
5335}
5336
5337/**
5338 * Callback employed by ahciR3Suspend and ahciR3PowerOff.
5339 *
5340 * @returns true if we've quiesced, false if we're still working.
5341 * @param pDevIns The device instance.
5342 */
5343static DECLCALLBACK(bool) ahciR3IsAsyncSuspendOrPowerOffDone(PPDMDEVINS pDevIns)
5344{
5345 if (!ahciR3AllAsyncIOIsFinished(pDevIns))
5346 return false;
5347
5348 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
5349 ASMAtomicWriteBool(&pThis->fSignalIdle, false);
5350 return true;
5351}
5352
5353/**
5354 * Common worker for ahciR3Suspend and ahciR3PowerOff.
5355 */
5356static void ahciR3SuspendOrPowerOff(PPDMDEVINS pDevIns)
5357{
5358 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
5359
5360 ASMAtomicWriteBool(&pThis->fSignalIdle, true);
5361 if (!ahciR3AllAsyncIOIsFinished(pDevIns))
5362 PDMDevHlpSetAsyncNotification(pDevIns, ahciR3IsAsyncSuspendOrPowerOffDone);
5363 else
5364 ASMAtomicWriteBool(&pThis->fSignalIdle, false);
5365}
5366
5367/**
5368 * Suspend notification.
5369 *
5370 * @param pDevIns The device instance data.
5371 */
5372static DECLCALLBACK(void) ahciR3Suspend(PPDMDEVINS pDevIns)
5373{
5374 Log(("ahciR3Suspend\n"));
5375 ahciR3SuspendOrPowerOff(pDevIns);
5376}
5377
5378/**
5379 * Resume notification.
5380 *
5381 * @param pDevIns The device instance data.
5382 */
5383static DECLCALLBACK(void) ahciR3Resume(PPDMDEVINS pDevIns)
5384{
5385 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
5386
5387 /*
5388 * Check if one of the ports has pending tasks.
5389 * Queue a notification item again in this case.
5390 */
5391 for (unsigned i = 0; i < RT_ELEMENTS(pAhci->ahciPort); i++)
5392 {
5393 PAHCIPort pAhciPort = &pAhci->ahciPort[i];
5394
5395 if (pAhciPort->u32TasksRedo)
5396 {
5397 PDEVPORTNOTIFIERQUEUEITEM pItem = (PDEVPORTNOTIFIERQUEUEITEM)PDMQueueAlloc(pAhci->CTX_SUFF(pNotifierQueue));
5398 AssertMsg(pItem, ("Allocating item for queue failed\n"));
5399
5400 pAhciPort->u32TasksNew |= pAhciPort->u32TasksRedo;
5401 pAhciPort->u32TasksRedo = 0;
5402
5403 Assert(pAhciPort->fRedo);
5404 pAhciPort->fRedo = false;
5405
5406 pItem->iPort = pAhci->ahciPort[i].iLUN;
5407 PDMQueueInsert(pAhci->CTX_SUFF(pNotifierQueue), (PPDMQUEUEITEMCORE)pItem);
5408 }
5409 }
5410
5411 Log(("%s:\n", __FUNCTION__));
5412}
5413
5414/**
5415 * Initializes the VPD data of a attached device.
5416 *
5417 * @returns VBox status code.
5418 * @param pDevIns The device instance.
5419 * @param pAhciPort The attached device.
5420 * @param pszName Name of the port to get the CFGM node.
5421 */
5422static int ahciR3VpdInit(PPDMDEVINS pDevIns, PAHCIPort pAhciPort, const char *pszName)
5423{
5424
5425 /* Generate a default serial number. */
5426 char szSerial[AHCI_SERIAL_NUMBER_LENGTH+1];
5427 RTUUID Uuid;
5428
5429 int rc = VINF_SUCCESS;
5430 if (pAhciPort->pDrvMedia)
5431 rc = pAhciPort->pDrvMedia->pfnGetUuid(pAhciPort->pDrvMedia, &Uuid);
5432 else
5433 RTUuidClear(&Uuid);
5434
5435 if (RT_FAILURE(rc) || RTUuidIsNull(&Uuid))
5436 {
5437 /* Generate a predictable serial for drives which don't have a UUID. */
5438 RTStrPrintf(szSerial, sizeof(szSerial), "VB%x-1a2b3c4d",
5439 pAhciPort->iLUN);
5440 }
5441 else
5442 RTStrPrintf(szSerial, sizeof(szSerial), "VB%08x-%08x", Uuid.au32[0], Uuid.au32[3]);
5443
5444 /* Get user config if present using defaults otherwise. */
5445 PCFGMNODE pCfgNode = CFGMR3GetChild(pDevIns->pCfg, pszName);
5446 rc = CFGMR3QueryStringDef(pCfgNode, "SerialNumber", pAhciPort->szSerialNumber, sizeof(pAhciPort->szSerialNumber),
5447 szSerial);
5448 if (RT_FAILURE(rc))
5449 {
5450 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
5451 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
5452 N_("AHCI configuration error: \"SerialNumber\" is longer than 20 bytes"));
5453 return PDMDEV_SET_ERROR(pDevIns, rc,
5454 N_("AHCI configuration error: failed to read \"SerialNumber\" as string"));
5455 }
5456
5457 rc = CFGMR3QueryStringDef(pCfgNode, "FirmwareRevision", pAhciPort->szFirmwareRevision, sizeof(pAhciPort->szFirmwareRevision),
5458 "1.0");
5459 if (RT_FAILURE(rc))
5460 {
5461 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
5462 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
5463 N_("AHCI configuration error: \"FirmwareRevision\" is longer than 8 bytes"));
5464 return PDMDEV_SET_ERROR(pDevIns, rc,
5465 N_("AHCI configuration error: failed to read \"FirmwareRevision\" as string"));
5466 }
5467
5468 rc = CFGMR3QueryStringDef(pCfgNode, "ModelNumber", pAhciPort->szModelNumber, sizeof(pAhciPort->szModelNumber),
5469 pAhciPort->fATAPI ? "VBOX CD-ROM" : "VBOX HARDDISK");
5470 if (RT_FAILURE(rc))
5471 {
5472 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
5473 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
5474 N_("AHCI configuration error: \"ModelNumber\" is longer than 40 bytes"));
5475 return PDMDEV_SET_ERROR(pDevIns, rc,
5476 N_("AHCI configuration error: failed to read \"ModelNumber\" as string"));
5477 }
5478
5479 rc = CFGMR3QueryU8Def(pCfgNode, "LogicalSectorsPerPhysical", &pAhciPort->cLogSectorsPerPhysicalExp, 0);
5480 if (RT_FAILURE(rc))
5481 return PDMDEV_SET_ERROR(pDevIns, rc,
5482 N_("AHCI configuration error: failed to read \"LogicalSectorsPerPhysical\" as integer"));
5483 if (pAhciPort->cLogSectorsPerPhysicalExp >= 16)
5484 return PDMDEV_SET_ERROR(pDevIns, rc,
5485 N_("AHCI configuration error: \"LogicalSectorsPerPhysical\" must be between 0 and 15"));
5486
5487 return rc;
5488}
5489
5490
5491/**
5492 * Detach notification.
5493 *
5494 * One harddisk at one port has been unplugged.
5495 * The VM is suspended at this point.
5496 *
5497 * @param pDevIns The device instance.
5498 * @param iLUN The logical unit which is being detached.
5499 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5500 */
5501static DECLCALLBACK(void) ahciR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
5502{
5503 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
5504 PAHCIPort pAhciPort = &pAhci->ahciPort[iLUN];
5505 int rc = VINF_SUCCESS;
5506
5507 Log(("%s:\n", __FUNCTION__));
5508
5509 AssertMsg(iLUN < pAhci->cPortsImpl, ("iLUN=%u", iLUN));
5510 AssertMsgReturnVoid( pAhciPort->fHotpluggable
5511 || (fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
5512 ("AHCI: Port %d is not marked hotpluggable\n", pAhciPort->iLUN));
5513
5514
5515 if (pAhciPort->pAsyncIOThread)
5516 {
5517 int rcThread;
5518 /* Destroy the thread. */
5519 rc = PDMR3ThreadDestroy(pAhciPort->pAsyncIOThread, &rcThread);
5520 if (RT_FAILURE(rc) || RT_FAILURE(rcThread))
5521 AssertMsgFailed(("%s Failed to destroy async IO thread rc=%Rrc rcThread=%Rrc\n", __FUNCTION__, rc, rcThread));
5522
5523 pAhciPort->pAsyncIOThread = NULL;
5524 pAhciPort->fWrkThreadSleeping = true;
5525 }
5526
5527 if (!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG))
5528 {
5529 /*
5530 * Inform the guest about the removed device.
5531 */
5532 pAhciPort->regSSTS = 0;
5533 pAhciPort->regSIG = 0;
5534 /*
5535 * Clear CR bit too to prevent submission of new commands when CI is written
5536 * (AHCI Spec 1.2: 7.4 Interaction of the Command List and Port Change Status).
5537 */
5538 ASMAtomicAndU32(&pAhciPort->regCMD, ~(AHCI_PORT_CMD_CPS | AHCI_PORT_CMD_CR));
5539 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_CPDS | AHCI_PORT_IS_PRCS | AHCI_PORT_IS_PCS);
5540 ASMAtomicOrU32(&pAhciPort->regSERR, AHCI_PORT_SERR_X | AHCI_PORT_SERR_N);
5541 if ( (pAhciPort->regIE & AHCI_PORT_IE_CPDE)
5542 || (pAhciPort->regIE & AHCI_PORT_IE_PCE)
5543 || (pAhciPort->regIE & AHCI_PORT_IE_PRCE))
5544 ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN, VERR_IGNORED);
5545 }
5546
5547 /*
5548 * Zero some important members.
5549 */
5550 pAhciPort->pDrvBase = NULL;
5551 pAhciPort->pDrvMedia = NULL;
5552 pAhciPort->pDrvMediaEx = NULL;
5553}
5554
5555/**
5556 * Attach command.
5557 *
5558 * This is called when we change block driver for one port.
5559 * The VM is suspended at this point.
5560 *
5561 * @returns VBox status code.
5562 * @param pDevIns The device instance.
5563 * @param iLUN The logical unit which is being detached.
5564 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5565 */
5566static DECLCALLBACK(int) ahciR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
5567{
5568 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
5569 PAHCIPort pAhciPort = &pThis->ahciPort[iLUN];
5570 int rc;
5571
5572 Log(("%s:\n", __FUNCTION__));
5573
5574 /* the usual paranoia */
5575 AssertMsg(iLUN < pThis->cPortsImpl, ("iLUN=%u", iLUN));
5576 AssertRelease(!pAhciPort->pDrvBase);
5577 AssertRelease(!pAhciPort->pDrvMedia);
5578 AssertRelease(!pAhciPort->pDrvMediaEx);
5579 Assert(pAhciPort->iLUN == iLUN);
5580
5581 AssertMsgReturn( pAhciPort->fHotpluggable
5582 || (fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
5583 ("AHCI: Port %d is not marked hotpluggable\n", pAhciPort->iLUN),
5584 VERR_INVALID_PARAMETER);
5585
5586 /*
5587 * Try attach the block device and get the interfaces,
5588 * required as well as optional.
5589 */
5590 rc = PDMDevHlpDriverAttach(pDevIns, pAhciPort->iLUN, &pAhciPort->IBase, &pAhciPort->pDrvBase, NULL);
5591 if (RT_SUCCESS(rc))
5592 rc = ahciR3ConfigureLUN(pDevIns, pAhciPort);
5593 else
5594 AssertMsgFailed(("Failed to attach LUN#%d. rc=%Rrc\n", pAhciPort->iLUN, rc));
5595
5596 if (RT_FAILURE(rc))
5597 {
5598 pAhciPort->pDrvBase = NULL;
5599 pAhciPort->pDrvMedia = NULL;
5600 }
5601 else
5602 {
5603 char szName[24];
5604 RTStrPrintf(szName, sizeof(szName), "Port%d", iLUN);
5605
5606 rc = SUPSemEventCreate(pThis->pSupDrvSession, &pAhciPort->hEvtProcess);
5607 if (RT_FAILURE(rc))
5608 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
5609 N_("AHCI: Failed to create SUP event semaphore"));
5610
5611 /* Create the async IO thread. */
5612 rc = PDMDevHlpThreadCreate(pDevIns, &pAhciPort->pAsyncIOThread, pAhciPort, ahciAsyncIOLoop, ahciAsyncIOLoopWakeUp, 0,
5613 RTTHREADTYPE_IO, szName);
5614 if (RT_FAILURE(rc))
5615 return rc;
5616
5617 /*
5618 * Init vendor product data.
5619 */
5620 if (RT_SUCCESS(rc))
5621 rc = ahciR3VpdInit(pDevIns, pAhciPort, szName);
5622
5623 /* Inform the guest about the added device in case of hotplugging. */
5624 if ( RT_SUCCESS(rc)
5625 && !(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG))
5626 {
5627 AssertMsgReturn(pAhciPort->fHotpluggable,
5628 ("AHCI: Port %d is not marked hotpluggable\n", pAhciPort->iLUN),
5629 VERR_NOT_SUPPORTED);
5630
5631 /*
5632 * Initialize registers
5633 */
5634 ASMAtomicOrU32(&pAhciPort->regCMD, AHCI_PORT_CMD_CPS);
5635 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_CPDS | AHCI_PORT_IS_PRCS | AHCI_PORT_IS_PCS);
5636 ASMAtomicOrU32(&pAhciPort->regSERR, AHCI_PORT_SERR_X | AHCI_PORT_SERR_N);
5637
5638 if (pAhciPort->fATAPI)
5639 pAhciPort->regSIG = AHCI_PORT_SIG_ATAPI;
5640 else
5641 pAhciPort->regSIG = AHCI_PORT_SIG_DISK;
5642 pAhciPort->regSSTS = (0x01 << 8) | /* Interface is active. */
5643 (0x02 << 4) | /* Generation 2 (3.0GBps) speed. */
5644 (0x03 << 0); /* Device detected and communication established. */
5645
5646 if ( (pAhciPort->regIE & AHCI_PORT_IE_CPDE)
5647 || (pAhciPort->regIE & AHCI_PORT_IE_PCE)
5648 || (pAhciPort->regIE & AHCI_PORT_IE_PRCE))
5649 ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN, VERR_IGNORED);
5650 }
5651
5652 }
5653
5654 return rc;
5655}
5656
5657/**
5658 * Common reset worker.
5659 *
5660 * @param pDevIns The device instance data.
5661 */
5662static int ahciR3ResetCommon(PPDMDEVINS pDevIns)
5663{
5664 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
5665
5666 ahciHBAReset(pAhci);
5667
5668 /* Hardware reset for the ports. */
5669 for (uint32_t i = 0; i < RT_ELEMENTS(pAhci->ahciPort); i++)
5670 ahciPortHwReset(&pAhci->ahciPort[i]);
5671 return VINF_SUCCESS;
5672}
5673
5674/**
5675 * Callback employed by ahciR3Reset.
5676 *
5677 * @returns true if we've quiesced, false if we're still working.
5678 * @param pDevIns The device instance.
5679 */
5680static DECLCALLBACK(bool) ahciR3IsAsyncResetDone(PPDMDEVINS pDevIns)
5681{
5682 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
5683
5684 if (!ahciR3AllAsyncIOIsFinished(pDevIns))
5685 return false;
5686 ASMAtomicWriteBool(&pThis->fSignalIdle, false);
5687
5688 ahciR3ResetCommon(pDevIns);
5689 return true;
5690}
5691
5692/**
5693 * Reset notification.
5694 *
5695 * @param pDevIns The device instance data.
5696 */
5697static DECLCALLBACK(void) ahciR3Reset(PPDMDEVINS pDevIns)
5698{
5699 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
5700
5701 ASMAtomicWriteBool(&pThis->fSignalIdle, true);
5702 if (!ahciR3AllAsyncIOIsFinished(pDevIns))
5703 PDMDevHlpSetAsyncNotification(pDevIns, ahciR3IsAsyncResetDone);
5704 else
5705 {
5706 ASMAtomicWriteBool(&pThis->fSignalIdle, false);
5707 ahciR3ResetCommon(pDevIns);
5708 }
5709}
5710
5711/**
5712 * Poweroff notification.
5713 *
5714 * @param pDevIns Pointer to the device instance
5715 */
5716static DECLCALLBACK(void) ahciR3PowerOff(PPDMDEVINS pDevIns)
5717{
5718 Log(("achiR3PowerOff\n"));
5719 ahciR3SuspendOrPowerOff(pDevIns);
5720}
5721
5722/**
5723 * Destroy a driver instance.
5724 *
5725 * Most VM resources are freed by the VM. This callback is provided so that any non-VM
5726 * resources can be freed correctly.
5727 *
5728 * @param pDevIns The device instance data.
5729 */
5730static DECLCALLBACK(int) ahciR3Destruct(PPDMDEVINS pDevIns)
5731{
5732 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
5733 int rc = VINF_SUCCESS;
5734 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
5735
5736 /*
5737 * At this point the async I/O thread is suspended and will not enter
5738 * this module again. So, no coordination is needed here and PDM
5739 * will take care of terminating and cleaning up the thread.
5740 */
5741 if (PDMCritSectIsInitialized(&pThis->lock))
5742 {
5743 TMR3TimerDestroy(pThis->CTX_SUFF(pHbaCccTimer));
5744 pThis->CTX_SUFF(pHbaCccTimer) = NULL;
5745
5746 Log(("%s: Destruct every port\n", __FUNCTION__));
5747 for (unsigned iActPort = 0; iActPort < pThis->cPortsImpl; iActPort++)
5748 {
5749 PAHCIPort pAhciPort = &pThis->ahciPort[iActPort];
5750
5751 if (pAhciPort->hEvtProcess != NIL_SUPSEMEVENT)
5752 {
5753 SUPSemEventClose(pThis->pSupDrvSession, pAhciPort->hEvtProcess);
5754 pAhciPort->hEvtProcess = NIL_SUPSEMEVENT;
5755 }
5756 }
5757
5758 PDMR3CritSectDelete(&pThis->lock);
5759 }
5760
5761 return rc;
5762}
5763
5764/**
5765 * @interface_method_impl{PDMDEVREG,pfnConstruct}
5766 */
5767static DECLCALLBACK(int) ahciR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
5768{
5769 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
5770 PPDMIBASE pBase;
5771 int rc = VINF_SUCCESS;
5772 unsigned i = 0;
5773 bool fGCEnabled = false;
5774 bool fR0Enabled = false;
5775 uint32_t cbTotalBufferSize = 0;
5776 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5777
5778 LogFlowFunc(("pThis=%#p\n", pThis));
5779
5780 /*
5781 * Validate and read configuration.
5782 */
5783 if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0"
5784 "R0Enabled\0"
5785 "PrimaryMaster\0"
5786 "PrimarySlave\0"
5787 "SecondaryMaster\0"
5788 "SecondarySlave\0"
5789 "PortCount\0"
5790 "Bootable\0"
5791 "CmdSlotsAvail\0"))
5792 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
5793 N_("AHCI configuration error: unknown option specified"));
5794
5795 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
5796 if (RT_FAILURE(rc))
5797 return PDMDEV_SET_ERROR(pDevIns, rc,
5798 N_("AHCI configuration error: failed to read GCEnabled as boolean"));
5799 Log(("%s: fGCEnabled=%d\n", __FUNCTION__, fGCEnabled));
5800
5801 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
5802 if (RT_FAILURE(rc))
5803 return PDMDEV_SET_ERROR(pDevIns, rc,
5804 N_("AHCI configuration error: failed to read R0Enabled as boolean"));
5805 Log(("%s: fR0Enabled=%d\n", __FUNCTION__, fR0Enabled));
5806
5807 rc = CFGMR3QueryU32Def(pCfg, "PortCount", &pThis->cPortsImpl, AHCI_MAX_NR_PORTS_IMPL);
5808 if (RT_FAILURE(rc))
5809 return PDMDEV_SET_ERROR(pDevIns, rc,
5810 N_("AHCI configuration error: failed to read PortCount as integer"));
5811 Log(("%s: cPortsImpl=%u\n", __FUNCTION__, pThis->cPortsImpl));
5812 if (pThis->cPortsImpl > AHCI_MAX_NR_PORTS_IMPL)
5813 return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
5814 N_("AHCI configuration error: PortCount=%u should not exceed %u"),
5815 pThis->cPortsImpl, AHCI_MAX_NR_PORTS_IMPL);
5816 if (pThis->cPortsImpl < 1)
5817 return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
5818 N_("AHCI configuration error: PortCount=%u should be at least 1"),
5819 pThis->cPortsImpl);
5820
5821 rc = CFGMR3QueryBoolDef(pCfg, "Bootable", &pThis->fBootable, true);
5822 if (RT_FAILURE(rc))
5823 return PDMDEV_SET_ERROR(pDevIns, rc,
5824 N_("AHCI configuration error: failed to read Bootable as boolean"));
5825
5826 rc = CFGMR3QueryU32Def(pCfg, "CmdSlotsAvail", &pThis->cCmdSlotsAvail, AHCI_NR_COMMAND_SLOTS);
5827 if (RT_FAILURE(rc))
5828 return PDMDEV_SET_ERROR(pDevIns, rc,
5829 N_("AHCI configuration error: failed to read CmdSlotsAvail as integer"));
5830 Log(("%s: cCmdSlotsAvail=%u\n", __FUNCTION__, pThis->cCmdSlotsAvail));
5831 if (pThis->cCmdSlotsAvail > AHCI_NR_COMMAND_SLOTS)
5832 return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
5833 N_("AHCI configuration error: CmdSlotsAvail=%u should not exceed %u"),
5834 pThis->cPortsImpl, AHCI_NR_COMMAND_SLOTS);
5835 if (pThis->cCmdSlotsAvail < 1)
5836 return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
5837 N_("AHCI configuration error: CmdSlotsAvail=%u should be at least 1"),
5838 pThis->cCmdSlotsAvail);
5839
5840 /*
5841 * Initialize the instance data (everything touched by the destructor need
5842 * to be initialized here!).
5843 */
5844 pThis->fR0Enabled = fR0Enabled;
5845 pThis->fGCEnabled = fGCEnabled;
5846 pThis->pDevInsR3 = pDevIns;
5847 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
5848 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5849 pThis->pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
5850
5851 PCIDevSetVendorId (&pThis->dev, 0x8086); /* Intel */
5852 PCIDevSetDeviceId (&pThis->dev, 0x2829); /* ICH-8M */
5853 PCIDevSetCommand (&pThis->dev, 0x0000);
5854#ifdef VBOX_WITH_MSI_DEVICES
5855 PCIDevSetStatus (&pThis->dev, VBOX_PCI_STATUS_CAP_LIST);
5856 PCIDevSetCapabilityList(&pThis->dev, 0x80);
5857#else
5858 PCIDevSetCapabilityList(&pThis->dev, 0x70);
5859#endif
5860 PCIDevSetRevisionId (&pThis->dev, 0x02);
5861 PCIDevSetClassProg (&pThis->dev, 0x01);
5862 PCIDevSetClassSub (&pThis->dev, 0x06);
5863 PCIDevSetClassBase (&pThis->dev, 0x01);
5864 PCIDevSetBaseAddress (&pThis->dev, 5, false, false, false, 0x00000000);
5865
5866 PCIDevSetInterruptLine(&pThis->dev, 0x00);
5867 PCIDevSetInterruptPin (&pThis->dev, 0x01);
5868
5869 pThis->dev.config[0x70] = VBOX_PCI_CAP_ID_PM; /* Capability ID: PCI Power Management Interface */
5870 pThis->dev.config[0x71] = 0xa8; /* next */
5871 pThis->dev.config[0x72] = 0x03; /* version ? */
5872
5873 pThis->dev.config[0x90] = 0x40; /* AHCI mode. */
5874 pThis->dev.config[0x92] = 0x3f;
5875 pThis->dev.config[0x94] = 0x80;
5876 pThis->dev.config[0x95] = 0x01;
5877 pThis->dev.config[0x97] = 0x78;
5878
5879 pThis->dev.config[0xa8] = 0x12; /* SATACR capability */
5880 pThis->dev.config[0xa9] = 0x00; /* next */
5881 PCIDevSetWord(&pThis->dev, 0xaa, 0x0010); /* Revision */
5882 PCIDevSetDWord(&pThis->dev, 0xac, 0x00000028); /* SATA Capability Register 1 */
5883
5884 pThis->cThreadsActive = 0;
5885
5886 /* Initialize port members. */
5887 for (i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
5888 {
5889 PAHCIPort pAhciPort = &pThis->ahciPort[i];
5890 pAhciPort->pDevInsR3 = pDevIns;
5891 pAhciPort->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
5892 pAhciPort->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5893 pAhciPort->iLUN = i;
5894 pAhciPort->pAhciR3 = pThis;
5895 pAhciPort->pAhciR0 = PDMINS_2_DATA_R0PTR(pDevIns);
5896 pAhciPort->pAhciRC = PDMINS_2_DATA_RCPTR(pDevIns);
5897 pAhciPort->Led.u32Magic = PDMLED_MAGIC;
5898 pAhciPort->pDrvBase = NULL;
5899 pAhciPort->pAsyncIOThread = NULL;
5900 pAhciPort->hEvtProcess = NIL_SUPSEMEVENT;
5901 pAhciPort->fHotpluggable = true;
5902 }
5903
5904 /*
5905 * Init locks, using explicit locking where necessary.
5906 */
5907 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
5908 if (RT_FAILURE(rc))
5909 return rc;
5910
5911 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->lock, RT_SRC_POS, "AHCI#%u", iInstance);
5912 if (RT_FAILURE(rc))
5913 {
5914 Log(("%s: Failed to create critical section.\n", __FUNCTION__));
5915 return rc;
5916 }
5917
5918 /*
5919 * Register the PCI device, it's I/O regions.
5920 */
5921 rc = PDMDevHlpPCIRegister (pDevIns, &pThis->dev);
5922 if (RT_FAILURE(rc))
5923 return rc;
5924
5925#ifdef VBOX_WITH_MSI_DEVICES
5926 PDMMSIREG MsiReg;
5927 RT_ZERO(MsiReg);
5928 MsiReg.cMsiVectors = 1;
5929 MsiReg.iMsiCapOffset = 0x80;
5930 MsiReg.iMsiNextOffset = 0x70;
5931 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
5932 if (RT_FAILURE(rc))
5933 {
5934 PCIDevSetCapabilityList(&pThis->dev, 0x70);
5935 /* That's OK, we can work without MSI */
5936 }
5937#endif
5938
5939 /*
5940 * Solaris 10 U5 fails to map the AHCI register space when the sets (0..5) for the legacy
5941 * IDE registers are not available.
5942 * We set up "fake" entries in the PCI configuration register.
5943 * That means they are available but read and writes from/to them have no effect.
5944 * No guest should access them anyway because the controller is marked as AHCI in the Programming interface
5945 * and we don't have an option to change to IDE emulation (real hardware provides an option in the BIOS
5946 * to switch to it which also changes device Id and other things in the PCI configuration space).
5947 */
5948 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 8, PCI_ADDRESS_SPACE_IO, ahciR3LegacyFakeIORangeMap);
5949 if (RT_FAILURE(rc))
5950 return PDMDEV_SET_ERROR(pDevIns, rc,
5951 N_("AHCI cannot register PCI I/O region"));
5952
5953 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 1, 1, PCI_ADDRESS_SPACE_IO, ahciR3LegacyFakeIORangeMap);
5954 if (RT_FAILURE(rc))
5955 return PDMDEV_SET_ERROR(pDevIns, rc,
5956 N_("AHCI cannot register PCI I/O region"));
5957
5958 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 2, 8, PCI_ADDRESS_SPACE_IO, ahciR3LegacyFakeIORangeMap);
5959 if (RT_FAILURE(rc))
5960 return PDMDEV_SET_ERROR(pDevIns, rc,
5961 N_("AHCI cannot register PCI I/O region"));
5962
5963 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 3, 1, PCI_ADDRESS_SPACE_IO, ahciR3LegacyFakeIORangeMap);
5964 if (RT_FAILURE(rc))
5965 return PDMDEV_SET_ERROR(pDevIns, rc,
5966 N_("AHCI cannot register PCI I/O region"));
5967
5968 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 4, 0x10, PCI_ADDRESS_SPACE_IO, ahciR3IdxDataIORangeMap);
5969 if (RT_FAILURE(rc))
5970 return PDMDEV_SET_ERROR(pDevIns, rc,
5971 N_("AHCI cannot register PCI I/O region for BMDMA"));
5972
5973 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 5, 4352, PCI_ADDRESS_SPACE_MEM, ahciR3MMIOMap);
5974 if (RT_FAILURE(rc))
5975 return PDMDEV_SET_ERROR(pDevIns, rc,
5976 N_("AHCI cannot register PCI memory region for registers"));
5977
5978 /* Create the timer for command completion coalescing feature. */
5979 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, ahciCccTimer, pThis,
5980 TMTIMER_FLAGS_NO_CRIT_SECT, "AHCI CCC Timer", &pThis->pHbaCccTimerR3);
5981 if (RT_FAILURE(rc))
5982 {
5983 AssertMsgFailed(("pfnTMTimerCreate -> %Rrc\n", rc));
5984 return rc;
5985 }
5986 pThis->pHbaCccTimerR0 = TMTimerR0Ptr(pThis->pHbaCccTimerR3);
5987 pThis->pHbaCccTimerRC = TMTimerRCPtr(pThis->pHbaCccTimerR3);
5988
5989 /* Status LUN. */
5990 pThis->IBase.pfnQueryInterface = ahciR3Status_QueryInterface;
5991 pThis->ILeds.pfnQueryStatusLed = ahciR3Status_QueryStatusLed;
5992
5993 /*
5994 * Create the notification queue.
5995 *
5996 * We need 2 items for every port because of SMP races.
5997 */
5998 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(DEVPORTNOTIFIERQUEUEITEM), AHCI_MAX_NR_PORTS_IMPL * 2, 0,
5999 ahciNotifyQueueConsumer, true, "AHCI-Xmit", &pThis->pNotifierQueueR3);
6000 if (RT_FAILURE(rc))
6001 return rc;
6002 pThis->pNotifierQueueR0 = PDMQueueR0Ptr(pThis->pNotifierQueueR3);
6003 pThis->pNotifierQueueRC = PDMQueueRCPtr(pThis->pNotifierQueueR3);
6004
6005 /* Initialize static members on every port. */
6006 for (i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
6007 {
6008 PAHCIPort pAhciPort = &pThis->ahciPort[i];
6009
6010 PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatDMA, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
6011 "Number of DMA transfers.", "/Devices/SATA%d/Port%d/DMA", iInstance, i);
6012 PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatBytesRead, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_BYTES,
6013 "Amount of data read.", "/Devices/SATA%d/Port%d/ReadBytes", iInstance, i);
6014 PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatBytesWritten, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_BYTES,
6015 "Amount of data written.", "/Devices/SATA%d/Port%d/WrittenBytes", iInstance, i);
6016 PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatIORequestsPerSecond, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
6017 "Number of processed I/O requests per second.", "/Devices/SATA%d/Port%d/IORequestsPerSecond", iInstance, i);
6018#ifdef VBOX_WITH_STATISTICS
6019 PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatProfileProcessTime, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_NS_PER_CALL,
6020 "Amount of time to process one request.", "/Devices/SATA%d/Port%d/ProfileProcessTime", iInstance, i);
6021 PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatProfileReadWrite, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_NS_PER_CALL,
6022 "Amount of time for the read/write operation to complete.", "/Devices/SATA%d/Port%d/ProfileReadWrite", iInstance, i);
6023#endif
6024
6025 ahciPortHwReset(pAhciPort);
6026 }
6027
6028 /* Attach drivers to every available port. */
6029 for (i = 0; i < pThis->cPortsImpl; i++)
6030 {
6031 char szName[24];
6032 RTStrPrintf(szName, sizeof(szName), "Port%u", i);
6033
6034 PAHCIPort pAhciPort = &pThis->ahciPort[i];
6035 /*
6036 * Init interfaces.
6037 */
6038 pAhciPort->IBase.pfnQueryInterface = ahciR3PortQueryInterface;
6039 pAhciPort->IMediaExPort.pfnIoReqCompleteNotify = ahciR3IoReqCompleteNotify;
6040 pAhciPort->IMediaExPort.pfnIoReqCopyFromBuf = ahciR3IoReqCopyFromBuf;
6041 pAhciPort->IMediaExPort.pfnIoReqCopyToBuf = ahciR3IoReqCopyToBuf;
6042 pAhciPort->IMediaExPort.pfnIoReqQueryDiscardRanges = ahciR3IoReqQueryDiscardRanges;
6043 pAhciPort->IMediaExPort.pfnIoReqStateChanged = ahciR3IoReqStateChanged;
6044 pAhciPort->IMediaExPort.pfnMediumEjected = ahciR3MediumEjected;
6045 pAhciPort->IPort.pfnQueryDeviceLocation = ahciR3PortQueryDeviceLocation;
6046 pAhciPort->fWrkThreadSleeping = true;
6047
6048 /* Query per port configuration options if available. */
6049 PCFGMNODE pCfgPort = CFGMR3GetChild(pDevIns->pCfg, szName);
6050 if (pCfgPort)
6051 {
6052 rc = CFGMR3QueryBoolDef(pCfgPort, "Hotpluggable", &pAhciPort->fHotpluggable, true);
6053 if (RT_FAILURE(rc))
6054 return PDMDEV_SET_ERROR(pDevIns, rc,
6055 N_("AHCI configuration error: failed to read Hotpluggable as boolean"));
6056 }
6057
6058 /*
6059 * Attach the block driver
6060 */
6061 rc = PDMDevHlpDriverAttach(pDevIns, pAhciPort->iLUN, &pAhciPort->IBase, &pAhciPort->pDrvBase, szName);
6062 if (RT_SUCCESS(rc))
6063 {
6064 rc = ahciR3ConfigureLUN(pDevIns, pAhciPort);
6065 if (RT_FAILURE(rc))
6066 {
6067 Log(("%s: Failed to configure the %s.\n", __FUNCTION__, szName));
6068 return rc;
6069 }
6070
6071 /* Mark that a device is present on that port */
6072 if (i < 6)
6073 pThis->dev.config[0x93] |= (1 << i);
6074
6075 /*
6076 * Init vendor product data.
6077 */
6078 rc = ahciR3VpdInit(pDevIns, pAhciPort, szName);
6079 if (RT_FAILURE(rc))
6080 return rc;
6081
6082 rc = SUPSemEventCreate(pThis->pSupDrvSession, &pAhciPort->hEvtProcess);
6083 if (RT_FAILURE(rc))
6084 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
6085 N_("AHCI: Failed to create SUP event semaphore"));
6086
6087 rc = PDMDevHlpThreadCreate(pDevIns, &pAhciPort->pAsyncIOThread, pAhciPort, ahciAsyncIOLoop,
6088 ahciAsyncIOLoopWakeUp, 0, RTTHREADTYPE_IO, szName);
6089 if (RT_FAILURE(rc))
6090 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
6091 N_("AHCI: Failed to create worker thread %s"), szName);
6092 }
6093 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
6094 {
6095 pAhciPort->pDrvBase = NULL;
6096 rc = VINF_SUCCESS;
6097 LogRel(("AHCI: %s: No driver attached\n", szName));
6098 }
6099 else
6100 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
6101 N_("AHCI: Failed to attach drive to %s"), szName);
6102 }
6103
6104 /*
6105 * Attach status driver (optional).
6106 */
6107 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThis->IBase, &pBase, "Status Port");
6108 if (RT_SUCCESS(rc))
6109 {
6110 pThis->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
6111 pThis->pMediaNotify = PDMIBASE_QUERY_INTERFACE(pBase, PDMIMEDIANOTIFY);
6112 }
6113 else if (rc != VERR_PDM_NO_ATTACHED_DRIVER)
6114 {
6115 AssertMsgFailed(("Failed to attach to status driver. rc=%Rrc\n", rc));
6116 return PDMDEV_SET_ERROR(pDevIns, rc, N_("AHCI cannot attach to status driver"));
6117 }
6118 rc = PDMDevHlpSSMRegisterEx(pDevIns, AHCI_SAVED_STATE_VERSION, sizeof(*pThis) + cbTotalBufferSize, NULL,
6119 NULL, ahciR3LiveExec, NULL,
6120 ahciR3SavePrep, ahciR3SaveExec, NULL,
6121 ahciR3LoadPrep, ahciR3LoadExec, NULL);
6122 if (RT_FAILURE(rc))
6123 return rc;
6124
6125 /*
6126 * Register the info item.
6127 */
6128 char szTmp[128];
6129 RTStrPrintf(szTmp, sizeof(szTmp), "%s%d", pDevIns->pReg->szName, pDevIns->iInstance);
6130 PDMDevHlpDBGFInfoRegister(pDevIns, szTmp, "AHCI info", ahciR3Info);
6131
6132 return ahciR3ResetCommon(pDevIns);
6133}
6134
6135/**
6136 * The device registration structure.
6137 */
6138const PDMDEVREG g_DeviceAHCI =
6139{
6140 /* u32Version */
6141 PDM_DEVREG_VERSION,
6142 /* szName */
6143 "ahci",
6144 /* szRCMod */
6145 "VBoxDDRC.rc",
6146 /* szR0Mod */
6147 "VBoxDDR0.r0",
6148 /* pszDescription */
6149 "Intel AHCI controller.\n",
6150 /* fFlags */
6151 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0 |
6152 PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION | PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION |
6153 PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION,
6154 /* fClass */
6155 PDM_DEVREG_CLASS_STORAGE,
6156 /* cMaxInstances */
6157 ~0U,
6158 /* cbInstance */
6159 sizeof(AHCI),
6160 /* pfnConstruct */
6161 ahciR3Construct,
6162 /* pfnDestruct */
6163 ahciR3Destruct,
6164 /* pfnRelocate */
6165 ahciR3Relocate,
6166 /* pfnMemSetup */
6167 NULL,
6168 /* pfnPowerOn */
6169 NULL,
6170 /* pfnReset */
6171 ahciR3Reset,
6172 /* pfnSuspend */
6173 ahciR3Suspend,
6174 /* pfnResume */
6175 ahciR3Resume,
6176 /* pfnAttach */
6177 ahciR3Attach,
6178 /* pfnDetach */
6179 ahciR3Detach,
6180 /* pfnQueryInterface. */
6181 NULL,
6182 /* pfnInitComplete */
6183 NULL,
6184 /* pfnPowerOff */
6185 ahciR3PowerOff,
6186 /* pfnSoftReset */
6187 NULL,
6188 /* u32VersionEnd */
6189 PDM_DEVREG_VERSION
6190};
6191
6192#endif /* IN_RING3 */
6193#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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