VirtualBox

source: vbox/trunk/src/VBox/Devices/Storage/DevAHCI.cpp@ 74441

Last change on this file since 74441 was 73097, checked in by vboxsync, 6 years ago

*: Made RT_UOFFSETOF, RT_OFFSETOF, RT_UOFFSETOF_ADD and RT_OFFSETOF_ADD work like builtin_offsetof() and require compile time resolvable requests, adding RT_UOFFSETOF_DYN for the dynamic questions that can only be answered at runtime.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 237.3 KB
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1/* $Id: DevAHCI.cpp 73097 2018-07-12 21:06:33Z vboxsync $ */
2/** @file
3 * DevAHCI - AHCI controller device (disk and cdrom).
4 *
5 * Implements the AHCI standard 1.1
6 */
7
8/*
9 * Copyright (C) 2006-2017 Oracle Corporation
10 *
11 * This file is part of VirtualBox Open Source Edition (OSE), as
12 * available from http://www.virtualbox.org. This file is free software;
13 * you can redistribute it and/or modify it under the terms of the GNU
14 * General Public License (GPL) as published by the Free Software
15 * Foundation, in version 2 as it comes in the "COPYING" file of the
16 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18 */
19
20/** @page pg_dev_ahci AHCI - Advanced Host Controller Interface Emulation.
21 *
22 * This component implements an AHCI serial ATA controller. The device is split
23 * into two parts. The first part implements the register interface for the
24 * guest and the second one does the data transfer.
25 *
26 * The guest can access the controller in two ways. The first one is the native
27 * way implementing the registers described in the AHCI specification and is
28 * the preferred one. The second implements the I/O ports used for booting from
29 * the hard disk and for guests which don't have an AHCI SATA driver.
30 *
31 * The data is transfered using the extended media interface, asynchronously if
32 * it is supported by the driver below otherwise it weill be done synchronous.
33 * Either way a thread is used to process new requests from the guest.
34 */
35
36
37/*********************************************************************************************************************************
38* Header Files *
39*********************************************************************************************************************************/
40#define LOG_GROUP LOG_GROUP_DEV_AHCI
41#include <VBox/vmm/pdmdev.h>
42#include <VBox/vmm/pdmstorageifs.h>
43#include <VBox/vmm/pdmqueue.h>
44#include <VBox/vmm/pdmthread.h>
45#include <VBox/vmm/pdmcritsect.h>
46#include <VBox/sup.h>
47#include <VBox/scsi.h>
48#include <VBox/ata.h>
49#include <iprt/assert.h>
50#include <iprt/asm.h>
51#include <iprt/string.h>
52#include <iprt/list.h>
53#ifdef IN_RING3
54# include <iprt/param.h>
55# include <iprt/thread.h>
56# include <iprt/semaphore.h>
57# include <iprt/alloc.h>
58# include <iprt/uuid.h>
59# include <iprt/time.h>
60#endif
61#include "VBoxDD.h"
62
63#if defined(VBOX_WITH_DTRACE) \
64 && defined(IN_RING3) \
65 && !defined(VBOX_DEVICE_STRUCT_TESTCASE)
66# include "dtrace/VBoxDD.h"
67#else
68# define VBOXDD_AHCI_REQ_SUBMIT(a,b,c,d) do { } while (0)
69# define VBOXDD_AHCI_REQ_COMPLETED(a,b,c,d) do { } while (0)
70#endif
71
72/** Maximum number of ports available.
73 * Spec defines 32 but we have one allocated for command completion coalescing
74 * and another for a reserved future feature.
75 */
76#define AHCI_MAX_NR_PORTS_IMPL 30
77/** Maximum number of command slots available. */
78#define AHCI_NR_COMMAND_SLOTS 32
79
80/** The current saved state version. */
81#define AHCI_SAVED_STATE_VERSION 9
82/** The saved state version before the ATAPI emulation was removed and the generic SCSI driver was used. */
83#define AHCI_SAVED_STATE_VERSION_PRE_ATAPI_REMOVE 8
84/** The saved state version before changing the port reset logic in an incompatible way. */
85#define AHCI_SAVED_STATE_VERSION_PRE_PORT_RESET_CHANGES 7
86/** Saved state version before the per port hotplug port was added. */
87#define AHCI_SAVED_STATE_VERSION_PRE_HOTPLUG_FLAG 6
88/** Saved state version before legacy ATA emulation was dropped. */
89#define AHCI_SAVED_STATE_VERSION_IDE_EMULATION 5
90/** Saved state version before ATAPI support was added. */
91#define AHCI_SAVED_STATE_VERSION_PRE_ATAPI 3
92/** The saved state version use in VirtualBox 3.0 and earlier.
93 * This was before the config was added and ahciIOTasks was dropped. */
94#define AHCI_SAVED_STATE_VERSION_VBOX_30 2
95/* for Older ATA state Read handling */
96#define ATA_CTL_SAVED_STATE_VERSION 3
97#define ATA_CTL_SAVED_STATE_VERSION_WITHOUT_FULL_SENSE 1
98#define ATA_CTL_SAVED_STATE_VERSION_WITHOUT_EVENT_STATUS 2
99
100/** The maximum number of release log entries per device. */
101#define MAX_LOG_REL_ERRORS 1024
102
103/**
104 * Maximum number of sectors to transfer in a READ/WRITE MULTIPLE request.
105 * Set to 1 to disable multi-sector read support. According to the ATA
106 * specification this must be a power of 2 and it must fit in an 8 bit
107 * value. Thus the only valid values are 1, 2, 4, 8, 16, 32, 64 and 128.
108 */
109#define ATA_MAX_MULT_SECTORS 128
110
111/**
112 * Fastest PIO mode supported by the drive.
113 */
114#define ATA_PIO_MODE_MAX 4
115/**
116 * Fastest MDMA mode supported by the drive.
117 */
118#define ATA_MDMA_MODE_MAX 2
119/**
120 * Fastest UDMA mode supported by the drive.
121 */
122#define ATA_UDMA_MODE_MAX 6
123
124/**
125 * Length of the configurable VPD data (without termination)
126 */
127#define AHCI_SERIAL_NUMBER_LENGTH 20
128#define AHCI_FIRMWARE_REVISION_LENGTH 8
129#define AHCI_MODEL_NUMBER_LENGTH 40
130#define AHCI_ATAPI_INQUIRY_VENDOR_ID_LENGTH 8
131#define AHCI_ATAPI_INQUIRY_PRODUCT_ID_LENGTH 16
132#define AHCI_ATAPI_INQUIRY_REVISION_LENGTH 4
133
134/** ATAPI sense info size. */
135#define ATAPI_SENSE_SIZE 64
136
137/**
138 * Command Header.
139 */
140#pragma pack(1)
141typedef struct
142{
143 /** Description Information. */
144 uint32_t u32DescInf;
145 /** Command status. */
146 uint32_t u32PRDBC;
147 /** Command Table Base Address. */
148 uint32_t u32CmdTblAddr;
149 /** Command Table Base Address - upper 32-bits. */
150 uint32_t u32CmdTblAddrUp;
151 /** Reserved */
152 uint32_t u32Reserved[4];
153} CmdHdr;
154#pragma pack()
155AssertCompileSize(CmdHdr, 32);
156
157/* Defines for the command header. */
158#define AHCI_CMDHDR_PRDTL_MASK 0xffff0000
159#define AHCI_CMDHDR_PRDTL_ENTRIES(x) ((x & AHCI_CMDHDR_PRDTL_MASK) >> 16)
160#define AHCI_CMDHDR_C RT_BIT(10)
161#define AHCI_CMDHDR_B RT_BIT(9)
162#define AHCI_CMDHDR_R RT_BIT(8)
163#define AHCI_CMDHDR_P RT_BIT(7)
164#define AHCI_CMDHDR_W RT_BIT(6)
165#define AHCI_CMDHDR_A RT_BIT(5)
166#define AHCI_CMDHDR_CFL_MASK 0x1f
167
168#define AHCI_CMDHDR_PRDT_OFFSET 0x80
169#define AHCI_CMDHDR_ACMD_OFFSET 0x40
170
171/* Defines for the command FIS. */
172/* Defines that are used in the first double word. */
173#define AHCI_CMDFIS_TYPE 0 /* The first byte. */
174# define AHCI_CMDFIS_TYPE_H2D 0x27 /* Register - Host to Device FIS. */
175# define AHCI_CMDFIS_TYPE_H2D_SIZE 20 /* Five double words. */
176# define AHCI_CMDFIS_TYPE_D2H 0x34 /* Register - Device to Host FIS. */
177# define AHCI_CMDFIS_TYPE_D2H_SIZE 20 /* Five double words. */
178# define AHCI_CMDFIS_TYPE_SETDEVBITS 0xa1 /* Set Device Bits - Device to Host FIS. */
179# define AHCI_CMDFIS_TYPE_SETDEVBITS_SIZE 8 /* Two double words. */
180# define AHCI_CMDFIS_TYPE_DMAACTD2H 0x39 /* DMA Activate - Device to Host FIS. */
181# define AHCI_CMDFIS_TYPE_DMAACTD2H_SIZE 4 /* One double word. */
182# define AHCI_CMDFIS_TYPE_DMASETUP 0x41 /* DMA Setup - Bidirectional FIS. */
183# define AHCI_CMDFIS_TYPE_DMASETUP_SIZE 28 /* Seven double words. */
184# define AHCI_CMDFIS_TYPE_PIOSETUP 0x5f /* PIO Setup - Device to Host FIS. */
185# define AHCI_CMDFIS_TYPE_PIOSETUP_SIZE 20 /* Five double words. */
186# define AHCI_CMDFIS_TYPE_DATA 0x46 /* Data - Bidirectional FIS. */
187
188#define AHCI_CMDFIS_BITS 1 /* Interrupt and Update bit. */
189#define AHCI_CMDFIS_C RT_BIT(7) /* Host to device. */
190#define AHCI_CMDFIS_I RT_BIT(6) /* Device to Host. */
191#define AHCI_CMDFIS_D RT_BIT(5)
192
193#define AHCI_CMDFIS_CMD 2
194#define AHCI_CMDFIS_FET 3
195
196#define AHCI_CMDFIS_SECTN 4
197#define AHCI_CMDFIS_CYLL 5
198#define AHCI_CMDFIS_CYLH 6
199#define AHCI_CMDFIS_HEAD 7
200
201#define AHCI_CMDFIS_SECTNEXP 8
202#define AHCI_CMDFIS_CYLLEXP 9
203#define AHCI_CMDFIS_CYLHEXP 10
204#define AHCI_CMDFIS_FETEXP 11
205
206#define AHCI_CMDFIS_SECTC 12
207#define AHCI_CMDFIS_SECTCEXP 13
208#define AHCI_CMDFIS_CTL 15
209# define AHCI_CMDFIS_CTL_SRST RT_BIT(2) /* Reset device. */
210# define AHCI_CMDFIS_CTL_NIEN RT_BIT(1) /* Assert or clear interrupt. */
211
212/* For D2H FIS */
213#define AHCI_CMDFIS_STS 2
214#define AHCI_CMDFIS_ERR 3
215
216/** Pointer to a task state. */
217typedef struct AHCIREQ *PAHCIREQ;
218
219/** Task encountered a buffer overflow. */
220#define AHCI_REQ_OVERFLOW RT_BIT_32(0)
221/** Request is a PIO data command, if this flag is not set it either is
222 * a command which does not transfer data or a DMA command based on the transfer size. */
223#define AHCI_REQ_PIO_DATA RT_BIT_32(1)
224/** The request has the SACT register set. */
225#define AHCI_REQ_CLEAR_SACT RT_BIT_32(2)
226/** Flag whether the request is queued. */
227#define AHCI_REQ_IS_QUEUED RT_BIT_32(3)
228/** Flag whether the request is stored on the stack. */
229#define AHCI_REQ_IS_ON_STACK RT_BIT_32(4)
230/** Flag whether this request transfers data from the device to the HBA or
231 * the other way around .*/
232#define AHCI_REQ_XFER_2_HOST RT_BIT_32(5)
233
234/**
235 * A task state.
236 */
237typedef struct AHCIREQ
238{
239 /** The I/O request handle from the driver below associated with this request. */
240 PDMMEDIAEXIOREQ hIoReq;
241 /** Tag of the task. */
242 uint32_t uTag;
243 /** The command Fis for this task. */
244 uint8_t cmdFis[AHCI_CMDFIS_TYPE_H2D_SIZE];
245 /** The ATAPI command data. */
246 uint8_t aATAPICmd[ATAPI_PACKET_SIZE];
247 /** Size of one sector for the ATAPI transfer. */
248 uint32_t cbATAPISector;
249 /** Physical address of the command header. - GC */
250 RTGCPHYS GCPhysCmdHdrAddr;
251 /** Physical address of the PRDT */
252 RTGCPHYS GCPhysPrdtl;
253 /** Number of entries in the PRDTL. */
254 unsigned cPrdtlEntries;
255 /** Data direction. */
256 PDMMEDIAEXIOREQTYPE enmType;
257 /** Start offset. */
258 uint64_t uOffset;
259 /** Number of bytes to transfer. */
260 size_t cbTransfer;
261 /** Flags for this task. */
262 uint32_t fFlags;
263 /** SCSI status code. */
264 uint8_t u8ScsiSts;
265 /** Flag when the buffer is mapped. */
266 bool fMapped;
267 /** Page lock when the buffer is mapped. */
268 PGMPAGEMAPLOCK PgLck;
269} AHCIREQ;
270
271/**
272 * Notifier queue item.
273 */
274typedef struct DEVPORTNOTIFIERQUEUEITEM
275{
276 /** The core part owned by the queue manager. */
277 PDMQUEUEITEMCORE Core;
278 /** The port to process. */
279 uint8_t iPort;
280} DEVPORTNOTIFIERQUEUEITEM, *PDEVPORTNOTIFIERQUEUEITEM;
281
282
283/**
284 * @implements PDMIBASE
285 * @implements PDMIMEDIAPORT
286 * @implements PDMIMEDIAEXPORT
287 */
288typedef struct AHCIPort
289{
290 /** Pointer to the device instance - HC ptr */
291 PPDMDEVINSR3 pDevInsR3;
292 /** Pointer to the device instance - R0 ptr */
293 PPDMDEVINSR0 pDevInsR0;
294 /** Pointer to the device instance - RC ptr. */
295 PPDMDEVINSRC pDevInsRC;
296
297#if HC_ARCH_BITS == 64
298 uint32_t Alignment0;
299#endif
300
301 /** Pointer to the parent AHCI structure - R3 ptr. */
302 R3PTRTYPE(struct AHCI *) pAhciR3;
303 /** Pointer to the parent AHCI structure - R0 ptr. */
304 R0PTRTYPE(struct AHCI *) pAhciR0;
305 /** Pointer to the parent AHCI structure - RC ptr. */
306 RCPTRTYPE(struct AHCI *) pAhciRC;
307
308 /** Command List Base Address. */
309 uint32_t regCLB;
310 /** Command List Base Address upper bits. */
311 uint32_t regCLBU;
312 /** FIS Base Address. */
313 uint32_t regFB;
314 /** FIS Base Address upper bits. */
315 uint32_t regFBU;
316 /** Interrupt Status. */
317 volatile uint32_t regIS;
318 /** Interrupt Enable. */
319 uint32_t regIE;
320 /** Command. */
321 uint32_t regCMD;
322 /** Task File Data. */
323 uint32_t regTFD;
324 /** Signature */
325 uint32_t regSIG;
326 /** Serial ATA Status. */
327 uint32_t regSSTS;
328 /** Serial ATA Control. */
329 uint32_t regSCTL;
330 /** Serial ATA Error. */
331 uint32_t regSERR;
332 /** Serial ATA Active. */
333 volatile uint32_t regSACT;
334 /** Command Issue. */
335 uint32_t regCI;
336
337 /** Current number of active tasks. */
338 volatile uint32_t cTasksActive;
339 /** Command List Base Address */
340 volatile RTGCPHYS GCPhysAddrClb;
341 /** FIS Base Address */
342 volatile RTGCPHYS GCPhysAddrFb;
343
344 /** Device is powered on. */
345 bool fPoweredOn;
346 /** Device has spun up. */
347 bool fSpunUp;
348 /** First D2H FIS was sent. */
349 bool fFirstD2HFisSent;
350 /** Attached device is a CD/DVD drive. */
351 bool fATAPI;
352 /** Flag whether this port is in a reset state. */
353 volatile bool fPortReset;
354 /** Flag whether TRIM is supported. */
355 bool fTrimEnabled;
356 /** Flag if we are in a device reset. */
357 bool fResetDevice;
358 /** Flag whether this port is hot plug capable. */
359 bool fHotpluggable;
360 /** Flag whether the port is in redo task mode. */
361 volatile bool fRedo;
362 /** Flag whether the worker thread is sleeping. */
363 volatile bool fWrkThreadSleeping;
364
365 bool afAlignment[4];
366
367 /** Number of total sectors. */
368 uint64_t cTotalSectors;
369 /** Size of one sector. */
370 uint32_t cbSector;
371 /** Currently configured number of sectors in a multi-sector transfer. */
372 uint32_t cMultSectors;
373 /** Currently active transfer mode (MDMA/UDMA) and speed. */
374 uint8_t uATATransferMode;
375 /** ATAPI sense data. */
376 uint8_t abATAPISense[ATAPI_SENSE_SIZE];
377 /** Exponent of logical sectors in a physical sector, number of logical sectors is 2^exp. */
378 uint8_t cLogSectorsPerPhysicalExp;
379 /** The LUN. */
380 RTUINT iLUN;
381
382 /** Bitmap for finished tasks (R3 -> Guest). */
383 volatile uint32_t u32TasksFinished;
384 /** Bitmap for finished queued tasks (R3 -> Guest). */
385 volatile uint32_t u32QueuedTasksFinished;
386 /** Bitmap for new queued tasks (Guest -> R3). */
387 volatile uint32_t u32TasksNew;
388 /** Bitmap of tasks which must be redone because of a non fatal error. */
389 volatile uint32_t u32TasksRedo;
390
391 /** Current command slot processed.
392 * Accessed by the guest by reading the CMD register.
393 * Holds the command slot of the command processed at the moment. */
394 volatile uint32_t u32CurrentCommandSlot;
395
396#if HC_ARCH_BITS == 64
397 uint32_t u32Alignment2;
398#endif
399
400 /** Device specific settings (R3 only stuff). */
401 /** Pointer to the attached driver's base interface. */
402 R3PTRTYPE(PPDMIBASE) pDrvBase;
403 /** Pointer to the attached driver's block interface. */
404 R3PTRTYPE(PPDMIMEDIA) pDrvMedia;
405 /** Pointer to the attached driver's extended interface. */
406 R3PTRTYPE(PPDMIMEDIAEX) pDrvMediaEx;
407 /** The base interface. */
408 PDMIBASE IBase;
409 /** The block port interface. */
410 PDMIMEDIAPORT IPort;
411 /** The extended media port interface. */
412 PDMIMEDIAEXPORT IMediaExPort;
413 /** Physical geometry of this image. */
414 PDMMEDIAGEOMETRY PCHSGeometry;
415 /** The status LED state for this drive. */
416 PDMLED Led;
417
418 uint32_t u32Alignment3;
419
420 /** Async IO Thread. */
421 R3PTRTYPE(PPDMTHREAD) pAsyncIOThread;
422 /** First task throwing an error. */
423 R3PTRTYPE(volatile PAHCIREQ) pTaskErr;
424
425 /** The event semaphore the processing thread waits on. */
426 SUPSEMEVENT hEvtProcess;
427
428 /** The serial numnber to use for IDENTIFY DEVICE commands. */
429 char szSerialNumber[AHCI_SERIAL_NUMBER_LENGTH+1]; /** < one extra byte for termination */
430 /** The firmware revision to use for IDENTIFY DEVICE commands. */
431 char szFirmwareRevision[AHCI_FIRMWARE_REVISION_LENGTH+1]; /** < one extra byte for termination */
432 /** The model number to use for IDENTIFY DEVICE commands. */
433 char szModelNumber[AHCI_MODEL_NUMBER_LENGTH+1]; /** < one extra byte for termination */
434 /** The vendor identification string for SCSI INQUIRY commands. */
435 char szInquiryVendorId[AHCI_ATAPI_INQUIRY_VENDOR_ID_LENGTH+1];
436 /** The product identification string for SCSI INQUIRY commands. */
437 char szInquiryProductId[AHCI_ATAPI_INQUIRY_PRODUCT_ID_LENGTH+1];
438 /** The revision string for SCSI INQUIRY commands. */
439 char szInquiryRevision[AHCI_ATAPI_INQUIRY_REVISION_LENGTH+1];
440 /** Error counter */
441 uint32_t cErrors;
442
443 uint32_t u32Alignment5;
444
445} AHCIPort;
446/** Pointer to the state of an AHCI port. */
447typedef AHCIPort *PAHCIPort;
448
449AssertCompileSizeAlignment(AHCIPort, 8);
450
451/**
452 * Main AHCI device state.
453 *
454 * @implements PDMILEDPORTS
455 */
456typedef struct AHCI
457{
458 /** The PCI device structure. */
459 PDMPCIDEV dev;
460 /** Pointer to the device instance - R3 ptr */
461 PPDMDEVINSR3 pDevInsR3;
462 /** Pointer to the device instance - R0 ptr */
463 PPDMDEVINSR0 pDevInsR0;
464 /** Pointer to the device instance - RC ptr. */
465 PPDMDEVINSRC pDevInsRC;
466
467#if HC_ARCH_BITS == 64
468 uint32_t Alignment0;
469#endif
470
471 /** Status LUN: The base interface. */
472 PDMIBASE IBase;
473 /** Status LUN: Leds interface. */
474 PDMILEDPORTS ILeds;
475 /** Status LUN: Partner of ILeds. */
476 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
477 /** Status LUN: Media Notifys. */
478 R3PTRTYPE(PPDMIMEDIANOTIFY) pMediaNotify;
479
480#if HC_ARCH_BITS == 32
481 uint32_t Alignment1;
482#endif
483
484 /** Base address of the MMIO region. */
485 RTGCPHYS MMIOBase;
486 /** Base address of the I/O port region for Idx/Data. */
487 RTIOPORT IOPortBase;
488
489 /** Global Host Control register of the HBA */
490
491 /** HBA Capabilities - Readonly */
492 uint32_t regHbaCap;
493 /** HBA Control */
494 uint32_t regHbaCtrl;
495 /** Interrupt Status */
496 uint32_t regHbaIs;
497 /** Ports Implemented - Readonly */
498 uint32_t regHbaPi;
499 /** AHCI Version - Readonly */
500 uint32_t regHbaVs;
501 /** Command completion coalescing control */
502 uint32_t regHbaCccCtl;
503 /** Command completion coalescing ports */
504 uint32_t regHbaCccPorts;
505
506 /** Index register for BIOS access. */
507 uint32_t regIdx;
508
509#if HC_ARCH_BITS == 64
510 uint32_t Alignment3;
511#endif
512
513 /** Countdown timer for command completion coalescing - R3 ptr */
514 PTMTIMERR3 pHbaCccTimerR3;
515 /** Countdown timer for command completion coalescing - R0 ptr */
516 PTMTIMERR0 pHbaCccTimerR0;
517 /** Countdown timer for command completion coalescing - RC ptr */
518 PTMTIMERRC pHbaCccTimerRC;
519
520#if HC_ARCH_BITS == 64
521 uint32_t Alignment4;
522#endif
523
524 /** Queue to send tasks to R3. - HC ptr */
525 R3PTRTYPE(PPDMQUEUE) pNotifierQueueR3;
526 /** Queue to send tasks to R3. - HC ptr */
527 R0PTRTYPE(PPDMQUEUE) pNotifierQueueR0;
528 /** Queue to send tasks to R3. - RC ptr */
529 RCPTRTYPE(PPDMQUEUE) pNotifierQueueRC;
530
531#if HC_ARCH_BITS == 64
532 uint32_t Alignment5;
533#endif
534
535
536 /** Which port number is used to mark an CCC interrupt */
537 uint8_t uCccPortNr;
538
539#if HC_ARCH_BITS == 64
540 uint32_t Alignment6;
541#endif
542
543 /** Timeout value */
544 uint64_t uCccTimeout;
545 /** Number of completions used to assert an interrupt */
546 uint32_t uCccNr;
547 /** Current number of completed commands */
548 uint32_t uCccCurrentNr;
549
550 /** Register structure per port */
551 AHCIPort ahciPort[AHCI_MAX_NR_PORTS_IMPL];
552
553 /** The critical section. */
554 PDMCRITSECT lock;
555
556 /** Bitmask of ports which asserted an interrupt. */
557 volatile uint32_t u32PortsInterrupted;
558 /** Number of I/O threads currently active - used for async controller reset handling. */
559 volatile uint32_t cThreadsActive;
560 /** Device is in a reset state. */
561 bool fReset;
562 /** Supports 64bit addressing */
563 bool f64BitAddr;
564 /** GC enabled. */
565 bool fGCEnabled;
566 /** R0 enabled. */
567 bool fR0Enabled;
568 /** Indicates that PDMDevHlpAsyncNotificationCompleted should be called when
569 * a port is entering the idle state. */
570 bool volatile fSignalIdle;
571 /** Flag whether the controller has BIOS access enabled. */
572 bool fBootable;
573 /** Flag whether the legacy port reset method should be used to make it work with saved states. */
574 bool fLegacyPortResetMethod;
575
576 /** Number of usable ports on this controller. */
577 uint32_t cPortsImpl;
578 /** Number of usable command slots for each port. */
579 uint32_t cCmdSlotsAvail;
580
581 /** Flag whether we have written the first 4bytes in an 8byte MMIO write successfully. */
582 volatile bool f8ByteMMIO4BytesWrittenSuccessfully;
583
584#if HC_ARCH_BITS == 64
585 uint32_t Alignment7;
586#endif
587
588 /** The support driver session handle. */
589 R3R0PTRTYPE(PSUPDRVSESSION) pSupDrvSession;
590} AHCI;
591/** Pointer to the state of an AHCI device. */
592typedef AHCI *PAHCI;
593
594AssertCompileMemberAlignment(AHCI, ahciPort, 8);
595
596/**
597 * Scatter gather list entry.
598 */
599typedef struct
600{
601 /** Data Base Address. */
602 uint32_t u32DBA;
603 /** Data Base Address - Upper 32-bits. */
604 uint32_t u32DBAUp;
605 /** Reserved */
606 uint32_t u32Reserved;
607 /** Description information. */
608 uint32_t u32DescInf;
609} SGLEntry;
610AssertCompileSize(SGLEntry, 16);
611
612#ifdef IN_RING3
613/**
614 * Memory buffer callback.
615 *
616 * @returns nothing.
617 * @param pThis The NVME controller instance.
618 * @param GCPhys The guest physical address of the memory buffer.
619 * @param pSgBuf The pointer to the host R3 S/G buffer.
620 * @param cbCopy How many bytes to copy between the two buffers.
621 * @param pcbSkip Initially contains the amount of bytes to skip
622 * starting from the guest physical address before
623 * accessing the S/G buffer and start copying data.
624 * On return this contains the remaining amount if
625 * cbCopy < *pcbSkip or 0 otherwise.
626 */
627typedef DECLCALLBACK(void) AHCIR3MEMCOPYCALLBACK(PAHCI pThis, RTGCPHYS GCPhys, PRTSGBUF pSgBuf, size_t cbCopy,
628 size_t *pcbSkip);
629/** Pointer to a memory copy buffer callback. */
630typedef AHCIR3MEMCOPYCALLBACK *PAHCIR3MEMCOPYCALLBACK;
631#endif
632
633/** Defines for a scatter gather list entry. */
634#define SGLENTRY_DBA_READONLY ~(RT_BIT(0))
635#define SGLENTRY_DESCINF_I RT_BIT(31)
636#define SGLENTRY_DESCINF_DBC 0x3fffff
637#define SGLENTRY_DESCINF_READONLY 0x803fffff
638
639/* Defines for the global host control registers for the HBA. */
640
641#define AHCI_HBA_GLOBAL_SIZE 0x100
642
643/* Defines for the HBA Capabilities - Readonly */
644#define AHCI_HBA_CAP_S64A RT_BIT(31)
645#define AHCI_HBA_CAP_SNCQ RT_BIT(30)
646#define AHCI_HBA_CAP_SIS RT_BIT(28)
647#define AHCI_HBA_CAP_SSS RT_BIT(27)
648#define AHCI_HBA_CAP_SALP RT_BIT(26)
649#define AHCI_HBA_CAP_SAL RT_BIT(25)
650#define AHCI_HBA_CAP_SCLO RT_BIT(24)
651#define AHCI_HBA_CAP_ISS (RT_BIT(23) | RT_BIT(22) | RT_BIT(21) | RT_BIT(20))
652# define AHCI_HBA_CAP_ISS_SHIFT(x) (((x) << 20) & AHCI_HBA_CAP_ISS)
653# define AHCI_HBA_CAP_ISS_GEN1 RT_BIT(0)
654# define AHCI_HBA_CAP_ISS_GEN2 RT_BIT(1)
655#define AHCI_HBA_CAP_SNZO RT_BIT(19)
656#define AHCI_HBA_CAP_SAM RT_BIT(18)
657#define AHCI_HBA_CAP_SPM RT_BIT(17)
658#define AHCI_HBA_CAP_PMD RT_BIT(15)
659#define AHCI_HBA_CAP_SSC RT_BIT(14)
660#define AHCI_HBA_CAP_PSC RT_BIT(13)
661#define AHCI_HBA_CAP_NCS (RT_BIT(12) | RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8))
662#define AHCI_HBA_CAP_NCS_SET(x) (((x-1) << 8) & AHCI_HBA_CAP_NCS) /* 0's based */
663#define AHCI_HBA_CAP_CCCS RT_BIT(7)
664#define AHCI_HBA_CAP_NP (RT_BIT(4) | RT_BIT(3) | RT_BIT(2) | RT_BIT(1) | RT_BIT(0))
665#define AHCI_HBA_CAP_NP_SET(x) ((x-1) & AHCI_HBA_CAP_NP) /* 0's based */
666
667/* Defines for the HBA Control register - Read/Write */
668#define AHCI_HBA_CTRL_AE RT_BIT(31)
669#define AHCI_HBA_CTRL_IE RT_BIT(1)
670#define AHCI_HBA_CTRL_HR RT_BIT(0)
671#define AHCI_HBA_CTRL_RW_MASK (RT_BIT(0) | RT_BIT(1)) /* Mask for the used bits */
672
673/* Defines for the HBA Version register - Readonly (We support AHCI 1.0) */
674#define AHCI_HBA_VS_MJR (1 << 16)
675#define AHCI_HBA_VS_MNR 0x100
676
677/* Defines for the command completion coalescing control register */
678#define AHCI_HBA_CCC_CTL_TV 0xffff0000
679#define AHCI_HBA_CCC_CTL_TV_SET(x) (x << 16)
680#define AHCI_HBA_CCC_CTL_TV_GET(x) ((x & AHCI_HBA_CCC_CTL_TV) >> 16)
681
682#define AHCI_HBA_CCC_CTL_CC 0xff00
683#define AHCI_HBA_CCC_CTL_CC_SET(x) (x << 8)
684#define AHCI_HBA_CCC_CTL_CC_GET(x) ((x & AHCI_HBA_CCC_CTL_CC) >> 8)
685
686#define AHCI_HBA_CCC_CTL_INT 0xf8
687#define AHCI_HBA_CCC_CTL_INT_SET(x) (x << 3)
688#define AHCI_HBA_CCC_CTL_INT_GET(x) ((x & AHCI_HBA_CCC_CTL_INT) >> 3)
689
690#define AHCI_HBA_CCC_CTL_EN RT_BIT(0)
691
692/* Defines for the port registers. */
693
694#define AHCI_PORT_REGISTER_SIZE 0x80
695
696#define AHCI_PORT_CLB_RESERVED 0xfffffc00 /* For masking out the reserved bits. */
697
698#define AHCI_PORT_FB_RESERVED 0xffffff00 /* For masking out the reserved bits. */
699
700#define AHCI_PORT_IS_CPDS RT_BIT(31)
701#define AHCI_PORT_IS_TFES RT_BIT(30)
702#define AHCI_PORT_IS_HBFS RT_BIT(29)
703#define AHCI_PORT_IS_HBDS RT_BIT(28)
704#define AHCI_PORT_IS_IFS RT_BIT(27)
705#define AHCI_PORT_IS_INFS RT_BIT(26)
706#define AHCI_PORT_IS_OFS RT_BIT(24)
707#define AHCI_PORT_IS_IPMS RT_BIT(23)
708#define AHCI_PORT_IS_PRCS RT_BIT(22)
709#define AHCI_PORT_IS_DIS RT_BIT(7)
710#define AHCI_PORT_IS_PCS RT_BIT(6)
711#define AHCI_PORT_IS_DPS RT_BIT(5)
712#define AHCI_PORT_IS_UFS RT_BIT(4)
713#define AHCI_PORT_IS_SDBS RT_BIT(3)
714#define AHCI_PORT_IS_DSS RT_BIT(2)
715#define AHCI_PORT_IS_PSS RT_BIT(1)
716#define AHCI_PORT_IS_DHRS RT_BIT(0)
717#define AHCI_PORT_IS_READONLY 0xfd8000af /* Readonly mask including reserved bits. */
718
719#define AHCI_PORT_IE_CPDE RT_BIT(31)
720#define AHCI_PORT_IE_TFEE RT_BIT(30)
721#define AHCI_PORT_IE_HBFE RT_BIT(29)
722#define AHCI_PORT_IE_HBDE RT_BIT(28)
723#define AHCI_PORT_IE_IFE RT_BIT(27)
724#define AHCI_PORT_IE_INFE RT_BIT(26)
725#define AHCI_PORT_IE_OFE RT_BIT(24)
726#define AHCI_PORT_IE_IPME RT_BIT(23)
727#define AHCI_PORT_IE_PRCE RT_BIT(22)
728#define AHCI_PORT_IE_DIE RT_BIT(7) /* Not supported for now, readonly. */
729#define AHCI_PORT_IE_PCE RT_BIT(6)
730#define AHCI_PORT_IE_DPE RT_BIT(5)
731#define AHCI_PORT_IE_UFE RT_BIT(4)
732#define AHCI_PORT_IE_SDBE RT_BIT(3)
733#define AHCI_PORT_IE_DSE RT_BIT(2)
734#define AHCI_PORT_IE_PSE RT_BIT(1)
735#define AHCI_PORT_IE_DHRE RT_BIT(0)
736#define AHCI_PORT_IE_READONLY (0xfdc000ff) /* Readonly mask including reserved bits. */
737
738#define AHCI_PORT_CMD_ICC (RT_BIT(28) | RT_BIT(29) | RT_BIT(30) | RT_BIT(31))
739#define AHCI_PORT_CMD_ICC_SHIFT(x) ((x) << 28)
740# define AHCI_PORT_CMD_ICC_IDLE 0x0
741# define AHCI_PORT_CMD_ICC_ACTIVE 0x1
742# define AHCI_PORT_CMD_ICC_PARTIAL 0x2
743# define AHCI_PORT_CMD_ICC_SLUMBER 0x6
744#define AHCI_PORT_CMD_ASP RT_BIT(27) /* Not supported - Readonly */
745#define AHCI_PORT_CMD_ALPE RT_BIT(26) /* Not supported - Readonly */
746#define AHCI_PORT_CMD_DLAE RT_BIT(25)
747#define AHCI_PORT_CMD_ATAPI RT_BIT(24)
748#define AHCI_PORT_CMD_CPD RT_BIT(20)
749#define AHCI_PORT_CMD_ISP RT_BIT(19) /* Readonly */
750#define AHCI_PORT_CMD_HPCP RT_BIT(18)
751#define AHCI_PORT_CMD_PMA RT_BIT(17) /* Not supported - Readonly */
752#define AHCI_PORT_CMD_CPS RT_BIT(16)
753#define AHCI_PORT_CMD_CR RT_BIT(15) /* Readonly */
754#define AHCI_PORT_CMD_FR RT_BIT(14) /* Readonly */
755#define AHCI_PORT_CMD_ISS RT_BIT(13) /* Readonly */
756#define AHCI_PORT_CMD_CCS (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11) | RT_BIT(12))
757#define AHCI_PORT_CMD_CCS_SHIFT(x) (x << 8) /* Readonly */
758#define AHCI_PORT_CMD_FRE RT_BIT(4)
759#define AHCI_PORT_CMD_CLO RT_BIT(3)
760#define AHCI_PORT_CMD_POD RT_BIT(2)
761#define AHCI_PORT_CMD_SUD RT_BIT(1)
762#define AHCI_PORT_CMD_ST RT_BIT(0)
763#define AHCI_PORT_CMD_READONLY (0xff02001f & ~(AHCI_PORT_CMD_ASP | AHCI_PORT_CMD_ALPE | AHCI_PORT_CMD_PMA))
764
765#define AHCI_PORT_SCTL_IPM (RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8))
766#define AHCI_PORT_SCTL_IPM_GET(x) ((x & AHCI_PORT_SCTL_IPM) >> 8)
767#define AHCI_PORT_SCTL_SPD (RT_BIT(7) | RT_BIT(6) | RT_BIT(5) | RT_BIT(4))
768#define AHCI_PORT_SCTL_SPD_GET(x) ((x & AHCI_PORT_SCTL_SPD) >> 4)
769#define AHCI_PORT_SCTL_DET (RT_BIT(3) | RT_BIT(2) | RT_BIT(1) | RT_BIT(0))
770#define AHCI_PORT_SCTL_DET_GET(x) (x & AHCI_PORT_SCTL_DET)
771#define AHCI_PORT_SCTL_DET_NINIT 0
772#define AHCI_PORT_SCTL_DET_INIT 1
773#define AHCI_PORT_SCTL_DET_OFFLINE 4
774#define AHCI_PORT_SCTL_READONLY 0xfff
775
776#define AHCI_PORT_SSTS_IPM (RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8))
777#define AHCI_PORT_SSTS_IPM_GET(x) ((x & AHCI_PORT_SCTL_IPM) >> 8)
778#define AHCI_PORT_SSTS_SPD (RT_BIT(7) | RT_BIT(6) | RT_BIT(5) | RT_BIT(4))
779#define AHCI_PORT_SSTS_SPD_GET(x) ((x & AHCI_PORT_SCTL_SPD) >> 4)
780#define AHCI_PORT_SSTS_DET (RT_BIT(3) | RT_BIT(2) | RT_BIT(1) | RT_BIT(0))
781#define AHCI_PORT_SSTS_DET_GET(x) (x & AHCI_PORT_SCTL_DET)
782
783#define AHCI_PORT_TFD_BSY RT_BIT(7)
784#define AHCI_PORT_TFD_DRQ RT_BIT(3)
785#define AHCI_PORT_TFD_ERR RT_BIT(0)
786
787#define AHCI_PORT_SERR_X RT_BIT(26)
788#define AHCI_PORT_SERR_W RT_BIT(18)
789#define AHCI_PORT_SERR_N RT_BIT(16)
790
791/* Signatures for attached storage devices. */
792#define AHCI_PORT_SIG_DISK 0x00000101
793#define AHCI_PORT_SIG_ATAPI 0xeb140101
794
795/*
796 * The AHCI spec defines an area of memory where the HBA posts received FIS's from the device.
797 * regFB points to the base of this area.
798 * Every FIS type has an offset where it is posted in this area.
799 */
800#define AHCI_RECFIS_DSFIS_OFFSET 0x00 /* DMA Setup FIS */
801#define AHCI_RECFIS_PSFIS_OFFSET 0x20 /* PIO Setup FIS */
802#define AHCI_RECFIS_RFIS_OFFSET 0x40 /* D2H Register FIS */
803#define AHCI_RECFIS_SDBFIS_OFFSET 0x58 /* Set Device Bits FIS */
804#define AHCI_RECFIS_UFIS_OFFSET 0x60 /* Unknown FIS type */
805
806/** Mask to get the LBA value from a LBA range. */
807#define AHCI_RANGE_LBA_MASK UINT64_C(0xffffffffffff)
808/** Mas to get the length value from a LBA range. */
809#define AHCI_RANGE_LENGTH_MASK UINT64_C(0xffff000000000000)
810/** Returns the length of the range in sectors. */
811#define AHCI_RANGE_LENGTH_GET(val) (((val) & AHCI_RANGE_LENGTH_MASK) >> 48)
812
813/**
814 * AHCI register operator.
815 */
816typedef struct ahci_opreg
817{
818 const char *pszName;
819 int (*pfnRead )(PAHCI pAhci, uint32_t iReg, uint32_t *pu32Value);
820 int (*pfnWrite)(PAHCI pAhci, uint32_t iReg, uint32_t u32Value);
821} AHCIOPREG;
822
823/**
824 * AHCI port register operator.
825 */
826typedef struct pAhciPort_opreg
827{
828 const char *pszName;
829 int (*pfnRead )(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value);
830 int (*pfnWrite)(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value);
831} AHCIPORTOPREG;
832
833#ifndef VBOX_DEVICE_STRUCT_TESTCASE
834RT_C_DECLS_BEGIN
835#ifdef IN_RING3
836static void ahciHBAReset(PAHCI pThis);
837static int ahciPostFisIntoMemory(PAHCIPort pAhciPort, unsigned uFisType, uint8_t *cmdFis);
838static void ahciPostFirstD2HFisIntoMemory(PAHCIPort pAhciPort);
839static size_t ahciR3CopyBufferToPrdtl(PAHCI pThis, PAHCIREQ pAhciReq, const void *pvSrc,
840 size_t cbSrc, size_t cbSkip);
841static bool ahciCancelActiveTasks(PAHCIPort pAhciPort);
842#endif
843RT_C_DECLS_END
844
845#define PCIDEV_2_PAHCI(pPciDev) ( (PAHCI)(pPciDev) )
846#define PDMIBASE_2_PAHCIPORT(pInterface) ( (PAHCIPort)((uintptr_t)(pInterface) - RT_UOFFSETOF(AHCIPort, IBase)) )
847#define PDMIMEDIAPORT_2_PAHCIPORT(pInterface) ( (PAHCIPort)((uintptr_t)(pInterface) - RT_UOFFSETOF(AHCIPort, IPort)) )
848#define PDMIBASE_2_PAHCI(pInterface) ( (PAHCI)((uintptr_t)(pInterface) - RT_UOFFSETOF(AHCI, IBase)) )
849#define PDMILEDPORTS_2_PAHCI(pInterface) ( (PAHCI)((uintptr_t)(pInterface) - RT_UOFFSETOF(AHCI, ILeds)) )
850
851#define AHCI_RTGCPHYS_FROM_U32(Hi, Lo) ( (RTGCPHYS)RT_MAKE_U64(Lo, Hi) )
852
853#ifdef IN_RING3
854
855# ifdef LOG_USE_C99
856# define ahciLog(a) \
857 Log(("R3 P%u: %M", pAhciPort->iLUN, _LogRelRemoveParentheseis a))
858# else
859# define ahciLog(a) \
860 do { Log(("R3 P%u: ", pAhciPort->iLUN)); Log(a); } while(0)
861# endif
862
863#elif defined(IN_RING0)
864
865# ifdef LOG_USE_C99
866# define ahciLog(a) \
867 Log(("R0 P%u: %M", pAhciPort->iLUN, _LogRelRemoveParentheseis a))
868# else
869# define ahciLog(a) \
870 do { Log(("R0 P%u: ", pAhciPort->iLUN)); Log(a); } while(0)
871# endif
872
873#elif defined(IN_RC)
874
875# ifdef LOG_USE_C99
876# define ahciLog(a) \
877 Log(("GC P%u: %M", pAhciPort->iLUN, _LogRelRemoveParentheseis a))
878# else
879# define ahciLog(a) \
880 do { Log(("GC P%u: ", pAhciPort->iLUN)); Log(a); } while(0)
881# endif
882
883#endif
884
885/**
886 * Update PCI IRQ levels
887 */
888static void ahciHbaClearInterrupt(PAHCI pAhci)
889{
890 Log(("%s: Clearing interrupt\n", __FUNCTION__));
891 PDMDevHlpPCISetIrq(pAhci->CTX_SUFF(pDevIns), 0, 0);
892}
893
894/**
895 * Updates the IRQ level and sets port bit in the global interrupt status register of the HBA.
896 */
897static int ahciHbaSetInterrupt(PAHCI pAhci, uint8_t iPort, int rcBusy)
898{
899 Log(("P%u: %s: Setting interrupt\n", iPort, __FUNCTION__));
900
901 int rc = PDMCritSectEnter(&pAhci->lock, rcBusy);
902 if (rc != VINF_SUCCESS)
903 return rc;
904
905 if (pAhci->regHbaCtrl & AHCI_HBA_CTRL_IE)
906 {
907 if ((pAhci->regHbaCccCtl & AHCI_HBA_CCC_CTL_EN) && (pAhci->regHbaCccPorts & (1 << iPort)))
908 {
909 pAhci->uCccCurrentNr++;
910 if (pAhci->uCccCurrentNr >= pAhci->uCccNr)
911 {
912 /* Reset command completion coalescing state. */
913 TMTimerSetMillies(pAhci->CTX_SUFF(pHbaCccTimer), pAhci->uCccTimeout);
914 pAhci->uCccCurrentNr = 0;
915
916 pAhci->u32PortsInterrupted |= (1 << pAhci->uCccPortNr);
917 if (!(pAhci->u32PortsInterrupted & ~(1 << pAhci->uCccPortNr)))
918 {
919 Log(("P%u: %s: Fire interrupt\n", iPort, __FUNCTION__));
920 PDMDevHlpPCISetIrq(pAhci->CTX_SUFF(pDevIns), 0, 1);
921 }
922 }
923 }
924 else
925 {
926 /* If only the bit of the actual port is set assert an interrupt
927 * because the interrupt status register was already read by the guest
928 * and we need to send a new notification.
929 * Otherwise an interrupt is still pending.
930 */
931 ASMAtomicOrU32((volatile uint32_t *)&pAhci->u32PortsInterrupted, (1 << iPort));
932 if (!(pAhci->u32PortsInterrupted & ~(1 << iPort)))
933 {
934 Log(("P%u: %s: Fire interrupt\n", iPort, __FUNCTION__));
935 PDMDevHlpPCISetIrq(pAhci->CTX_SUFF(pDevIns), 0, 1);
936 }
937 }
938 }
939
940 PDMCritSectLeave(&pAhci->lock);
941 return VINF_SUCCESS;
942}
943
944#ifdef IN_RING3
945
946/*
947 * Assert irq when an CCC timeout occurs
948 */
949static DECLCALLBACK(void) ahciCccTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
950{
951 RT_NOREF(pDevIns, pTimer);
952 PAHCI pAhci = (PAHCI)pvUser;
953
954 int rc = ahciHbaSetInterrupt(pAhci, pAhci->uCccPortNr, VERR_IGNORED);
955 AssertRC(rc);
956}
957
958/**
959 * Finishes the port reset of the given port.
960 *
961 * @returns nothing.
962 * @param pAhciPort The port to finish the reset on.
963 */
964static void ahciPortResetFinish(PAHCIPort pAhciPort)
965{
966 ahciLog(("%s: Initiated.\n", __FUNCTION__));
967
968 /* Cancel all tasks first. */
969 bool fAllTasksCanceled = ahciCancelActiveTasks(pAhciPort);
970 Assert(fAllTasksCanceled); NOREF(fAllTasksCanceled);
971
972 /* Signature for SATA device. */
973 if (pAhciPort->fATAPI)
974 pAhciPort->regSIG = AHCI_PORT_SIG_ATAPI;
975 else
976 pAhciPort->regSIG = AHCI_PORT_SIG_DISK;
977
978 /* We received a COMINIT from the device. Tell the guest. */
979 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_PCS);
980 pAhciPort->regSERR |= AHCI_PORT_SERR_X;
981 pAhciPort->regTFD |= ATA_STAT_BUSY;
982
983 if ((pAhciPort->regCMD & AHCI_PORT_CMD_FRE) && (!pAhciPort->fFirstD2HFisSent))
984 {
985 ahciPostFirstD2HFisIntoMemory(pAhciPort);
986 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_DHRS);
987
988 if (pAhciPort->regIE & AHCI_PORT_IE_DHRE)
989 {
990 int rc = ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN, VERR_IGNORED);
991 AssertRC(rc);
992 }
993 }
994
995 pAhciPort->regSSTS = (0x01 << 8) | /* Interface is active. */
996 (0x03 << 0); /* Device detected and communication established. */
997
998 /*
999 * Use the maximum allowed speed.
1000 * (Not that it changes anything really)
1001 */
1002 switch (AHCI_PORT_SCTL_SPD_GET(pAhciPort->regSCTL))
1003 {
1004 case 0x01:
1005 pAhciPort->regSSTS |= (0x01 << 4); /* Generation 1 (1.5GBps) speed. */
1006 break;
1007 case 0x02:
1008 case 0x00:
1009 default:
1010 pAhciPort->regSSTS |= (0x02 << 4); /* Generation 2 (3.0GBps) speed. */
1011 break;
1012 }
1013
1014 ASMAtomicXchgBool(&pAhciPort->fPortReset, false);
1015}
1016
1017#endif /* IN_RING3 */
1018
1019/**
1020 * Kicks the I/O thread from RC or R0.
1021 *
1022 * @returns nothing.
1023 * @param pAhci The AHCI controller instance.
1024 * @param pAhciPort The port to kick.
1025 */
1026static void ahciIoThreadKick(PAHCI pAhci, PAHCIPort pAhciPort)
1027{
1028#ifdef IN_RC
1029 PDEVPORTNOTIFIERQUEUEITEM pItem = (PDEVPORTNOTIFIERQUEUEITEM)PDMQueueAlloc(pAhci->CTX_SUFF(pNotifierQueue));
1030 AssertMsg(VALID_PTR(pItem), ("Allocating item for queue failed\n"));
1031
1032 if (pItem)
1033 {
1034 pItem->iPort = pAhciPort->iLUN;
1035 PDMQueueInsert(pAhci->CTX_SUFF(pNotifierQueue), (PPDMQUEUEITEMCORE)pItem);
1036 }
1037#else
1038 LogFlowFunc(("Signal event semaphore\n"));
1039 int rc = SUPSemEventSignal(pAhci->pSupDrvSession, pAhciPort->hEvtProcess);
1040 AssertRC(rc);
1041#endif
1042}
1043
1044static int PortCmdIssue_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1045{
1046 RT_NOREF1(iReg);
1047 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1048
1049 /* Update the CI register first. */
1050 uint32_t uCIValue = ASMAtomicXchgU32(&pAhciPort->u32TasksFinished, 0);
1051 pAhciPort->regCI &= ~uCIValue;
1052
1053 if ( (pAhciPort->regCMD & AHCI_PORT_CMD_CR)
1054 && u32Value > 0)
1055 {
1056 /*
1057 * Clear all tasks which are already marked as busy. The guest
1058 * shouldn't write already busy tasks actually.
1059 */
1060 u32Value &= ~pAhciPort->regCI;
1061
1062 ASMAtomicOrU32(&pAhciPort->u32TasksNew, u32Value);
1063
1064 /* Send a notification to R3 if u32TasksNew was 0 before our write. */
1065 if (ASMAtomicReadBool(&pAhciPort->fWrkThreadSleeping))
1066 ahciIoThreadKick(pAhci, pAhciPort);
1067 else
1068 ahciLog(("%s: Worker thread busy, no need to kick.\n", __FUNCTION__));
1069 }
1070 else
1071 ahciLog(("%s: Nothing to do (CMD=%08x).\n", __FUNCTION__, pAhciPort->regCMD));
1072
1073 pAhciPort->regCI |= u32Value;
1074
1075 return VINF_SUCCESS;
1076}
1077
1078static int PortCmdIssue_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1079{
1080 RT_NOREF2(pAhci, iReg);
1081
1082 uint32_t uCIValue = ASMAtomicXchgU32(&pAhciPort->u32TasksFinished, 0);
1083 ahciLog(("%s: read regCI=%#010x uCIValue=%#010x\n", __FUNCTION__, pAhciPort->regCI, uCIValue));
1084
1085 pAhciPort->regCI &= ~uCIValue;
1086 *pu32Value = pAhciPort->regCI;
1087
1088 return VINF_SUCCESS;
1089}
1090
1091static int PortSActive_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1092{
1093 RT_NOREF2(pAhci, iReg);
1094 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1095
1096 pAhciPort->regSACT |= u32Value;
1097
1098 return VINF_SUCCESS;
1099}
1100
1101static int PortSActive_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1102{
1103 RT_NOREF2(pAhci, iReg);
1104
1105 uint32_t u32TasksFinished = ASMAtomicXchgU32(&pAhciPort->u32QueuedTasksFinished, 0);
1106 pAhciPort->regSACT &= ~u32TasksFinished;
1107
1108 ahciLog(("%s: read regSACT=%#010x regCI=%#010x u32TasksFinished=%#010x\n",
1109 __FUNCTION__, pAhciPort->regSACT, pAhciPort->regCI, u32TasksFinished));
1110
1111 *pu32Value = pAhciPort->regSACT;
1112
1113 return VINF_SUCCESS;
1114}
1115
1116static int PortSError_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1117{
1118 RT_NOREF2(pAhci, iReg);
1119 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1120
1121 if ( (u32Value & AHCI_PORT_SERR_X)
1122 && (pAhciPort->regSERR & AHCI_PORT_SERR_X))
1123 {
1124 ASMAtomicAndU32(&pAhciPort->regIS, ~AHCI_PORT_IS_PCS);
1125 pAhciPort->regTFD |= ATA_STAT_ERR;
1126 pAhciPort->regTFD &= ~(ATA_STAT_DRQ | ATA_STAT_BUSY);
1127 }
1128
1129 if ( (u32Value & AHCI_PORT_SERR_N)
1130 && (pAhciPort->regSERR & AHCI_PORT_SERR_N))
1131 ASMAtomicAndU32(&pAhciPort->regIS, ~AHCI_PORT_IS_PRCS);
1132
1133 pAhciPort->regSERR &= ~u32Value;
1134
1135 return VINF_SUCCESS;
1136}
1137
1138static int PortSError_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1139{
1140 RT_NOREF2(pAhci, iReg);
1141 ahciLog(("%s: read regSERR=%#010x\n", __FUNCTION__, pAhciPort->regSERR));
1142 *pu32Value = pAhciPort->regSERR;
1143 return VINF_SUCCESS;
1144}
1145
1146static int PortSControl_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1147{
1148 RT_NOREF2(pAhci, iReg);
1149 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1150 ahciLog(("%s: IPM=%d SPD=%d DET=%d\n", __FUNCTION__,
1151 AHCI_PORT_SCTL_IPM_GET(u32Value), AHCI_PORT_SCTL_SPD_GET(u32Value), AHCI_PORT_SCTL_DET_GET(u32Value)));
1152
1153#ifndef IN_RING3
1154 RT_NOREF2(pAhciPort, u32Value);
1155 return VINF_IOM_R3_MMIO_WRITE;
1156#else
1157 if ((u32Value & AHCI_PORT_SCTL_DET) == AHCI_PORT_SCTL_DET_INIT)
1158 {
1159 if (!ASMAtomicXchgBool(&pAhciPort->fPortReset, true))
1160 LogRel(("AHCI#%u: Port %d reset\n", pAhci->CTX_SUFF(pDevIns)->iInstance,
1161 pAhciPort->iLUN));
1162
1163 pAhciPort->regSSTS = 0;
1164 pAhciPort->regSIG = UINT32_MAX;
1165 pAhciPort->regTFD = 0x7f;
1166 pAhciPort->fFirstD2HFisSent = false;
1167 pAhciPort->regSCTL = u32Value;
1168 }
1169 else if ( (u32Value & AHCI_PORT_SCTL_DET) == AHCI_PORT_SCTL_DET_NINIT
1170 && (pAhciPort->regSCTL & AHCI_PORT_SCTL_DET) == AHCI_PORT_SCTL_DET_INIT
1171 && pAhciPort->pDrvBase)
1172 {
1173 /* Do the port reset here, so the guest sees the new status immediately. */
1174 if (pAhci->fLegacyPortResetMethod)
1175 {
1176 ahciPortResetFinish(pAhciPort);
1177 pAhciPort->regSCTL = u32Value; /* Update after finishing the reset, so the I/O thread doesn't get a chance to do the reset. */
1178 }
1179 else
1180 {
1181 pAhciPort->regSSTS = 0x1; /* Indicate device presence detected but communication not established. */
1182 pAhciPort->regSCTL = u32Value; /* Update before kicking the I/O thread. */
1183
1184 /* Kick the thread to finish the reset. */
1185 ahciIoThreadKick(pAhci, pAhciPort);
1186 }
1187 }
1188 else /* Just update the value if there is no device attached. */
1189 pAhciPort->regSCTL = u32Value;
1190
1191 return VINF_SUCCESS;
1192#endif
1193}
1194
1195static int PortSControl_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1196{
1197 RT_NOREF2(pAhci, iReg);
1198 ahciLog(("%s: read regSCTL=%#010x\n", __FUNCTION__, pAhciPort->regSCTL));
1199 ahciLog(("%s: IPM=%d SPD=%d DET=%d\n", __FUNCTION__,
1200 AHCI_PORT_SCTL_IPM_GET(pAhciPort->regSCTL), AHCI_PORT_SCTL_SPD_GET(pAhciPort->regSCTL),
1201 AHCI_PORT_SCTL_DET_GET(pAhciPort->regSCTL)));
1202
1203 *pu32Value = pAhciPort->regSCTL;
1204 return VINF_SUCCESS;
1205}
1206
1207static int PortSStatus_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1208{
1209 RT_NOREF2(pAhci, iReg);
1210 ahciLog(("%s: read regSSTS=%#010x\n", __FUNCTION__, pAhciPort->regSSTS));
1211 ahciLog(("%s: IPM=%d SPD=%d DET=%d\n", __FUNCTION__,
1212 AHCI_PORT_SSTS_IPM_GET(pAhciPort->regSSTS), AHCI_PORT_SSTS_SPD_GET(pAhciPort->regSSTS),
1213 AHCI_PORT_SSTS_DET_GET(pAhciPort->regSSTS)));
1214
1215 *pu32Value = pAhciPort->regSSTS;
1216 return VINF_SUCCESS;
1217}
1218
1219static int PortSignature_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1220{
1221 RT_NOREF2(pAhci, iReg);
1222 ahciLog(("%s: read regSIG=%#010x\n", __FUNCTION__, pAhciPort->regSIG));
1223 *pu32Value = pAhciPort->regSIG;
1224 return VINF_SUCCESS;
1225}
1226
1227static int PortTaskFileData_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1228{
1229 RT_NOREF2(pAhci, iReg);
1230 ahciLog(("%s: read regTFD=%#010x\n", __FUNCTION__, pAhciPort->regTFD));
1231 ahciLog(("%s: ERR=%x BSY=%d DRQ=%d ERR=%d\n", __FUNCTION__,
1232 (pAhciPort->regTFD >> 8), (pAhciPort->regTFD & AHCI_PORT_TFD_BSY) >> 7,
1233 (pAhciPort->regTFD & AHCI_PORT_TFD_DRQ) >> 3, (pAhciPort->regTFD & AHCI_PORT_TFD_ERR)));
1234 *pu32Value = pAhciPort->regTFD;
1235 return VINF_SUCCESS;
1236}
1237
1238/**
1239 * Read from the port command register.
1240 */
1241static int PortCmd_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1242{
1243 RT_NOREF2(pAhci, iReg);
1244 ahciLog(("%s: read regCMD=%#010x\n", __FUNCTION__, pAhciPort->regCMD | AHCI_PORT_CMD_CCS_SHIFT(pAhciPort->u32CurrentCommandSlot)));
1245 ahciLog(("%s: ICC=%d ASP=%d ALPE=%d DLAE=%d ATAPI=%d CPD=%d ISP=%d HPCP=%d PMA=%d CPS=%d CR=%d FR=%d ISS=%d CCS=%d FRE=%d CLO=%d POD=%d SUD=%d ST=%d\n",
1246 __FUNCTION__, (pAhciPort->regCMD & AHCI_PORT_CMD_ICC) >> 28, (pAhciPort->regCMD & AHCI_PORT_CMD_ASP) >> 27,
1247 (pAhciPort->regCMD & AHCI_PORT_CMD_ALPE) >> 26, (pAhciPort->regCMD & AHCI_PORT_CMD_DLAE) >> 25,
1248 (pAhciPort->regCMD & AHCI_PORT_CMD_ATAPI) >> 24, (pAhciPort->regCMD & AHCI_PORT_CMD_CPD) >> 20,
1249 (pAhciPort->regCMD & AHCI_PORT_CMD_ISP) >> 19, (pAhciPort->regCMD & AHCI_PORT_CMD_HPCP) >> 18,
1250 (pAhciPort->regCMD & AHCI_PORT_CMD_PMA) >> 17, (pAhciPort->regCMD & AHCI_PORT_CMD_CPS) >> 16,
1251 (pAhciPort->regCMD & AHCI_PORT_CMD_CR) >> 15, (pAhciPort->regCMD & AHCI_PORT_CMD_FR) >> 14,
1252 (pAhciPort->regCMD & AHCI_PORT_CMD_ISS) >> 13, pAhciPort->u32CurrentCommandSlot,
1253 (pAhciPort->regCMD & AHCI_PORT_CMD_FRE) >> 4, (pAhciPort->regCMD & AHCI_PORT_CMD_CLO) >> 3,
1254 (pAhciPort->regCMD & AHCI_PORT_CMD_POD) >> 2, (pAhciPort->regCMD & AHCI_PORT_CMD_SUD) >> 1,
1255 (pAhciPort->regCMD & AHCI_PORT_CMD_ST)));
1256 *pu32Value = pAhciPort->regCMD | AHCI_PORT_CMD_CCS_SHIFT(pAhciPort->u32CurrentCommandSlot);
1257 return VINF_SUCCESS;
1258}
1259
1260/**
1261 * Write to the port command register.
1262 * This is the register where all the data transfer is started
1263 */
1264static int PortCmd_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1265{
1266 RT_NOREF1(iReg);
1267 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1268 ahciLog(("%s: ICC=%d ASP=%d ALPE=%d DLAE=%d ATAPI=%d CPD=%d ISP=%d HPCP=%d PMA=%d CPS=%d CR=%d FR=%d ISS=%d CCS=%d FRE=%d CLO=%d POD=%d SUD=%d ST=%d\n",
1269 __FUNCTION__, (u32Value & AHCI_PORT_CMD_ICC) >> 28, (u32Value & AHCI_PORT_CMD_ASP) >> 27,
1270 (u32Value & AHCI_PORT_CMD_ALPE) >> 26, (u32Value & AHCI_PORT_CMD_DLAE) >> 25,
1271 (u32Value & AHCI_PORT_CMD_ATAPI) >> 24, (u32Value & AHCI_PORT_CMD_CPD) >> 20,
1272 (u32Value & AHCI_PORT_CMD_ISP) >> 19, (u32Value & AHCI_PORT_CMD_HPCP) >> 18,
1273 (u32Value & AHCI_PORT_CMD_PMA) >> 17, (u32Value & AHCI_PORT_CMD_CPS) >> 16,
1274 (u32Value & AHCI_PORT_CMD_CR) >> 15, (u32Value & AHCI_PORT_CMD_FR) >> 14,
1275 (u32Value & AHCI_PORT_CMD_ISS) >> 13, (u32Value & AHCI_PORT_CMD_CCS) >> 8,
1276 (u32Value & AHCI_PORT_CMD_FRE) >> 4, (u32Value & AHCI_PORT_CMD_CLO) >> 3,
1277 (u32Value & AHCI_PORT_CMD_POD) >> 2, (u32Value & AHCI_PORT_CMD_SUD) >> 1,
1278 (u32Value & AHCI_PORT_CMD_ST)));
1279
1280 /* The PxCMD.CCS bits are R/O and maintained separately. */
1281 u32Value &= ~AHCI_PORT_CMD_CCS;
1282
1283 if (pAhciPort->fPoweredOn && pAhciPort->fSpunUp)
1284 {
1285 if (u32Value & AHCI_PORT_CMD_CLO)
1286 {
1287 ahciLog(("%s: Command list override requested\n", __FUNCTION__));
1288 u32Value &= ~(AHCI_PORT_TFD_BSY | AHCI_PORT_TFD_DRQ);
1289 /* Clear the CLO bit. */
1290 u32Value &= ~(AHCI_PORT_CMD_CLO);
1291 }
1292
1293 if (u32Value & AHCI_PORT_CMD_ST)
1294 {
1295 /*
1296 * Set engine state to running if there is a device attached and
1297 * IS.PCS is clear.
1298 */
1299 if ( pAhciPort->pDrvBase
1300 && !(pAhciPort->regIS & AHCI_PORT_IS_PCS))
1301 {
1302 ahciLog(("%s: Engine starts\n", __FUNCTION__));
1303 u32Value |= AHCI_PORT_CMD_CR;
1304
1305 /* If there is something in CI, kick the I/O thread. */
1306 if ( pAhciPort->regCI > 0
1307 && ASMAtomicReadBool(&pAhciPort->fWrkThreadSleeping))
1308 {
1309 ASMAtomicOrU32(&pAhciPort->u32TasksNew, pAhciPort->regCI);
1310#ifdef IN_RC
1311 PDEVPORTNOTIFIERQUEUEITEM pItem = (PDEVPORTNOTIFIERQUEUEITEM)PDMQueueAlloc(pAhci->CTX_SUFF(pNotifierQueue));
1312 AssertMsg(VALID_PTR(pItem), ("Allocating item for queue failed\n"));
1313
1314 pItem->iPort = pAhciPort->iLUN;
1315 PDMQueueInsert(pAhci->CTX_SUFF(pNotifierQueue), (PPDMQUEUEITEMCORE)pItem);
1316#else
1317 LogFlowFunc(("Signal event semaphore\n"));
1318 int rc = SUPSemEventSignal(pAhci->pSupDrvSession, pAhciPort->hEvtProcess);
1319 AssertRC(rc);
1320#endif
1321 }
1322 }
1323 else
1324 {
1325 if (!pAhciPort->pDrvBase)
1326 ahciLog(("%s: No pDrvBase, clearing PxCMD.CR!\n", __FUNCTION__));
1327 else
1328 ahciLog(("%s: PxIS.PCS set (PxIS=%#010x), clearing PxCMD.CR!\n", __FUNCTION__, pAhciPort->regIS));
1329
1330 u32Value &= ~AHCI_PORT_CMD_CR;
1331 }
1332 }
1333 else
1334 {
1335 ahciLog(("%s: Engine stops\n", __FUNCTION__));
1336 /* Clear command issue register. */
1337 pAhciPort->regCI = 0;
1338 pAhciPort->regSACT = 0;
1339 /* Clear current command slot. */
1340 pAhciPort->u32CurrentCommandSlot = 0;
1341 u32Value &= ~AHCI_PORT_CMD_CR;
1342 }
1343 }
1344 else if (pAhciPort->pDrvBase)
1345 {
1346 if ((u32Value & AHCI_PORT_CMD_POD) && (pAhciPort->regCMD & AHCI_PORT_CMD_CPS) && !pAhciPort->fPoweredOn)
1347 {
1348 ahciLog(("%s: Power on the device\n", __FUNCTION__));
1349 pAhciPort->fPoweredOn = true;
1350
1351 /*
1352 * Set states in the Port Signature and SStatus registers.
1353 */
1354 if (pAhciPort->fATAPI)
1355 pAhciPort->regSIG = AHCI_PORT_SIG_ATAPI;
1356 else
1357 pAhciPort->regSIG = AHCI_PORT_SIG_DISK;
1358 pAhciPort->regSSTS = (0x01 << 8) | /* Interface is active. */
1359 (0x02 << 4) | /* Generation 2 (3.0GBps) speed. */
1360 (0x03 << 0); /* Device detected and communication established. */
1361
1362 if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
1363 {
1364#ifndef IN_RING3
1365 return VINF_IOM_R3_MMIO_WRITE;
1366#else
1367 ahciPostFirstD2HFisIntoMemory(pAhciPort);
1368 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_DHRS);
1369
1370 if (pAhciPort->regIE & AHCI_PORT_IE_DHRE)
1371 {
1372 int rc = ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN, VERR_IGNORED);
1373 AssertRC(rc);
1374 }
1375#endif
1376 }
1377 }
1378
1379 if ((u32Value & AHCI_PORT_CMD_SUD) && pAhciPort->fPoweredOn && !pAhciPort->fSpunUp)
1380 {
1381 ahciLog(("%s: Spin up the device\n", __FUNCTION__));
1382 pAhciPort->fSpunUp = true;
1383 }
1384 }
1385 else
1386 ahciLog(("%s: No pDrvBase, no fPoweredOn + fSpunUp, doing nothing!\n", __FUNCTION__));
1387
1388 if (u32Value & AHCI_PORT_CMD_FRE)
1389 {
1390 ahciLog(("%s: FIS receive enabled\n", __FUNCTION__));
1391
1392 u32Value |= AHCI_PORT_CMD_FR;
1393
1394 /* Send the first D2H FIS only if it wasn't already sent. */
1395 if ( !pAhciPort->fFirstD2HFisSent
1396 && pAhciPort->pDrvBase)
1397 {
1398#ifndef IN_RING3
1399 return VINF_IOM_R3_MMIO_WRITE;
1400#else
1401 ahciPostFirstD2HFisIntoMemory(pAhciPort);
1402 pAhciPort->fFirstD2HFisSent = true;
1403#endif
1404 }
1405 }
1406 else if (!(u32Value & AHCI_PORT_CMD_FRE))
1407 {
1408 ahciLog(("%s: FIS receive disabled\n", __FUNCTION__));
1409 u32Value &= ~AHCI_PORT_CMD_FR;
1410 }
1411
1412 pAhciPort->regCMD = u32Value;
1413
1414 return VINF_SUCCESS;
1415}
1416
1417/**
1418 * Read from the port interrupt enable register.
1419 */
1420static int PortIntrEnable_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1421{
1422 RT_NOREF2(pAhci, iReg);
1423 ahciLog(("%s: read regIE=%#010x\n", __FUNCTION__, pAhciPort->regIE));
1424 ahciLog(("%s: CPDE=%d TFEE=%d HBFE=%d HBDE=%d IFE=%d INFE=%d OFE=%d IPME=%d PRCE=%d DIE=%d PCE=%d DPE=%d UFE=%d SDBE=%d DSE=%d PSE=%d DHRE=%d\n",
1425 __FUNCTION__, (pAhciPort->regIE & AHCI_PORT_IE_CPDE) >> 31, (pAhciPort->regIE & AHCI_PORT_IE_TFEE) >> 30,
1426 (pAhciPort->regIE & AHCI_PORT_IE_HBFE) >> 29, (pAhciPort->regIE & AHCI_PORT_IE_HBDE) >> 28,
1427 (pAhciPort->regIE & AHCI_PORT_IE_IFE) >> 27, (pAhciPort->regIE & AHCI_PORT_IE_INFE) >> 26,
1428 (pAhciPort->regIE & AHCI_PORT_IE_OFE) >> 24, (pAhciPort->regIE & AHCI_PORT_IE_IPME) >> 23,
1429 (pAhciPort->regIE & AHCI_PORT_IE_PRCE) >> 22, (pAhciPort->regIE & AHCI_PORT_IE_DIE) >> 7,
1430 (pAhciPort->regIE & AHCI_PORT_IE_PCE) >> 6, (pAhciPort->regIE & AHCI_PORT_IE_DPE) >> 5,
1431 (pAhciPort->regIE & AHCI_PORT_IE_UFE) >> 4, (pAhciPort->regIE & AHCI_PORT_IE_SDBE) >> 3,
1432 (pAhciPort->regIE & AHCI_PORT_IE_DSE) >> 2, (pAhciPort->regIE & AHCI_PORT_IE_PSE) >> 1,
1433 (pAhciPort->regIE & AHCI_PORT_IE_DHRE)));
1434 *pu32Value = pAhciPort->regIE;
1435 return VINF_SUCCESS;
1436}
1437
1438/**
1439 * Write to the port interrupt enable register.
1440 */
1441static int PortIntrEnable_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1442{
1443 RT_NOREF1(iReg);
1444 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1445 ahciLog(("%s: CPDE=%d TFEE=%d HBFE=%d HBDE=%d IFE=%d INFE=%d OFE=%d IPME=%d PRCE=%d DIE=%d PCE=%d DPE=%d UFE=%d SDBE=%d DSE=%d PSE=%d DHRE=%d\n",
1446 __FUNCTION__, (u32Value & AHCI_PORT_IE_CPDE) >> 31, (u32Value & AHCI_PORT_IE_TFEE) >> 30,
1447 (u32Value & AHCI_PORT_IE_HBFE) >> 29, (u32Value & AHCI_PORT_IE_HBDE) >> 28,
1448 (u32Value & AHCI_PORT_IE_IFE) >> 27, (u32Value & AHCI_PORT_IE_INFE) >> 26,
1449 (u32Value & AHCI_PORT_IE_OFE) >> 24, (u32Value & AHCI_PORT_IE_IPME) >> 23,
1450 (u32Value & AHCI_PORT_IE_PRCE) >> 22, (u32Value & AHCI_PORT_IE_DIE) >> 7,
1451 (u32Value & AHCI_PORT_IE_PCE) >> 6, (u32Value & AHCI_PORT_IE_DPE) >> 5,
1452 (u32Value & AHCI_PORT_IE_UFE) >> 4, (u32Value & AHCI_PORT_IE_SDBE) >> 3,
1453 (u32Value & AHCI_PORT_IE_DSE) >> 2, (u32Value & AHCI_PORT_IE_PSE) >> 1,
1454 (u32Value & AHCI_PORT_IE_DHRE)));
1455
1456 u32Value &= AHCI_PORT_IE_READONLY;
1457
1458 /* Check if some a interrupt status bit changed*/
1459 uint32_t u32IntrStatus = ASMAtomicReadU32(&pAhciPort->regIS);
1460
1461 int rc = VINF_SUCCESS;
1462 if (u32Value & u32IntrStatus)
1463 rc = ahciHbaSetInterrupt(pAhci, pAhciPort->iLUN, VINF_IOM_R3_MMIO_WRITE);
1464
1465 if (rc == VINF_SUCCESS)
1466 pAhciPort->regIE = u32Value;
1467
1468 return rc;
1469}
1470
1471/**
1472 * Read from the port interrupt status register.
1473 */
1474static int PortIntrSts_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1475{
1476 RT_NOREF2(pAhci, iReg);
1477 ahciLog(("%s: read regIS=%#010x\n", __FUNCTION__, pAhciPort->regIS));
1478 ahciLog(("%s: CPDS=%d TFES=%d HBFS=%d HBDS=%d IFS=%d INFS=%d OFS=%d IPMS=%d PRCS=%d DIS=%d PCS=%d DPS=%d UFS=%d SDBS=%d DSS=%d PSS=%d DHRS=%d\n",
1479 __FUNCTION__, (pAhciPort->regIS & AHCI_PORT_IS_CPDS) >> 31, (pAhciPort->regIS & AHCI_PORT_IS_TFES) >> 30,
1480 (pAhciPort->regIS & AHCI_PORT_IS_HBFS) >> 29, (pAhciPort->regIS & AHCI_PORT_IS_HBDS) >> 28,
1481 (pAhciPort->regIS & AHCI_PORT_IS_IFS) >> 27, (pAhciPort->regIS & AHCI_PORT_IS_INFS) >> 26,
1482 (pAhciPort->regIS & AHCI_PORT_IS_OFS) >> 24, (pAhciPort->regIS & AHCI_PORT_IS_IPMS) >> 23,
1483 (pAhciPort->regIS & AHCI_PORT_IS_PRCS) >> 22, (pAhciPort->regIS & AHCI_PORT_IS_DIS) >> 7,
1484 (pAhciPort->regIS & AHCI_PORT_IS_PCS) >> 6, (pAhciPort->regIS & AHCI_PORT_IS_DPS) >> 5,
1485 (pAhciPort->regIS & AHCI_PORT_IS_UFS) >> 4, (pAhciPort->regIS & AHCI_PORT_IS_SDBS) >> 3,
1486 (pAhciPort->regIS & AHCI_PORT_IS_DSS) >> 2, (pAhciPort->regIS & AHCI_PORT_IS_PSS) >> 1,
1487 (pAhciPort->regIS & AHCI_PORT_IS_DHRS)));
1488 *pu32Value = pAhciPort->regIS;
1489 return VINF_SUCCESS;
1490}
1491
1492/**
1493 * Write to the port interrupt status register.
1494 */
1495static int PortIntrSts_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1496{
1497 RT_NOREF2(pAhci, iReg);
1498 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1499 ASMAtomicAndU32(&pAhciPort->regIS, ~(u32Value & AHCI_PORT_IS_READONLY));
1500
1501 return VINF_SUCCESS;
1502}
1503
1504/**
1505 * Read from the port FIS base address upper 32bit register.
1506 */
1507static int PortFisAddrUp_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1508{
1509 RT_NOREF2(pAhci, iReg);
1510 ahciLog(("%s: read regFBU=%#010x\n", __FUNCTION__, pAhciPort->regFBU));
1511 *pu32Value = pAhciPort->regFBU;
1512 return VINF_SUCCESS;
1513}
1514
1515/**
1516 * Write to the port FIS base address upper 32bit register.
1517 */
1518static int PortFisAddrUp_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1519{
1520 RT_NOREF2(pAhci, iReg);
1521 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1522
1523 pAhciPort->regFBU = u32Value;
1524 pAhciPort->GCPhysAddrFb = AHCI_RTGCPHYS_FROM_U32(pAhciPort->regFBU, pAhciPort->regFB);
1525
1526 return VINF_SUCCESS;
1527}
1528
1529/**
1530 * Read from the port FIS base address register.
1531 */
1532static int PortFisAddr_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1533{
1534 RT_NOREF2(pAhci, iReg);
1535 ahciLog(("%s: read regFB=%#010x\n", __FUNCTION__, pAhciPort->regFB));
1536 *pu32Value = pAhciPort->regFB;
1537 return VINF_SUCCESS;
1538}
1539
1540/**
1541 * Write to the port FIS base address register.
1542 */
1543static int PortFisAddr_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1544{
1545 RT_NOREF2(pAhci, iReg);
1546 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1547
1548 Assert(!(u32Value & ~AHCI_PORT_FB_RESERVED));
1549
1550 pAhciPort->regFB = (u32Value & AHCI_PORT_FB_RESERVED);
1551 pAhciPort->GCPhysAddrFb = AHCI_RTGCPHYS_FROM_U32(pAhciPort->regFBU, pAhciPort->regFB);
1552
1553 return VINF_SUCCESS;
1554}
1555
1556/**
1557 * Write to the port command list base address upper 32bit register.
1558 */
1559static int PortCmdLstAddrUp_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1560{
1561 RT_NOREF2(pAhci, iReg);
1562 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1563
1564 pAhciPort->regCLBU = u32Value;
1565 pAhciPort->GCPhysAddrClb = AHCI_RTGCPHYS_FROM_U32(pAhciPort->regCLBU, pAhciPort->regCLB);
1566
1567 return VINF_SUCCESS;
1568}
1569
1570/**
1571 * Read from the port command list base address upper 32bit register.
1572 */
1573static int PortCmdLstAddrUp_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1574{
1575 RT_NOREF2(pAhci, iReg);
1576 ahciLog(("%s: read regCLBU=%#010x\n", __FUNCTION__, pAhciPort->regCLBU));
1577 *pu32Value = pAhciPort->regCLBU;
1578 return VINF_SUCCESS;
1579}
1580
1581/**
1582 * Read from the port command list base address register.
1583 */
1584static int PortCmdLstAddr_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1585{
1586 RT_NOREF2(pAhci, iReg);
1587 ahciLog(("%s: read regCLB=%#010x\n", __FUNCTION__, pAhciPort->regCLB));
1588 *pu32Value = pAhciPort->regCLB;
1589 return VINF_SUCCESS;
1590}
1591
1592/**
1593 * Write to the port command list base address register.
1594 */
1595static int PortCmdLstAddr_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1596{
1597 RT_NOREF2(pAhci, iReg);
1598 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1599
1600 Assert(!(u32Value & ~AHCI_PORT_CLB_RESERVED));
1601
1602 pAhciPort->regCLB = (u32Value & AHCI_PORT_CLB_RESERVED);
1603 pAhciPort->GCPhysAddrClb = AHCI_RTGCPHYS_FROM_U32(pAhciPort->regCLBU, pAhciPort->regCLB);
1604
1605 return VINF_SUCCESS;
1606}
1607
1608/**
1609 * Read from the global Version register.
1610 */
1611static int HbaVersion_r(PAHCI pAhci, uint32_t iReg, uint32_t *pu32Value)
1612{
1613 RT_NOREF1(iReg);
1614 Log(("%s: read regHbaVs=%#010x\n", __FUNCTION__, pAhci->regHbaVs));
1615 *pu32Value = pAhci->regHbaVs;
1616 return VINF_SUCCESS;
1617}
1618
1619/**
1620 * Read from the global Ports implemented register.
1621 */
1622static int HbaPortsImplemented_r(PAHCI pAhci, uint32_t iReg, uint32_t *pu32Value)
1623{
1624 RT_NOREF1(iReg);
1625 Log(("%s: read regHbaPi=%#010x\n", __FUNCTION__, pAhci->regHbaPi));
1626 *pu32Value = pAhci->regHbaPi;
1627 return VINF_SUCCESS;
1628}
1629
1630/**
1631 * Write to the global interrupt status register.
1632 */
1633static int HbaInterruptStatus_w(PAHCI pAhci, uint32_t iReg, uint32_t u32Value)
1634{
1635 RT_NOREF1(iReg);
1636 Log(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1637
1638 int rc = PDMCritSectEnter(&pAhci->lock, VINF_IOM_R3_MMIO_WRITE);
1639 if (rc != VINF_SUCCESS)
1640 return rc;
1641
1642 pAhci->regHbaIs &= ~(u32Value);
1643
1644 /*
1645 * Update interrupt status register and check for ports who
1646 * set the interrupt inbetween.
1647 */
1648 bool fClear = true;
1649 pAhci->regHbaIs |= ASMAtomicXchgU32(&pAhci->u32PortsInterrupted, 0);
1650 if (!pAhci->regHbaIs)
1651 {
1652 unsigned i = 0;
1653
1654 /* Check if the cleared ports have a interrupt status bit set. */
1655 while ((u32Value > 0) && (i < AHCI_MAX_NR_PORTS_IMPL))
1656 {
1657 if (u32Value & 0x01)
1658 {
1659 PAHCIPort pAhciPort = &pAhci->ahciPort[i];
1660
1661 if (pAhciPort->regIE & pAhciPort->regIS)
1662 {
1663 Log(("%s: Interrupt status of port %u set -> Set interrupt again\n", __FUNCTION__, i));
1664 ASMAtomicOrU32(&pAhci->u32PortsInterrupted, 1 << i);
1665 fClear = false;
1666 break;
1667 }
1668 }
1669 u32Value >>= 1;
1670 i++;
1671 }
1672 }
1673 else
1674 fClear = false;
1675
1676 if (fClear)
1677 ahciHbaClearInterrupt(pAhci);
1678 else
1679 {
1680 Log(("%s: Not clearing interrupt: u32PortsInterrupted=%#010x\n", __FUNCTION__, pAhci->u32PortsInterrupted));
1681 /*
1682 * We need to set the interrupt again because the I/O APIC does not set it again even if the
1683 * line is still high.
1684 * We need to clear it first because the PCI bus only calls the interrupt controller if the state changes.
1685 */
1686 PDMDevHlpPCISetIrq(pAhci->CTX_SUFF(pDevIns), 0, 0);
1687 PDMDevHlpPCISetIrq(pAhci->CTX_SUFF(pDevIns), 0, 1);
1688 }
1689
1690 PDMCritSectLeave(&pAhci->lock);
1691 return VINF_SUCCESS;
1692}
1693
1694/**
1695 * Read from the global interrupt status register.
1696 */
1697static int HbaInterruptStatus_r(PAHCI pAhci, uint32_t iReg, uint32_t *pu32Value)
1698{
1699 RT_NOREF1(iReg);
1700
1701 int rc = PDMCritSectEnter(&pAhci->lock, VINF_IOM_R3_MMIO_READ);
1702 if (rc != VINF_SUCCESS)
1703 return rc;
1704
1705 uint32_t u32PortsInterrupted = ASMAtomicXchgU32(&pAhci->u32PortsInterrupted, 0);
1706
1707 PDMCritSectLeave(&pAhci->lock);
1708 Log(("%s: read regHbaIs=%#010x u32PortsInterrupted=%#010x\n", __FUNCTION__, pAhci->regHbaIs, u32PortsInterrupted));
1709
1710 pAhci->regHbaIs |= u32PortsInterrupted;
1711
1712#ifdef LOG_ENABLED
1713 Log(("%s:", __FUNCTION__));
1714 unsigned i;
1715 for (i = 0; i < pAhci->cPortsImpl; i++)
1716 {
1717 if ((pAhci->regHbaIs >> i) & 0x01)
1718 Log((" P%d", i));
1719 }
1720 Log(("\n"));
1721#endif
1722
1723 *pu32Value = pAhci->regHbaIs;
1724
1725 return VINF_SUCCESS;
1726}
1727
1728/**
1729 * Write to the global control register.
1730 */
1731static int HbaControl_w(PAHCI pAhci, uint32_t iReg, uint32_t u32Value)
1732{
1733 RT_NOREF1(iReg);
1734 Log(("%s: write u32Value=%#010x\n"
1735 "%s: AE=%d IE=%d HR=%d\n",
1736 __FUNCTION__, u32Value,
1737 __FUNCTION__, (u32Value & AHCI_HBA_CTRL_AE) >> 31, (u32Value & AHCI_HBA_CTRL_IE) >> 1,
1738 (u32Value & AHCI_HBA_CTRL_HR)));
1739
1740#ifndef IN_RING3
1741 RT_NOREF2(pAhci, u32Value);
1742 return VINF_IOM_R3_MMIO_WRITE;
1743#else
1744 /*
1745 * Increase the active thread counter because we might set the host controller
1746 * reset bit.
1747 */
1748 ASMAtomicIncU32(&pAhci->cThreadsActive);
1749 ASMAtomicWriteU32(&pAhci->regHbaCtrl, (u32Value & AHCI_HBA_CTRL_RW_MASK) | AHCI_HBA_CTRL_AE);
1750
1751 /*
1752 * Do the HBA reset if requested and there is no other active thread at the moment,
1753 * the work is deferred to the last active thread otherwise.
1754 */
1755 uint32_t cThreadsActive = ASMAtomicDecU32(&pAhci->cThreadsActive);
1756 if ( (u32Value & AHCI_HBA_CTRL_HR)
1757 && !cThreadsActive)
1758 ahciHBAReset(pAhci);
1759
1760 return VINF_SUCCESS;
1761#endif
1762}
1763
1764/**
1765 * Read the global control register.
1766 */
1767static int HbaControl_r(PAHCI pAhci, uint32_t iReg, uint32_t *pu32Value)
1768{
1769 RT_NOREF1(iReg);
1770 Log(("%s: read regHbaCtrl=%#010x\n"
1771 "%s: AE=%d IE=%d HR=%d\n",
1772 __FUNCTION__, pAhci->regHbaCtrl,
1773 __FUNCTION__, (pAhci->regHbaCtrl & AHCI_HBA_CTRL_AE) >> 31, (pAhci->regHbaCtrl & AHCI_HBA_CTRL_IE) >> 1,
1774 (pAhci->regHbaCtrl & AHCI_HBA_CTRL_HR)));
1775 *pu32Value = pAhci->regHbaCtrl;
1776 return VINF_SUCCESS;
1777}
1778
1779/**
1780 * Read the global capabilities register.
1781 */
1782static int HbaCapabilities_r(PAHCI pAhci, uint32_t iReg, uint32_t *pu32Value)
1783{
1784 RT_NOREF1(iReg);
1785 Log(("%s: read regHbaCap=%#010x\n"
1786 "%s: S64A=%d SNCQ=%d SIS=%d SSS=%d SALP=%d SAL=%d SCLO=%d ISS=%d SNZO=%d SAM=%d SPM=%d PMD=%d SSC=%d PSC=%d NCS=%d NP=%d\n",
1787 __FUNCTION__, pAhci->regHbaCap,
1788 __FUNCTION__, (pAhci->regHbaCap & AHCI_HBA_CAP_S64A) >> 31, (pAhci->regHbaCap & AHCI_HBA_CAP_SNCQ) >> 30,
1789 (pAhci->regHbaCap & AHCI_HBA_CAP_SIS) >> 28, (pAhci->regHbaCap & AHCI_HBA_CAP_SSS) >> 27,
1790 (pAhci->regHbaCap & AHCI_HBA_CAP_SALP) >> 26, (pAhci->regHbaCap & AHCI_HBA_CAP_SAL) >> 25,
1791 (pAhci->regHbaCap & AHCI_HBA_CAP_SCLO) >> 24, (pAhci->regHbaCap & AHCI_HBA_CAP_ISS) >> 20,
1792 (pAhci->regHbaCap & AHCI_HBA_CAP_SNZO) >> 19, (pAhci->regHbaCap & AHCI_HBA_CAP_SAM) >> 18,
1793 (pAhci->regHbaCap & AHCI_HBA_CAP_SPM) >> 17, (pAhci->regHbaCap & AHCI_HBA_CAP_PMD) >> 15,
1794 (pAhci->regHbaCap & AHCI_HBA_CAP_SSC) >> 14, (pAhci->regHbaCap & AHCI_HBA_CAP_PSC) >> 13,
1795 (pAhci->regHbaCap & AHCI_HBA_CAP_NCS) >> 8, (pAhci->regHbaCap & AHCI_HBA_CAP_NP)));
1796 *pu32Value = pAhci->regHbaCap;
1797 return VINF_SUCCESS;
1798}
1799
1800/**
1801 * Write to the global command completion coalescing control register.
1802 */
1803static int HbaCccCtl_w(PAHCI pAhci, uint32_t iReg, uint32_t u32Value)
1804{
1805 RT_NOREF1(iReg);
1806 Log(("%s: write u32Value=%#010x\n"
1807 "%s: TV=%d CC=%d INT=%d EN=%d\n",
1808 __FUNCTION__, u32Value,
1809 __FUNCTION__, AHCI_HBA_CCC_CTL_TV_GET(u32Value), AHCI_HBA_CCC_CTL_CC_GET(u32Value),
1810 AHCI_HBA_CCC_CTL_INT_GET(u32Value), (u32Value & AHCI_HBA_CCC_CTL_EN)));
1811
1812 pAhci->regHbaCccCtl = u32Value;
1813 pAhci->uCccTimeout = AHCI_HBA_CCC_CTL_TV_GET(u32Value);
1814 pAhci->uCccPortNr = AHCI_HBA_CCC_CTL_INT_GET(u32Value);
1815 pAhci->uCccNr = AHCI_HBA_CCC_CTL_CC_GET(u32Value);
1816
1817 if (u32Value & AHCI_HBA_CCC_CTL_EN)
1818 TMTimerSetMillies(pAhci->CTX_SUFF(pHbaCccTimer), pAhci->uCccTimeout); /* Arm the timer */
1819 else
1820 TMTimerStop(pAhci->CTX_SUFF(pHbaCccTimer));
1821
1822 return VINF_SUCCESS;
1823}
1824
1825/**
1826 * Read the global command completion coalescing control register.
1827 */
1828static int HbaCccCtl_r(PAHCI pAhci, uint32_t iReg, uint32_t *pu32Value)
1829{
1830 RT_NOREF1(iReg);
1831 Log(("%s: read regHbaCccCtl=%#010x\n"
1832 "%s: TV=%d CC=%d INT=%d EN=%d\n",
1833 __FUNCTION__, pAhci->regHbaCccCtl,
1834 __FUNCTION__, AHCI_HBA_CCC_CTL_TV_GET(pAhci->regHbaCccCtl), AHCI_HBA_CCC_CTL_CC_GET(pAhci->regHbaCccCtl),
1835 AHCI_HBA_CCC_CTL_INT_GET(pAhci->regHbaCccCtl), (pAhci->regHbaCccCtl & AHCI_HBA_CCC_CTL_EN)));
1836 *pu32Value = pAhci->regHbaCccCtl;
1837 return VINF_SUCCESS;
1838}
1839
1840/**
1841 * Write to the global command completion coalescing ports register.
1842 */
1843static int HbaCccPorts_w(PAHCI pAhci, uint32_t iReg, uint32_t u32Value)
1844{
1845 RT_NOREF1(iReg);
1846 Log(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1847
1848 pAhci->regHbaCccPorts = u32Value;
1849
1850 return VINF_SUCCESS;
1851}
1852
1853/**
1854 * Read the global command completion coalescing ports register.
1855 */
1856static int HbaCccPorts_r(PAHCI pAhci, uint32_t iReg, uint32_t *pu32Value)
1857{
1858 RT_NOREF1(iReg);
1859 Log(("%s: read regHbaCccPorts=%#010x\n", __FUNCTION__, pAhci->regHbaCccPorts));
1860
1861#ifdef LOG_ENABLED
1862 Log(("%s:", __FUNCTION__));
1863 unsigned i;
1864 for (i = 0; i < pAhci->cPortsImpl; i++)
1865 {
1866 if ((pAhci->regHbaCccPorts >> i) & 0x01)
1867 Log((" P%d", i));
1868 }
1869 Log(("\n"));
1870#endif
1871
1872 *pu32Value = pAhci->regHbaCccPorts;
1873 return VINF_SUCCESS;
1874}
1875
1876/**
1877 * Invalid write to global register
1878 */
1879static int HbaInvalid_w(PAHCI pAhci, uint32_t iReg, uint32_t u32Value)
1880{
1881 RT_NOREF3(pAhci, iReg, u32Value);
1882 Log(("%s: Write denied!!! iReg=%u u32Value=%#010x\n", __FUNCTION__, iReg, u32Value));
1883 return VINF_SUCCESS;
1884}
1885
1886/**
1887 * Invalid Port write.
1888 */
1889static int PortInvalid_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1890{
1891 RT_NOREF4(pAhci, pAhciPort, iReg, u32Value);
1892 ahciLog(("%s: Write denied!!! iReg=%u u32Value=%#010x\n", __FUNCTION__, iReg, u32Value));
1893 return VINF_SUCCESS;
1894}
1895
1896/**
1897 * Invalid Port read.
1898 */
1899static int PortInvalid_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1900{
1901 RT_NOREF4(pAhci, pAhciPort, iReg, pu32Value);
1902 ahciLog(("%s: Read denied!!! iReg=%u\n", __FUNCTION__, iReg));
1903 return VINF_SUCCESS;
1904}
1905
1906/**
1907 * Register descriptor table for global HBA registers
1908 */
1909static const AHCIOPREG g_aOpRegs[] =
1910{
1911 {"HbaCapabilites", HbaCapabilities_r, HbaInvalid_w}, /* Readonly */
1912 {"HbaControl" , HbaControl_r, HbaControl_w},
1913 {"HbaInterruptStatus", HbaInterruptStatus_r, HbaInterruptStatus_w},
1914 {"HbaPortsImplemented", HbaPortsImplemented_r, HbaInvalid_w}, /* Readonly */
1915 {"HbaVersion", HbaVersion_r, HbaInvalid_w}, /* ReadOnly */
1916 {"HbaCccCtl", HbaCccCtl_r, HbaCccCtl_w},
1917 {"HbaCccPorts", HbaCccPorts_r, HbaCccPorts_w},
1918};
1919
1920/**
1921 * Register descriptor table for port registers
1922 */
1923static const AHCIPORTOPREG g_aPortOpRegs[] =
1924{
1925 {"PortCmdLstAddr", PortCmdLstAddr_r, PortCmdLstAddr_w},
1926 {"PortCmdLstAddrUp", PortCmdLstAddrUp_r, PortCmdLstAddrUp_w},
1927 {"PortFisAddr", PortFisAddr_r, PortFisAddr_w},
1928 {"PortFisAddrUp", PortFisAddrUp_r, PortFisAddrUp_w},
1929 {"PortIntrSts", PortIntrSts_r, PortIntrSts_w},
1930 {"PortIntrEnable", PortIntrEnable_r, PortIntrEnable_w},
1931 {"PortCmd", PortCmd_r, PortCmd_w},
1932 {"PortReserved1", PortInvalid_r, PortInvalid_w}, /* Not used. */
1933 {"PortTaskFileData", PortTaskFileData_r, PortInvalid_w}, /* Readonly */
1934 {"PortSignature", PortSignature_r, PortInvalid_w}, /* Readonly */
1935 {"PortSStatus", PortSStatus_r, PortInvalid_w}, /* Readonly */
1936 {"PortSControl", PortSControl_r, PortSControl_w},
1937 {"PortSError", PortSError_r, PortSError_w},
1938 {"PortSActive", PortSActive_r, PortSActive_w},
1939 {"PortCmdIssue", PortCmdIssue_r, PortCmdIssue_w},
1940 {"PortReserved2", PortInvalid_r, PortInvalid_w}, /* Not used. */
1941};
1942
1943#ifdef IN_RING3
1944/**
1945 * Reset initiated by system software for one port.
1946 *
1947 * @param pAhciPort The port to reset.
1948 */
1949static void ahciPortSwReset(PAHCIPort pAhciPort)
1950{
1951 bool fAllTasksCanceled;
1952
1953 /* Cancel all tasks first. */
1954 fAllTasksCanceled = ahciCancelActiveTasks(pAhciPort);
1955 Assert(fAllTasksCanceled);
1956
1957 Assert(pAhciPort->cTasksActive == 0);
1958
1959 pAhciPort->regIS = 0;
1960 pAhciPort->regIE = 0;
1961 pAhciPort->regCMD = AHCI_PORT_CMD_CPD | /* Cold presence detection */
1962 AHCI_PORT_CMD_SUD | /* Device has spun up. */
1963 AHCI_PORT_CMD_POD; /* Port is powered on. */
1964
1965 /* Hotplugging supported?. */
1966 if (pAhciPort->fHotpluggable)
1967 pAhciPort->regCMD |= AHCI_PORT_CMD_HPCP;
1968
1969 pAhciPort->regTFD = (1 << 8) | ATA_STAT_SEEK | ATA_STAT_WRERR;
1970 pAhciPort->regSIG = UINT32_MAX;
1971 pAhciPort->regSSTS = 0;
1972 pAhciPort->regSCTL = 0;
1973 pAhciPort->regSERR = 0;
1974 pAhciPort->regSACT = 0;
1975 pAhciPort->regCI = 0;
1976
1977 pAhciPort->fResetDevice = false;
1978 pAhciPort->fPoweredOn = true;
1979 pAhciPort->fSpunUp = true;
1980 pAhciPort->cMultSectors = ATA_MAX_MULT_SECTORS;
1981 pAhciPort->uATATransferMode = ATA_MODE_UDMA | 6;
1982
1983 pAhciPort->u32TasksNew = 0;
1984 pAhciPort->u32TasksRedo = 0;
1985 pAhciPort->u32TasksFinished = 0;
1986 pAhciPort->u32QueuedTasksFinished = 0;
1987 pAhciPort->u32CurrentCommandSlot = 0;
1988
1989 if (pAhciPort->pDrvBase)
1990 {
1991 pAhciPort->regCMD |= AHCI_PORT_CMD_CPS; /* Indicate that there is a device on that port */
1992
1993 if (pAhciPort->fPoweredOn)
1994 {
1995 /*
1996 * Set states in the Port Signature and SStatus registers.
1997 */
1998 if (pAhciPort->fATAPI)
1999 pAhciPort->regSIG = AHCI_PORT_SIG_ATAPI;
2000 else
2001 pAhciPort->regSIG = AHCI_PORT_SIG_DISK;
2002 pAhciPort->regSSTS = (0x01 << 8) | /* Interface is active. */
2003 (0x02 << 4) | /* Generation 2 (3.0GBps) speed. */
2004 (0x03 << 0); /* Device detected and communication established. */
2005 }
2006 }
2007}
2008
2009/**
2010 * Hardware reset used for machine power on and reset.
2011 *
2012 * @param pAhciPort The port to reset.
2013 */
2014static void ahciPortHwReset(PAHCIPort pAhciPort)
2015{
2016 /* Reset the address registers. */
2017 pAhciPort->regCLB = 0;
2018 pAhciPort->regCLBU = 0;
2019 pAhciPort->regFB = 0;
2020 pAhciPort->regFBU = 0;
2021
2022 /* Reset calculated addresses. */
2023 pAhciPort->GCPhysAddrClb = 0;
2024 pAhciPort->GCPhysAddrFb = 0;
2025}
2026
2027/**
2028 * Create implemented ports bitmap.
2029 *
2030 * @returns 32bit bitmask with a bit set for every implemented port.
2031 * @param cPorts Number of ports.
2032 */
2033static uint32_t ahciGetPortsImplemented(unsigned cPorts)
2034{
2035 uint32_t uPortsImplemented = 0;
2036
2037 for (unsigned i = 0; i < cPorts; i++)
2038 uPortsImplemented |= (1 << i);
2039
2040 return uPortsImplemented;
2041}
2042
2043/**
2044 * Reset the entire HBA.
2045 *
2046 * @param pThis The HBA state.
2047 */
2048static void ahciHBAReset(PAHCI pThis)
2049{
2050 unsigned i;
2051 int rc = VINF_SUCCESS;
2052
2053 LogRel(("AHCI#%u: Reset the HBA\n", pThis->CTX_SUFF(pDevIns)->iInstance));
2054
2055 /* Stop the CCC timer. */
2056 if (pThis->regHbaCccCtl & AHCI_HBA_CCC_CTL_EN)
2057 {
2058 rc = TMTimerStop(pThis->CTX_SUFF(pHbaCccTimer));
2059 if (RT_FAILURE(rc))
2060 AssertMsgFailed(("%s: Failed to stop timer!\n", __FUNCTION__));
2061 }
2062
2063 /* Reset every port */
2064 for (i = 0; i < pThis->cPortsImpl; i++)
2065 {
2066 PAHCIPort pAhciPort = &pThis->ahciPort[i];
2067
2068 pAhciPort->iLUN = i;
2069 ahciPortSwReset(pAhciPort);
2070 }
2071
2072 /* Init Global registers */
2073 pThis->regHbaCap = AHCI_HBA_CAP_ISS_SHIFT(AHCI_HBA_CAP_ISS_GEN2) |
2074 AHCI_HBA_CAP_S64A | /* 64bit addressing supported */
2075 AHCI_HBA_CAP_SAM | /* AHCI mode only */
2076 AHCI_HBA_CAP_SNCQ | /* Support native command queuing */
2077 AHCI_HBA_CAP_SSS | /* Staggered spin up */
2078 AHCI_HBA_CAP_CCCS | /* Support command completion coalescing */
2079 AHCI_HBA_CAP_NCS_SET(pThis->cCmdSlotsAvail) | /* Number of command slots we support */
2080 AHCI_HBA_CAP_NP_SET(pThis->cPortsImpl); /* Number of supported ports */
2081 pThis->regHbaCtrl = AHCI_HBA_CTRL_AE;
2082 pThis->regHbaPi = ahciGetPortsImplemented(pThis->cPortsImpl);
2083 pThis->regHbaVs = AHCI_HBA_VS_MJR | AHCI_HBA_VS_MNR;
2084 pThis->regHbaCccCtl = 0;
2085 pThis->regHbaCccPorts = 0;
2086 pThis->uCccTimeout = 0;
2087 pThis->uCccPortNr = 0;
2088 pThis->uCccNr = 0;
2089
2090 /* Clear pending interrupts. */
2091 pThis->regHbaIs = 0;
2092 pThis->u32PortsInterrupted = 0;
2093 ahciHbaClearInterrupt(pThis);
2094
2095 pThis->f64BitAddr = false;
2096 pThis->u32PortsInterrupted = 0;
2097 pThis->f8ByteMMIO4BytesWrittenSuccessfully = false;
2098 /* Clear the HBA Reset bit */
2099 pThis->regHbaCtrl &= ~AHCI_HBA_CTRL_HR;
2100}
2101#endif
2102
2103/**
2104 * Reads from a AHCI controller register.
2105 *
2106 * @returns VBox status code.
2107 *
2108 * @param pAhci The AHCI instance.
2109 * @param uReg The register to write.
2110 * @param pv Where to store the result.
2111 * @param cb Number of bytes read.
2112 */
2113static int ahciRegisterRead(PAHCI pAhci, uint32_t uReg, void *pv, unsigned cb)
2114{
2115 int rc = VINF_SUCCESS;
2116 uint32_t iReg;
2117
2118 /*
2119 * If the access offset is smaller than AHCI_HBA_GLOBAL_SIZE the guest accesses the global registers.
2120 * Otherwise it accesses the registers of a port.
2121 */
2122 if (uReg < AHCI_HBA_GLOBAL_SIZE)
2123 {
2124 iReg = uReg >> 2;
2125 Log3(("%s: Trying to read from global register %u\n", __FUNCTION__, iReg));
2126 if (iReg < RT_ELEMENTS(g_aOpRegs))
2127 {
2128 const AHCIOPREG *pReg = &g_aOpRegs[iReg];
2129 rc = pReg->pfnRead(pAhci, iReg, (uint32_t *)pv);
2130 }
2131 else
2132 {
2133 Log3(("%s: Trying to read global register %u/%u!!!\n", __FUNCTION__, iReg, RT_ELEMENTS(g_aOpRegs)));
2134 *(uint32_t *)pv = 0;
2135 }
2136 }
2137 else
2138 {
2139 uint32_t iRegOffset;
2140 uint32_t iPort;
2141
2142 /* Calculate accessed port. */
2143 uReg -= AHCI_HBA_GLOBAL_SIZE;
2144 iPort = uReg / AHCI_PORT_REGISTER_SIZE;
2145 iRegOffset = (uReg % AHCI_PORT_REGISTER_SIZE);
2146 iReg = iRegOffset >> 2;
2147
2148 Log3(("%s: Trying to read from port %u and register %u\n", __FUNCTION__, iPort, iReg));
2149
2150 if (RT_LIKELY( iPort < pAhci->cPortsImpl
2151 && iReg < RT_ELEMENTS(g_aPortOpRegs)))
2152 {
2153 const AHCIPORTOPREG *pPortReg = &g_aPortOpRegs[iReg];
2154 rc = pPortReg->pfnRead(pAhci, &pAhci->ahciPort[iPort], iReg, (uint32_t *)pv);
2155 }
2156 else
2157 {
2158 Log3(("%s: Trying to read port %u register %u/%u!!!\n", __FUNCTION__, iPort, iReg, RT_ELEMENTS(g_aPortOpRegs)));
2159 rc = VINF_IOM_MMIO_UNUSED_00;
2160 }
2161
2162 /*
2163 * Windows Vista tries to read one byte from some registers instead of four.
2164 * Correct the value according to the read size.
2165 */
2166 if (RT_SUCCESS(rc) && cb != sizeof(uint32_t))
2167 {
2168 switch (cb)
2169 {
2170 case 1:
2171 {
2172 uint8_t uNewValue;
2173 uint8_t *p = (uint8_t *)pv;
2174
2175 iRegOffset &= 3;
2176 Log3(("%s: iRegOffset=%u\n", __FUNCTION__, iRegOffset));
2177 uNewValue = p[iRegOffset];
2178 /* Clear old value */
2179 *(uint32_t *)pv = 0;
2180 *(uint8_t *)pv = uNewValue;
2181 break;
2182 }
2183 default:
2184 AssertMsgFailed(("%s: unsupported access width cb=%d iPort=%x iRegOffset=%x iReg=%x!!!\n",
2185 __FUNCTION__, cb, iPort, iRegOffset, iReg));
2186 }
2187 }
2188 }
2189
2190 return rc;
2191}
2192
2193/**
2194 * Writes a value to one of the AHCI controller registers.
2195 *
2196 * @returns VBox status code.
2197 *
2198 * @param pAhci The AHCI instance.
2199 * @param offReg The offset of the register to write to.
2200 * @param u32Value The value to write.
2201 */
2202static int ahciRegisterWrite(PAHCI pAhci, uint32_t offReg, uint32_t u32Value)
2203{
2204 int rc;
2205 uint32_t iReg;
2206
2207 /*
2208 * If the access offset is smaller than 100h the guest accesses the global registers.
2209 * Otherwise it accesses the registers of a port.
2210 */
2211 if (offReg < AHCI_HBA_GLOBAL_SIZE)
2212 {
2213 Log3(("Write global HBA register\n"));
2214 iReg = offReg >> 2;
2215 if (iReg < RT_ELEMENTS(g_aOpRegs))
2216 {
2217 const AHCIOPREG *pReg = &g_aOpRegs[iReg];
2218 rc = pReg->pfnWrite(pAhci, iReg, u32Value);
2219 }
2220 else
2221 {
2222 Log3(("%s: Trying to write global register %u/%u!!!\n", __FUNCTION__, iReg, RT_ELEMENTS(g_aOpRegs)));
2223 rc = VINF_SUCCESS;
2224 }
2225 }
2226 else
2227 {
2228 uint32_t iPort;
2229 Log3(("Write Port register\n"));
2230 /* Calculate accessed port. */
2231 offReg -= AHCI_HBA_GLOBAL_SIZE;
2232 iPort = offReg / AHCI_PORT_REGISTER_SIZE;
2233 iReg = (offReg % AHCI_PORT_REGISTER_SIZE) >> 2;
2234 Log3(("%s: Trying to write to port %u and register %u\n", __FUNCTION__, iPort, iReg));
2235 if (RT_LIKELY( iPort < pAhci->cPortsImpl
2236 && iReg < RT_ELEMENTS(g_aPortOpRegs)))
2237 {
2238 const AHCIPORTOPREG *pPortReg = &g_aPortOpRegs[iReg];
2239 rc = pPortReg->pfnWrite(pAhci, &pAhci->ahciPort[iPort], iReg, u32Value);
2240 }
2241 else
2242 {
2243 Log3(("%s: Trying to write port %u register %u/%u!!!\n", __FUNCTION__, iPort, iReg, RT_ELEMENTS(g_aPortOpRegs)));
2244 rc = VINF_SUCCESS;
2245 }
2246 }
2247
2248 return rc;
2249}
2250
2251/**
2252 * Memory mapped I/O Handler for read operations.
2253 *
2254 * @returns VBox status code.
2255 *
2256 * @param pDevIns The device instance.
2257 * @param pvUser User argument.
2258 * @param GCPhysAddr Physical address (in GC) where the read starts.
2259 * @param pv Where to store the result.
2260 * @param cb Number of bytes read.
2261 */
2262PDMBOTHCBDECL(int) ahciMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2263{
2264 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
2265 Log2(("#%d ahciMMIORead: pvUser=%p:{%.*Rhxs} cb=%d GCPhysAddr=%RGp\n", pDevIns->iInstance, pv, cb, pv, cb, GCPhysAddr));
2266 RT_NOREF1(pvUser);
2267
2268 int rc = ahciRegisterRead(pAhci, GCPhysAddr - pAhci->MMIOBase, pv, cb);
2269
2270 Log2(("#%d ahciMMIORead: return pvUser=%p:{%.*Rhxs} cb=%d GCPhysAddr=%RGp rc=%Rrc\n",
2271 pDevIns->iInstance, pv, cb, pv, cb, GCPhysAddr, rc));
2272 return rc;
2273}
2274
2275
2276/**
2277 * Memory mapped I/O Handler for write operations.
2278 *
2279 * @returns VBox status code.
2280 *
2281 * @param pDevIns The device instance.
2282 * @param pvUser User argument.
2283 * @param GCPhysAddr Physical address (in GC) where the read starts.
2284 * @param pv Where to fetch the result.
2285 * @param cb Number of bytes to write.
2286 */
2287PDMBOTHCBDECL(int) ahciMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
2288{
2289 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
2290 Assert(cb == 4 || cb == 8);
2291 Assert(!(GCPhysAddr & (cb - 1)));
2292
2293 /* Break up 64 bits writes into two dword writes. */
2294 /** @todo Eliminate this code once the IOM/EM starts taking care of these
2295 * situations. */
2296 if (cb == 8)
2297 {
2298 /*
2299 * Only write the first 4 bytes if they weren't already.
2300 * It is possible that the last write to the register caused a world
2301 * switch and we entered this function again.
2302 * Writing the first 4 bytes again could cause indeterminate behavior
2303 * which can cause errors in the guest.
2304 */
2305 int rc = VINF_SUCCESS;
2306 if (!pAhci->f8ByteMMIO4BytesWrittenSuccessfully)
2307 {
2308 rc = ahciMMIOWrite(pDevIns, pvUser, GCPhysAddr, pv, 4);
2309 if (rc != VINF_SUCCESS)
2310 return rc;
2311
2312 pAhci->f8ByteMMIO4BytesWrittenSuccessfully = true;
2313 }
2314
2315 rc = ahciMMIOWrite(pDevIns, pvUser, GCPhysAddr + 4, (uint8_t *)pv + 4, 4);
2316 /*
2317 * Reset flag again so that the first 4 bytes are written again on the next
2318 * 8byte MMIO access.
2319 */
2320 if (rc == VINF_SUCCESS)
2321 pAhci->f8ByteMMIO4BytesWrittenSuccessfully = false;
2322
2323 return rc;
2324 }
2325
2326 /* Do the access. */
2327 Log2(("#%d ahciMMIOWrite: pvUser=%p:{%.*Rhxs} cb=%d GCPhysAddr=%RGp\n", pDevIns->iInstance, pv, cb, pv, cb, GCPhysAddr));
2328 return ahciRegisterWrite(pAhci, GCPhysAddr - pAhci->MMIOBase, *(uint32_t const *)pv);
2329}
2330
2331PDMBOTHCBDECL(int) ahciLegacyFakeWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2332{
2333 RT_NOREF5(pDevIns, pvUser, Port, u32, cb);
2334 AssertMsgFailed(("Should not happen\n"));
2335 return VINF_SUCCESS;
2336}
2337
2338PDMBOTHCBDECL(int) ahciLegacyFakeRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
2339{
2340 RT_NOREF5(pDevIns, pvUser, Port, pu32, cb);
2341 AssertMsgFailed(("Should not happen\n"));
2342 return VINF_SUCCESS;
2343}
2344
2345/**
2346 * I/O port handler for writes to the index/data register pair.
2347 *
2348 * @returns VBox status code.
2349 *
2350 * @param pDevIns The device instance.
2351 * @param pvUser User argument.
2352 * @param Port Port address where the write starts.
2353 * @param u32 Where to fetch the result.
2354 * @param cb Number of bytes to write.
2355 */
2356PDMBOTHCBDECL(int) ahciIdxDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2357{
2358 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
2359 int rc = VINF_SUCCESS;
2360 RT_NOREF2(pvUser, cb);
2361
2362 if (Port - pAhci->IOPortBase >= 8)
2363 {
2364 unsigned iReg = (Port - pAhci->IOPortBase - 8) / 4;
2365
2366 Assert(cb == 4);
2367
2368 if (iReg == 0)
2369 {
2370 /* Write the index register. */
2371 pAhci->regIdx = u32;
2372 }
2373 else
2374 {
2375 /** @todo range check? */
2376 Assert(iReg == 1);
2377 rc = ahciRegisterWrite(pAhci, pAhci->regIdx, u32);
2378 if (rc == VINF_IOM_R3_MMIO_WRITE)
2379 rc = VINF_IOM_R3_IOPORT_WRITE;
2380 }
2381 }
2382 /* else: ignore */
2383
2384 Log2(("#%d ahciIdxDataWrite: pu32=%p:{%.*Rhxs} cb=%d Port=%#x rc=%Rrc\n",
2385 pDevIns->iInstance, &u32, cb, &u32, cb, Port, rc));
2386 return rc;
2387}
2388
2389/**
2390 * I/O port handler for reads from the index/data register pair.
2391 *
2392 * @returns VBox status code.
2393 *
2394 * @param pDevIns The device instance.
2395 * @param pvUser User argument.
2396 * @param Port Port address where the read starts.
2397 * @param pu32 Where to fetch the result.
2398 * @param cb Number of bytes to write.
2399 */
2400PDMBOTHCBDECL(int) ahciIdxDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
2401{
2402 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
2403 int rc = VINF_SUCCESS;
2404 RT_NOREF1(pvUser);
2405
2406 if (Port - pAhci->IOPortBase >= 8)
2407 {
2408 unsigned iReg = (Port - pAhci->IOPortBase - 8) / 4;
2409
2410 Assert(cb == 4);
2411
2412 if (iReg == 0)
2413 {
2414 /* Read the index register. */
2415 *pu32 = pAhci->regIdx;
2416 }
2417 else
2418 {
2419 Assert(iReg == 1);
2420 /** @todo range check? */
2421 rc = ahciRegisterRead(pAhci, pAhci->regIdx, pu32, cb);
2422 if (rc == VINF_IOM_R3_MMIO_READ)
2423 rc = VINF_IOM_R3_IOPORT_READ;
2424 else if (rc == VINF_IOM_MMIO_UNUSED_00)
2425 rc = VERR_IOM_IOPORT_UNUSED;
2426 }
2427 }
2428 else
2429 *pu32 = UINT32_C(0xffffffff);
2430
2431 Log2(("#%d ahciIdxDataRead: pu32=%p:{%.*Rhxs} cb=%d Port=%#x rc=%Rrc\n",
2432 pDevIns->iInstance, pu32, cb, pu32, cb, Port, rc));
2433 return rc;
2434}
2435
2436#ifdef IN_RING3
2437
2438/**
2439 * @callback_method_impl{FNPCIIOREGIONMAP}
2440 */
2441static DECLCALLBACK(int) ahciR3MMIOMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
2442 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
2443{
2444 RT_NOREF(iRegion, enmType);
2445 PAHCI pThis = PCIDEV_2_PAHCI(pPciDev);
2446
2447 Log2(("%s: registering MMIO area at GCPhysAddr=%RGp cb=%RGp\n", __FUNCTION__, GCPhysAddress, cb));
2448
2449 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
2450 Assert(cb >= 4352);
2451
2452 /* We use the assigned size here, because we currently only support page aligned MMIO ranges. */
2453 /** @todo change this to IOMMMIO_FLAGS_WRITE_ONLY_DWORD once EM/IOM starts
2454 * handling 2nd DWORD failures on split accesses correctly. */
2455 int rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
2456 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_ONLY_DWORD_QWORD,
2457 ahciMMIOWrite, ahciMMIORead, "AHCI");
2458 if (RT_FAILURE(rc))
2459 return rc;
2460
2461 if (pThis->fR0Enabled)
2462 {
2463 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/, "ahciMMIOWrite", "ahciMMIORead");
2464 if (RT_FAILURE(rc))
2465 return rc;
2466 }
2467
2468 if (pThis->fGCEnabled)
2469 {
2470 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/, "ahciMMIOWrite", "ahciMMIORead");
2471 if (RT_FAILURE(rc))
2472 return rc;
2473 }
2474
2475 pThis->MMIOBase = GCPhysAddress;
2476 return rc;
2477}
2478
2479
2480/**
2481 * @callback_method_impl{FNPCIIOREGIONMAP,
2482 * Map the legacy I/O port ranges to make Solaris work with the
2483 * controller.}
2484 */
2485static DECLCALLBACK(int) ahciR3LegacyFakeIORangeMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
2486 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
2487{
2488 RT_NOREF(iRegion, enmType);
2489 PAHCI pThis = PCIDEV_2_PAHCI(pPciDev);
2490 int rc = VINF_SUCCESS;
2491
2492 Log2(("%s: registering fake I/O area at GCPhysAddr=%RGp cb=%RGp\n", __FUNCTION__, GCPhysAddress, cb));
2493
2494 Assert(enmType == PCI_ADDRESS_SPACE_IO);
2495
2496 /* We use the assigned size here, because we currently only support page aligned MMIO ranges. */
2497 rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, NULL,
2498 ahciLegacyFakeWrite, ahciLegacyFakeRead, NULL, NULL, "AHCI Fake");
2499 if (RT_FAILURE(rc))
2500 return rc;
2501
2502 if (pThis->fR0Enabled)
2503 {
2504 rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
2505 "ahciLegacyFakeWrite", "ahciLegacyFakeRead", NULL, NULL, "AHCI Fake");
2506 if (RT_FAILURE(rc))
2507 return rc;
2508 }
2509
2510 if (pThis->fGCEnabled)
2511 {
2512 rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
2513 "ahciLegacyFakeWrite", "ahciLegacyFakeRead", NULL, NULL, "AHCI Fake");
2514 if (RT_FAILURE(rc))
2515 return rc;
2516 }
2517
2518 return rc;
2519}
2520
2521/**
2522 * @callback_method_impl{FNPCIIOREGIONMAP,
2523 * Map the BMDMA I/O port range (used for the Index/Data pair register access)}
2524 */
2525static DECLCALLBACK(int) ahciR3IdxDataIORangeMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
2526 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
2527{
2528 RT_NOREF(iRegion, enmType);
2529 PAHCI pThis = PCIDEV_2_PAHCI(pPciDev);
2530 int rc = VINF_SUCCESS;
2531
2532 Log2(("%s: registering fake I/O area at GCPhysAddr=%RGp cb=%RGp\n", __FUNCTION__, GCPhysAddress, cb));
2533
2534 Assert(enmType == PCI_ADDRESS_SPACE_IO);
2535
2536 /* We use the assigned size here, because we currently only support page aligned MMIO ranges. */
2537 rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, NULL,
2538 ahciIdxDataWrite, ahciIdxDataRead, NULL, NULL, "AHCI IDX/DATA");
2539 if (RT_FAILURE(rc))
2540 return rc;
2541
2542 if (pThis->fR0Enabled)
2543 {
2544 rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
2545 "ahciIdxDataWrite", "ahciIdxDataRead", NULL, NULL, "AHCI IDX/DATA");
2546 if (RT_FAILURE(rc))
2547 return rc;
2548 }
2549
2550 if (pThis->fGCEnabled)
2551 {
2552 rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
2553 "ahciIdxDataWrite", "ahciIdxDataRead", NULL, NULL, "AHCI IDX/DATA");
2554 if (RT_FAILURE(rc))
2555 return rc;
2556 }
2557
2558 pThis->IOPortBase = (RTIOPORT)GCPhysAddress;
2559 return rc;
2560}
2561
2562/* -=-=-=-=-=- PAHCI::ILeds -=-=-=-=-=- */
2563
2564/**
2565 * Gets the pointer to the status LED of a unit.
2566 *
2567 * @returns VBox status code.
2568 * @param pInterface Pointer to the interface structure containing the called function pointer.
2569 * @param iLUN The unit which status LED we desire.
2570 * @param ppLed Where to store the LED pointer.
2571 */
2572static DECLCALLBACK(int) ahciR3Status_QueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
2573{
2574 PAHCI pAhci = PDMILEDPORTS_2_PAHCI(pInterface);
2575 if (iLUN < AHCI_MAX_NR_PORTS_IMPL)
2576 {
2577 *ppLed = &pAhci->ahciPort[iLUN].Led;
2578 Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
2579 return VINF_SUCCESS;
2580 }
2581 return VERR_PDM_LUN_NOT_FOUND;
2582}
2583
2584/**
2585 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2586 */
2587static DECLCALLBACK(void *) ahciR3Status_QueryInterface(PPDMIBASE pInterface, const char *pszIID)
2588{
2589 PAHCI pThis = PDMIBASE_2_PAHCI(pInterface);
2590 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
2591 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
2592 return NULL;
2593}
2594
2595/**
2596 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2597 */
2598static DECLCALLBACK(void *) ahciR3PortQueryInterface(PPDMIBASE pInterface, const char *pszIID)
2599{
2600 PAHCIPort pAhciPort = PDMIBASE_2_PAHCIPORT(pInterface);
2601 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pAhciPort->IBase);
2602 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIMEDIAPORT, &pAhciPort->IPort);
2603 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIMEDIAEXPORT, &pAhciPort->IMediaExPort);
2604 return NULL;
2605}
2606
2607/**
2608 * @interface_method_impl{PDMIMEDIAPORT,pfnQueryDeviceLocation}
2609 */
2610static DECLCALLBACK(int) ahciR3PortQueryDeviceLocation(PPDMIMEDIAPORT pInterface, const char **ppcszController,
2611 uint32_t *piInstance, uint32_t *piLUN)
2612{
2613 PAHCIPort pAhciPort = PDMIMEDIAPORT_2_PAHCIPORT(pInterface);
2614 PPDMDEVINS pDevIns = pAhciPort->CTX_SUFF(pDevIns);
2615
2616 AssertPtrReturn(ppcszController, VERR_INVALID_POINTER);
2617 AssertPtrReturn(piInstance, VERR_INVALID_POINTER);
2618 AssertPtrReturn(piLUN, VERR_INVALID_POINTER);
2619
2620 *ppcszController = pDevIns->pReg->szName;
2621 *piInstance = pDevIns->iInstance;
2622 *piLUN = pAhciPort->iLUN;
2623
2624 return VINF_SUCCESS;
2625}
2626
2627/**
2628 * @interface_method_impl{PDMIMEDIAPORT,pfnQueryScsiInqStrings}
2629 */
2630static DECLCALLBACK(int) ahciR3PortQueryScsiInqStrings(PPDMIMEDIAPORT pInterface, const char **ppszVendorId,
2631 const char **ppszProductId, const char **ppszRevision)
2632{
2633 PAHCIPort pAhciPort = PDMIMEDIAPORT_2_PAHCIPORT(pInterface);
2634
2635 if (ppszVendorId)
2636 *ppszVendorId = &pAhciPort->szInquiryVendorId[0];
2637 if (ppszProductId)
2638 *ppszProductId = &pAhciPort->szInquiryProductId[0];
2639 if (ppszRevision)
2640 *ppszRevision = &pAhciPort->szInquiryRevision[0];
2641 return VINF_SUCCESS;
2642}
2643
2644#ifdef LOG_ENABLED
2645
2646/**
2647 * Dump info about the FIS
2648 *
2649 * @returns nothing
2650 * @param pAhciPort The port the command FIS was read from.
2651 * @param cmdFis The FIS to print info from.
2652 */
2653static void ahciDumpFisInfo(PAHCIPort pAhciPort, uint8_t *cmdFis)
2654{
2655 ahciLog(("%s: *** Begin FIS info dump. ***\n", __FUNCTION__));
2656 /* Print FIS type. */
2657 switch (cmdFis[AHCI_CMDFIS_TYPE])
2658 {
2659 case AHCI_CMDFIS_TYPE_H2D:
2660 {
2661 ahciLog(("%s: Command Fis type: H2D\n", __FUNCTION__));
2662 ahciLog(("%s: Command Fis size: %d bytes\n", __FUNCTION__, AHCI_CMDFIS_TYPE_H2D_SIZE));
2663 if (cmdFis[AHCI_CMDFIS_BITS] & AHCI_CMDFIS_C)
2664 ahciLog(("%s: Command register update\n", __FUNCTION__));
2665 else
2666 ahciLog(("%s: Control register update\n", __FUNCTION__));
2667 ahciLog(("%s: CMD=%#04x \"%s\"\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CMD], ATACmdText(cmdFis[AHCI_CMDFIS_CMD])));
2668 ahciLog(("%s: FEAT=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_FET]));
2669 ahciLog(("%s: SECTN=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_SECTN]));
2670 ahciLog(("%s: CYLL=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CYLL]));
2671 ahciLog(("%s: CYLH=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CYLH]));
2672 ahciLog(("%s: HEAD=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_HEAD]));
2673
2674 ahciLog(("%s: SECTNEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_SECTNEXP]));
2675 ahciLog(("%s: CYLLEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CYLLEXP]));
2676 ahciLog(("%s: CYLHEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CYLHEXP]));
2677 ahciLog(("%s: FETEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_FETEXP]));
2678
2679 ahciLog(("%s: SECTC=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_SECTC]));
2680 ahciLog(("%s: SECTCEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_SECTCEXP]));
2681 ahciLog(("%s: CTL=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CTL]));
2682 if (cmdFis[AHCI_CMDFIS_CTL] & AHCI_CMDFIS_CTL_SRST)
2683 ahciLog(("%s: Reset bit is set\n", __FUNCTION__));
2684 break;
2685 }
2686 case AHCI_CMDFIS_TYPE_D2H:
2687 {
2688 ahciLog(("%s: Command Fis type D2H\n", __FUNCTION__));
2689 ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_D2H_SIZE));
2690 break;
2691 }
2692 case AHCI_CMDFIS_TYPE_SETDEVBITS:
2693 {
2694 ahciLog(("%s: Command Fis type Set Device Bits\n", __FUNCTION__));
2695 ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_SETDEVBITS_SIZE));
2696 break;
2697 }
2698 case AHCI_CMDFIS_TYPE_DMAACTD2H:
2699 {
2700 ahciLog(("%s: Command Fis type DMA Activate H2D\n", __FUNCTION__));
2701 ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_DMAACTD2H_SIZE));
2702 break;
2703 }
2704 case AHCI_CMDFIS_TYPE_DMASETUP:
2705 {
2706 ahciLog(("%s: Command Fis type DMA Setup\n", __FUNCTION__));
2707 ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_DMASETUP_SIZE));
2708 break;
2709 }
2710 case AHCI_CMDFIS_TYPE_PIOSETUP:
2711 {
2712 ahciLog(("%s: Command Fis type PIO Setup\n", __FUNCTION__));
2713 ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_PIOSETUP_SIZE));
2714 break;
2715 }
2716 case AHCI_CMDFIS_TYPE_DATA:
2717 {
2718 ahciLog(("%s: Command Fis type Data\n", __FUNCTION__));
2719 break;
2720 }
2721 default:
2722 ahciLog(("%s: ERROR Unknown command FIS type\n", __FUNCTION__));
2723 break;
2724 }
2725 ahciLog(("%s: *** End FIS info dump. ***\n", __FUNCTION__));
2726}
2727
2728/**
2729 * Dump info about the command header
2730 *
2731 * @returns nothing
2732 * @param pAhciPort Pointer to the port the command header was read from.
2733 * @param pCmdHdr The command header to print info from.
2734 */
2735static void ahciDumpCmdHdrInfo(PAHCIPort pAhciPort, CmdHdr *pCmdHdr)
2736{
2737 ahciLog(("%s: *** Begin command header info dump. ***\n", __FUNCTION__));
2738 ahciLog(("%s: Number of Scatter/Gatther List entries: %u\n", __FUNCTION__, AHCI_CMDHDR_PRDTL_ENTRIES(pCmdHdr->u32DescInf)));
2739 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_C)
2740 ahciLog(("%s: Clear busy upon R_OK\n", __FUNCTION__));
2741 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_B)
2742 ahciLog(("%s: BIST Fis\n", __FUNCTION__));
2743 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_R)
2744 ahciLog(("%s: Device Reset Fis\n", __FUNCTION__));
2745 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_P)
2746 ahciLog(("%s: Command prefetchable\n", __FUNCTION__));
2747 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_W)
2748 ahciLog(("%s: Device write\n", __FUNCTION__));
2749 else
2750 ahciLog(("%s: Device read\n", __FUNCTION__));
2751 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_A)
2752 ahciLog(("%s: ATAPI command\n", __FUNCTION__));
2753 else
2754 ahciLog(("%s: ATA command\n", __FUNCTION__));
2755
2756 ahciLog(("%s: Command FIS length %u DW\n", __FUNCTION__, (pCmdHdr->u32DescInf & AHCI_CMDHDR_CFL_MASK)));
2757 ahciLog(("%s: *** End command header info dump. ***\n", __FUNCTION__));
2758}
2759
2760#endif /* LOG_ENABLED */
2761
2762/**
2763 * Post the first D2H FIS from the device into guest memory.
2764 *
2765 * @returns nothing
2766 * @param pAhciPort Pointer to the port which "receives" the FIS.
2767 */
2768static void ahciPostFirstD2HFisIntoMemory(PAHCIPort pAhciPort)
2769{
2770 uint8_t d2hFis[AHCI_CMDFIS_TYPE_D2H_SIZE];
2771
2772 pAhciPort->fFirstD2HFisSent = true;
2773
2774 ahciLog(("%s: Sending First D2H FIS from FIFO\n", __FUNCTION__));
2775 memset(&d2hFis[0], 0, sizeof(d2hFis));
2776 d2hFis[AHCI_CMDFIS_TYPE] = AHCI_CMDFIS_TYPE_D2H;
2777 d2hFis[AHCI_CMDFIS_ERR] = 0x01;
2778
2779 d2hFis[AHCI_CMDFIS_STS] = 0x00;
2780
2781 /* Set the signature based on the device type. */
2782 if (pAhciPort->fATAPI)
2783 {
2784 d2hFis[AHCI_CMDFIS_CYLL] = 0x14;
2785 d2hFis[AHCI_CMDFIS_CYLH] = 0xeb;
2786 }
2787 else
2788 {
2789 d2hFis[AHCI_CMDFIS_CYLL] = 0x00;
2790 d2hFis[AHCI_CMDFIS_CYLH] = 0x00;
2791 }
2792
2793 d2hFis[AHCI_CMDFIS_HEAD] = 0x00;
2794 d2hFis[AHCI_CMDFIS_SECTN] = 0x01;
2795 d2hFis[AHCI_CMDFIS_SECTC] = 0x01;
2796
2797 pAhciPort->regTFD = (1 << 8) | ATA_STAT_SEEK | ATA_STAT_WRERR;
2798 if (!pAhciPort->fATAPI)
2799 pAhciPort->regTFD |= ATA_STAT_READY;
2800
2801 ahciPostFisIntoMemory(pAhciPort, AHCI_CMDFIS_TYPE_D2H, d2hFis);
2802}
2803
2804/**
2805 * Post the FIS in the memory area allocated by the guest and set interrupt if necessary.
2806 *
2807 * @returns VBox status code
2808 * @param pAhciPort The port which "receives" the FIS.
2809 * @param uFisType The type of the FIS.
2810 * @param pCmdFis Pointer to the FIS which is to be posted into memory.
2811 */
2812static int ahciPostFisIntoMemory(PAHCIPort pAhciPort, unsigned uFisType, uint8_t *pCmdFis)
2813{
2814 int rc = VINF_SUCCESS;
2815 RTGCPHYS GCPhysAddrRecFis = pAhciPort->GCPhysAddrFb;
2816 unsigned cbFis = 0;
2817
2818 ahciLog(("%s: pAhciPort=%p uFisType=%u pCmdFis=%p\n", __FUNCTION__, pAhciPort, uFisType, pCmdFis));
2819
2820 if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
2821 {
2822 AssertMsg(GCPhysAddrRecFis, ("%s: GCPhysAddrRecFis is 0\n", __FUNCTION__));
2823
2824 /* Determine the offset and size of the FIS based on uFisType. */
2825 switch (uFisType)
2826 {
2827 case AHCI_CMDFIS_TYPE_D2H:
2828 {
2829 GCPhysAddrRecFis += AHCI_RECFIS_RFIS_OFFSET;
2830 cbFis = AHCI_CMDFIS_TYPE_D2H_SIZE;
2831 break;
2832 }
2833 case AHCI_CMDFIS_TYPE_SETDEVBITS:
2834 {
2835 GCPhysAddrRecFis += AHCI_RECFIS_SDBFIS_OFFSET;
2836 cbFis = AHCI_CMDFIS_TYPE_SETDEVBITS_SIZE;
2837 break;
2838 }
2839 case AHCI_CMDFIS_TYPE_DMASETUP:
2840 {
2841 GCPhysAddrRecFis += AHCI_RECFIS_DSFIS_OFFSET;
2842 cbFis = AHCI_CMDFIS_TYPE_DMASETUP_SIZE;
2843 break;
2844 }
2845 case AHCI_CMDFIS_TYPE_PIOSETUP:
2846 {
2847 GCPhysAddrRecFis += AHCI_RECFIS_PSFIS_OFFSET;
2848 cbFis = AHCI_CMDFIS_TYPE_PIOSETUP_SIZE;
2849 break;
2850 }
2851 default:
2852 /*
2853 * We should post the unknown FIS into memory too but this never happens because
2854 * we know which FIS types we generate. ;)
2855 */
2856 AssertMsgFailed(("%s: Unknown FIS type!\n", __FUNCTION__));
2857 }
2858
2859 /* Post the FIS into memory. */
2860 ahciLog(("%s: PDMDevHlpPCIPhysWrite GCPhysAddrRecFis=%RGp cbFis=%u\n", __FUNCTION__, GCPhysAddrRecFis, cbFis));
2861 PDMDevHlpPCIPhysWrite(pAhciPort->CTX_SUFF(pDevIns), GCPhysAddrRecFis, pCmdFis, cbFis);
2862 }
2863
2864 return rc;
2865}
2866
2867DECLINLINE(void) ahciReqSetStatus(PAHCIREQ pAhciReq, uint8_t u8Error, uint8_t u8Status)
2868{
2869 pAhciReq->cmdFis[AHCI_CMDFIS_ERR] = u8Error;
2870 pAhciReq->cmdFis[AHCI_CMDFIS_STS] = u8Status;
2871}
2872
2873static void ataPadString(uint8_t *pbDst, const char *pbSrc, uint32_t cbSize)
2874{
2875 for (uint32_t i = 0; i < cbSize; i++)
2876 {
2877 if (*pbSrc)
2878 pbDst[i ^ 1] = *pbSrc++;
2879 else
2880 pbDst[i ^ 1] = ' ';
2881 }
2882}
2883
2884static uint32_t ataChecksum(void* ptr, size_t count)
2885{
2886 uint8_t u8Sum = 0xa5, *p = (uint8_t*)ptr;
2887 size_t i;
2888
2889 for (i = 0; i < count; i++)
2890 {
2891 u8Sum += *p++;
2892 }
2893
2894 return (uint8_t)-(int32_t)u8Sum;
2895}
2896
2897static int ahciIdentifySS(PAHCIPort pAhciPort, void *pvBuf)
2898{
2899 uint16_t *p = (uint16_t *)pvBuf;
2900 memset(p, 0, 512);
2901 p[0] = RT_H2LE_U16(0x0040);
2902 p[1] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383));
2903 p[3] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cHeads);
2904 /* Block size; obsolete, but required for the BIOS. */
2905 p[5] = RT_H2LE_U16(512);
2906 p[6] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cSectors);
2907 ataPadString((uint8_t *)(p + 10), pAhciPort->szSerialNumber, AHCI_SERIAL_NUMBER_LENGTH); /* serial number */
2908 p[20] = RT_H2LE_U16(3); /* XXX: retired, cache type */
2909 p[21] = RT_H2LE_U16(512); /* XXX: retired, cache size in sectors */
2910 p[22] = RT_H2LE_U16(0); /* ECC bytes per sector */
2911 ataPadString((uint8_t *)(p + 23), pAhciPort->szFirmwareRevision, AHCI_FIRMWARE_REVISION_LENGTH); /* firmware version */
2912 ataPadString((uint8_t *)(p + 27), pAhciPort->szModelNumber, AHCI_MODEL_NUMBER_LENGTH); /* model */
2913#if ATA_MAX_MULT_SECTORS > 1
2914 p[47] = RT_H2LE_U16(0x8000 | ATA_MAX_MULT_SECTORS);
2915#endif
2916 p[48] = RT_H2LE_U16(1); /* dword I/O, used by the BIOS */
2917 p[49] = RT_H2LE_U16(1 << 11 | 1 << 9 | 1 << 8); /* DMA and LBA supported */
2918 p[50] = RT_H2LE_U16(1 << 14); /* No drive specific standby timer minimum */
2919 p[51] = RT_H2LE_U16(240); /* PIO transfer cycle */
2920 p[52] = RT_H2LE_U16(240); /* DMA transfer cycle */
2921 p[53] = RT_H2LE_U16(1 | 1 << 1 | 1 << 2); /* words 54-58,64-70,88 valid */
2922 p[54] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383));
2923 p[55] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cHeads);
2924 p[56] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cSectors);
2925 p[57] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383) * pAhciPort->PCHSGeometry.cHeads * pAhciPort->PCHSGeometry.cSectors);
2926 p[58] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383) * pAhciPort->PCHSGeometry.cHeads * pAhciPort->PCHSGeometry.cSectors >> 16);
2927 if (pAhciPort->cMultSectors)
2928 p[59] = RT_H2LE_U16(0x100 | pAhciPort->cMultSectors);
2929 if (pAhciPort->cTotalSectors <= (1 << 28) - 1)
2930 {
2931 p[60] = RT_H2LE_U16(pAhciPort->cTotalSectors);
2932 p[61] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 16);
2933 }
2934 else
2935 {
2936 /* Report maximum number of sectors possible with LBA28 */
2937 p[60] = RT_H2LE_U16(((1 << 28) - 1) & 0xffff);
2938 p[61] = RT_H2LE_U16(((1 << 28) - 1) >> 16);
2939 }
2940 p[63] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_MDMA, ATA_MDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* MDMA modes supported / mode enabled */
2941 p[64] = RT_H2LE_U16(ATA_PIO_MODE_MAX > 2 ? (1 << (ATA_PIO_MODE_MAX - 2)) - 1 : 0); /* PIO modes beyond PIO2 supported */
2942 p[65] = RT_H2LE_U16(120); /* minimum DMA multiword tx cycle time */
2943 p[66] = RT_H2LE_U16(120); /* recommended DMA multiword tx cycle time */
2944 p[67] = RT_H2LE_U16(120); /* minimum PIO cycle time without flow control */
2945 p[68] = RT_H2LE_U16(120); /* minimum PIO cycle time with IORDY flow control */
2946 if ( pAhciPort->fTrimEnabled
2947 || pAhciPort->cbSector != 512
2948 || pAhciPort->pDrvMedia->pfnIsNonRotational(pAhciPort->pDrvMedia))
2949 {
2950 p[80] = RT_H2LE_U16(0x1f0); /* support everything up to ATA/ATAPI-8 ACS */
2951 p[81] = RT_H2LE_U16(0x28); /* conforms to ATA/ATAPI-8 ACS */
2952 }
2953 else
2954 {
2955 p[80] = RT_H2LE_U16(0x7e); /* support everything up to ATA/ATAPI-6 */
2956 p[81] = RT_H2LE_U16(0x22); /* conforms to ATA/ATAPI-6 */
2957 }
2958 p[82] = RT_H2LE_U16(1 << 3 | 1 << 5 | 1 << 6); /* supports power management, write cache and look-ahead */
2959 p[83] = RT_H2LE_U16(1 << 14 | 1 << 10 | 1 << 12 | 1 << 13); /* supports LBA48, FLUSH CACHE and FLUSH CACHE EXT */
2960 p[84] = RT_H2LE_U16(1 << 14);
2961 p[85] = RT_H2LE_U16(1 << 3 | 1 << 5 | 1 << 6); /* enabled power management, write cache and look-ahead */
2962 p[86] = RT_H2LE_U16(1 << 10 | 1 << 12 | 1 << 13); /* enabled LBA48, FLUSH CACHE and FLUSH CACHE EXT */
2963 p[87] = RT_H2LE_U16(1 << 14);
2964 p[88] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_UDMA, ATA_UDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* UDMA modes supported / mode enabled */
2965 p[93] = RT_H2LE_U16(0x00);
2966 p[100] = RT_H2LE_U16(pAhciPort->cTotalSectors);
2967 p[101] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 16);
2968 p[102] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 32);
2969 p[103] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 48);
2970
2971 /* valid information, more than one logical sector per physical sector, 2^cLogSectorsPerPhysicalExp logical sectors per physical sector */
2972 if (pAhciPort->cLogSectorsPerPhysicalExp)
2973 p[106] = RT_H2LE_U16(RT_BIT(14) | RT_BIT(13) | pAhciPort->cLogSectorsPerPhysicalExp);
2974
2975 if (pAhciPort->cbSector != 512)
2976 {
2977 uint32_t cSectorSizeInWords = pAhciPort->cbSector / sizeof(uint16_t);
2978 /* Enable reporting of logical sector size. */
2979 p[106] |= RT_H2LE_U16(RT_BIT(12) | RT_BIT(14));
2980 p[117] = RT_H2LE_U16(cSectorSizeInWords);
2981 p[118] = RT_H2LE_U16(cSectorSizeInWords >> 16);
2982 }
2983
2984 if (pAhciPort->pDrvMedia->pfnIsNonRotational(pAhciPort->pDrvMedia))
2985 p[217] = RT_H2LE_U16(1); /* Non-rotational medium */
2986
2987 if (pAhciPort->fTrimEnabled) /** @todo Set bit 14 in word 69 too? (Deterministic read after TRIM). */
2988 p[169] = RT_H2LE_U16(1); /* DATA SET MANAGEMENT command supported. */
2989
2990 /* The following are SATA specific */
2991 p[75] = RT_H2LE_U16(pAhciPort->CTX_SUFF(pAhci)->cCmdSlotsAvail-1); /* Number of commands we support, 0's based */
2992 p[76] = RT_H2LE_U16((1 << 8) | (1 << 2)); /* Native command queuing and Serial ATA Gen2 (3.0 Gbps) speed supported */
2993
2994 uint32_t uCsum = ataChecksum(p, 510);
2995 p[255] = RT_H2LE_U16(0xa5 | (uCsum << 8)); /* Integrity word */
2996
2997 return VINF_SUCCESS;
2998}
2999
3000static int ahciR3AtapiIdentify(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
3001{
3002 uint16_t p[256];
3003
3004 memset(p, 0, 512);
3005 /* Removable CDROM, 50us response, 12 byte packets */
3006 p[0] = RT_H2LE_U16(2 << 14 | 5 << 8 | 1 << 7 | 2 << 5 | 0 << 0);
3007 ataPadString((uint8_t *)(p + 10), pAhciPort->szSerialNumber, AHCI_SERIAL_NUMBER_LENGTH); /* serial number */
3008 p[20] = RT_H2LE_U16(3); /* XXX: retired, cache type */
3009 p[21] = RT_H2LE_U16(512); /* XXX: retired, cache size in sectors */
3010 ataPadString((uint8_t *)(p + 23), pAhciPort->szFirmwareRevision, AHCI_FIRMWARE_REVISION_LENGTH); /* firmware version */
3011 ataPadString((uint8_t *)(p + 27), pAhciPort->szModelNumber, AHCI_MODEL_NUMBER_LENGTH); /* model */
3012 p[49] = RT_H2LE_U16(1 << 11 | 1 << 9 | 1 << 8); /* DMA and LBA supported */
3013 p[50] = RT_H2LE_U16(1 << 14); /* No drive specific standby timer minimum */
3014 p[51] = RT_H2LE_U16(240); /* PIO transfer cycle */
3015 p[52] = RT_H2LE_U16(240); /* DMA transfer cycle */
3016 p[53] = RT_H2LE_U16(1 << 1 | 1 << 2); /* words 64-70,88 are valid */
3017 p[63] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_MDMA, ATA_MDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* MDMA modes supported / mode enabled */
3018 p[64] = RT_H2LE_U16(ATA_PIO_MODE_MAX > 2 ? (1 << (ATA_PIO_MODE_MAX - 2)) - 1 : 0); /* PIO modes beyond PIO2 supported */
3019 p[65] = RT_H2LE_U16(120); /* minimum DMA multiword tx cycle time */
3020 p[66] = RT_H2LE_U16(120); /* recommended DMA multiword tx cycle time */
3021 p[67] = RT_H2LE_U16(120); /* minimum PIO cycle time without flow control */
3022 p[68] = RT_H2LE_U16(120); /* minimum PIO cycle time with IORDY flow control */
3023 p[73] = RT_H2LE_U16(0x003e); /* ATAPI CDROM major */
3024 p[74] = RT_H2LE_U16(9); /* ATAPI CDROM minor */
3025 p[80] = RT_H2LE_U16(0x7e); /* support everything up to ATA/ATAPI-6 */
3026 p[81] = RT_H2LE_U16(0x22); /* conforms to ATA/ATAPI-6 */
3027 p[82] = RT_H2LE_U16(1 << 4 | 1 << 9); /* supports packet command set and DEVICE RESET */
3028 p[83] = RT_H2LE_U16(1 << 14);
3029 p[84] = RT_H2LE_U16(1 << 14);
3030 p[85] = RT_H2LE_U16(1 << 4 | 1 << 9); /* enabled packet command set and DEVICE RESET */
3031 p[86] = RT_H2LE_U16(0);
3032 p[87] = RT_H2LE_U16(1 << 14);
3033 p[88] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_UDMA, ATA_UDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* UDMA modes supported / mode enabled */
3034 p[93] = RT_H2LE_U16((1 | 1 << 1) << ((pAhciPort->iLUN & 1) == 0 ? 0 : 8) | 1 << 13 | 1 << 14);
3035
3036 /* The following are SATA specific */
3037 p[75] = RT_H2LE_U16(31); /* We support 32 commands */
3038 p[76] = RT_H2LE_U16((1 << 8) | (1 << 2)); /* Native command queuing and Serial ATA Gen2 (3.0 Gbps) speed supported */
3039
3040 /* Copy the buffer in to the scatter gather list. */
3041 *pcbData = ahciR3CopyBufferToPrdtl(pAhciPort->CTX_SUFF(pAhci), pAhciReq, (void *)&p[0],
3042 RT_MIN(cbData, sizeof(p)), 0 /* cbSkip */);
3043 return VINF_SUCCESS;
3044}
3045
3046/**
3047 * Reset all values after a reset of the attached storage device.
3048 *
3049 * @returns nothing
3050 * @param pAhciPort The port the device is attached to.
3051 * @param pAhciReq The state to get the tag number from.
3052 */
3053static void ahciFinishStorageDeviceReset(PAHCIPort pAhciPort, PAHCIREQ pAhciReq)
3054{
3055 int rc;
3056
3057 /* Send a status good D2H FIS. */
3058 pAhciPort->fResetDevice = false;
3059 if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
3060 ahciPostFirstD2HFisIntoMemory(pAhciPort);
3061
3062 /* As this is the first D2H FIS after the reset update the signature in the SIG register of the port. */
3063 if (pAhciPort->fATAPI)
3064 pAhciPort->regSIG = AHCI_PORT_SIG_ATAPI;
3065 else
3066 pAhciPort->regSIG = AHCI_PORT_SIG_DISK;
3067 ASMAtomicOrU32(&pAhciPort->u32TasksFinished, (1 << pAhciReq->uTag));
3068
3069 rc = ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN, VERR_IGNORED);
3070 AssertRC(rc);
3071}
3072
3073/**
3074 * Initiates a device reset caused by ATA_DEVICE_RESET (ATAPI only).
3075 *
3076 * @returns nothing.
3077 * @param pAhciPort The device to reset.
3078 * @param pAhciReq The task state.
3079 */
3080static void ahciDeviceReset(PAHCIPort pAhciPort, PAHCIREQ pAhciReq)
3081{
3082 ASMAtomicWriteBool(&pAhciPort->fResetDevice, true);
3083
3084 /*
3085 * Because this ATAPI only and ATAPI can't have
3086 * more than one command active at a time the task counter should be 0
3087 * and it is possible to finish the reset now.
3088 */
3089 Assert(ASMAtomicReadU32(&pAhciPort->cTasksActive) == 0);
3090 ahciFinishStorageDeviceReset(pAhciPort, pAhciReq);
3091}
3092
3093/**
3094 * Create a PIO setup FIS and post it into the memory area of the guest.
3095 *
3096 * @returns nothing.
3097 * @param pAhciPort The port of the SATA controller.
3098 * @param cbTransfer Transfer size of the request.
3099 * @param pCmdFis Pointer to the command FIS from the guest.
3100 * @param fRead Flag whether this is a read request.
3101 * @param fInterrupt If an interrupt should be send to the guest.
3102 */
3103static void ahciSendPioSetupFis(PAHCIPort pAhciPort, size_t cbTransfer, uint8_t *pCmdFis,
3104 bool fRead, bool fInterrupt)
3105{
3106 uint8_t abPioSetupFis[20];
3107 bool fAssertIntr = false;
3108 PAHCI pAhci = pAhciPort->CTX_SUFF(pAhci);
3109
3110 ahciLog(("%s: building PIO setup Fis\n", __FUNCTION__));
3111
3112 AssertMsg( cbTransfer > 0
3113 && cbTransfer <= 65534,
3114 ("Can't send PIO setup FIS for requests with 0 bytes to transfer or greater than 65534\n"));
3115
3116 if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
3117 {
3118 memset(&abPioSetupFis[0], 0, sizeof(abPioSetupFis));
3119 abPioSetupFis[AHCI_CMDFIS_TYPE] = AHCI_CMDFIS_TYPE_PIOSETUP;
3120 abPioSetupFis[AHCI_CMDFIS_BITS] = (fInterrupt ? AHCI_CMDFIS_I : 0);
3121 if (fRead)
3122 abPioSetupFis[AHCI_CMDFIS_BITS] |= AHCI_CMDFIS_D;
3123 abPioSetupFis[AHCI_CMDFIS_STS] = pCmdFis[AHCI_CMDFIS_STS];
3124 abPioSetupFis[AHCI_CMDFIS_ERR] = pCmdFis[AHCI_CMDFIS_ERR];
3125 abPioSetupFis[AHCI_CMDFIS_SECTN] = pCmdFis[AHCI_CMDFIS_SECTN];
3126 abPioSetupFis[AHCI_CMDFIS_CYLL] = pCmdFis[AHCI_CMDFIS_CYLL];
3127 abPioSetupFis[AHCI_CMDFIS_CYLH] = pCmdFis[AHCI_CMDFIS_CYLH];
3128 abPioSetupFis[AHCI_CMDFIS_HEAD] = pCmdFis[AHCI_CMDFIS_HEAD];
3129 abPioSetupFis[AHCI_CMDFIS_SECTNEXP] = pCmdFis[AHCI_CMDFIS_SECTNEXP];
3130 abPioSetupFis[AHCI_CMDFIS_CYLLEXP] = pCmdFis[AHCI_CMDFIS_CYLLEXP];
3131 abPioSetupFis[AHCI_CMDFIS_CYLHEXP] = pCmdFis[AHCI_CMDFIS_CYLHEXP];
3132 abPioSetupFis[AHCI_CMDFIS_SECTC] = pCmdFis[AHCI_CMDFIS_SECTC];
3133 abPioSetupFis[AHCI_CMDFIS_SECTCEXP] = pCmdFis[AHCI_CMDFIS_SECTCEXP];
3134
3135 /* Set transfer count. */
3136 abPioSetupFis[16] = (cbTransfer >> 8) & 0xff;
3137 abPioSetupFis[17] = cbTransfer & 0xff;
3138
3139 /* Update registers. */
3140 pAhciPort->regTFD = (pCmdFis[AHCI_CMDFIS_ERR] << 8) | pCmdFis[AHCI_CMDFIS_STS];
3141
3142 ahciPostFisIntoMemory(pAhciPort, AHCI_CMDFIS_TYPE_PIOSETUP, abPioSetupFis);
3143
3144 if (fInterrupt)
3145 {
3146 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_PSS);
3147 /* Check if we should assert an interrupt */
3148 if (pAhciPort->regIE & AHCI_PORT_IE_PSE)
3149 fAssertIntr = true;
3150 }
3151
3152 if (fAssertIntr)
3153 {
3154 int rc = ahciHbaSetInterrupt(pAhci, pAhciPort->iLUN, VERR_IGNORED);
3155 AssertRC(rc);
3156 }
3157 }
3158}
3159
3160/**
3161 * Build a D2H FIS and post into the memory area of the guest.
3162 *
3163 * @returns Nothing
3164 * @param pAhciPort The port of the SATA controller.
3165 * @param uTag The tag of the request.
3166 * @param pCmdFis Pointer to the command FIS from the guest.
3167 * @param fInterrupt If an interrupt should be send to the guest.
3168 */
3169static void ahciSendD2HFis(PAHCIPort pAhciPort, uint32_t uTag, uint8_t *pCmdFis, bool fInterrupt)
3170{
3171 uint8_t d2hFis[20];
3172 bool fAssertIntr = false;
3173 PAHCI pAhci = pAhciPort->CTX_SUFF(pAhci);
3174
3175 ahciLog(("%s: building D2H Fis\n", __FUNCTION__));
3176
3177 if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
3178 {
3179 memset(&d2hFis[0], 0, sizeof(d2hFis));
3180 d2hFis[AHCI_CMDFIS_TYPE] = AHCI_CMDFIS_TYPE_D2H;
3181 d2hFis[AHCI_CMDFIS_BITS] = (fInterrupt ? AHCI_CMDFIS_I : 0);
3182 d2hFis[AHCI_CMDFIS_STS] = pCmdFis[AHCI_CMDFIS_STS];
3183 d2hFis[AHCI_CMDFIS_ERR] = pCmdFis[AHCI_CMDFIS_ERR];
3184 d2hFis[AHCI_CMDFIS_SECTN] = pCmdFis[AHCI_CMDFIS_SECTN];
3185 d2hFis[AHCI_CMDFIS_CYLL] = pCmdFis[AHCI_CMDFIS_CYLL];
3186 d2hFis[AHCI_CMDFIS_CYLH] = pCmdFis[AHCI_CMDFIS_CYLH];
3187 d2hFis[AHCI_CMDFIS_HEAD] = pCmdFis[AHCI_CMDFIS_HEAD];
3188 d2hFis[AHCI_CMDFIS_SECTNEXP] = pCmdFis[AHCI_CMDFIS_SECTNEXP];
3189 d2hFis[AHCI_CMDFIS_CYLLEXP] = pCmdFis[AHCI_CMDFIS_CYLLEXP];
3190 d2hFis[AHCI_CMDFIS_CYLHEXP] = pCmdFis[AHCI_CMDFIS_CYLHEXP];
3191 d2hFis[AHCI_CMDFIS_SECTC] = pCmdFis[AHCI_CMDFIS_SECTC];
3192 d2hFis[AHCI_CMDFIS_SECTCEXP] = pCmdFis[AHCI_CMDFIS_SECTCEXP];
3193
3194 /* Update registers. */
3195 pAhciPort->regTFD = (pCmdFis[AHCI_CMDFIS_ERR] << 8) | pCmdFis[AHCI_CMDFIS_STS];
3196
3197 ahciPostFisIntoMemory(pAhciPort, AHCI_CMDFIS_TYPE_D2H, d2hFis);
3198
3199 if (pCmdFis[AHCI_CMDFIS_STS] & ATA_STAT_ERR)
3200 {
3201 /* Error bit is set. */
3202 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_TFES);
3203 if (pAhciPort->regIE & AHCI_PORT_IE_TFEE)
3204 fAssertIntr = true;
3205 /*
3206 * Don't mark the command slot as completed because the guest
3207 * needs it to identify the failed command.
3208 */
3209 }
3210 else if (fInterrupt)
3211 {
3212 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_DHRS);
3213 /* Check if we should assert an interrupt */
3214 if (pAhciPort->regIE & AHCI_PORT_IE_DHRE)
3215 fAssertIntr = true;
3216
3217 /* Mark command as completed. */
3218 ASMAtomicOrU32(&pAhciPort->u32TasksFinished, RT_BIT_32(uTag));
3219 }
3220
3221 if (fAssertIntr)
3222 {
3223 int rc = ahciHbaSetInterrupt(pAhci, pAhciPort->iLUN, VERR_IGNORED);
3224 AssertRC(rc);
3225 }
3226 }
3227}
3228
3229/**
3230 * Build a SDB Fis and post it into the memory area of the guest.
3231 *
3232 * @returns Nothing
3233 * @param pAhciPort The port for which the SDB Fis is send.
3234 * @param uFinishedTasks Bitmask of finished tasks.
3235 * @param fInterrupt If an interrupt should be asserted.
3236 */
3237static void ahciSendSDBFis(PAHCIPort pAhciPort, uint32_t uFinishedTasks, bool fInterrupt)
3238{
3239 uint32_t sdbFis[2];
3240 bool fAssertIntr = false;
3241 PAHCI pAhci = pAhciPort->CTX_SUFF(pAhci);
3242 PAHCIREQ pTaskErr = ASMAtomicReadPtrT(&pAhciPort->pTaskErr, PAHCIREQ);
3243
3244 ahciLog(("%s: Building SDB FIS\n", __FUNCTION__));
3245
3246 if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
3247 {
3248 memset(&sdbFis[0], 0, sizeof(sdbFis));
3249 sdbFis[0] = AHCI_CMDFIS_TYPE_SETDEVBITS;
3250 sdbFis[0] |= (fInterrupt ? (1 << 14) : 0);
3251 if (RT_UNLIKELY(pTaskErr))
3252 {
3253 sdbFis[0] = pTaskErr->cmdFis[AHCI_CMDFIS_ERR];
3254 sdbFis[0] |= (pTaskErr->cmdFis[AHCI_CMDFIS_STS] & 0x77) << 16; /* Some bits are marked as reserved and thus are masked out. */
3255
3256 /* Update registers. */
3257 pAhciPort->regTFD = (pTaskErr->cmdFis[AHCI_CMDFIS_ERR] << 8) | pTaskErr->cmdFis[AHCI_CMDFIS_STS];
3258 }
3259 else
3260 {
3261 sdbFis[0] = 0;
3262 sdbFis[0] |= (ATA_STAT_READY | ATA_STAT_SEEK) << 16;
3263 pAhciPort->regTFD = ATA_STAT_READY | ATA_STAT_SEEK;
3264 }
3265
3266 sdbFis[1] = pAhciPort->u32QueuedTasksFinished | uFinishedTasks;
3267
3268 ahciPostFisIntoMemory(pAhciPort, AHCI_CMDFIS_TYPE_SETDEVBITS, (uint8_t *)sdbFis);
3269
3270 if (RT_UNLIKELY(pTaskErr))
3271 {
3272 /* Error bit is set. */
3273 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_TFES);
3274 if (pAhciPort->regIE & AHCI_PORT_IE_TFEE)
3275 fAssertIntr = true;
3276 }
3277
3278 if (fInterrupt)
3279 {
3280 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_SDBS);
3281 /* Check if we should assert an interrupt */
3282 if (pAhciPort->regIE & AHCI_PORT_IE_SDBE)
3283 fAssertIntr = true;
3284 }
3285
3286 ASMAtomicOrU32(&pAhciPort->u32QueuedTasksFinished, uFinishedTasks);
3287
3288 if (fAssertIntr)
3289 {
3290 int rc = ahciHbaSetInterrupt(pAhci, pAhciPort->iLUN, VERR_IGNORED);
3291 AssertRC(rc);
3292 }
3293 }
3294}
3295
3296static uint32_t ahciGetNSectors(uint8_t *pCmdFis, bool fLBA48)
3297{
3298 /* 0 means either 256 (LBA28) or 65536 (LBA48) sectors. */
3299 if (fLBA48)
3300 {
3301 if (!pCmdFis[AHCI_CMDFIS_SECTC] && !pCmdFis[AHCI_CMDFIS_SECTCEXP])
3302 return 65536;
3303 else
3304 return pCmdFis[AHCI_CMDFIS_SECTCEXP] << 8 | pCmdFis[AHCI_CMDFIS_SECTC];
3305 }
3306 else
3307 {
3308 if (!pCmdFis[AHCI_CMDFIS_SECTC])
3309 return 256;
3310 else
3311 return pCmdFis[AHCI_CMDFIS_SECTC];
3312 }
3313}
3314
3315static uint64_t ahciGetSector(PAHCIPort pAhciPort, uint8_t *pCmdFis, bool fLBA48)
3316{
3317 uint64_t iLBA;
3318 if (pCmdFis[AHCI_CMDFIS_HEAD] & 0x40)
3319 {
3320 /* any LBA variant */
3321 if (fLBA48)
3322 {
3323 /* LBA48 */
3324 iLBA = ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLHEXP] << 40) |
3325 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLLEXP] << 32) |
3326 ((uint64_t)pCmdFis[AHCI_CMDFIS_SECTNEXP] << 24) |
3327 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLH] << 16) |
3328 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLL] << 8) |
3329 pCmdFis[AHCI_CMDFIS_SECTN];
3330 }
3331 else
3332 {
3333 /* LBA */
3334 iLBA = ((pCmdFis[AHCI_CMDFIS_HEAD] & 0x0f) << 24) | (pCmdFis[AHCI_CMDFIS_CYLH] << 16) |
3335 (pCmdFis[AHCI_CMDFIS_CYLL] << 8) | pCmdFis[AHCI_CMDFIS_SECTN];
3336 }
3337 }
3338 else
3339 {
3340 /* CHS */
3341 iLBA = ((pCmdFis[AHCI_CMDFIS_CYLH] << 8) | pCmdFis[AHCI_CMDFIS_CYLL]) * pAhciPort->PCHSGeometry.cHeads * pAhciPort->PCHSGeometry.cSectors +
3342 (pCmdFis[AHCI_CMDFIS_HEAD] & 0x0f) * pAhciPort->PCHSGeometry.cSectors +
3343 (pCmdFis[AHCI_CMDFIS_SECTN] - 1);
3344 }
3345 return iLBA;
3346}
3347
3348static uint64_t ahciGetSectorQueued(uint8_t *pCmdFis)
3349{
3350 uint64_t uLBA;
3351
3352 uLBA = ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLHEXP] << 40) |
3353 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLLEXP] << 32) |
3354 ((uint64_t)pCmdFis[AHCI_CMDFIS_SECTNEXP] << 24) |
3355 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLH] << 16) |
3356 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLL] << 8) |
3357 pCmdFis[AHCI_CMDFIS_SECTN];
3358
3359 return uLBA;
3360}
3361
3362DECLINLINE(uint32_t) ahciGetNSectorsQueued(uint8_t *pCmdFis)
3363{
3364 if (!pCmdFis[AHCI_CMDFIS_FETEXP] && !pCmdFis[AHCI_CMDFIS_FET])
3365 return 65536;
3366 else
3367 return pCmdFis[AHCI_CMDFIS_FETEXP] << 8 | pCmdFis[AHCI_CMDFIS_FET];
3368}
3369
3370/**
3371 * Copy from guest to host memory worker.
3372 *
3373 * @copydoc AHCIR3MEMCOPYCALLBACK
3374 */
3375static DECLCALLBACK(void) ahciR3CopyBufferFromGuestWorker(PAHCI pThis, RTGCPHYS GCPhys, PRTSGBUF pSgBuf,
3376 size_t cbCopy, size_t *pcbSkip)
3377{
3378 size_t cbSkipped = RT_MIN(cbCopy, *pcbSkip);
3379 cbCopy -= cbSkipped;
3380 GCPhys += cbSkipped;
3381 *pcbSkip -= cbSkipped;
3382
3383 while (cbCopy)
3384 {
3385 size_t cbSeg = cbCopy;
3386 void *pvSeg = RTSgBufGetNextSegment(pSgBuf, &cbSeg);
3387
3388 AssertPtr(pvSeg);
3389 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, pvSeg, cbSeg);
3390 GCPhys += cbSeg;
3391 cbCopy -= cbSeg;
3392 }
3393}
3394
3395/**
3396 * Copy from host to guest memory worker.
3397 *
3398 * @copydoc AHCIR3MEMCOPYCALLBACK
3399 */
3400static DECLCALLBACK(void) ahciR3CopyBufferToGuestWorker(PAHCI pThis, RTGCPHYS GCPhys, PRTSGBUF pSgBuf,
3401 size_t cbCopy, size_t *pcbSkip)
3402{
3403 size_t cbSkipped = RT_MIN(cbCopy, *pcbSkip);
3404 cbCopy -= cbSkipped;
3405 GCPhys += cbSkipped;
3406 *pcbSkip -= cbSkipped;
3407
3408 while (cbCopy)
3409 {
3410 size_t cbSeg = cbCopy;
3411 void *pvSeg = RTSgBufGetNextSegment(pSgBuf, &cbSeg);
3412
3413 AssertPtr(pvSeg);
3414 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhys, pvSeg, cbSeg);
3415 GCPhys += cbSeg;
3416 cbCopy -= cbSeg;
3417 }
3418}
3419
3420/**
3421 * Walks the PRDTL list copying data between the guest and host memory buffers.
3422 *
3423 * @returns Amount of bytes copied.
3424 * @param pThis The AHCI controller device instance.
3425 * @param pAhciReq AHCI request structure.
3426 * @param pfnCopyWorker The copy method to apply for each guest buffer.
3427 * @param pSgBuf The host S/G buffer.
3428 * @param cbSkip How many bytes to skip in advance before starting to copy.
3429 * @param cbCopy How many bytes to copy.
3430 */
3431static size_t ahciR3PrdtlWalk(PAHCI pThis, PAHCIREQ pAhciReq,
3432 PAHCIR3MEMCOPYCALLBACK pfnCopyWorker,
3433 PRTSGBUF pSgBuf, size_t cbSkip, size_t cbCopy)
3434{
3435 RTGCPHYS GCPhysPrdtl = pAhciReq->GCPhysPrdtl;
3436 unsigned cPrdtlEntries = pAhciReq->cPrdtlEntries;
3437 size_t cbCopied = 0;
3438
3439 /*
3440 * Add the amount to skip to the host buffer size to avoid a
3441 * few conditionals later on.
3442 */
3443 cbCopy += cbSkip;
3444
3445 AssertMsgReturn(cPrdtlEntries > 0, ("Copying 0 bytes is not possible\n"), 0);
3446
3447 do
3448 {
3449 SGLEntry aPrdtlEntries[32];
3450 uint32_t cPrdtlEntriesRead = cPrdtlEntries < RT_ELEMENTS(aPrdtlEntries)
3451 ? cPrdtlEntries
3452 : RT_ELEMENTS(aPrdtlEntries);
3453
3454 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhysPrdtl, &aPrdtlEntries[0],
3455 cPrdtlEntriesRead * sizeof(SGLEntry));
3456
3457 for (uint32_t i = 0; (i < cPrdtlEntriesRead) && cbCopy; i++)
3458 {
3459 RTGCPHYS GCPhysAddrDataBase = AHCI_RTGCPHYS_FROM_U32(aPrdtlEntries[i].u32DBAUp, aPrdtlEntries[i].u32DBA);
3460 uint32_t cbThisCopy = (aPrdtlEntries[i].u32DescInf & SGLENTRY_DESCINF_DBC) + 1;
3461
3462 cbThisCopy = (uint32_t)RT_MIN(cbThisCopy, cbCopy);
3463
3464 /* Copy into SG entry. */
3465 pfnCopyWorker(pThis, GCPhysAddrDataBase, pSgBuf, cbThisCopy, &cbSkip);
3466
3467 cbCopy -= cbThisCopy;
3468 cbCopied += cbThisCopy;
3469 }
3470
3471 GCPhysPrdtl += cPrdtlEntriesRead * sizeof(SGLEntry);
3472 cPrdtlEntries -= cPrdtlEntriesRead;
3473 } while (cPrdtlEntries && cbCopy);
3474
3475 if (cbCopied < cbCopy)
3476 pAhciReq->fFlags |= AHCI_REQ_OVERFLOW;
3477
3478 return cbCopied;
3479}
3480
3481/**
3482 * Copies a data buffer into the S/G buffer set up by the guest.
3483 *
3484 * @returns Amount of bytes copied to the PRDTL.
3485 * @param pThis The AHCI controller device instance.
3486 * @param pAhciReq AHCI request structure.
3487 * @param pSgBuf The S/G buffer to copy from.
3488 * @param cbSkip How many bytes to skip in advance before starting to copy.
3489 * @param cbCopy How many bytes to copy.
3490 */
3491static size_t ahciR3CopySgBufToPrdtl(PAHCI pThis, PAHCIREQ pAhciReq, PRTSGBUF pSgBuf,
3492 size_t cbSkip, size_t cbCopy)
3493{
3494 return ahciR3PrdtlWalk(pThis, pAhciReq, ahciR3CopyBufferToGuestWorker,
3495 pSgBuf, cbSkip, cbCopy);
3496}
3497
3498/**
3499 * Copies the S/G buffer into a data buffer.
3500 *
3501 * @returns Amount of bytes copied from the PRDTL.
3502 * @param pThis The AHCI controller device instance.
3503 * @param pAhciReq AHCI request structure.
3504 * @param pSgBuf The S/G buffer to copy into.
3505 * @param cbSkip How many bytes to skip in advance before starting to copy.
3506 * @param cbCopy How many bytes to copy.
3507 */
3508static size_t ahciR3CopySgBufFromPrdtl(PAHCI pThis, PAHCIREQ pAhciReq, PRTSGBUF pSgBuf,
3509 size_t cbSkip, size_t cbCopy)
3510{
3511 return ahciR3PrdtlWalk(pThis, pAhciReq, ahciR3CopyBufferFromGuestWorker,
3512 pSgBuf, cbSkip, cbCopy);
3513}
3514
3515/**
3516 * Copy a simple memory buffer to the guest memory buffer.
3517 *
3518 * @returns Amount of bytes copied from the PRDTL.
3519 * @param pThis The AHCI controller device instance.
3520 * @param pAhciReq AHCI request structure.
3521 * @param pvSrc The buffer to copy from.
3522 * @param cbSrc How many bytes to copy.
3523 * @param cbSkip How many bytes to skip initially.
3524 */
3525static size_t ahciR3CopyBufferToPrdtl(PAHCI pThis, PAHCIREQ pAhciReq, const void *pvSrc,
3526 size_t cbSrc, size_t cbSkip)
3527{
3528 RTSGSEG Seg;
3529 RTSGBUF SgBuf;
3530 Seg.pvSeg = (void *)pvSrc;
3531 Seg.cbSeg = cbSrc;
3532 RTSgBufInit(&SgBuf, &Seg, 1);
3533 return ahciR3CopySgBufToPrdtl(pThis, pAhciReq, &SgBuf, cbSkip, cbSrc);
3534}
3535
3536/**
3537 * Calculates the size of the guest buffer described by the PRDT.
3538 *
3539 * @returns VBox status code.
3540 * @param pThis The AHCI controller device instance.
3541 * @param pAhciReq AHCI request structure.
3542 * @param pcbPrdt Where to store the size of the guest buffer.
3543 */
3544static int ahciR3PrdtQuerySize(PAHCI pThis, PAHCIREQ pAhciReq, size_t *pcbPrdt)
3545{
3546 RTGCPHYS GCPhysPrdtl = pAhciReq->GCPhysPrdtl;
3547 unsigned cPrdtlEntries = pAhciReq->cPrdtlEntries;
3548 size_t cbPrdt = 0;
3549
3550 do
3551 {
3552 SGLEntry aPrdtlEntries[32];
3553 uint32_t cPrdtlEntriesRead = cPrdtlEntries < RT_ELEMENTS(aPrdtlEntries)
3554 ? cPrdtlEntries
3555 : RT_ELEMENTS(aPrdtlEntries);
3556
3557 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhysPrdtl, &aPrdtlEntries[0],
3558 cPrdtlEntriesRead * sizeof(SGLEntry));
3559
3560 for (uint32_t i = 0; i < cPrdtlEntriesRead; i++)
3561 cbPrdt += (aPrdtlEntries[i].u32DescInf & SGLENTRY_DESCINF_DBC) + 1;
3562
3563 GCPhysPrdtl += cPrdtlEntriesRead * sizeof(SGLEntry);
3564 cPrdtlEntries -= cPrdtlEntriesRead;
3565 } while (cPrdtlEntries);
3566
3567 *pcbPrdt = cbPrdt;
3568 return VINF_SUCCESS;
3569}
3570
3571/**
3572 * Cancels all active tasks on the port.
3573 *
3574 * @returns Whether all active tasks were canceled.
3575 * @param pAhciPort The AHCI port.
3576 */
3577static bool ahciCancelActiveTasks(PAHCIPort pAhciPort)
3578{
3579 if (pAhciPort->pDrvMediaEx)
3580 {
3581 int rc = pAhciPort->pDrvMediaEx->pfnIoReqCancelAll(pAhciPort->pDrvMediaEx);
3582 AssertRC(rc);
3583 }
3584 return true; /* always true for now because tasks don't use guest memory as the buffer which makes canceling a task impossible. */
3585}
3586
3587/**
3588 * Creates the array of ranges to trim.
3589 *
3590 * @returns VBox status code.
3591 * @param pAhciPort AHCI port state.
3592 * @param pAhciReq The request handling the TRIM request.
3593 * @param idxRangeStart Index of the first range to start copying.
3594 * @param paRanges Where to store the ranges.
3595 * @param cRanges Number of ranges fitting into the array.
3596 * @param pcRanges Where to store the amount of ranges actually copied on success.
3597 */
3598static int ahciTrimRangesCreate(PAHCIPort pAhciPort, PAHCIREQ pAhciReq, uint32_t idxRangeStart,
3599 PRTRANGE paRanges, uint32_t cRanges, uint32_t *pcRanges)
3600{
3601 SGLEntry aPrdtlEntries[32];
3602 uint64_t aRanges[64];
3603 uint32_t cPrdtlEntries = pAhciReq->cPrdtlEntries;
3604 RTGCPHYS GCPhysPrdtl = pAhciReq->GCPhysPrdtl;
3605 PPDMDEVINS pDevIns = pAhciPort->CTX_SUFF(pDevIns);
3606 int rc = VERR_PDM_MEDIAEX_IOBUF_OVERFLOW;
3607 uint32_t idxRange = 0;
3608
3609 LogFlowFunc(("pAhciPort=%#p pAhciReq=%#p\n", pAhciPort, pAhciReq));
3610
3611 AssertMsgReturn(pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_DISCARD, ("This is not a trim request\n"), VERR_INVALID_PARAMETER);
3612
3613 if (!cPrdtlEntries)
3614 pAhciReq->fFlags |= AHCI_REQ_OVERFLOW;
3615
3616 /* Convert the ranges from ATA to our format. */
3617 while ( cPrdtlEntries
3618 && idxRange < cRanges)
3619 {
3620 uint32_t cPrdtlEntriesRead = RT_MIN(cPrdtlEntries, RT_ELEMENTS(aPrdtlEntries));
3621
3622 rc = VINF_SUCCESS;
3623 PDMDevHlpPhysRead(pDevIns, GCPhysPrdtl, &aPrdtlEntries[0], cPrdtlEntriesRead * sizeof(SGLEntry));
3624
3625 for (uint32_t i = 0; i < cPrdtlEntriesRead && idxRange < cRanges; i++)
3626 {
3627 RTGCPHYS GCPhysAddrDataBase = AHCI_RTGCPHYS_FROM_U32(aPrdtlEntries[i].u32DBAUp, aPrdtlEntries[i].u32DBA);
3628 uint32_t cbThisCopy = (aPrdtlEntries[i].u32DescInf & SGLENTRY_DESCINF_DBC) + 1;
3629
3630 cbThisCopy = RT_MIN(cbThisCopy, sizeof(aRanges));
3631
3632 /* Copy into buffer. */
3633 PDMDevHlpPhysRead(pDevIns, GCPhysAddrDataBase, aRanges, cbThisCopy);
3634
3635 for (unsigned idxRangeSrc = 0; idxRangeSrc < RT_ELEMENTS(aRanges) && idxRange < cRanges; idxRangeSrc++)
3636 {
3637 /* Skip range if told to do so. */
3638 if (!idxRangeStart)
3639 {
3640 aRanges[idxRangeSrc] = RT_H2LE_U64(aRanges[idxRangeSrc]);
3641 if (AHCI_RANGE_LENGTH_GET(aRanges[idxRangeSrc]) != 0)
3642 {
3643 paRanges[idxRange].offStart = (aRanges[idxRangeSrc] & AHCI_RANGE_LBA_MASK) * pAhciPort->cbSector;
3644 paRanges[idxRange].cbRange = AHCI_RANGE_LENGTH_GET(aRanges[idxRangeSrc]) * pAhciPort->cbSector;
3645 idxRange++;
3646 }
3647 else
3648 break;
3649 }
3650 else
3651 idxRangeStart--;
3652 }
3653 }
3654
3655 GCPhysPrdtl += cPrdtlEntriesRead * sizeof(SGLEntry);
3656 cPrdtlEntries -= cPrdtlEntriesRead;
3657 }
3658
3659 *pcRanges = idxRange;
3660
3661 LogFlowFunc(("returns rc=%Rrc\n", rc));
3662 return rc;
3663}
3664
3665/**
3666 * Allocates a new AHCI request.
3667 *
3668 * @returns A new AHCI request structure or NULL if out of memory.
3669 * @param pAhciPort The AHCI port.
3670 * @param uTag The tag to assign.
3671 */
3672static PAHCIREQ ahciR3ReqAlloc(PAHCIPort pAhciPort, uint32_t uTag)
3673{
3674 PAHCIREQ pAhciReq = NULL;
3675 PDMMEDIAEXIOREQ hIoReq = NULL;
3676
3677 int rc = pAhciPort->pDrvMediaEx->pfnIoReqAlloc(pAhciPort->pDrvMediaEx, &hIoReq, (void **)&pAhciReq,
3678 uTag, PDMIMEDIAEX_F_SUSPEND_ON_RECOVERABLE_ERR);
3679 if (RT_SUCCESS(rc))
3680 {
3681 pAhciReq->hIoReq = hIoReq;
3682 pAhciReq->fMapped = false;
3683 }
3684 else
3685 pAhciReq = NULL;
3686 return pAhciReq;
3687}
3688
3689/**
3690 * Frees a given AHCI request structure.
3691 *
3692 * @returns nothing.
3693 * @param pAhciPort The AHCI port.
3694 * @param pAhciReq The request to free.
3695 */
3696static void ahciR3ReqFree(PAHCIPort pAhciPort, PAHCIREQ pAhciReq)
3697{
3698 if ( pAhciReq
3699 && !(pAhciReq->fFlags & AHCI_REQ_IS_ON_STACK))
3700 {
3701 int rc = pAhciPort->pDrvMediaEx->pfnIoReqFree(pAhciPort->pDrvMediaEx, pAhciReq->hIoReq);
3702 AssertRC(rc);
3703 }
3704}
3705
3706/**
3707 * Complete a data transfer task by freeing all occupied resources
3708 * and notifying the guest.
3709 *
3710 * @returns Flag whether the given request was canceled inbetween;
3711 *
3712 * @param pAhciPort Pointer to the port where to request completed.
3713 * @param pAhciReq Pointer to the task which finished.
3714 * @param rcReq IPRT status code of the completed request.
3715 */
3716static bool ahciTransferComplete(PAHCIPort pAhciPort, PAHCIREQ pAhciReq, int rcReq)
3717{
3718 bool fCanceled = false;
3719
3720 LogFlowFunc(("pAhciPort=%p pAhciReq=%p rcReq=%d\n",
3721 pAhciPort, pAhciReq, rcReq));
3722
3723 VBOXDD_AHCI_REQ_COMPLETED(pAhciReq, rcReq, pAhciReq->uOffset, pAhciReq->cbTransfer);
3724
3725 if (pAhciReq->fMapped)
3726 PDMDevHlpPhysReleasePageMappingLock(pAhciPort->CTX_SUFF(pAhci)->CTX_SUFF(pDevIns),
3727 &pAhciReq->PgLck);
3728
3729 if (rcReq != VERR_PDM_MEDIAEX_IOREQ_CANCELED)
3730 {
3731 if (pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_READ)
3732 pAhciPort->Led.Actual.s.fReading = 0;
3733 else if (pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_WRITE)
3734 pAhciPort->Led.Actual.s.fWriting = 0;
3735 else if (pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_DISCARD)
3736 pAhciPort->Led.Actual.s.fWriting = 0;
3737 else if (pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_SCSI)
3738 {
3739 pAhciPort->Led.Actual.s.fWriting = 0;
3740 pAhciPort->Led.Actual.s.fReading = 0;
3741 }
3742
3743 if (RT_FAILURE(rcReq))
3744 {
3745 /* Log the error. */
3746 if (pAhciPort->cErrors++ < MAX_LOG_REL_ERRORS)
3747 {
3748 if (pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_FLUSH)
3749 LogRel(("AHCI#%uP%u: Flush returned rc=%Rrc\n",
3750 pAhciPort->CTX_SUFF(pDevIns)->iInstance, pAhciPort->iLUN, rcReq));
3751 else if (pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_DISCARD)
3752 LogRel(("AHCI#%uP%u: Trim returned rc=%Rrc\n",
3753 pAhciPort->CTX_SUFF(pDevIns)->iInstance, pAhciPort->iLUN, rcReq));
3754 else
3755 LogRel(("AHCI#%uP%u: %s at offset %llu (%zu bytes left) returned rc=%Rrc\n",
3756 pAhciPort->CTX_SUFF(pDevIns)->iInstance, pAhciPort->iLUN,
3757 pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_READ
3758 ? "Read"
3759 : "Write",
3760 pAhciReq->uOffset,
3761 pAhciReq->cbTransfer, rcReq));
3762 }
3763
3764 ahciReqSetStatus(pAhciReq, ID_ERR, ATA_STAT_READY | ATA_STAT_ERR);
3765 /*
3766 * We have to duplicate the request here as the underlying I/O
3767 * request will be freed later.
3768 */
3769 PAHCIREQ pReqDup = (PAHCIREQ)RTMemDup(pAhciReq, sizeof(AHCIREQ));
3770 if ( pReqDup
3771 && !ASMAtomicCmpXchgPtr(&pAhciPort->pTaskErr, pReqDup, NULL))
3772 RTMemFree(pReqDup);
3773 }
3774 else
3775 {
3776 /* Status will be set already for non I/O requests. */
3777 if (pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_SCSI)
3778 {
3779 if (pAhciReq->u8ScsiSts == SCSI_STATUS_OK)
3780 {
3781 ahciReqSetStatus(pAhciReq, 0, ATA_STAT_READY | ATA_STAT_SEEK);
3782 pAhciReq->cmdFis[AHCI_CMDFIS_SECTN] = (pAhciReq->cmdFis[AHCI_CMDFIS_SECTN] & ~7)
3783 | ((pAhciReq->fFlags & AHCI_REQ_XFER_2_HOST) ? ATAPI_INT_REASON_IO : 0)
3784 | (!pAhciReq->cbTransfer ? ATAPI_INT_REASON_CD : 0);
3785 }
3786 else
3787 {
3788 ahciReqSetStatus(pAhciReq, pAhciPort->abATAPISense[2] << 4, ATA_STAT_READY | ATA_STAT_ERR);
3789 pAhciReq->cmdFis[AHCI_CMDFIS_SECTN] = (pAhciReq->cmdFis[AHCI_CMDFIS_SECTN] & ~7) |
3790 ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
3791 pAhciReq->cbTransfer = 0;
3792 LogFlowFunc(("SCSI request completed with %u status\n", pAhciReq->u8ScsiSts));
3793 }
3794 }
3795 else if (pAhciReq->enmType != PDMMEDIAEXIOREQTYPE_INVALID)
3796 ahciReqSetStatus(pAhciReq, 0, ATA_STAT_READY | ATA_STAT_SEEK);
3797
3798 /* Write updated command header into memory of the guest. */
3799 uint32_t u32PRDBC = 0;
3800 if (pAhciReq->enmType != PDMMEDIAEXIOREQTYPE_INVALID)
3801 {
3802 size_t cbXfer = 0;
3803 int rc = pAhciPort->pDrvMediaEx->pfnIoReqQueryXferSize(pAhciPort->pDrvMediaEx, pAhciReq->hIoReq, &cbXfer);
3804 AssertRC(rc);
3805 u32PRDBC = (uint32_t)RT_MIN(cbXfer, pAhciReq->cbTransfer);
3806 }
3807 else
3808 u32PRDBC = (uint32_t)pAhciReq->cbTransfer;
3809
3810 PDMDevHlpPCIPhysWrite(pAhciPort->CTX_SUFF(pDevIns), pAhciReq->GCPhysCmdHdrAddr + RT_UOFFSETOF(CmdHdr, u32PRDBC),
3811 &u32PRDBC, sizeof(u32PRDBC));
3812
3813 if (pAhciReq->fFlags & AHCI_REQ_OVERFLOW)
3814 {
3815 /*
3816 * The guest tried to transfer more data than there is space in the buffer.
3817 * Terminate task and set the overflow bit.
3818 */
3819 /* Notify the guest. */
3820 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_OFS);
3821 if (pAhciPort->regIE & AHCI_PORT_IE_OFE)
3822 ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN, VERR_IGNORED);
3823 }
3824 }
3825
3826 /*
3827 * Make a copy of the required data now and free the request. Otherwise the guest
3828 * might issue a new request with the same tag and we run into a conflict when allocating
3829 * a new request with the same tag later on.
3830 */
3831 uint32_t fFlags = pAhciReq->fFlags;
3832 uint32_t uTag = pAhciReq->uTag;
3833 size_t cbTransfer = pAhciReq->cbTransfer;
3834 bool fRead = pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_READ;
3835 uint8_t cmdFis[AHCI_CMDFIS_TYPE_H2D_SIZE];
3836 memcpy(&cmdFis[0], &pAhciReq->cmdFis[0], sizeof(cmdFis));
3837
3838 ahciR3ReqFree(pAhciPort, pAhciReq);
3839
3840 /* Post a PIO setup FIS first if this is a PIO command which transfers data. */
3841 if (fFlags & AHCI_REQ_PIO_DATA)
3842 ahciSendPioSetupFis(pAhciPort, cbTransfer, &cmdFis[0], fRead, false /* fInterrupt */);
3843
3844 if (fFlags & AHCI_REQ_CLEAR_SACT)
3845 {
3846 if (RT_SUCCESS(rcReq) && !ASMAtomicReadPtrT(&pAhciPort->pTaskErr, PAHCIREQ))
3847 ASMAtomicOrU32(&pAhciPort->u32QueuedTasksFinished, RT_BIT_32(uTag));
3848 }
3849
3850 if (fFlags & AHCI_REQ_IS_QUEUED)
3851 {
3852 /*
3853 * Always raise an interrupt after task completion; delaying
3854 * this (interrupt coalescing) increases latency and has a significant
3855 * impact on performance (see @bugref{5071})
3856 */
3857 ahciSendSDBFis(pAhciPort, 0, true);
3858 }
3859 else
3860 ahciSendD2HFis(pAhciPort, uTag, &cmdFis[0], true);
3861 }
3862 else
3863 {
3864 /*
3865 * Task was canceled, do the cleanup but DO NOT access the guest memory!
3866 * The guest might use it for other things now because it doesn't know about that task anymore.
3867 */
3868 fCanceled = true;
3869
3870 /* Leave a log message about the canceled request. */
3871 if (pAhciPort->cErrors++ < MAX_LOG_REL_ERRORS)
3872 {
3873 if (pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_FLUSH)
3874 LogRel(("AHCI#%uP%u: Canceled flush returned rc=%Rrc\n",
3875 pAhciPort->CTX_SUFF(pDevIns)->iInstance, pAhciPort->iLUN, rcReq));
3876 else if (pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_DISCARD)
3877 LogRel(("AHCI#%uP%u: Canceled trim returned rc=%Rrc\n",
3878 pAhciPort->CTX_SUFF(pDevIns)->iInstance,pAhciPort->iLUN, rcReq));
3879 else
3880 LogRel(("AHCI#%uP%u: Canceled %s at offset %llu (%zu bytes left) returned rc=%Rrc\n",
3881 pAhciPort->CTX_SUFF(pDevIns)->iInstance, pAhciPort->iLUN,
3882 pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_READ
3883 ? "read"
3884 : "write",
3885 pAhciReq->uOffset,
3886 pAhciReq->cbTransfer, rcReq));
3887 }
3888
3889 ahciR3ReqFree(pAhciPort, pAhciReq);
3890 }
3891
3892 /*
3893 * Decrement the active task counter as the last step or we might run into a
3894 * hang during power off otherwise (see @bugref{7859}).
3895 * Before it could happen that we signal PDM that we are done while we still have to
3896 * copy the data to the guest but EMT might be busy destroying the driver chains
3897 * below us while we have to delegate copying data to EMT instead of doing it
3898 * on this thread.
3899 */
3900 ASMAtomicDecU32(&pAhciPort->cTasksActive);
3901
3902 if (pAhciPort->cTasksActive == 0 && pAhciPort->pAhciR3->fSignalIdle)
3903 PDMDevHlpAsyncNotificationCompleted(pAhciPort->pDevInsR3);
3904
3905 return fCanceled;
3906}
3907
3908/**
3909 * @interface_method_impl{PDMIMEDIAEXPORT,pfnIoReqCopyFromBuf}
3910 */
3911static DECLCALLBACK(int) ahciR3IoReqCopyFromBuf(PPDMIMEDIAEXPORT pInterface, PDMMEDIAEXIOREQ hIoReq,
3912 void *pvIoReqAlloc, uint32_t offDst, PRTSGBUF pSgBuf,
3913 size_t cbCopy)
3914{
3915 RT_NOREF1(hIoReq);
3916 PAHCIPort pAhciPort = RT_FROM_MEMBER(pInterface, AHCIPort, IMediaExPort);
3917 int rc = VINF_SUCCESS;
3918 PAHCIREQ pIoReq = (PAHCIREQ)pvIoReqAlloc;
3919
3920 ahciR3CopySgBufToPrdtl(pAhciPort->CTX_SUFF(pAhci), pIoReq, pSgBuf, offDst, cbCopy);
3921
3922 if (pIoReq->fFlags & AHCI_REQ_OVERFLOW)
3923 rc = VERR_PDM_MEDIAEX_IOBUF_OVERFLOW;
3924
3925 return rc;
3926}
3927
3928/**
3929 * @interface_method_impl{PDMIMEDIAEXPORT,pfnIoReqCopyToBuf}
3930 */
3931static DECLCALLBACK(int) ahciR3IoReqCopyToBuf(PPDMIMEDIAEXPORT pInterface, PDMMEDIAEXIOREQ hIoReq,
3932 void *pvIoReqAlloc, uint32_t offSrc, PRTSGBUF pSgBuf,
3933 size_t cbCopy)
3934{
3935 RT_NOREF1(hIoReq);
3936 PAHCIPort pAhciPort = RT_FROM_MEMBER(pInterface, AHCIPort, IMediaExPort);
3937 int rc = VINF_SUCCESS;
3938 PAHCIREQ pIoReq = (PAHCIREQ)pvIoReqAlloc;
3939
3940 ahciR3CopySgBufFromPrdtl(pAhciPort->CTX_SUFF(pAhci), pIoReq, pSgBuf, offSrc, cbCopy);
3941 if (pIoReq->fFlags & AHCI_REQ_OVERFLOW)
3942 rc = VERR_PDM_MEDIAEX_IOBUF_UNDERRUN;
3943
3944 return rc;
3945}
3946
3947/**
3948 * @interface_method_impl{PDMIMEDIAEXPORT,pfnIoReqQueryBuf}
3949 */
3950static DECLCALLBACK(int) ahciR3IoReqQueryBuf(PPDMIMEDIAEXPORT pInterface, PDMMEDIAEXIOREQ hIoReq,
3951 void *pvIoReqAlloc, void **ppvBuf, size_t *pcbBuf)
3952{
3953 RT_NOREF(hIoReq);
3954 int rc = VERR_NOT_SUPPORTED;
3955 PAHCIPort pAhciPort = RT_FROM_MEMBER(pInterface, AHCIPort, IMediaExPort);
3956 PAHCIREQ pIoReq = (PAHCIREQ)pvIoReqAlloc;
3957 PAHCI pThis = pAhciPort->CTX_SUFF(pAhci);
3958
3959 /* Only allow single 4KB page aligned buffers at the moment. */
3960 if ( pIoReq->cPrdtlEntries == 1
3961 && pIoReq->cbTransfer == _4K)
3962 {
3963 RTGCPHYS GCPhysPrdt = pIoReq->GCPhysPrdtl;
3964 SGLEntry PrdtEntry;
3965
3966 PDMDevHlpPhysRead(pThis->pDevInsR3, GCPhysPrdt, &PrdtEntry, sizeof(SGLEntry));
3967
3968 RTGCPHYS GCPhysAddrDataBase = AHCI_RTGCPHYS_FROM_U32(PrdtEntry.u32DBAUp, PrdtEntry.u32DBA);
3969 uint32_t cbData = (PrdtEntry.u32DescInf & SGLENTRY_DESCINF_DBC) + 1;
3970
3971 if ( cbData >= _4K
3972 && !(GCPhysAddrDataBase & (_4K - 1)))
3973 {
3974 rc = PDMDevHlpPhysGCPhys2CCPtr(pThis->pDevInsR3, GCPhysAddrDataBase,
3975 0, ppvBuf, &pIoReq->PgLck);
3976 if (RT_SUCCESS(rc))
3977 {
3978 pIoReq->fMapped = true;
3979 *pcbBuf = cbData;
3980 }
3981 else
3982 rc = VERR_NOT_SUPPORTED;
3983 }
3984 }
3985
3986 return rc;
3987}
3988
3989/**
3990 * @interface_method_impl{PDMIMEDIAEXPORT,pfnIoReqQueryDiscardRanges}
3991 */
3992static DECLCALLBACK(int) ahciR3IoReqQueryDiscardRanges(PPDMIMEDIAEXPORT pInterface, PDMMEDIAEXIOREQ hIoReq,
3993 void *pvIoReqAlloc, uint32_t idxRangeStart,
3994 uint32_t cRanges, PRTRANGE paRanges,
3995 uint32_t *pcRanges)
3996{
3997 RT_NOREF1(hIoReq);
3998 PAHCIPort pAhciPort = RT_FROM_MEMBER(pInterface, AHCIPort, IMediaExPort);
3999 PAHCIREQ pIoReq = (PAHCIREQ)pvIoReqAlloc;
4000
4001 return ahciTrimRangesCreate(pAhciPort, pIoReq, idxRangeStart, paRanges, cRanges, pcRanges);
4002}
4003
4004/**
4005 * @interface_method_impl{PDMIMEDIAEXPORT,pfnIoReqCompleteNotify}
4006 */
4007static DECLCALLBACK(int) ahciR3IoReqCompleteNotify(PPDMIMEDIAEXPORT pInterface, PDMMEDIAEXIOREQ hIoReq,
4008 void *pvIoReqAlloc, int rcReq)
4009{
4010 RT_NOREF(hIoReq);
4011 PAHCIPort pAhciPort = RT_FROM_MEMBER(pInterface, AHCIPort, IMediaExPort);
4012 ahciTransferComplete(pAhciPort, (PAHCIREQ)pvIoReqAlloc, rcReq);
4013 return VINF_SUCCESS;
4014}
4015
4016/**
4017 * @interface_method_impl{PDMIMEDIAEXPORT,pfnIoReqStateChanged}
4018 */
4019static DECLCALLBACK(void) ahciR3IoReqStateChanged(PPDMIMEDIAEXPORT pInterface, PDMMEDIAEXIOREQ hIoReq,
4020 void *pvIoReqAlloc, PDMMEDIAEXIOREQSTATE enmState)
4021{
4022 RT_NOREF2(hIoReq, pvIoReqAlloc);
4023 PAHCIPort pAhciPort = RT_FROM_MEMBER(pInterface, AHCIPort, IMediaExPort);
4024
4025 switch (enmState)
4026 {
4027 case PDMMEDIAEXIOREQSTATE_SUSPENDED:
4028 {
4029 /* Make sure the request is not accounted for so the VM can suspend successfully. */
4030 uint32_t cTasksActive = ASMAtomicDecU32(&pAhciPort->cTasksActive);
4031 if (!cTasksActive && pAhciPort->pAhciR3->fSignalIdle)
4032 PDMDevHlpAsyncNotificationCompleted(pAhciPort->pDevInsR3);
4033 break;
4034 }
4035 case PDMMEDIAEXIOREQSTATE_ACTIVE:
4036 /* Make sure the request is accounted for so the VM suspends only when the request is complete. */
4037 ASMAtomicIncU32(&pAhciPort->cTasksActive);
4038 break;
4039 default:
4040 AssertMsgFailed(("Invalid request state given %u\n", enmState));
4041 }
4042}
4043
4044/**
4045 * @interface_method_impl{PDMIMEDIAEXPORT,pfnMediumEjected}
4046 */
4047static DECLCALLBACK(void) ahciR3MediumEjected(PPDMIMEDIAEXPORT pInterface)
4048{
4049 PAHCIPort pAhciPort = RT_FROM_MEMBER(pInterface, AHCIPort, IMediaExPort);
4050 PAHCI pThis = pAhciPort->CTX_SUFF(pAhci);
4051
4052 if (pThis->pMediaNotify)
4053 {
4054 int rc = VMR3ReqCallNoWait(PDMDevHlpGetVM(pThis->CTX_SUFF(pDevIns)), VMCPUID_ANY,
4055 (PFNRT)pThis->pMediaNotify->pfnEjected, 2,
4056 pThis->pMediaNotify, pAhciPort->iLUN);
4057 AssertRC(rc);
4058 }
4059}
4060
4061/**
4062 * Process an non read/write ATA command.
4063 *
4064 * @returns The direction of the data transfer
4065 * @param pAhciPort The AHCI port of the request.
4066 * @param pAhciReq The AHCI request state.
4067 * @param pCmdFis Pointer to the command FIS.
4068 */
4069static PDMMEDIAEXIOREQTYPE ahciProcessCmd(PAHCIPort pAhciPort, PAHCIREQ pAhciReq, uint8_t *pCmdFis)
4070{
4071 PDMMEDIAEXIOREQTYPE enmType = PDMMEDIAEXIOREQTYPE_INVALID;
4072 bool fLBA48 = false;
4073
4074 AssertMsg(pCmdFis[AHCI_CMDFIS_TYPE] == AHCI_CMDFIS_TYPE_H2D, ("FIS is not a host to device Fis!!\n"));
4075
4076 pAhciReq->cbTransfer = 0;
4077
4078 switch (pCmdFis[AHCI_CMDFIS_CMD])
4079 {
4080 case ATA_IDENTIFY_DEVICE:
4081 {
4082 if (pAhciPort->pDrvMedia && !pAhciPort->fATAPI)
4083 {
4084 uint16_t u16Temp[256];
4085
4086 /* Fill the buffer. */
4087 ahciIdentifySS(pAhciPort, u16Temp);
4088
4089 /* Copy the buffer. */
4090 size_t cbCopied = ahciR3CopyBufferToPrdtl(pAhciPort->CTX_SUFF(pAhci), pAhciReq,
4091 &u16Temp[0], sizeof(u16Temp), 0 /* cbSkip */);
4092
4093 pAhciReq->fFlags |= AHCI_REQ_PIO_DATA;
4094 pAhciReq->cbTransfer = cbCopied;
4095 ahciReqSetStatus(pAhciReq, 0, ATA_STAT_READY | ATA_STAT_SEEK);
4096 }
4097 else
4098 ahciReqSetStatus(pAhciReq, ABRT_ERR, ATA_STAT_READY | ATA_STAT_SEEK | ATA_STAT_ERR);
4099 break;
4100 }
4101 case ATA_READ_NATIVE_MAX_ADDRESS_EXT:
4102 case ATA_READ_NATIVE_MAX_ADDRESS:
4103 break;
4104 case ATA_SET_FEATURES:
4105 {
4106 switch (pCmdFis[AHCI_CMDFIS_FET])
4107 {
4108 case 0x02: /* write cache enable */
4109 case 0xaa: /* read look-ahead enable */
4110 case 0x55: /* read look-ahead disable */
4111 case 0xcc: /* reverting to power-on defaults enable */
4112 case 0x66: /* reverting to power-on defaults disable */
4113 ahciReqSetStatus(pAhciReq, 0, ATA_STAT_READY | ATA_STAT_SEEK);
4114 break;
4115 case 0x82: /* write cache disable */
4116 enmType = PDMMEDIAEXIOREQTYPE_FLUSH;
4117 break;
4118 case 0x03:
4119 {
4120 /* set transfer mode */
4121 Log2(("%s: transfer mode %#04x\n", __FUNCTION__, pCmdFis[AHCI_CMDFIS_SECTC]));
4122 switch (pCmdFis[AHCI_CMDFIS_SECTC] & 0xf8)
4123 {
4124 case 0x00: /* PIO default */
4125 case 0x08: /* PIO mode */
4126 break;
4127 case ATA_MODE_MDMA: /* MDMA mode */
4128 pAhciPort->uATATransferMode = (pCmdFis[AHCI_CMDFIS_SECTC] & 0xf8) | RT_MIN(pCmdFis[AHCI_CMDFIS_SECTC] & 0x07, ATA_MDMA_MODE_MAX);
4129 break;
4130 case ATA_MODE_UDMA: /* UDMA mode */
4131 pAhciPort->uATATransferMode = (pCmdFis[AHCI_CMDFIS_SECTC] & 0xf8) | RT_MIN(pCmdFis[AHCI_CMDFIS_SECTC] & 0x07, ATA_UDMA_MODE_MAX);
4132 break;
4133 }
4134 ahciReqSetStatus(pAhciReq, 0, ATA_STAT_READY | ATA_STAT_SEEK);
4135 break;
4136 }
4137 default:
4138 ahciReqSetStatus(pAhciReq, ABRT_ERR, ATA_STAT_READY | ATA_STAT_ERR);
4139 }
4140 break;
4141 }
4142 case ATA_DEVICE_RESET:
4143 {
4144 if (!pAhciPort->fATAPI)
4145 ahciReqSetStatus(pAhciReq, ABRT_ERR, ATA_STAT_READY | ATA_STAT_ERR);
4146 else
4147 {
4148 /* Reset the device. */
4149 ahciDeviceReset(pAhciPort, pAhciReq);
4150 }
4151 break;
4152 }
4153 case ATA_FLUSH_CACHE_EXT:
4154 case ATA_FLUSH_CACHE:
4155 enmType = PDMMEDIAEXIOREQTYPE_FLUSH;
4156 break;
4157 case ATA_PACKET:
4158 if (!pAhciPort->fATAPI)
4159 ahciReqSetStatus(pAhciReq, ABRT_ERR, ATA_STAT_READY | ATA_STAT_ERR);
4160 else
4161 enmType = PDMMEDIAEXIOREQTYPE_SCSI;
4162 break;
4163 case ATA_IDENTIFY_PACKET_DEVICE:
4164 if (!pAhciPort->fATAPI)
4165 ahciReqSetStatus(pAhciReq, ABRT_ERR, ATA_STAT_READY | ATA_STAT_ERR);
4166 else
4167 {
4168 size_t cbData;
4169 ahciR3AtapiIdentify(pAhciReq, pAhciPort, 512, &cbData);
4170
4171 pAhciReq->fFlags |= AHCI_REQ_PIO_DATA;
4172 pAhciReq->cbTransfer = cbData;
4173 pAhciReq->cmdFis[AHCI_CMDFIS_SECTN] = (pAhciReq->cmdFis[AHCI_CMDFIS_SECTN] & ~7)
4174 | ((pAhciReq->fFlags & AHCI_REQ_XFER_2_HOST) ? ATAPI_INT_REASON_IO : 0)
4175 | (!pAhciReq->cbTransfer ? ATAPI_INT_REASON_CD : 0);
4176
4177 ahciReqSetStatus(pAhciReq, 0, ATA_STAT_READY | ATA_STAT_SEEK);
4178 }
4179 break;
4180 case ATA_SET_MULTIPLE_MODE:
4181 if ( pCmdFis[AHCI_CMDFIS_SECTC] != 0
4182 && ( pCmdFis[AHCI_CMDFIS_SECTC] > ATA_MAX_MULT_SECTORS
4183 || (pCmdFis[AHCI_CMDFIS_SECTC] & (pCmdFis[AHCI_CMDFIS_SECTC] - 1)) != 0))
4184 ahciReqSetStatus(pAhciReq, ABRT_ERR, ATA_STAT_READY | ATA_STAT_ERR);
4185 else
4186 {
4187 Log2(("%s: set multi sector count to %d\n", __FUNCTION__, pCmdFis[AHCI_CMDFIS_SECTC]));
4188 pAhciPort->cMultSectors = pCmdFis[AHCI_CMDFIS_SECTC];
4189 ahciReqSetStatus(pAhciReq, 0, ATA_STAT_READY | ATA_STAT_SEEK);
4190 }
4191 break;
4192 case ATA_STANDBY_IMMEDIATE:
4193 break; /* Do nothing. */
4194 case ATA_CHECK_POWER_MODE:
4195 pAhciReq->cmdFis[AHCI_CMDFIS_SECTC] = 0xff; /* drive active or idle */
4196 RT_FALL_THRU();
4197 case ATA_INITIALIZE_DEVICE_PARAMETERS:
4198 case ATA_IDLE_IMMEDIATE:
4199 case ATA_RECALIBRATE:
4200 case ATA_NOP:
4201 case ATA_READ_VERIFY_SECTORS_EXT:
4202 case ATA_READ_VERIFY_SECTORS:
4203 case ATA_READ_VERIFY_SECTORS_WITHOUT_RETRIES:
4204 case ATA_SLEEP:
4205 ahciReqSetStatus(pAhciReq, 0, ATA_STAT_READY | ATA_STAT_SEEK);
4206 break;
4207 case ATA_READ_DMA_EXT:
4208 fLBA48 = true;
4209 RT_FALL_THRU();
4210 case ATA_READ_DMA:
4211 {
4212 pAhciReq->cbTransfer = ahciGetNSectors(pCmdFis, fLBA48) * pAhciPort->cbSector;
4213 pAhciReq->uOffset = ahciGetSector(pAhciPort, pCmdFis, fLBA48) * pAhciPort->cbSector;
4214 enmType = PDMMEDIAEXIOREQTYPE_READ;
4215 break;
4216 }
4217 case ATA_WRITE_DMA_EXT:
4218 fLBA48 = true;
4219 RT_FALL_THRU();
4220 case ATA_WRITE_DMA:
4221 {
4222 pAhciReq->cbTransfer = ahciGetNSectors(pCmdFis, fLBA48) * pAhciPort->cbSector;
4223 pAhciReq->uOffset = ahciGetSector(pAhciPort, pCmdFis, fLBA48) * pAhciPort->cbSector;
4224 enmType = PDMMEDIAEXIOREQTYPE_WRITE;
4225 break;
4226 }
4227 case ATA_READ_FPDMA_QUEUED:
4228 {
4229 pAhciReq->cbTransfer = ahciGetNSectorsQueued(pCmdFis) * pAhciPort->cbSector;
4230 pAhciReq->uOffset = ahciGetSectorQueued(pCmdFis) * pAhciPort->cbSector;
4231 pAhciReq->fFlags |= AHCI_REQ_IS_QUEUED;
4232 enmType = PDMMEDIAEXIOREQTYPE_READ;
4233 break;
4234 }
4235 case ATA_WRITE_FPDMA_QUEUED:
4236 {
4237 pAhciReq->cbTransfer = ahciGetNSectorsQueued(pCmdFis) * pAhciPort->cbSector;
4238 pAhciReq->uOffset = ahciGetSectorQueued(pCmdFis) * pAhciPort->cbSector;
4239 pAhciReq->fFlags |= AHCI_REQ_IS_QUEUED;
4240 enmType = PDMMEDIAEXIOREQTYPE_WRITE;
4241 break;
4242 }
4243 case ATA_READ_LOG_EXT:
4244 {
4245 size_t cbLogRead = ((pCmdFis[AHCI_CMDFIS_SECTCEXP] << 8) | pCmdFis[AHCI_CMDFIS_SECTC]) * 512;
4246 unsigned offLogRead = ((pCmdFis[AHCI_CMDFIS_CYLLEXP] << 8) | pCmdFis[AHCI_CMDFIS_CYLL]) * 512;
4247 unsigned iPage = pCmdFis[AHCI_CMDFIS_SECTN];
4248
4249 LogFlow(("Trying to read %zu bytes starting at offset %u from page %u\n", cbLogRead, offLogRead, iPage));
4250
4251 uint8_t aBuf[512];
4252
4253 memset(aBuf, 0, sizeof(aBuf));
4254
4255 if (offLogRead + cbLogRead <= sizeof(aBuf))
4256 {
4257 switch (iPage)
4258 {
4259 case 0x10:
4260 {
4261 LogFlow(("Reading error page\n"));
4262 PAHCIREQ pTaskErr = ASMAtomicXchgPtrT(&pAhciPort->pTaskErr, NULL, PAHCIREQ);
4263 if (pTaskErr)
4264 {
4265 aBuf[0] = (pTaskErr->fFlags & AHCI_REQ_IS_QUEUED) ? pTaskErr->uTag : (1 << 7);
4266 aBuf[2] = pTaskErr->cmdFis[AHCI_CMDFIS_STS];
4267 aBuf[3] = pTaskErr->cmdFis[AHCI_CMDFIS_ERR];
4268 aBuf[4] = pTaskErr->cmdFis[AHCI_CMDFIS_SECTN];
4269 aBuf[5] = pTaskErr->cmdFis[AHCI_CMDFIS_CYLL];
4270 aBuf[6] = pTaskErr->cmdFis[AHCI_CMDFIS_CYLH];
4271 aBuf[7] = pTaskErr->cmdFis[AHCI_CMDFIS_HEAD];
4272 aBuf[8] = pTaskErr->cmdFis[AHCI_CMDFIS_SECTNEXP];
4273 aBuf[9] = pTaskErr->cmdFis[AHCI_CMDFIS_CYLLEXP];
4274 aBuf[10] = pTaskErr->cmdFis[AHCI_CMDFIS_CYLHEXP];
4275 aBuf[12] = pTaskErr->cmdFis[AHCI_CMDFIS_SECTC];
4276 aBuf[13] = pTaskErr->cmdFis[AHCI_CMDFIS_SECTCEXP];
4277
4278 /* Calculate checksum */
4279 uint8_t uChkSum = 0;
4280 for (unsigned i = 0; i < RT_ELEMENTS(aBuf)-1; i++)
4281 uChkSum += aBuf[i];
4282
4283 aBuf[511] = (uint8_t)-(int8_t)uChkSum;
4284
4285 /* Finally free the error task state structure because it is completely unused now. */
4286 RTMemFree(pTaskErr);
4287 }
4288
4289 /*
4290 * Reading this log page results in an abort of all outstanding commands
4291 * and clearing the SActive register and TaskFile register.
4292 *
4293 * See SATA2 1.2 spec chapter 4.2.3.4
4294 */
4295 bool fAbortedAll = ahciCancelActiveTasks(pAhciPort);
4296 Assert(fAbortedAll); NOREF(fAbortedAll);
4297 ahciSendSDBFis(pAhciPort, 0xffffffff, true);
4298
4299 break;
4300 }
4301 }
4302
4303 /* Copy the buffer. */
4304 size_t cbCopied = ahciR3CopyBufferToPrdtl(pAhciPort->CTX_SUFF(pAhci), pAhciReq,
4305 &aBuf[offLogRead], cbLogRead, 0 /* cbSkip */);
4306
4307 pAhciReq->fFlags |= AHCI_REQ_PIO_DATA;
4308 pAhciReq->cbTransfer = cbCopied;
4309 }
4310
4311 break;
4312 }
4313 case ATA_DATA_SET_MANAGEMENT:
4314 {
4315 if (pAhciPort->fTrimEnabled)
4316 {
4317 /* Check that the trim bit is set and all other bits are 0. */
4318 if ( !(pAhciReq->cmdFis[AHCI_CMDFIS_FET] & UINT16_C(0x01))
4319 || (pAhciReq->cmdFis[AHCI_CMDFIS_FET] & ~UINT16_C(0x1)))
4320 ahciReqSetStatus(pAhciReq, ABRT_ERR, ATA_STAT_READY | ATA_STAT_ERR);
4321 else
4322 enmType = PDMMEDIAEXIOREQTYPE_DISCARD;
4323 break;
4324 }
4325 /* else: fall through and report error to the guest. */
4326 }
4327 RT_FALL_THRU();
4328 /* All not implemented commands go below. */
4329 case ATA_SECURITY_FREEZE_LOCK:
4330 case ATA_SMART:
4331 case ATA_NV_CACHE:
4332 case ATA_IDLE:
4333 case ATA_TRUSTED_RECEIVE_DMA: /* Windows 8+ */
4334 ahciReqSetStatus(pAhciReq, ABRT_ERR, ATA_STAT_READY | ATA_STAT_ERR);
4335 break;
4336 default: /* For debugging purposes. */
4337 AssertMsgFailed(("Unknown command issued (%#x)\n", pCmdFis[AHCI_CMDFIS_CMD]));
4338 ahciReqSetStatus(pAhciReq, ABRT_ERR, ATA_STAT_READY | ATA_STAT_ERR);
4339 }
4340
4341 return enmType;
4342}
4343
4344/**
4345 * Retrieve a command FIS from guest memory.
4346 *
4347 * @returns whether the H2D FIS was successfully read from the guest memory.
4348 * @param pAhciPort The AHCI port of the request.
4349 * @param pAhciReq The state of the actual task.
4350 */
4351static bool ahciPortTaskGetCommandFis(PAHCIPort pAhciPort, PAHCIREQ pAhciReq)
4352{
4353 AssertMsgReturn(pAhciPort->GCPhysAddrClb && pAhciPort->GCPhysAddrFb,
4354 ("%s: GCPhysAddrClb and/or GCPhysAddrFb are 0\n", __FUNCTION__),
4355 false);
4356
4357 /*
4358 * First we are reading the command header pointed to by regCLB.
4359 * From this we get the address of the command table which we are reading too.
4360 * We can process the Command FIS afterwards.
4361 */
4362 CmdHdr cmdHdr;
4363 pAhciReq->GCPhysCmdHdrAddr = pAhciPort->GCPhysAddrClb + pAhciReq->uTag * sizeof(CmdHdr);
4364 LogFlow(("%s: PDMDevHlpPhysRead GCPhysAddrCmdLst=%RGp cbCmdHdr=%u\n", __FUNCTION__,
4365 pAhciReq->GCPhysCmdHdrAddr, sizeof(CmdHdr)));
4366 PDMDevHlpPhysRead(pAhciPort->CTX_SUFF(pDevIns), pAhciReq->GCPhysCmdHdrAddr, &cmdHdr, sizeof(CmdHdr));
4367
4368#ifdef LOG_ENABLED
4369 /* Print some infos about the command header. */
4370 ahciDumpCmdHdrInfo(pAhciPort, &cmdHdr);
4371#endif
4372
4373 RTGCPHYS GCPhysAddrCmdTbl = AHCI_RTGCPHYS_FROM_U32(cmdHdr.u32CmdTblAddrUp, cmdHdr.u32CmdTblAddr);
4374
4375 AssertMsgReturn((cmdHdr.u32DescInf & AHCI_CMDHDR_CFL_MASK) * sizeof(uint32_t) == AHCI_CMDFIS_TYPE_H2D_SIZE,
4376 ("This is not a command FIS!!\n"),
4377 false);
4378
4379 /* Read the command Fis. */
4380 LogFlow(("%s: PDMDevHlpPhysRead GCPhysAddrCmdTbl=%RGp cbCmdFis=%u\n", __FUNCTION__, GCPhysAddrCmdTbl, AHCI_CMDFIS_TYPE_H2D_SIZE));
4381 PDMDevHlpPhysRead(pAhciPort->CTX_SUFF(pDevIns), GCPhysAddrCmdTbl, &pAhciReq->cmdFis[0], AHCI_CMDFIS_TYPE_H2D_SIZE);
4382
4383 AssertMsgReturn(pAhciReq->cmdFis[AHCI_CMDFIS_TYPE] == AHCI_CMDFIS_TYPE_H2D,
4384 ("This is not a command FIS\n"),
4385 false);
4386
4387 /* Set transfer direction. */
4388 pAhciReq->fFlags |= (cmdHdr.u32DescInf & AHCI_CMDHDR_W) ? 0 : AHCI_REQ_XFER_2_HOST;
4389
4390 /* If this is an ATAPI command read the atapi command. */
4391 if (cmdHdr.u32DescInf & AHCI_CMDHDR_A)
4392 {
4393 GCPhysAddrCmdTbl += AHCI_CMDHDR_ACMD_OFFSET;
4394 PDMDevHlpPhysRead(pAhciPort->CTX_SUFF(pDevIns), GCPhysAddrCmdTbl, &pAhciReq->aATAPICmd[0], ATAPI_PACKET_SIZE);
4395 }
4396
4397 /* We "received" the FIS. Clear the BSY bit in regTFD. */
4398 if ((cmdHdr.u32DescInf & AHCI_CMDHDR_C) && (pAhciReq->fFlags & AHCI_REQ_CLEAR_SACT))
4399 {
4400 /*
4401 * We need to send a FIS which clears the busy bit if this is a queued command so that the guest can queue other commands.
4402 * but this FIS does not assert an interrupt
4403 */
4404 ahciSendD2HFis(pAhciPort, pAhciReq->uTag, pAhciReq->cmdFis, false);
4405 pAhciPort->regTFD &= ~AHCI_PORT_TFD_BSY;
4406 }
4407
4408 pAhciReq->GCPhysPrdtl = AHCI_RTGCPHYS_FROM_U32(cmdHdr.u32CmdTblAddrUp, cmdHdr.u32CmdTblAddr) + AHCI_CMDHDR_PRDT_OFFSET;
4409 pAhciReq->cPrdtlEntries = AHCI_CMDHDR_PRDTL_ENTRIES(cmdHdr.u32DescInf);
4410
4411#ifdef LOG_ENABLED
4412 /* Print some infos about the FIS. */
4413 ahciDumpFisInfo(pAhciPort, &pAhciReq->cmdFis[0]);
4414
4415 /* Print the PRDT */
4416 ahciLog(("PRDT address %RGp number of entries %u\n", pAhciReq->GCPhysPrdtl, pAhciReq->cPrdtlEntries));
4417 RTGCPHYS GCPhysPrdtl = pAhciReq->GCPhysPrdtl;
4418
4419 for (unsigned i = 0; i < pAhciReq->cPrdtlEntries; i++)
4420 {
4421 SGLEntry SGEntry;
4422
4423 ahciLog(("Entry %u at address %RGp\n", i, GCPhysPrdtl));
4424 PDMDevHlpPhysRead(pAhciPort->CTX_SUFF(pDevIns), GCPhysPrdtl, &SGEntry, sizeof(SGLEntry));
4425
4426 RTGCPHYS GCPhysDataAddr = AHCI_RTGCPHYS_FROM_U32(SGEntry.u32DBAUp, SGEntry.u32DBA);
4427 ahciLog(("GCPhysAddr=%RGp Size=%u\n", GCPhysDataAddr, SGEntry.u32DescInf & SGLENTRY_DESCINF_DBC));
4428
4429 GCPhysPrdtl += sizeof(SGLEntry);
4430 }
4431#endif
4432
4433 return true;
4434}
4435
4436/**
4437 * Submits a given request for execution.
4438 *
4439 * @returns Flag whether the request was canceled inbetween.
4440 * @param pAhciPort The port the request is for.
4441 * @param pAhciReq The request to submit.
4442 * @param enmType The request type.
4443 */
4444static bool ahciR3ReqSubmit(PAHCIPort pAhciPort, PAHCIREQ pAhciReq, PDMMEDIAEXIOREQTYPE enmType)
4445{
4446 int rc = VINF_SUCCESS;
4447 bool fReqCanceled = false;
4448
4449 VBOXDD_AHCI_REQ_SUBMIT(pAhciReq, pAhciReq->enmType, pAhciReq->uOffset, pAhciReq->cbTransfer);
4450
4451 if (enmType == PDMMEDIAEXIOREQTYPE_FLUSH)
4452 rc = pAhciPort->pDrvMediaEx->pfnIoReqFlush(pAhciPort->pDrvMediaEx, pAhciReq->hIoReq);
4453 else if (enmType == PDMMEDIAEXIOREQTYPE_DISCARD)
4454 {
4455 uint32_t cRangesMax;
4456
4457 /* The data buffer contains LBA range entries. Each range is 8 bytes big. */
4458 if (!pAhciReq->cmdFis[AHCI_CMDFIS_SECTC] && !pAhciReq->cmdFis[AHCI_CMDFIS_SECTCEXP])
4459 cRangesMax = 65536 * 512 / 8;
4460 else
4461 cRangesMax = pAhciReq->cmdFis[AHCI_CMDFIS_SECTC] * 512 / 8;
4462
4463 pAhciPort->Led.Asserted.s.fWriting = pAhciPort->Led.Actual.s.fWriting = 1;
4464 rc = pAhciPort->pDrvMediaEx->pfnIoReqDiscard(pAhciPort->pDrvMediaEx, pAhciReq->hIoReq,
4465 cRangesMax);
4466 }
4467 else if (enmType == PDMMEDIAEXIOREQTYPE_READ)
4468 {
4469 pAhciPort->Led.Asserted.s.fReading = pAhciPort->Led.Actual.s.fReading = 1;
4470 rc = pAhciPort->pDrvMediaEx->pfnIoReqRead(pAhciPort->pDrvMediaEx, pAhciReq->hIoReq,
4471 pAhciReq->uOffset, pAhciReq->cbTransfer);
4472 }
4473 else if (enmType == PDMMEDIAEXIOREQTYPE_WRITE)
4474 {
4475 pAhciPort->Led.Asserted.s.fWriting = pAhciPort->Led.Actual.s.fWriting = 1;
4476 rc = pAhciPort->pDrvMediaEx->pfnIoReqWrite(pAhciPort->pDrvMediaEx, pAhciReq->hIoReq,
4477 pAhciReq->uOffset, pAhciReq->cbTransfer);
4478 }
4479 else if (enmType == PDMMEDIAEXIOREQTYPE_SCSI)
4480 {
4481 size_t cbBuf = 0;
4482
4483 if (pAhciReq->cPrdtlEntries)
4484 rc = ahciR3PrdtQuerySize(pAhciPort->CTX_SUFF(pAhci), pAhciReq, &cbBuf);
4485 pAhciReq->cbTransfer = cbBuf;
4486 if (RT_SUCCESS(rc))
4487 {
4488 if (cbBuf && (pAhciReq->fFlags & AHCI_REQ_XFER_2_HOST))
4489 pAhciPort->Led.Asserted.s.fReading = pAhciPort->Led.Actual.s.fReading = 1;
4490 else if (cbBuf)
4491 pAhciPort->Led.Asserted.s.fWriting = pAhciPort->Led.Actual.s.fWriting = 1;
4492 rc = pAhciPort->pDrvMediaEx->pfnIoReqSendScsiCmd(pAhciPort->pDrvMediaEx, pAhciReq->hIoReq,
4493 0, &pAhciReq->aATAPICmd[0], ATAPI_PACKET_SIZE,
4494 PDMMEDIAEXIOREQSCSITXDIR_UNKNOWN, cbBuf,
4495 &pAhciPort->abATAPISense[0], sizeof(pAhciPort->abATAPISense),
4496 &pAhciReq->u8ScsiSts, 30 * RT_MS_1SEC);
4497 }
4498 }
4499
4500 if (rc == VINF_SUCCESS)
4501 fReqCanceled = ahciTransferComplete(pAhciPort, pAhciReq, VINF_SUCCESS);
4502 else if (rc != VINF_PDM_MEDIAEX_IOREQ_IN_PROGRESS)
4503 fReqCanceled = ahciTransferComplete(pAhciPort, pAhciReq, rc);
4504
4505 return fReqCanceled;
4506}
4507
4508/**
4509 * Prepares the command for execution coping it from guest memory and doing a few
4510 * validation checks on it.
4511 *
4512 * @returns Whether the command was successfully fetched from guest memory and
4513 * can be continued.
4514 * @param pAhciPort The AHCI port the request is for.
4515 * @param pAhciReq Request structure to copy the command to.
4516 */
4517static bool ahciR3CmdPrepare(PAHCIPort pAhciPort, PAHCIREQ pAhciReq)
4518{
4519 /* Set current command slot */
4520 ASMAtomicWriteU32(&pAhciPort->u32CurrentCommandSlot, pAhciReq->uTag);
4521
4522 bool fContinue = ahciPortTaskGetCommandFis(pAhciPort, pAhciReq);
4523 if (fContinue)
4524 {
4525 /* Mark the task as processed by the HBA if this is a queued task so that it doesn't occur in the CI register anymore. */
4526 if (pAhciPort->regSACT & RT_BIT_32(pAhciReq->uTag))
4527 {
4528 pAhciReq->fFlags |= AHCI_REQ_CLEAR_SACT;
4529 ASMAtomicOrU32(&pAhciPort->u32TasksFinished, RT_BIT_32(pAhciReq->uTag));
4530 }
4531
4532 if (pAhciReq->cmdFis[AHCI_CMDFIS_BITS] & AHCI_CMDFIS_C)
4533 {
4534 /*
4535 * It is possible that the request counter can get one higher than the maximum because
4536 * the request counter is decremented after the guest was notified about the completed
4537 * request (see @bugref{7859}). If the completing thread is preempted in between the
4538 * guest might already issue another request before the request counter is decremented
4539 * which would trigger the following assertion incorrectly in the past.
4540 */
4541 AssertLogRelMsg(ASMAtomicReadU32(&pAhciPort->cTasksActive) <= AHCI_NR_COMMAND_SLOTS,
4542 ("AHCI#%uP%u: There are more than %u (+1) requests active",
4543 pAhciPort->CTX_SUFF(pDevIns)->iInstance, pAhciPort->iLUN,
4544 AHCI_NR_COMMAND_SLOTS));
4545 ASMAtomicIncU32(&pAhciPort->cTasksActive);
4546 }
4547 else
4548 {
4549 /* If the reset bit is set put the device into reset state. */
4550 if (pAhciReq->cmdFis[AHCI_CMDFIS_CTL] & AHCI_CMDFIS_CTL_SRST)
4551 {
4552 ahciLog(("%s: Setting device into reset state\n", __FUNCTION__));
4553 pAhciPort->fResetDevice = true;
4554 ahciSendD2HFis(pAhciPort, pAhciReq->uTag, pAhciReq->cmdFis, true);
4555 }
4556 else if (pAhciPort->fResetDevice) /* The bit is not set and we are in a reset state. */
4557 ahciFinishStorageDeviceReset(pAhciPort, pAhciReq);
4558 else /* We are not in a reset state update the control registers. */
4559 AssertMsgFailed(("%s: Update the control register\n", __FUNCTION__));
4560
4561 fContinue = false;
4562 }
4563 }
4564 else
4565 {
4566 /*
4567 * Couldn't find anything in either the AHCI or SATA spec which
4568 * indicates what should be done if the FIS is not read successfully.
4569 * The closest thing is in the state machine, stating that the device
4570 * should go into idle state again (SATA spec 1.0 chapter 8.7.1).
4571 * Do the same here and ignore any corrupt FIS types, after all
4572 * the guest messed up everything and this behavior is undefined.
4573 */
4574 fContinue = false;
4575 }
4576
4577 return fContinue;
4578}
4579
4580/**
4581 * Transmit queue consumer
4582 * Queue a new async task.
4583 *
4584 * @returns Success indicator.
4585 * If false the item will not be removed and the flushing will stop.
4586 * @param pDevIns The device instance.
4587 * @param pItem The item to consume. Upon return this item will be freed.
4588 */
4589static DECLCALLBACK(bool) ahciNotifyQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
4590{
4591 PDEVPORTNOTIFIERQUEUEITEM pNotifierItem = (PDEVPORTNOTIFIERQUEUEITEM)pItem;
4592 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
4593 PAHCIPort pAhciPort = &pThis->ahciPort[pNotifierItem->iPort];
4594 int rc = VINF_SUCCESS;
4595
4596 ahciLog(("%s: Got notification from GC\n", __FUNCTION__));
4597 /* Notify the async IO thread. */
4598 rc = SUPSemEventSignal(pThis->pSupDrvSession, pAhciPort->hEvtProcess);
4599 AssertRC(rc);
4600
4601 return true;
4602}
4603
4604/* The async IO thread for one port. */
4605static DECLCALLBACK(int) ahciAsyncIOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4606{
4607 RT_NOREF(pDevIns);
4608 PAHCIPort pAhciPort = (PAHCIPort)pThread->pvUser;
4609 PAHCI pAhci = pAhciPort->CTX_SUFF(pAhci);
4610 int rc = VINF_SUCCESS;
4611
4612 ahciLog(("%s: Port %d entering async IO loop.\n", __FUNCTION__, pAhciPort->iLUN));
4613
4614 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
4615 return VINF_SUCCESS;
4616
4617 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4618 {
4619 unsigned idx = 0;
4620 uint32_t u32Tasks = 0;
4621 uint32_t u32RegHbaCtrl = 0;
4622
4623 ASMAtomicWriteBool(&pAhciPort->fWrkThreadSleeping, true);
4624 u32Tasks = ASMAtomicXchgU32(&pAhciPort->u32TasksNew, 0);
4625 if (!u32Tasks)
4626 {
4627 Assert(ASMAtomicReadBool(&pAhciPort->fWrkThreadSleeping));
4628 rc = SUPSemEventWaitNoResume(pAhci->pSupDrvSession, pAhciPort->hEvtProcess, RT_INDEFINITE_WAIT);
4629 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
4630 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
4631 break;
4632 LogFlowFunc(("Woken up with rc=%Rrc\n", rc));
4633 u32Tasks = ASMAtomicXchgU32(&pAhciPort->u32TasksNew, 0);
4634 }
4635
4636 ASMAtomicWriteBool(&pAhciPort->fWrkThreadSleeping, false);
4637 ASMAtomicIncU32(&pAhci->cThreadsActive);
4638
4639 /* Check whether the thread should be suspended. */
4640 if (pAhci->fSignalIdle)
4641 {
4642 if (!ASMAtomicDecU32(&pAhci->cThreadsActive))
4643 PDMDevHlpAsyncNotificationCompleted(pAhciPort->pDevInsR3);
4644 continue;
4645 }
4646
4647 /*
4648 * Check whether the global host controller bit is set and go to sleep immediately again
4649 * if it is set.
4650 */
4651 u32RegHbaCtrl = ASMAtomicReadU32(&pAhci->regHbaCtrl);
4652 if ( u32RegHbaCtrl & AHCI_HBA_CTRL_HR
4653 && !ASMAtomicDecU32(&pAhci->cThreadsActive))
4654 {
4655 ahciHBAReset(pAhci);
4656 if (pAhci->fSignalIdle)
4657 PDMDevHlpAsyncNotificationCompleted(pAhciPort->pDevInsR3);
4658 continue;
4659 }
4660
4661 idx = ASMBitFirstSetU32(u32Tasks);
4662 while ( idx
4663 && !pAhciPort->fPortReset)
4664 {
4665 bool fReqCanceled = false;
4666
4667 /* Decrement to get the slot number. */
4668 idx--;
4669 ahciLog(("%s: Processing command at slot %d\n", __FUNCTION__, idx));
4670
4671 PAHCIREQ pAhciReq = ahciR3ReqAlloc(pAhciPort, idx);
4672 if (RT_LIKELY(pAhciReq))
4673 {
4674 pAhciReq->uTag = idx;
4675 pAhciReq->fFlags = 0;
4676
4677 bool fContinue = ahciR3CmdPrepare(pAhciPort, pAhciReq);
4678 if (fContinue)
4679 {
4680 PDMMEDIAEXIOREQTYPE enmType = ahciProcessCmd(pAhciPort, pAhciReq, pAhciReq->cmdFis);
4681 pAhciReq->enmType = enmType;
4682
4683 if (enmType != PDMMEDIAEXIOREQTYPE_INVALID)
4684 fReqCanceled = ahciR3ReqSubmit(pAhciPort, pAhciReq, enmType);
4685 else
4686 fReqCanceled = ahciTransferComplete(pAhciPort, pAhciReq, VINF_SUCCESS);
4687 } /* Command */
4688 else
4689 ahciR3ReqFree(pAhciPort, pAhciReq);
4690 }
4691 else /* !Request allocated, use on stack variant to signal the error. */
4692 {
4693 AHCIREQ Req;
4694 Req.uTag = idx;
4695 Req.fFlags = AHCI_REQ_IS_ON_STACK;
4696 Req.fMapped = false;
4697 Req.cbTransfer = 0;
4698 Req.uOffset = 0;
4699 Req.enmType = PDMMEDIAEXIOREQTYPE_INVALID;
4700
4701 bool fContinue = ahciR3CmdPrepare(pAhciPort, &Req);
4702 if (fContinue)
4703 fReqCanceled = ahciTransferComplete(pAhciPort, &Req, VERR_NO_MEMORY);
4704 }
4705
4706 /*
4707 * Don't process other requests if the last one was canceled,
4708 * the others are not valid anymore.
4709 */
4710 if (fReqCanceled)
4711 break;
4712
4713 u32Tasks &= ~RT_BIT_32(idx); /* Clear task bit. */
4714 idx = ASMBitFirstSetU32(u32Tasks);
4715 } /* while tasks available */
4716
4717 /* Check whether a port reset was active. */
4718 if ( ASMAtomicReadBool(&pAhciPort->fPortReset)
4719 && (pAhciPort->regSCTL & AHCI_PORT_SCTL_DET) == AHCI_PORT_SCTL_DET_NINIT)
4720 ahciPortResetFinish(pAhciPort);
4721
4722 /*
4723 * Check whether a host controller reset is pending and execute the reset
4724 * if this is the last active thread.
4725 */
4726 u32RegHbaCtrl = ASMAtomicReadU32(&pAhci->regHbaCtrl);
4727 uint32_t cThreadsActive = ASMAtomicDecU32(&pAhci->cThreadsActive);
4728 if ( (u32RegHbaCtrl & AHCI_HBA_CTRL_HR)
4729 && !cThreadsActive)
4730 ahciHBAReset(pAhci);
4731
4732 if (!cThreadsActive && pAhci->fSignalIdle)
4733 PDMDevHlpAsyncNotificationCompleted(pAhciPort->pDevInsR3);
4734 } /* While running */
4735
4736 ahciLog(("%s: Port %d async IO thread exiting\n", __FUNCTION__, pAhciPort->iLUN));
4737 return VINF_SUCCESS;
4738}
4739
4740/**
4741 * Unblock the async I/O thread so it can respond to a state change.
4742 *
4743 * @returns VBox status code.
4744 * @param pDevIns The device instance.
4745 * @param pThread The send thread.
4746 */
4747static DECLCALLBACK(int) ahciAsyncIOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4748{
4749 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
4750 PAHCIPort pAhciPort = (PAHCIPort)pThread->pvUser;
4751 return SUPSemEventSignal(pThis->pSupDrvSession, pAhciPort->hEvtProcess);
4752}
4753
4754/* -=-=-=-=- DBGF -=-=-=-=- */
4755
4756/**
4757 * AHCI status info callback.
4758 *
4759 * @param pDevIns The device instance.
4760 * @param pHlp The output helpers.
4761 * @param pszArgs The arguments.
4762 */
4763static DECLCALLBACK(void) ahciR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4764{
4765 RT_NOREF(pszArgs);
4766 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
4767
4768 /*
4769 * Show info.
4770 */
4771 pHlp->pfnPrintf(pHlp,
4772 "%s#%d: mmio=%RGp ports=%u GC=%RTbool R0=%RTbool\n",
4773 pDevIns->pReg->szName,
4774 pDevIns->iInstance,
4775 pThis->MMIOBase,
4776 pThis->cPortsImpl,
4777 pThis->fGCEnabled ? true : false,
4778 pThis->fR0Enabled ? true : false);
4779
4780 /*
4781 * Show global registers.
4782 */
4783 pHlp->pfnPrintf(pHlp, "HbaCap=%#x\n", pThis->regHbaCap);
4784 pHlp->pfnPrintf(pHlp, "HbaCtrl=%#x\n", pThis->regHbaCtrl);
4785 pHlp->pfnPrintf(pHlp, "HbaIs=%#x\n", pThis->regHbaIs);
4786 pHlp->pfnPrintf(pHlp, "HbaPi=%#x\n", pThis->regHbaPi);
4787 pHlp->pfnPrintf(pHlp, "HbaVs=%#x\n", pThis->regHbaVs);
4788 pHlp->pfnPrintf(pHlp, "HbaCccCtl=%#x\n", pThis->regHbaCccCtl);
4789 pHlp->pfnPrintf(pHlp, "HbaCccPorts=%#x\n", pThis->regHbaCccPorts);
4790 pHlp->pfnPrintf(pHlp, "PortsInterrupted=%#x\n", pThis->u32PortsInterrupted);
4791
4792 /*
4793 * Per port data.
4794 */
4795 for (unsigned i = 0; i < pThis->cPortsImpl; i++)
4796 {
4797 PAHCIPort pThisPort = &pThis->ahciPort[i];
4798
4799 pHlp->pfnPrintf(pHlp, "Port %d: device-attached=%RTbool\n",
4800 pThisPort->iLUN, pThisPort->pDrvBase != NULL);
4801 pHlp->pfnPrintf(pHlp, "PortClb=%#x\n", pThisPort->regCLB);
4802 pHlp->pfnPrintf(pHlp, "PortClbU=%#x\n", pThisPort->regCLBU);
4803 pHlp->pfnPrintf(pHlp, "PortFb=%#x\n", pThisPort->regFB);
4804 pHlp->pfnPrintf(pHlp, "PortFbU=%#x\n", pThisPort->regFBU);
4805 pHlp->pfnPrintf(pHlp, "PortIs=%#x\n", pThisPort->regIS);
4806 pHlp->pfnPrintf(pHlp, "PortIe=%#x\n", pThisPort->regIE);
4807 pHlp->pfnPrintf(pHlp, "PortCmd=%#x\n", pThisPort->regCMD);
4808 pHlp->pfnPrintf(pHlp, "PortTfd=%#x\n", pThisPort->regTFD);
4809 pHlp->pfnPrintf(pHlp, "PortSig=%#x\n", pThisPort->regSIG);
4810 pHlp->pfnPrintf(pHlp, "PortSSts=%#x\n", pThisPort->regSSTS);
4811 pHlp->pfnPrintf(pHlp, "PortSCtl=%#x\n", pThisPort->regSCTL);
4812 pHlp->pfnPrintf(pHlp, "PortSErr=%#x\n", pThisPort->regSERR);
4813 pHlp->pfnPrintf(pHlp, "PortSAct=%#x\n", pThisPort->regSACT);
4814 pHlp->pfnPrintf(pHlp, "PortCi=%#x\n", pThisPort->regCI);
4815 pHlp->pfnPrintf(pHlp, "PortPhysClb=%RGp\n", pThisPort->GCPhysAddrClb);
4816 pHlp->pfnPrintf(pHlp, "PortPhysFb=%RGp\n", pThisPort->GCPhysAddrFb);
4817 pHlp->pfnPrintf(pHlp, "PortActTasksActive=%u\n", pThisPort->cTasksActive);
4818 pHlp->pfnPrintf(pHlp, "PortPoweredOn=%RTbool\n", pThisPort->fPoweredOn);
4819 pHlp->pfnPrintf(pHlp, "PortSpunUp=%RTbool\n", pThisPort->fSpunUp);
4820 pHlp->pfnPrintf(pHlp, "PortFirstD2HFisSent=%RTbool\n", pThisPort->fFirstD2HFisSent);
4821 pHlp->pfnPrintf(pHlp, "PortATAPI=%RTbool\n", pThisPort->fATAPI);
4822 pHlp->pfnPrintf(pHlp, "PortTasksFinished=%#x\n", pThisPort->u32TasksFinished);
4823 pHlp->pfnPrintf(pHlp, "PortQueuedTasksFinished=%#x\n", pThisPort->u32QueuedTasksFinished);
4824 pHlp->pfnPrintf(pHlp, "PortTasksNew=%#x\n", pThisPort->u32TasksNew);
4825 pHlp->pfnPrintf(pHlp, "\n");
4826 }
4827}
4828
4829/* -=-=-=-=- Helper -=-=-=-=- */
4830
4831/**
4832 * Checks if all asynchronous I/O is finished, both AHCI and IDE.
4833 *
4834 * Used by ahciR3Reset, ahciR3Suspend and ahciR3PowerOff. ahciR3SavePrep makes
4835 * use of it in strict builds (which is why it's up here).
4836 *
4837 * @returns true if quiesced, false if busy.
4838 * @param pDevIns The device instance.
4839 */
4840static bool ahciR3AllAsyncIOIsFinished(PPDMDEVINS pDevIns)
4841{
4842 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
4843
4844 if (pThis->cThreadsActive)
4845 return false;
4846
4847 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->ahciPort); i++)
4848 {
4849 PAHCIPort pThisPort = &pThis->ahciPort[i];
4850 if (pThisPort->pDrvBase)
4851 {
4852 if ( (pThisPort->cTasksActive != 0)
4853 || (pThisPort->u32TasksNew != 0))
4854 return false;
4855 }
4856 }
4857 return true;
4858}
4859
4860/* -=-=-=-=- Saved State -=-=-=-=- */
4861
4862/**
4863 * @callback_method_impl{FNSSMDEVSAVEPREP}
4864 */
4865static DECLCALLBACK(int) ahciR3SavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4866{
4867 RT_NOREF(pDevIns, pSSM);
4868 Assert(ahciR3AllAsyncIOIsFinished(pDevIns));
4869 return VINF_SUCCESS;
4870}
4871
4872/**
4873 * @callback_method_impl{FNSSMDEVLOADPREP}
4874 */
4875static DECLCALLBACK(int) ahciR3LoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4876{
4877 RT_NOREF(pDevIns, pSSM);
4878 Assert(ahciR3AllAsyncIOIsFinished(pDevIns));
4879 return VINF_SUCCESS;
4880}
4881
4882/**
4883 * @callback_method_impl{FNSSMDEVLIVEEXEC}
4884 */
4885static DECLCALLBACK(int) ahciR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
4886{
4887 RT_NOREF(uPass);
4888 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
4889
4890 /* config. */
4891 SSMR3PutU32(pSSM, pThis->cPortsImpl);
4892 for (uint32_t i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
4893 {
4894 SSMR3PutBool(pSSM, pThis->ahciPort[i].pDrvBase != NULL);
4895 SSMR3PutBool(pSSM, pThis->ahciPort[i].fHotpluggable);
4896 SSMR3PutStrZ(pSSM, pThis->ahciPort[i].szSerialNumber);
4897 SSMR3PutStrZ(pSSM, pThis->ahciPort[i].szFirmwareRevision);
4898 SSMR3PutStrZ(pSSM, pThis->ahciPort[i].szModelNumber);
4899 }
4900
4901 static const char *s_apszIdeEmuPortNames[4] = { "PrimaryMaster", "PrimarySlave", "SecondaryMaster", "SecondarySlave" };
4902 for (uint32_t i = 0; i < RT_ELEMENTS(s_apszIdeEmuPortNames); i++)
4903 {
4904 uint32_t iPort;
4905 int rc = CFGMR3QueryU32Def(pDevIns->pCfg, s_apszIdeEmuPortNames[i], &iPort, i);
4906 AssertRCReturn(rc, rc);
4907 SSMR3PutU32(pSSM, iPort);
4908 }
4909
4910 return VINF_SSM_DONT_CALL_AGAIN;
4911}
4912
4913/**
4914 * @callback_method_impl{FNSSMDEVSAVEEXEC}
4915 */
4916static DECLCALLBACK(int) ahciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4917{
4918 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
4919 uint32_t i;
4920 int rc;
4921
4922 Assert(!pThis->f8ByteMMIO4BytesWrittenSuccessfully);
4923
4924 /* The config */
4925 rc = ahciR3LiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
4926 AssertRCReturn(rc, rc);
4927
4928 /* The main device structure. */
4929 SSMR3PutU32(pSSM, pThis->regHbaCap);
4930 SSMR3PutU32(pSSM, pThis->regHbaCtrl);
4931 SSMR3PutU32(pSSM, pThis->regHbaIs);
4932 SSMR3PutU32(pSSM, pThis->regHbaPi);
4933 SSMR3PutU32(pSSM, pThis->regHbaVs);
4934 SSMR3PutU32(pSSM, pThis->regHbaCccCtl);
4935 SSMR3PutU32(pSSM, pThis->regHbaCccPorts);
4936 SSMR3PutU8(pSSM, pThis->uCccPortNr);
4937 SSMR3PutU64(pSSM, pThis->uCccTimeout);
4938 SSMR3PutU32(pSSM, pThis->uCccNr);
4939 SSMR3PutU32(pSSM, pThis->uCccCurrentNr);
4940 SSMR3PutU32(pSSM, pThis->u32PortsInterrupted);
4941 SSMR3PutBool(pSSM, pThis->fReset);
4942 SSMR3PutBool(pSSM, pThis->f64BitAddr);
4943 SSMR3PutBool(pSSM, pThis->fR0Enabled);
4944 SSMR3PutBool(pSSM, pThis->fGCEnabled);
4945 SSMR3PutBool(pSSM, pThis->fLegacyPortResetMethod);
4946
4947 /* Now every port. */
4948 for (i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
4949 {
4950 Assert(pThis->ahciPort[i].cTasksActive == 0);
4951 SSMR3PutU32(pSSM, pThis->ahciPort[i].regCLB);
4952 SSMR3PutU32(pSSM, pThis->ahciPort[i].regCLBU);
4953 SSMR3PutU32(pSSM, pThis->ahciPort[i].regFB);
4954 SSMR3PutU32(pSSM, pThis->ahciPort[i].regFBU);
4955 SSMR3PutGCPhys(pSSM, pThis->ahciPort[i].GCPhysAddrClb);
4956 SSMR3PutGCPhys(pSSM, pThis->ahciPort[i].GCPhysAddrFb);
4957 SSMR3PutU32(pSSM, pThis->ahciPort[i].regIS);
4958 SSMR3PutU32(pSSM, pThis->ahciPort[i].regIE);
4959 SSMR3PutU32(pSSM, pThis->ahciPort[i].regCMD);
4960 SSMR3PutU32(pSSM, pThis->ahciPort[i].regTFD);
4961 SSMR3PutU32(pSSM, pThis->ahciPort[i].regSIG);
4962 SSMR3PutU32(pSSM, pThis->ahciPort[i].regSSTS);
4963 SSMR3PutU32(pSSM, pThis->ahciPort[i].regSCTL);
4964 SSMR3PutU32(pSSM, pThis->ahciPort[i].regSERR);
4965 SSMR3PutU32(pSSM, pThis->ahciPort[i].regSACT);
4966 SSMR3PutU32(pSSM, pThis->ahciPort[i].regCI);
4967 SSMR3PutU32(pSSM, pThis->ahciPort[i].PCHSGeometry.cCylinders);
4968 SSMR3PutU32(pSSM, pThis->ahciPort[i].PCHSGeometry.cHeads);
4969 SSMR3PutU32(pSSM, pThis->ahciPort[i].PCHSGeometry.cSectors);
4970 SSMR3PutU64(pSSM, pThis->ahciPort[i].cTotalSectors);
4971 SSMR3PutU32(pSSM, pThis->ahciPort[i].cMultSectors);
4972 SSMR3PutU8(pSSM, pThis->ahciPort[i].uATATransferMode);
4973 SSMR3PutBool(pSSM, pThis->ahciPort[i].fResetDevice);
4974 SSMR3PutBool(pSSM, pThis->ahciPort[i].fPoweredOn);
4975 SSMR3PutBool(pSSM, pThis->ahciPort[i].fSpunUp);
4976 SSMR3PutU32(pSSM, pThis->ahciPort[i].u32TasksFinished);
4977 SSMR3PutU32(pSSM, pThis->ahciPort[i].u32QueuedTasksFinished);
4978 SSMR3PutU32(pSSM, pThis->ahciPort[i].u32CurrentCommandSlot);
4979
4980 /* ATAPI saved state. */
4981 SSMR3PutBool(pSSM, pThis->ahciPort[i].fATAPI);
4982 SSMR3PutMem(pSSM, &pThis->ahciPort[i].abATAPISense[0], sizeof(pThis->ahciPort[i].abATAPISense));
4983 }
4984
4985 return SSMR3PutU32(pSSM, UINT32_MAX); /* sanity/terminator */
4986}
4987
4988/**
4989 * Loads a saved legacy ATA emulated device state.
4990 *
4991 * @returns VBox status code.
4992 * @param pSSM The handle to the saved state.
4993 */
4994static int ahciR3LoadLegacyEmulationState(PSSMHANDLE pSSM)
4995{
4996 int rc;
4997 uint32_t u32Version;
4998 uint32_t u32;
4999 uint32_t u32IOBuffer;
5000
5001 /* Test for correct version. */
5002 rc = SSMR3GetU32(pSSM, &u32Version);
5003 AssertRCReturn(rc, rc);
5004 LogFlow(("LoadOldSavedStates u32Version = %d\n", u32Version));
5005
5006 if ( u32Version != ATA_CTL_SAVED_STATE_VERSION
5007 && u32Version != ATA_CTL_SAVED_STATE_VERSION_WITHOUT_FULL_SENSE
5008 && u32Version != ATA_CTL_SAVED_STATE_VERSION_WITHOUT_EVENT_STATUS)
5009 {
5010 AssertMsgFailed(("u32Version=%d\n", u32Version));
5011 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
5012 }
5013
5014 SSMR3Skip(pSSM, 19 + 5 * sizeof(bool) + 8 /* sizeof(BMDMAState) */);
5015
5016 for (uint32_t j = 0; j < 2; j++)
5017 {
5018 SSMR3Skip(pSSM, 88 + 5 * sizeof(bool) );
5019
5020 if (u32Version > ATA_CTL_SAVED_STATE_VERSION_WITHOUT_FULL_SENSE)
5021 SSMR3Skip(pSSM, 64);
5022 else
5023 SSMR3Skip(pSSM, 2);
5024 /** @todo triple-check this hack after passthrough is working */
5025 SSMR3Skip(pSSM, 1);
5026
5027 if (u32Version > ATA_CTL_SAVED_STATE_VERSION_WITHOUT_EVENT_STATUS)
5028 SSMR3Skip(pSSM, 4);
5029
5030 SSMR3Skip(pSSM, sizeof(PDMLED));
5031 SSMR3GetU32(pSSM, &u32IOBuffer);
5032 if (u32IOBuffer)
5033 SSMR3Skip(pSSM, u32IOBuffer);
5034 }
5035
5036 rc = SSMR3GetU32(pSSM, &u32);
5037 if (RT_FAILURE(rc))
5038 return rc;
5039 if (u32 != ~0U)
5040 {
5041 AssertMsgFailed(("u32=%#x expected ~0\n", u32));
5042 rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5043 return rc;
5044 }
5045
5046 return VINF_SUCCESS;
5047}
5048
5049/**
5050 * @callback_method_impl{FNSSMDEVLOADEXEC}
5051 */
5052static DECLCALLBACK(int) ahciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5053{
5054 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
5055 uint32_t u32;
5056 int rc;
5057
5058 if ( uVersion > AHCI_SAVED_STATE_VERSION
5059 || uVersion < AHCI_SAVED_STATE_VERSION_VBOX_30)
5060 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
5061
5062 /* Deal with the priod after removing the saved IDE bits where the saved
5063 state version remained unchanged. */
5064 if ( uVersion == AHCI_SAVED_STATE_VERSION_IDE_EMULATION
5065 && SSMR3HandleRevision(pSSM) >= 79045
5066 && SSMR3HandleRevision(pSSM) < 79201)
5067 uVersion++;
5068
5069 /*
5070 * Check whether we have to resort to the legacy port reset method to
5071 * prevent older BIOS versions from failing after a reset.
5072 */
5073 if (uVersion <= AHCI_SAVED_STATE_VERSION_PRE_PORT_RESET_CHANGES)
5074 pThis->fLegacyPortResetMethod = true;
5075
5076 /* Verify config. */
5077 if (uVersion > AHCI_SAVED_STATE_VERSION_VBOX_30)
5078 {
5079 rc = SSMR3GetU32(pSSM, &u32);
5080 AssertRCReturn(rc, rc);
5081 if (u32 != pThis->cPortsImpl)
5082 {
5083 LogRel(("AHCI: Config mismatch: cPortsImpl - saved=%u config=%u\n", u32, pThis->cPortsImpl));
5084 if ( u32 < pThis->cPortsImpl
5085 || u32 > AHCI_MAX_NR_PORTS_IMPL)
5086 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: cPortsImpl - saved=%u config=%u"),
5087 u32, pThis->cPortsImpl);
5088 }
5089
5090 for (uint32_t i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
5091 {
5092 bool fInUse;
5093 rc = SSMR3GetBool(pSSM, &fInUse);
5094 AssertRCReturn(rc, rc);
5095 if (fInUse != (pThis->ahciPort[i].pDrvBase != NULL))
5096 return SSMR3SetCfgError(pSSM, RT_SRC_POS,
5097 N_("The %s VM is missing a device on port %u. Please make sure the source and target VMs have compatible storage configurations"),
5098 fInUse ? "target" : "source", i );
5099
5100 if (uVersion > AHCI_SAVED_STATE_VERSION_PRE_HOTPLUG_FLAG)
5101 {
5102 bool fHotpluggable;
5103 rc = SSMR3GetBool(pSSM, &fHotpluggable);
5104 AssertRCReturn(rc, rc);
5105 if (fHotpluggable != pThis->ahciPort[i].fHotpluggable)
5106 return SSMR3SetCfgError(pSSM, RT_SRC_POS,
5107 N_("AHCI: Port %u config mismatch: Hotplug flag - saved=%RTbool config=%RTbool\n"),
5108 i, fHotpluggable, pThis->ahciPort[i].fHotpluggable);
5109 }
5110 else
5111 Assert(pThis->ahciPort[i].fHotpluggable);
5112
5113 char szSerialNumber[AHCI_SERIAL_NUMBER_LENGTH+1];
5114 rc = SSMR3GetStrZ(pSSM, szSerialNumber, sizeof(szSerialNumber));
5115 AssertRCReturn(rc, rc);
5116 if (strcmp(szSerialNumber, pThis->ahciPort[i].szSerialNumber))
5117 LogRel(("AHCI: Port %u config mismatch: Serial number - saved='%s' config='%s'\n",
5118 i, szSerialNumber, pThis->ahciPort[i].szSerialNumber));
5119
5120 char szFirmwareRevision[AHCI_FIRMWARE_REVISION_LENGTH+1];
5121 rc = SSMR3GetStrZ(pSSM, szFirmwareRevision, sizeof(szFirmwareRevision));
5122 AssertRCReturn(rc, rc);
5123 if (strcmp(szFirmwareRevision, pThis->ahciPort[i].szFirmwareRevision))
5124 LogRel(("AHCI: Port %u config mismatch: Firmware revision - saved='%s' config='%s'\n",
5125 i, szFirmwareRevision, pThis->ahciPort[i].szFirmwareRevision));
5126
5127 char szModelNumber[AHCI_MODEL_NUMBER_LENGTH+1];
5128 rc = SSMR3GetStrZ(pSSM, szModelNumber, sizeof(szModelNumber));
5129 AssertRCReturn(rc, rc);
5130 if (strcmp(szModelNumber, pThis->ahciPort[i].szModelNumber))
5131 LogRel(("AHCI: Port %u config mismatch: Model number - saved='%s' config='%s'\n",
5132 i, szModelNumber, pThis->ahciPort[i].szModelNumber));
5133 }
5134
5135 static const char *s_apszIdeEmuPortNames[4] = { "PrimaryMaster", "PrimarySlave", "SecondaryMaster", "SecondarySlave" };
5136 for (uint32_t i = 0; i < RT_ELEMENTS(s_apszIdeEmuPortNames); i++)
5137 {
5138 uint32_t iPort;
5139 rc = CFGMR3QueryU32Def(pDevIns->pCfg, s_apszIdeEmuPortNames[i], &iPort, i);
5140 AssertRCReturn(rc, rc);
5141
5142 uint32_t iPortSaved;
5143 rc = SSMR3GetU32(pSSM, &iPortSaved);
5144 AssertRCReturn(rc, rc);
5145
5146 if (iPortSaved != iPort)
5147 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("IDE %s config mismatch: saved=%u config=%u"),
5148 s_apszIdeEmuPortNames[i], iPortSaved, iPort);
5149 }
5150 }
5151
5152 if (uPass == SSM_PASS_FINAL)
5153 {
5154 /* Restore data. */
5155
5156 /* The main device structure. */
5157 SSMR3GetU32(pSSM, &pThis->regHbaCap);
5158 SSMR3GetU32(pSSM, &pThis->regHbaCtrl);
5159 SSMR3GetU32(pSSM, &pThis->regHbaIs);
5160 SSMR3GetU32(pSSM, &pThis->regHbaPi);
5161 SSMR3GetU32(pSSM, &pThis->regHbaVs);
5162 SSMR3GetU32(pSSM, &pThis->regHbaCccCtl);
5163 SSMR3GetU32(pSSM, &pThis->regHbaCccPorts);
5164 SSMR3GetU8(pSSM, &pThis->uCccPortNr);
5165 SSMR3GetU64(pSSM, &pThis->uCccTimeout);
5166 SSMR3GetU32(pSSM, &pThis->uCccNr);
5167 SSMR3GetU32(pSSM, &pThis->uCccCurrentNr);
5168
5169 SSMR3GetU32(pSSM, (uint32_t *)&pThis->u32PortsInterrupted);
5170 SSMR3GetBool(pSSM, &pThis->fReset);
5171 SSMR3GetBool(pSSM, &pThis->f64BitAddr);
5172 SSMR3GetBool(pSSM, &pThis->fR0Enabled);
5173 SSMR3GetBool(pSSM, &pThis->fGCEnabled);
5174 if (uVersion > AHCI_SAVED_STATE_VERSION_PRE_PORT_RESET_CHANGES)
5175 SSMR3GetBool(pSSM, &pThis->fLegacyPortResetMethod);
5176
5177 /* Now every port. */
5178 for (uint32_t i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
5179 {
5180 PAHCIPort pAhciPort = &pThis->ahciPort[i];
5181
5182 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regCLB);
5183 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regCLBU);
5184 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regFB);
5185 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regFBU);
5186 SSMR3GetGCPhys(pSSM, (RTGCPHYS *)&pThis->ahciPort[i].GCPhysAddrClb);
5187 SSMR3GetGCPhys(pSSM, (RTGCPHYS *)&pThis->ahciPort[i].GCPhysAddrFb);
5188 SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].regIS);
5189 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regIE);
5190 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regCMD);
5191 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regTFD);
5192 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regSIG);
5193 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regSSTS);
5194 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regSCTL);
5195 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regSERR);
5196 SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].regSACT);
5197 SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].regCI);
5198 SSMR3GetU32(pSSM, &pThis->ahciPort[i].PCHSGeometry.cCylinders);
5199 SSMR3GetU32(pSSM, &pThis->ahciPort[i].PCHSGeometry.cHeads);
5200 SSMR3GetU32(pSSM, &pThis->ahciPort[i].PCHSGeometry.cSectors);
5201 SSMR3GetU64(pSSM, &pThis->ahciPort[i].cTotalSectors);
5202 SSMR3GetU32(pSSM, &pThis->ahciPort[i].cMultSectors);
5203 SSMR3GetU8(pSSM, &pThis->ahciPort[i].uATATransferMode);
5204 SSMR3GetBool(pSSM, &pThis->ahciPort[i].fResetDevice);
5205
5206 if (uVersion <= AHCI_SAVED_STATE_VERSION_VBOX_30)
5207 SSMR3Skip(pSSM, AHCI_NR_COMMAND_SLOTS * sizeof(uint8_t)); /* no active data here */
5208
5209 if (uVersion < AHCI_SAVED_STATE_VERSION_IDE_EMULATION)
5210 {
5211 /* The old positions in the FIFO, not required. */
5212 SSMR3Skip(pSSM, 2*sizeof(uint8_t));
5213 }
5214 SSMR3GetBool(pSSM, &pThis->ahciPort[i].fPoweredOn);
5215 SSMR3GetBool(pSSM, &pThis->ahciPort[i].fSpunUp);
5216 SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].u32TasksFinished);
5217 SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].u32QueuedTasksFinished);
5218
5219 if (uVersion >= AHCI_SAVED_STATE_VERSION_IDE_EMULATION)
5220 SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].u32CurrentCommandSlot);
5221
5222 if (uVersion > AHCI_SAVED_STATE_VERSION_PRE_ATAPI)
5223 {
5224 SSMR3GetBool(pSSM, &pThis->ahciPort[i].fATAPI);
5225 SSMR3GetMem(pSSM, pThis->ahciPort[i].abATAPISense, sizeof(pThis->ahciPort[i].abATAPISense));
5226 if (uVersion <= AHCI_SAVED_STATE_VERSION_PRE_ATAPI_REMOVE)
5227 {
5228 SSMR3Skip(pSSM, 1); /* cNotifiedMediaChange. */
5229 SSMR3Skip(pSSM, 4); /* MediaEventStatus */
5230 }
5231 }
5232 else if (pThis->ahciPort[i].fATAPI)
5233 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: atapi - saved=false config=true"));
5234
5235 /* Check if we have tasks pending. */
5236 uint32_t fTasksOutstanding = pAhciPort->regCI & ~pAhciPort->u32TasksFinished;
5237 uint32_t fQueuedTasksOutstanding = pAhciPort->regSACT & ~pAhciPort->u32QueuedTasksFinished;
5238
5239 pAhciPort->u32TasksNew = fTasksOutstanding | fQueuedTasksOutstanding;
5240
5241 if (pAhciPort->u32TasksNew)
5242 {
5243 /*
5244 * There are tasks pending. The VM was saved after a task failed
5245 * because of non-fatal error. Set the redo flag.
5246 */
5247 pAhciPort->fRedo = true;
5248 }
5249 }
5250
5251 if (uVersion <= AHCI_SAVED_STATE_VERSION_IDE_EMULATION)
5252 {
5253 for (uint32_t i = 0; i < 2; i++)
5254 {
5255 rc = ahciR3LoadLegacyEmulationState(pSSM);
5256 if(RT_FAILURE(rc))
5257 return rc;
5258 }
5259 }
5260
5261 rc = SSMR3GetU32(pSSM, &u32);
5262 if (RT_FAILURE(rc))
5263 return rc;
5264 AssertMsgReturn(u32 == UINT32_MAX, ("%#x\n", u32), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5265 }
5266
5267 return VINF_SUCCESS;
5268}
5269
5270/* -=-=-=-=- device PDM interface -=-=-=-=- */
5271
5272static DECLCALLBACK(void) ahciR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
5273{
5274 uint32_t i;
5275 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
5276
5277 pAhci->pDevInsRC += offDelta;
5278 pAhci->pHbaCccTimerRC = TMTimerRCPtr(pAhci->pHbaCccTimerR3);
5279 pAhci->pNotifierQueueRC = PDMQueueRCPtr(pAhci->pNotifierQueueR3);
5280
5281 /* Relocate every port. */
5282 for (i = 0; i < RT_ELEMENTS(pAhci->ahciPort); i++)
5283 {
5284 PAHCIPort pAhciPort = &pAhci->ahciPort[i];
5285 pAhciPort->pAhciRC += offDelta;
5286 pAhciPort->pDevInsRC += offDelta;
5287 }
5288}
5289
5290/**
5291 * Configure the attached device for a port.
5292 *
5293 * Used by ahciR3Construct and ahciR3Attach.
5294 *
5295 * @returns VBox status code
5296 * @param pDevIns The device instance data.
5297 * @param pAhciPort The port for which the device is to be configured.
5298 */
5299static int ahciR3ConfigureLUN(PPDMDEVINS pDevIns, PAHCIPort pAhciPort)
5300{
5301 /* Query the media interface. */
5302 pAhciPort->pDrvMedia = PDMIBASE_QUERY_INTERFACE(pAhciPort->pDrvBase, PDMIMEDIA);
5303 AssertMsgReturn(VALID_PTR(pAhciPort->pDrvMedia),
5304 ("AHCI configuration error: LUN#%d misses the basic media interface!\n", pAhciPort->iLUN),
5305 VERR_PDM_MISSING_INTERFACE);
5306
5307 /* Get the extended media interface. */
5308 pAhciPort->pDrvMediaEx = PDMIBASE_QUERY_INTERFACE(pAhciPort->pDrvBase, PDMIMEDIAEX);
5309 AssertMsgReturn(VALID_PTR(pAhciPort->pDrvMediaEx),
5310 ("AHCI configuration error: LUN#%d misses the extended media interface!\n", pAhciPort->iLUN),
5311 VERR_PDM_MISSING_INTERFACE);
5312
5313 /*
5314 * Validate type.
5315 */
5316 PDMMEDIATYPE enmType = pAhciPort->pDrvMedia->pfnGetType(pAhciPort->pDrvMedia);
5317 AssertMsgReturn(enmType == PDMMEDIATYPE_HARD_DISK || enmType == PDMMEDIATYPE_CDROM || enmType == PDMMEDIATYPE_DVD,
5318 ("AHCI configuration error: LUN#%d isn't a disk or cd/dvd. enmType=%u\n", pAhciPort->iLUN, enmType),
5319 VERR_PDM_UNSUPPORTED_BLOCK_TYPE);
5320
5321 int rc = pAhciPort->pDrvMediaEx->pfnIoReqAllocSizeSet(pAhciPort->pDrvMediaEx, sizeof(AHCIREQ));
5322 if (RT_FAILURE(rc))
5323 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
5324 N_("AHCI configuration error: LUN#%u: Failed to set I/O request size!"),
5325 pAhciPort->iLUN);
5326
5327 uint32_t fFeatures = 0;
5328 rc = pAhciPort->pDrvMediaEx->pfnQueryFeatures(pAhciPort->pDrvMediaEx, &fFeatures);
5329 if (RT_FAILURE(rc))
5330 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
5331 N_("AHCI configuration error: LUN#%u: Failed to query features of device"),
5332 pAhciPort->iLUN);
5333
5334 if (fFeatures & PDMIMEDIAEX_FEATURE_F_DISCARD)
5335 pAhciPort->fTrimEnabled = true;
5336
5337 pAhciPort->fATAPI = (enmType == PDMMEDIATYPE_CDROM || enmType == PDMMEDIATYPE_DVD)
5338 && RT_BOOL(fFeatures & PDMIMEDIAEX_FEATURE_F_RAWSCSICMD);
5339 if (pAhciPort->fATAPI)
5340 {
5341 pAhciPort->PCHSGeometry.cCylinders = 0;
5342 pAhciPort->PCHSGeometry.cHeads = 0;
5343 pAhciPort->PCHSGeometry.cSectors = 0;
5344 LogRel(("AHCI: LUN#%d: CD/DVD\n", pAhciPort->iLUN));
5345 }
5346 else
5347 {
5348 pAhciPort->cbSector = pAhciPort->pDrvMedia->pfnGetSectorSize(pAhciPort->pDrvMedia);
5349 pAhciPort->cTotalSectors = pAhciPort->pDrvMedia->pfnGetSize(pAhciPort->pDrvMedia) / pAhciPort->cbSector;
5350 rc = pAhciPort->pDrvMedia->pfnBiosGetPCHSGeometry(pAhciPort->pDrvMedia, &pAhciPort->PCHSGeometry);
5351 if (rc == VERR_PDM_MEDIA_NOT_MOUNTED)
5352 {
5353 pAhciPort->PCHSGeometry.cCylinders = 0;
5354 pAhciPort->PCHSGeometry.cHeads = 16; /*??*/
5355 pAhciPort->PCHSGeometry.cSectors = 63; /*??*/
5356 }
5357 else if (rc == VERR_PDM_GEOMETRY_NOT_SET)
5358 {
5359 pAhciPort->PCHSGeometry.cCylinders = 0; /* autodetect marker */
5360 rc = VINF_SUCCESS;
5361 }
5362 AssertRC(rc);
5363
5364 if ( pAhciPort->PCHSGeometry.cCylinders == 0
5365 || pAhciPort->PCHSGeometry.cHeads == 0
5366 || pAhciPort->PCHSGeometry.cSectors == 0)
5367 {
5368 uint64_t cCylinders = pAhciPort->cTotalSectors / (16 * 63);
5369 pAhciPort->PCHSGeometry.cCylinders = RT_MAX(RT_MIN(cCylinders, 16383), 1);
5370 pAhciPort->PCHSGeometry.cHeads = 16;
5371 pAhciPort->PCHSGeometry.cSectors = 63;
5372 /* Set the disk geometry information. Ignore errors. */
5373 pAhciPort->pDrvMedia->pfnBiosSetPCHSGeometry(pAhciPort->pDrvMedia, &pAhciPort->PCHSGeometry);
5374 rc = VINF_SUCCESS;
5375 }
5376 LogRel(("AHCI: LUN#%d: disk, PCHS=%u/%u/%u, total number of sectors %Ld\n",
5377 pAhciPort->iLUN, pAhciPort->PCHSGeometry.cCylinders,
5378 pAhciPort->PCHSGeometry.cHeads, pAhciPort->PCHSGeometry.cSectors,
5379 pAhciPort->cTotalSectors));
5380 if (pAhciPort->fTrimEnabled)
5381 LogRel(("AHCI: LUN#%d: Enabled TRIM support\n", pAhciPort->iLUN));
5382 }
5383 return rc;
5384}
5385
5386/**
5387 * Callback employed by ahciR3Suspend and ahciR3PowerOff.
5388 *
5389 * @returns true if we've quiesced, false if we're still working.
5390 * @param pDevIns The device instance.
5391 */
5392static DECLCALLBACK(bool) ahciR3IsAsyncSuspendOrPowerOffDone(PPDMDEVINS pDevIns)
5393{
5394 if (!ahciR3AllAsyncIOIsFinished(pDevIns))
5395 return false;
5396
5397 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
5398 ASMAtomicWriteBool(&pThis->fSignalIdle, false);
5399 return true;
5400}
5401
5402/**
5403 * Common worker for ahciR3Suspend and ahciR3PowerOff.
5404 */
5405static void ahciR3SuspendOrPowerOff(PPDMDEVINS pDevIns)
5406{
5407 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
5408
5409 ASMAtomicWriteBool(&pThis->fSignalIdle, true);
5410 if (!ahciR3AllAsyncIOIsFinished(pDevIns))
5411 PDMDevHlpSetAsyncNotification(pDevIns, ahciR3IsAsyncSuspendOrPowerOffDone);
5412 else
5413 ASMAtomicWriteBool(&pThis->fSignalIdle, false);
5414
5415 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->ahciPort); i++)
5416 {
5417 PAHCIPort pThisPort = &pThis->ahciPort[i];
5418 if (pThisPort->pDrvMediaEx)
5419 pThisPort->pDrvMediaEx->pfnNotifySuspend(pThisPort->pDrvMediaEx);
5420 }
5421}
5422
5423/**
5424 * Suspend notification.
5425 *
5426 * @param pDevIns The device instance data.
5427 */
5428static DECLCALLBACK(void) ahciR3Suspend(PPDMDEVINS pDevIns)
5429{
5430 Log(("ahciR3Suspend\n"));
5431 ahciR3SuspendOrPowerOff(pDevIns);
5432}
5433
5434/**
5435 * Resume notification.
5436 *
5437 * @param pDevIns The device instance data.
5438 */
5439static DECLCALLBACK(void) ahciR3Resume(PPDMDEVINS pDevIns)
5440{
5441 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
5442
5443 /*
5444 * Check if one of the ports has pending tasks.
5445 * Queue a notification item again in this case.
5446 */
5447 for (unsigned i = 0; i < RT_ELEMENTS(pAhci->ahciPort); i++)
5448 {
5449 PAHCIPort pAhciPort = &pAhci->ahciPort[i];
5450
5451 if (pAhciPort->u32TasksRedo)
5452 {
5453 PDEVPORTNOTIFIERQUEUEITEM pItem = (PDEVPORTNOTIFIERQUEUEITEM)PDMQueueAlloc(pAhci->CTX_SUFF(pNotifierQueue));
5454 AssertMsg(pItem, ("Allocating item for queue failed\n"));
5455
5456 pAhciPort->u32TasksNew |= pAhciPort->u32TasksRedo;
5457 pAhciPort->u32TasksRedo = 0;
5458
5459 Assert(pAhciPort->fRedo);
5460 pAhciPort->fRedo = false;
5461
5462 pItem->iPort = pAhci->ahciPort[i].iLUN;
5463 PDMQueueInsert(pAhci->CTX_SUFF(pNotifierQueue), (PPDMQUEUEITEMCORE)pItem);
5464 }
5465 }
5466
5467 Log(("%s:\n", __FUNCTION__));
5468}
5469
5470/**
5471 * Initializes the VPD data of a attached device.
5472 *
5473 * @returns VBox status code.
5474 * @param pDevIns The device instance.
5475 * @param pAhciPort The attached device.
5476 * @param pszName Name of the port to get the CFGM node.
5477 */
5478static int ahciR3VpdInit(PPDMDEVINS pDevIns, PAHCIPort pAhciPort, const char *pszName)
5479{
5480
5481 /* Generate a default serial number. */
5482 char szSerial[AHCI_SERIAL_NUMBER_LENGTH+1];
5483 RTUUID Uuid;
5484
5485 int rc = VINF_SUCCESS;
5486 if (pAhciPort->pDrvMedia)
5487 rc = pAhciPort->pDrvMedia->pfnGetUuid(pAhciPort->pDrvMedia, &Uuid);
5488 else
5489 RTUuidClear(&Uuid);
5490
5491 if (RT_FAILURE(rc) || RTUuidIsNull(&Uuid))
5492 {
5493 /* Generate a predictable serial for drives which don't have a UUID. */
5494 RTStrPrintf(szSerial, sizeof(szSerial), "VB%x-1a2b3c4d",
5495 pAhciPort->iLUN);
5496 }
5497 else
5498 RTStrPrintf(szSerial, sizeof(szSerial), "VB%08x-%08x", Uuid.au32[0], Uuid.au32[3]);
5499
5500 /* Get user config if present using defaults otherwise. */
5501 PCFGMNODE pCfgNode = CFGMR3GetChild(pDevIns->pCfg, pszName);
5502 rc = CFGMR3QueryStringDef(pCfgNode, "SerialNumber", pAhciPort->szSerialNumber, sizeof(pAhciPort->szSerialNumber),
5503 szSerial);
5504 if (RT_FAILURE(rc))
5505 {
5506 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
5507 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
5508 N_("AHCI configuration error: \"SerialNumber\" is longer than 20 bytes"));
5509 return PDMDEV_SET_ERROR(pDevIns, rc,
5510 N_("AHCI configuration error: failed to read \"SerialNumber\" as string"));
5511 }
5512
5513 rc = CFGMR3QueryStringDef(pCfgNode, "FirmwareRevision", pAhciPort->szFirmwareRevision, sizeof(pAhciPort->szFirmwareRevision),
5514 "1.0");
5515 if (RT_FAILURE(rc))
5516 {
5517 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
5518 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
5519 N_("AHCI configuration error: \"FirmwareRevision\" is longer than 8 bytes"));
5520 return PDMDEV_SET_ERROR(pDevIns, rc,
5521 N_("AHCI configuration error: failed to read \"FirmwareRevision\" as string"));
5522 }
5523
5524 rc = CFGMR3QueryStringDef(pCfgNode, "ModelNumber", pAhciPort->szModelNumber, sizeof(pAhciPort->szModelNumber),
5525 pAhciPort->fATAPI ? "VBOX CD-ROM" : "VBOX HARDDISK");
5526 if (RT_FAILURE(rc))
5527 {
5528 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
5529 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
5530 N_("AHCI configuration error: \"ModelNumber\" is longer than 40 bytes"));
5531 return PDMDEV_SET_ERROR(pDevIns, rc,
5532 N_("AHCI configuration error: failed to read \"ModelNumber\" as string"));
5533 }
5534
5535 rc = CFGMR3QueryU8Def(pCfgNode, "LogicalSectorsPerPhysical", &pAhciPort->cLogSectorsPerPhysicalExp, 0);
5536 if (RT_FAILURE(rc))
5537 return PDMDEV_SET_ERROR(pDevIns, rc,
5538 N_("AHCI configuration error: failed to read \"LogicalSectorsPerPhysical\" as integer"));
5539 if (pAhciPort->cLogSectorsPerPhysicalExp >= 16)
5540 return PDMDEV_SET_ERROR(pDevIns, rc,
5541 N_("AHCI configuration error: \"LogicalSectorsPerPhysical\" must be between 0 and 15"));
5542
5543 /* There are three other identification strings for CD drives used for INQUIRY */
5544 if (pAhciPort->fATAPI)
5545 {
5546 rc = CFGMR3QueryStringDef(pCfgNode, "ATAPIVendorId", pAhciPort->szInquiryVendorId, sizeof(pAhciPort->szInquiryVendorId),
5547 "VBOX");
5548 if (RT_FAILURE(rc))
5549 {
5550 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
5551 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
5552 N_("AHCI configuration error: \"ATAPIVendorId\" is longer than 16 bytes"));
5553 return PDMDEV_SET_ERROR(pDevIns, rc,
5554 N_("AHCI configuration error: failed to read \"ATAPIVendorId\" as string"));
5555 }
5556
5557 rc = CFGMR3QueryStringDef(pCfgNode, "ATAPIProductId", pAhciPort->szInquiryProductId, sizeof(pAhciPort->szInquiryProductId),
5558 "CD-ROM");
5559 if (RT_FAILURE(rc))
5560 {
5561 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
5562 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
5563 N_("AHCI configuration error: \"ATAPIProductId\" is longer than 16 bytes"));
5564 return PDMDEV_SET_ERROR(pDevIns, rc,
5565 N_("AHCI configuration error: failed to read \"ATAPIProductId\" as string"));
5566 }
5567
5568 rc = CFGMR3QueryStringDef(pCfgNode, "ATAPIRevision", pAhciPort->szInquiryRevision, sizeof(pAhciPort->szInquiryRevision),
5569 "1.0");
5570 if (RT_FAILURE(rc))
5571 {
5572 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
5573 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
5574 N_("AHCI configuration error: \"ATAPIRevision\" is longer than 4 bytes"));
5575 return PDMDEV_SET_ERROR(pDevIns, rc,
5576 N_("AHCI configuration error: failed to read \"ATAPIRevision\" as string"));
5577 }
5578 }
5579
5580 return rc;
5581}
5582
5583
5584/**
5585 * Detach notification.
5586 *
5587 * One harddisk at one port has been unplugged.
5588 * The VM is suspended at this point.
5589 *
5590 * @param pDevIns The device instance.
5591 * @param iLUN The logical unit which is being detached.
5592 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5593 */
5594static DECLCALLBACK(void) ahciR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
5595{
5596 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
5597 PAHCIPort pAhciPort = &pAhci->ahciPort[iLUN];
5598 int rc = VINF_SUCCESS;
5599
5600 Log(("%s:\n", __FUNCTION__));
5601
5602 AssertMsg(iLUN < pAhci->cPortsImpl, ("iLUN=%u", iLUN));
5603 AssertMsgReturnVoid( pAhciPort->fHotpluggable
5604 || (fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
5605 ("AHCI: Port %d is not marked hotpluggable\n", pAhciPort->iLUN));
5606
5607
5608 if (pAhciPort->pAsyncIOThread)
5609 {
5610 int rcThread;
5611 /* Destroy the thread. */
5612 rc = PDMR3ThreadDestroy(pAhciPort->pAsyncIOThread, &rcThread);
5613 if (RT_FAILURE(rc) || RT_FAILURE(rcThread))
5614 AssertMsgFailed(("%s Failed to destroy async IO thread rc=%Rrc rcThread=%Rrc\n", __FUNCTION__, rc, rcThread));
5615
5616 pAhciPort->pAsyncIOThread = NULL;
5617 pAhciPort->fWrkThreadSleeping = true;
5618 }
5619
5620 if (!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG))
5621 {
5622 /*
5623 * Inform the guest about the removed device.
5624 */
5625 pAhciPort->regSSTS = 0;
5626 pAhciPort->regSIG = 0;
5627 /*
5628 * Clear CR bit too to prevent submission of new commands when CI is written
5629 * (AHCI Spec 1.2: 7.4 Interaction of the Command List and Port Change Status).
5630 */
5631 ASMAtomicAndU32(&pAhciPort->regCMD, ~(AHCI_PORT_CMD_CPS | AHCI_PORT_CMD_CR));
5632 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_CPDS | AHCI_PORT_IS_PRCS | AHCI_PORT_IS_PCS);
5633 ASMAtomicOrU32(&pAhciPort->regSERR, AHCI_PORT_SERR_X | AHCI_PORT_SERR_N);
5634 if ( (pAhciPort->regIE & AHCI_PORT_IE_CPDE)
5635 || (pAhciPort->regIE & AHCI_PORT_IE_PCE)
5636 || (pAhciPort->regIE & AHCI_PORT_IE_PRCE))
5637 ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN, VERR_IGNORED);
5638 }
5639
5640 /*
5641 * Zero some important members.
5642 */
5643 pAhciPort->pDrvBase = NULL;
5644 pAhciPort->pDrvMedia = NULL;
5645 pAhciPort->pDrvMediaEx = NULL;
5646}
5647
5648/**
5649 * Attach command.
5650 *
5651 * This is called when we change block driver for one port.
5652 * The VM is suspended at this point.
5653 *
5654 * @returns VBox status code.
5655 * @param pDevIns The device instance.
5656 * @param iLUN The logical unit which is being detached.
5657 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5658 */
5659static DECLCALLBACK(int) ahciR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
5660{
5661 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
5662 PAHCIPort pAhciPort = &pThis->ahciPort[iLUN];
5663 int rc;
5664
5665 Log(("%s:\n", __FUNCTION__));
5666
5667 /* the usual paranoia */
5668 AssertMsg(iLUN < pThis->cPortsImpl, ("iLUN=%u", iLUN));
5669 AssertRelease(!pAhciPort->pDrvBase);
5670 AssertRelease(!pAhciPort->pDrvMedia);
5671 AssertRelease(!pAhciPort->pDrvMediaEx);
5672 Assert(pAhciPort->iLUN == iLUN);
5673
5674 AssertMsgReturn( pAhciPort->fHotpluggable
5675 || (fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
5676 ("AHCI: Port %d is not marked hotpluggable\n", pAhciPort->iLUN),
5677 VERR_INVALID_PARAMETER);
5678
5679 /*
5680 * Try attach the block device and get the interfaces,
5681 * required as well as optional.
5682 */
5683 rc = PDMDevHlpDriverAttach(pDevIns, pAhciPort->iLUN, &pAhciPort->IBase, &pAhciPort->pDrvBase, NULL);
5684 if (RT_SUCCESS(rc))
5685 rc = ahciR3ConfigureLUN(pDevIns, pAhciPort);
5686 else
5687 AssertMsgFailed(("Failed to attach LUN#%d. rc=%Rrc\n", pAhciPort->iLUN, rc));
5688
5689 if (RT_FAILURE(rc))
5690 {
5691 pAhciPort->pDrvBase = NULL;
5692 pAhciPort->pDrvMedia = NULL;
5693 }
5694 else
5695 {
5696 char szName[24];
5697 RTStrPrintf(szName, sizeof(szName), "Port%d", iLUN);
5698
5699 rc = SUPSemEventCreate(pThis->pSupDrvSession, &pAhciPort->hEvtProcess);
5700 if (RT_FAILURE(rc))
5701 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
5702 N_("AHCI: Failed to create SUP event semaphore"));
5703
5704 /* Create the async IO thread. */
5705 rc = PDMDevHlpThreadCreate(pDevIns, &pAhciPort->pAsyncIOThread, pAhciPort, ahciAsyncIOLoop, ahciAsyncIOLoopWakeUp, 0,
5706 RTTHREADTYPE_IO, szName);
5707 if (RT_FAILURE(rc))
5708 return rc;
5709
5710 /*
5711 * Init vendor product data.
5712 */
5713 if (RT_SUCCESS(rc))
5714 rc = ahciR3VpdInit(pDevIns, pAhciPort, szName);
5715
5716 /* Inform the guest about the added device in case of hotplugging. */
5717 if ( RT_SUCCESS(rc)
5718 && !(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG))
5719 {
5720 AssertMsgReturn(pAhciPort->fHotpluggable,
5721 ("AHCI: Port %d is not marked hotpluggable\n", pAhciPort->iLUN),
5722 VERR_NOT_SUPPORTED);
5723
5724 /*
5725 * Initialize registers
5726 */
5727 ASMAtomicOrU32(&pAhciPort->regCMD, AHCI_PORT_CMD_CPS);
5728 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_CPDS | AHCI_PORT_IS_PRCS | AHCI_PORT_IS_PCS);
5729 ASMAtomicOrU32(&pAhciPort->regSERR, AHCI_PORT_SERR_X | AHCI_PORT_SERR_N);
5730
5731 if (pAhciPort->fATAPI)
5732 pAhciPort->regSIG = AHCI_PORT_SIG_ATAPI;
5733 else
5734 pAhciPort->regSIG = AHCI_PORT_SIG_DISK;
5735 pAhciPort->regSSTS = (0x01 << 8) | /* Interface is active. */
5736 (0x02 << 4) | /* Generation 2 (3.0GBps) speed. */
5737 (0x03 << 0); /* Device detected and communication established. */
5738
5739 if ( (pAhciPort->regIE & AHCI_PORT_IE_CPDE)
5740 || (pAhciPort->regIE & AHCI_PORT_IE_PCE)
5741 || (pAhciPort->regIE & AHCI_PORT_IE_PRCE))
5742 ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN, VERR_IGNORED);
5743 }
5744
5745 }
5746
5747 return rc;
5748}
5749
5750/**
5751 * Common reset worker.
5752 *
5753 * @param pDevIns The device instance data.
5754 */
5755static int ahciR3ResetCommon(PPDMDEVINS pDevIns)
5756{
5757 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
5758
5759 ahciHBAReset(pAhci);
5760
5761 /* Hardware reset for the ports. */
5762 for (uint32_t i = 0; i < RT_ELEMENTS(pAhci->ahciPort); i++)
5763 ahciPortHwReset(&pAhci->ahciPort[i]);
5764 return VINF_SUCCESS;
5765}
5766
5767/**
5768 * Callback employed by ahciR3Reset.
5769 *
5770 * @returns true if we've quiesced, false if we're still working.
5771 * @param pDevIns The device instance.
5772 */
5773static DECLCALLBACK(bool) ahciR3IsAsyncResetDone(PPDMDEVINS pDevIns)
5774{
5775 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
5776
5777 if (!ahciR3AllAsyncIOIsFinished(pDevIns))
5778 return false;
5779 ASMAtomicWriteBool(&pThis->fSignalIdle, false);
5780
5781 ahciR3ResetCommon(pDevIns);
5782 return true;
5783}
5784
5785/**
5786 * Reset notification.
5787 *
5788 * @param pDevIns The device instance data.
5789 */
5790static DECLCALLBACK(void) ahciR3Reset(PPDMDEVINS pDevIns)
5791{
5792 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
5793
5794 ASMAtomicWriteBool(&pThis->fSignalIdle, true);
5795 if (!ahciR3AllAsyncIOIsFinished(pDevIns))
5796 PDMDevHlpSetAsyncNotification(pDevIns, ahciR3IsAsyncResetDone);
5797 else
5798 {
5799 ASMAtomicWriteBool(&pThis->fSignalIdle, false);
5800 ahciR3ResetCommon(pDevIns);
5801 }
5802}
5803
5804/**
5805 * Poweroff notification.
5806 *
5807 * @param pDevIns Pointer to the device instance
5808 */
5809static DECLCALLBACK(void) ahciR3PowerOff(PPDMDEVINS pDevIns)
5810{
5811 Log(("achiR3PowerOff\n"));
5812 ahciR3SuspendOrPowerOff(pDevIns);
5813}
5814
5815/**
5816 * Destroy a driver instance.
5817 *
5818 * Most VM resources are freed by the VM. This callback is provided so that any non-VM
5819 * resources can be freed correctly.
5820 *
5821 * @param pDevIns The device instance data.
5822 */
5823static DECLCALLBACK(int) ahciR3Destruct(PPDMDEVINS pDevIns)
5824{
5825 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
5826 int rc = VINF_SUCCESS;
5827 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
5828
5829 /*
5830 * At this point the async I/O thread is suspended and will not enter
5831 * this module again. So, no coordination is needed here and PDM
5832 * will take care of terminating and cleaning up the thread.
5833 */
5834 if (PDMCritSectIsInitialized(&pThis->lock))
5835 {
5836 TMR3TimerDestroy(pThis->CTX_SUFF(pHbaCccTimer));
5837 pThis->CTX_SUFF(pHbaCccTimer) = NULL;
5838
5839 Log(("%s: Destruct every port\n", __FUNCTION__));
5840 for (unsigned iActPort = 0; iActPort < pThis->cPortsImpl; iActPort++)
5841 {
5842 PAHCIPort pAhciPort = &pThis->ahciPort[iActPort];
5843
5844 if (pAhciPort->hEvtProcess != NIL_SUPSEMEVENT)
5845 {
5846 SUPSemEventClose(pThis->pSupDrvSession, pAhciPort->hEvtProcess);
5847 pAhciPort->hEvtProcess = NIL_SUPSEMEVENT;
5848 }
5849 }
5850
5851 PDMR3CritSectDelete(&pThis->lock);
5852 }
5853
5854 return rc;
5855}
5856
5857/**
5858 * @interface_method_impl{PDMDEVREG,pfnConstruct}
5859 */
5860static DECLCALLBACK(int) ahciR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
5861{
5862 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
5863 PPDMIBASE pBase;
5864 int rc = VINF_SUCCESS;
5865 unsigned i = 0;
5866 bool fGCEnabled = false;
5867 bool fR0Enabled = false;
5868 uint32_t cbTotalBufferSize = 0;
5869 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5870
5871 LogFlowFunc(("pThis=%#p\n", pThis));
5872
5873 /*
5874 * Validate and read configuration.
5875 */
5876 if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0"
5877 "R0Enabled\0"
5878 "PrimaryMaster\0"
5879 "PrimarySlave\0"
5880 "SecondaryMaster\0"
5881 "SecondarySlave\0"
5882 "PortCount\0"
5883 "Bootable\0"
5884 "CmdSlotsAvail\0"))
5885 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
5886 N_("AHCI configuration error: unknown option specified"));
5887
5888 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
5889 if (RT_FAILURE(rc))
5890 return PDMDEV_SET_ERROR(pDevIns, rc,
5891 N_("AHCI configuration error: failed to read GCEnabled as boolean"));
5892 Log(("%s: fGCEnabled=%d\n", __FUNCTION__, fGCEnabled));
5893
5894 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
5895 if (RT_FAILURE(rc))
5896 return PDMDEV_SET_ERROR(pDevIns, rc,
5897 N_("AHCI configuration error: failed to read R0Enabled as boolean"));
5898 Log(("%s: fR0Enabled=%d\n", __FUNCTION__, fR0Enabled));
5899
5900 rc = CFGMR3QueryU32Def(pCfg, "PortCount", &pThis->cPortsImpl, AHCI_MAX_NR_PORTS_IMPL);
5901 if (RT_FAILURE(rc))
5902 return PDMDEV_SET_ERROR(pDevIns, rc,
5903 N_("AHCI configuration error: failed to read PortCount as integer"));
5904 Log(("%s: cPortsImpl=%u\n", __FUNCTION__, pThis->cPortsImpl));
5905 if (pThis->cPortsImpl > AHCI_MAX_NR_PORTS_IMPL)
5906 return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
5907 N_("AHCI configuration error: PortCount=%u should not exceed %u"),
5908 pThis->cPortsImpl, AHCI_MAX_NR_PORTS_IMPL);
5909 if (pThis->cPortsImpl < 1)
5910 return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
5911 N_("AHCI configuration error: PortCount=%u should be at least 1"),
5912 pThis->cPortsImpl);
5913
5914 rc = CFGMR3QueryBoolDef(pCfg, "Bootable", &pThis->fBootable, true);
5915 if (RT_FAILURE(rc))
5916 return PDMDEV_SET_ERROR(pDevIns, rc,
5917 N_("AHCI configuration error: failed to read Bootable as boolean"));
5918
5919 rc = CFGMR3QueryU32Def(pCfg, "CmdSlotsAvail", &pThis->cCmdSlotsAvail, AHCI_NR_COMMAND_SLOTS);
5920 if (RT_FAILURE(rc))
5921 return PDMDEV_SET_ERROR(pDevIns, rc,
5922 N_("AHCI configuration error: failed to read CmdSlotsAvail as integer"));
5923 Log(("%s: cCmdSlotsAvail=%u\n", __FUNCTION__, pThis->cCmdSlotsAvail));
5924 if (pThis->cCmdSlotsAvail > AHCI_NR_COMMAND_SLOTS)
5925 return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
5926 N_("AHCI configuration error: CmdSlotsAvail=%u should not exceed %u"),
5927 pThis->cPortsImpl, AHCI_NR_COMMAND_SLOTS);
5928 if (pThis->cCmdSlotsAvail < 1)
5929 return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
5930 N_("AHCI configuration error: CmdSlotsAvail=%u should be at least 1"),
5931 pThis->cCmdSlotsAvail);
5932
5933 /*
5934 * Initialize the instance data (everything touched by the destructor need
5935 * to be initialized here!).
5936 */
5937 pThis->fR0Enabled = fR0Enabled;
5938 pThis->fGCEnabled = fGCEnabled;
5939 pThis->pDevInsR3 = pDevIns;
5940 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
5941 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5942 pThis->pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
5943
5944 PCIDevSetVendorId (&pThis->dev, 0x8086); /* Intel */
5945 PCIDevSetDeviceId (&pThis->dev, 0x2829); /* ICH-8M */
5946 PCIDevSetCommand (&pThis->dev, 0x0000);
5947#ifdef VBOX_WITH_MSI_DEVICES
5948 PCIDevSetStatus (&pThis->dev, VBOX_PCI_STATUS_CAP_LIST);
5949 PCIDevSetCapabilityList(&pThis->dev, 0x80);
5950#else
5951 PCIDevSetCapabilityList(&pThis->dev, 0x70);
5952#endif
5953 PCIDevSetRevisionId (&pThis->dev, 0x02);
5954 PCIDevSetClassProg (&pThis->dev, 0x01);
5955 PCIDevSetClassSub (&pThis->dev, 0x06);
5956 PCIDevSetClassBase (&pThis->dev, 0x01);
5957 PCIDevSetBaseAddress (&pThis->dev, 5, false, false, false, 0x00000000);
5958
5959 PCIDevSetInterruptLine(&pThis->dev, 0x00);
5960 PCIDevSetInterruptPin (&pThis->dev, 0x01);
5961
5962 pThis->dev.abConfig[0x70] = VBOX_PCI_CAP_ID_PM; /* Capability ID: PCI Power Management Interface */
5963 pThis->dev.abConfig[0x71] = 0xa8; /* next */
5964 pThis->dev.abConfig[0x72] = 0x03; /* version ? */
5965
5966 pThis->dev.abConfig[0x90] = 0x40; /* AHCI mode. */
5967 pThis->dev.abConfig[0x92] = 0x3f;
5968 pThis->dev.abConfig[0x94] = 0x80;
5969 pThis->dev.abConfig[0x95] = 0x01;
5970 pThis->dev.abConfig[0x97] = 0x78;
5971
5972 pThis->dev.abConfig[0xa8] = 0x12; /* SATACR capability */
5973 pThis->dev.abConfig[0xa9] = 0x00; /* next */
5974 PCIDevSetWord(&pThis->dev, 0xaa, 0x0010); /* Revision */
5975 PCIDevSetDWord(&pThis->dev, 0xac, 0x00000028); /* SATA Capability Register 1 */
5976
5977 pThis->cThreadsActive = 0;
5978
5979 /* Initialize port members. */
5980 for (i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
5981 {
5982 PAHCIPort pAhciPort = &pThis->ahciPort[i];
5983 pAhciPort->pDevInsR3 = pDevIns;
5984 pAhciPort->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
5985 pAhciPort->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5986 pAhciPort->iLUN = i;
5987 pAhciPort->pAhciR3 = pThis;
5988 pAhciPort->pAhciR0 = PDMINS_2_DATA_R0PTR(pDevIns);
5989 pAhciPort->pAhciRC = PDMINS_2_DATA_RCPTR(pDevIns);
5990 pAhciPort->Led.u32Magic = PDMLED_MAGIC;
5991 pAhciPort->pDrvBase = NULL;
5992 pAhciPort->pAsyncIOThread = NULL;
5993 pAhciPort->hEvtProcess = NIL_SUPSEMEVENT;
5994 pAhciPort->fHotpluggable = true;
5995 }
5996
5997 /*
5998 * Init locks, using explicit locking where necessary.
5999 */
6000 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
6001 if (RT_FAILURE(rc))
6002 return rc;
6003
6004 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->lock, RT_SRC_POS, "AHCI#%u", iInstance);
6005 if (RT_FAILURE(rc))
6006 {
6007 Log(("%s: Failed to create critical section.\n", __FUNCTION__));
6008 return rc;
6009 }
6010
6011 /*
6012 * Register the PCI device, it's I/O regions.
6013 */
6014 rc = PDMDevHlpPCIRegister (pDevIns, &pThis->dev);
6015 if (RT_FAILURE(rc))
6016 return rc;
6017
6018#ifdef VBOX_WITH_MSI_DEVICES
6019 PDMMSIREG MsiReg;
6020 RT_ZERO(MsiReg);
6021 MsiReg.cMsiVectors = 1;
6022 MsiReg.iMsiCapOffset = 0x80;
6023 MsiReg.iMsiNextOffset = 0x70;
6024 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
6025 if (RT_FAILURE(rc))
6026 {
6027 PCIDevSetCapabilityList(&pThis->dev, 0x70);
6028 /* That's OK, we can work without MSI */
6029 }
6030#endif
6031
6032 /*
6033 * Solaris 10 U5 fails to map the AHCI register space when the sets (0..5) for the legacy
6034 * IDE registers are not available.
6035 * We set up "fake" entries in the PCI configuration register.
6036 * That means they are available but read and writes from/to them have no effect.
6037 * No guest should access them anyway because the controller is marked as AHCI in the Programming interface
6038 * and we don't have an option to change to IDE emulation (real hardware provides an option in the BIOS
6039 * to switch to it which also changes device Id and other things in the PCI configuration space).
6040 */
6041 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 8, PCI_ADDRESS_SPACE_IO, ahciR3LegacyFakeIORangeMap);
6042 if (RT_FAILURE(rc))
6043 return PDMDEV_SET_ERROR(pDevIns, rc,
6044 N_("AHCI cannot register PCI I/O region"));
6045
6046 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 1, 1, PCI_ADDRESS_SPACE_IO, ahciR3LegacyFakeIORangeMap);
6047 if (RT_FAILURE(rc))
6048 return PDMDEV_SET_ERROR(pDevIns, rc,
6049 N_("AHCI cannot register PCI I/O region"));
6050
6051 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 2, 8, PCI_ADDRESS_SPACE_IO, ahciR3LegacyFakeIORangeMap);
6052 if (RT_FAILURE(rc))
6053 return PDMDEV_SET_ERROR(pDevIns, rc,
6054 N_("AHCI cannot register PCI I/O region"));
6055
6056 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 3, 1, PCI_ADDRESS_SPACE_IO, ahciR3LegacyFakeIORangeMap);
6057 if (RT_FAILURE(rc))
6058 return PDMDEV_SET_ERROR(pDevIns, rc,
6059 N_("AHCI cannot register PCI I/O region"));
6060
6061 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 4, 0x10, PCI_ADDRESS_SPACE_IO, ahciR3IdxDataIORangeMap);
6062 if (RT_FAILURE(rc))
6063 return PDMDEV_SET_ERROR(pDevIns, rc,
6064 N_("AHCI cannot register PCI I/O region for BMDMA"));
6065
6066 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 5, 4352, PCI_ADDRESS_SPACE_MEM, ahciR3MMIOMap);
6067 if (RT_FAILURE(rc))
6068 return PDMDEV_SET_ERROR(pDevIns, rc,
6069 N_("AHCI cannot register PCI memory region for registers"));
6070
6071 /* Create the timer for command completion coalescing feature. */
6072 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, ahciCccTimer, pThis,
6073 TMTIMER_FLAGS_NO_CRIT_SECT, "AHCI CCC Timer", &pThis->pHbaCccTimerR3);
6074 if (RT_FAILURE(rc))
6075 {
6076 AssertMsgFailed(("pfnTMTimerCreate -> %Rrc\n", rc));
6077 return rc;
6078 }
6079 pThis->pHbaCccTimerR0 = TMTimerR0Ptr(pThis->pHbaCccTimerR3);
6080 pThis->pHbaCccTimerRC = TMTimerRCPtr(pThis->pHbaCccTimerR3);
6081
6082 /* Status LUN. */
6083 pThis->IBase.pfnQueryInterface = ahciR3Status_QueryInterface;
6084 pThis->ILeds.pfnQueryStatusLed = ahciR3Status_QueryStatusLed;
6085
6086 /*
6087 * Create the notification queue.
6088 *
6089 * We need 2 items for every port because of SMP races.
6090 */
6091 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(DEVPORTNOTIFIERQUEUEITEM), AHCI_MAX_NR_PORTS_IMPL * 2, 0,
6092 ahciNotifyQueueConsumer, true, "AHCI-Xmit", &pThis->pNotifierQueueR3);
6093 if (RT_FAILURE(rc))
6094 return rc;
6095 pThis->pNotifierQueueR0 = PDMQueueR0Ptr(pThis->pNotifierQueueR3);
6096 pThis->pNotifierQueueRC = PDMQueueRCPtr(pThis->pNotifierQueueR3);
6097
6098 /* Initialize static members on every port. */
6099 for (i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
6100 ahciPortHwReset(&pThis->ahciPort[i]);
6101
6102 /* Attach drivers to every available port. */
6103 for (i = 0; i < pThis->cPortsImpl; i++)
6104 {
6105 char *pszName;
6106 if (RTStrAPrintf(&pszName, "Port%u", i) <= 0)
6107 AssertLogRelFailedReturn(VERR_NO_MEMORY);
6108
6109 PAHCIPort pAhciPort = &pThis->ahciPort[i];
6110 /*
6111 * Init interfaces.
6112 */
6113 pAhciPort->IBase.pfnQueryInterface = ahciR3PortQueryInterface;
6114 pAhciPort->IMediaExPort.pfnIoReqCompleteNotify = ahciR3IoReqCompleteNotify;
6115 pAhciPort->IMediaExPort.pfnIoReqCopyFromBuf = ahciR3IoReqCopyFromBuf;
6116 pAhciPort->IMediaExPort.pfnIoReqCopyToBuf = ahciR3IoReqCopyToBuf;
6117 pAhciPort->IMediaExPort.pfnIoReqQueryBuf = ahciR3IoReqQueryBuf;
6118 pAhciPort->IMediaExPort.pfnIoReqQueryDiscardRanges = ahciR3IoReqQueryDiscardRanges;
6119 pAhciPort->IMediaExPort.pfnIoReqStateChanged = ahciR3IoReqStateChanged;
6120 pAhciPort->IMediaExPort.pfnMediumEjected = ahciR3MediumEjected;
6121 pAhciPort->IPort.pfnQueryDeviceLocation = ahciR3PortQueryDeviceLocation;
6122 pAhciPort->IPort.pfnQueryScsiInqStrings = ahciR3PortQueryScsiInqStrings;
6123 pAhciPort->fWrkThreadSleeping = true;
6124
6125 /* Query per port configuration options if available. */
6126 PCFGMNODE pCfgPort = CFGMR3GetChild(pDevIns->pCfg, pszName);
6127 if (pCfgPort)
6128 {
6129 rc = CFGMR3QueryBoolDef(pCfgPort, "Hotpluggable", &pAhciPort->fHotpluggable, true);
6130 if (RT_FAILURE(rc))
6131 return PDMDEV_SET_ERROR(pDevIns, rc,
6132 N_("AHCI configuration error: failed to read Hotpluggable as boolean"));
6133 }
6134
6135 /*
6136 * Attach the block driver
6137 */
6138 rc = PDMDevHlpDriverAttach(pDevIns, pAhciPort->iLUN, &pAhciPort->IBase, &pAhciPort->pDrvBase, pszName);
6139 if (RT_SUCCESS(rc))
6140 {
6141 rc = ahciR3ConfigureLUN(pDevIns, pAhciPort);
6142 if (RT_FAILURE(rc))
6143 {
6144 Log(("%s: Failed to configure the %s.\n", __FUNCTION__, pszName));
6145 return rc;
6146 }
6147
6148 /* Mark that a device is present on that port */
6149 if (i < 6)
6150 pThis->dev.abConfig[0x93] |= (1 << i);
6151
6152 /*
6153 * Init vendor product data.
6154 */
6155 rc = ahciR3VpdInit(pDevIns, pAhciPort, pszName);
6156 if (RT_FAILURE(rc))
6157 return rc;
6158
6159 rc = SUPSemEventCreate(pThis->pSupDrvSession, &pAhciPort->hEvtProcess);
6160 if (RT_FAILURE(rc))
6161 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
6162 N_("AHCI: Failed to create SUP event semaphore"));
6163
6164 rc = PDMDevHlpThreadCreate(pDevIns, &pAhciPort->pAsyncIOThread, pAhciPort, ahciAsyncIOLoop,
6165 ahciAsyncIOLoopWakeUp, 0, RTTHREADTYPE_IO, pszName);
6166 if (RT_FAILURE(rc))
6167 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
6168 N_("AHCI: Failed to create worker thread %s"), pszName);
6169 }
6170 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
6171 {
6172 pAhciPort->pDrvBase = NULL;
6173 rc = VINF_SUCCESS;
6174 LogRel(("AHCI: %s: No driver attached\n", pszName));
6175 }
6176 else
6177 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
6178 N_("AHCI: Failed to attach drive to %s"), pszName);
6179 }
6180
6181 /*
6182 * Attach status driver (optional).
6183 */
6184 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThis->IBase, &pBase, "Status Port");
6185 if (RT_SUCCESS(rc))
6186 {
6187 pThis->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
6188 pThis->pMediaNotify = PDMIBASE_QUERY_INTERFACE(pBase, PDMIMEDIANOTIFY);
6189 }
6190 else if (rc != VERR_PDM_NO_ATTACHED_DRIVER)
6191 {
6192 AssertMsgFailed(("Failed to attach to status driver. rc=%Rrc\n", rc));
6193 return PDMDEV_SET_ERROR(pDevIns, rc, N_("AHCI cannot attach to status driver"));
6194 }
6195 rc = PDMDevHlpSSMRegisterEx(pDevIns, AHCI_SAVED_STATE_VERSION, sizeof(*pThis) + cbTotalBufferSize, NULL,
6196 NULL, ahciR3LiveExec, NULL,
6197 ahciR3SavePrep, ahciR3SaveExec, NULL,
6198 ahciR3LoadPrep, ahciR3LoadExec, NULL);
6199 if (RT_FAILURE(rc))
6200 return rc;
6201
6202 /*
6203 * Register the info item.
6204 */
6205 char szTmp[128];
6206 RTStrPrintf(szTmp, sizeof(szTmp), "%s%d", pDevIns->pReg->szName, pDevIns->iInstance);
6207 PDMDevHlpDBGFInfoRegister(pDevIns, szTmp, "AHCI info", ahciR3Info);
6208
6209 return ahciR3ResetCommon(pDevIns);
6210}
6211
6212/**
6213 * The device registration structure.
6214 */
6215const PDMDEVREG g_DeviceAHCI =
6216{
6217 /* u32Version */
6218 PDM_DEVREG_VERSION,
6219 /* szName */
6220 "ahci",
6221 /* szRCMod */
6222 "VBoxDDRC.rc",
6223 /* szR0Mod */
6224 "VBoxDDR0.r0",
6225 /* pszDescription */
6226 "Intel AHCI controller.\n",
6227 /* fFlags */
6228 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0 |
6229 PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION | PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION |
6230 PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION,
6231 /* fClass */
6232 PDM_DEVREG_CLASS_STORAGE,
6233 /* cMaxInstances */
6234 ~0U,
6235 /* cbInstance */
6236 sizeof(AHCI),
6237 /* pfnConstruct */
6238 ahciR3Construct,
6239 /* pfnDestruct */
6240 ahciR3Destruct,
6241 /* pfnRelocate */
6242 ahciR3Relocate,
6243 /* pfnMemSetup */
6244 NULL,
6245 /* pfnPowerOn */
6246 NULL,
6247 /* pfnReset */
6248 ahciR3Reset,
6249 /* pfnSuspend */
6250 ahciR3Suspend,
6251 /* pfnResume */
6252 ahciR3Resume,
6253 /* pfnAttach */
6254 ahciR3Attach,
6255 /* pfnDetach */
6256 ahciR3Detach,
6257 /* pfnQueryInterface. */
6258 NULL,
6259 /* pfnInitComplete */
6260 NULL,
6261 /* pfnPowerOff */
6262 ahciR3PowerOff,
6263 /* pfnSoftReset */
6264 NULL,
6265 /* u32VersionEnd */
6266 PDM_DEVREG_VERSION
6267};
6268
6269#endif /* IN_RING3 */
6270#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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