VirtualBox

source: vbox/trunk/src/VBox/Devices/Storage/DevATA.cpp@ 93411

Last change on this file since 93411 was 93411, checked in by vboxsync, 3 years ago

DevATA: Keep track of current LBA for ATA R/W commands, too, not just ATAPI. Fixes problem with NetWare IDE.DSK which may overwrite CHS head of an in-progress command. See bugref:5869.

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File size: 332.8 KB
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1/* $Id: DevATA.cpp 93411 2022-01-24 14:46:17Z vboxsync $ */
2/** @file
3 * VBox storage devices: ATA/ATAPI controller device (disk and cdrom).
4 */
5
6/*
7 * Copyright (C) 2006-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_IDE
23#include <VBox/vmm/pdmdev.h>
24#include <VBox/vmm/pdmstorageifs.h>
25#include <iprt/assert.h>
26#include <iprt/string.h>
27#ifdef IN_RING3
28# include <iprt/mem.h>
29# include <iprt/mp.h>
30# include <iprt/semaphore.h>
31# include <iprt/thread.h>
32# include <iprt/time.h>
33# include <iprt/uuid.h>
34#endif /* IN_RING3 */
35#include <iprt/critsect.h>
36#include <iprt/asm.h>
37#include <VBox/vmm/stam.h>
38#include <VBox/vmm/mm.h>
39#include <VBox/vmm/pgm.h>
40
41#include <VBox/sup.h>
42#include <VBox/AssertGuest.h>
43#include <VBox/scsi.h>
44#include <VBox/scsiinline.h>
45#include <VBox/ata.h>
46
47#include "ATAPIPassthrough.h"
48#include "VBoxDD.h"
49
50
51/*********************************************************************************************************************************
52* Defined Constants And Macros *
53*********************************************************************************************************************************/
54/** Temporary instrumentation for tracking down potential virtual disk
55 * write performance issues. */
56#undef VBOX_INSTRUMENT_DMA_WRITES
57
58/** @name The SSM saved state versions.
59 * @{
60 */
61/** The current saved state version. */
62#define ATA_SAVED_STATE_VERSION 21
63/** Saved state version without iCurLBA for ATA commands. */
64#define ATA_SAVED_STATE_VERSION_WITHOUT_ATA_ILBA 20
65/** The saved state version used by VirtualBox 3.0.
66 * This lacks the config part and has the type at the and. */
67#define ATA_SAVED_STATE_VERSION_VBOX_30 19
68#define ATA_SAVED_STATE_VERSION_WITH_BOOL_TYPE 18
69#define ATA_SAVED_STATE_VERSION_WITHOUT_FULL_SENSE 16
70#define ATA_SAVED_STATE_VERSION_WITHOUT_EVENT_STATUS 17
71/** @} */
72
73/** Values read from an empty (with no devices attached) ATA bus. */
74#define ATA_EMPTY_BUS_DATA 0x7F
75#define ATA_EMPTY_BUS_DATA_32 0x7F7F7F7F
76
77/**
78 * Maximum number of sectors to transfer in a READ/WRITE MULTIPLE request.
79 * Set to 1 to disable multi-sector read support. According to the ATA
80 * specification this must be a power of 2 and it must fit in an 8 bit
81 * value. Thus the only valid values are 1, 2, 4, 8, 16, 32, 64 and 128.
82 */
83#define ATA_MAX_MULT_SECTORS 128
84
85/** The maxium I/O buffer size (for sanity). */
86#define ATA_MAX_SECTOR_SIZE _4K
87/** The maxium I/O buffer size (for sanity). */
88#define ATA_MAX_IO_BUFFER_SIZE (ATA_MAX_MULT_SECTORS * ATA_MAX_SECTOR_SIZE)
89
90/** Mask to be applied to all indexing into ATACONTROLLER::aIfs. */
91#define ATA_SELECTED_IF_MASK 1
92
93/**
94 * Fastest PIO mode supported by the drive.
95 */
96#define ATA_PIO_MODE_MAX 4
97/**
98 * Fastest MDMA mode supported by the drive.
99 */
100#define ATA_MDMA_MODE_MAX 2
101/**
102 * Fastest UDMA mode supported by the drive.
103 */
104#define ATA_UDMA_MODE_MAX 6
105
106/** ATAPI sense info size. */
107#define ATAPI_SENSE_SIZE 64
108
109/** The maximum number of release log entries per device. */
110#define MAX_LOG_REL_ERRORS 1024
111
112/* MediaEventStatus */
113#define ATA_EVENT_STATUS_UNCHANGED 0 /**< medium event status not changed */
114#define ATA_EVENT_STATUS_MEDIA_EJECT_REQUESTED 1 /**< medium eject requested (eject button pressed) */
115#define ATA_EVENT_STATUS_MEDIA_NEW 2 /**< new medium inserted */
116#define ATA_EVENT_STATUS_MEDIA_REMOVED 3 /**< medium removed */
117#define ATA_EVENT_STATUS_MEDIA_CHANGED 4 /**< medium was removed + new medium was inserted */
118
119/* Media track type */
120#define ATA_MEDIA_TYPE_UNKNOWN 0 /**< unknown CD type */
121#define ATA_MEDIA_NO_DISC 0x70 /**< Door closed, no medium */
122
123/** @defgroup grp_piix3atabmdma PIIX3 ATA Bus Master DMA
124 * @{
125 */
126
127/** @name BM_STATUS
128 * @{
129 */
130/** Currently performing a DMA operation. */
131#define BM_STATUS_DMAING 0x01
132/** An error occurred during the DMA operation. */
133#define BM_STATUS_ERROR 0x02
134/** The DMA unit has raised the IDE interrupt line. */
135#define BM_STATUS_INT 0x04
136/** User-defined bit 0, commonly used to signal that drive 0 supports DMA. */
137#define BM_STATUS_D0DMA 0x20
138/** User-defined bit 1, commonly used to signal that drive 1 supports DMA. */
139#define BM_STATUS_D1DMA 0x40
140/** @} */
141
142/** @name BM_CMD
143 * @{
144 */
145/** Start the DMA operation. */
146#define BM_CMD_START 0x01
147/** Data transfer direction: from device to memory if set. */
148#define BM_CMD_WRITE 0x08
149/** @} */
150
151/** Number of I/O ports per bus-master DMA controller. */
152#define BM_DMA_CTL_IOPORTS 8
153/** Mask corresponding to BM_DMA_CTL_IOPORTS. */
154#define BM_DMA_CTL_IOPORTS_MASK 7
155/** Shift count corresponding to BM_DMA_CTL_IOPORTS. */
156#define BM_DMA_CTL_IOPORTS_SHIFT 3
157
158/** @} */
159
160#define ATADEVSTATE_2_DEVINS(pIf) ( (pIf)->CTX_SUFF(pDevIns) )
161#define CONTROLLER_2_DEVINS(pController) ( (pController)->CTX_SUFF(pDevIns) )
162
163
164/*********************************************************************************************************************************
165* Structures and Typedefs *
166*********************************************************************************************************************************/
167/** @defgroup grp_piix3atabmdma PIIX3 ATA Bus Master DMA
168 * @{
169 */
170/** PIIX3 Bus Master DMA unit state. */
171typedef struct BMDMAState
172{
173 /** Command register. */
174 uint8_t u8Cmd;
175 /** Status register. */
176 uint8_t u8Status;
177 /** Explicit alignment padding. */
178 uint8_t abAlignment[2];
179 /** Address of the MMIO region in the guest's memory space. */
180 RTGCPHYS32 GCPhysAddr;
181} BMDMAState;
182
183/** PIIX3 Bus Master DMA descriptor entry. */
184typedef struct BMDMADesc
185{
186 /** Address of the DMA source/target buffer. */
187 RTGCPHYS32 GCPhysBuffer;
188 /** Size of the DMA source/target buffer. */
189 uint32_t cbBuffer;
190} BMDMADesc;
191/** @} */
192
193
194/**
195 * The shared state of an ATA device.
196 */
197typedef struct ATADEVSTATE
198{
199 /** The I/O buffer.
200 * @note Page aligned in case it helps. */
201 uint8_t abIOBuffer[ATA_MAX_IO_BUFFER_SIZE];
202
203 /** Flag indicating whether the current command uses LBA48 mode. */
204 bool fLBA48;
205 /** Flag indicating whether this drive implements the ATAPI command set. */
206 bool fATAPI;
207 /** Set if this interface has asserted the IRQ. */
208 bool fIrqPending;
209 /** Currently configured number of sectors in a multi-sector transfer. */
210 uint8_t cMultSectors;
211 /** Physical CHS disk geometry (static). */
212 PDMMEDIAGEOMETRY PCHSGeometry;
213 /** Translated CHS disk geometry (variable). */
214 PDMMEDIAGEOMETRY XCHSGeometry;
215 /** Total number of sectors on this disk. */
216 uint64_t cTotalSectors;
217 /** Sector size of the medium. */
218 uint32_t cbSector;
219 /** Number of sectors to transfer per IRQ. */
220 uint32_t cSectorsPerIRQ;
221
222 /** ATA/ATAPI register 1: feature (write-only). */
223 uint8_t uATARegFeature;
224 /** ATA/ATAPI register 1: feature, high order byte. */
225 uint8_t uATARegFeatureHOB;
226 /** ATA/ATAPI register 1: error (read-only). */
227 uint8_t uATARegError;
228 /** ATA/ATAPI register 2: sector count (read/write). */
229 uint8_t uATARegNSector;
230 /** ATA/ATAPI register 2: sector count, high order byte. */
231 uint8_t uATARegNSectorHOB;
232 /** ATA/ATAPI register 3: sector (read/write). */
233 uint8_t uATARegSector;
234 /** ATA/ATAPI register 3: sector, high order byte. */
235 uint8_t uATARegSectorHOB;
236 /** ATA/ATAPI register 4: cylinder low (read/write). */
237 uint8_t uATARegLCyl;
238 /** ATA/ATAPI register 4: cylinder low, high order byte. */
239 uint8_t uATARegLCylHOB;
240 /** ATA/ATAPI register 5: cylinder high (read/write). */
241 uint8_t uATARegHCyl;
242 /** ATA/ATAPI register 5: cylinder high, high order byte. */
243 uint8_t uATARegHCylHOB;
244 /** ATA/ATAPI register 6: select drive/head (read/write). */
245 uint8_t uATARegSelect;
246 /** ATA/ATAPI register 7: status (read-only). */
247 uint8_t uATARegStatus;
248 /** ATA/ATAPI register 7: command (write-only). */
249 uint8_t uATARegCommand;
250 /** ATA/ATAPI drive control register (write-only). */
251 uint8_t uATARegDevCtl;
252
253 /** Currently active transfer mode (MDMA/UDMA) and speed. */
254 uint8_t uATATransferMode;
255 /** Current transfer direction. */
256 uint8_t uTxDir;
257 /** Index of callback for begin transfer. */
258 uint8_t iBeginTransfer;
259 /** Index of callback for source/sink of data. */
260 uint8_t iSourceSink;
261 /** Flag indicating whether the current command transfers data in DMA mode. */
262 bool fDMA;
263 /** Set to indicate that ATAPI transfer semantics must be used. */
264 bool fATAPITransfer;
265
266 /** Total ATA/ATAPI transfer size, shared PIO/DMA. */
267 uint32_t cbTotalTransfer;
268 /** Elementary ATA/ATAPI transfer size, shared PIO/DMA. */
269 uint32_t cbElementaryTransfer;
270 /** Maximum ATAPI elementary transfer size, PIO only. */
271 uint32_t cbPIOTransferLimit;
272 /** ATAPI passthrough transfer size, shared PIO/DMA */
273 uint32_t cbAtapiPassthroughTransfer;
274 /** Current read/write buffer position, shared PIO/DMA. */
275 uint32_t iIOBufferCur;
276 /** First element beyond end of valid buffer content, shared PIO/DMA. */
277 uint32_t iIOBufferEnd;
278 /** Align the following fields correctly. */
279 uint32_t Alignment0;
280
281 /** ATA/ATAPI current PIO read/write transfer position. Not shared with DMA for safety reasons. */
282 uint32_t iIOBufferPIODataStart;
283 /** ATA/ATAPI current PIO read/write transfer end. Not shared with DMA for safety reasons. */
284 uint32_t iIOBufferPIODataEnd;
285
286 /** Current LBA position (both ATA/ATAPI). */
287 uint32_t iCurLBA;
288 /** ATAPI current sector size. */
289 uint32_t cbATAPISector;
290 /** ATAPI current command. */
291 uint8_t abATAPICmd[ATAPI_PACKET_SIZE];
292 /** ATAPI sense data. */
293 uint8_t abATAPISense[ATAPI_SENSE_SIZE];
294 /** HACK: Countdown till we report a newly unmounted drive as mounted. */
295 uint8_t cNotifiedMediaChange;
296 /** The same for GET_EVENT_STATUS for mechanism */
297 volatile uint32_t MediaEventStatus;
298
299 /** Media type if known. */
300 volatile uint32_t MediaTrackType;
301
302 /** The status LED state for this drive. */
303 PDMLED Led;
304
305 /** Size of I/O buffer. */
306 uint32_t cbIOBuffer;
307
308 /*
309 * No data that is part of the saved state after this point!!!!!
310 */
311
312 /** Counter for number of busy status seen in R3 in a row. */
313 uint8_t cBusyStatusHackR3;
314 /** Counter for number of busy status seen in GC/R0 in a row. */
315 uint8_t cBusyStatusHackRZ;
316 /** Defines the R3 yield rate by a mask (power of 2 minus one).
317 * Lower is more agressive. */
318 uint8_t cBusyStatusHackR3Rate;
319 /** Defines the R0/RC yield rate by a mask (power of 2 minus one).
320 * Lower is more agressive. */
321 uint8_t cBusyStatusHackRZRate;
322
323 /** Release statistics: number of ATA DMA commands. */
324 STAMCOUNTER StatATADMA;
325 /** Release statistics: number of ATA PIO commands. */
326 STAMCOUNTER StatATAPIO;
327 /** Release statistics: number of ATAPI PIO commands. */
328 STAMCOUNTER StatATAPIDMA;
329 /** Release statistics: number of ATAPI PIO commands. */
330 STAMCOUNTER StatATAPIPIO;
331#ifdef VBOX_INSTRUMENT_DMA_WRITES
332 /** Release statistics: number of DMA sector writes and the time spent. */
333 STAMPROFILEADV StatInstrVDWrites;
334#endif
335 /** Release statistics: Profiling RTThreadYield calls during status polling. */
336 STAMPROFILEADV StatStatusYields;
337
338 /** Statistics: number of read operations and the time spent reading. */
339 STAMPROFILEADV StatReads;
340 /** Statistics: number of bytes read. */
341 STAMCOUNTER StatBytesRead;
342 /** Statistics: number of write operations and the time spent writing. */
343 STAMPROFILEADV StatWrites;
344 /** Statistics: number of bytes written. */
345 STAMCOUNTER StatBytesWritten;
346 /** Statistics: number of flush operations and the time spend flushing. */
347 STAMPROFILE StatFlushes;
348
349 /** Enable passing through commands directly to the ATAPI drive. */
350 bool fATAPIPassthrough;
351 /** Flag whether to overwrite inquiry data in passthrough mode. */
352 bool fOverwriteInquiry;
353 /** Number of errors we've reported to the release log.
354 * This is to prevent flooding caused by something going horribly wrong.
355 * this value against MAX_LOG_REL_ERRORS in places likely to cause floods
356 * like the ones we currently seeing on the linux smoke tests (2006-11-10). */
357 uint32_t cErrors;
358 /** Timestamp of last started command. 0 if no command pending. */
359 uint64_t u64CmdTS;
360
361 /** The LUN number. */
362 uint32_t iLUN;
363 /** The controller number. */
364 uint8_t iCtl;
365 /** The device number. */
366 uint8_t iDev;
367 /** Set if the device is present. */
368 bool fPresent;
369 /** Explicit alignment. */
370 uint8_t bAlignment2;
371
372 /** The serial number to use for IDENTIFY DEVICE commands. */
373 char szSerialNumber[ATA_SERIAL_NUMBER_LENGTH+1];
374 /** The firmware revision to use for IDENTIFY DEVICE commands. */
375 char szFirmwareRevision[ATA_FIRMWARE_REVISION_LENGTH+1];
376 /** The model number to use for IDENTIFY DEVICE commands. */
377 char szModelNumber[ATA_MODEL_NUMBER_LENGTH+1];
378 /** The vendor identification string for SCSI INQUIRY commands. */
379 char szInquiryVendorId[SCSI_INQUIRY_VENDOR_ID_LENGTH+1];
380 /** The product identification string for SCSI INQUIRY commands. */
381 char szInquiryProductId[SCSI_INQUIRY_PRODUCT_ID_LENGTH+1];
382 /** The revision string for SCSI INQUIRY commands. */
383 char szInquiryRevision[SCSI_INQUIRY_REVISION_LENGTH+1];
384
385 /** Padding the structure to a multiple of 4096 for better I/O buffer alignment. */
386 uint8_t abAlignment4[7 + 3528];
387} ATADEVSTATE;
388AssertCompileMemberAlignment(ATADEVSTATE, cTotalSectors, 8);
389AssertCompileMemberAlignment(ATADEVSTATE, StatATADMA, 8);
390AssertCompileMemberAlignment(ATADEVSTATE, u64CmdTS, 8);
391AssertCompileMemberAlignment(ATADEVSTATE, szSerialNumber, 8);
392AssertCompileSizeAlignment(ATADEVSTATE, 4096); /* To align the buffer on a page boundrary. */
393/** Pointer to the shared state of an ATA device. */
394typedef ATADEVSTATE *PATADEVSTATE;
395
396
397/**
398 * The ring-3 state of an ATA device.
399 *
400 * @implements PDMIBASE
401 * @implements PDMIBLOCKPORT
402 * @implements PDMIMOUNTNOTIFY
403 */
404typedef struct ATADEVSTATER3
405{
406 /** Pointer to the attached driver's base interface. */
407 R3PTRTYPE(PPDMIBASE) pDrvBase;
408 /** Pointer to the attached driver's block interface. */
409 R3PTRTYPE(PPDMIMEDIA) pDrvMedia;
410 /** Pointer to the attached driver's mount interface.
411 * This is NULL if the driver isn't a removable unit. */
412 R3PTRTYPE(PPDMIMOUNT) pDrvMount;
413 /** The base interface. */
414 PDMIBASE IBase;
415 /** The block port interface. */
416 PDMIMEDIAPORT IPort;
417 /** The mount notify interface. */
418 PDMIMOUNTNOTIFY IMountNotify;
419
420 /** The LUN number. */
421 uint32_t iLUN;
422 /** The controller number. */
423 uint8_t iCtl;
424 /** The device number. */
425 uint8_t iDev;
426 /** Explicit alignment. */
427 uint8_t abAlignment2[2];
428 /** The device instance so we can get our bearings from an interface method. */
429 PPDMDEVINSR3 pDevIns;
430
431 /** The current tracklist of the loaded medium if passthrough is used. */
432 R3PTRTYPE(PTRACKLIST) pTrackList;
433} ATADEVSTATER3;
434/** Pointer to the ring-3 state of an ATA device. */
435typedef ATADEVSTATER3 *PATADEVSTATER3;
436
437
438/**
439 * Transfer request forwarded to the async I/O thread.
440 */
441typedef struct ATATransferRequest
442{
443 /** The interface index the request is for. */
444 uint8_t iIf;
445 /** The index of the begin transfer callback to call. */
446 uint8_t iBeginTransfer;
447 /** The index of the source sink callback to call for doing the transfer. */
448 uint8_t iSourceSink;
449 /** Transfer direction. */
450 uint8_t uTxDir;
451 /** How many bytes to transfer. */
452 uint32_t cbTotalTransfer;
453} ATATransferRequest;
454
455
456/**
457 * Abort request forwarded to the async I/O thread.
458 */
459typedef struct ATAAbortRequest
460{
461 /** The interface index the request is for. */
462 uint8_t iIf;
463 /** Flag whether to reset the drive. */
464 bool fResetDrive;
465} ATAAbortRequest;
466
467
468/**
469 * Request type indicator.
470 */
471typedef enum
472{
473 /** Begin a new transfer. */
474 ATA_AIO_NEW = 0,
475 /** Continue a DMA transfer. */
476 ATA_AIO_DMA,
477 /** Continue a PIO transfer. */
478 ATA_AIO_PIO,
479 /** Reset the drives on current controller, stop all transfer activity. */
480 ATA_AIO_RESET_ASSERTED,
481 /** Reset the drives on current controller, resume operation. */
482 ATA_AIO_RESET_CLEARED,
483 /** Abort the current transfer of a particular drive. */
484 ATA_AIO_ABORT
485} ATAAIO;
486
487
488/**
489 * Combining structure for an ATA request to the async I/O thread
490 * started with the request type insicator.
491 */
492typedef struct ATARequest
493{
494 /** Request type. */
495 ATAAIO ReqType;
496 /** Request type dependent data. */
497 union
498 {
499 /** Transfer request specific data. */
500 ATATransferRequest t;
501 /** Abort request specific data. */
502 ATAAbortRequest a;
503 } u;
504} ATARequest;
505
506
507/**
508 * The shared state of an ATA controller.
509 *
510 * Has two devices, the master (0) and the slave (1).
511 */
512typedef struct ATACONTROLLER
513{
514 /** The ATA/ATAPI interfaces of this controller. */
515 ATADEVSTATE aIfs[2];
516
517 /** The base of the first I/O Port range. */
518 RTIOPORT IOPortBase1;
519 /** The base of the second I/O Port range. (0 if none) */
520 RTIOPORT IOPortBase2;
521 /** The assigned IRQ. */
522 uint32_t irq;
523 /** Access critical section */
524 PDMCRITSECT lock;
525
526 /** Selected drive. */
527 uint8_t iSelectedIf;
528 /** The interface on which to handle async I/O. */
529 uint8_t iAIOIf;
530 /** The state of the async I/O thread. */
531 uint8_t uAsyncIOState;
532 /** Flag indicating whether the next transfer is part of the current command. */
533 bool fChainedTransfer;
534 /** Set when the reset processing is currently active on this controller. */
535 bool fReset;
536 /** Flag whether the current transfer needs to be redone. */
537 bool fRedo;
538 /** Flag whether the redo suspend has been finished. */
539 bool fRedoIdle;
540 /** Flag whether the DMA operation to be redone is the final transfer. */
541 bool fRedoDMALastDesc;
542 /** The BusMaster DMA state. */
543 BMDMAState BmDma;
544 /** Pointer to first DMA descriptor. */
545 RTGCPHYS32 GCPhysFirstDMADesc;
546 /** Pointer to last DMA descriptor. */
547 RTGCPHYS32 GCPhysLastDMADesc;
548 /** Pointer to current DMA buffer (for redo operations). */
549 RTGCPHYS32 GCPhysRedoDMABuffer;
550 /** Size of current DMA buffer (for redo operations). */
551 uint32_t cbRedoDMABuffer;
552
553 /** The event semaphore the thread is waiting on for requests. */
554 SUPSEMEVENT hAsyncIOSem;
555 /** The request queue for the AIO thread. One element is always unused. */
556 ATARequest aAsyncIORequests[4];
557 /** The position at which to insert a new request for the AIO thread. */
558 volatile uint8_t AsyncIOReqHead;
559 /** The position at which to get a new request for the AIO thread. */
560 volatile uint8_t AsyncIOReqTail;
561 /** The controller number. */
562 uint8_t iCtl;
563 /** Magic delay before triggering interrupts in DMA mode. */
564 uint32_t msDelayIRQ;
565 /** The lock protecting the request queue. */
566 PDMCRITSECT AsyncIORequestLock;
567
568 /** Timestamp we started the reset. */
569 uint64_t u64ResetTime;
570
571 /** The first port in the first I/O port range, regular operation. */
572 IOMIOPORTHANDLE hIoPorts1First;
573 /** The other ports in the first I/O port range, regular operation. */
574 IOMIOPORTHANDLE hIoPorts1Other;
575 /** The second I/O port range, regular operation. */
576 IOMIOPORTHANDLE hIoPorts2;
577 /** The first I/O port range, empty controller operation. */
578 IOMIOPORTHANDLE hIoPortsEmpty1;
579 /** The second I/O port range, empty controller operation. */
580 IOMIOPORTHANDLE hIoPortsEmpty2;
581
582 /* Statistics */
583 STAMCOUNTER StatAsyncOps;
584 uint64_t StatAsyncMinWait;
585 uint64_t StatAsyncMaxWait;
586 STAMCOUNTER StatAsyncTimeUS;
587 STAMPROFILEADV StatAsyncTime;
588 STAMPROFILE StatLockWait;
589 uint8_t abAlignment4[3328];
590} ATACONTROLLER;
591AssertCompileMemberAlignment(ATACONTROLLER, lock, 8);
592AssertCompileMemberAlignment(ATACONTROLLER, aIfs, 8);
593AssertCompileMemberAlignment(ATACONTROLLER, u64ResetTime, 8);
594AssertCompileMemberAlignment(ATACONTROLLER, StatAsyncOps, 8);
595AssertCompileMemberAlignment(ATACONTROLLER, AsyncIORequestLock, 8);
596AssertCompileSizeAlignment(ATACONTROLLER, 4096); /* To align the controllers, devices and I/O buffers on page boundaries. */
597/** Pointer to the shared state of an ATA controller. */
598typedef ATACONTROLLER *PATACONTROLLER;
599
600
601/**
602 * The ring-3 state of an ATA controller.
603 */
604typedef struct ATACONTROLLERR3
605{
606 /** The ATA/ATAPI interfaces of this controller. */
607 ATADEVSTATER3 aIfs[2];
608
609 /** Pointer to device instance. */
610 PPDMDEVINSR3 pDevIns;
611
612 /** The async I/O thread handle. NIL_RTTHREAD if no thread. */
613 RTTHREAD hAsyncIOThread;
614 /** The event semaphore the thread is waiting on during suspended I/O. */
615 RTSEMEVENT hSuspendIOSem;
616 /** Set when the destroying the device instance and the thread must exit. */
617 uint32_t volatile fShutdown;
618 /** Whether to call PDMDevHlpAsyncNotificationCompleted when idle. */
619 bool volatile fSignalIdle;
620
621 /** The controller number. */
622 uint8_t iCtl;
623
624 uint8_t abAlignment[3];
625} ATACONTROLLERR3;
626/** Pointer to the ring-3 state of an ATA controller. */
627typedef ATACONTROLLERR3 *PATACONTROLLERR3;
628
629
630/** ATA chipset type. */
631typedef enum CHIPSET
632{
633 /** PIIX3 chipset, must be 0 for saved state compatibility */
634 CHIPSET_PIIX3 = 0,
635 /** PIIX4 chipset, must be 1 for saved state compatibility */
636 CHIPSET_PIIX4,
637 /** ICH6 chipset */
638 CHIPSET_ICH6,
639 CHIPSET_32BIT_HACK=0x7fffffff
640} CHIPSET;
641AssertCompileSize(CHIPSET, 4);
642
643/**
644 * The shared state of a ATA PCI device.
645 */
646typedef struct ATASTATE
647{
648 /** The controllers. */
649 ATACONTROLLER aCts[2];
650 /** Flag indicating chipset being emulated. */
651 CHIPSET enmChipset;
652 /** Explicit alignment padding. */
653 uint8_t abAlignment1[7];
654 /** PCI region \#4: Bus-master DMA I/O ports. */
655 IOMIOPORTHANDLE hIoPortsBmDma;
656} ATASTATE;
657/** Pointer to the shared state of an ATA PCI device. */
658typedef ATASTATE *PATASTATE;
659
660
661/**
662 * The ring-3 state of a ATA PCI device.
663 *
664 * @implements PDMILEDPORTS
665 */
666typedef struct ATASTATER3
667{
668 /** The controllers. */
669 ATACONTROLLERR3 aCts[2];
670 /** Status LUN: Base interface. */
671 PDMIBASE IBase;
672 /** Status LUN: Leds interface. */
673 PDMILEDPORTS ILeds;
674 /** Status LUN: Partner of ILeds. */
675 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
676 /** Status LUN: Media Notify. */
677 R3PTRTYPE(PPDMIMEDIANOTIFY) pMediaNotify;
678 /** Pointer to device instance (for getting our bearings in interface methods). */
679 PPDMDEVINSR3 pDevIns;
680} ATASTATER3;
681/** Pointer to the ring-3 state of an ATA PCI device. */
682typedef ATASTATER3 *PATASTATER3;
683
684
685/**
686 * The ring-0 state of the ATA PCI device.
687 */
688typedef struct ATASTATER0
689{
690 uint64_t uUnused;
691} ATASTATER0;
692/** Pointer to the ring-0 state of an ATA PCI device. */
693typedef ATASTATER0 *PATASTATER0;
694
695
696/**
697 * The raw-mode state of the ATA PCI device.
698 */
699typedef struct ATASTATERC
700{
701 uint64_t uUnused;
702} ATASTATERC;
703/** Pointer to the raw-mode state of an ATA PCI device. */
704typedef ATASTATERC *PATASTATERC;
705
706
707/** The current context state of an ATA PCI device. */
708typedef CTX_SUFF(ATASTATE) ATASTATECC;
709/** Pointer to the current context state of an ATA PCI device. */
710typedef CTX_SUFF(PATASTATE) PATASTATECC;
711
712
713#ifndef VBOX_DEVICE_STRUCT_TESTCASE
714
715
716#ifdef IN_RING3
717DECLINLINE(void) ataSetStatusValue(PATACONTROLLER pCtl, PATADEVSTATE s, uint8_t stat)
718{
719 /* Freeze status register contents while processing RESET. */
720 if (!pCtl->fReset)
721 {
722 s->uATARegStatus = stat;
723 Log2(("%s: LUN#%d status %#04x\n", __FUNCTION__, s->iLUN, s->uATARegStatus));
724 }
725}
726#endif /* IN_RING3 */
727
728
729DECLINLINE(void) ataSetStatus(PATACONTROLLER pCtl, PATADEVSTATE s, uint8_t stat)
730{
731 /* Freeze status register contents while processing RESET. */
732 if (!pCtl->fReset)
733 {
734 s->uATARegStatus |= stat;
735 Log2(("%s: LUN#%d status %#04x\n", __FUNCTION__, s->iLUN, s->uATARegStatus));
736 }
737}
738
739
740DECLINLINE(void) ataUnsetStatus(PATACONTROLLER pCtl, PATADEVSTATE s, uint8_t stat)
741{
742 /* Freeze status register contents while processing RESET. */
743 if (!pCtl->fReset)
744 {
745 s->uATARegStatus &= ~stat;
746 Log2(("%s: LUN#%d status %#04x\n", __FUNCTION__, s->iLUN, s->uATARegStatus));
747 }
748}
749
750#if defined(IN_RING3) || defined(IN_RING0)
751
752# ifdef IN_RING3
753typedef void FNBEGINTRANSFER(PATACONTROLLER pCtl, PATADEVSTATE s);
754typedef FNBEGINTRANSFER *PFNBEGINTRANSFER;
755typedef bool FNSOURCESINK(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3);
756typedef FNSOURCESINK *PFNSOURCESINK;
757
758static FNBEGINTRANSFER ataR3ReadWriteSectorsBT;
759static FNBEGINTRANSFER ataR3PacketBT;
760static FNBEGINTRANSFER atapiR3CmdBT;
761static FNBEGINTRANSFER atapiR3PassthroughCmdBT;
762
763static FNSOURCESINK ataR3IdentifySS;
764static FNSOURCESINK ataR3FlushSS;
765static FNSOURCESINK ataR3ReadSectorsSS;
766static FNSOURCESINK ataR3WriteSectorsSS;
767static FNSOURCESINK ataR3ExecuteDeviceDiagnosticSS;
768static FNSOURCESINK ataR3TrimSS;
769static FNSOURCESINK ataR3PacketSS;
770static FNSOURCESINK ataR3InitDevParmSS;
771static FNSOURCESINK ataR3RecalibrateSS;
772static FNSOURCESINK atapiR3GetConfigurationSS;
773static FNSOURCESINK atapiR3GetEventStatusNotificationSS;
774static FNSOURCESINK atapiR3IdentifySS;
775static FNSOURCESINK atapiR3InquirySS;
776static FNSOURCESINK atapiR3MechanismStatusSS;
777static FNSOURCESINK atapiR3ModeSenseErrorRecoverySS;
778static FNSOURCESINK atapiR3ModeSenseCDStatusSS;
779static FNSOURCESINK atapiR3ReadSS;
780static FNSOURCESINK atapiR3ReadCapacitySS;
781static FNSOURCESINK atapiR3ReadDiscInformationSS;
782static FNSOURCESINK atapiR3ReadTOCNormalSS;
783static FNSOURCESINK atapiR3ReadTOCMultiSS;
784static FNSOURCESINK atapiR3ReadTOCRawSS;
785static FNSOURCESINK atapiR3ReadTrackInformationSS;
786static FNSOURCESINK atapiR3RequestSenseSS;
787static FNSOURCESINK atapiR3PassthroughSS;
788static FNSOURCESINK atapiR3ReadDVDStructureSS;
789# endif /* IN_RING3 */
790
791/**
792 * Begin of transfer function indexes for g_apfnBeginTransFuncs.
793 */
794typedef enum ATAFNBT
795{
796 ATAFN_BT_NULL = 0,
797 ATAFN_BT_READ_WRITE_SECTORS,
798 ATAFN_BT_PACKET,
799 ATAFN_BT_ATAPI_CMD,
800 ATAFN_BT_ATAPI_PASSTHROUGH_CMD,
801 ATAFN_BT_MAX
802} ATAFNBT;
803
804# ifdef IN_RING3
805/**
806 * Array of end transfer functions, the index is ATAFNET.
807 * Make sure ATAFNET and this array match!
808 */
809static const PFNBEGINTRANSFER g_apfnBeginTransFuncs[ATAFN_BT_MAX] =
810{
811 NULL,
812 ataR3ReadWriteSectorsBT,
813 ataR3PacketBT,
814 atapiR3CmdBT,
815 atapiR3PassthroughCmdBT,
816};
817# endif /* IN_RING3 */
818
819/**
820 * Source/sink function indexes for g_apfnSourceSinkFuncs.
821 */
822typedef enum ATAFNSS
823{
824 ATAFN_SS_NULL = 0,
825 ATAFN_SS_IDENTIFY,
826 ATAFN_SS_FLUSH,
827 ATAFN_SS_READ_SECTORS,
828 ATAFN_SS_WRITE_SECTORS,
829 ATAFN_SS_EXECUTE_DEVICE_DIAGNOSTIC,
830 ATAFN_SS_TRIM,
831 ATAFN_SS_PACKET,
832 ATAFN_SS_INITIALIZE_DEVICE_PARAMETERS,
833 ATAFN_SS_RECALIBRATE,
834 ATAFN_SS_ATAPI_GET_CONFIGURATION,
835 ATAFN_SS_ATAPI_GET_EVENT_STATUS_NOTIFICATION,
836 ATAFN_SS_ATAPI_IDENTIFY,
837 ATAFN_SS_ATAPI_INQUIRY,
838 ATAFN_SS_ATAPI_MECHANISM_STATUS,
839 ATAFN_SS_ATAPI_MODE_SENSE_ERROR_RECOVERY,
840 ATAFN_SS_ATAPI_MODE_SENSE_CD_STATUS,
841 ATAFN_SS_ATAPI_READ,
842 ATAFN_SS_ATAPI_READ_CAPACITY,
843 ATAFN_SS_ATAPI_READ_DISC_INFORMATION,
844 ATAFN_SS_ATAPI_READ_TOC_NORMAL,
845 ATAFN_SS_ATAPI_READ_TOC_MULTI,
846 ATAFN_SS_ATAPI_READ_TOC_RAW,
847 ATAFN_SS_ATAPI_READ_TRACK_INFORMATION,
848 ATAFN_SS_ATAPI_REQUEST_SENSE,
849 ATAFN_SS_ATAPI_PASSTHROUGH,
850 ATAFN_SS_ATAPI_READ_DVD_STRUCTURE,
851 ATAFN_SS_MAX
852} ATAFNSS;
853
854# ifdef IN_RING3
855/**
856 * Array of source/sink functions, the index is ATAFNSS.
857 * Make sure ATAFNSS and this array match!
858 */
859static const PFNSOURCESINK g_apfnSourceSinkFuncs[ATAFN_SS_MAX] =
860{
861 NULL,
862 ataR3IdentifySS,
863 ataR3FlushSS,
864 ataR3ReadSectorsSS,
865 ataR3WriteSectorsSS,
866 ataR3ExecuteDeviceDiagnosticSS,
867 ataR3TrimSS,
868 ataR3PacketSS,
869 ataR3InitDevParmSS,
870 ataR3RecalibrateSS,
871 atapiR3GetConfigurationSS,
872 atapiR3GetEventStatusNotificationSS,
873 atapiR3IdentifySS,
874 atapiR3InquirySS,
875 atapiR3MechanismStatusSS,
876 atapiR3ModeSenseErrorRecoverySS,
877 atapiR3ModeSenseCDStatusSS,
878 atapiR3ReadSS,
879 atapiR3ReadCapacitySS,
880 atapiR3ReadDiscInformationSS,
881 atapiR3ReadTOCNormalSS,
882 atapiR3ReadTOCMultiSS,
883 atapiR3ReadTOCRawSS,
884 atapiR3ReadTrackInformationSS,
885 atapiR3RequestSenseSS,
886 atapiR3PassthroughSS,
887 atapiR3ReadDVDStructureSS
888};
889# endif /* IN_RING3 */
890
891
892static const ATARequest g_ataDMARequest = { ATA_AIO_DMA, { { 0, 0, 0, 0, 0 } } };
893static const ATARequest g_ataPIORequest = { ATA_AIO_PIO, { { 0, 0, 0, 0, 0 } } };
894# ifdef IN_RING3
895static const ATARequest g_ataResetARequest = { ATA_AIO_RESET_ASSERTED, { { 0, 0, 0, 0, 0 } } };
896static const ATARequest g_ataResetCRequest = { ATA_AIO_RESET_CLEARED, { { 0, 0, 0, 0, 0 } } };
897# endif
898
899# ifdef IN_RING3
900static void ataR3AsyncIOClearRequests(PPDMDEVINS pDevIns, PATACONTROLLER pCtl)
901{
902 int rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->AsyncIORequestLock, VINF_SUCCESS);
903 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pCtl->AsyncIORequestLock, rc);
904
905 pCtl->AsyncIOReqHead = 0;
906 pCtl->AsyncIOReqTail = 0;
907
908 rc = PDMDevHlpCritSectLeave(pDevIns, &pCtl->AsyncIORequestLock);
909 AssertRC(rc);
910}
911# endif /* IN_RING3 */
912
913static void ataHCAsyncIOPutRequest(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, const ATARequest *pReq)
914{
915 int rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->AsyncIORequestLock, VINF_SUCCESS);
916 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pCtl->AsyncIORequestLock, rc);
917
918 uint8_t const iAsyncIORequest = pCtl->AsyncIOReqHead % RT_ELEMENTS(pCtl->aAsyncIORequests);
919 Assert((iAsyncIORequest + 1) % RT_ELEMENTS(pCtl->aAsyncIORequests) != pCtl->AsyncIOReqTail);
920 memcpy(&pCtl->aAsyncIORequests[iAsyncIORequest], pReq, sizeof(*pReq));
921 pCtl->AsyncIOReqHead = (iAsyncIORequest + 1) % RT_ELEMENTS(pCtl->aAsyncIORequests);
922
923 rc = PDMDevHlpCritSectLeave(pDevIns, &pCtl->AsyncIORequestLock);
924 AssertRC(rc);
925
926 rc = PDMDevHlpCritSectScheduleExitEvent(pDevIns, &pCtl->lock, pCtl->hAsyncIOSem);
927 if (RT_FAILURE(rc))
928 {
929 rc = PDMDevHlpSUPSemEventSignal(pDevIns, pCtl->hAsyncIOSem);
930 AssertRC(rc);
931 }
932}
933
934# ifdef IN_RING3
935
936static const ATARequest *ataR3AsyncIOGetCurrentRequest(PPDMDEVINS pDevIns, PATACONTROLLER pCtl)
937{
938 const ATARequest *pReq;
939
940 int rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->AsyncIORequestLock, VINF_SUCCESS);
941 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pCtl->AsyncIORequestLock, rc);
942
943 if (pCtl->AsyncIOReqHead != pCtl->AsyncIOReqTail)
944 pReq = &pCtl->aAsyncIORequests[pCtl->AsyncIOReqTail];
945 else
946 pReq = NULL;
947
948 rc = PDMDevHlpCritSectLeave(pDevIns, &pCtl->AsyncIORequestLock);
949 AssertRC(rc);
950 return pReq;
951}
952
953
954/**
955 * Remove the request with the given type, as it's finished. The request
956 * is not removed blindly, as this could mean a RESET request that is not
957 * yet processed (but has cleared the request queue) is lost.
958 *
959 * @param pDevIns The device instance.
960 * @param pCtl Controller for which to remove the request.
961 * @param ReqType Type of the request to remove.
962 */
963static void ataR3AsyncIORemoveCurrentRequest(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, ATAAIO ReqType)
964{
965 int rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->AsyncIORequestLock, VINF_SUCCESS);
966 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pCtl->AsyncIORequestLock, rc);
967
968 if (pCtl->AsyncIOReqHead != pCtl->AsyncIOReqTail && pCtl->aAsyncIORequests[pCtl->AsyncIOReqTail].ReqType == ReqType)
969 {
970 pCtl->AsyncIOReqTail++;
971 pCtl->AsyncIOReqTail %= RT_ELEMENTS(pCtl->aAsyncIORequests);
972 }
973
974 rc = PDMDevHlpCritSectLeave(pDevIns, &pCtl->AsyncIORequestLock);
975 AssertRC(rc);
976}
977
978
979/**
980 * Dump the request queue for a particular controller. First dump the queue
981 * contents, then the already processed entries, as long as they haven't been
982 * overwritten.
983 *
984 * @param pDevIns The device instance.
985 * @param pCtl Controller for which to dump the queue.
986 */
987static void ataR3AsyncIODumpRequests(PPDMDEVINS pDevIns, PATACONTROLLER pCtl)
988{
989 int rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->AsyncIORequestLock, VINF_SUCCESS);
990 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pCtl->AsyncIORequestLock, rc);
991
992 LogRel(("PIIX3 ATA: Ctl#%d: request queue dump (topmost is current):\n", pCtl->iCtl));
993 uint8_t curr = pCtl->AsyncIOReqTail;
994 do
995 {
996 if (curr == pCtl->AsyncIOReqHead)
997 LogRel(("PIIX3 ATA: Ctl#%d: processed requests (topmost is oldest):\n", pCtl->iCtl));
998 switch (pCtl->aAsyncIORequests[curr].ReqType)
999 {
1000 case ATA_AIO_NEW:
1001 LogRel(("new transfer request, iIf=%d iBeginTransfer=%d iSourceSink=%d cbTotalTransfer=%d uTxDir=%d\n",
1002 pCtl->aAsyncIORequests[curr].u.t.iIf, pCtl->aAsyncIORequests[curr].u.t.iBeginTransfer,
1003 pCtl->aAsyncIORequests[curr].u.t.iSourceSink, pCtl->aAsyncIORequests[curr].u.t.cbTotalTransfer,
1004 pCtl->aAsyncIORequests[curr].u.t.uTxDir));
1005 break;
1006 case ATA_AIO_DMA:
1007 LogRel(("dma transfer continuation\n"));
1008 break;
1009 case ATA_AIO_PIO:
1010 LogRel(("pio transfer continuation\n"));
1011 break;
1012 case ATA_AIO_RESET_ASSERTED:
1013 LogRel(("reset asserted request\n"));
1014 break;
1015 case ATA_AIO_RESET_CLEARED:
1016 LogRel(("reset cleared request\n"));
1017 break;
1018 case ATA_AIO_ABORT:
1019 LogRel(("abort request, iIf=%d fResetDrive=%d\n", pCtl->aAsyncIORequests[curr].u.a.iIf,
1020 pCtl->aAsyncIORequests[curr].u.a.fResetDrive));
1021 break;
1022 default:
1023 LogRel(("unknown request %d\n", pCtl->aAsyncIORequests[curr].ReqType));
1024 }
1025 curr = (curr + 1) % RT_ELEMENTS(pCtl->aAsyncIORequests);
1026 } while (curr != pCtl->AsyncIOReqTail);
1027
1028 rc = PDMDevHlpCritSectLeave(pDevIns, &pCtl->AsyncIORequestLock);
1029 AssertRC(rc);
1030}
1031
1032
1033/**
1034 * Checks whether the request queue for a particular controller is empty
1035 * or whether a particular controller is idle.
1036 *
1037 * @param pDevIns The device instance.
1038 * @param pCtl Controller for which to check the queue.
1039 * @param fStrict If set then the controller is checked to be idle.
1040 */
1041static bool ataR3AsyncIOIsIdle(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, bool fStrict)
1042{
1043 int rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->AsyncIORequestLock, VINF_SUCCESS);
1044 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pCtl->AsyncIORequestLock, rc);
1045
1046 bool fIdle = pCtl->fRedoIdle;
1047 if (!fIdle)
1048 fIdle = (pCtl->AsyncIOReqHead == pCtl->AsyncIOReqTail);
1049 if (fStrict)
1050 fIdle &= (pCtl->uAsyncIOState == ATA_AIO_NEW);
1051
1052 rc = PDMDevHlpCritSectLeave(pDevIns, &pCtl->AsyncIORequestLock);
1053 AssertRC(rc);
1054 return fIdle;
1055}
1056
1057
1058/**
1059 * Send a transfer request to the async I/O thread.
1060 *
1061 * @param pDevIns The device instance.
1062 * @param pCtl The ATA controller.
1063 * @param s Pointer to the ATA device state data.
1064 * @param cbTotalTransfer Data transfer size.
1065 * @param uTxDir Data transfer direction.
1066 * @param iBeginTransfer Index of BeginTransfer callback.
1067 * @param iSourceSink Index of SourceSink callback.
1068 * @param fChainedTransfer Whether this is a transfer that is part of the previous command/transfer.
1069 */
1070static void ataR3StartTransfer(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s,
1071 uint32_t cbTotalTransfer, uint8_t uTxDir, ATAFNBT iBeginTransfer,
1072 ATAFNSS iSourceSink, bool fChainedTransfer)
1073{
1074 ATARequest Req;
1075
1076 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pCtl->lock));
1077
1078 /* Do not issue new requests while the RESET line is asserted. */
1079 if (pCtl->fReset)
1080 {
1081 Log2(("%s: Ctl#%d: suppressed new request as RESET is active\n", __FUNCTION__, pCtl->iCtl));
1082 return;
1083 }
1084
1085 /* If the controller is already doing something else right now, ignore
1086 * the command that is being submitted. Some broken guests issue commands
1087 * twice (e.g. the Linux kernel that comes with Acronis True Image 8). */
1088 if (!fChainedTransfer && !ataR3AsyncIOIsIdle(pDevIns, pCtl, true /*fStrict*/))
1089 {
1090 Log(("%s: Ctl#%d: ignored command %#04x, controller state %d\n", __FUNCTION__, pCtl->iCtl, s->uATARegCommand, pCtl->uAsyncIOState));
1091 LogRel(("PIIX3 IDE: guest issued command %#04x while controller busy\n", s->uATARegCommand));
1092 return;
1093 }
1094
1095 Req.ReqType = ATA_AIO_NEW;
1096 if (fChainedTransfer)
1097 Req.u.t.iIf = pCtl->iAIOIf;
1098 else
1099 Req.u.t.iIf = pCtl->iSelectedIf;
1100 Req.u.t.cbTotalTransfer = cbTotalTransfer;
1101 Req.u.t.uTxDir = uTxDir;
1102 Req.u.t.iBeginTransfer = iBeginTransfer;
1103 Req.u.t.iSourceSink = iSourceSink;
1104 ataSetStatusValue(pCtl, s, ATA_STAT_BUSY);
1105 pCtl->fChainedTransfer = fChainedTransfer;
1106
1107 /*
1108 * Kick the worker thread into action.
1109 */
1110 Log2(("%s: Ctl#%d: message to async I/O thread, new request\n", __FUNCTION__, pCtl->iCtl));
1111 ataHCAsyncIOPutRequest(pDevIns, pCtl, &Req);
1112}
1113
1114
1115/**
1116 * Send an abort command request to the async I/O thread.
1117 *
1118 * @param pDevIns The device instance.
1119 * @param pCtl The ATA controller.
1120 * @param s Pointer to the ATA device state data.
1121 * @param fResetDrive Whether to reset the drive or just abort a command.
1122 */
1123static void ataR3AbortCurrentCommand(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, bool fResetDrive)
1124{
1125 ATARequest Req;
1126
1127 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pCtl->lock));
1128
1129 /* Do not issue new requests while the RESET line is asserted. */
1130 if (pCtl->fReset)
1131 {
1132 Log2(("%s: Ctl#%d: suppressed aborting command as RESET is active\n", __FUNCTION__, pCtl->iCtl));
1133 return;
1134 }
1135
1136 Req.ReqType = ATA_AIO_ABORT;
1137 Req.u.a.iIf = pCtl->iSelectedIf;
1138 Req.u.a.fResetDrive = fResetDrive;
1139 ataSetStatus(pCtl, s, ATA_STAT_BUSY);
1140 Log2(("%s: Ctl#%d: message to async I/O thread, abort command on LUN#%d\n", __FUNCTION__, pCtl->iCtl, s->iLUN));
1141 ataHCAsyncIOPutRequest(pDevIns, pCtl, &Req);
1142}
1143
1144# endif /* IN_RING3 */
1145
1146/**
1147 * Set the internal interrupt pending status, update INTREQ as appropriate.
1148 *
1149 * @param pDevIns The device instance.
1150 * @param pCtl The ATA controller.
1151 * @param s Pointer to the ATA device state data.
1152 */
1153static void ataHCSetIRQ(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s)
1154{
1155 if (!s->fIrqPending)
1156 {
1157 if (!(s->uATARegDevCtl & ATA_DEVCTL_DISABLE_IRQ))
1158 {
1159 Log2(("%s: LUN#%d asserting IRQ\n", __FUNCTION__, s->iLUN));
1160 /* The BMDMA unit unconditionally sets BM_STATUS_INT if the interrupt
1161 * line is asserted. It monitors the line for a rising edge. */
1162 pCtl->BmDma.u8Status |= BM_STATUS_INT;
1163 /* Only actually set the IRQ line if updating the currently selected drive. */
1164 if (s == &pCtl->aIfs[pCtl->iSelectedIf & ATA_SELECTED_IF_MASK])
1165 {
1166 /** @todo experiment with adaptive IRQ delivery: for reads it is
1167 * better to wait for IRQ delivery, as it reduces latency. */
1168 if (pCtl->irq == 16)
1169 PDMDevHlpPCISetIrq(pDevIns, 0, 1);
1170 else
1171 PDMDevHlpISASetIrq(pDevIns, pCtl->irq, 1);
1172 }
1173 }
1174 s->fIrqPending = true;
1175 }
1176}
1177
1178#endif /* IN_RING0 || IN_RING3 */
1179
1180/**
1181 * Clear the internal interrupt pending status, update INTREQ as appropriate.
1182 *
1183 * @param pDevIns The device instance.
1184 * @param pCtl The ATA controller.
1185 * @param s Pointer to the ATA device state data.
1186 */
1187static void ataUnsetIRQ(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s)
1188{
1189 if (s->fIrqPending)
1190 {
1191 if (!(s->uATARegDevCtl & ATA_DEVCTL_DISABLE_IRQ))
1192 {
1193 Log2(("%s: LUN#%d deasserting IRQ\n", __FUNCTION__, s->iLUN));
1194 /* Only actually unset the IRQ line if updating the currently selected drive. */
1195 if (s == &pCtl->aIfs[pCtl->iSelectedIf & ATA_SELECTED_IF_MASK])
1196 {
1197 if (pCtl->irq == 16)
1198 PDMDevHlpPCISetIrq(pDevIns, 0, 0);
1199 else
1200 PDMDevHlpISASetIrq(pDevIns, pCtl->irq, 0);
1201 }
1202 }
1203 s->fIrqPending = false;
1204 }
1205}
1206
1207#if defined(IN_RING0) || defined(IN_RING3)
1208
1209static void ataHCPIOTransferStart(PATACONTROLLER pCtl, PATADEVSTATE s, uint32_t start, uint32_t size)
1210{
1211 Log2(("%s: LUN#%d start %d size %d\n", __FUNCTION__, s->iLUN, start, size));
1212 s->iIOBufferPIODataStart = start;
1213 s->iIOBufferPIODataEnd = start + size;
1214 ataSetStatus(pCtl, s, ATA_STAT_DRQ | ATA_STAT_SEEK);
1215 ataUnsetStatus(pCtl, s, ATA_STAT_BUSY);
1216}
1217
1218
1219static void ataHCPIOTransferStop(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s)
1220{
1221 Log2(("%s: LUN#%d\n", __FUNCTION__, s->iLUN));
1222 if (s->fATAPITransfer)
1223 {
1224 s->uATARegNSector = (s->uATARegNSector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
1225 Log2(("%s: interrupt reason %#04x\n", __FUNCTION__, s->uATARegNSector));
1226 ataHCSetIRQ(pDevIns, pCtl, s);
1227 s->fATAPITransfer = false;
1228 }
1229 s->cbTotalTransfer = 0;
1230 s->cbElementaryTransfer = 0;
1231 s->iIOBufferPIODataStart = 0;
1232 s->iIOBufferPIODataEnd = 0;
1233 s->iBeginTransfer = ATAFN_BT_NULL;
1234 s->iSourceSink = ATAFN_SS_NULL;
1235}
1236
1237
1238static void ataHCPIOTransferLimitATAPI(PATADEVSTATE s)
1239{
1240 uint32_t cbLimit, cbTransfer;
1241
1242 cbLimit = s->cbPIOTransferLimit;
1243 /* Use maximum transfer size if the guest requested 0. Avoids a hang. */
1244 if (cbLimit == 0)
1245 cbLimit = 0xfffe;
1246 Log2(("%s: byte count limit=%d\n", __FUNCTION__, cbLimit));
1247 if (cbLimit == 0xffff)
1248 cbLimit--;
1249 cbTransfer = RT_MIN(s->cbTotalTransfer, s->iIOBufferEnd - s->iIOBufferCur);
1250 if (cbTransfer > cbLimit)
1251 {
1252 /* Byte count limit for clipping must be even in this case */
1253 if (cbLimit & 1)
1254 cbLimit--;
1255 cbTransfer = cbLimit;
1256 }
1257 s->uATARegLCyl = cbTransfer;
1258 s->uATARegHCyl = cbTransfer >> 8;
1259 s->cbElementaryTransfer = cbTransfer;
1260}
1261
1262# ifdef IN_RING3
1263
1264/**
1265 * Enters the lock protecting the controller data against concurrent access.
1266 *
1267 * @returns nothing.
1268 * @param pDevIns The device instance.
1269 * @param pCtl The controller to lock.
1270 */
1271DECLINLINE(void) ataR3LockEnter(PPDMDEVINS pDevIns, PATACONTROLLER pCtl)
1272{
1273 STAM_PROFILE_START(&pCtl->StatLockWait, a);
1274 int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pCtl->lock, VINF_SUCCESS);
1275 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pCtl->lock, rcLock);
1276 STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
1277}
1278
1279/**
1280 * Leaves the lock protecting the controller against concurrent data access.
1281 *
1282 * @returns nothing.
1283 * @param pDevIns The device instance.
1284 * @param pCtl The controller to unlock.
1285 */
1286DECLINLINE(void) ataR3LockLeave(PPDMDEVINS pDevIns, PATACONTROLLER pCtl)
1287{
1288 PDMDevHlpCritSectLeave(pDevIns, &pCtl->lock);
1289}
1290
1291static uint32_t ataR3GetNSectors(PATADEVSTATE s)
1292{
1293 /* 0 means either 256 (LBA28) or 65536 (LBA48) sectors. */
1294 if (s->fLBA48)
1295 {
1296 if (!s->uATARegNSector && !s->uATARegNSectorHOB)
1297 return 65536;
1298 else
1299 return s->uATARegNSectorHOB << 8 | s->uATARegNSector;
1300 }
1301 else
1302 {
1303 if (!s->uATARegNSector)
1304 return 256;
1305 else
1306 return s->uATARegNSector;
1307 }
1308}
1309
1310
1311static void ataR3PadString(uint8_t *pbDst, const char *pbSrc, uint32_t cbSize)
1312{
1313 for (uint32_t i = 0; i < cbSize; i++)
1314 {
1315 if (*pbSrc)
1316 pbDst[i ^ 1] = *pbSrc++;
1317 else
1318 pbDst[i ^ 1] = ' ';
1319 }
1320}
1321
1322
1323#if 0 /* unused */
1324/**
1325 * Compares two MSF values.
1326 *
1327 * @returns 1 if the first value is greater than the second value.
1328 * 0 if both are equal
1329 * -1 if the first value is smaller than the second value.
1330 */
1331DECLINLINE(int) atapiCmpMSF(const uint8_t *pbMSF1, const uint8_t *pbMSF2)
1332{
1333 int iRes = 0;
1334
1335 for (unsigned i = 0; i < 3; i++)
1336 {
1337 if (pbMSF1[i] < pbMSF2[i])
1338 {
1339 iRes = -1;
1340 break;
1341 }
1342 else if (pbMSF1[i] > pbMSF2[i])
1343 {
1344 iRes = 1;
1345 break;
1346 }
1347 }
1348
1349 return iRes;
1350}
1351#endif /* unused */
1352
1353static void ataR3CmdOK(PATACONTROLLER pCtl, PATADEVSTATE s, uint8_t status)
1354{
1355 s->uATARegError = 0; /* Not needed by ATA spec, but cannot hurt. */
1356 ataSetStatusValue(pCtl, s, ATA_STAT_READY | status);
1357}
1358
1359
1360static void ataR3CmdError(PATACONTROLLER pCtl, PATADEVSTATE s, uint8_t uErrorCode)
1361{
1362 Log(("%s: code=%#x\n", __FUNCTION__, uErrorCode));
1363 Assert(uErrorCode);
1364 s->uATARegError = uErrorCode;
1365 ataSetStatusValue(pCtl, s, ATA_STAT_READY | ATA_STAT_SEEK | ATA_STAT_ERR);
1366 s->cbTotalTransfer = 0;
1367 s->cbElementaryTransfer = 0;
1368 s->iIOBufferCur = 0;
1369 s->iIOBufferEnd = 0;
1370 s->uTxDir = PDMMEDIATXDIR_NONE;
1371 s->iBeginTransfer = ATAFN_BT_NULL;
1372 s->iSourceSink = ATAFN_SS_NULL;
1373}
1374
1375static uint32_t ataR3Checksum(void* ptr, size_t count)
1376{
1377 uint8_t u8Sum = 0xa5, *p = (uint8_t*)ptr;
1378 size_t i;
1379
1380 for (i = 0; i < count; i++)
1381 {
1382 u8Sum += *p++;
1383 }
1384
1385 return (uint8_t)-(int32_t)u8Sum;
1386}
1387
1388/**
1389 * Sink/Source: IDENTIFY
1390 */
1391static bool ataR3IdentifySS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3)
1392{
1393 uint16_t *p;
1394 RT_NOREF(pDevIns);
1395
1396 Assert(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE);
1397 Assert(s->cbElementaryTransfer == 512);
1398
1399 p = (uint16_t *)&s->abIOBuffer[0];
1400 memset(p, 0, 512);
1401 p[0] = RT_H2LE_U16(0x0040);
1402 p[1] = RT_H2LE_U16(RT_MIN(s->PCHSGeometry.cCylinders, 16383));
1403 p[3] = RT_H2LE_U16(s->PCHSGeometry.cHeads);
1404 /* Block size; obsolete, but required for the BIOS. */
1405 p[5] = RT_H2LE_U16(s->cbSector);
1406 p[6] = RT_H2LE_U16(s->PCHSGeometry.cSectors);
1407 ataR3PadString((uint8_t *)(p + 10), s->szSerialNumber, ATA_SERIAL_NUMBER_LENGTH); /* serial number */
1408 p[20] = RT_H2LE_U16(3); /* XXX: retired, cache type */
1409 p[21] = RT_H2LE_U16(512); /* XXX: retired, cache size in sectors */
1410 p[22] = RT_H2LE_U16(0); /* ECC bytes per sector */
1411 ataR3PadString((uint8_t *)(p + 23), s->szFirmwareRevision, ATA_FIRMWARE_REVISION_LENGTH); /* firmware version */
1412 ataR3PadString((uint8_t *)(p + 27), s->szModelNumber, ATA_MODEL_NUMBER_LENGTH); /* model */
1413# if ATA_MAX_MULT_SECTORS > 1
1414 p[47] = RT_H2LE_U16(0x8000 | ATA_MAX_MULT_SECTORS);
1415# endif
1416 p[48] = RT_H2LE_U16(1); /* dword I/O, used by the BIOS */
1417 p[49] = RT_H2LE_U16(1 << 11 | 1 << 9 | 1 << 8); /* DMA and LBA supported */
1418 p[50] = RT_H2LE_U16(1 << 14); /* No drive specific standby timer minimum */
1419 p[51] = RT_H2LE_U16(240); /* PIO transfer cycle */
1420 p[52] = RT_H2LE_U16(240); /* DMA transfer cycle */
1421 p[53] = RT_H2LE_U16(1 | 1 << 1 | 1 << 2); /* words 54-58,64-70,88 valid */
1422 p[54] = RT_H2LE_U16(RT_MIN(s->XCHSGeometry.cCylinders, 16383));
1423 p[55] = RT_H2LE_U16(s->XCHSGeometry.cHeads);
1424 p[56] = RT_H2LE_U16(s->XCHSGeometry.cSectors);
1425 p[57] = RT_H2LE_U16( RT_MIN(s->XCHSGeometry.cCylinders, 16383)
1426 * s->XCHSGeometry.cHeads
1427 * s->XCHSGeometry.cSectors);
1428 p[58] = RT_H2LE_U16( RT_MIN(s->XCHSGeometry.cCylinders, 16383)
1429 * s->XCHSGeometry.cHeads
1430 * s->XCHSGeometry.cSectors >> 16);
1431 if (s->cMultSectors)
1432 p[59] = RT_H2LE_U16(0x100 | s->cMultSectors);
1433 if (s->cTotalSectors <= (1 << 28) - 1)
1434 {
1435 p[60] = RT_H2LE_U16(s->cTotalSectors);
1436 p[61] = RT_H2LE_U16(s->cTotalSectors >> 16);
1437 }
1438 else
1439 {
1440 /* Report maximum number of sectors possible with LBA28 */
1441 p[60] = RT_H2LE_U16(((1 << 28) - 1) & 0xffff);
1442 p[61] = RT_H2LE_U16(((1 << 28) - 1) >> 16);
1443 }
1444 p[63] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_MDMA, ATA_MDMA_MODE_MAX, s->uATATransferMode)); /* MDMA modes supported / mode enabled */
1445 p[64] = RT_H2LE_U16(ATA_PIO_MODE_MAX > 2 ? (1 << (ATA_PIO_MODE_MAX - 2)) - 1 : 0); /* PIO modes beyond PIO2 supported */
1446 p[65] = RT_H2LE_U16(120); /* minimum DMA multiword tx cycle time */
1447 p[66] = RT_H2LE_U16(120); /* recommended DMA multiword tx cycle time */
1448 p[67] = RT_H2LE_U16(120); /* minimum PIO cycle time without flow control */
1449 p[68] = RT_H2LE_U16(120); /* minimum PIO cycle time with IORDY flow control */
1450 if ( pDevR3->pDrvMedia->pfnDiscard
1451 || s->cbSector != 512
1452 || pDevR3->pDrvMedia->pfnIsNonRotational(pDevR3->pDrvMedia))
1453 {
1454 p[80] = RT_H2LE_U16(0x1f0); /* support everything up to ATA/ATAPI-8 ACS */
1455 p[81] = RT_H2LE_U16(0x28); /* conforms to ATA/ATAPI-8 ACS */
1456 }
1457 else
1458 {
1459 p[80] = RT_H2LE_U16(0x7e); /* support everything up to ATA/ATAPI-6 */
1460 p[81] = RT_H2LE_U16(0x22); /* conforms to ATA/ATAPI-6 */
1461 }
1462 p[82] = RT_H2LE_U16(1 << 3 | 1 << 5 | 1 << 6); /* supports power management, write cache and look-ahead */
1463 if (s->cTotalSectors <= (1 << 28) - 1)
1464 p[83] = RT_H2LE_U16(1 << 14 | 1 << 12); /* supports FLUSH CACHE */
1465 else
1466 p[83] = RT_H2LE_U16(1 << 14 | 1 << 10 | 1 << 12 | 1 << 13); /* supports LBA48, FLUSH CACHE and FLUSH CACHE EXT */
1467 p[84] = RT_H2LE_U16(1 << 14);
1468 p[85] = RT_H2LE_U16(1 << 3 | 1 << 5 | 1 << 6); /* enabled power management, write cache and look-ahead */
1469 if (s->cTotalSectors <= (1 << 28) - 1)
1470 p[86] = RT_H2LE_U16(1 << 12); /* enabled FLUSH CACHE */
1471 else
1472 p[86] = RT_H2LE_U16(1 << 10 | 1 << 12 | 1 << 13); /* enabled LBA48, FLUSH CACHE and FLUSH CACHE EXT */
1473 p[87] = RT_H2LE_U16(1 << 14);
1474 p[88] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_UDMA, ATA_UDMA_MODE_MAX, s->uATATransferMode)); /* UDMA modes supported / mode enabled */
1475 p[93] = RT_H2LE_U16((1 | 1 << 1) << ((s->iLUN & 1) == 0 ? 0 : 8) | 1 << 13 | 1 << 14);
1476 if (s->cTotalSectors > (1 << 28) - 1)
1477 {
1478 p[100] = RT_H2LE_U16(s->cTotalSectors);
1479 p[101] = RT_H2LE_U16(s->cTotalSectors >> 16);
1480 p[102] = RT_H2LE_U16(s->cTotalSectors >> 32);
1481 p[103] = RT_H2LE_U16(s->cTotalSectors >> 48);
1482 }
1483
1484 if (s->cbSector != 512)
1485 {
1486 uint32_t cSectorSizeInWords = s->cbSector / sizeof(uint16_t);
1487 /* Enable reporting of logical sector size. */
1488 p[106] |= RT_H2LE_U16(RT_BIT(12) | RT_BIT(14));
1489 p[117] = RT_H2LE_U16(cSectorSizeInWords);
1490 p[118] = RT_H2LE_U16(cSectorSizeInWords >> 16);
1491 }
1492
1493 if (pDevR3->pDrvMedia->pfnDiscard) /** @todo Set bit 14 in word 69 too? (Deterministic read after TRIM). */
1494 p[169] = RT_H2LE_U16(1); /* DATA SET MANAGEMENT command supported. */
1495 if (pDevR3->pDrvMedia->pfnIsNonRotational(pDevR3->pDrvMedia))
1496 p[217] = RT_H2LE_U16(1); /* Non-rotational medium */
1497 uint32_t uCsum = ataR3Checksum(p, 510);
1498 p[255] = RT_H2LE_U16(0xa5 | (uCsum << 8)); /* Integrity word */
1499 s->iSourceSink = ATAFN_SS_NULL;
1500 ataR3CmdOK(pCtl, s, ATA_STAT_SEEK);
1501 return false;
1502}
1503
1504
1505/**
1506 * Sink/Source: FLUSH
1507 */
1508static bool ataR3FlushSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3)
1509{
1510 int rc;
1511
1512 Assert(s->uTxDir == PDMMEDIATXDIR_NONE);
1513 Assert(!s->cbElementaryTransfer);
1514
1515 ataR3LockLeave(pDevIns, pCtl);
1516
1517 STAM_PROFILE_START(&s->StatFlushes, f);
1518 rc = pDevR3->pDrvMedia->pfnFlush(pDevR3->pDrvMedia);
1519 AssertRC(rc);
1520 STAM_PROFILE_STOP(&s->StatFlushes, f);
1521
1522 ataR3LockEnter(pDevIns, pCtl);
1523 ataR3CmdOK(pCtl, s, 0);
1524 return false;
1525}
1526
1527/**
1528 * Sink/Source: ATAPI IDENTIFY
1529 */
1530static bool atapiR3IdentifySS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3)
1531{
1532 uint16_t *p;
1533 RT_NOREF(pDevIns, pDevR3);
1534
1535 Assert(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE);
1536 Assert(s->cbElementaryTransfer == 512);
1537
1538 p = (uint16_t *)&s->abIOBuffer[0];
1539 memset(p, 0, 512);
1540 /* Removable CDROM, 3ms response, 12 byte packets */
1541 p[0] = RT_H2LE_U16(2 << 14 | 5 << 8 | 1 << 7 | 0 << 5 | 0 << 0);
1542 ataR3PadString((uint8_t *)(p + 10), s->szSerialNumber, ATA_SERIAL_NUMBER_LENGTH); /* serial number */
1543 p[20] = RT_H2LE_U16(3); /* XXX: retired, cache type */
1544 p[21] = RT_H2LE_U16(512); /* XXX: retired, cache size in sectors */
1545 ataR3PadString((uint8_t *)(p + 23), s->szFirmwareRevision, ATA_FIRMWARE_REVISION_LENGTH); /* firmware version */
1546 ataR3PadString((uint8_t *)(p + 27), s->szModelNumber, ATA_MODEL_NUMBER_LENGTH); /* model */
1547 p[49] = RT_H2LE_U16(1 << 11 | 1 << 9 | 1 << 8); /* DMA and LBA supported */
1548 p[50] = RT_H2LE_U16(1 << 14); /* No drive specific standby timer minimum */
1549 p[51] = RT_H2LE_U16(240); /* PIO transfer cycle */
1550 p[52] = RT_H2LE_U16(240); /* DMA transfer cycle */
1551 p[53] = RT_H2LE_U16(1 << 1 | 1 << 2); /* words 64-70,88 are valid */
1552 p[63] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_MDMA, ATA_MDMA_MODE_MAX, s->uATATransferMode)); /* MDMA modes supported / mode enabled */
1553 p[64] = RT_H2LE_U16(ATA_PIO_MODE_MAX > 2 ? (1 << (ATA_PIO_MODE_MAX - 2)) - 1 : 0); /* PIO modes beyond PIO2 supported */
1554 p[65] = RT_H2LE_U16(120); /* minimum DMA multiword tx cycle time */
1555 p[66] = RT_H2LE_U16(120); /* recommended DMA multiword tx cycle time */
1556 p[67] = RT_H2LE_U16(120); /* minimum PIO cycle time without flow control */
1557 p[68] = RT_H2LE_U16(120); /* minimum PIO cycle time with IORDY flow control */
1558 p[73] = RT_H2LE_U16(0x003e); /* ATAPI CDROM major */
1559 p[74] = RT_H2LE_U16(9); /* ATAPI CDROM minor */
1560 p[75] = RT_H2LE_U16(1); /* queue depth 1 */
1561 p[80] = RT_H2LE_U16(0x7e); /* support everything up to ATA/ATAPI-6 */
1562 p[81] = RT_H2LE_U16(0x22); /* conforms to ATA/ATAPI-6 */
1563 p[82] = RT_H2LE_U16(1 << 4 | 1 << 9); /* supports packet command set and DEVICE RESET */
1564 p[83] = RT_H2LE_U16(1 << 14);
1565 p[84] = RT_H2LE_U16(1 << 14);
1566 p[85] = RT_H2LE_U16(1 << 4 | 1 << 9); /* enabled packet command set and DEVICE RESET */
1567 p[86] = RT_H2LE_U16(0);
1568 p[87] = RT_H2LE_U16(1 << 14);
1569 p[88] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_UDMA, ATA_UDMA_MODE_MAX, s->uATATransferMode)); /* UDMA modes supported / mode enabled */
1570 p[93] = RT_H2LE_U16((1 | 1 << 1) << ((s->iLUN & 1) == 0 ? 0 : 8) | 1 << 13 | 1 << 14);
1571 /* According to ATAPI-5 spec:
1572 *
1573 * The use of this word is optional.
1574 * If bits 7:0 of this word contain the signature A5h, bits 15:8
1575 * contain the data
1576 * structure checksum.
1577 * The data structure checksum is the twos complement of the sum of
1578 * all bytes in words 0 through 254 and the byte consisting of
1579 * bits 7:0 in word 255.
1580 * Each byte shall be added with unsigned arithmetic,
1581 * and overflow shall be ignored.
1582 * The sum of all 512 bytes is zero when the checksum is correct.
1583 */
1584 uint32_t uCsum = ataR3Checksum(p, 510);
1585 p[255] = RT_H2LE_U16(0xa5 | (uCsum << 8)); /* Integrity word */
1586
1587 s->iSourceSink = ATAFN_SS_NULL;
1588 ataR3CmdOK(pCtl, s, ATA_STAT_SEEK);
1589 return false;
1590}
1591
1592
1593static void ataR3SetSignature(PATADEVSTATE s)
1594{
1595 s->uATARegSelect &= 0xf0; /* clear head */
1596 /* put signature */
1597 s->uATARegNSector = 1;
1598 s->uATARegSector = 1;
1599 if (s->fATAPI)
1600 {
1601 s->uATARegLCyl = 0x14;
1602 s->uATARegHCyl = 0xeb;
1603 }
1604 else
1605 {
1606 s->uATARegLCyl = 0;
1607 s->uATARegHCyl = 0;
1608 }
1609}
1610
1611
1612static uint64_t ataR3GetSector(PATADEVSTATE s)
1613{
1614 uint64_t iLBA;
1615 if (s->uATARegSelect & 0x40)
1616 {
1617 /* any LBA variant */
1618 if (s->fLBA48)
1619 {
1620 /* LBA48 */
1621 iLBA = ((uint64_t)s->uATARegHCylHOB << 40)
1622 | ((uint64_t)s->uATARegLCylHOB << 32)
1623 | ((uint64_t)s->uATARegSectorHOB << 24)
1624 | ((uint64_t)s->uATARegHCyl << 16)
1625 | ((uint64_t)s->uATARegLCyl << 8)
1626 | s->uATARegSector;
1627 }
1628 else
1629 {
1630 /* LBA */
1631 iLBA = ((uint32_t)(s->uATARegSelect & 0x0f) << 24)
1632 | ((uint32_t)s->uATARegHCyl << 16)
1633 | ((uint32_t)s->uATARegLCyl << 8)
1634 | s->uATARegSector;
1635 }
1636 }
1637 else
1638 {
1639 /* CHS */
1640 iLBA = (((uint32_t)s->uATARegHCyl << 8) | s->uATARegLCyl) * s->XCHSGeometry.cHeads * s->XCHSGeometry.cSectors
1641 + (s->uATARegSelect & 0x0f) * s->XCHSGeometry.cSectors
1642 + (s->uATARegSector - 1);
1643 LogFlowFunc(("CHS %u/%u/%u -> LBA %llu\n", ((uint32_t)s->uATARegHCyl << 8) | s->uATARegLCyl, s->uATARegSelect & 0x0f, s->uATARegSector, iLBA));
1644 }
1645 return iLBA;
1646}
1647
1648static void ataR3SetSector(PATADEVSTATE s, uint64_t iLBA)
1649{
1650 uint32_t cyl, r;
1651 if (s->uATARegSelect & 0x40)
1652 {
1653 /* any LBA variant */
1654 if (s->fLBA48)
1655 {
1656 /* LBA48 */
1657 s->uATARegHCylHOB = iLBA >> 40;
1658 s->uATARegLCylHOB = iLBA >> 32;
1659 s->uATARegSectorHOB = iLBA >> 24;
1660 s->uATARegHCyl = iLBA >> 16;
1661 s->uATARegLCyl = iLBA >> 8;
1662 s->uATARegSector = iLBA;
1663 }
1664 else
1665 {
1666 /* LBA */
1667 s->uATARegSelect = (s->uATARegSelect & 0xf0) | (iLBA >> 24);
1668 s->uATARegHCyl = (iLBA >> 16);
1669 s->uATARegLCyl = (iLBA >> 8);
1670 s->uATARegSector = (iLBA);
1671 }
1672 }
1673 else
1674 {
1675 /* CHS */
1676 AssertMsgReturnVoid(s->XCHSGeometry.cHeads && s->XCHSGeometry.cSectors, ("Device geometry not set!\n"));
1677 cyl = iLBA / (s->XCHSGeometry.cHeads * s->XCHSGeometry.cSectors);
1678 r = iLBA % (s->XCHSGeometry.cHeads * s->XCHSGeometry.cSectors);
1679 s->uATARegHCyl = cyl >> 8;
1680 s->uATARegLCyl = cyl;
1681 s->uATARegSelect = (s->uATARegSelect & 0xf0) | ((r / s->XCHSGeometry.cSectors) & 0x0f);
1682 s->uATARegSector = (r % s->XCHSGeometry.cSectors) + 1;
1683 LogFlowFunc(("LBA %llu -> CHS %u/%u/%u\n", iLBA, cyl, s->uATARegSelect & 0x0f, s->uATARegSector));
1684 }
1685}
1686
1687
1688static void ataR3WarningDiskFull(PPDMDEVINS pDevIns)
1689{
1690 int rc;
1691 LogRel(("PIIX3 ATA: Host disk full\n"));
1692 rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND | VMSETRTERR_FLAGS_NO_WAIT, "DevATA_DISKFULL",
1693 N_("Host system reported disk full. VM execution is suspended. You can resume after freeing some space"));
1694 AssertRC(rc);
1695}
1696
1697static void ataR3WarningFileTooBig(PPDMDEVINS pDevIns)
1698{
1699 int rc;
1700 LogRel(("PIIX3 ATA: File too big\n"));
1701 rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND | VMSETRTERR_FLAGS_NO_WAIT, "DevATA_FILETOOBIG",
1702 N_("Host system reported that the file size limit of the host file system has been exceeded. VM execution is suspended. You need to move your virtual hard disk to a filesystem which allows bigger files"));
1703 AssertRC(rc);
1704}
1705
1706static void ataR3WarningISCSI(PPDMDEVINS pDevIns)
1707{
1708 int rc;
1709 LogRel(("PIIX3 ATA: iSCSI target unavailable\n"));
1710 rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND | VMSETRTERR_FLAGS_NO_WAIT, "DevATA_ISCSIDOWN",
1711 N_("The iSCSI target has stopped responding. VM execution is suspended. You can resume when it is available again"));
1712 AssertRC(rc);
1713}
1714
1715static bool ataR3IsRedoSetWarning(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, int rc)
1716{
1717 Assert(!PDMDevHlpCritSectIsOwner(pDevIns, &pCtl->lock));
1718 if (rc == VERR_DISK_FULL)
1719 {
1720 pCtl->fRedoIdle = true;
1721 ataR3WarningDiskFull(pDevIns);
1722 return true;
1723 }
1724 if (rc == VERR_FILE_TOO_BIG)
1725 {
1726 pCtl->fRedoIdle = true;
1727 ataR3WarningFileTooBig(pDevIns);
1728 return true;
1729 }
1730 if (rc == VERR_BROKEN_PIPE || rc == VERR_NET_CONNECTION_REFUSED)
1731 {
1732 pCtl->fRedoIdle = true;
1733 /* iSCSI connection abort (first error) or failure to reestablish
1734 * connection (second error). Pause VM. On resume we'll retry. */
1735 ataR3WarningISCSI(pDevIns);
1736 return true;
1737 }
1738 if (rc == VERR_VD_DEK_MISSING)
1739 {
1740 /* Error message already set. */
1741 pCtl->fRedoIdle = true;
1742 return true;
1743 }
1744
1745 return false;
1746}
1747
1748
1749static int ataR3ReadSectors(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3,
1750 uint64_t u64Sector, void *pvBuf, uint32_t cSectors, bool *pfRedo)
1751{
1752 int rc;
1753 uint32_t const cbSector = s->cbSector;
1754 uint32_t cbToRead = cSectors * cbSector;
1755 Assert(pvBuf == &s->abIOBuffer[0]);
1756 AssertReturnStmt(cbToRead <= sizeof(s->abIOBuffer), *pfRedo = false, VERR_BUFFER_OVERFLOW);
1757
1758 ataR3LockLeave(pDevIns, pCtl);
1759
1760 STAM_PROFILE_ADV_START(&s->StatReads, r);
1761 s->Led.Asserted.s.fReading = s->Led.Actual.s.fReading = 1;
1762 rc = pDevR3->pDrvMedia->pfnRead(pDevR3->pDrvMedia, u64Sector * cbSector, pvBuf, cbToRead);
1763 s->Led.Actual.s.fReading = 0;
1764 STAM_PROFILE_ADV_STOP(&s->StatReads, r);
1765 Log4(("ataR3ReadSectors: rc=%Rrc cSectors=%#x u64Sector=%llu\n%.*Rhxd\n",
1766 rc, cSectors, u64Sector, cbToRead, pvBuf));
1767
1768 STAM_REL_COUNTER_ADD(&s->StatBytesRead, cbToRead);
1769
1770 if (RT_SUCCESS(rc))
1771 *pfRedo = false;
1772 else
1773 *pfRedo = ataR3IsRedoSetWarning(pDevIns, pCtl, rc);
1774
1775 ataR3LockEnter(pDevIns, pCtl);
1776 return rc;
1777}
1778
1779
1780static int ataR3WriteSectors(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3,
1781 uint64_t u64Sector, const void *pvBuf, uint32_t cSectors, bool *pfRedo)
1782{
1783 int rc;
1784 uint32_t const cbSector = s->cbSector;
1785 uint32_t cbToWrite = cSectors * cbSector;
1786 Assert(pvBuf == &s->abIOBuffer[0]);
1787 AssertReturnStmt(cbToWrite <= sizeof(s->abIOBuffer), *pfRedo = false, VERR_BUFFER_OVERFLOW);
1788
1789 ataR3LockLeave(pDevIns, pCtl);
1790
1791 STAM_PROFILE_ADV_START(&s->StatWrites, w);
1792 s->Led.Asserted.s.fWriting = s->Led.Actual.s.fWriting = 1;
1793# ifdef VBOX_INSTRUMENT_DMA_WRITES
1794 if (s->fDMA)
1795 STAM_PROFILE_ADV_START(&s->StatInstrVDWrites, vw);
1796# endif
1797 rc = pDevR3->pDrvMedia->pfnWrite(pDevR3->pDrvMedia, u64Sector * cbSector, pvBuf, cbToWrite);
1798# ifdef VBOX_INSTRUMENT_DMA_WRITES
1799 if (s->fDMA)
1800 STAM_PROFILE_ADV_STOP(&s->StatInstrVDWrites, vw);
1801# endif
1802 s->Led.Actual.s.fWriting = 0;
1803 STAM_PROFILE_ADV_STOP(&s->StatWrites, w);
1804 Log4(("ataR3WriteSectors: rc=%Rrc cSectors=%#x u64Sector=%llu\n%.*Rhxd\n",
1805 rc, cSectors, u64Sector, cbToWrite, pvBuf));
1806
1807 STAM_REL_COUNTER_ADD(&s->StatBytesWritten, cbToWrite);
1808
1809 if (RT_SUCCESS(rc))
1810 *pfRedo = false;
1811 else
1812 *pfRedo = ataR3IsRedoSetWarning(pDevIns, pCtl, rc);
1813
1814 ataR3LockEnter(pDevIns, pCtl);
1815 return rc;
1816}
1817
1818
1819/**
1820 * Begin Transfer: READ/WRITE SECTORS
1821 */
1822static void ataR3ReadWriteSectorsBT(PATACONTROLLER pCtl, PATADEVSTATE s)
1823{
1824 uint32_t const cbSector = RT_MAX(s->cbSector, 1);
1825 uint32_t cSectors;
1826
1827 cSectors = s->cbTotalTransfer / cbSector;
1828 if (cSectors > s->cSectorsPerIRQ)
1829 s->cbElementaryTransfer = s->cSectorsPerIRQ * cbSector;
1830 else
1831 s->cbElementaryTransfer = cSectors * cbSector;
1832 if (s->uTxDir == PDMMEDIATXDIR_TO_DEVICE)
1833 ataR3CmdOK(pCtl, s, 0);
1834}
1835
1836
1837/**
1838 * Sink/Source: READ SECTORS
1839 */
1840static bool ataR3ReadSectorsSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3)
1841{
1842 uint32_t const cbSector = RT_MAX(s->cbSector, 1);
1843 uint32_t cSectors;
1844 uint64_t iLBA;
1845 bool fRedo;
1846 int rc;
1847
1848 cSectors = s->cbElementaryTransfer / cbSector;
1849 Assert(cSectors);
1850 iLBA = s->iCurLBA;
1851 Log(("%s: %d sectors at LBA %d\n", __FUNCTION__, cSectors, iLBA));
1852 rc = ataR3ReadSectors(pDevIns, pCtl, s, pDevR3, iLBA, s->abIOBuffer, cSectors, &fRedo);
1853 if (RT_SUCCESS(rc))
1854 {
1855 /* When READ SECTORS etc. finishes, the address in the task
1856 * file register points at the last sector read, not at the next
1857 * sector that would be read. This ensures the registers always
1858 * contain a valid sector address.
1859 */
1860 if (s->cbElementaryTransfer == s->cbTotalTransfer)
1861 {
1862 s->iSourceSink = ATAFN_SS_NULL;
1863 ataR3SetSector(s, iLBA + cSectors - 1);
1864 }
1865 else
1866 ataR3SetSector(s, iLBA + cSectors);
1867 s->uATARegNSector -= cSectors;
1868 s->iCurLBA += cSectors;
1869 ataR3CmdOK(pCtl, s, ATA_STAT_SEEK);
1870 }
1871 else
1872 {
1873 if (fRedo)
1874 return fRedo;
1875 if (s->cErrors++ < MAX_LOG_REL_ERRORS)
1876 LogRel(("PIIX3 ATA: LUN#%d: disk read error (rc=%Rrc iSector=%#RX64 cSectors=%#RX32)\n",
1877 s->iLUN, rc, iLBA, cSectors));
1878
1879 /*
1880 * Check if we got interrupted. We don't need to set status variables
1881 * because the request was aborted.
1882 */
1883 if (rc != VERR_INTERRUPTED)
1884 ataR3CmdError(pCtl, s, ID_ERR);
1885 }
1886 return false;
1887}
1888
1889
1890/**
1891 * Sink/Source: WRITE SECTOR
1892 */
1893static bool ataR3WriteSectorsSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3)
1894{
1895 uint32_t const cbSector = RT_MAX(s->cbSector, 1);
1896 uint64_t iLBA;
1897 uint32_t cSectors;
1898 bool fRedo;
1899 int rc;
1900
1901 cSectors = s->cbElementaryTransfer / cbSector;
1902 Assert(cSectors);
1903 iLBA = s->iCurLBA;
1904 Log(("%s: %d sectors at LBA %d\n", __FUNCTION__, cSectors, iLBA));
1905 rc = ataR3WriteSectors(pDevIns, pCtl, s, pDevR3, iLBA, s->abIOBuffer, cSectors, &fRedo);
1906 if (RT_SUCCESS(rc))
1907 {
1908 ataR3SetSector(s, iLBA + cSectors);
1909 s->iCurLBA = iLBA + cSectors;
1910 if (!s->cbTotalTransfer)
1911 s->iSourceSink = ATAFN_SS_NULL;
1912 ataR3CmdOK(pCtl, s, ATA_STAT_SEEK);
1913 }
1914 else
1915 {
1916 if (fRedo)
1917 return fRedo;
1918 if (s->cErrors++ < MAX_LOG_REL_ERRORS)
1919 LogRel(("PIIX3 ATA: LUN#%d: disk write error (rc=%Rrc iSector=%#RX64 cSectors=%#RX32)\n",
1920 s->iLUN, rc, iLBA, cSectors));
1921
1922 /*
1923 * Check if we got interrupted. We don't need to set status variables
1924 * because the request was aborted.
1925 */
1926 if (rc != VERR_INTERRUPTED)
1927 ataR3CmdError(pCtl, s, ID_ERR);
1928 }
1929 return false;
1930}
1931
1932
1933static void atapiR3CmdOK(PATACONTROLLER pCtl, PATADEVSTATE s)
1934{
1935 s->uATARegError = 0;
1936 ataSetStatusValue(pCtl, s, ATA_STAT_READY);
1937 s->uATARegNSector = (s->uATARegNSector & ~7)
1938 | ((s->uTxDir != PDMMEDIATXDIR_TO_DEVICE) ? ATAPI_INT_REASON_IO : 0)
1939 | (!s->cbTotalTransfer ? ATAPI_INT_REASON_CD : 0);
1940 Log2(("%s: interrupt reason %#04x\n", __FUNCTION__, s->uATARegNSector));
1941
1942 memset(s->abATAPISense, '\0', sizeof(s->abATAPISense));
1943 s->abATAPISense[0] = 0x70 | (1 << 7);
1944 s->abATAPISense[7] = 10;
1945}
1946
1947
1948static void atapiR3CmdError(PATACONTROLLER pCtl, PATADEVSTATE s, const uint8_t *pabATAPISense, size_t cbATAPISense)
1949{
1950 Log(("%s: sense=%#x (%s) asc=%#x ascq=%#x (%s)\n", __FUNCTION__, pabATAPISense[2] & 0x0f, SCSISenseText(pabATAPISense[2] & 0x0f),
1951 pabATAPISense[12], pabATAPISense[13], SCSISenseExtText(pabATAPISense[12], pabATAPISense[13])));
1952 s->uATARegError = pabATAPISense[2] << 4;
1953 ataSetStatusValue(pCtl, s, ATA_STAT_READY | ATA_STAT_ERR);
1954 s->uATARegNSector = (s->uATARegNSector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
1955 Log2(("%s: interrupt reason %#04x\n", __FUNCTION__, s->uATARegNSector));
1956 memset(s->abATAPISense, '\0', sizeof(s->abATAPISense));
1957 memcpy(s->abATAPISense, pabATAPISense, RT_MIN(cbATAPISense, sizeof(s->abATAPISense)));
1958 s->cbTotalTransfer = 0;
1959 s->cbElementaryTransfer = 0;
1960 s->cbAtapiPassthroughTransfer = 0;
1961 s->iIOBufferCur = 0;
1962 s->iIOBufferEnd = 0;
1963 s->uTxDir = PDMMEDIATXDIR_NONE;
1964 s->iBeginTransfer = ATAFN_BT_NULL;
1965 s->iSourceSink = ATAFN_SS_NULL;
1966}
1967
1968
1969/** @todo deprecated function - doesn't provide enough info. Replace by direct
1970 * calls to atapiR3CmdError() with full data. */
1971static void atapiR3CmdErrorSimple(PATACONTROLLER pCtl, PATADEVSTATE s, uint8_t uATAPISenseKey, uint8_t uATAPIASC)
1972{
1973 uint8_t abATAPISense[ATAPI_SENSE_SIZE];
1974 memset(abATAPISense, '\0', sizeof(abATAPISense));
1975 abATAPISense[0] = 0x70 | (1 << 7);
1976 abATAPISense[2] = uATAPISenseKey & 0x0f;
1977 abATAPISense[7] = 10;
1978 abATAPISense[12] = uATAPIASC;
1979 atapiR3CmdError(pCtl, s, abATAPISense, sizeof(abATAPISense));
1980}
1981
1982
1983/**
1984 * Begin Transfer: ATAPI command
1985 */
1986static void atapiR3CmdBT(PATACONTROLLER pCtl, PATADEVSTATE s)
1987{
1988 s->fATAPITransfer = true;
1989 s->cbElementaryTransfer = s->cbTotalTransfer;
1990 s->cbAtapiPassthroughTransfer = s->cbTotalTransfer;
1991 s->cbPIOTransferLimit = s->uATARegLCyl | (s->uATARegHCyl << 8);
1992 if (s->uTxDir == PDMMEDIATXDIR_TO_DEVICE)
1993 atapiR3CmdOK(pCtl, s);
1994}
1995
1996
1997/**
1998 * Begin Transfer: ATAPI Passthrough command
1999 */
2000static void atapiR3PassthroughCmdBT(PATACONTROLLER pCtl, PATADEVSTATE s)
2001{
2002 atapiR3CmdBT(pCtl, s);
2003}
2004
2005
2006/**
2007 * Sink/Source: READ
2008 */
2009static bool atapiR3ReadSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3)
2010{
2011 int rc;
2012 uint64_t cbBlockRegion = 0;
2013 VDREGIONDATAFORM enmDataForm;
2014
2015 Assert(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE);
2016 uint32_t const iATAPILBA = s->iCurLBA;
2017 uint32_t const cbTransfer = RT_MIN(s->cbTotalTransfer, RT_MIN(s->cbIOBuffer, ATA_MAX_IO_BUFFER_SIZE));
2018 uint32_t const cbATAPISector = s->cbATAPISector;
2019 uint32_t const cSectors = cbTransfer / cbATAPISector;
2020 Assert(cSectors * cbATAPISector <= cbTransfer);
2021 Log(("%s: %d sectors at LBA %d\n", __FUNCTION__, cSectors, iATAPILBA));
2022 AssertLogRelReturn(cSectors * cbATAPISector <= sizeof(s->abIOBuffer), false);
2023
2024 ataR3LockLeave(pDevIns, pCtl);
2025
2026 rc = pDevR3->pDrvMedia->pfnQueryRegionPropertiesForLba(pDevR3->pDrvMedia, iATAPILBA, NULL, NULL,
2027 &cbBlockRegion, &enmDataForm);
2028 if (RT_SUCCESS(rc))
2029 {
2030 STAM_PROFILE_ADV_START(&s->StatReads, r);
2031 s->Led.Asserted.s.fReading = s->Led.Actual.s.fReading = 1;
2032
2033 /* If the region block size and requested sector matches we can just pass the request through. */
2034 if (cbBlockRegion == cbATAPISector)
2035 rc = pDevR3->pDrvMedia->pfnRead(pDevR3->pDrvMedia, (uint64_t)iATAPILBA * cbATAPISector,
2036 s->abIOBuffer, cbATAPISector * cSectors);
2037 else
2038 {
2039 uint32_t const iEndSector = iATAPILBA + cSectors;
2040 ASSERT_GUEST(iEndSector >= iATAPILBA);
2041 if (cbBlockRegion == 2048 && cbATAPISector == 2352)
2042 {
2043 /* Generate the sync bytes. */
2044 uint8_t *pbBuf = s->abIOBuffer;
2045
2046 for (uint32_t i = iATAPILBA; i < iEndSector; i++)
2047 {
2048 /* Sync bytes, see 4.2.3.8 CD Main Channel Block Formats */
2049 *pbBuf++ = 0x00;
2050 memset(pbBuf, 0xff, 10);
2051 pbBuf += 10;
2052 *pbBuf++ = 0x00;
2053 /* MSF */
2054 scsiLBA2MSF(pbBuf, i);
2055 pbBuf += 3;
2056 *pbBuf++ = 0x01; /* mode 1 data */
2057 /* data */
2058 rc = pDevR3->pDrvMedia->pfnRead(pDevR3->pDrvMedia, (uint64_t)i * 2048, pbBuf, 2048);
2059 if (RT_FAILURE(rc))
2060 break;
2061 pbBuf += 2048;
2062 /**
2063 * @todo maybe compute ECC and parity, layout is:
2064 * 2072 4 EDC
2065 * 2076 172 P parity symbols
2066 * 2248 104 Q parity symbols
2067 */
2068 memset(pbBuf, 0, 280);
2069 pbBuf += 280;
2070 }
2071 }
2072 else if (cbBlockRegion == 2352 && cbATAPISector == 2048)
2073 {
2074 /* Read only the user data portion. */
2075 uint8_t *pbBuf = s->abIOBuffer;
2076
2077 for (uint32_t i = iATAPILBA; i < iEndSector; i++)
2078 {
2079 uint8_t abTmp[2352];
2080 uint8_t cbSkip;
2081
2082 rc = pDevR3->pDrvMedia->pfnRead(pDevR3->pDrvMedia, (uint64_t)i * 2352, &abTmp[0], 2352);
2083 if (RT_FAILURE(rc))
2084 break;
2085
2086 /* Mode 2 has an additional subheader before user data; we need to
2087 * skip 16 bytes for Mode 1 (sync + header) and 20 bytes for Mode 2 +
2088 * (sync + header + subheader).
2089 */
2090 switch (enmDataForm) {
2091 case VDREGIONDATAFORM_MODE2_2352:
2092 case VDREGIONDATAFORM_XA_2352:
2093 cbSkip = 24;
2094 break;
2095 case VDREGIONDATAFORM_MODE1_2352:
2096 cbSkip = 16;
2097 break;
2098 default:
2099 AssertMsgFailed(("Unexpected region form (%#u), using default skip value\n", enmDataForm));
2100 cbSkip = 16;
2101 }
2102 memcpy(pbBuf, &abTmp[cbSkip], 2048);
2103 pbBuf += 2048;
2104 }
2105 }
2106 else
2107 ASSERT_GUEST_MSG_FAILED(("Unsupported: cbBlockRegion=%u cbATAPISector=%u\n", cbBlockRegion, cbATAPISector));
2108 }
2109 s->Led.Actual.s.fReading = 0;
2110 STAM_PROFILE_ADV_STOP(&s->StatReads, r);
2111 }
2112
2113 ataR3LockEnter(pDevIns, pCtl);
2114
2115 if (RT_SUCCESS(rc))
2116 {
2117 STAM_REL_COUNTER_ADD(&s->StatBytesRead, cbATAPISector * cSectors);
2118
2119 /* The initial buffer end value has been set up based on the total
2120 * transfer size. But the I/O buffer size limits what can actually be
2121 * done in one transfer, so set the actual value of the buffer end. */
2122 s->cbElementaryTransfer = cbTransfer;
2123 if (cbTransfer >= s->cbTotalTransfer)
2124 s->iSourceSink = ATAFN_SS_NULL;
2125 atapiR3CmdOK(pCtl, s);
2126 s->iCurLBA = iATAPILBA + cSectors;
2127 }
2128 else
2129 {
2130 if (s->cErrors++ < MAX_LOG_REL_ERRORS)
2131 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM read error, %d sectors at LBA %d\n", s->iLUN, cSectors, iATAPILBA));
2132
2133 /*
2134 * Check if we got interrupted. We don't need to set status variables
2135 * because the request was aborted.
2136 */
2137 if (rc != VERR_INTERRUPTED)
2138 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_MEDIUM_ERROR, SCSI_ASC_READ_ERROR);
2139 }
2140 return false;
2141}
2142
2143/**
2144 * Sets the given media track type.
2145 */
2146static uint32_t ataR3MediumTypeSet(PATADEVSTATE s, uint32_t MediaTrackType)
2147{
2148 return ASMAtomicXchgU32(&s->MediaTrackType, MediaTrackType);
2149}
2150
2151
2152/**
2153 * Sink/Source: Passthrough
2154 */
2155static bool atapiR3PassthroughSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3)
2156{
2157 int rc = VINF_SUCCESS;
2158 uint8_t abATAPISense[ATAPI_SENSE_SIZE];
2159 uint32_t cbTransfer;
2160 PSTAMPROFILEADV pProf = NULL;
2161
2162 cbTransfer = RT_MIN(s->cbAtapiPassthroughTransfer, RT_MIN(s->cbIOBuffer, ATA_MAX_IO_BUFFER_SIZE));
2163
2164 if (s->uTxDir == PDMMEDIATXDIR_TO_DEVICE)
2165 Log3(("ATAPI PT data write (%d): %.*Rhxs\n", cbTransfer, cbTransfer, s->abIOBuffer));
2166
2167 /* Simple heuristics: if there is at least one sector of data
2168 * to transfer, it's worth updating the LEDs. */
2169 if (cbTransfer >= 2048)
2170 {
2171 if (s->uTxDir != PDMMEDIATXDIR_TO_DEVICE)
2172 {
2173 s->Led.Asserted.s.fReading = s->Led.Actual.s.fReading = 1;
2174 pProf = &s->StatReads;
2175 }
2176 else
2177 {
2178 s->Led.Asserted.s.fWriting = s->Led.Actual.s.fWriting = 1;
2179 pProf = &s->StatWrites;
2180 }
2181 }
2182
2183 ataR3LockLeave(pDevIns, pCtl);
2184
2185# if defined(LOG_ENABLED)
2186 char szBuf[1024];
2187
2188 memset(szBuf, 0, sizeof(szBuf));
2189
2190 switch (s->abATAPICmd[0])
2191 {
2192 case SCSI_MODE_SELECT_10:
2193 {
2194 size_t cbBlkDescLength = scsiBE2H_U16(&s->abIOBuffer[6]);
2195
2196 SCSILogModePage(szBuf, sizeof(szBuf) - 1,
2197 s->abIOBuffer + 8 + cbBlkDescLength,
2198 cbTransfer - 8 - cbBlkDescLength);
2199 break;
2200 }
2201 case SCSI_SEND_CUE_SHEET:
2202 {
2203 SCSILogCueSheet(szBuf, sizeof(szBuf) - 1,
2204 s->abIOBuffer, cbTransfer);
2205 break;
2206 }
2207 default:
2208 break;
2209 }
2210
2211 Log2(("%s\n", szBuf));
2212# endif
2213
2214 if (pProf) { STAM_PROFILE_ADV_START(pProf, b); }
2215
2216 Assert(s->cbATAPISector);
2217 const uint32_t cbATAPISector = RT_MAX(s->cbATAPISector, 1); /* paranoia */
2218 const uint32_t cbIOBuffer = RT_MIN(s->cbIOBuffer, ATA_MAX_IO_BUFFER_SIZE); /* ditto */
2219
2220 if ( cbTransfer > SCSI_MAX_BUFFER_SIZE
2221 || s->cbElementaryTransfer > cbIOBuffer)
2222 {
2223 /* Linux accepts commands with up to 100KB of data, but expects
2224 * us to handle commands with up to 128KB of data. The usual
2225 * imbalance of powers. */
2226 uint8_t abATAPICmd[ATAPI_PACKET_SIZE];
2227 uint32_t iATAPILBA, cSectors, cReqSectors, cbCurrTX;
2228 uint8_t *pbBuf = s->abIOBuffer;
2229 uint32_t cSectorsMax; /**< Maximum amount of sectors to read without exceeding the I/O buffer. */
2230
2231 cSectorsMax = cbTransfer / cbATAPISector;
2232 AssertStmt(cSectorsMax * s->cbATAPISector <= cbIOBuffer, cSectorsMax = cbIOBuffer / cbATAPISector);
2233
2234 switch (s->abATAPICmd[0])
2235 {
2236 case SCSI_READ_10:
2237 case SCSI_WRITE_10:
2238 case SCSI_WRITE_AND_VERIFY_10:
2239 iATAPILBA = scsiBE2H_U32(s->abATAPICmd + 2);
2240 cSectors = scsiBE2H_U16(s->abATAPICmd + 7);
2241 break;
2242 case SCSI_READ_12:
2243 case SCSI_WRITE_12:
2244 iATAPILBA = scsiBE2H_U32(s->abATAPICmd + 2);
2245 cSectors = scsiBE2H_U32(s->abATAPICmd + 6);
2246 break;
2247 case SCSI_READ_CD:
2248 iATAPILBA = scsiBE2H_U32(s->abATAPICmd + 2);
2249 cSectors = scsiBE2H_U24(s->abATAPICmd + 6);
2250 break;
2251 case SCSI_READ_CD_MSF:
2252 iATAPILBA = scsiMSF2LBA(s->abATAPICmd + 3);
2253 cSectors = scsiMSF2LBA(s->abATAPICmd + 6) - iATAPILBA;
2254 break;
2255 default:
2256 AssertMsgFailed(("Don't know how to split command %#04x\n", s->abATAPICmd[0]));
2257 if (s->cErrors++ < MAX_LOG_REL_ERRORS)
2258 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM passthrough split error\n", s->iLUN));
2259 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE);
2260 ataR3LockEnter(pDevIns, pCtl);
2261 return false;
2262 }
2263 cSectorsMax = RT_MIN(cSectorsMax, cSectors);
2264 memcpy(abATAPICmd, s->abATAPICmd, ATAPI_PACKET_SIZE);
2265 cReqSectors = 0;
2266 for (uint32_t i = cSectorsMax; i > 0; i -= cReqSectors)
2267 {
2268 if (i * cbATAPISector > SCSI_MAX_BUFFER_SIZE)
2269 cReqSectors = SCSI_MAX_BUFFER_SIZE / cbATAPISector;
2270 else
2271 cReqSectors = i;
2272 cbCurrTX = cbATAPISector * cReqSectors;
2273 switch (s->abATAPICmd[0])
2274 {
2275 case SCSI_READ_10:
2276 case SCSI_WRITE_10:
2277 case SCSI_WRITE_AND_VERIFY_10:
2278 scsiH2BE_U32(abATAPICmd + 2, iATAPILBA);
2279 scsiH2BE_U16(abATAPICmd + 7, cReqSectors);
2280 break;
2281 case SCSI_READ_12:
2282 case SCSI_WRITE_12:
2283 scsiH2BE_U32(abATAPICmd + 2, iATAPILBA);
2284 scsiH2BE_U32(abATAPICmd + 6, cReqSectors);
2285 break;
2286 case SCSI_READ_CD:
2287 scsiH2BE_U32(abATAPICmd + 2, iATAPILBA);
2288 scsiH2BE_U24(abATAPICmd + 6, cReqSectors);
2289 break;
2290 case SCSI_READ_CD_MSF:
2291 scsiLBA2MSF(abATAPICmd + 3, iATAPILBA);
2292 scsiLBA2MSF(abATAPICmd + 6, iATAPILBA + cReqSectors);
2293 break;
2294 }
2295 AssertLogRelReturn((uintptr_t)(pbBuf - &s->abIOBuffer[0]) + cbCurrTX <= sizeof(s->abIOBuffer), false);
2296 rc = pDevR3->pDrvMedia->pfnSendCmd(pDevR3->pDrvMedia, abATAPICmd, ATAPI_PACKET_SIZE, (PDMMEDIATXDIR)s->uTxDir,
2297 pbBuf, &cbCurrTX, abATAPISense, sizeof(abATAPISense), 30000 /**< @todo timeout */);
2298 if (rc != VINF_SUCCESS)
2299 break;
2300 iATAPILBA += cReqSectors;
2301 pbBuf += cbATAPISector * cReqSectors;
2302 }
2303
2304 if (RT_SUCCESS(rc))
2305 {
2306 /* Adjust ATAPI command for the next call. */
2307 switch (s->abATAPICmd[0])
2308 {
2309 case SCSI_READ_10:
2310 case SCSI_WRITE_10:
2311 case SCSI_WRITE_AND_VERIFY_10:
2312 scsiH2BE_U32(s->abATAPICmd + 2, iATAPILBA);
2313 scsiH2BE_U16(s->abATAPICmd + 7, cSectors - cSectorsMax);
2314 break;
2315 case SCSI_READ_12:
2316 case SCSI_WRITE_12:
2317 scsiH2BE_U32(s->abATAPICmd + 2, iATAPILBA);
2318 scsiH2BE_U32(s->abATAPICmd + 6, cSectors - cSectorsMax);
2319 break;
2320 case SCSI_READ_CD:
2321 scsiH2BE_U32(s->abATAPICmd + 2, iATAPILBA);
2322 scsiH2BE_U24(s->abATAPICmd + 6, cSectors - cSectorsMax);
2323 break;
2324 case SCSI_READ_CD_MSF:
2325 scsiLBA2MSF(s->abATAPICmd + 3, iATAPILBA);
2326 scsiLBA2MSF(s->abATAPICmd + 6, iATAPILBA + cSectors - cSectorsMax);
2327 break;
2328 default:
2329 AssertMsgFailed(("Don't know how to split command %#04x\n", s->abATAPICmd[0]));
2330 if (s->cErrors++ < MAX_LOG_REL_ERRORS)
2331 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM passthrough split error\n", s->iLUN));
2332 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE);
2333 return false;
2334 }
2335 }
2336 }
2337 else
2338 {
2339 AssertLogRelReturn(cbTransfer <= sizeof(s->abIOBuffer), false);
2340 rc = pDevR3->pDrvMedia->pfnSendCmd(pDevR3->pDrvMedia, s->abATAPICmd, ATAPI_PACKET_SIZE, (PDMMEDIATXDIR)s->uTxDir,
2341 s->abIOBuffer, &cbTransfer, abATAPISense, sizeof(abATAPISense), 30000 /**< @todo timeout */);
2342 }
2343 if (pProf) { STAM_PROFILE_ADV_STOP(pProf, b); }
2344
2345 ataR3LockEnter(pDevIns, pCtl);
2346
2347 /* Update the LEDs and the read/write statistics. */
2348 if (cbTransfer >= 2048)
2349 {
2350 if (s->uTxDir != PDMMEDIATXDIR_TO_DEVICE)
2351 {
2352 s->Led.Actual.s.fReading = 0;
2353 STAM_REL_COUNTER_ADD(&s->StatBytesRead, cbTransfer);
2354 }
2355 else
2356 {
2357 s->Led.Actual.s.fWriting = 0;
2358 STAM_REL_COUNTER_ADD(&s->StatBytesWritten, cbTransfer);
2359 }
2360 }
2361
2362 if (RT_SUCCESS(rc))
2363 {
2364 /* Do post processing for certain commands. */
2365 switch (s->abATAPICmd[0])
2366 {
2367 case SCSI_SEND_CUE_SHEET:
2368 case SCSI_READ_TOC_PMA_ATIP:
2369 {
2370 if (!pDevR3->pTrackList)
2371 rc = ATAPIPassthroughTrackListCreateEmpty(&pDevR3->pTrackList);
2372
2373 if (RT_SUCCESS(rc))
2374 rc = ATAPIPassthroughTrackListUpdate(pDevR3->pTrackList, s->abATAPICmd, s->abIOBuffer, sizeof(s->abIOBuffer));
2375
2376 if ( RT_FAILURE(rc)
2377 && s->cErrors++ < MAX_LOG_REL_ERRORS)
2378 LogRel(("ATA: Error (%Rrc) while updating the tracklist during %s, burning the disc might fail\n",
2379 rc, s->abATAPICmd[0] == SCSI_SEND_CUE_SHEET ? "SEND CUE SHEET" : "READ TOC/PMA/ATIP"));
2380 break;
2381 }
2382 case SCSI_SYNCHRONIZE_CACHE:
2383 {
2384 if (pDevR3->pTrackList)
2385 ATAPIPassthroughTrackListClear(pDevR3->pTrackList);
2386 break;
2387 }
2388 }
2389
2390 if (s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE)
2391 {
2392 /*
2393 * Reply with the same amount of data as the real drive
2394 * but only if the command wasn't split.
2395 */
2396 if (s->cbAtapiPassthroughTransfer < cbIOBuffer)
2397 s->cbTotalTransfer = cbTransfer;
2398
2399 if ( s->abATAPICmd[0] == SCSI_INQUIRY
2400 && s->fOverwriteInquiry)
2401 {
2402 /* Make sure that the real drive cannot be identified.
2403 * Motivation: changing the VM configuration should be as
2404 * invisible as possible to the guest. */
2405 Log3(("ATAPI PT inquiry data before (%d): %.*Rhxs\n", cbTransfer, cbTransfer, s->abIOBuffer));
2406 scsiPadStr(&s->abIOBuffer[8], "VBOX", 8);
2407 scsiPadStr(&s->abIOBuffer[16], "CD-ROM", 16);
2408 scsiPadStr(&s->abIOBuffer[32], "1.0", 4);
2409 }
2410
2411 if (cbTransfer)
2412 Log3(("ATAPI PT data read (%d):\n%.*Rhxd\n", cbTransfer, cbTransfer, s->abIOBuffer));
2413 }
2414
2415 /* The initial buffer end value has been set up based on the total
2416 * transfer size. But the I/O buffer size limits what can actually be
2417 * done in one transfer, so set the actual value of the buffer end. */
2418 Assert(cbTransfer <= s->cbAtapiPassthroughTransfer);
2419 s->cbElementaryTransfer = cbTransfer;
2420 s->cbAtapiPassthroughTransfer -= cbTransfer;
2421 if (!s->cbAtapiPassthroughTransfer)
2422 {
2423 s->iSourceSink = ATAFN_SS_NULL;
2424 atapiR3CmdOK(pCtl, s);
2425 }
2426 }
2427 else
2428 {
2429 if (s->cErrors < MAX_LOG_REL_ERRORS)
2430 {
2431 uint8_t u8Cmd = s->abATAPICmd[0];
2432 do
2433 {
2434 /* don't log superfluous errors */
2435 if ( rc == VERR_DEV_IO_ERROR
2436 && ( u8Cmd == SCSI_TEST_UNIT_READY
2437 || u8Cmd == SCSI_READ_CAPACITY
2438 || u8Cmd == SCSI_READ_DVD_STRUCTURE
2439 || u8Cmd == SCSI_READ_TOC_PMA_ATIP))
2440 break;
2441 s->cErrors++;
2442 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM passthrough cmd=%#04x sense=%d ASC=%#02x ASCQ=%#02x %Rrc\n",
2443 s->iLUN, u8Cmd, abATAPISense[2] & 0x0f, abATAPISense[12], abATAPISense[13], rc));
2444 } while (0);
2445 }
2446 atapiR3CmdError(pCtl, s, abATAPISense, sizeof(abATAPISense));
2447 }
2448 return false;
2449}
2450
2451
2452/**
2453 * Begin Transfer: Read DVD structures
2454 */
2455static bool atapiR3ReadDVDStructureSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3)
2456{
2457 uint8_t *buf = s->abIOBuffer;
2458 int media = s->abATAPICmd[1];
2459 int format = s->abATAPICmd[7];
2460 RT_NOREF(pDevIns, pDevR3);
2461
2462 AssertCompile(sizeof(s->abIOBuffer) > UINT16_MAX /* want a RT_MIN() below, but clang takes offence at always false stuff */);
2463 uint16_t max_len = scsiBE2H_U16(&s->abATAPICmd[8]);
2464 memset(buf, 0, max_len);
2465
2466 switch (format) {
2467 case 0x00:
2468 case 0x01:
2469 case 0x02:
2470 case 0x03:
2471 case 0x04:
2472 case 0x05:
2473 case 0x06:
2474 case 0x07:
2475 case 0x08:
2476 case 0x09:
2477 case 0x0a:
2478 case 0x0b:
2479 case 0x0c:
2480 case 0x0d:
2481 case 0x0e:
2482 case 0x0f:
2483 case 0x10:
2484 case 0x11:
2485 case 0x30:
2486 case 0x31:
2487 case 0xff:
2488 if (media == 0)
2489 {
2490 int uASC = SCSI_ASC_NONE;
2491
2492 switch (format)
2493 {
2494 case 0x0: /* Physical format information */
2495 {
2496 int layer = s->abATAPICmd[6];
2497 uint64_t total_sectors;
2498
2499 if (layer != 0)
2500 {
2501 uASC = -SCSI_ASC_INV_FIELD_IN_CMD_PACKET;
2502 break;
2503 }
2504
2505 total_sectors = s->cTotalSectors;
2506 total_sectors >>= 2;
2507 if (total_sectors == 0)
2508 {
2509 uASC = -SCSI_ASC_MEDIUM_NOT_PRESENT;
2510 break;
2511 }
2512
2513 buf[4] = 1; /* DVD-ROM, part version 1 */
2514 buf[5] = 0xf; /* 120mm disc, minimum rate unspecified */
2515 buf[6] = 1; /* one layer, read-only (per MMC-2 spec) */
2516 buf[7] = 0; /* default densities */
2517
2518 /* FIXME: 0x30000 per spec? */
2519 scsiH2BE_U32(buf + 8, 0); /* start sector */
2520 scsiH2BE_U32(buf + 12, total_sectors - 1); /* end sector */
2521 scsiH2BE_U32(buf + 16, total_sectors - 1); /* l0 end sector */
2522
2523 /* Size of buffer, not including 2 byte size field */
2524 scsiH2BE_U32(&buf[0], 2048 + 2);
2525
2526 /* 2k data + 4 byte header */
2527 uASC = (2048 + 4);
2528 break;
2529 }
2530 case 0x01: /* DVD copyright information */
2531 buf[4] = 0; /* no copyright data */
2532 buf[5] = 0; /* no region restrictions */
2533
2534 /* Size of buffer, not including 2 byte size field */
2535 scsiH2BE_U16(buf, 4 + 2);
2536
2537 /* 4 byte header + 4 byte data */
2538 uASC = (4 + 4);
2539 break;
2540
2541 case 0x03: /* BCA information - invalid field for no BCA info */
2542 uASC = -SCSI_ASC_INV_FIELD_IN_CMD_PACKET;
2543 break;
2544
2545 case 0x04: /* DVD disc manufacturing information */
2546 /* Size of buffer, not including 2 byte size field */
2547 scsiH2BE_U16(buf, 2048 + 2);
2548
2549 /* 2k data + 4 byte header */
2550 uASC = (2048 + 4);
2551 break;
2552 case 0xff:
2553 /*
2554 * This lists all the command capabilities above. Add new ones
2555 * in order and update the length and buffer return values.
2556 */
2557
2558 buf[4] = 0x00; /* Physical format */
2559 buf[5] = 0x40; /* Not writable, is readable */
2560 scsiH2BE_U16((buf + 6), 2048 + 4);
2561
2562 buf[8] = 0x01; /* Copyright info */
2563 buf[9] = 0x40; /* Not writable, is readable */
2564 scsiH2BE_U16((buf + 10), 4 + 4);
2565
2566 buf[12] = 0x03; /* BCA info */
2567 buf[13] = 0x40; /* Not writable, is readable */
2568 scsiH2BE_U16((buf + 14), 188 + 4);
2569
2570 buf[16] = 0x04; /* Manufacturing info */
2571 buf[17] = 0x40; /* Not writable, is readable */
2572 scsiH2BE_U16((buf + 18), 2048 + 4);
2573
2574 /* Size of buffer, not including 2 byte size field */
2575 scsiH2BE_U16(buf, 16 + 2);
2576
2577 /* data written + 4 byte header */
2578 uASC = (16 + 4);
2579 break;
2580 default: /** @todo formats beyond DVD-ROM requires */
2581 uASC = -SCSI_ASC_INV_FIELD_IN_CMD_PACKET;
2582 }
2583
2584 if (uASC < 0)
2585 {
2586 s->iSourceSink = ATAFN_SS_NULL;
2587 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, -uASC);
2588 return false;
2589 }
2590 break;
2591 }
2592 /** @todo BD support, fall through for now */
2593 RT_FALL_THRU();
2594
2595 /* Generic disk structures */
2596 case 0x80: /** @todo AACS volume identifier */
2597 case 0x81: /** @todo AACS media serial number */
2598 case 0x82: /** @todo AACS media identifier */
2599 case 0x83: /** @todo AACS media key block */
2600 case 0x90: /** @todo List of recognized format layers */
2601 case 0xc0: /** @todo Write protection status */
2602 default:
2603 s->iSourceSink = ATAFN_SS_NULL;
2604 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
2605 return false;
2606 }
2607
2608 s->iSourceSink = ATAFN_SS_NULL;
2609 atapiR3CmdOK(pCtl, s);
2610 return false;
2611}
2612
2613
2614static bool atapiR3ReadSectors(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s,
2615 uint32_t iATAPILBA, uint32_t cSectors, uint32_t cbSector)
2616{
2617 Assert(cSectors > 0);
2618 s->iCurLBA = iATAPILBA;
2619 s->cbATAPISector = cbSector;
2620 ataR3StartTransfer(pDevIns, pCtl, s, cSectors * cbSector,
2621 PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ, true);
2622 return false;
2623}
2624
2625
2626/**
2627 * Sink/Source: ATAPI READ CAPACITY
2628 */
2629static bool atapiR3ReadCapacitySS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3)
2630{
2631 uint8_t *pbBuf = s->abIOBuffer;
2632 RT_NOREF(pDevIns, pDevR3);
2633
2634 Assert(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE);
2635 Assert(s->cbElementaryTransfer <= 8);
2636 scsiH2BE_U32(pbBuf, s->cTotalSectors - 1);
2637 scsiH2BE_U32(pbBuf + 4, 2048);
2638 s->iSourceSink = ATAFN_SS_NULL;
2639 atapiR3CmdOK(pCtl, s);
2640 return false;
2641}
2642
2643
2644/**
2645 * Sink/Source: ATAPI READ DISCK INFORMATION
2646 */
2647static bool atapiR3ReadDiscInformationSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3)
2648{
2649 uint8_t *pbBuf = s->abIOBuffer;
2650 RT_NOREF(pDevIns, pDevR3);
2651
2652 Assert(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE);
2653 Assert(s->cbElementaryTransfer <= 34);
2654 memset(pbBuf, '\0', 34);
2655 scsiH2BE_U16(pbBuf, 32);
2656 pbBuf[2] = (0 << 4) | (3 << 2) | (2 << 0); /* not erasable, complete session, complete disc */
2657 pbBuf[3] = 1; /* number of first track */
2658 pbBuf[4] = 1; /* number of sessions (LSB) */
2659 pbBuf[5] = 1; /* first track number in last session (LSB) */
2660 pbBuf[6] = (uint8_t)pDevR3->pDrvMedia->pfnGetRegionCount(pDevR3->pDrvMedia); /* last track number in last session (LSB) */
2661 pbBuf[7] = (0 << 7) | (0 << 6) | (1 << 5) | (0 << 2) | (0 << 0); /* disc id not valid, disc bar code not valid, unrestricted use, not dirty, not RW medium */
2662 pbBuf[8] = 0; /* disc type = CD-ROM */
2663 pbBuf[9] = 0; /* number of sessions (MSB) */
2664 pbBuf[10] = 0; /* number of sessions (MSB) */
2665 pbBuf[11] = 0; /* number of sessions (MSB) */
2666 scsiH2BE_U32(pbBuf + 16, 0xffffffff); /* last session lead-in start time is not available */
2667 scsiH2BE_U32(pbBuf + 20, 0xffffffff); /* last possible start time for lead-out is not available */
2668 s->iSourceSink = ATAFN_SS_NULL;
2669 atapiR3CmdOK(pCtl, s);
2670 return false;
2671}
2672
2673
2674/**
2675 * Sink/Source: ATAPI READ TRACK INFORMATION
2676 */
2677static bool atapiR3ReadTrackInformationSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3)
2678{
2679 uint8_t *pbBuf = s->abIOBuffer;
2680 uint32_t u32LogAddr = scsiBE2H_U32(&s->abATAPICmd[2]);
2681 uint8_t u8LogAddrType = s->abATAPICmd[1] & 0x03;
2682 RT_NOREF(pDevIns);
2683
2684 int rc;
2685 uint64_t u64LbaStart = 0;
2686 uint32_t uRegion = 0;
2687 uint64_t cBlocks = 0;
2688 uint64_t cbBlock = 0;
2689 uint8_t u8DataMode = 0xf; /* Unknown data mode. */
2690 uint8_t u8TrackMode = 0;
2691 VDREGIONDATAFORM enmDataForm = VDREGIONDATAFORM_INVALID;
2692
2693 Assert(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE);
2694 Assert(s->cbElementaryTransfer <= 36);
2695
2696 switch (u8LogAddrType)
2697 {
2698 case 0x00:
2699 rc = pDevR3->pDrvMedia->pfnQueryRegionPropertiesForLba(pDevR3->pDrvMedia, u32LogAddr, &uRegion,
2700 NULL, NULL, NULL);
2701 if (RT_SUCCESS(rc))
2702 rc = pDevR3->pDrvMedia->pfnQueryRegionProperties(pDevR3->pDrvMedia, uRegion, &u64LbaStart,
2703 &cBlocks, &cbBlock, &enmDataForm);
2704 break;
2705 case 0x01:
2706 {
2707 if (u32LogAddr >= 1)
2708 {
2709 uRegion = u32LogAddr - 1;
2710 rc = pDevR3->pDrvMedia->pfnQueryRegionProperties(pDevR3->pDrvMedia, uRegion, &u64LbaStart,
2711 &cBlocks, &cbBlock, &enmDataForm);
2712 }
2713 else
2714 rc = VERR_NOT_FOUND; /** @todo Return lead-in information. */
2715 break;
2716 }
2717 case 0x02:
2718 default:
2719 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
2720 return false;
2721 }
2722
2723 if (RT_FAILURE(rc))
2724 {
2725 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
2726 return false;
2727 }
2728
2729 switch (enmDataForm)
2730 {
2731 case VDREGIONDATAFORM_MODE1_2048:
2732 case VDREGIONDATAFORM_MODE1_2352:
2733 case VDREGIONDATAFORM_MODE1_0:
2734 u8DataMode = 1;
2735 break;
2736 case VDREGIONDATAFORM_XA_2336:
2737 case VDREGIONDATAFORM_XA_2352:
2738 case VDREGIONDATAFORM_XA_0:
2739 case VDREGIONDATAFORM_MODE2_2336:
2740 case VDREGIONDATAFORM_MODE2_2352:
2741 case VDREGIONDATAFORM_MODE2_0:
2742 u8DataMode = 2;
2743 break;
2744 default:
2745 u8DataMode = 0xf;
2746 }
2747
2748 if (enmDataForm == VDREGIONDATAFORM_CDDA)
2749 u8TrackMode = 0x0;
2750 else
2751 u8TrackMode = 0x4;
2752
2753 memset(pbBuf, '\0', 36);
2754 scsiH2BE_U16(pbBuf, 34);
2755 pbBuf[2] = uRegion + 1; /* track number (LSB) */
2756 pbBuf[3] = 1; /* session number (LSB) */
2757 pbBuf[5] = (0 << 5) | (0 << 4) | u8TrackMode; /* not damaged, primary copy, data track */
2758 pbBuf[6] = (0 << 7) | (0 << 6) | (0 << 5) | (0 << 6) | u8DataMode; /* not reserved track, not blank, not packet writing, not fixed packet */
2759 pbBuf[7] = (0 << 1) | (0 << 0); /* last recorded address not valid, next recordable address not valid */
2760 scsiH2BE_U32(pbBuf + 8, (uint32_t)u64LbaStart); /* track start address is 0 */
2761 scsiH2BE_U32(pbBuf + 24, (uint32_t)cBlocks); /* track size */
2762 pbBuf[32] = 0; /* track number (MSB) */
2763 pbBuf[33] = 0; /* session number (MSB) */
2764 s->iSourceSink = ATAFN_SS_NULL;
2765 atapiR3CmdOK(pCtl, s);
2766 return false;
2767}
2768
2769static DECLCALLBACK(uint32_t) atapiR3GetConfigurationFillFeatureListProfiles(PATADEVSTATE s, uint8_t *pbBuf, size_t cbBuf)
2770{
2771 RT_NOREF(s);
2772 if (cbBuf < 3*4)
2773 return 0;
2774
2775 scsiH2BE_U16(pbBuf, 0x0); /* feature 0: list of profiles supported */
2776 pbBuf[2] = (0 << 2) | (1 << 1) | (1 << 0); /* version 0, persistent, current */
2777 pbBuf[3] = 8; /* additional bytes for profiles */
2778 /* The MMC-3 spec says that DVD-ROM read capability should be reported
2779 * before CD-ROM read capability. */
2780 scsiH2BE_U16(pbBuf + 4, 0x10); /* profile: read-only DVD */
2781 pbBuf[6] = (0 << 0); /* NOT current profile */
2782 scsiH2BE_U16(pbBuf + 8, 0x08); /* profile: read only CD */
2783 pbBuf[10] = (1 << 0); /* current profile */
2784
2785 return 3*4; /* Header + 2 profiles entries */
2786}
2787
2788static DECLCALLBACK(uint32_t) atapiR3GetConfigurationFillFeatureCore(PATADEVSTATE s, uint8_t *pbBuf, size_t cbBuf)
2789{
2790 RT_NOREF(s);
2791 if (cbBuf < 12)
2792 return 0;
2793
2794 scsiH2BE_U16(pbBuf, 0x1); /* feature 0001h: Core Feature */
2795 pbBuf[2] = (0x2 << 2) | RT_BIT(1) | RT_BIT(0); /* Version | Persistent | Current */
2796 pbBuf[3] = 8; /* Additional length */
2797 scsiH2BE_U16(pbBuf + 4, 0x00000002); /* Physical interface ATAPI. */
2798 pbBuf[8] = RT_BIT(0); /* DBE */
2799 /* Rest is reserved. */
2800
2801 return 12;
2802}
2803
2804static DECLCALLBACK(uint32_t) atapiR3GetConfigurationFillFeatureMorphing(PATADEVSTATE s, uint8_t *pbBuf, size_t cbBuf)
2805{
2806 RT_NOREF(s);
2807 if (cbBuf < 8)
2808 return 0;
2809
2810 scsiH2BE_U16(pbBuf, 0x2); /* feature 0002h: Morphing Feature */
2811 pbBuf[2] = (0x1 << 2) | RT_BIT(1) | RT_BIT(0); /* Version | Persistent | Current */
2812 pbBuf[3] = 4; /* Additional length */
2813 pbBuf[4] = RT_BIT(1) | 0x0; /* OCEvent | !ASYNC */
2814 /* Rest is reserved. */
2815
2816 return 8;
2817}
2818
2819static DECLCALLBACK(uint32_t) atapiR3GetConfigurationFillFeatureRemovableMedium(PATADEVSTATE s, uint8_t *pbBuf, size_t cbBuf)
2820{
2821 RT_NOREF(s);
2822 if (cbBuf < 8)
2823 return 0;
2824
2825 scsiH2BE_U16(pbBuf, 0x3); /* feature 0003h: Removable Medium Feature */
2826 pbBuf[2] = (0x2 << 2) | RT_BIT(1) | RT_BIT(0); /* Version | Persistent | Current */
2827 pbBuf[3] = 4; /* Additional length */
2828 /* Tray type loading | Load | Eject | !Pvnt Jmpr | !DBML | Lock */
2829 pbBuf[4] = (0x2 << 5) | RT_BIT(4) | RT_BIT(3) | (0x0 << 2) | (0x0 << 1) | RT_BIT(0);
2830 /* Rest is reserved. */
2831
2832 return 8;
2833}
2834
2835static DECLCALLBACK(uint32_t) atapiR3GetConfigurationFillFeatureRandomReadable (PATADEVSTATE s, uint8_t *pbBuf, size_t cbBuf)
2836{
2837 RT_NOREF(s);
2838 if (cbBuf < 12)
2839 return 0;
2840
2841 scsiH2BE_U16(pbBuf, 0x10); /* feature 0010h: Random Readable Feature */
2842 pbBuf[2] = (0x0 << 2) | RT_BIT(1) | RT_BIT(0); /* Version | Persistent | Current */
2843 pbBuf[3] = 8; /* Additional length */
2844 scsiH2BE_U32(pbBuf + 4, 2048); /* Logical block size. */
2845 scsiH2BE_U16(pbBuf + 8, 0x10); /* Blocking (0x10 for DVD, CD is not defined). */
2846 pbBuf[10] = 0; /* PP not present */
2847 /* Rest is reserved. */
2848
2849 return 12;
2850}
2851
2852static DECLCALLBACK(uint32_t) atapiR3GetConfigurationFillFeatureCDRead(PATADEVSTATE s, uint8_t *pbBuf, size_t cbBuf)
2853{
2854 RT_NOREF(s);
2855 if (cbBuf < 8)
2856 return 0;
2857
2858 scsiH2BE_U16(pbBuf, 0x1e); /* feature 001Eh: CD Read Feature */
2859 pbBuf[2] = (0x2 << 2) | RT_BIT(1) | RT_BIT(0); /* Version | Persistent | Current */
2860 pbBuf[3] = 0; /* Additional length */
2861 pbBuf[4] = (0x0 << 7) | (0x0 << 1) | 0x0; /* !DAP | !C2-Flags | !CD-Text. */
2862 /* Rest is reserved. */
2863
2864 return 8;
2865}
2866
2867static DECLCALLBACK(uint32_t) atapiR3GetConfigurationFillFeaturePowerManagement(PATADEVSTATE s, uint8_t *pbBuf, size_t cbBuf)
2868{
2869 RT_NOREF(s);
2870 if (cbBuf < 4)
2871 return 0;
2872
2873 scsiH2BE_U16(pbBuf, 0x100); /* feature 0100h: Power Management Feature */
2874 pbBuf[2] = (0x0 << 2) | RT_BIT(1) | RT_BIT(0); /* Version | Persistent | Current */
2875 pbBuf[3] = 0; /* Additional length */
2876
2877 return 4;
2878}
2879
2880static DECLCALLBACK(uint32_t) atapiR3GetConfigurationFillFeatureTimeout(PATADEVSTATE s, uint8_t *pbBuf, size_t cbBuf)
2881{
2882 RT_NOREF(s);
2883 if (cbBuf < 8)
2884 return 0;
2885
2886 scsiH2BE_U16(pbBuf, 0x105); /* feature 0105h: Timeout Feature */
2887 pbBuf[2] = (0x0 << 2) | RT_BIT(1) | RT_BIT(0); /* Version | Persistent | Current */
2888 pbBuf[3] = 4; /* Additional length */
2889 pbBuf[4] = 0x0; /* !Group3 */
2890
2891 return 8;
2892}
2893
2894/**
2895 * Callback to fill in the correct data for a feature.
2896 *
2897 * @returns Number of bytes written into the buffer.
2898 * @param s The ATA device state.
2899 * @param pbBuf The buffer to fill the data with.
2900 * @param cbBuf Size of the buffer.
2901 */
2902typedef DECLCALLBACKTYPE(uint32_t, FNATAPIR3FEATUREFILL,(PATADEVSTATE s, uint8_t *pbBuf, size_t cbBuf));
2903/** Pointer to a feature fill callback. */
2904typedef FNATAPIR3FEATUREFILL *PFNATAPIR3FEATUREFILL;
2905
2906/**
2907 * ATAPI feature descriptor.
2908 */
2909typedef struct ATAPIR3FEATDESC
2910{
2911 /** The feature number. */
2912 uint16_t u16Feat;
2913 /** The callback to fill in the correct data. */
2914 PFNATAPIR3FEATUREFILL pfnFeatureFill;
2915} ATAPIR3FEATDESC;
2916
2917/**
2918 * Array of known ATAPI feature descriptors.
2919 */
2920static const ATAPIR3FEATDESC s_aAtapiR3Features[] =
2921{
2922 { 0x0000, atapiR3GetConfigurationFillFeatureListProfiles},
2923 { 0x0001, atapiR3GetConfigurationFillFeatureCore},
2924 { 0x0002, atapiR3GetConfigurationFillFeatureMorphing},
2925 { 0x0003, atapiR3GetConfigurationFillFeatureRemovableMedium},
2926 { 0x0010, atapiR3GetConfigurationFillFeatureRandomReadable},
2927 { 0x001e, atapiR3GetConfigurationFillFeatureCDRead},
2928 { 0x0100, atapiR3GetConfigurationFillFeaturePowerManagement},
2929 { 0x0105, atapiR3GetConfigurationFillFeatureTimeout}
2930};
2931
2932/**
2933 * Sink/Source: ATAPI GET CONFIGURATION
2934 */
2935static bool atapiR3GetConfigurationSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3)
2936{
2937 uint32_t const cbIOBuffer = RT_MIN(s->cbIOBuffer, ATA_MAX_IO_BUFFER_SIZE);
2938 uint8_t *pbBuf = s->abIOBuffer;
2939 uint32_t cbBuf = cbIOBuffer;
2940 uint32_t cbCopied = 0;
2941 uint16_t u16Sfn = scsiBE2H_U16(&s->abATAPICmd[2]);
2942 uint8_t u8Rt = s->abATAPICmd[1] & 0x03;
2943 RT_NOREF(pDevIns, pDevR3);
2944
2945 Assert(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE);
2946 Assert(s->cbElementaryTransfer <= 80);
2947 /* Accept valid request types only. */
2948 if (u8Rt == 3)
2949 {
2950 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
2951 return false;
2952 }
2953 memset(pbBuf, '\0', cbBuf);
2954 /** @todo implement switching between CD-ROM and DVD-ROM profile (the only
2955 * way to differentiate them right now is based on the image size). */
2956 if (s->cTotalSectors)
2957 scsiH2BE_U16(pbBuf + 6, 0x08); /* current profile: read-only CD */
2958 else
2959 scsiH2BE_U16(pbBuf + 6, 0x00); /* current profile: none -> no media */
2960 cbBuf -= 8;
2961 pbBuf += 8;
2962
2963 if (u8Rt == 0x2)
2964 {
2965 for (uint32_t i = 0; i < RT_ELEMENTS(s_aAtapiR3Features); i++)
2966 {
2967 if (s_aAtapiR3Features[i].u16Feat == u16Sfn)
2968 {
2969 cbCopied = s_aAtapiR3Features[i].pfnFeatureFill(s, pbBuf, cbBuf);
2970 cbBuf -= cbCopied;
2971 pbBuf += cbCopied;
2972 break;
2973 }
2974 }
2975 }
2976 else
2977 {
2978 for (uint32_t i = 0; i < RT_ELEMENTS(s_aAtapiR3Features); i++)
2979 {
2980 if (s_aAtapiR3Features[i].u16Feat > u16Sfn)
2981 {
2982 cbCopied = s_aAtapiR3Features[i].pfnFeatureFill(s, pbBuf, cbBuf);
2983 cbBuf -= cbCopied;
2984 pbBuf += cbCopied;
2985 }
2986 }
2987 }
2988
2989 /* Set data length now - the field is not included in the final length. */
2990 scsiH2BE_U32(s->abIOBuffer, cbIOBuffer - cbBuf - 4);
2991
2992 /* Other profiles we might want to add in the future: 0x40 (BD-ROM) and 0x50 (HDDVD-ROM) */
2993 s->iSourceSink = ATAFN_SS_NULL;
2994 atapiR3CmdOK(pCtl, s);
2995 return false;
2996}
2997
2998
2999/**
3000 * Sink/Source: ATAPI GET EVENT STATUS NOTIFICATION
3001 */
3002static bool atapiR3GetEventStatusNotificationSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3)
3003{
3004 uint8_t *pbBuf = s->abIOBuffer;
3005 RT_NOREF(pDevIns, pDevR3);
3006
3007 Assert(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE);
3008 Assert(s->cbElementaryTransfer <= 8);
3009
3010 if (!(s->abATAPICmd[1] & 1))
3011 {
3012 /* no asynchronous operation supported */
3013 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
3014 return false;
3015 }
3016
3017 uint32_t OldStatus, NewStatus;
3018 do
3019 {
3020 OldStatus = ASMAtomicReadU32(&s->MediaEventStatus);
3021 NewStatus = ATA_EVENT_STATUS_UNCHANGED;
3022 switch (OldStatus)
3023 {
3024 case ATA_EVENT_STATUS_MEDIA_NEW:
3025 /* mount */
3026 scsiH2BE_U16(pbBuf + 0, 6);
3027 pbBuf[2] = 0x04; /* media */
3028 pbBuf[3] = 0x5e; /* supported = busy|media|external|power|operational */
3029 pbBuf[4] = 0x02; /* new medium */
3030 pbBuf[5] = 0x02; /* medium present / door closed */
3031 pbBuf[6] = 0x00;
3032 pbBuf[7] = 0x00;
3033 break;
3034
3035 case ATA_EVENT_STATUS_MEDIA_CHANGED:
3036 case ATA_EVENT_STATUS_MEDIA_REMOVED:
3037 /* umount */
3038 scsiH2BE_U16(pbBuf + 0, 6);
3039 pbBuf[2] = 0x04; /* media */
3040 pbBuf[3] = 0x5e; /* supported = busy|media|external|power|operational */
3041 pbBuf[4] = OldStatus == ATA_EVENT_STATUS_MEDIA_CHANGED ? 0x04 /* media changed */ : 0x03; /* media removed */
3042 pbBuf[5] = 0x00; /* medium absent / door closed */
3043 pbBuf[6] = 0x00;
3044 pbBuf[7] = 0x00;
3045 if (OldStatus == ATA_EVENT_STATUS_MEDIA_CHANGED)
3046 NewStatus = ATA_EVENT_STATUS_MEDIA_NEW;
3047 break;
3048
3049 case ATA_EVENT_STATUS_MEDIA_EJECT_REQUESTED: /* currently unused */
3050 scsiH2BE_U16(pbBuf + 0, 6);
3051 pbBuf[2] = 0x04; /* media */
3052 pbBuf[3] = 0x5e; /* supported = busy|media|external|power|operational */
3053 pbBuf[4] = 0x01; /* eject requested (eject button pressed) */
3054 pbBuf[5] = 0x02; /* medium present / door closed */
3055 pbBuf[6] = 0x00;
3056 pbBuf[7] = 0x00;
3057 break;
3058
3059 case ATA_EVENT_STATUS_UNCHANGED:
3060 default:
3061 scsiH2BE_U16(pbBuf + 0, 6);
3062 pbBuf[2] = 0x01; /* operational change request / notification */
3063 pbBuf[3] = 0x5e; /* supported = busy|media|external|power|operational */
3064 pbBuf[4] = 0x00;
3065 pbBuf[5] = 0x00;
3066 pbBuf[6] = 0x00;
3067 pbBuf[7] = 0x00;
3068 break;
3069 }
3070 } while (!ASMAtomicCmpXchgU32(&s->MediaEventStatus, NewStatus, OldStatus));
3071
3072 s->iSourceSink = ATAFN_SS_NULL;
3073 atapiR3CmdOK(pCtl, s);
3074 return false;
3075}
3076
3077
3078/**
3079 * Sink/Source: ATAPI INQUIRY
3080 */
3081static bool atapiR3InquirySS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3)
3082{
3083 uint8_t *pbBuf = s->abIOBuffer;
3084 RT_NOREF(pDevIns, pDevR3);
3085
3086 Assert(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE);
3087 Assert(s->cbElementaryTransfer <= 36);
3088 pbBuf[0] = 0x05; /* CD-ROM */
3089 pbBuf[1] = 0x80; /* removable */
3090# if 1/*ndef VBOX*/ /** @todo implement MESN + AENC. (async notification on removal and stuff.) */
3091 pbBuf[2] = 0x00; /* ISO */
3092 pbBuf[3] = 0x21; /* ATAPI-2 (XXX: put ATAPI-4 ?) */
3093# else
3094 pbBuf[2] = 0x00; /* ISO */
3095 pbBuf[3] = 0x91; /* format 1, MESN=1, AENC=9 ??? */
3096# endif
3097 pbBuf[4] = 31; /* additional length */
3098 pbBuf[5] = 0; /* reserved */
3099 pbBuf[6] = 0; /* reserved */
3100 pbBuf[7] = 0; /* reserved */
3101 scsiPadStr(pbBuf + 8, s->szInquiryVendorId, 8);
3102 scsiPadStr(pbBuf + 16, s->szInquiryProductId, 16);
3103 scsiPadStr(pbBuf + 32, s->szInquiryRevision, 4);
3104 s->iSourceSink = ATAFN_SS_NULL;
3105 atapiR3CmdOK(pCtl, s);
3106 return false;
3107}
3108
3109
3110/**
3111 * Sink/Source: ATAPI MODE SENSE ERROR RECOVERY
3112 */
3113static bool atapiR3ModeSenseErrorRecoverySS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3)
3114{
3115 uint8_t *pbBuf = s->abIOBuffer;
3116 RT_NOREF(pDevIns, pDevR3);
3117
3118 Assert(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE);
3119 Assert(s->cbElementaryTransfer <= 16);
3120 scsiH2BE_U16(&pbBuf[0], 16 + 6);
3121 pbBuf[2] = (uint8_t)s->MediaTrackType;
3122 pbBuf[3] = 0;
3123 pbBuf[4] = 0;
3124 pbBuf[5] = 0;
3125 pbBuf[6] = 0;
3126 pbBuf[7] = 0;
3127
3128 pbBuf[8] = 0x01;
3129 pbBuf[9] = 0x06;
3130 pbBuf[10] = 0x00; /* Maximum error recovery */
3131 pbBuf[11] = 0x05; /* 5 retries */
3132 pbBuf[12] = 0x00;
3133 pbBuf[13] = 0x00;
3134 pbBuf[14] = 0x00;
3135 pbBuf[15] = 0x00;
3136 s->iSourceSink = ATAFN_SS_NULL;
3137 atapiR3CmdOK(pCtl, s);
3138 return false;
3139}
3140
3141
3142/**
3143 * Sink/Source: ATAPI MODE SENSE CD STATUS
3144 */
3145static bool atapiR3ModeSenseCDStatusSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3)
3146{
3147 uint8_t *pbBuf = s->abIOBuffer;
3148 RT_NOREF(pDevIns);
3149
3150 /* 28 bytes of total returned data corresponds to ATAPI 2.6. Note that at least some versions
3151 * of NEC_IDE.SYS DOS driver (possibly other Oak Technology OTI-011 drivers) do not correctly
3152 * handle cases where more than 28 bytes are returned due to bugs. See @bugref{5869}.
3153 */
3154 Assert(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE);
3155 Assert(s->cbElementaryTransfer <= 28);
3156 scsiH2BE_U16(&pbBuf[0], 26);
3157 pbBuf[2] = (uint8_t)s->MediaTrackType;
3158 pbBuf[3] = 0;
3159 pbBuf[4] = 0;
3160 pbBuf[5] = 0;
3161 pbBuf[6] = 0;
3162 pbBuf[7] = 0;
3163
3164 pbBuf[8] = 0x2a;
3165 pbBuf[9] = 18; /* page length */
3166 pbBuf[10] = 0x08; /* DVD-ROM read support */
3167 pbBuf[11] = 0x00; /* no write support */
3168 /* The following claims we support audio play. This is obviously false,
3169 * but the Linux generic CDROM support makes many features depend on this
3170 * capability. If it's not set, this causes many things to be disabled. */
3171 pbBuf[12] = 0x71; /* multisession support, mode 2 form 1/2 support, audio play */
3172 pbBuf[13] = 0x00; /* no subchannel reads supported */
3173 pbBuf[14] = (1 << 0) | (1 << 3) | (1 << 5); /* lock supported, eject supported, tray type loading mechanism */
3174 if (pDevR3->pDrvMount->pfnIsLocked(pDevR3->pDrvMount))
3175 pbBuf[14] |= 1 << 1; /* report lock state */
3176 pbBuf[15] = 0; /* no subchannel reads supported, no separate audio volume control, no changer etc. */
3177 scsiH2BE_U16(&pbBuf[16], 5632); /* (obsolete) claim 32x speed support */
3178 scsiH2BE_U16(&pbBuf[18], 2); /* number of audio volume levels */
3179 scsiH2BE_U16(&pbBuf[20], RT_MIN(s->cbIOBuffer, ATA_MAX_IO_BUFFER_SIZE) / _1K); /* buffer size supported in Kbyte */
3180 scsiH2BE_U16(&pbBuf[22], 5632); /* (obsolete) current read speed 32x */
3181 pbBuf[24] = 0; /* reserved */
3182 pbBuf[25] = 0; /* reserved for digital audio (see idx 15) */
3183 pbBuf[26] = 0; /* reserved */
3184 pbBuf[27] = 0; /* reserved */
3185 s->iSourceSink = ATAFN_SS_NULL;
3186 atapiR3CmdOK(pCtl, s);
3187 return false;
3188}
3189
3190
3191/**
3192 * Sink/Source: ATAPI REQUEST SENSE
3193 */
3194static bool atapiR3RequestSenseSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3)
3195{
3196 uint8_t *pbBuf = s->abIOBuffer;
3197 RT_NOREF(pDevIns, pDevR3);
3198
3199 Assert(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE);
3200 memset(pbBuf, '\0', RT_MIN(s->cbElementaryTransfer, sizeof(s->abIOBuffer)));
3201 AssertCompile(sizeof(s->abIOBuffer) >= sizeof(s->abATAPISense));
3202 memcpy(pbBuf, s->abATAPISense, RT_MIN(s->cbElementaryTransfer, sizeof(s->abATAPISense)));
3203 s->iSourceSink = ATAFN_SS_NULL;
3204 atapiR3CmdOK(pCtl, s);
3205 return false;
3206}
3207
3208
3209/**
3210 * Sink/Source: ATAPI MECHANISM STATUS
3211 */
3212static bool atapiR3MechanismStatusSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3)
3213{
3214 uint8_t *pbBuf = s->abIOBuffer;
3215 RT_NOREF(pDevIns, pDevR3);
3216
3217 Assert(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE);
3218 Assert(s->cbElementaryTransfer <= 8);
3219 scsiH2BE_U16(pbBuf, 0);
3220 /* no current LBA */
3221 pbBuf[2] = 0;
3222 pbBuf[3] = 0;
3223 pbBuf[4] = 0;
3224 pbBuf[5] = 1;
3225 scsiH2BE_U16(pbBuf + 6, 0);
3226 s->iSourceSink = ATAFN_SS_NULL;
3227 atapiR3CmdOK(pCtl, s);
3228 return false;
3229}
3230
3231
3232/**
3233 * Sink/Source: ATAPI READ TOC NORMAL
3234 */
3235static bool atapiR3ReadTOCNormalSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3)
3236{
3237 uint8_t *pbBuf = s->abIOBuffer;
3238 uint8_t *q;
3239 uint8_t iStartTrack;
3240 bool fMSF;
3241 uint32_t cbSize;
3242 RT_NOREF(pDevIns);
3243
3244 /* Track fields are 8-bit and 1-based, so cut the track count at 255,
3245 avoiding any potential buffer overflow issues below. */
3246 uint32_t cTracks = pDevR3->pDrvMedia->pfnGetRegionCount(pDevR3->pDrvMedia);
3247 AssertStmt(cTracks <= UINT8_MAX, cTracks = UINT8_MAX);
3248 AssertCompile(sizeof(s->abIOBuffer) >= 2 + 256 + 8);
3249
3250 Assert(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE);
3251 fMSF = (s->abATAPICmd[1] >> 1) & 1;
3252 iStartTrack = s->abATAPICmd[6];
3253 if (iStartTrack == 0)
3254 iStartTrack = 1;
3255
3256 if (iStartTrack > cTracks && iStartTrack != 0xaa)
3257 {
3258 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
3259 return false;
3260 }
3261 q = pbBuf + 2;
3262 *q++ = iStartTrack; /* first track number */
3263 *q++ = cTracks; /* last track number */
3264 for (uint32_t iTrack = iStartTrack; iTrack <= cTracks; iTrack++)
3265 {
3266 uint64_t uLbaStart = 0;
3267 VDREGIONDATAFORM enmDataForm = VDREGIONDATAFORM_MODE1_2048;
3268
3269 int rc = pDevR3->pDrvMedia->pfnQueryRegionProperties(pDevR3->pDrvMedia, iTrack - 1, &uLbaStart,
3270 NULL, NULL, &enmDataForm);
3271 AssertRC(rc);
3272
3273 *q++ = 0; /* reserved */
3274
3275 if (enmDataForm == VDREGIONDATAFORM_CDDA)
3276 *q++ = 0x10; /* ADR, control */
3277 else
3278 *q++ = 0x14; /* ADR, control */
3279
3280 *q++ = (uint8_t)iTrack; /* track number */
3281 *q++ = 0; /* reserved */
3282 if (fMSF)
3283 {
3284 *q++ = 0; /* reserved */
3285 scsiLBA2MSF(q, (uint32_t)uLbaStart);
3286 q += 3;
3287 }
3288 else
3289 {
3290 /* sector 0 */
3291 scsiH2BE_U32(q, (uint32_t)uLbaStart);
3292 q += 4;
3293 }
3294 }
3295 /* lead out track */
3296 *q++ = 0; /* reserved */
3297 *q++ = 0x14; /* ADR, control */
3298 *q++ = 0xaa; /* track number */
3299 *q++ = 0; /* reserved */
3300
3301 /* Query start and length of last track to get the start of the lead out track. */
3302 uint64_t uLbaStart = 0;
3303 uint64_t cBlocks = 0;
3304
3305 int rc = pDevR3->pDrvMedia->pfnQueryRegionProperties(pDevR3->pDrvMedia, cTracks - 1, &uLbaStart,
3306 &cBlocks, NULL, NULL);
3307 AssertRC(rc);
3308
3309 uLbaStart += cBlocks;
3310 if (fMSF)
3311 {
3312 *q++ = 0; /* reserved */
3313 scsiLBA2MSF(q, (uint32_t)uLbaStart);
3314 q += 3;
3315 }
3316 else
3317 {
3318 scsiH2BE_U32(q, (uint32_t)uLbaStart);
3319 q += 4;
3320 }
3321 cbSize = q - pbBuf;
3322 scsiH2BE_U16(pbBuf, cbSize - 2);
3323 if (cbSize < s->cbTotalTransfer)
3324 s->cbTotalTransfer = cbSize;
3325 s->iSourceSink = ATAFN_SS_NULL;
3326 atapiR3CmdOK(pCtl, s);
3327 return false;
3328}
3329
3330
3331/**
3332 * Sink/Source: ATAPI READ TOC MULTI
3333 */
3334static bool atapiR3ReadTOCMultiSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3)
3335{
3336 uint8_t *pbBuf = s->abIOBuffer;
3337 bool fMSF;
3338 RT_NOREF(pDevIns);
3339
3340 Assert(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE);
3341 Assert(s->cbElementaryTransfer <= 12);
3342 fMSF = (s->abATAPICmd[1] >> 1) & 1;
3343 /* multi session: only a single session defined */
3344 /** @todo double-check this stuff against what a real drive says for a CD-ROM (not a CD-R)
3345 * with only a single data session. Maybe solve the problem with "cdrdao read-toc" not being
3346 * able to figure out whether numbers are in BCD or hex. */
3347 memset(pbBuf, 0, 12);
3348 pbBuf[1] = 0x0a;
3349 pbBuf[2] = 0x01;
3350 pbBuf[3] = 0x01;
3351
3352 VDREGIONDATAFORM enmDataForm = VDREGIONDATAFORM_MODE1_2048;
3353 int rc = pDevR3->pDrvMedia->pfnQueryRegionProperties(pDevR3->pDrvMedia, 0, NULL, NULL, NULL, &enmDataForm);
3354 AssertRC(rc);
3355
3356 if (enmDataForm == VDREGIONDATAFORM_CDDA)
3357 pbBuf[5] = 0x10; /* ADR, control */
3358 else
3359 pbBuf[5] = 0x14; /* ADR, control */
3360
3361 pbBuf[6] = 1; /* first track in last complete session */
3362 if (fMSF)
3363 {
3364 pbBuf[8] = 0; /* reserved */
3365 scsiLBA2MSF(&pbBuf[9], 0);
3366 }
3367 else
3368 {
3369 /* sector 0 */
3370 scsiH2BE_U32(pbBuf + 8, 0);
3371 }
3372 s->iSourceSink = ATAFN_SS_NULL;
3373 atapiR3CmdOK(pCtl, s);
3374 return false;
3375}
3376
3377
3378/**
3379 * Sink/Source: ATAPI READ TOC RAW
3380 */
3381static bool atapiR3ReadTOCRawSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3)
3382{
3383 uint8_t *pbBuf = s->abIOBuffer;
3384 uint8_t *q;
3385 uint8_t iStartTrack;
3386 bool fMSF;
3387 uint32_t cbSize;
3388 RT_NOREF(pDevIns, pDevR3);
3389
3390 Assert(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE);
3391 fMSF = (s->abATAPICmd[1] >> 1) & 1;
3392 iStartTrack = s->abATAPICmd[6];
3393
3394 q = pbBuf + 2;
3395 *q++ = 1; /* first session */
3396 *q++ = 1; /* last session */
3397
3398 *q++ = 1; /* session number */
3399 *q++ = 0x14; /* data track */
3400 *q++ = 0; /* track number */
3401 *q++ = 0xa0; /* first track in program area */
3402 *q++ = 0; /* min */
3403 *q++ = 0; /* sec */
3404 *q++ = 0; /* frame */
3405 *q++ = 0;
3406 *q++ = 1; /* first track */
3407 *q++ = 0x00; /* disk type CD-DA or CD data */
3408 *q++ = 0;
3409
3410 *q++ = 1; /* session number */
3411 *q++ = 0x14; /* data track */
3412 *q++ = 0; /* track number */
3413 *q++ = 0xa1; /* last track in program area */
3414 *q++ = 0; /* min */
3415 *q++ = 0; /* sec */
3416 *q++ = 0; /* frame */
3417 *q++ = 0;
3418 *q++ = 1; /* last track */
3419 *q++ = 0;
3420 *q++ = 0;
3421
3422 *q++ = 1; /* session number */
3423 *q++ = 0x14; /* data track */
3424 *q++ = 0; /* track number */
3425 *q++ = 0xa2; /* lead-out */
3426 *q++ = 0; /* min */
3427 *q++ = 0; /* sec */
3428 *q++ = 0; /* frame */
3429 if (fMSF)
3430 {
3431 *q++ = 0; /* reserved */
3432 scsiLBA2MSF(q, s->cTotalSectors);
3433 q += 3;
3434 }
3435 else
3436 {
3437 scsiH2BE_U32(q, s->cTotalSectors);
3438 q += 4;
3439 }
3440
3441 *q++ = 1; /* session number */
3442 *q++ = 0x14; /* ADR, control */
3443 *q++ = 0; /* track number */
3444 *q++ = 1; /* point */
3445 *q++ = 0; /* min */
3446 *q++ = 0; /* sec */
3447 *q++ = 0; /* frame */
3448 if (fMSF)
3449 {
3450 *q++ = 0; /* reserved */
3451 scsiLBA2MSF(q, 0);
3452 q += 3;
3453 }
3454 else
3455 {
3456 /* sector 0 */
3457 scsiH2BE_U32(q, 0);
3458 q += 4;
3459 }
3460
3461 cbSize = q - pbBuf;
3462 scsiH2BE_U16(pbBuf, cbSize - 2);
3463 if (cbSize < s->cbTotalTransfer)
3464 s->cbTotalTransfer = cbSize;
3465 s->iSourceSink = ATAFN_SS_NULL;
3466 atapiR3CmdOK(pCtl, s);
3467 return false;
3468}
3469
3470
3471static void atapiR3ParseCmdVirtualATAPI(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3)
3472{
3473 const uint8_t *pbPacket = s->abATAPICmd;
3474 uint32_t cbMax;
3475 uint32_t cSectors, iATAPILBA;
3476
3477 switch (pbPacket[0])
3478 {
3479 case SCSI_TEST_UNIT_READY:
3480 if (s->cNotifiedMediaChange > 0)
3481 {
3482 if (s->cNotifiedMediaChange-- > 2)
3483 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3484 else
3485 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3486 }
3487 else if (pDevR3->pDrvMount->pfnIsMounted(pDevR3->pDrvMount))
3488 atapiR3CmdOK(pCtl, s);
3489 else
3490 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3491 break;
3492 case SCSI_GET_EVENT_STATUS_NOTIFICATION:
3493 cbMax = scsiBE2H_U16(pbPacket + 7);
3494 ataR3StartTransfer(pDevIns, pCtl, s, RT_MIN(cbMax, 8), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_GET_EVENT_STATUS_NOTIFICATION, true);
3495 break;
3496 case SCSI_MODE_SENSE_10:
3497 {
3498 uint8_t uPageControl, uPageCode;
3499 cbMax = scsiBE2H_U16(pbPacket + 7);
3500 uPageControl = pbPacket[2] >> 6;
3501 uPageCode = pbPacket[2] & 0x3f;
3502 switch (uPageControl)
3503 {
3504 case SCSI_PAGECONTROL_CURRENT:
3505 switch (uPageCode)
3506 {
3507 case SCSI_MODEPAGE_ERROR_RECOVERY:
3508 ataR3StartTransfer(pDevIns, pCtl, s, RT_MIN(cbMax, 16), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_MODE_SENSE_ERROR_RECOVERY, true);
3509 break;
3510 case SCSI_MODEPAGE_CD_STATUS:
3511 ataR3StartTransfer(pDevIns, pCtl, s, RT_MIN(cbMax, 28), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_MODE_SENSE_CD_STATUS, true);
3512 break;
3513 default:
3514 goto error_cmd;
3515 }
3516 break;
3517 case SCSI_PAGECONTROL_CHANGEABLE:
3518 goto error_cmd;
3519 case SCSI_PAGECONTROL_DEFAULT:
3520 goto error_cmd;
3521 default:
3522 case SCSI_PAGECONTROL_SAVED:
3523 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_SAVING_PARAMETERS_NOT_SUPPORTED);
3524 break;
3525 }
3526 break;
3527 }
3528 case SCSI_REQUEST_SENSE:
3529 cbMax = pbPacket[4];
3530 ataR3StartTransfer(pDevIns, pCtl, s, RT_MIN(cbMax, 18), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_REQUEST_SENSE, true);
3531 break;
3532 case SCSI_PREVENT_ALLOW_MEDIUM_REMOVAL:
3533 if (pDevR3->pDrvMount->pfnIsMounted(pDevR3->pDrvMount))
3534 {
3535 if (pbPacket[4] & 1)
3536 pDevR3->pDrvMount->pfnLock(pDevR3->pDrvMount);
3537 else
3538 pDevR3->pDrvMount->pfnUnlock(pDevR3->pDrvMount);
3539 atapiR3CmdOK(pCtl, s);
3540 }
3541 else
3542 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3543 break;
3544 case SCSI_READ_10:
3545 case SCSI_READ_12:
3546 {
3547 if (s->cNotifiedMediaChange > 0)
3548 {
3549 s->cNotifiedMediaChange-- ;
3550 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3551 break;
3552 }
3553 else if (!pDevR3->pDrvMount->pfnIsMounted(pDevR3->pDrvMount))
3554 {
3555 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3556 break;
3557 }
3558 if (pbPacket[0] == SCSI_READ_10)
3559 cSectors = scsiBE2H_U16(pbPacket + 7);
3560 else
3561 cSectors = scsiBE2H_U32(pbPacket + 6);
3562 iATAPILBA = scsiBE2H_U32(pbPacket + 2);
3563
3564 if (cSectors == 0)
3565 {
3566 atapiR3CmdOK(pCtl, s);
3567 break;
3568 }
3569
3570 /* Check that the sector size is valid. */
3571 VDREGIONDATAFORM enmDataForm = VDREGIONDATAFORM_INVALID;
3572 int rc = pDevR3->pDrvMedia->pfnQueryRegionPropertiesForLba(pDevR3->pDrvMedia, iATAPILBA,
3573 NULL, NULL, NULL, &enmDataForm);
3574 if (RT_UNLIKELY( rc == VERR_NOT_FOUND
3575 || ((uint64_t)iATAPILBA + cSectors > s->cTotalSectors)))
3576 {
3577 /* Rate limited logging, one log line per second. For
3578 * guests that insist on reading from places outside the
3579 * valid area this often generates too many release log
3580 * entries otherwise. */
3581 static uint64_t uLastLogTS = 0;
3582 if (RTTimeMilliTS() >= uLastLogTS + 1000)
3583 {
3584 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM block number %Ld invalid (READ)\n", s->iLUN, (uint64_t)iATAPILBA + cSectors));
3585 uLastLogTS = RTTimeMilliTS();
3586 }
3587 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_LOGICAL_BLOCK_OOR);
3588 break;
3589 }
3590 else if ( enmDataForm != VDREGIONDATAFORM_MODE1_2048
3591 && enmDataForm != VDREGIONDATAFORM_MODE1_2352
3592 && enmDataForm != VDREGIONDATAFORM_MODE2_2336
3593 && enmDataForm != VDREGIONDATAFORM_MODE2_2352
3594 && enmDataForm != VDREGIONDATAFORM_RAW)
3595 {
3596 uint8_t abATAPISense[ATAPI_SENSE_SIZE];
3597 RT_ZERO(abATAPISense);
3598
3599 abATAPISense[0] = 0x70 | (1 << 7);
3600 abATAPISense[2] = (SCSI_SENSE_ILLEGAL_REQUEST & 0x0f) | SCSI_SENSE_FLAG_ILI;
3601 scsiH2BE_U32(&abATAPISense[3], iATAPILBA);
3602 abATAPISense[7] = 10;
3603 abATAPISense[12] = SCSI_ASC_ILLEGAL_MODE_FOR_THIS_TRACK;
3604 atapiR3CmdError(pCtl, s, &abATAPISense[0], sizeof(abATAPISense));
3605 break;
3606 }
3607 atapiR3ReadSectors(pDevIns, pCtl, s, iATAPILBA, cSectors, 2048);
3608 break;
3609 }
3610 case SCSI_READ_CD_MSF:
3611 case SCSI_READ_CD:
3612 {
3613 if (s->cNotifiedMediaChange > 0)
3614 {
3615 s->cNotifiedMediaChange-- ;
3616 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3617 break;
3618 }
3619 else if (!pDevR3->pDrvMount->pfnIsMounted(pDevR3->pDrvMount))
3620 {
3621 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3622 break;
3623 }
3624 if ((pbPacket[10] & 0x7) != 0)
3625 {
3626 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
3627 break;
3628 }
3629 if (pbPacket[0] == SCSI_READ_CD)
3630 {
3631 cSectors = (pbPacket[6] << 16) | (pbPacket[7] << 8) | pbPacket[8];
3632 iATAPILBA = scsiBE2H_U32(pbPacket + 2);
3633 }
3634 else /* READ CD MSF */
3635 {
3636 iATAPILBA = scsiMSF2LBA(pbPacket + 3);
3637 if (iATAPILBA > scsiMSF2LBA(pbPacket + 6))
3638 {
3639 Log2(("Start MSF %02u:%02u:%02u > end MSF %02u:%02u:%02u!\n", *(pbPacket + 3), *(pbPacket + 4), *(pbPacket + 5),
3640 *(pbPacket + 6), *(pbPacket + 7), *(pbPacket + 8)));
3641 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
3642 break;
3643 }
3644 cSectors = scsiMSF2LBA(pbPacket + 6) - iATAPILBA;
3645 Log2(("Start MSF %02u:%02u:%02u -> LBA %u\n", *(pbPacket + 3), *(pbPacket + 4), *(pbPacket + 5), iATAPILBA));
3646 Log2(("End MSF %02u:%02u:%02u -> %u sectors\n", *(pbPacket + 6), *(pbPacket + 7), *(pbPacket + 8), cSectors));
3647 }
3648 if (cSectors == 0)
3649 {
3650 atapiR3CmdOK(pCtl, s);
3651 break;
3652 }
3653 if ((uint64_t)iATAPILBA + cSectors > s->cTotalSectors)
3654 {
3655 /* Rate limited logging, one log line per second. For
3656 * guests that insist on reading from places outside the
3657 * valid area this often generates too many release log
3658 * entries otherwise. */
3659 static uint64_t uLastLogTS = 0;
3660 if (RTTimeMilliTS() >= uLastLogTS + 1000)
3661 {
3662 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM block number %Ld invalid (READ CD)\n", s->iLUN, (uint64_t)iATAPILBA + cSectors));
3663 uLastLogTS = RTTimeMilliTS();
3664 }
3665 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_LOGICAL_BLOCK_OOR);
3666 break;
3667 }
3668 /*
3669 * If the LBA is in an audio track we are required to ignore pretty much all
3670 * of the channel selection values (except 0x00) and map everything to 0x10
3671 * which means read user data with a sector size of 2352 bytes.
3672 *
3673 * (MMC-6 chapter 6.19.2.6)
3674 */
3675 uint8_t uChnSel = pbPacket[9] & 0xf8;
3676 VDREGIONDATAFORM enmDataForm;
3677 int rc = pDevR3->pDrvMedia->pfnQueryRegionPropertiesForLba(pDevR3->pDrvMedia, iATAPILBA,
3678 NULL, NULL, NULL, &enmDataForm);
3679 AssertRC(rc);
3680
3681 if (enmDataForm == VDREGIONDATAFORM_CDDA)
3682 {
3683 if (uChnSel == 0)
3684 {
3685 /* nothing */
3686 atapiR3CmdOK(pCtl, s);
3687 }
3688 else
3689 atapiR3ReadSectors(pDevIns, pCtl, s, iATAPILBA, cSectors, 2352);
3690 }
3691 else
3692 {
3693 switch (uChnSel)
3694 {
3695 case 0x00:
3696 /* nothing */
3697 atapiR3CmdOK(pCtl, s);
3698 break;
3699 case 0x10:
3700 /* normal read */
3701 atapiR3ReadSectors(pDevIns, pCtl, s, iATAPILBA, cSectors, 2048);
3702 break;
3703 case 0xf8:
3704 /* read all data */
3705 atapiR3ReadSectors(pDevIns, pCtl, s, iATAPILBA, cSectors, 2352);
3706 break;
3707 default:
3708 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM sector format not supported (%#x)\n", s->iLUN, pbPacket[9] & 0xf8));
3709 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
3710 break;
3711 }
3712 }
3713 break;
3714 }
3715 case SCSI_SEEK_10:
3716 {
3717 if (s->cNotifiedMediaChange > 0)
3718 {
3719 s->cNotifiedMediaChange-- ;
3720 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3721 break;
3722 }
3723 else if (!pDevR3->pDrvMount->pfnIsMounted(pDevR3->pDrvMount))
3724 {
3725 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3726 break;
3727 }
3728 iATAPILBA = scsiBE2H_U32(pbPacket + 2);
3729 if (iATAPILBA > s->cTotalSectors)
3730 {
3731 /* Rate limited logging, one log line per second. For
3732 * guests that insist on seeking to places outside the
3733 * valid area this often generates too many release log
3734 * entries otherwise. */
3735 static uint64_t uLastLogTS = 0;
3736 if (RTTimeMilliTS() >= uLastLogTS + 1000)
3737 {
3738 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM block number %Ld invalid (SEEK)\n", s->iLUN, (uint64_t)iATAPILBA));
3739 uLastLogTS = RTTimeMilliTS();
3740 }
3741 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_LOGICAL_BLOCK_OOR);
3742 break;
3743 }
3744 atapiR3CmdOK(pCtl, s);
3745 ataSetStatus(pCtl, s, ATA_STAT_SEEK); /* Linux expects this. */
3746 break;
3747 }
3748 case SCSI_START_STOP_UNIT:
3749 {
3750 int rc = VINF_SUCCESS;
3751 switch (pbPacket[4] & 3)
3752 {
3753 case 0: /* 00 - Stop motor */
3754 case 1: /* 01 - Start motor */
3755 break;
3756 case 2: /* 10 - Eject media */
3757 {
3758 /* This must be done from EMT. */
3759 PATASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PATASTATER3);
3760
3761 ataR3LockLeave(pDevIns, pCtl);
3762 rc = PDMDevHlpVMReqPriorityCallWait(pDevIns, VMCPUID_ANY,
3763 (PFNRT)pDevR3->pDrvMount->pfnUnmount, 3,
3764 pDevR3->pDrvMount, false /*=fForce*/, true /*=fEject*/);
3765 Assert(RT_SUCCESS(rc) || rc == VERR_PDM_MEDIA_LOCKED || rc == VERR_PDM_MEDIA_NOT_MOUNTED);
3766 if (RT_SUCCESS(rc) && pThisCC->pMediaNotify)
3767 {
3768 rc = PDMDevHlpVMReqCallNoWait(pDevIns, VMCPUID_ANY,
3769 (PFNRT)pThisCC->pMediaNotify->pfnEjected, 2,
3770 pThisCC->pMediaNotify, s->iLUN);
3771 AssertRC(rc);
3772 }
3773
3774 ataR3LockEnter(pDevIns, pCtl);
3775 break;
3776 }
3777 case 3: /* 11 - Load media */
3778 /** @todo rc = pDevR3->pDrvMount->pfnLoadMedia(pDevR3->pDrvMount) */
3779 break;
3780 }
3781 if (RT_SUCCESS(rc))
3782 atapiR3CmdOK(pCtl, s);
3783 else
3784 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIA_LOAD_OR_EJECT_FAILED);
3785 break;
3786 }
3787 case SCSI_MECHANISM_STATUS:
3788 {
3789 cbMax = scsiBE2H_U16(pbPacket + 8);
3790 ataR3StartTransfer(pDevIns, pCtl, s, RT_MIN(cbMax, 8), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_MECHANISM_STATUS, true);
3791 break;
3792 }
3793 case SCSI_READ_TOC_PMA_ATIP:
3794 {
3795 uint8_t format;
3796
3797 if (s->cNotifiedMediaChange > 0)
3798 {
3799 s->cNotifiedMediaChange-- ;
3800 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3801 break;
3802 }
3803 else if (!pDevR3->pDrvMount->pfnIsMounted(pDevR3->pDrvMount))
3804 {
3805 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3806 break;
3807 }
3808 cbMax = scsiBE2H_U16(pbPacket + 7);
3809 /* SCSI MMC-3 spec says format is at offset 2 (lower 4 bits),
3810 * but Linux kernel uses offset 9 (topmost 2 bits). Hope that
3811 * the other field is clear... */
3812 format = (pbPacket[2] & 0xf) | (pbPacket[9] >> 6);
3813 switch (format)
3814 {
3815 case 0:
3816 ataR3StartTransfer(pDevIns, pCtl, s, cbMax, PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_TOC_NORMAL, true);
3817 break;
3818 case 1:
3819 ataR3StartTransfer(pDevIns, pCtl, s, RT_MIN(cbMax, 12), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_TOC_MULTI, true);
3820 break;
3821 case 2:
3822 ataR3StartTransfer(pDevIns, pCtl, s, cbMax, PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_TOC_RAW, true);
3823 break;
3824 default:
3825 error_cmd:
3826 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
3827 break;
3828 }
3829 break;
3830 }
3831 case SCSI_READ_CAPACITY:
3832 if (s->cNotifiedMediaChange > 0)
3833 {
3834 s->cNotifiedMediaChange-- ;
3835 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3836 break;
3837 }
3838 else if (!pDevR3->pDrvMount->pfnIsMounted(pDevR3->pDrvMount))
3839 {
3840 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3841 break;
3842 }
3843 ataR3StartTransfer(pDevIns, pCtl, s, 8, PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_CAPACITY, true);
3844 break;
3845 case SCSI_READ_DISC_INFORMATION:
3846 if (s->cNotifiedMediaChange > 0)
3847 {
3848 s->cNotifiedMediaChange-- ;
3849 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3850 break;
3851 }
3852 else if (!pDevR3->pDrvMount->pfnIsMounted(pDevR3->pDrvMount))
3853 {
3854 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3855 break;
3856 }
3857 cbMax = scsiBE2H_U16(pbPacket + 7);
3858 ataR3StartTransfer(pDevIns, pCtl, s, RT_MIN(cbMax, 34), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_DISC_INFORMATION, true);
3859 break;
3860 case SCSI_READ_TRACK_INFORMATION:
3861 if (s->cNotifiedMediaChange > 0)
3862 {
3863 s->cNotifiedMediaChange-- ;
3864 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3865 break;
3866 }
3867 else if (!pDevR3->pDrvMount->pfnIsMounted(pDevR3->pDrvMount))
3868 {
3869 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3870 break;
3871 }
3872 cbMax = scsiBE2H_U16(pbPacket + 7);
3873 ataR3StartTransfer(pDevIns, pCtl, s, RT_MIN(cbMax, 36), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_TRACK_INFORMATION, true);
3874 break;
3875 case SCSI_GET_CONFIGURATION:
3876 /* No media change stuff here, it can confuse Linux guests. */
3877 cbMax = scsiBE2H_U16(pbPacket + 7);
3878 ataR3StartTransfer(pDevIns, pCtl, s, RT_MIN(cbMax, 80), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_GET_CONFIGURATION, true);
3879 break;
3880 case SCSI_INQUIRY:
3881 cbMax = scsiBE2H_U16(pbPacket + 3);
3882 ataR3StartTransfer(pDevIns, pCtl, s, RT_MIN(cbMax, 36), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_INQUIRY, true);
3883 break;
3884 case SCSI_READ_DVD_STRUCTURE:
3885 {
3886 cbMax = scsiBE2H_U16(pbPacket + 8);
3887 ataR3StartTransfer(pDevIns, pCtl, s, RT_MIN(cbMax, 4), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_DVD_STRUCTURE, true);
3888 break;
3889 }
3890 default:
3891 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE);
3892 break;
3893 }
3894}
3895
3896
3897/*
3898 * Parse ATAPI commands, passing them directly to the CD/DVD drive.
3899 */
3900static void atapiR3ParseCmdPassthrough(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3)
3901{
3902 const uint8_t *pbPacket = &s->abATAPICmd[0];
3903
3904 /* Some cases we have to handle here. */
3905 if ( pbPacket[0] == SCSI_GET_EVENT_STATUS_NOTIFICATION
3906 && ASMAtomicReadU32(&s->MediaEventStatus) != ATA_EVENT_STATUS_UNCHANGED)
3907 {
3908 uint32_t cbTransfer = scsiBE2H_U16(pbPacket + 7);
3909 ataR3StartTransfer(pDevIns, pCtl, s, RT_MIN(cbTransfer, 8), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_GET_EVENT_STATUS_NOTIFICATION, true);
3910 }
3911 else if ( pbPacket[0] == SCSI_REQUEST_SENSE
3912 && (s->abATAPISense[2] & 0x0f) != SCSI_SENSE_NONE)
3913 ataR3StartTransfer(pDevIns, pCtl, s, RT_MIN(pbPacket[4], 18), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_REQUEST_SENSE, true);
3914 else
3915 {
3916 size_t cbBuf = 0;
3917 size_t cbATAPISector = 0;
3918 size_t cbTransfer = 0;
3919 PDMMEDIATXDIR uTxDir = PDMMEDIATXDIR_NONE;
3920 uint8_t u8ScsiSts = SCSI_STATUS_OK;
3921
3922 if (pbPacket[0] == SCSI_FORMAT_UNIT || pbPacket[0] == SCSI_GET_PERFORMANCE)
3923 cbBuf = s->uATARegLCyl | (s->uATARegHCyl << 8); /* use ATAPI transfer length */
3924
3925 bool fPassthrough = ATAPIPassthroughParseCdb(pbPacket, sizeof(s->abATAPICmd), cbBuf, pDevR3->pTrackList,
3926 &s->abATAPISense[0], sizeof(s->abATAPISense), &uTxDir, &cbTransfer,
3927 &cbATAPISector, &u8ScsiSts);
3928 if (fPassthrough)
3929 {
3930 s->cbATAPISector = (uint32_t)cbATAPISector;
3931 Assert(s->cbATAPISector == (uint32_t)cbATAPISector);
3932 Assert(cbTransfer == (uint32_t)cbTransfer);
3933
3934 /*
3935 * Send a command to the drive, passing data in/out as required.
3936 * Commands which exceed the I/O buffer size are split below
3937 * or aborted if splitting is not implemented.
3938 */
3939 Log2(("ATAPI PT: max size %d\n", cbTransfer));
3940 if (cbTransfer == 0)
3941 uTxDir = PDMMEDIATXDIR_NONE;
3942 ataR3StartTransfer(pDevIns, pCtl, s, (uint32_t)cbTransfer, uTxDir, ATAFN_BT_ATAPI_PASSTHROUGH_CMD, ATAFN_SS_ATAPI_PASSTHROUGH, true);
3943 }
3944 else if (u8ScsiSts == SCSI_STATUS_CHECK_CONDITION)
3945 {
3946 /* Sense data is already set, end the request and notify the guest. */
3947 Log(("%s: sense=%#x (%s) asc=%#x ascq=%#x (%s)\n", __FUNCTION__, s->abATAPISense[2] & 0x0f, SCSISenseText(s->abATAPISense[2] & 0x0f),
3948 s->abATAPISense[12], s->abATAPISense[13], SCSISenseExtText(s->abATAPISense[12], s->abATAPISense[13])));
3949 s->uATARegError = s->abATAPISense[2] << 4;
3950 ataSetStatusValue(pCtl, s, ATA_STAT_READY | ATA_STAT_ERR);
3951 s->uATARegNSector = (s->uATARegNSector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
3952 Log2(("%s: interrupt reason %#04x\n", __FUNCTION__, s->uATARegNSector));
3953 s->cbTotalTransfer = 0;
3954 s->cbElementaryTransfer = 0;
3955 s->cbAtapiPassthroughTransfer = 0;
3956 s->iIOBufferCur = 0;
3957 s->iIOBufferEnd = 0;
3958 s->uTxDir = PDMMEDIATXDIR_NONE;
3959 s->iBeginTransfer = ATAFN_BT_NULL;
3960 s->iSourceSink = ATAFN_SS_NULL;
3961 }
3962 else if (u8ScsiSts == SCSI_STATUS_OK)
3963 atapiR3CmdOK(pCtl, s);
3964 }
3965}
3966
3967
3968static void atapiR3ParseCmd(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3)
3969{
3970 const uint8_t *pbPacket;
3971
3972 pbPacket = s->abATAPICmd;
3973# ifdef DEBUG
3974 Log(("%s: LUN#%d DMA=%d CMD=%#04x \"%s\"\n", __FUNCTION__, s->iLUN, s->fDMA, pbPacket[0], SCSICmdText(pbPacket[0])));
3975# else /* !DEBUG */
3976 Log(("%s: LUN#%d DMA=%d CMD=%#04x\n", __FUNCTION__, s->iLUN, s->fDMA, pbPacket[0]));
3977# endif /* !DEBUG */
3978 Log2(("%s: limit=%#x packet: %.*Rhxs\n", __FUNCTION__, s->uATARegLCyl | (s->uATARegHCyl << 8), ATAPI_PACKET_SIZE, pbPacket));
3979
3980 if (s->fATAPIPassthrough)
3981 atapiR3ParseCmdPassthrough(pDevIns, pCtl, s, pDevR3);
3982 else
3983 atapiR3ParseCmdVirtualATAPI(pDevIns, pCtl, s, pDevR3);
3984}
3985
3986
3987/**
3988 * Sink/Source: PACKET
3989 */
3990static bool ataR3PacketSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3)
3991{
3992 s->fDMA = !!(s->uATARegFeature & 1);
3993 memcpy(s->abATAPICmd, s->abIOBuffer, ATAPI_PACKET_SIZE);
3994 s->uTxDir = PDMMEDIATXDIR_NONE;
3995 s->cbTotalTransfer = 0;
3996 s->cbElementaryTransfer = 0;
3997 s->cbAtapiPassthroughTransfer = 0;
3998 atapiR3ParseCmd(pDevIns, pCtl, s, pDevR3);
3999 return false;
4000}
4001
4002
4003/**
4004 * SCSI_GET_EVENT_STATUS_NOTIFICATION should return "medium removed" event
4005 * from now on, regardless if there was a medium inserted or not.
4006 */
4007static void ataR3MediumRemoved(PATADEVSTATE s)
4008{
4009 ASMAtomicWriteU32(&s->MediaEventStatus, ATA_EVENT_STATUS_MEDIA_REMOVED);
4010}
4011
4012
4013/**
4014 * SCSI_GET_EVENT_STATUS_NOTIFICATION should return "medium inserted". If
4015 * there was already a medium inserted, don't forget to send the "medium
4016 * removed" event first.
4017 */
4018static void ataR3MediumInserted(PATADEVSTATE s)
4019{
4020 uint32_t OldStatus, NewStatus;
4021 do
4022 {
4023 OldStatus = ASMAtomicReadU32(&s->MediaEventStatus);
4024 switch (OldStatus)
4025 {
4026 case ATA_EVENT_STATUS_MEDIA_CHANGED:
4027 case ATA_EVENT_STATUS_MEDIA_REMOVED:
4028 /* no change, we will send "medium removed" + "medium inserted" */
4029 NewStatus = ATA_EVENT_STATUS_MEDIA_CHANGED;
4030 break;
4031 default:
4032 NewStatus = ATA_EVENT_STATUS_MEDIA_NEW;
4033 break;
4034 }
4035 } while (!ASMAtomicCmpXchgU32(&s->MediaEventStatus, NewStatus, OldStatus));
4036}
4037
4038
4039/**
4040 * @interface_method_impl{PDMIMOUNTNOTIFY,pfnMountNotify}
4041 */
4042static DECLCALLBACK(void) ataR3MountNotify(PPDMIMOUNTNOTIFY pInterface)
4043{
4044 PATADEVSTATER3 pIfR3 = RT_FROM_MEMBER(pInterface, ATADEVSTATER3, IMountNotify);
4045 PATASTATE pThis = PDMDEVINS_2_DATA(pIfR3->pDevIns, PATASTATE);
4046 PATADEVSTATE pIf = &RT_SAFE_SUBSCRIPT(RT_SAFE_SUBSCRIPT(pThis->aCts, pIfR3->iCtl).aIfs, pIfR3->iDev);
4047 Log(("%s: changing LUN#%d\n", __FUNCTION__, pIfR3->iLUN));
4048
4049 /* Ignore the call if we're called while being attached. */
4050 if (!pIfR3->pDrvMedia)
4051 return;
4052
4053 uint32_t cRegions = pIfR3->pDrvMedia->pfnGetRegionCount(pIfR3->pDrvMedia);
4054 for (uint32_t i = 0; i < cRegions; i++)
4055 {
4056 uint64_t cBlocks = 0;
4057 int rc = pIfR3->pDrvMedia->pfnQueryRegionProperties(pIfR3->pDrvMedia, i, NULL, &cBlocks,
4058 NULL, NULL);
4059 AssertRC(rc);
4060 pIf->cTotalSectors += cBlocks;
4061 }
4062
4063 LogRel(("PIIX3 ATA: LUN#%d: CD/DVD, total number of sectors %Ld, passthrough unchanged\n", pIf->iLUN, pIf->cTotalSectors));
4064
4065 /* Report media changed in TEST UNIT and other (probably incorrect) places. */
4066 if (pIf->cNotifiedMediaChange < 2)
4067 pIf->cNotifiedMediaChange = 1;
4068 ataR3MediumInserted(pIf);
4069 ataR3MediumTypeSet(pIf, ATA_MEDIA_TYPE_UNKNOWN);
4070}
4071
4072/**
4073 * @interface_method_impl{PDMIMOUNTNOTIFY,pfnUnmountNotify}
4074 */
4075static DECLCALLBACK(void) ataR3UnmountNotify(PPDMIMOUNTNOTIFY pInterface)
4076{
4077 PATADEVSTATER3 pIfR3 = RT_FROM_MEMBER(pInterface, ATADEVSTATER3, IMountNotify);
4078 PATASTATE pThis = PDMDEVINS_2_DATA(pIfR3->pDevIns, PATASTATE);
4079 PATADEVSTATE pIf = &RT_SAFE_SUBSCRIPT(RT_SAFE_SUBSCRIPT(pThis->aCts, pIfR3->iCtl).aIfs, pIfR3->iDev);
4080 Log(("%s:\n", __FUNCTION__));
4081 pIf->cTotalSectors = 0;
4082
4083 /*
4084 * Whatever I do, XP will not use the GET MEDIA STATUS nor the EVENT stuff.
4085 * However, it will respond to TEST UNIT with a 0x6 0x28 (media changed) sense code.
4086 * So, we'll give it 4 TEST UNIT command to catch up, two which the media is not
4087 * present and 2 in which it is changed.
4088 */
4089 pIf->cNotifiedMediaChange = 1;
4090 ataR3MediumRemoved(pIf);
4091 ataR3MediumTypeSet(pIf, ATA_MEDIA_NO_DISC);
4092}
4093
4094/**
4095 * Begin Transfer: PACKET
4096 */
4097static void ataR3PacketBT(PATACONTROLLER pCtl, PATADEVSTATE s)
4098{
4099 s->cbElementaryTransfer = s->cbTotalTransfer;
4100 s->cbAtapiPassthroughTransfer = s->cbTotalTransfer;
4101 s->uATARegNSector = (s->uATARegNSector & ~7) | ATAPI_INT_REASON_CD;
4102 Log2(("%s: interrupt reason %#04x\n", __FUNCTION__, s->uATARegNSector));
4103 ataSetStatusValue(pCtl, s, ATA_STAT_READY);
4104}
4105
4106
4107static void ataR3ResetDevice(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s)
4108{
4109 LogFlowFunc(("\n"));
4110 s->cMultSectors = ATA_MAX_MULT_SECTORS;
4111 s->cNotifiedMediaChange = 0;
4112 ASMAtomicWriteU32(&s->MediaEventStatus, ATA_EVENT_STATUS_UNCHANGED);
4113 ASMAtomicWriteU32(&s->MediaTrackType, ATA_MEDIA_TYPE_UNKNOWN);
4114 ataUnsetIRQ(pDevIns, pCtl, s);
4115
4116 s->uATARegSelect = 0x20;
4117 ataSetStatusValue(pCtl, s, ATA_STAT_READY | ATA_STAT_SEEK);
4118 ataR3SetSignature(s);
4119 s->cbTotalTransfer = 0;
4120 s->cbElementaryTransfer = 0;
4121 s->cbAtapiPassthroughTransfer = 0;
4122 s->iIOBufferPIODataStart = 0;
4123 s->iIOBufferPIODataEnd = 0;
4124 s->iBeginTransfer = ATAFN_BT_NULL;
4125 s->iSourceSink = ATAFN_SS_NULL;
4126 s->fDMA = false;
4127 s->fATAPITransfer = false;
4128 s->uATATransferMode = ATA_MODE_UDMA | 2; /* PIIX3 supports only up to UDMA2 */
4129
4130 s->XCHSGeometry = s->PCHSGeometry; /* Restore default CHS translation. */
4131
4132 s->uATARegFeature = 0;
4133}
4134
4135
4136static void ataR3DeviceDiag(PATACONTROLLER pCtl, PATADEVSTATE s)
4137{
4138 ataR3SetSignature(s);
4139 if (s->fATAPI)
4140 ataSetStatusValue(pCtl, s, 0); /* NOTE: READY is _not_ set */
4141 else
4142 ataSetStatusValue(pCtl, s, ATA_STAT_READY | ATA_STAT_SEEK);
4143 s->uATARegError = 0x01;
4144}
4145
4146
4147/**
4148 * Sink/Source: EXECUTE DEVICE DIAGNOTIC
4149 */
4150static bool ataR3ExecuteDeviceDiagnosticSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3)
4151{
4152 RT_NOREF(pDevIns, s, pDevR3);
4153
4154 /* EXECUTE DEVICE DIAGNOSTIC is a very special command which always
4155 * gets executed, regardless of which device is selected. As a side
4156 * effect, it always completes with device 0 selected.
4157 */
4158 for (uint32_t i = 0; i < RT_ELEMENTS(pCtl->aIfs); i++)
4159 ataR3DeviceDiag(pCtl, &pCtl->aIfs[i]);
4160
4161 LogRel(("ATA: LUN#%d: EXECUTE DEVICE DIAGNOSTIC, status %02X\n", s->iLUN, s->uATARegStatus));
4162 pCtl->iSelectedIf = 0;
4163
4164 return false;
4165}
4166
4167
4168/**
4169 * Sink/Source: INITIALIZE DEVICE PARAMETERS
4170 */
4171static bool ataR3InitDevParmSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3)
4172{
4173 RT_NOREF(pDevR3);
4174 LogFlowFunc(("\n"));
4175
4176 /* Technical Note:
4177 * On ST506 type drives with a separate controller, the INITIALIZE DRIVE PARAMETERS command was
4178 * required to inform the controller of drive geometry. The controller needed to know the
4179 * number of heads and sectors per track so that it could correctly advance to the next track
4180 * or cylinder when executing multi-sector commands. Setting a geometry that didn't match the
4181 * drive made very little sense because sectors had fixed CHS addresses. It was at best
4182 * possible to reduce the drive's capacity by limiting the number of heads and/or sectors
4183 * per track.
4184 *
4185 * IDE drives inherently have to know their true geometry, but most of them also support
4186 * programmable translation that can be set through the INITIALIZE DEVICE PARAMETERS command.
4187 * In fact most older IDE drives typically weren't operated using their default (native) geometry,
4188 * and with newer IDE drives that's not even an option.
4189 *
4190 * Up to and including ATA-5, the standard defined a CHS to LBA translation (since ATA-6, CHS
4191 * support is optional):
4192 *
4193 * LBA = (((cyl_num * heads_per_cyl) + head_num) * sectors_per_track) + sector_num - 1
4194 *
4195 * The INITIALIZE DEVICE PARAMETERS command sets the heads_per_cyl and sectors_per_track
4196 * values used in the above formula.
4197 *
4198 * Drives must obviously support an INITIALIZE DRIVE PARAMETERS command matching the drive's
4199 * default CHS translation. Everything else is optional.
4200 *
4201 * We support any geometry with non-zero sectors per track because there's no reason not to;
4202 * this behavior is common in many if not most IDE drives.
4203 */
4204
4205 PDMMEDIAGEOMETRY Geom = { 0 };
4206
4207 Geom.cHeads = (s->uATARegSelect & 0x0f) + 1; /* Effective range 1-16. */
4208 Geom.cSectors = s->uATARegNSector; /* Range 0-255, zero is not valid. */
4209
4210 if (Geom.cSectors)
4211 {
4212 uint64_t cCylinders = s->cTotalSectors / (Geom.cHeads * Geom.cSectors);
4213 Geom.cCylinders = RT_MAX(RT_MIN(cCylinders, 16383), 1);
4214
4215 s->XCHSGeometry = Geom;
4216
4217 ataR3LockLeave(pDevIns, pCtl);
4218 LogRel(("ATA: LUN#%d: INITIALIZE DEVICE PARAMETERS: %u sectors per track, %u heads\n",
4219 s->iLUN, s->uATARegNSector, (s->uATARegSelect & 0x0f) + 1));
4220 RTThreadSleep(pCtl->msDelayIRQ);
4221 ataR3LockEnter(pDevIns, pCtl);
4222 ataR3CmdOK(pCtl, s, ATA_STAT_SEEK);
4223 }
4224 else
4225 {
4226 ataR3LockLeave(pDevIns, pCtl);
4227 LogRel(("ATA: LUN#%d: INITIALIZE DEVICE PARAMETERS error (zero sectors per track)!\n", s->iLUN));
4228 RTThreadSleep(pCtl->msDelayIRQ);
4229 ataR3LockEnter(pDevIns, pCtl);
4230 ataR3CmdError(pCtl, s, ABRT_ERR);
4231 }
4232 return false;
4233}
4234
4235
4236/**
4237 * Sink/Source: RECALIBRATE
4238 */
4239static bool ataR3RecalibrateSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3)
4240{
4241 RT_NOREF(pDevR3);
4242 LogFlowFunc(("\n"));
4243 ataR3LockLeave(pDevIns, pCtl);
4244 RTThreadSleep(pCtl->msDelayIRQ);
4245 ataR3LockEnter(pDevIns, pCtl);
4246 ataR3CmdOK(pCtl, s, ATA_STAT_SEEK);
4247 return false;
4248}
4249
4250
4251static int ataR3TrimSectors(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3,
4252 uint64_t u64Sector, uint32_t cSectors, bool *pfRedo)
4253{
4254 RTRANGE TrimRange;
4255 int rc;
4256
4257 ataR3LockLeave(pDevIns, pCtl);
4258
4259 TrimRange.offStart = u64Sector * s->cbSector;
4260 TrimRange.cbRange = cSectors * s->cbSector;
4261
4262 s->Led.Asserted.s.fWriting = s->Led.Actual.s.fWriting = 1;
4263 rc = pDevR3->pDrvMedia->pfnDiscard(pDevR3->pDrvMedia, &TrimRange, 1);
4264 s->Led.Actual.s.fWriting = 0;
4265
4266 if (RT_SUCCESS(rc))
4267 *pfRedo = false;
4268 else
4269 *pfRedo = ataR3IsRedoSetWarning(pDevIns, pCtl, rc);
4270
4271 ataR3LockEnter(pDevIns, pCtl);
4272 return rc;
4273}
4274
4275
4276/**
4277 * Sink/Source: TRIM
4278 */
4279static bool ataR3TrimSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3)
4280{
4281 int rc = VERR_GENERAL_FAILURE;
4282 uint32_t cRangesMax;
4283 uint64_t *pu64Range = (uint64_t *)&s->abIOBuffer[0];
4284 bool fRedo = false;
4285
4286 cRangesMax = RT_MIN(s->cbElementaryTransfer, sizeof(s->abIOBuffer)) / sizeof(uint64_t);
4287 Assert(cRangesMax);
4288
4289 while (cRangesMax-- > 0)
4290 {
4291 if (ATA_RANGE_LENGTH_GET(*pu64Range) == 0)
4292 break;
4293
4294 rc = ataR3TrimSectors(pDevIns, pCtl, s, pDevR3, *pu64Range & ATA_RANGE_LBA_MASK,
4295 ATA_RANGE_LENGTH_GET(*pu64Range), &fRedo);
4296 if (RT_FAILURE(rc))
4297 break;
4298
4299 pu64Range++;
4300 }
4301
4302 if (RT_SUCCESS(rc))
4303 {
4304 s->iSourceSink = ATAFN_SS_NULL;
4305 ataR3CmdOK(pCtl, s, ATA_STAT_SEEK);
4306 }
4307 else
4308 {
4309 if (fRedo)
4310 return fRedo;
4311 if (s->cErrors++ < MAX_LOG_REL_ERRORS)
4312 LogRel(("PIIX3 ATA: LUN#%d: disk trim error (rc=%Rrc iSector=%#RX64 cSectors=%#RX32)\n",
4313 s->iLUN, rc, *pu64Range & ATA_RANGE_LBA_MASK, ATA_RANGE_LENGTH_GET(*pu64Range)));
4314
4315 /*
4316 * Check if we got interrupted. We don't need to set status variables
4317 * because the request was aborted.
4318 */
4319 if (rc != VERR_INTERRUPTED)
4320 ataR3CmdError(pCtl, s, ID_ERR);
4321 }
4322
4323 return false;
4324}
4325
4326
4327static void ataR3ParseCmd(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3, uint8_t cmd)
4328{
4329# ifdef DEBUG
4330 Log(("%s: LUN#%d CMD=%#04x \"%s\"\n", __FUNCTION__, s->iLUN, cmd, ATACmdText(cmd)));
4331# else /* !DEBUG */
4332 Log(("%s: LUN#%d CMD=%#04x\n", __FUNCTION__, s->iLUN, cmd));
4333# endif /* !DEBUG */
4334 s->fLBA48 = false;
4335 s->fDMA = false;
4336 if (cmd == ATA_IDLE_IMMEDIATE)
4337 {
4338 /* Detect Linux timeout recovery, first tries IDLE IMMEDIATE (which
4339 * would overwrite the failing command unfortunately), then RESET. */
4340 int32_t uCmdWait = -1;
4341 uint64_t uNow = RTTimeNanoTS();
4342 if (s->u64CmdTS)
4343 uCmdWait = (uNow - s->u64CmdTS) / 1000;
4344 LogRel(("PIIX3 ATA: LUN#%d: IDLE IMMEDIATE, CmdIf=%#04x (%d usec ago)\n",
4345 s->iLUN, s->uATARegCommand, uCmdWait));
4346 }
4347 s->uATARegCommand = cmd;
4348 switch (cmd)
4349 {
4350 case ATA_IDENTIFY_DEVICE:
4351 if (pDevR3->pDrvMedia && !s->fATAPI)
4352 ataR3StartTransfer(pDevIns, pCtl, s, 512, PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_NULL, ATAFN_SS_IDENTIFY, false);
4353 else
4354 {
4355 if (s->fATAPI)
4356 ataR3SetSignature(s);
4357 ataR3CmdError(pCtl, s, ABRT_ERR);
4358 ataUnsetStatus(pCtl, s, ATA_STAT_READY);
4359 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */
4360 }
4361 break;
4362 case ATA_RECALIBRATE:
4363 if (s->fATAPI)
4364 goto abort_cmd;
4365 ataR3StartTransfer(pDevIns, pCtl, s, 0, PDMMEDIATXDIR_NONE, ATAFN_BT_NULL, ATAFN_SS_RECALIBRATE, false);
4366 break;
4367 case ATA_INITIALIZE_DEVICE_PARAMETERS:
4368 if (s->fATAPI)
4369 goto abort_cmd;
4370 ataR3StartTransfer(pDevIns, pCtl, s, 0, PDMMEDIATXDIR_NONE, ATAFN_BT_NULL, ATAFN_SS_INITIALIZE_DEVICE_PARAMETERS, false);
4371 break;
4372 case ATA_SET_MULTIPLE_MODE:
4373 if ( s->uATARegNSector != 0
4374 && ( s->uATARegNSector > ATA_MAX_MULT_SECTORS
4375 || (s->uATARegNSector & (s->uATARegNSector - 1)) != 0))
4376 {
4377 ataR3CmdError(pCtl, s, ABRT_ERR);
4378 }
4379 else
4380 {
4381 Log2(("%s: set multi sector count to %d\n", __FUNCTION__, s->uATARegNSector));
4382 s->cMultSectors = s->uATARegNSector;
4383 ataR3CmdOK(pCtl, s, 0);
4384 }
4385 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */
4386 break;
4387 case ATA_READ_VERIFY_SECTORS_EXT:
4388 s->fLBA48 = true;
4389 RT_FALL_THRU();
4390 case ATA_READ_VERIFY_SECTORS:
4391 case ATA_READ_VERIFY_SECTORS_WITHOUT_RETRIES:
4392 /* do sector number check ? */
4393 ataR3CmdOK(pCtl, s, ATA_STAT_SEEK);
4394 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */
4395 break;
4396 case ATA_READ_SECTORS_EXT:
4397 s->fLBA48 = true;
4398 RT_FALL_THRU();
4399 case ATA_READ_SECTORS:
4400 case ATA_READ_SECTORS_WITHOUT_RETRIES:
4401 if (!pDevR3->pDrvMedia || s->fATAPI)
4402 goto abort_cmd;
4403 s->cSectorsPerIRQ = 1;
4404 s->iCurLBA = ataR3GetSector(s);
4405 ataR3StartTransfer(pDevIns, pCtl, s, ataR3GetNSectors(s) * s->cbSector, PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_READ_SECTORS, false);
4406 break;
4407 case ATA_WRITE_SECTORS_EXT:
4408 s->fLBA48 = true;
4409 RT_FALL_THRU();
4410 case ATA_WRITE_SECTORS:
4411 case ATA_WRITE_SECTORS_WITHOUT_RETRIES:
4412 if (!pDevR3->pDrvMedia || s->fATAPI)
4413 goto abort_cmd;
4414 s->cSectorsPerIRQ = 1;
4415 s->iCurLBA = ataR3GetSector(s);
4416 ataR3StartTransfer(pDevIns, pCtl, s, ataR3GetNSectors(s) * s->cbSector, PDMMEDIATXDIR_TO_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_WRITE_SECTORS, false);
4417 break;
4418 case ATA_READ_MULTIPLE_EXT:
4419 s->fLBA48 = true;
4420 RT_FALL_THRU();
4421 case ATA_READ_MULTIPLE:
4422 if (!pDevR3->pDrvMedia || !s->cMultSectors || s->fATAPI)
4423 goto abort_cmd;
4424 s->cSectorsPerIRQ = s->cMultSectors;
4425 s->iCurLBA = ataR3GetSector(s);
4426 ataR3StartTransfer(pDevIns, pCtl, s, ataR3GetNSectors(s) * s->cbSector, PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_READ_SECTORS, false);
4427 break;
4428 case ATA_WRITE_MULTIPLE_EXT:
4429 s->fLBA48 = true;
4430 RT_FALL_THRU();
4431 case ATA_WRITE_MULTIPLE:
4432 if (!pDevR3->pDrvMedia || !s->cMultSectors || s->fATAPI)
4433 goto abort_cmd;
4434 s->cSectorsPerIRQ = s->cMultSectors;
4435 s->iCurLBA = ataR3GetSector(s);
4436 ataR3StartTransfer(pDevIns, pCtl, s, ataR3GetNSectors(s) * s->cbSector, PDMMEDIATXDIR_TO_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_WRITE_SECTORS, false);
4437 break;
4438 case ATA_READ_DMA_EXT:
4439 s->fLBA48 = true;
4440 RT_FALL_THRU();
4441 case ATA_READ_DMA:
4442 case ATA_READ_DMA_WITHOUT_RETRIES:
4443 if (!pDevR3->pDrvMedia || s->fATAPI)
4444 goto abort_cmd;
4445 s->cSectorsPerIRQ = ATA_MAX_MULT_SECTORS;
4446 s->iCurLBA = ataR3GetSector(s);
4447 s->fDMA = true;
4448 ataR3StartTransfer(pDevIns, pCtl, s, ataR3GetNSectors(s) * s->cbSector, PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_READ_SECTORS, false);
4449 break;
4450 case ATA_WRITE_DMA_EXT:
4451 s->fLBA48 = true;
4452 RT_FALL_THRU();
4453 case ATA_WRITE_DMA:
4454 case ATA_WRITE_DMA_WITHOUT_RETRIES:
4455 if (!pDevR3->pDrvMedia || s->fATAPI)
4456 goto abort_cmd;
4457 s->cSectorsPerIRQ = ATA_MAX_MULT_SECTORS;
4458 s->iCurLBA = ataR3GetSector(s);
4459 s->fDMA = true;
4460 ataR3StartTransfer(pDevIns, pCtl, s, ataR3GetNSectors(s) * s->cbSector, PDMMEDIATXDIR_TO_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_WRITE_SECTORS, false);
4461 break;
4462 case ATA_READ_NATIVE_MAX_ADDRESS_EXT:
4463 if (!pDevR3->pDrvMedia || s->fATAPI)
4464 goto abort_cmd;
4465 s->fLBA48 = true;
4466 ataR3SetSector(s, s->cTotalSectors - 1);
4467 ataR3CmdOK(pCtl, s, 0);
4468 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */
4469 break;
4470 case ATA_SEEK: /* Used by the SCO OpenServer. Command is marked as obsolete */
4471 ataR3CmdOK(pCtl, s, 0);
4472 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */
4473 break;
4474 case ATA_READ_NATIVE_MAX_ADDRESS:
4475 if (!pDevR3->pDrvMedia || s->fATAPI)
4476 goto abort_cmd;
4477 ataR3SetSector(s, RT_MIN(s->cTotalSectors, 1 << 28) - 1);
4478 ataR3CmdOK(pCtl, s, 0);
4479 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */
4480 break;
4481 case ATA_CHECK_POWER_MODE:
4482 s->uATARegNSector = 0xff; /* drive active or idle */
4483 ataR3CmdOK(pCtl, s, 0);
4484 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */
4485 break;
4486 case ATA_SET_FEATURES:
4487 Log2(("%s: feature=%#x\n", __FUNCTION__, s->uATARegFeature));
4488 if (!pDevR3->pDrvMedia)
4489 goto abort_cmd;
4490 switch (s->uATARegFeature)
4491 {
4492 case 0x02: /* write cache enable */
4493 Log2(("%s: write cache enable\n", __FUNCTION__));
4494 ataR3CmdOK(pCtl, s, ATA_STAT_SEEK);
4495 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */
4496 break;
4497 case 0xaa: /* read look-ahead enable */
4498 Log2(("%s: read look-ahead enable\n", __FUNCTION__));
4499 ataR3CmdOK(pCtl, s, ATA_STAT_SEEK);
4500 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */
4501 break;
4502 case 0x55: /* read look-ahead disable */
4503 Log2(("%s: read look-ahead disable\n", __FUNCTION__));
4504 ataR3CmdOK(pCtl, s, ATA_STAT_SEEK);
4505 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */
4506 break;
4507 case 0xcc: /* reverting to power-on defaults enable */
4508 Log2(("%s: revert to power-on defaults enable\n", __FUNCTION__));
4509 ataR3CmdOK(pCtl, s, ATA_STAT_SEEK);
4510 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */
4511 break;
4512 case 0x66: /* reverting to power-on defaults disable */
4513 Log2(("%s: revert to power-on defaults disable\n", __FUNCTION__));
4514 ataR3CmdOK(pCtl, s, ATA_STAT_SEEK);
4515 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */
4516 break;
4517 case 0x82: /* write cache disable */
4518 Log2(("%s: write cache disable\n", __FUNCTION__));
4519 /* As per the ATA/ATAPI-6 specs, a write cache disable
4520 * command MUST flush the write buffers to disc. */
4521 ataR3StartTransfer(pDevIns, pCtl, s, 0, PDMMEDIATXDIR_NONE, ATAFN_BT_NULL, ATAFN_SS_FLUSH, false);
4522 break;
4523 case 0x03: { /* set transfer mode */
4524 Log2(("%s: transfer mode %#04x\n", __FUNCTION__, s->uATARegNSector));
4525 switch (s->uATARegNSector & 0xf8)
4526 {
4527 case 0x00: /* PIO default */
4528 case 0x08: /* PIO mode */
4529 break;
4530 case ATA_MODE_MDMA: /* MDMA mode */
4531 s->uATATransferMode = (s->uATARegNSector & 0xf8) | RT_MIN(s->uATARegNSector & 0x07, ATA_MDMA_MODE_MAX);
4532 break;
4533 case ATA_MODE_UDMA: /* UDMA mode */
4534 s->uATATransferMode = (s->uATARegNSector & 0xf8) | RT_MIN(s->uATARegNSector & 0x07, ATA_UDMA_MODE_MAX);
4535 break;
4536 default:
4537 goto abort_cmd;
4538 }
4539 ataR3CmdOK(pCtl, s, ATA_STAT_SEEK);
4540 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */
4541 break;
4542 }
4543 default:
4544 goto abort_cmd;
4545 }
4546 /*
4547 * OS/2 workarond:
4548 * The OS/2 IDE driver from MCP2 appears to rely on the feature register being
4549 * reset here. According to the specification, this is a driver bug as the register
4550 * contents are undefined after the call. This means we can just as well reset it.
4551 */
4552 s->uATARegFeature = 0;
4553 break;
4554 case ATA_FLUSH_CACHE_EXT:
4555 case ATA_FLUSH_CACHE:
4556 if (!pDevR3->pDrvMedia || s->fATAPI)
4557 goto abort_cmd;
4558 ataR3StartTransfer(pDevIns, pCtl, s, 0, PDMMEDIATXDIR_NONE, ATAFN_BT_NULL, ATAFN_SS_FLUSH, false);
4559 break;
4560 case ATA_STANDBY_IMMEDIATE:
4561 ataR3CmdOK(pCtl, s, 0);
4562 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */
4563 break;
4564 case ATA_IDLE_IMMEDIATE:
4565 LogRel(("PIIX3 ATA: LUN#%d: aborting current command\n", s->iLUN));
4566 ataR3AbortCurrentCommand(pDevIns, pCtl, s, false);
4567 break;
4568 case ATA_SLEEP:
4569 ataR3CmdOK(pCtl, s, 0);
4570 ataHCSetIRQ(pDevIns, pCtl, s);
4571 break;
4572 /* ATAPI commands */
4573 case ATA_IDENTIFY_PACKET_DEVICE:
4574 if (s->fATAPI)
4575 ataR3StartTransfer(pDevIns, pCtl, s, 512, PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_NULL, ATAFN_SS_ATAPI_IDENTIFY, false);
4576 else
4577 {
4578 ataR3CmdError(pCtl, s, ABRT_ERR);
4579 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */
4580 }
4581 break;
4582 case ATA_EXECUTE_DEVICE_DIAGNOSTIC:
4583 ataR3StartTransfer(pDevIns, pCtl, s, 0, PDMMEDIATXDIR_NONE, ATAFN_BT_NULL, ATAFN_SS_EXECUTE_DEVICE_DIAGNOSTIC, false);
4584 break;
4585 case ATA_DEVICE_RESET:
4586 if (!s->fATAPI)
4587 goto abort_cmd;
4588 LogRel(("PIIX3 ATA: LUN#%d: performing device RESET\n", s->iLUN));
4589 ataR3AbortCurrentCommand(pDevIns, pCtl, s, true);
4590 break;
4591 case ATA_PACKET:
4592 if (!s->fATAPI)
4593 goto abort_cmd;
4594 /* overlapping commands not supported */
4595 if (s->uATARegFeature & 0x02)
4596 goto abort_cmd;
4597 ataR3StartTransfer(pDevIns, pCtl, s, ATAPI_PACKET_SIZE, PDMMEDIATXDIR_TO_DEVICE, ATAFN_BT_PACKET, ATAFN_SS_PACKET, false);
4598 break;
4599 case ATA_DATA_SET_MANAGEMENT:
4600 if (!pDevR3->pDrvMedia || !pDevR3->pDrvMedia->pfnDiscard)
4601 goto abort_cmd;
4602 if ( !(s->uATARegFeature & UINT8_C(0x01))
4603 || (s->uATARegFeature & ~UINT8_C(0x01)))
4604 goto abort_cmd;
4605 s->fDMA = true;
4606 ataR3StartTransfer(pDevIns, pCtl, s, (s->uATARegNSectorHOB << 8 | s->uATARegNSector) * s->cbSector, PDMMEDIATXDIR_TO_DEVICE, ATAFN_BT_NULL, ATAFN_SS_TRIM, false);
4607 break;
4608 default:
4609 abort_cmd:
4610 ataR3CmdError(pCtl, s, ABRT_ERR);
4611 if (s->fATAPI)
4612 ataUnsetStatus(pCtl, s, ATA_STAT_READY);
4613 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */
4614 break;
4615 }
4616}
4617
4618# endif /* IN_RING3 */
4619#endif /* IN_RING0 || IN_RING3 */
4620
4621/*
4622 * Note: There are four distinct cases of port I/O handling depending on
4623 * which devices (if any) are attached to an IDE channel:
4624 *
4625 * 1) No device attached. No response to writes or reads (i.e. reads return
4626 * all bits set).
4627 *
4628 * 2) Both devices attached. Reads and writes are processed normally.
4629 *
4630 * 3) Device 0 only. If device 0 is selected, normal behavior applies. But
4631 * if Device 1 is selected, writes are still directed to Device 0 (except
4632 * commands are not executed), reads from control/command registers are
4633 * directed to Device 0, but status/alt status reads return 0. If Device 1
4634 * is a PACKET device, all reads return 0. See ATAPI-6 clause 9.16.1 and
4635 * Table 18 in clause 7.1.
4636 *
4637 * 4) Device 1 only - non-standard(!). Device 1 can't tell if Device 0 is
4638 * present or not and behaves the same. That means if Device 0 is selected,
4639 * Device 1 responds to writes (except commands are not executed) but does
4640 * not respond to reads. If Device 1 selected, normal behavior applies.
4641 * See ATAPI-6 clause 9.16.2 and Table 15 in clause 7.1.
4642 */
4643
4644static VBOXSTRICTRC ataIOPortWriteU8(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, uint32_t addr, uint32_t val, uintptr_t iCtl)
4645{
4646 RT_NOREF(iCtl);
4647 Log2(("%s: LUN#%d write addr=%#x val=%#04x\n", __FUNCTION__, pCtl->aIfs[pCtl->iSelectedIf & ATA_SELECTED_IF_MASK].iLUN, addr, val));
4648 addr &= 7;
4649 switch (addr)
4650 {
4651 case 0:
4652 break;
4653 case 1: /* feature register */
4654 /* NOTE: data is written to the two drives */
4655 pCtl->aIfs[0].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
4656 pCtl->aIfs[1].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
4657 pCtl->aIfs[0].uATARegFeatureHOB = pCtl->aIfs[0].uATARegFeature;
4658 pCtl->aIfs[1].uATARegFeatureHOB = pCtl->aIfs[1].uATARegFeature;
4659 pCtl->aIfs[0].uATARegFeature = val;
4660 pCtl->aIfs[1].uATARegFeature = val;
4661 break;
4662 case 2: /* sector count */
4663 pCtl->aIfs[0].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
4664 pCtl->aIfs[1].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
4665 pCtl->aIfs[0].uATARegNSectorHOB = pCtl->aIfs[0].uATARegNSector;
4666 pCtl->aIfs[1].uATARegNSectorHOB = pCtl->aIfs[1].uATARegNSector;
4667 pCtl->aIfs[0].uATARegNSector = val;
4668 pCtl->aIfs[1].uATARegNSector = val;
4669 break;
4670 case 3: /* sector number */
4671 pCtl->aIfs[0].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
4672 pCtl->aIfs[1].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
4673 pCtl->aIfs[0].uATARegSectorHOB = pCtl->aIfs[0].uATARegSector;
4674 pCtl->aIfs[1].uATARegSectorHOB = pCtl->aIfs[1].uATARegSector;
4675 pCtl->aIfs[0].uATARegSector = val;
4676 pCtl->aIfs[1].uATARegSector = val;
4677 break;
4678 case 4: /* cylinder low */
4679 pCtl->aIfs[0].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
4680 pCtl->aIfs[1].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
4681 pCtl->aIfs[0].uATARegLCylHOB = pCtl->aIfs[0].uATARegLCyl;
4682 pCtl->aIfs[1].uATARegLCylHOB = pCtl->aIfs[1].uATARegLCyl;
4683 pCtl->aIfs[0].uATARegLCyl = val;
4684 pCtl->aIfs[1].uATARegLCyl = val;
4685 break;
4686 case 5: /* cylinder high */
4687 pCtl->aIfs[0].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
4688 pCtl->aIfs[1].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
4689 pCtl->aIfs[0].uATARegHCylHOB = pCtl->aIfs[0].uATARegHCyl;
4690 pCtl->aIfs[1].uATARegHCylHOB = pCtl->aIfs[1].uATARegHCyl;
4691 pCtl->aIfs[0].uATARegHCyl = val;
4692 pCtl->aIfs[1].uATARegHCyl = val;
4693 break;
4694 case 6: /* drive/head */
4695 pCtl->aIfs[0].uATARegSelect = (val & ~0x10) | 0xa0;
4696 pCtl->aIfs[1].uATARegSelect = (val | 0x10) | 0xa0;
4697 if (((val >> 4) & ATA_SELECTED_IF_MASK) != pCtl->iSelectedIf)
4698 {
4699 /* select another drive */
4700 uintptr_t const iSelectedIf = (val >> 4) & ATA_SELECTED_IF_MASK;
4701 pCtl->iSelectedIf = (uint8_t)iSelectedIf;
4702 /* The IRQ line is multiplexed between the two drives, so
4703 * update the state when switching to another drive. Only need
4704 * to update interrupt line if it is enabled and there is a
4705 * state change. */
4706 if ( !(pCtl->aIfs[iSelectedIf].uATARegDevCtl & ATA_DEVCTL_DISABLE_IRQ)
4707 && pCtl->aIfs[iSelectedIf].fIrqPending != pCtl->aIfs[iSelectedIf ^ 1].fIrqPending)
4708 {
4709 if (pCtl->aIfs[iSelectedIf].fIrqPending)
4710 {
4711 Log2(("%s: LUN#%d asserting IRQ (drive select change)\n", __FUNCTION__, pCtl->aIfs[iSelectedIf].iLUN));
4712 /* The BMDMA unit unconditionally sets BM_STATUS_INT if
4713 * the interrupt line is asserted. It monitors the line
4714 * for a rising edge. */
4715 pCtl->BmDma.u8Status |= BM_STATUS_INT;
4716 if (pCtl->irq == 16)
4717 PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4718 else
4719 PDMDevHlpISASetIrq(pDevIns, pCtl->irq, 1);
4720 }
4721 else
4722 {
4723 Log2(("%s: LUN#%d deasserting IRQ (drive select change)\n", __FUNCTION__, pCtl->aIfs[iSelectedIf].iLUN));
4724 if (pCtl->irq == 16)
4725 PDMDevHlpPCISetIrq(pDevIns, 0, 0);
4726 else
4727 PDMDevHlpISASetIrq(pDevIns, pCtl->irq, 0);
4728 }
4729 }
4730 }
4731 break;
4732 default:
4733 case 7: /* command */
4734 {
4735 /* ignore commands to non-existent device */
4736 uintptr_t iSelectedIf = pCtl->iSelectedIf & ATA_SELECTED_IF_MASK;
4737 PATADEVSTATE pDev = &pCtl->aIfs[iSelectedIf];
4738 if (iSelectedIf && !pDev->fPresent) /** @todo r=bird the iSelectedIf test here looks bogus... explain. */
4739 break;
4740#ifndef IN_RING3
4741 /* Don't do anything complicated in GC */
4742 return VINF_IOM_R3_IOPORT_WRITE;
4743#else /* IN_RING3 */
4744 PATASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PATASTATER3);
4745 ataUnsetIRQ(pDevIns, pCtl, &pCtl->aIfs[iSelectedIf]);
4746 ataR3ParseCmd(pDevIns, pCtl, &pCtl->aIfs[iSelectedIf], &pThisCC->aCts[iCtl].aIfs[iSelectedIf], val);
4747 break;
4748#endif /* !IN_RING3 */
4749 }
4750 }
4751 return VINF_SUCCESS;
4752}
4753
4754
4755static VBOXSTRICTRC ataIOPortReadU8(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, uint32_t addr, uint32_t *pu32)
4756{
4757 PATADEVSTATE s = &pCtl->aIfs[pCtl->iSelectedIf & ATA_SELECTED_IF_MASK];
4758 uint32_t val;
4759 bool fHOB;
4760
4761 /* Check if the guest is reading from a non-existent device. */
4762 if (RT_LIKELY(s->fPresent))
4763 { /* likely */ }
4764 else
4765 {
4766 if (pCtl->iSelectedIf) /* Device 1 selected, Device 0 responding for it. */
4767 {
4768 Assert(pCtl->aIfs[0].fPresent);
4769
4770 /* When an ATAPI device 0 responds for non-present device 1, it generally
4771 * returns zeros on reads. The Error register is an exception. See clause 7.1,
4772 * table 16 in ATA-6 specification.
4773 */
4774 if (((addr & 7) != 1) && pCtl->aIfs[0].fATAPI)
4775 {
4776 Log2(("%s: addr=%#x, val=0: LUN#%d not attached/LUN#%d ATAPI\n", __FUNCTION__, addr, s->iLUN, pCtl->aIfs[0].iLUN));
4777 *pu32 = 0;
4778 return VINF_SUCCESS;
4779 }
4780 /* Else handle normally. */
4781 }
4782 else /* Device 0 selected (but not present). */
4783 {
4784 /* Because device 1 has no way to tell if there is device 0, the behavior is the same
4785 * as for an empty bus; see comments in ataIOPortReadEmptyBus(). Note that EFI (TianoCore)
4786 * relies on this behavior when detecting devices.
4787 */
4788 *pu32 = ATA_EMPTY_BUS_DATA;
4789 Log2(("%s: addr=%#x: LUN#%d not attached, val=%#02x\n", __FUNCTION__, addr, s->iLUN, *pu32));
4790 return VINF_SUCCESS;
4791 }
4792 }
4793
4794 fHOB = !!(s->uATARegDevCtl & (1 << 7));
4795 switch (addr & 7)
4796 {
4797 case 0: /* data register */
4798 val = 0xff;
4799 break;
4800 case 1: /* error register */
4801 /* The ATA specification is very terse when it comes to specifying
4802 * the precise effects of reading back the error/feature register.
4803 * The error register (read-only) shares the register number with
4804 * the feature register (write-only), so it seems that it's not
4805 * necessary to support the usual HOB readback here. */
4806 if (!s->fPresent)
4807 val = 0;
4808 else
4809 val = s->uATARegError;
4810 break;
4811 case 2: /* sector count */
4812 if (fHOB)
4813 val = s->uATARegNSectorHOB;
4814 else
4815 val = s->uATARegNSector;
4816 break;
4817 case 3: /* sector number */
4818 if (fHOB)
4819 val = s->uATARegSectorHOB;
4820 else
4821 val = s->uATARegSector;
4822 break;
4823 case 4: /* cylinder low */
4824 if (fHOB)
4825 val = s->uATARegLCylHOB;
4826 else
4827 val = s->uATARegLCyl;
4828 break;
4829 case 5: /* cylinder high */
4830 if (fHOB)
4831 val = s->uATARegHCylHOB;
4832 else
4833 val = s->uATARegHCyl;
4834 break;
4835 case 6: /* drive/head */
4836 /* This register must always work as long as there is at least
4837 * one drive attached to the controller. It is common between
4838 * both drives anyway (completely identical content). */
4839 if (!pCtl->aIfs[0].fPresent && !pCtl->aIfs[1].fPresent)
4840 val = 0;
4841 else
4842 val = s->uATARegSelect;
4843 break;
4844 default:
4845 case 7: /* primary status */
4846 {
4847 if (!s->fPresent)
4848 val = 0;
4849 else
4850 val = s->uATARegStatus;
4851
4852 /* Give the async I/O thread an opportunity to make progress,
4853 * don't let it starve by guests polling frequently. EMT has a
4854 * lower priority than the async I/O thread, but sometimes the
4855 * host OS doesn't care. With some guests we are only allowed to
4856 * be busy for about 5 milliseconds in some situations. Note that
4857 * this is no guarantee for any other VBox thread getting
4858 * scheduled, so this just lowers the CPU load a bit when drives
4859 * are busy. It cannot help with timing problems. */
4860 if (val & ATA_STAT_BUSY)
4861 {
4862#ifdef IN_RING3
4863 /* @bugref{1960}: Don't yield all the time, unless it's a reset (can be tricky). */
4864 bool fYield = (s->cBusyStatusHackR3++ & s->cBusyStatusHackR3Rate) == 0
4865 || pCtl->fReset;
4866
4867 ataR3LockLeave(pDevIns, pCtl);
4868
4869 /*
4870 * The thread might be stuck in an I/O operation due to a high I/O
4871 * load on the host (see @bugref{3301}). To perform the reset
4872 * successfully we interrupt the operation by sending a signal to
4873 * the thread if the thread didn't responded in 10ms.
4874 *
4875 * This works only on POSIX hosts (Windows has a CancelSynchronousIo
4876 * function which does the same but it was introduced with Vista) but
4877 * so far this hang was only observed on Linux and Mac OS X.
4878 *
4879 * This is a workaround and needs to be solved properly.
4880 */
4881 if (pCtl->fReset)
4882 {
4883 uint64_t u64ResetTimeStop = RTTimeMilliTS();
4884 if (u64ResetTimeStop - pCtl->u64ResetTime >= 10)
4885 {
4886 LogRel(("PIIX3 ATA LUN#%d: Async I/O thread probably stuck in operation, interrupting\n", s->iLUN));
4887 pCtl->u64ResetTime = u64ResetTimeStop;
4888# ifndef RT_OS_WINDOWS /* We've got this API on windows, but it doesn't necessarily interrupt I/O. */
4889 PATASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PATASTATER3);
4890 PATACONTROLLERR3 pCtlR3 = &RT_SAFE_SUBSCRIPT(pThisCC->aCts, pCtl->iCtl);
4891 RTThreadPoke(pCtlR3->hAsyncIOThread);
4892# endif
4893 Assert(fYield);
4894 }
4895 }
4896
4897 if (fYield)
4898 {
4899 STAM_REL_PROFILE_ADV_START(&s->StatStatusYields, a);
4900 RTThreadYield();
4901 STAM_REL_PROFILE_ADV_STOP(&s->StatStatusYields, a);
4902 }
4903 ASMNopPause();
4904
4905 ataR3LockEnter(pDevIns, pCtl);
4906
4907 val = s->uATARegStatus;
4908#else /* !IN_RING3 */
4909 /* Cannot yield CPU in raw-mode and ring-0 context. And switching
4910 * to host context for each and every busy status is too costly,
4911 * especially on SMP systems where we don't gain much by
4912 * yielding the CPU to someone else. */
4913 if ((s->cBusyStatusHackRZ++ & s->cBusyStatusHackRZRate) == 1)
4914 {
4915 s->cBusyStatusHackR3 = 0; /* Forces a yield. */
4916 return VINF_IOM_R3_IOPORT_READ;
4917 }
4918#endif /* !IN_RING3 */
4919 }
4920 else
4921 {
4922 s->cBusyStatusHackRZ = 0;
4923 s->cBusyStatusHackR3 = 0;
4924 }
4925 ataUnsetIRQ(pDevIns, pCtl, s);
4926 break;
4927 }
4928 }
4929 Log2(("%s: LUN#%d addr=%#x val=%#04x\n", __FUNCTION__, s->iLUN, addr, val));
4930 *pu32 = val;
4931 return VINF_SUCCESS;
4932}
4933
4934
4935/*
4936 * Read the Alternate status register. Does not affect interrupts.
4937 */
4938static uint32_t ataStatusRead(PATACONTROLLER pCtl, uint32_t uIoPortForLog)
4939{
4940 PATADEVSTATE s = &pCtl->aIfs[pCtl->iSelectedIf & ATA_SELECTED_IF_MASK];
4941 uint32_t val;
4942 RT_NOREF(uIoPortForLog);
4943
4944 Assert(pCtl->aIfs[0].fPresent || pCtl->aIfs[1].fPresent); /* Channel must not be empty. */
4945 if (pCtl->iSelectedIf == 1 && !s->fPresent)
4946 val = 0; /* Device 1 selected, Device 0 responding for it. */
4947 else
4948 val = s->uATARegStatus;
4949 Log2(("%s: LUN#%d read addr=%#x val=%#04x\n", __FUNCTION__, pCtl->aIfs[pCtl->iSelectedIf & ATA_SELECTED_IF_MASK].iLUN, uIoPortForLog, val));
4950 return val;
4951}
4952
4953static int ataControlWrite(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, uint32_t val, uint32_t uIoPortForLog)
4954{
4955 RT_NOREF(uIoPortForLog);
4956#ifndef IN_RING3
4957 if ((val ^ pCtl->aIfs[0].uATARegDevCtl) & ATA_DEVCTL_RESET)
4958 return VINF_IOM_R3_IOPORT_WRITE; /* The RESET stuff is too complicated for RC+R0. */
4959#endif /* !IN_RING3 */
4960
4961 Log2(("%s: LUN#%d write addr=%#x val=%#04x\n", __FUNCTION__, pCtl->aIfs[pCtl->iSelectedIf & ATA_SELECTED_IF_MASK].iLUN, uIoPortForLog, val));
4962 /* RESET is common for both drives attached to a controller. */
4963 if ( !(pCtl->aIfs[0].uATARegDevCtl & ATA_DEVCTL_RESET)
4964 && (val & ATA_DEVCTL_RESET))
4965 {
4966#ifdef IN_RING3
4967 /* Software RESET low to high */
4968 int32_t uCmdWait0 = -1;
4969 int32_t uCmdWait1 = -1;
4970 uint64_t uNow = RTTimeNanoTS();
4971 if (pCtl->aIfs[0].u64CmdTS)
4972 uCmdWait0 = (uNow - pCtl->aIfs[0].u64CmdTS) / 1000;
4973 if (pCtl->aIfs[1].u64CmdTS)
4974 uCmdWait1 = (uNow - pCtl->aIfs[1].u64CmdTS) / 1000;
4975 LogRel(("PIIX3 ATA: Ctl#%d: RESET, DevSel=%d AIOIf=%d CmdIf0=%#04x (%d usec ago) CmdIf1=%#04x (%d usec ago)\n",
4976 pCtl->iCtl, pCtl->iSelectedIf, pCtl->iAIOIf,
4977 pCtl->aIfs[0].uATARegCommand, uCmdWait0,
4978 pCtl->aIfs[1].uATARegCommand, uCmdWait1));
4979 pCtl->fReset = true;
4980 /* Everything must be done after the reset flag is set, otherwise
4981 * there are unavoidable races with the currently executing request
4982 * (which might just finish in the mean time). */
4983 pCtl->fChainedTransfer = false;
4984 for (uint32_t i = 0; i < RT_ELEMENTS(pCtl->aIfs); i++)
4985 {
4986 ataR3ResetDevice(pDevIns, pCtl, &pCtl->aIfs[i]);
4987 /* The following cannot be done using ataSetStatusValue() since the
4988 * reset flag is already set, which suppresses all status changes. */
4989 pCtl->aIfs[i].uATARegStatus = ATA_STAT_BUSY | ATA_STAT_SEEK;
4990 Log2(("%s: LUN#%d status %#04x\n", __FUNCTION__, pCtl->aIfs[i].iLUN, pCtl->aIfs[i].uATARegStatus));
4991 pCtl->aIfs[i].uATARegError = 0x01;
4992 }
4993 pCtl->iSelectedIf = 0;
4994 ataR3AsyncIOClearRequests(pDevIns, pCtl);
4995 Log2(("%s: Ctl#%d: message to async I/O thread, resetA\n", __FUNCTION__, pCtl->iCtl));
4996 if (val & ATA_DEVCTL_HOB)
4997 {
4998 val &= ~ATA_DEVCTL_HOB;
4999 Log2(("%s: ignored setting HOB\n", __FUNCTION__));
5000 }
5001
5002 /* Save the timestamp we started the reset. */
5003 pCtl->u64ResetTime = RTTimeMilliTS();
5004
5005 /* Issue the reset request now. */
5006 ataHCAsyncIOPutRequest(pDevIns, pCtl, &g_ataResetARequest);
5007#else /* !IN_RING3 */
5008 AssertMsgFailed(("RESET handling is too complicated for GC\n"));
5009#endif /* IN_RING3 */
5010 }
5011 else if ( (pCtl->aIfs[0].uATARegDevCtl & ATA_DEVCTL_RESET)
5012 && !(val & ATA_DEVCTL_RESET))
5013 {
5014#ifdef IN_RING3
5015 /* Software RESET high to low */
5016 Log(("%s: deasserting RESET\n", __FUNCTION__));
5017 Log2(("%s: Ctl#%d: message to async I/O thread, resetC\n", __FUNCTION__, pCtl->iCtl));
5018 if (val & ATA_DEVCTL_HOB)
5019 {
5020 val &= ~ATA_DEVCTL_HOB;
5021 Log2(("%s: ignored setting HOB\n", __FUNCTION__));
5022 }
5023 ataHCAsyncIOPutRequest(pDevIns, pCtl, &g_ataResetCRequest);
5024#else /* !IN_RING3 */
5025 AssertMsgFailed(("RESET handling is too complicated for GC\n"));
5026#endif /* IN_RING3 */
5027 }
5028
5029 /* Change of interrupt disable flag. Update interrupt line if interrupt
5030 * is pending on the current interface. */
5031 if ( ((val ^ pCtl->aIfs[0].uATARegDevCtl) & ATA_DEVCTL_DISABLE_IRQ)
5032 && pCtl->aIfs[pCtl->iSelectedIf & ATA_SELECTED_IF_MASK].fIrqPending)
5033 {
5034 if (!(val & ATA_DEVCTL_DISABLE_IRQ))
5035 {
5036 Log2(("%s: LUN#%d asserting IRQ (interrupt disable change)\n", __FUNCTION__, pCtl->aIfs[pCtl->iSelectedIf & ATA_SELECTED_IF_MASK].iLUN));
5037 /* The BMDMA unit unconditionally sets BM_STATUS_INT if the
5038 * interrupt line is asserted. It monitors the line for a rising
5039 * edge. */
5040 pCtl->BmDma.u8Status |= BM_STATUS_INT;
5041 if (pCtl->irq == 16)
5042 PDMDevHlpPCISetIrq(pDevIns, 0, 1);
5043 else
5044 PDMDevHlpISASetIrq(pDevIns, pCtl->irq, 1);
5045 }
5046 else
5047 {
5048 Log2(("%s: LUN#%d deasserting IRQ (interrupt disable change)\n", __FUNCTION__, pCtl->aIfs[pCtl->iSelectedIf & ATA_SELECTED_IF_MASK].iLUN));
5049 if (pCtl->irq == 16)
5050 PDMDevHlpPCISetIrq(pDevIns, 0, 0);
5051 else
5052 PDMDevHlpISASetIrq(pDevIns, pCtl->irq, 0);
5053 }
5054 }
5055
5056 if (val & ATA_DEVCTL_HOB)
5057 Log2(("%s: set HOB\n", __FUNCTION__));
5058
5059 pCtl->aIfs[0].uATARegDevCtl = val;
5060 pCtl->aIfs[1].uATARegDevCtl = val;
5061
5062 return VINF_SUCCESS;
5063}
5064
5065#if defined(IN_RING0) || defined(IN_RING3)
5066
5067static void ataHCPIOTransfer(PPDMDEVINS pDevIns, PATACONTROLLER pCtl)
5068{
5069 PATADEVSTATE s;
5070
5071 s = &pCtl->aIfs[pCtl->iAIOIf & ATA_SELECTED_IF_MASK];
5072 Log3(("%s: if=%p\n", __FUNCTION__, s));
5073
5074 if (s->cbTotalTransfer && s->iIOBufferCur > s->iIOBufferEnd)
5075 {
5076# ifdef IN_RING3
5077 LogRel(("PIIX3 ATA: LUN#%d: %s data in the middle of a PIO transfer - VERY SLOW\n",
5078 s->iLUN, s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE ? "loading" : "storing"));
5079 /* Any guest OS that triggers this case has a pathetic ATA driver.
5080 * In a real system it would block the CPU via IORDY, here we do it
5081 * very similarly by not continuing with the current instruction
5082 * until the transfer to/from the storage medium is completed. */
5083 uint8_t const iSourceSink = s->iSourceSink;
5084 if ( iSourceSink != ATAFN_SS_NULL
5085 && iSourceSink < RT_ELEMENTS(g_apfnSourceSinkFuncs))
5086 {
5087 bool fRedo;
5088 uint8_t status = s->uATARegStatus;
5089 PATASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PATASTATER3);
5090 PATADEVSTATER3 pDevR3 = &RT_SAFE_SUBSCRIPT(RT_SAFE_SUBSCRIPT(pThisCC->aCts, pCtl->iCtl).aIfs, s->iDev);
5091
5092 ataSetStatusValue(pCtl, s, ATA_STAT_BUSY);
5093 Log2(("%s: calling source/sink function\n", __FUNCTION__));
5094 fRedo = g_apfnSourceSinkFuncs[iSourceSink](pDevIns, pCtl, s, pDevR3);
5095 pCtl->fRedo = fRedo;
5096 if (RT_UNLIKELY(fRedo))
5097 return;
5098 ataSetStatusValue(pCtl, s, status);
5099 s->iIOBufferCur = 0;
5100 s->iIOBufferEnd = s->cbElementaryTransfer;
5101 }
5102 else
5103 Assert(iSourceSink == ATAFN_SS_NULL);
5104# else
5105 AssertReleaseFailed();
5106# endif
5107 }
5108 if (s->cbTotalTransfer)
5109 {
5110 if (s->fATAPITransfer)
5111 ataHCPIOTransferLimitATAPI(s);
5112
5113 if (s->uTxDir == PDMMEDIATXDIR_TO_DEVICE && s->cbElementaryTransfer > s->cbTotalTransfer)
5114 s->cbElementaryTransfer = s->cbTotalTransfer;
5115
5116 Log2(("%s: %s tx_size=%d elem_tx_size=%d index=%d end=%d\n",
5117 __FUNCTION__, s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE ? "T2I" : "I2T",
5118 s->cbTotalTransfer, s->cbElementaryTransfer,
5119 s->iIOBufferCur, s->iIOBufferEnd));
5120 ataHCPIOTransferStart(pCtl, s, s->iIOBufferCur, s->cbElementaryTransfer);
5121 s->cbTotalTransfer -= s->cbElementaryTransfer;
5122 s->iIOBufferCur += s->cbElementaryTransfer;
5123
5124 if (s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE && s->cbElementaryTransfer > s->cbTotalTransfer)
5125 s->cbElementaryTransfer = s->cbTotalTransfer;
5126 }
5127 else
5128 ataHCPIOTransferStop(pDevIns, pCtl, s);
5129}
5130
5131
5132DECLINLINE(void) ataHCPIOTransferFinish(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s)
5133{
5134 /* Do not interfere with RESET processing if the PIO transfer finishes
5135 * while the RESET line is asserted. */
5136 if (pCtl->fReset)
5137 {
5138 Log2(("%s: Ctl#%d: suppressed continuing PIO transfer as RESET is active\n", __FUNCTION__, pCtl->iCtl));
5139 return;
5140 }
5141
5142 if ( s->uTxDir == PDMMEDIATXDIR_TO_DEVICE
5143 || ( s->iSourceSink != ATAFN_SS_NULL
5144 && s->iIOBufferCur >= s->iIOBufferEnd))
5145 {
5146 /* Need to continue the transfer in the async I/O thread. This is
5147 * the case for write operations or generally for not yet finished
5148 * transfers (some data might need to be read). */
5149 ataSetStatus(pCtl, s, ATA_STAT_BUSY);
5150 ataUnsetStatus(pCtl, s, ATA_STAT_READY | ATA_STAT_DRQ);
5151
5152 Log2(("%s: Ctl#%d: message to async I/O thread, continuing PIO transfer\n", __FUNCTION__, pCtl->iCtl));
5153 ataHCAsyncIOPutRequest(pDevIns, pCtl, &g_ataPIORequest);
5154 }
5155 else
5156 {
5157 /* Either everything finished (though some data might still be pending)
5158 * or some data is pending before the next read is due. */
5159
5160 /* Continue a previously started transfer. */
5161 ataUnsetStatus(pCtl, s, ATA_STAT_DRQ);
5162 ataSetStatus(pCtl, s, ATA_STAT_READY);
5163
5164 if (s->cbTotalTransfer)
5165 {
5166 /* There is more to transfer, happens usually for large ATAPI
5167 * reads - the protocol limits the chunk size to 65534 bytes. */
5168 ataHCPIOTransfer(pDevIns, pCtl);
5169 ataHCSetIRQ(pDevIns, pCtl, s);
5170 }
5171 else
5172 {
5173 Log2(("%s: Ctl#%d: skipping message to async I/O thread, ending PIO transfer\n", __FUNCTION__, pCtl->iCtl));
5174 /* Finish PIO transfer. */
5175 ataHCPIOTransfer(pDevIns, pCtl);
5176 Assert(!pCtl->fRedo);
5177 }
5178 }
5179}
5180
5181#endif /* IN_RING0 || IN_RING3 */
5182
5183/**
5184 * Fallback for ataCopyPioData124 that handles unaligned and out of bounds cases.
5185 *
5186 * @param pIf The device interface to work with.
5187 * @param pbDst The destination buffer.
5188 * @param pbSrc The source buffer.
5189 * @param offStart The start offset (iIOBufferPIODataStart).
5190 * @param cbCopy The number of bytes to copy, either 1, 2 or 4 bytes.
5191 */
5192DECL_NO_INLINE(static, void) ataCopyPioData124Slow(PATADEVSTATE pIf, uint8_t *pbDst, const uint8_t *pbSrc,
5193 uint32_t offStart, uint32_t cbCopy)
5194{
5195 uint32_t const offNext = offStart + cbCopy;
5196 uint32_t const cbIOBuffer = RT_MIN(pIf->cbIOBuffer, ATA_MAX_IO_BUFFER_SIZE);
5197
5198 if (offStart + cbCopy > cbIOBuffer)
5199 {
5200 Log(("%s: cbCopy=%#x offStart=%#x cbIOBuffer=%#x offNext=%#x (iIOBufferPIODataEnd=%#x)\n",
5201 __FUNCTION__, cbCopy, offStart, cbIOBuffer, offNext, pIf->iIOBufferPIODataEnd));
5202 if (offStart < cbIOBuffer)
5203 cbCopy = cbIOBuffer - offStart;
5204 else
5205 cbCopy = 0;
5206 }
5207
5208 switch (cbCopy)
5209 {
5210 case 4: pbDst[3] = pbSrc[3]; RT_FALL_THRU();
5211 case 3: pbDst[2] = pbSrc[2]; RT_FALL_THRU();
5212 case 2: pbDst[1] = pbSrc[1]; RT_FALL_THRU();
5213 case 1: pbDst[0] = pbSrc[0]; RT_FALL_THRU();
5214 case 0: break;
5215 default: AssertFailed(); /* impossible */
5216 }
5217
5218 pIf->iIOBufferPIODataStart = offNext;
5219
5220}
5221
5222
5223/**
5224 * Work for ataDataWrite & ataDataRead that copies data without using memcpy.
5225 *
5226 * This also updates pIf->iIOBufferPIODataStart.
5227 *
5228 * The two buffers are either stack (32-bit aligned) or somewhere within
5229 * pIf->abIOBuffer.
5230 *
5231 * @param pIf The device interface to work with.
5232 * @param pbDst The destination buffer.
5233 * @param pbSrc The source buffer.
5234 * @param offStart The start offset (iIOBufferPIODataStart).
5235 * @param cbCopy The number of bytes to copy, either 1, 2 or 4 bytes.
5236 */
5237DECLINLINE(void) ataCopyPioData124(PATADEVSTATE pIf, uint8_t *pbDst, const uint8_t *pbSrc, uint32_t offStart, uint32_t cbCopy)
5238{
5239 /*
5240 * Quick bounds checking can be done by checking that the abIOBuffer offset
5241 * (iIOBufferPIODataStart) is aligned at the transfer size (which is ASSUMED
5242 * to be 1, 2 or 4). However, since we're paranoid and don't currently
5243 * trust iIOBufferPIODataEnd to be within bounds, we current check against the
5244 * IO buffer size too.
5245 */
5246 Assert(cbCopy == 1 || cbCopy == 2 || cbCopy == 4);
5247 if (RT_LIKELY( !(offStart & (cbCopy - 1))
5248 && offStart + cbCopy <= RT_MIN(pIf->cbIOBuffer, ATA_MAX_IO_BUFFER_SIZE)))
5249 {
5250 switch (cbCopy)
5251 {
5252 case 4: *(uint32_t *)pbDst = *(uint32_t const *)pbSrc; break;
5253 case 2: *(uint16_t *)pbDst = *(uint16_t const *)pbSrc; break;
5254 case 1: *pbDst = *pbSrc; break;
5255 }
5256 pIf->iIOBufferPIODataStart = offStart + cbCopy;
5257 }
5258 else
5259 ataCopyPioData124Slow(pIf, pbDst, pbSrc, offStart, cbCopy);
5260}
5261
5262
5263/**
5264 * @callback_method_impl{FNIOMIOPORTNEWOUT,
5265 * Port I/O Handler for primary port range OUT operations.}
5266 * @note offPort is an absolute port number!
5267 */
5268static DECLCALLBACK(VBOXSTRICTRC)
5269ataIOPortWrite1Data(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
5270{
5271 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE);
5272 PATACONTROLLER pCtl = &RT_SAFE_SUBSCRIPT(pThis->aCts, (uintptr_t)pvUser);
5273 RT_NOREF(offPort);
5274
5275 Assert((uintptr_t)pvUser < 2);
5276 Assert(offPort == pCtl->IOPortBase1);
5277 Assert(cb == 2 || cb == 4); /* Writes to the data port may be 16-bit or 32-bit. */
5278
5279 VBOXSTRICTRC rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->lock, VINF_IOM_R3_IOPORT_WRITE);
5280 if (rc == VINF_SUCCESS)
5281 {
5282 PATADEVSTATE s = &pCtl->aIfs[pCtl->iSelectedIf & ATA_SELECTED_IF_MASK];
5283 uint32_t const iIOBufferPIODataStart = RT_MIN(s->iIOBufferPIODataStart, sizeof(s->abIOBuffer));
5284 uint32_t const iIOBufferPIODataEnd = RT_MIN(s->iIOBufferPIODataEnd, sizeof(s->abIOBuffer));
5285
5286 if (iIOBufferPIODataStart < iIOBufferPIODataEnd)
5287 {
5288 Assert(s->uTxDir == PDMMEDIATXDIR_TO_DEVICE);
5289 uint8_t *pbDst = &s->abIOBuffer[iIOBufferPIODataStart];
5290 uint8_t const *pbSrc = (uint8_t const *)&u32;
5291
5292#ifdef IN_RC
5293 /* Raw-mode: The ataHCPIOTransfer following the last transfer unit
5294 requires I/O thread signalling, we must go to ring-3 for that. */
5295 if (iIOBufferPIODataStart + cb < iIOBufferPIODataEnd)
5296 ataCopyPioData124(s, pbDst, pbSrc, iIOBufferPIODataStart, cb);
5297 else
5298 rc = VINF_IOM_R3_IOPORT_WRITE;
5299
5300#elif defined(IN_RING0)
5301 /* Ring-0: We can do I/O thread signalling here, however for paranoid reasons
5302 triggered by a special case in ataHCPIOTransferFinish, we take extra care here. */
5303 if (iIOBufferPIODataStart + cb < iIOBufferPIODataEnd)
5304 ataCopyPioData124(s, pbDst, pbSrc, iIOBufferPIODataStart, cb);
5305 else if (s->uTxDir == PDMMEDIATXDIR_TO_DEVICE) /* paranoia */
5306 {
5307 ataCopyPioData124(s, pbDst, pbSrc, iIOBufferPIODataStart, cb);
5308 ataHCPIOTransferFinish(pDevIns, pCtl, s);
5309 }
5310 else
5311 {
5312 Log(("%s: Unexpected\n", __FUNCTION__));
5313 rc = VINF_IOM_R3_IOPORT_WRITE;
5314 }
5315
5316#else /* IN_RING 3*/
5317 ataCopyPioData124(s, pbDst, pbSrc, iIOBufferPIODataStart, cb);
5318 if (s->iIOBufferPIODataStart >= iIOBufferPIODataEnd)
5319 ataHCPIOTransferFinish(pDevIns, pCtl, s);
5320#endif /* IN_RING 3*/
5321 }
5322 else
5323 Log2(("%s: DUMMY data\n", __FUNCTION__));
5324
5325 Log3(("%s: addr=%#x val=%.*Rhxs rc=%d\n", __FUNCTION__, offPort + pCtl->IOPortBase1, cb, &u32, VBOXSTRICTRC_VAL(rc)));
5326 PDMDevHlpCritSectLeave(pDevIns, &pCtl->lock);
5327 }
5328 else
5329 Log3(("%s: addr=%#x -> %d\n", __FUNCTION__, offPort + pCtl->IOPortBase1, VBOXSTRICTRC_VAL(rc)));
5330 return rc;
5331}
5332
5333
5334/**
5335 * @callback_method_impl{FNIOMIOPORTNEWIN,
5336 * Port I/O Handler for primary port range IN operations.}
5337 * @note offPort is an absolute port number!
5338 */
5339static DECLCALLBACK(VBOXSTRICTRC)
5340ataIOPortRead1Data(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
5341{
5342 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE);
5343 PATACONTROLLER pCtl = &RT_SAFE_SUBSCRIPT(pThis->aCts, (uintptr_t)pvUser);
5344 RT_NOREF(offPort);
5345
5346 Assert((uintptr_t)pvUser < 2);
5347 Assert(offPort == pCtl->IOPortBase1);
5348
5349 /* Reads from the data register may be 16-bit or 32-bit. Byte accesses are
5350 upgraded to word. */
5351 Assert(cb == 1 || cb == 2 || cb == 4);
5352 uint32_t cbActual = cb != 1 ? cb : 2;
5353 *pu32 = 0;
5354
5355 VBOXSTRICTRC rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->lock, VINF_IOM_R3_IOPORT_READ);
5356 if (rc == VINF_SUCCESS)
5357 {
5358 PATADEVSTATE s = &pCtl->aIfs[pCtl->iSelectedIf & ATA_SELECTED_IF_MASK];
5359
5360 if (s->iIOBufferPIODataStart < s->iIOBufferPIODataEnd)
5361 {
5362 AssertMsg(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE, ("%#x\n", s->uTxDir));
5363 uint32_t const iIOBufferPIODataStart = RT_MIN(s->iIOBufferPIODataStart, sizeof(s->abIOBuffer));
5364 uint32_t const iIOBufferPIODataEnd = RT_MIN(s->iIOBufferPIODataEnd, sizeof(s->abIOBuffer));
5365 uint8_t const *pbSrc = &s->abIOBuffer[iIOBufferPIODataStart];
5366 uint8_t *pbDst = (uint8_t *)pu32;
5367
5368#ifdef IN_RC
5369 /* All but the last transfer unit is simple enough for RC, but
5370 * sending a request to the async IO thread is too complicated. */
5371 if (iIOBufferPIODataStart + cbActual < iIOBufferPIODataEnd)
5372 ataCopyPioData124(s, pbDst, pbSrc, iIOBufferPIODataStart, cbActual);
5373 else
5374 rc = VINF_IOM_R3_IOPORT_READ;
5375
5376#elif defined(IN_RING0)
5377 /* Ring-0: We can do I/O thread signalling here. However there is one
5378 case in ataHCPIOTransfer that does a LogRel and would (but not from
5379 here) call directly into the driver code. We detect that odd case
5380 here cand return to ring-3 to handle it. */
5381 if (iIOBufferPIODataStart + cbActual < iIOBufferPIODataEnd)
5382 ataCopyPioData124(s, pbDst, pbSrc, iIOBufferPIODataStart, cbActual);
5383 else if ( s->cbTotalTransfer == 0
5384 || s->iSourceSink != ATAFN_SS_NULL
5385 || s->iIOBufferCur <= s->iIOBufferEnd)
5386 {
5387 ataCopyPioData124(s, pbDst, pbSrc, iIOBufferPIODataStart, cbActual);
5388 ataHCPIOTransferFinish(pDevIns, pCtl, s);
5389 }
5390 else
5391 {
5392 Log(("%s: Unexpected\n",__FUNCTION__));
5393 rc = VINF_IOM_R3_IOPORT_READ;
5394 }
5395
5396#else /* IN_RING3 */
5397 ataCopyPioData124(s, pbDst, pbSrc, iIOBufferPIODataStart, cbActual);
5398 if (s->iIOBufferPIODataStart >= iIOBufferPIODataEnd)
5399 ataHCPIOTransferFinish(pDevIns, pCtl, s);
5400#endif /* IN_RING3 */
5401
5402 /* Just to be on the safe side (caller takes care of this, really). */
5403 if (cb == 1)
5404 *pu32 &= 0xff;
5405 }
5406 else
5407 {
5408 Log2(("%s: DUMMY data\n", __FUNCTION__));
5409 memset(pu32, 0xff, cb);
5410 }
5411 Log3(("%s: addr=%#x val=%.*Rhxs rc=%d\n", __FUNCTION__, offPort, cb, pu32, VBOXSTRICTRC_VAL(rc)));
5412
5413 PDMDevHlpCritSectLeave(pDevIns, &pCtl->lock);
5414 }
5415 else
5416 Log3(("%s: addr=%#x -> %d\n", __FUNCTION__, offPort, VBOXSTRICTRC_VAL(rc)));
5417
5418 return rc;
5419}
5420
5421
5422/**
5423 * @callback_method_impl{FNIOMIOPORTNEWINSTRING,
5424 * Port I/O Handler for primary port range IN string operations.}
5425 * @note offPort is an absolute port number!
5426 */
5427static DECLCALLBACK(VBOXSTRICTRC)
5428ataIOPortReadStr1Data(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint8_t *pbDst, uint32_t *pcTransfers, unsigned cb)
5429{
5430 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE);
5431 PATACONTROLLER pCtl = &RT_SAFE_SUBSCRIPT(pThis->aCts, (uintptr_t)pvUser);
5432 RT_NOREF(offPort);
5433
5434 Assert((uintptr_t)pvUser < 2);
5435 Assert(offPort == pCtl->IOPortBase1);
5436 Assert(*pcTransfers > 0);
5437
5438 VBOXSTRICTRC rc;
5439 if (cb == 2 || cb == 4)
5440 {
5441 rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->lock, VINF_IOM_R3_IOPORT_READ);
5442 if (rc == VINF_SUCCESS)
5443 {
5444 PATADEVSTATE s = &pCtl->aIfs[pCtl->iSelectedIf & ATA_SELECTED_IF_MASK];
5445
5446 uint32_t const offStart = s->iIOBufferPIODataStart;
5447 uint32_t const offEnd = s->iIOBufferPIODataEnd;
5448 if (offStart < offEnd)
5449 {
5450 /*
5451 * Figure how much we can copy. Usually it's the same as the request.
5452 * The last transfer unit cannot be handled in RC, as it involves
5453 * thread communication. In R0 we let the non-string callback handle it,
5454 * and ditto for overflows/dummy data.
5455 */
5456 uint32_t cAvailable = (offEnd - offStart) / cb;
5457#ifndef IN_RING3
5458 if (cAvailable > 0)
5459 cAvailable--;
5460#endif
5461 uint32_t const cRequested = *pcTransfers;
5462 if (cAvailable > cRequested)
5463 cAvailable = cRequested;
5464 uint32_t const cbTransfer = cAvailable * cb;
5465 uint32_t const offEndThisXfer = offStart + cbTransfer;
5466 if ( offEndThisXfer <= RT_MIN(s->cbIOBuffer, ATA_MAX_IO_BUFFER_SIZE)
5467 && offStart < RT_MIN(s->cbIOBuffer, ATA_MAX_IO_BUFFER_SIZE) /* paranoia */
5468 && cbTransfer > 0)
5469 {
5470 /*
5471 * Do the transfer.
5472 */
5473 uint8_t const *pbSrc = &s->abIOBuffer[offStart];
5474 memcpy(pbDst, pbSrc, cbTransfer);
5475 Log3(("%s: addr=%#x cb=%#x cbTransfer=%#x val=%.*Rhxd\n",
5476 __FUNCTION__, offPort, cb, cbTransfer, cbTransfer, pbSrc));
5477 s->iIOBufferPIODataStart = offEndThisXfer;
5478#ifdef IN_RING3
5479 if (offEndThisXfer >= offEnd)
5480 ataHCPIOTransferFinish(pDevIns, pCtl, s);
5481#endif
5482 *pcTransfers = cRequested - cAvailable;
5483 }
5484 else
5485 Log2(("ataIOPortReadStr1Data: DUMMY/Overflow!\n"));
5486 }
5487 else
5488 {
5489 /*
5490 * Dummy read (shouldn't happen) return 0xff like the non-string handler.
5491 */
5492 Log2(("ataIOPortReadStr1Data: DUMMY data (%#x bytes)\n", *pcTransfers * cb));
5493 memset(pbDst, 0xff, *pcTransfers * cb);
5494 *pcTransfers = 0;
5495 }
5496
5497 PDMDevHlpCritSectLeave(pDevIns, &pCtl->lock);
5498 }
5499 }
5500 /*
5501 * Let the non-string I/O callback handle 1 byte reads.
5502 */
5503 else
5504 {
5505 Log2(("ataIOPortReadStr1Data: 1 byte read (%#x transfers)\n", *pcTransfers));
5506 AssertFailed();
5507 rc = VINF_SUCCESS;
5508 }
5509 return rc;
5510}
5511
5512
5513/**
5514 * @callback_method_impl{FNIOMIOPORTNEWOUTSTRING,
5515 * Port I/O Handler for primary port range OUT string operations.}
5516 * @note offPort is an absolute port number!
5517 */
5518static DECLCALLBACK(VBOXSTRICTRC)
5519ataIOPortWriteStr1Data(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint8_t const *pbSrc, uint32_t *pcTransfers, unsigned cb)
5520{
5521 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE);
5522 PATACONTROLLER pCtl = &RT_SAFE_SUBSCRIPT(pThis->aCts, (uintptr_t)pvUser);
5523 RT_NOREF(offPort);
5524
5525 Assert((uintptr_t)pvUser < 2);
5526 Assert(offPort == pCtl->IOPortBase1);
5527 Assert(*pcTransfers > 0);
5528
5529 VBOXSTRICTRC rc;
5530 if (cb == 2 || cb == 4)
5531 {
5532 rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->lock, VINF_IOM_R3_IOPORT_WRITE);
5533 if (rc == VINF_SUCCESS)
5534 {
5535 PATADEVSTATE s = &pCtl->aIfs[pCtl->iSelectedIf & ATA_SELECTED_IF_MASK];
5536
5537 uint32_t const offStart = s->iIOBufferPIODataStart;
5538 uint32_t const offEnd = s->iIOBufferPIODataEnd;
5539 if (offStart < offEnd)
5540 {
5541 /*
5542 * Figure how much we can copy. Usually it's the same as the request.
5543 * The last transfer unit cannot be handled in RC, as it involves
5544 * thread communication. In R0 we let the non-string callback handle it,
5545 * and ditto for overflows/dummy data.
5546 */
5547 uint32_t cAvailable = (offEnd - offStart) / cb;
5548#ifndef IN_RING3
5549 if (cAvailable)
5550 cAvailable--;
5551#endif
5552 uint32_t const cRequested = *pcTransfers;
5553 if (cAvailable > cRequested)
5554 cAvailable = cRequested;
5555 uint32_t const cbTransfer = cAvailable * cb;
5556 uint32_t const offEndThisXfer = offStart + cbTransfer;
5557 if ( offEndThisXfer <= RT_MIN(s->cbIOBuffer, ATA_MAX_IO_BUFFER_SIZE)
5558 && offStart < RT_MIN(s->cbIOBuffer, ATA_MAX_IO_BUFFER_SIZE) /* paranoia */
5559 && cbTransfer > 0)
5560 {
5561 /*
5562 * Do the transfer.
5563 */
5564 void *pvDst = &s->abIOBuffer[offStart];
5565 memcpy(pvDst, pbSrc, cbTransfer);
5566 Log3(("%s: addr=%#x val=%.*Rhxs\n", __FUNCTION__, offPort + pCtl->IOPortBase1, cbTransfer, pvDst));
5567 s->iIOBufferPIODataStart = offEndThisXfer;
5568#ifdef IN_RING3
5569 if (offEndThisXfer >= offEnd)
5570 ataHCPIOTransferFinish(pDevIns, pCtl, s);
5571#endif
5572 *pcTransfers = cRequested - cAvailable;
5573 }
5574 else
5575 Log2(("ataIOPortWriteStr1Data: DUMMY/Overflow!\n"));
5576 }
5577 else
5578 {
5579 Log2(("ataIOPortWriteStr1Data: DUMMY data (%#x bytes)\n", *pcTransfers * cb));
5580 *pcTransfers = 0;
5581 }
5582
5583 PDMDevHlpCritSectLeave(pDevIns, &pCtl->lock);
5584 }
5585 }
5586 /*
5587 * Let the non-string I/O callback handle 1 byte reads.
5588 */
5589 else
5590 {
5591 Log2(("ataIOPortWriteStr1Data: 1 byte write (%#x transfers)\n", *pcTransfers));
5592 AssertFailed();
5593 rc = VINF_SUCCESS;
5594 }
5595
5596 return rc;
5597}
5598
5599
5600#ifdef IN_RING3
5601
5602static void ataR3DMATransferStop(PATADEVSTATE s)
5603{
5604 s->cbTotalTransfer = 0;
5605 s->cbElementaryTransfer = 0;
5606 s->iBeginTransfer = ATAFN_BT_NULL;
5607 s->iSourceSink = ATAFN_SS_NULL;
5608}
5609
5610
5611/**
5612 * Perform the entire DMA transfer in one go (unless a source/sink operation
5613 * has to be redone or a RESET comes in between). Unlike the PIO counterpart
5614 * this function cannot handle empty transfers.
5615 *
5616 * @param pDevIns The device instance.
5617 * @param pCtl Controller for which to perform the transfer, shared bits.
5618 * @param pCtlR3 The ring-3 controller state.
5619 */
5620static void ataR3DMATransfer(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATACONTROLLERR3 pCtlR3)
5621{
5622 uint8_t const iAIOIf = pCtl->iAIOIf & ATA_SELECTED_IF_MASK;
5623 PATADEVSTATE s = &pCtl->aIfs[iAIOIf];
5624 PATADEVSTATER3 pDevR3 = &pCtlR3->aIfs[iAIOIf];
5625 bool fRedo;
5626 RTGCPHYS32 GCPhysDesc;
5627 uint32_t cbTotalTransfer, cbElementaryTransfer;
5628 uint32_t iIOBufferCur, iIOBufferEnd;
5629 PDMMEDIATXDIR uTxDir;
5630 bool fLastDesc = false;
5631
5632 Assert(sizeof(BMDMADesc) == 8);
5633
5634 fRedo = pCtl->fRedo;
5635 if (RT_LIKELY(!fRedo))
5636 Assert(s->cbTotalTransfer);
5637 uTxDir = (PDMMEDIATXDIR)s->uTxDir;
5638 cbTotalTransfer = s->cbTotalTransfer;
5639 cbElementaryTransfer = RT_MIN(s->cbElementaryTransfer, sizeof(s->abIOBuffer));
5640 iIOBufferEnd = RT_MIN(s->iIOBufferEnd, sizeof(s->abIOBuffer));
5641 iIOBufferCur = RT_MIN(RT_MIN(s->iIOBufferCur, sizeof(s->abIOBuffer)), iIOBufferEnd);
5642
5643 /* The DMA loop is designed to hold the lock only when absolutely
5644 * necessary. This avoids long freezes should the guest access the
5645 * ATA registers etc. for some reason. */
5646 ataR3LockLeave(pDevIns, pCtl);
5647
5648 Log2(("%s: %s tx_size=%d elem_tx_size=%d index=%d end=%d\n",
5649 __FUNCTION__, uTxDir == PDMMEDIATXDIR_FROM_DEVICE ? "T2I" : "I2T",
5650 cbTotalTransfer, cbElementaryTransfer,
5651 iIOBufferCur, iIOBufferEnd));
5652 for (GCPhysDesc = pCtl->GCPhysFirstDMADesc;
5653 GCPhysDesc <= pCtl->GCPhysLastDMADesc;
5654 GCPhysDesc += sizeof(BMDMADesc))
5655 {
5656 BMDMADesc DMADesc;
5657 RTGCPHYS32 GCPhysBuffer;
5658 uint32_t cbBuffer;
5659
5660 if (RT_UNLIKELY(fRedo))
5661 {
5662 GCPhysBuffer = pCtl->GCPhysRedoDMABuffer;
5663 cbBuffer = pCtl->cbRedoDMABuffer;
5664 fLastDesc = pCtl->fRedoDMALastDesc;
5665 DMADesc.GCPhysBuffer = DMADesc.cbBuffer = 0; /* Shut up MSC. */
5666 }
5667 else
5668 {
5669 PDMDevHlpPCIPhysReadMeta(pDevIns, GCPhysDesc, &DMADesc, sizeof(BMDMADesc));
5670 GCPhysBuffer = RT_LE2H_U32(DMADesc.GCPhysBuffer);
5671 cbBuffer = RT_LE2H_U32(DMADesc.cbBuffer);
5672 fLastDesc = RT_BOOL(cbBuffer & UINT32_C(0x80000000));
5673 cbBuffer &= 0xfffe;
5674 if (cbBuffer == 0)
5675 cbBuffer = 0x10000;
5676 if (cbBuffer > cbTotalTransfer)
5677 cbBuffer = cbTotalTransfer;
5678 }
5679
5680 while (RT_UNLIKELY(fRedo) || (cbBuffer && cbTotalTransfer))
5681 {
5682 if (RT_LIKELY(!fRedo))
5683 {
5684 uint32_t cbXfer = RT_MIN(RT_MIN(cbBuffer, iIOBufferEnd - iIOBufferCur),
5685 sizeof(s->abIOBuffer) - RT_MIN(iIOBufferCur, sizeof(s->abIOBuffer)));
5686 Log2(("%s: DMA desc %#010x: addr=%#010x size=%#010x orig_size=%#010x\n", __FUNCTION__,
5687 (int)GCPhysDesc, GCPhysBuffer, cbBuffer, RT_LE2H_U32(DMADesc.cbBuffer) & 0xfffe));
5688
5689 if (uTxDir == PDMMEDIATXDIR_FROM_DEVICE)
5690 PDMDevHlpPCIPhysWriteUser(pDevIns, GCPhysBuffer, &s->abIOBuffer[iIOBufferCur], cbXfer);
5691 else
5692 PDMDevHlpPCIPhysReadUser(pDevIns, GCPhysBuffer, &s->abIOBuffer[iIOBufferCur], cbXfer);
5693
5694 iIOBufferCur += cbXfer;
5695 cbTotalTransfer -= cbXfer;
5696 cbBuffer -= cbXfer;
5697 GCPhysBuffer += cbXfer;
5698 }
5699 if ( iIOBufferCur == iIOBufferEnd
5700 && (uTxDir == PDMMEDIATXDIR_TO_DEVICE || cbTotalTransfer))
5701 {
5702 if (uTxDir == PDMMEDIATXDIR_FROM_DEVICE && cbElementaryTransfer > cbTotalTransfer)
5703 cbElementaryTransfer = cbTotalTransfer;
5704
5705 ataR3LockEnter(pDevIns, pCtl);
5706
5707 /* The RESET handler could have cleared the DMA transfer
5708 * state (since we didn't hold the lock until just now
5709 * the guest can continue in parallel). If so, the state
5710 * is already set up so the loop is exited immediately. */
5711 uint8_t const iSourceSink = s->iSourceSink;
5712 if ( iSourceSink != ATAFN_SS_NULL
5713 && iSourceSink < RT_ELEMENTS(g_apfnSourceSinkFuncs))
5714 {
5715 s->iIOBufferCur = iIOBufferCur;
5716 s->iIOBufferEnd = iIOBufferEnd;
5717 s->cbElementaryTransfer = cbElementaryTransfer;
5718 s->cbTotalTransfer = cbTotalTransfer;
5719 Log2(("%s: calling source/sink function\n", __FUNCTION__));
5720 fRedo = g_apfnSourceSinkFuncs[iSourceSink](pDevIns, pCtl, s, pDevR3);
5721 if (RT_UNLIKELY(fRedo))
5722 {
5723 pCtl->GCPhysFirstDMADesc = GCPhysDesc;
5724 pCtl->GCPhysRedoDMABuffer = GCPhysBuffer;
5725 pCtl->cbRedoDMABuffer = cbBuffer;
5726 pCtl->fRedoDMALastDesc = fLastDesc;
5727 }
5728 else
5729 {
5730 cbTotalTransfer = s->cbTotalTransfer;
5731 cbElementaryTransfer = s->cbElementaryTransfer;
5732
5733 if (uTxDir == PDMMEDIATXDIR_TO_DEVICE && cbElementaryTransfer > cbTotalTransfer)
5734 cbElementaryTransfer = cbTotalTransfer;
5735 iIOBufferCur = 0;
5736 iIOBufferEnd = RT_MIN(cbElementaryTransfer, sizeof(s->abIOBuffer));
5737 }
5738 pCtl->fRedo = fRedo;
5739 }
5740 else
5741 {
5742 /* This forces the loop to exit immediately. */
5743 Assert(iSourceSink == ATAFN_SS_NULL);
5744 GCPhysDesc = pCtl->GCPhysLastDMADesc + 1;
5745 }
5746
5747 ataR3LockLeave(pDevIns, pCtl);
5748 if (RT_UNLIKELY(fRedo))
5749 break;
5750 }
5751 }
5752
5753 if (RT_UNLIKELY(fRedo))
5754 break;
5755
5756 /* end of transfer */
5757 if (!cbTotalTransfer || fLastDesc)
5758 break;
5759
5760 ataR3LockEnter(pDevIns, pCtl);
5761
5762 if (!(pCtl->BmDma.u8Cmd & BM_CMD_START) || pCtl->fReset)
5763 {
5764 LogRel(("PIIX3 ATA: Ctl#%d: ABORT DMA%s\n", pCtl->iCtl, pCtl->fReset ? " due to RESET" : ""));
5765 if (!pCtl->fReset)
5766 ataR3DMATransferStop(s);
5767 /* This forces the loop to exit immediately. */
5768 GCPhysDesc = pCtl->GCPhysLastDMADesc + 1;
5769 }
5770
5771 ataR3LockLeave(pDevIns, pCtl);
5772 }
5773
5774 ataR3LockEnter(pDevIns, pCtl);
5775 if (RT_UNLIKELY(fRedo))
5776 return;
5777
5778 if (fLastDesc)
5779 pCtl->BmDma.u8Status &= ~BM_STATUS_DMAING;
5780 s->cbTotalTransfer = cbTotalTransfer;
5781 s->cbElementaryTransfer = cbElementaryTransfer;
5782 s->iIOBufferCur = iIOBufferCur;
5783 s->iIOBufferEnd = iIOBufferEnd;
5784}
5785
5786/**
5787 * Signal PDM that we're idle (if we actually are).
5788 *
5789 * @param pDevIns The device instance.
5790 * @param pCtl The shared controller state.
5791 * @param pCtlR3 The ring-3 controller state.
5792 */
5793static void ataR3AsyncSignalIdle(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATACONTROLLERR3 pCtlR3)
5794{
5795 /*
5796 * Take the lock here and recheck the idle indicator to avoid
5797 * unnecessary work and racing ataR3WaitForAsyncIOIsIdle.
5798 */
5799 int rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->AsyncIORequestLock, VINF_SUCCESS);
5800 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pCtl->AsyncIORequestLock, rc);
5801
5802 if ( pCtlR3->fSignalIdle
5803 && ataR3AsyncIOIsIdle(pDevIns, pCtl, false /*fStrict*/))
5804 {
5805 PDMDevHlpAsyncNotificationCompleted(pDevIns);
5806 RTThreadUserSignal(pCtlR3->hAsyncIOThread); /* for ataR3Construct/ataR3ResetCommon. */
5807 }
5808
5809 rc = PDMDevHlpCritSectLeave(pDevIns, &pCtl->AsyncIORequestLock);
5810 AssertRC(rc);
5811}
5812
5813/**
5814 * Async I/O thread for an interface.
5815 *
5816 * Once upon a time this was readable code with several loops and a different
5817 * semaphore for each purpose. But then came the "how can one save the state in
5818 * the middle of a PIO transfer" question. The solution was to use an ASM,
5819 * which is what's there now.
5820 */
5821static DECLCALLBACK(int) ataR3AsyncIOThread(RTTHREAD hThreadSelf, void *pvUser)
5822{
5823 PATACONTROLLERR3 const pCtlR3 = (PATACONTROLLERR3)pvUser;
5824 PPDMDEVINSR3 const pDevIns = pCtlR3->pDevIns;
5825 PATASTATE const pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE);
5826 PATASTATER3 const pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PATASTATER3);
5827 uintptr_t const iCtl = pCtlR3 - &pThisCC->aCts[0];
5828 PATACONTROLLER const pCtl = &RT_SAFE_SUBSCRIPT(pThis->aCts, iCtl);
5829 int rc = VINF_SUCCESS;
5830 uint64_t u64TS = 0; /* shut up gcc */
5831 uint64_t uWait;
5832 const ATARequest *pReq;
5833 RT_NOREF(hThreadSelf);
5834 Assert(pCtl->iCtl == pCtlR3->iCtl);
5835
5836 pReq = NULL;
5837 pCtl->fChainedTransfer = false;
5838 while (!pCtlR3->fShutdown)
5839 {
5840 /* Keep this thread from doing anything as long as EMT is suspended. */
5841 while (pCtl->fRedoIdle)
5842 {
5843 if (pCtlR3->fSignalIdle)
5844 ataR3AsyncSignalIdle(pDevIns, pCtl, pCtlR3);
5845 rc = RTSemEventWait(pCtlR3->hSuspendIOSem, RT_INDEFINITE_WAIT);
5846 /* Continue if we got a signal by RTThreadPoke().
5847 * We will get notified if there is a request to process.
5848 */
5849 if (RT_UNLIKELY(rc == VERR_INTERRUPTED))
5850 continue;
5851 if (RT_FAILURE(rc) || pCtlR3->fShutdown)
5852 break;
5853
5854 pCtl->fRedoIdle = false;
5855 }
5856
5857 /* Wait for work. */
5858 while (pReq == NULL)
5859 {
5860 if (pCtlR3->fSignalIdle)
5861 ataR3AsyncSignalIdle(pDevIns, pCtl, pCtlR3);
5862 rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pCtl->hAsyncIOSem, RT_INDEFINITE_WAIT);
5863 /* Continue if we got a signal by RTThreadPoke().
5864 * We will get notified if there is a request to process.
5865 */
5866 if (RT_UNLIKELY(rc == VERR_INTERRUPTED))
5867 continue;
5868 if (RT_FAILURE(rc) || RT_UNLIKELY(pCtlR3->fShutdown))
5869 break;
5870
5871 pReq = ataR3AsyncIOGetCurrentRequest(pDevIns, pCtl);
5872 }
5873
5874 if (RT_FAILURE(rc) || pCtlR3->fShutdown)
5875 break;
5876
5877 if (pReq == NULL)
5878 continue;
5879
5880 ATAAIO ReqType = pReq->ReqType;
5881
5882 Log2(("%s: Ctl#%d: state=%d, req=%d\n", __FUNCTION__, pCtl->iCtl, pCtl->uAsyncIOState, ReqType));
5883 if (pCtl->uAsyncIOState != ReqType)
5884 {
5885 /* The new state is not the state that was expected by the normal
5886 * state changes. This is either a RESET/ABORT or there's something
5887 * really strange going on. */
5888 if ( (pCtl->uAsyncIOState == ATA_AIO_PIO || pCtl->uAsyncIOState == ATA_AIO_DMA)
5889 && (ReqType == ATA_AIO_PIO || ReqType == ATA_AIO_DMA))
5890 {
5891 /* Incorrect sequence of PIO/DMA states. Dump request queue. */
5892 ataR3AsyncIODumpRequests(pDevIns, pCtl);
5893 }
5894 AssertReleaseMsg( ReqType == ATA_AIO_RESET_ASSERTED
5895 || ReqType == ATA_AIO_RESET_CLEARED
5896 || ReqType == ATA_AIO_ABORT
5897 || pCtl->uAsyncIOState == ReqType,
5898 ("I/O state inconsistent: state=%d request=%d\n", pCtl->uAsyncIOState, ReqType));
5899 }
5900
5901 /* Do our work. */
5902 ataR3LockEnter(pDevIns, pCtl);
5903
5904 if (pCtl->uAsyncIOState == ATA_AIO_NEW && !pCtl->fChainedTransfer)
5905 {
5906 u64TS = RTTimeNanoTS();
5907#if defined(DEBUG) || defined(VBOX_WITH_STATISTICS)
5908 STAM_PROFILE_ADV_START(&pCtl->StatAsyncTime, a);
5909#endif
5910 }
5911
5912 switch (ReqType)
5913 {
5914 case ATA_AIO_NEW:
5915 {
5916 uint8_t const iIf = pReq->u.t.iIf & ATA_SELECTED_IF_MASK;
5917 pCtl->iAIOIf = iIf;
5918 PATADEVSTATE s = &pCtl->aIfs[iIf];
5919 PATADEVSTATER3 pDevR3 = &pCtlR3->aIfs[iIf];
5920
5921 s->cbTotalTransfer = pReq->u.t.cbTotalTransfer;
5922 s->uTxDir = pReq->u.t.uTxDir;
5923 s->iBeginTransfer = pReq->u.t.iBeginTransfer;
5924 s->iSourceSink = pReq->u.t.iSourceSink;
5925 s->iIOBufferEnd = 0;
5926 s->u64CmdTS = u64TS;
5927
5928 if (s->fATAPI)
5929 {
5930 if (pCtl->fChainedTransfer)
5931 {
5932 /* Only count the actual transfers, not the PIO
5933 * transfer of the ATAPI command bytes. */
5934 if (s->fDMA)
5935 STAM_REL_COUNTER_INC(&s->StatATAPIDMA);
5936 else
5937 STAM_REL_COUNTER_INC(&s->StatATAPIPIO);
5938 }
5939 }
5940 else
5941 {
5942 if (s->fDMA)
5943 STAM_REL_COUNTER_INC(&s->StatATADMA);
5944 else
5945 STAM_REL_COUNTER_INC(&s->StatATAPIO);
5946 }
5947
5948 pCtl->fChainedTransfer = false;
5949
5950 uint8_t const iBeginTransfer = s->iBeginTransfer;
5951 if ( iBeginTransfer != ATAFN_BT_NULL
5952 && iBeginTransfer < RT_ELEMENTS(g_apfnBeginTransFuncs))
5953 {
5954 Log2(("%s: Ctl#%d: calling begin transfer function\n", __FUNCTION__, pCtl->iCtl));
5955 g_apfnBeginTransFuncs[iBeginTransfer](pCtl, s);
5956 s->iBeginTransfer = ATAFN_BT_NULL;
5957 if (s->uTxDir != PDMMEDIATXDIR_FROM_DEVICE)
5958 s->iIOBufferEnd = s->cbElementaryTransfer;
5959 }
5960 else
5961 {
5962 Assert(iBeginTransfer == ATAFN_BT_NULL);
5963 s->cbElementaryTransfer = s->cbTotalTransfer;
5964 s->iIOBufferEnd = s->cbTotalTransfer;
5965 }
5966 s->iIOBufferCur = 0;
5967
5968 if (s->uTxDir != PDMMEDIATXDIR_TO_DEVICE)
5969 {
5970 uint8_t const iSourceSink = s->iSourceSink;
5971 if ( iSourceSink != ATAFN_SS_NULL
5972 && iSourceSink < RT_ELEMENTS(g_apfnSourceSinkFuncs))
5973 {
5974 bool fRedo;
5975 Log2(("%s: Ctl#%d: calling source/sink function\n", __FUNCTION__, pCtl->iCtl));
5976 fRedo = g_apfnSourceSinkFuncs[iSourceSink](pDevIns, pCtl, s, pDevR3);
5977 pCtl->fRedo = fRedo;
5978 if (RT_UNLIKELY(fRedo && !pCtl->fReset))
5979 {
5980 /* Operation failed at the initial transfer, restart
5981 * everything from scratch by resending the current
5982 * request. Occurs very rarely, not worth optimizing. */
5983 LogRel(("%s: Ctl#%d: redo entire operation\n", __FUNCTION__, pCtl->iCtl));
5984 ataHCAsyncIOPutRequest(pDevIns, pCtl, pReq);
5985 break;
5986 }
5987 }
5988 else
5989 {
5990 Assert(iSourceSink == ATAFN_SS_NULL);
5991 ataR3CmdOK(pCtl, s, 0);
5992 }
5993 s->iIOBufferEnd = s->cbElementaryTransfer;
5994
5995 }
5996
5997 /* Do not go into the transfer phase if RESET is asserted.
5998 * The CritSect is released while waiting for the host OS
5999 * to finish the I/O, thus RESET is possible here. Most
6000 * important: do not change uAsyncIOState. */
6001 if (pCtl->fReset)
6002 break;
6003
6004 if (s->fDMA)
6005 {
6006 if (s->cbTotalTransfer)
6007 {
6008 ataSetStatus(pCtl, s, ATA_STAT_DRQ);
6009
6010 pCtl->uAsyncIOState = ATA_AIO_DMA;
6011 /* If BMDMA is already started, do the transfer now. */
6012 if (pCtl->BmDma.u8Cmd & BM_CMD_START)
6013 {
6014 Log2(("%s: Ctl#%d: message to async I/O thread, continuing DMA transfer immediately\n", __FUNCTION__, pCtl->iCtl));
6015 ataHCAsyncIOPutRequest(pDevIns, pCtl, &g_ataDMARequest);
6016 }
6017 }
6018 else
6019 {
6020 Assert(s->uTxDir == PDMMEDIATXDIR_NONE); /* Any transfer which has an initial transfer size of 0 must be marked as such. */
6021 /* Finish DMA transfer. */
6022 ataR3DMATransferStop(s);
6023 ataHCSetIRQ(pDevIns, pCtl, s);
6024 pCtl->uAsyncIOState = ATA_AIO_NEW;
6025 }
6026 }
6027 else
6028 {
6029 if (s->cbTotalTransfer)
6030 {
6031 ataHCPIOTransfer(pDevIns, pCtl);
6032 Assert(!pCtl->fRedo);
6033 if (s->fATAPITransfer || s->uTxDir != PDMMEDIATXDIR_TO_DEVICE)
6034 ataHCSetIRQ(pDevIns, pCtl, s);
6035
6036 if (s->uTxDir == PDMMEDIATXDIR_TO_DEVICE || s->iSourceSink != ATAFN_SS_NULL)
6037 {
6038 /* Write operations and not yet finished transfers
6039 * must be completed in the async I/O thread. */
6040 pCtl->uAsyncIOState = ATA_AIO_PIO;
6041 }
6042 else
6043 {
6044 /* Finished read operation can be handled inline
6045 * in the end of PIO transfer handling code. Linux
6046 * depends on this, as it waits only briefly for
6047 * devices to become ready after incoming data
6048 * transfer. Cannot find anything in the ATA spec
6049 * that backs this assumption, but as all kernels
6050 * are affected (though most of the time it does
6051 * not cause any harm) this must work. */
6052 pCtl->uAsyncIOState = ATA_AIO_NEW;
6053 }
6054 }
6055 else
6056 {
6057 Assert(s->uTxDir == PDMMEDIATXDIR_NONE); /* Any transfer which has an initial transfer size of 0 must be marked as such. */
6058 /* Finish PIO transfer. */
6059 ataHCPIOTransfer(pDevIns, pCtl);
6060 Assert(!pCtl->fRedo);
6061 if (!s->fATAPITransfer)
6062 ataHCSetIRQ(pDevIns, pCtl, s);
6063 pCtl->uAsyncIOState = ATA_AIO_NEW;
6064 }
6065 }
6066 break;
6067 }
6068
6069 case ATA_AIO_DMA:
6070 {
6071 BMDMAState *bm = &pCtl->BmDma;
6072 PATADEVSTATE s = &pCtl->aIfs[pCtl->iAIOIf & ATA_SELECTED_IF_MASK];
6073 ATAFNSS iOriginalSourceSink = (ATAFNSS)s->iSourceSink; /* Used by the hack below, but gets reset by then. */
6074
6075 if (s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE)
6076 AssertRelease(bm->u8Cmd & BM_CMD_WRITE);
6077 else
6078 AssertRelease(!(bm->u8Cmd & BM_CMD_WRITE));
6079
6080 if (RT_LIKELY(!pCtl->fRedo))
6081 {
6082 /* The specs say that the descriptor table must not cross a
6083 * 4K boundary. */
6084 pCtl->GCPhysFirstDMADesc = bm->GCPhysAddr;
6085 pCtl->GCPhysLastDMADesc = RT_ALIGN_32(bm->GCPhysAddr + 1, _4K) - sizeof(BMDMADesc);
6086 }
6087 ataR3DMATransfer(pDevIns, pCtl, pCtlR3);
6088
6089 if (RT_UNLIKELY(pCtl->fRedo && !pCtl->fReset))
6090 {
6091 LogRel(("PIIX3 ATA: Ctl#%d: redo DMA operation\n", pCtl->iCtl));
6092 ataHCAsyncIOPutRequest(pDevIns, pCtl, &g_ataDMARequest);
6093 break;
6094 }
6095
6096 /* The infamous delay IRQ hack. */
6097 if ( iOriginalSourceSink == ATAFN_SS_WRITE_SECTORS
6098 && s->cbTotalTransfer == 0
6099 && pCtl->msDelayIRQ)
6100 {
6101 /* Delay IRQ for writing. Required to get the Win2K
6102 * installation work reliably (otherwise it crashes,
6103 * usually during component install). So far no better
6104 * solution has been found. */
6105 Log(("%s: delay IRQ hack\n", __FUNCTION__));
6106 ataR3LockLeave(pDevIns, pCtl);
6107 RTThreadSleep(pCtl->msDelayIRQ);
6108 ataR3LockEnter(pDevIns, pCtl);
6109 }
6110
6111 ataUnsetStatus(pCtl, s, ATA_STAT_DRQ);
6112 Assert(!pCtl->fChainedTransfer);
6113 Assert(s->iSourceSink == ATAFN_SS_NULL);
6114 if (s->fATAPITransfer)
6115 {
6116 s->uATARegNSector = (s->uATARegNSector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
6117 Log2(("%s: Ctl#%d: interrupt reason %#04x\n", __FUNCTION__, pCtl->iCtl, s->uATARegNSector));
6118 s->fATAPITransfer = false;
6119 }
6120 ataHCSetIRQ(pDevIns, pCtl, s);
6121 pCtl->uAsyncIOState = ATA_AIO_NEW;
6122 break;
6123 }
6124
6125 case ATA_AIO_PIO:
6126 {
6127 uint8_t const iIf = pCtl->iAIOIf & ATA_SELECTED_IF_MASK;
6128 pCtl->iAIOIf = iIf;
6129 PATADEVSTATE s = &pCtl->aIfs[iIf];
6130 PATADEVSTATER3 pDevR3 = &pCtlR3->aIfs[iIf];
6131
6132 uint8_t const iSourceSink = s->iSourceSink;
6133 if ( iSourceSink != ATAFN_SS_NULL
6134 && iSourceSink < RT_ELEMENTS(g_apfnSourceSinkFuncs))
6135 {
6136 bool fRedo;
6137 Log2(("%s: Ctl#%d: calling source/sink function\n", __FUNCTION__, pCtl->iCtl));
6138 fRedo = g_apfnSourceSinkFuncs[iSourceSink](pDevIns, pCtl, s, pDevR3);
6139 pCtl->fRedo = fRedo;
6140 if (RT_UNLIKELY(fRedo && !pCtl->fReset))
6141 {
6142 LogRel(("PIIX3 ATA: Ctl#%d: redo PIO operation\n", pCtl->iCtl));
6143 ataHCAsyncIOPutRequest(pDevIns, pCtl, &g_ataPIORequest);
6144 break;
6145 }
6146 s->iIOBufferCur = 0;
6147 s->iIOBufferEnd = s->cbElementaryTransfer;
6148 }
6149 else
6150 {
6151 /* Continue a previously started transfer. */
6152 Assert(iSourceSink == ATAFN_SS_NULL);
6153 ataUnsetStatus(pCtl, s, ATA_STAT_BUSY);
6154 ataSetStatus(pCtl, s, ATA_STAT_READY);
6155 }
6156
6157 /* It is possible that the drives on this controller get RESET
6158 * during the above call to the source/sink function. If that's
6159 * the case, don't restart the transfer and don't finish it the
6160 * usual way. RESET handling took care of all that already.
6161 * Most important: do not change uAsyncIOState. */
6162 if (pCtl->fReset)
6163 break;
6164
6165 if (s->cbTotalTransfer)
6166 {
6167 ataHCPIOTransfer(pDevIns, pCtl);
6168 ataHCSetIRQ(pDevIns, pCtl, s);
6169
6170 if (s->uTxDir == PDMMEDIATXDIR_TO_DEVICE || s->iSourceSink != ATAFN_SS_NULL)
6171 {
6172 /* Write operations and not yet finished transfers
6173 * must be completed in the async I/O thread. */
6174 pCtl->uAsyncIOState = ATA_AIO_PIO;
6175 }
6176 else
6177 {
6178 /* Finished read operation can be handled inline
6179 * in the end of PIO transfer handling code. Linux
6180 * depends on this, as it waits only briefly for
6181 * devices to become ready after incoming data
6182 * transfer. Cannot find anything in the ATA spec
6183 * that backs this assumption, but as all kernels
6184 * are affected (though most of the time it does
6185 * not cause any harm) this must work. */
6186 pCtl->uAsyncIOState = ATA_AIO_NEW;
6187 }
6188 }
6189 else
6190 {
6191 /* The infamous delay IRQ hack. */
6192 if (RT_UNLIKELY(pCtl->msDelayIRQ))
6193 {
6194 /* Various antique guests have buggy disk drivers silently
6195 * assuming that disk operations take a relatively long time.
6196 * Work around such bugs by holding off interrupts a bit.
6197 */
6198 Log(("%s: delay IRQ hack (PIO)\n", __FUNCTION__));
6199 ataR3LockLeave(pDevIns, pCtl);
6200 RTThreadSleep(pCtl->msDelayIRQ);
6201 ataR3LockEnter(pDevIns, pCtl);
6202 }
6203
6204 /* Finish PIO transfer. */
6205 ataHCPIOTransfer(pDevIns, pCtl);
6206 if ( !pCtl->fChainedTransfer
6207 && !s->fATAPITransfer
6208 && s->uTxDir != PDMMEDIATXDIR_FROM_DEVICE)
6209 {
6210 ataHCSetIRQ(pDevIns, pCtl, s);
6211 }
6212 pCtl->uAsyncIOState = ATA_AIO_NEW;
6213 }
6214 break;
6215 }
6216
6217 case ATA_AIO_RESET_ASSERTED:
6218 pCtl->uAsyncIOState = ATA_AIO_RESET_CLEARED;
6219 ataHCPIOTransferStop(pDevIns, pCtl, &pCtl->aIfs[0]);
6220 ataHCPIOTransferStop(pDevIns, pCtl, &pCtl->aIfs[1]);
6221 /* Do not change the DMA registers, they are not affected by the
6222 * ATA controller reset logic. It should be sufficient to issue a
6223 * new command, which is now possible as the state is cleared. */
6224 break;
6225
6226 case ATA_AIO_RESET_CLEARED:
6227 pCtl->uAsyncIOState = ATA_AIO_NEW;
6228 pCtl->fReset = false;
6229 /* Ensure that half-completed transfers are not redone. A reset
6230 * cancels the entire transfer, so continuing is wrong. */
6231 pCtl->fRedo = false;
6232 pCtl->fRedoDMALastDesc = false;
6233 LogRel(("PIIX3 ATA: Ctl#%d: finished processing RESET\n", pCtl->iCtl));
6234 for (uint32_t i = 0; i < RT_ELEMENTS(pCtl->aIfs); i++)
6235 {
6236 ataR3SetSignature(&pCtl->aIfs[i]);
6237 if (pCtl->aIfs[i].fATAPI)
6238 ataSetStatusValue(pCtl, &pCtl->aIfs[i], 0); /* NOTE: READY is _not_ set */
6239 else
6240 ataSetStatusValue(pCtl, &pCtl->aIfs[i], ATA_STAT_READY | ATA_STAT_SEEK);
6241 }
6242 break;
6243
6244 case ATA_AIO_ABORT:
6245 {
6246 /* Abort the current command no matter what. There cannot be
6247 * any command activity on the other drive otherwise using
6248 * one thread per controller wouldn't work at all. */
6249 PATADEVSTATE s = &pCtl->aIfs[pReq->u.a.iIf & ATA_SELECTED_IF_MASK];
6250
6251 pCtl->uAsyncIOState = ATA_AIO_NEW;
6252 /* Do not change the DMA registers, they are not affected by the
6253 * ATA controller reset logic. It should be sufficient to issue a
6254 * new command, which is now possible as the state is cleared. */
6255 if (pReq->u.a.fResetDrive)
6256 {
6257 ataR3ResetDevice(pDevIns, pCtl, s);
6258 ataR3DeviceDiag(pCtl, s);
6259 }
6260 else
6261 {
6262 /* Stop any pending DMA transfer. */
6263 s->fDMA = false;
6264 ataHCPIOTransferStop(pDevIns, pCtl, s);
6265 ataUnsetStatus(pCtl, s, ATA_STAT_BUSY | ATA_STAT_DRQ | ATA_STAT_SEEK | ATA_STAT_ERR);
6266 ataSetStatus(pCtl, s, ATA_STAT_READY);
6267 ataHCSetIRQ(pDevIns, pCtl, s);
6268 }
6269 break;
6270 }
6271
6272 default:
6273 AssertMsgFailed(("Undefined async I/O state %d\n", pCtl->uAsyncIOState));
6274 }
6275
6276 ataR3AsyncIORemoveCurrentRequest(pDevIns, pCtl, ReqType);
6277 pReq = ataR3AsyncIOGetCurrentRequest(pDevIns, pCtl);
6278
6279 if (pCtl->uAsyncIOState == ATA_AIO_NEW && !pCtl->fChainedTransfer)
6280 {
6281# if defined(DEBUG) || defined(VBOX_WITH_STATISTICS)
6282 STAM_PROFILE_ADV_STOP(&pCtl->StatAsyncTime, a);
6283# endif
6284
6285 u64TS = RTTimeNanoTS() - u64TS;
6286 uWait = u64TS / 1000;
6287 uintptr_t const iAIOIf = pCtl->iAIOIf & ATA_SELECTED_IF_MASK;
6288 Log(("%s: Ctl#%d: LUN#%d finished I/O transaction in %d microseconds\n",
6289 __FUNCTION__, pCtl->iCtl, pCtl->aIfs[iAIOIf].iLUN, (uint32_t)(uWait)));
6290 /* Mark command as finished. */
6291 pCtl->aIfs[iAIOIf].u64CmdTS = 0;
6292
6293 /*
6294 * Release logging of command execution times depends on the
6295 * command type. ATAPI commands often take longer (due to CD/DVD
6296 * spin up time etc.) so the threshold is different.
6297 */
6298 if (pCtl->aIfs[iAIOIf].uATARegCommand != ATA_PACKET)
6299 {
6300 if (uWait > 8 * 1000 * 1000)
6301 {
6302 /*
6303 * Command took longer than 8 seconds. This is close
6304 * enough or over the guest's command timeout, so place
6305 * an entry in the release log to allow tracking such
6306 * timing errors (which are often caused by the host).
6307 */
6308 LogRel(("PIIX3 ATA: execution time for ATA command %#04x was %d seconds\n",
6309 pCtl->aIfs[iAIOIf].uATARegCommand, uWait / (1000 * 1000)));
6310 }
6311 }
6312 else
6313 {
6314 if (uWait > 20 * 1000 * 1000)
6315 {
6316 /*
6317 * Command took longer than 20 seconds. This is close
6318 * enough or over the guest's command timeout, so place
6319 * an entry in the release log to allow tracking such
6320 * timing errors (which are often caused by the host).
6321 */
6322 LogRel(("PIIX3 ATA: execution time for ATAPI command %#04x was %d seconds\n",
6323 pCtl->aIfs[iAIOIf].abATAPICmd[0], uWait / (1000 * 1000)));
6324 }
6325 }
6326
6327# if defined(DEBUG) || defined(VBOX_WITH_STATISTICS)
6328 if (uWait < pCtl->StatAsyncMinWait || !pCtl->StatAsyncMinWait)
6329 pCtl->StatAsyncMinWait = uWait;
6330 if (uWait > pCtl->StatAsyncMaxWait)
6331 pCtl->StatAsyncMaxWait = uWait;
6332
6333 STAM_COUNTER_ADD(&pCtl->StatAsyncTimeUS, uWait);
6334 STAM_COUNTER_INC(&pCtl->StatAsyncOps);
6335# endif /* DEBUG || VBOX_WITH_STATISTICS */
6336 }
6337
6338 ataR3LockLeave(pDevIns, pCtl);
6339 }
6340
6341 /* Signal the ultimate idleness. */
6342 RTThreadUserSignal(pCtlR3->hAsyncIOThread);
6343 if (pCtlR3->fSignalIdle)
6344 PDMDevHlpAsyncNotificationCompleted(pDevIns);
6345
6346 /* Cleanup the state. */
6347 /* Do not destroy request lock yet, still needed for proper shutdown. */
6348 pCtlR3->fShutdown = false;
6349
6350 Log2(("%s: Ctl#%d: return %Rrc\n", __FUNCTION__, pCtl->iCtl, rc));
6351 return rc;
6352}
6353
6354#endif /* IN_RING3 */
6355
6356static uint32_t ataBMDMACmdReadB(PATACONTROLLER pCtl, uint32_t addr)
6357{
6358 uint32_t val = pCtl->BmDma.u8Cmd;
6359 RT_NOREF(addr);
6360 Log2(("%s: addr=%#06x val=%#04x\n", __FUNCTION__, addr, val));
6361 return val;
6362}
6363
6364
6365static void ataBMDMACmdWriteB(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, uint32_t addr, uint32_t val)
6366{
6367 RT_NOREF(pDevIns, addr);
6368 Log2(("%s: addr=%#06x val=%#04x\n", __FUNCTION__, addr, val));
6369 if (!(val & BM_CMD_START))
6370 {
6371 pCtl->BmDma.u8Status &= ~BM_STATUS_DMAING;
6372 pCtl->BmDma.u8Cmd = val & (BM_CMD_START | BM_CMD_WRITE);
6373 }
6374 else
6375 {
6376#ifndef IN_RC
6377 /* Check whether the guest OS wants to change DMA direction in
6378 * mid-flight. Not allowed, according to the PIIX3 specs. */
6379 Assert(!(pCtl->BmDma.u8Status & BM_STATUS_DMAING) || !((val ^ pCtl->BmDma.u8Cmd) & 0x04));
6380 uint8_t uOldBmDmaStatus = pCtl->BmDma.u8Status;
6381 pCtl->BmDma.u8Status |= BM_STATUS_DMAING;
6382 pCtl->BmDma.u8Cmd = val & (BM_CMD_START | BM_CMD_WRITE);
6383
6384 /* Do not continue DMA transfers while the RESET line is asserted. */
6385 if (pCtl->fReset)
6386 {
6387 Log2(("%s: Ctl#%d: suppressed continuing DMA transfer as RESET is active\n", __FUNCTION__, pCtl->iCtl));
6388 return;
6389 }
6390
6391 /* Do not start DMA transfers if there's a PIO transfer going on,
6392 * or if there is already a transfer started on this controller. */
6393 if ( !pCtl->aIfs[pCtl->iSelectedIf & ATA_SELECTED_IF_MASK].fDMA
6394 || (uOldBmDmaStatus & BM_STATUS_DMAING))
6395 return;
6396
6397 if (pCtl->aIfs[pCtl->iAIOIf & ATA_SELECTED_IF_MASK].uATARegStatus & ATA_STAT_DRQ)
6398 {
6399 Log2(("%s: Ctl#%d: message to async I/O thread, continuing DMA transfer\n", __FUNCTION__, pCtl->iCtl));
6400 ataHCAsyncIOPutRequest(pDevIns, pCtl, &g_ataDMARequest);
6401 }
6402#else /* !IN_RING3 */
6403 AssertMsgFailed(("DMA START handling is too complicated for RC\n"));
6404#endif /* IN_RING3 */
6405 }
6406}
6407
6408static uint32_t ataBMDMAStatusReadB(PATACONTROLLER pCtl, uint32_t addr)
6409{
6410 uint32_t val = pCtl->BmDma.u8Status;
6411 RT_NOREF(addr);
6412 Log2(("%s: addr=%#06x val=%#04x\n", __FUNCTION__, addr, val));
6413 return val;
6414}
6415
6416static void ataBMDMAStatusWriteB(PATACONTROLLER pCtl, uint32_t addr, uint32_t val)
6417{
6418 RT_NOREF(addr);
6419 Log2(("%s: addr=%#06x val=%#04x\n", __FUNCTION__, addr, val));
6420 pCtl->BmDma.u8Status = (val & (BM_STATUS_D0DMA | BM_STATUS_D1DMA))
6421 | (pCtl->BmDma.u8Status & BM_STATUS_DMAING)
6422 | (pCtl->BmDma.u8Status & ~val & (BM_STATUS_ERROR | BM_STATUS_INT));
6423}
6424
6425static uint32_t ataBMDMAAddrReadL(PATACONTROLLER pCtl, uint32_t addr)
6426{
6427 uint32_t val = (uint32_t)pCtl->BmDma.GCPhysAddr;
6428 RT_NOREF(addr);
6429 Log2(("%s: addr=%#06x val=%#010x\n", __FUNCTION__, addr, val));
6430 return val;
6431}
6432
6433static void ataBMDMAAddrWriteL(PATACONTROLLER pCtl, uint32_t addr, uint32_t val)
6434{
6435 RT_NOREF(addr);
6436 Log2(("%s: addr=%#06x val=%#010x\n", __FUNCTION__, addr, val));
6437 pCtl->BmDma.GCPhysAddr = val & ~3;
6438}
6439
6440static void ataBMDMAAddrWriteLowWord(PATACONTROLLER pCtl, uint32_t addr, uint32_t val)
6441{
6442 RT_NOREF(addr);
6443 Log2(("%s: addr=%#06x val=%#010x\n", __FUNCTION__, addr, val));
6444 pCtl->BmDma.GCPhysAddr = (pCtl->BmDma.GCPhysAddr & 0xFFFF0000) | RT_LOWORD(val & ~3);
6445
6446}
6447
6448static void ataBMDMAAddrWriteHighWord(PATACONTROLLER pCtl, uint32_t addr, uint32_t val)
6449{
6450 Log2(("%s: addr=%#06x val=%#010x\n", __FUNCTION__, addr, val));
6451 RT_NOREF(addr);
6452 pCtl->BmDma.GCPhysAddr = (RT_LOWORD(val) << 16) | RT_LOWORD(pCtl->BmDma.GCPhysAddr);
6453}
6454
6455/** Helper for ataBMDMAIOPortRead and ataBMDMAIOPortWrite. */
6456#define VAL(port, size) ( ((port) & BM_DMA_CTL_IOPORTS_MASK) | ((size) << BM_DMA_CTL_IOPORTS_SHIFT) )
6457
6458/**
6459 * @callback_method_impl{FNIOMIOPORTNEWOUT,
6460 * Port I/O Handler for bus-master DMA IN operations - both controllers.}
6461 */
6462static DECLCALLBACK(VBOXSTRICTRC)
6463ataBMDMAIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
6464{
6465 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE);
6466 PATACONTROLLER pCtl = &RT_SAFE_SUBSCRIPT(pThis->aCts, (offPort >> BM_DMA_CTL_IOPORTS_SHIFT));
6467 RT_NOREF(pvUser);
6468
6469 VBOXSTRICTRC rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->lock, VINF_IOM_R3_IOPORT_READ);
6470 if (rc == VINF_SUCCESS)
6471 {
6472 switch (VAL(offPort, cb))
6473 {
6474 case VAL(0, 1): *pu32 = ataBMDMACmdReadB(pCtl, offPort); break;
6475 case VAL(0, 2): *pu32 = ataBMDMACmdReadB(pCtl, offPort); break;
6476 case VAL(2, 1): *pu32 = ataBMDMAStatusReadB(pCtl, offPort); break;
6477 case VAL(2, 2): *pu32 = ataBMDMAStatusReadB(pCtl, offPort); break;
6478 case VAL(4, 4): *pu32 = ataBMDMAAddrReadL(pCtl, offPort); break;
6479 case VAL(0, 4):
6480 /* The SCO OpenServer tries to read 4 bytes starting from offset 0. */
6481 *pu32 = ataBMDMACmdReadB(pCtl, offPort) | (ataBMDMAStatusReadB(pCtl, offPort) << 16);
6482 break;
6483 default:
6484 ASSERT_GUEST_MSG_FAILED(("Unsupported read from port %x size=%d\n", offPort, cb));
6485 rc = VERR_IOM_IOPORT_UNUSED;
6486 break;
6487 }
6488 PDMDevHlpCritSectLeave(pDevIns, &pCtl->lock);
6489 }
6490 return rc;
6491}
6492
6493/**
6494 * @callback_method_impl{FNIOMIOPORTNEWOUT,
6495 * Port I/O Handler for bus-master DMA OUT operations - both controllers.}
6496 */
6497static DECLCALLBACK(VBOXSTRICTRC)
6498ataBMDMAIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
6499{
6500 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE);
6501 PATACONTROLLER pCtl = &RT_SAFE_SUBSCRIPT(pThis->aCts, (offPort >> BM_DMA_CTL_IOPORTS_SHIFT));
6502 RT_NOREF(pvUser);
6503
6504 VBOXSTRICTRC rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->lock, VINF_IOM_R3_IOPORT_WRITE);
6505 if (rc == VINF_SUCCESS)
6506 {
6507 switch (VAL(offPort, cb))
6508 {
6509 case VAL(0, 1):
6510#ifdef IN_RC
6511 if (u32 & BM_CMD_START)
6512 {
6513 rc = VINF_IOM_R3_IOPORT_WRITE;
6514 break;
6515 }
6516#endif
6517 ataBMDMACmdWriteB(pDevIns, pCtl, offPort, u32);
6518 break;
6519 case VAL(2, 1): ataBMDMAStatusWriteB(pCtl, offPort, u32); break;
6520 case VAL(4, 4): ataBMDMAAddrWriteL(pCtl, offPort, u32); break;
6521 case VAL(4, 2): ataBMDMAAddrWriteLowWord(pCtl, offPort, u32); break;
6522 case VAL(6, 2): ataBMDMAAddrWriteHighWord(pCtl, offPort, u32); break;
6523 default:
6524 ASSERT_GUEST_MSG_FAILED(("Unsupported write to port %x size=%d val=%x\n", offPort, cb, u32));
6525 break;
6526 }
6527 PDMDevHlpCritSectLeave(pDevIns, &pCtl->lock);
6528 }
6529 return rc;
6530}
6531
6532#undef VAL
6533
6534#ifdef IN_RING3
6535
6536/* -=-=-=-=-=- ATASTATE::IBase -=-=-=-=-=- */
6537
6538/**
6539 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
6540 */
6541static DECLCALLBACK(void *) ataR3Status_QueryInterface(PPDMIBASE pInterface, const char *pszIID)
6542{
6543 PATASTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ATASTATER3, IBase);
6544 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
6545 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThisCC->ILeds);
6546 return NULL;
6547}
6548
6549
6550/* -=-=-=-=-=- ATASTATE::ILeds -=-=-=-=-=- */
6551
6552/**
6553 * Gets the pointer to the status LED of a unit.
6554 *
6555 * @returns VBox status code.
6556 * @param pInterface Pointer to the interface structure containing the called function pointer.
6557 * @param iLUN The unit which status LED we desire.
6558 * @param ppLed Where to store the LED pointer.
6559 */
6560static DECLCALLBACK(int) ataR3Status_QueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
6561{
6562 if (iLUN < 4)
6563 {
6564 PATASTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ATASTATER3, ILeds);
6565 PATASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PATASTATE);
6566 switch (iLUN)
6567 {
6568 case 0: *ppLed = &pThis->aCts[0].aIfs[0].Led; break;
6569 case 1: *ppLed = &pThis->aCts[0].aIfs[1].Led; break;
6570 case 2: *ppLed = &pThis->aCts[1].aIfs[0].Led; break;
6571 case 3: *ppLed = &pThis->aCts[1].aIfs[1].Led; break;
6572 }
6573 Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
6574 return VINF_SUCCESS;
6575 }
6576 return VERR_PDM_LUN_NOT_FOUND;
6577}
6578
6579
6580/* -=-=-=-=-=- ATADEVSTATE::IBase -=-=-=-=-=- */
6581
6582/**
6583 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
6584 */
6585static DECLCALLBACK(void *) ataR3QueryInterface(PPDMIBASE pInterface, const char *pszIID)
6586{
6587 PATADEVSTATER3 pIfR3 = RT_FROM_MEMBER(pInterface, ATADEVSTATER3, IBase);
6588 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pIfR3->IBase);
6589 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIMEDIAPORT, &pIfR3->IPort);
6590 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIMOUNTNOTIFY, &pIfR3->IMountNotify);
6591 return NULL;
6592}
6593
6594
6595/* -=-=-=-=-=- ATADEVSTATE::IPort -=-=-=-=-=- */
6596
6597/**
6598 * @interface_method_impl{PDMIMEDIAPORT,pfnQueryDeviceLocation}
6599 */
6600static DECLCALLBACK(int) ataR3QueryDeviceLocation(PPDMIMEDIAPORT pInterface, const char **ppcszController,
6601 uint32_t *piInstance, uint32_t *piLUN)
6602{
6603 PATADEVSTATER3 pIfR3 = RT_FROM_MEMBER(pInterface, ATADEVSTATER3, IPort);
6604 PPDMDEVINS pDevIns = pIfR3->pDevIns;
6605
6606 AssertPtrReturn(ppcszController, VERR_INVALID_POINTER);
6607 AssertPtrReturn(piInstance, VERR_INVALID_POINTER);
6608 AssertPtrReturn(piLUN, VERR_INVALID_POINTER);
6609
6610 *ppcszController = pDevIns->pReg->szName;
6611 *piInstance = pDevIns->iInstance;
6612 *piLUN = pIfR3->iLUN;
6613
6614 return VINF_SUCCESS;
6615}
6616
6617#endif /* IN_RING3 */
6618
6619/* -=-=-=-=-=- Wrappers -=-=-=-=-=- */
6620
6621
6622/**
6623 * @callback_method_impl{FNIOMIOPORTNEWOUT,
6624 * Port I/O Handler for OUT operations on unpopulated IDE channels.}
6625 * @note offPort is an absolute port number!
6626 */
6627static DECLCALLBACK(VBOXSTRICTRC)
6628ataIOPortWriteEmptyBus(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
6629{
6630 RT_NOREF(pDevIns, pvUser, offPort, u32, cb);
6631
6632#ifdef VBOX_STRICT
6633 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE);
6634 PATACONTROLLER pCtl = &RT_SAFE_SUBSCRIPT(pThis->aCts, (uintptr_t)pvUser);
6635 Assert((uintptr_t)pvUser < 2);
6636 Assert(!pCtl->aIfs[0].fPresent && !pCtl->aIfs[1].fPresent);
6637#endif
6638
6639 /* This is simply a black hole, writes on unpopulated IDE channels elicit no response. */
6640 LogFunc(("Empty bus: Ignoring write to port %x val=%x size=%d\n", offPort, u32, cb));
6641 return VINF_SUCCESS;
6642}
6643
6644
6645/**
6646 * @callback_method_impl{FNIOMIOPORTNEWIN,
6647 * Port I/O Handler for IN operations on unpopulated IDE channels.}
6648 * @note offPort is an absolute port number!
6649 */
6650static DECLCALLBACK(VBOXSTRICTRC)
6651ataIOPortReadEmptyBus(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
6652{
6653 RT_NOREF(pDevIns, offPort, pvUser);
6654
6655#ifdef VBOX_STRICT
6656 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE);
6657 PATACONTROLLER pCtl = &RT_SAFE_SUBSCRIPT(pThis->aCts, (uintptr_t)pvUser);
6658 Assert((uintptr_t)pvUser < 2);
6659 Assert(cb <= 4);
6660 Assert(!pCtl->aIfs[0].fPresent && !pCtl->aIfs[1].fPresent);
6661#endif
6662
6663 /*
6664 * Reads on unpopulated IDE channels behave in a unique way. Newer ATA specifications
6665 * mandate that the host must have a pull-down resistor on signal DD7. As a consequence,
6666 * bit 7 is always read as zero. This greatly aids in ATA device detection because
6667 * the empty bus does not look to the host like a permanently busy drive, and no long
6668 * timeouts (on the order of 30 seconds) are needed.
6669 *
6670 * The response is entirely static and does not require any locking or other fancy
6671 * stuff. Breaking it out simplifies the I/O handling for non-empty IDE channels which
6672 * is quite complicated enough already.
6673 */
6674 *pu32 = ATA_EMPTY_BUS_DATA_32 >> ((4 - cb) * 8);
6675 LogFunc(("Empty bus: port %x val=%x size=%d\n", offPort, *pu32, cb));
6676 return VINF_SUCCESS;
6677}
6678
6679
6680/**
6681 * @callback_method_impl{FNIOMIOPORTNEWOUT,
6682 * Port I/O Handler for primary port range OUT operations.}
6683 * @note offPort is an absolute port number!
6684 */
6685static DECLCALLBACK(VBOXSTRICTRC)
6686ataIOPortWrite1Other(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
6687{
6688 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE);
6689 uintptr_t iCtl = (uintptr_t)pvUser % RT_ELEMENTS(pThis->aCts);
6690 PATACONTROLLER pCtl = &pThis->aCts[iCtl];
6691
6692 Assert((uintptr_t)pvUser < 2);
6693
6694 VBOXSTRICTRC rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->lock, VINF_IOM_R3_IOPORT_WRITE);
6695 if (rc == VINF_SUCCESS)
6696 {
6697 /* Writes to the other command block ports should be 8-bit only. If they
6698 * are not, the high bits are simply discarded. Undocumented, but observed
6699 * on a real PIIX4 system.
6700 */
6701 if (cb > 1)
6702 Log(("ataIOPortWrite1: suspect write to port %x val=%x size=%d\n", offPort, u32, cb));
6703
6704 rc = ataIOPortWriteU8(pDevIns, pCtl, offPort, u32, iCtl);
6705
6706 PDMDevHlpCritSectLeave(pDevIns, &pCtl->lock);
6707 }
6708 return rc;
6709}
6710
6711
6712/**
6713 * @callback_method_impl{FNIOMIOPORTNEWIN,
6714 * Port I/O Handler for primary port range IN operations.}
6715 * @note offPort is an absolute port number!
6716 */
6717static DECLCALLBACK(VBOXSTRICTRC)
6718ataIOPortRead1Other(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
6719{
6720 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE);
6721 PATACONTROLLER pCtl = &RT_SAFE_SUBSCRIPT(pThis->aCts, (uintptr_t)pvUser);
6722
6723 Assert((uintptr_t)pvUser < 2);
6724
6725 VBOXSTRICTRC rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->lock, VINF_IOM_R3_IOPORT_READ);
6726 if (rc == VINF_SUCCESS)
6727 {
6728 /* Reads from the other command block registers should be 8-bit only.
6729 * If they are not, the low byte is propagated to the high bits.
6730 * Undocumented, but observed on a real PIIX4 system.
6731 */
6732 rc = ataIOPortReadU8(pDevIns, pCtl, offPort, pu32);
6733 if (cb > 1)
6734 {
6735 uint32_t pad;
6736
6737 /* Replicate the 8-bit result into the upper three bytes. */
6738 pad = *pu32 & 0xff;
6739 pad = pad | (pad << 8);
6740 pad = pad | (pad << 16);
6741 *pu32 = pad;
6742 Log(("ataIOPortRead1: suspect read from port %x size=%d\n", offPort, cb));
6743 }
6744 PDMDevHlpCritSectLeave(pDevIns, &pCtl->lock);
6745 }
6746 return rc;
6747}
6748
6749
6750/**
6751 * @callback_method_impl{FNIOMIOPORTNEWOUT,
6752 * Port I/O Handler for secondary port range OUT operations.}
6753 * @note offPort is an absolute port number!
6754 */
6755static DECLCALLBACK(VBOXSTRICTRC)
6756ataIOPortWrite2(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
6757{
6758 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE);
6759 PATACONTROLLER pCtl = &RT_SAFE_SUBSCRIPT(pThis->aCts, (uintptr_t)pvUser);
6760 int rc;
6761
6762 Assert((uintptr_t)pvUser < 2);
6763
6764 if (cb == 1)
6765 {
6766 rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->lock, VINF_IOM_R3_IOPORT_WRITE);
6767 if (rc == VINF_SUCCESS)
6768 {
6769 rc = ataControlWrite(pDevIns, pCtl, u32, offPort);
6770 PDMDevHlpCritSectLeave(pDevIns, &pCtl->lock);
6771 }
6772 }
6773 else
6774 {
6775 Log(("ataIOPortWrite2: ignoring write to port %x+%x size=%d!\n", offPort, pCtl->IOPortBase2, cb));
6776 rc = VINF_SUCCESS;
6777 }
6778 return rc;
6779}
6780
6781
6782/**
6783 * @callback_method_impl{FNIOMIOPORTNEWIN,
6784 * Port I/O Handler for secondary port range IN operations.}
6785 * @note offPort is an absolute port number!
6786 */
6787static DECLCALLBACK(VBOXSTRICTRC)
6788ataIOPortRead2(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
6789{
6790 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE);
6791 PATACONTROLLER pCtl = &RT_SAFE_SUBSCRIPT(pThis->aCts, (uintptr_t)pvUser);
6792 int rc;
6793
6794 Assert((uintptr_t)pvUser < 2);
6795
6796 if (cb == 1)
6797 {
6798 rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->lock, VINF_IOM_R3_IOPORT_READ);
6799 if (rc == VINF_SUCCESS)
6800 {
6801 *pu32 = ataStatusRead(pCtl, offPort);
6802 PDMDevHlpCritSectLeave(pDevIns, &pCtl->lock);
6803 }
6804 }
6805 else
6806 {
6807 Log(("ataIOPortRead2: ignoring read from port %x+%x size=%d!\n", offPort, pCtl->IOPortBase2, cb));
6808 rc = VERR_IOM_IOPORT_UNUSED;
6809 }
6810 return rc;
6811}
6812
6813#ifdef IN_RING3
6814
6815/**
6816 * Detach notification.
6817 *
6818 * The DVD drive has been unplugged.
6819 *
6820 * @param pDevIns The device instance.
6821 * @param iLUN The logical unit which is being detached.
6822 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
6823 */
6824static DECLCALLBACK(void) ataR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
6825{
6826 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE);
6827 PATASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PATASTATECC);
6828 AssertMsg(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
6829 ("PIIX3IDE: Device does not support hotplugging\n")); RT_NOREF(fFlags);
6830
6831 /*
6832 * Locate the controller and stuff.
6833 */
6834 unsigned iController = iLUN / RT_ELEMENTS(pThis->aCts[0].aIfs);
6835 AssertReleaseMsg(iController < RT_ELEMENTS(pThis->aCts), ("iController=%d iLUN=%d\n", iController, iLUN));
6836 PATACONTROLLER pCtl = &pThis->aCts[iController];
6837 PATACONTROLLERR3 pCtlR3 = &pThisCC->aCts[iController];
6838
6839 unsigned iInterface = iLUN % RT_ELEMENTS(pThis->aCts[0].aIfs);
6840 PATADEVSTATE pIf = &pCtl->aIfs[iInterface];
6841 PATADEVSTATER3 pIfR3 = &pCtlR3->aIfs[iInterface];
6842
6843 /*
6844 * Zero some important members.
6845 */
6846 pIfR3->pDrvBase = NULL;
6847 pIfR3->pDrvMedia = NULL;
6848 pIfR3->pDrvMount = NULL;
6849 pIf->fPresent = false;
6850
6851 /*
6852 * In case there was a medium inserted.
6853 */
6854 ataR3MediumRemoved(pIf);
6855}
6856
6857
6858/**
6859 * Configure a LUN.
6860 *
6861 * @returns VBox status code.
6862 * @param pIf The ATA unit state, shared bits.
6863 * @param pIfR3 The ATA unit state, ring-3 bits.
6864 */
6865static int ataR3ConfigLun(PATADEVSTATE pIf, PATADEVSTATER3 pIfR3)
6866{
6867 /*
6868 * Query Block, Bios and Mount interfaces.
6869 */
6870 pIfR3->pDrvMedia = PDMIBASE_QUERY_INTERFACE(pIfR3->pDrvBase, PDMIMEDIA);
6871 if (!pIfR3->pDrvMedia)
6872 {
6873 AssertMsgFailed(("Configuration error: LUN#%d hasn't a block interface!\n", pIf->iLUN));
6874 return VERR_PDM_MISSING_INTERFACE;
6875 }
6876
6877 pIfR3->pDrvMount = PDMIBASE_QUERY_INTERFACE(pIfR3->pDrvBase, PDMIMOUNT);
6878 pIf->fPresent = true;
6879
6880 /*
6881 * Validate type.
6882 */
6883 PDMMEDIATYPE enmType = pIfR3->pDrvMedia->pfnGetType(pIfR3->pDrvMedia);
6884 if ( enmType != PDMMEDIATYPE_CDROM
6885 && enmType != PDMMEDIATYPE_DVD
6886 && enmType != PDMMEDIATYPE_HARD_DISK)
6887 {
6888 AssertMsgFailed(("Configuration error: LUN#%d isn't a disk or cd/dvd-rom. enmType=%d\n", pIf->iLUN, enmType));
6889 return VERR_PDM_UNSUPPORTED_BLOCK_TYPE;
6890 }
6891 if ( ( enmType == PDMMEDIATYPE_DVD
6892 || enmType == PDMMEDIATYPE_CDROM)
6893 && !pIfR3->pDrvMount)
6894 {
6895 AssertMsgFailed(("Internal error: cdrom without a mountable interface, WTF???!\n"));
6896 return VERR_INTERNAL_ERROR;
6897 }
6898 pIf->fATAPI = enmType == PDMMEDIATYPE_DVD || enmType == PDMMEDIATYPE_CDROM;
6899 pIf->fATAPIPassthrough = pIf->fATAPI && pIfR3->pDrvMedia->pfnSendCmd != NULL;
6900
6901 /*
6902 * Allocate I/O buffer.
6903 */
6904 if (pIf->fATAPI)
6905 pIf->cbSector = 2048; /* Not required for ATAPI, one medium can have multiple sector sizes. */
6906 else
6907 {
6908 pIf->cbSector = pIfR3->pDrvMedia->pfnGetSectorSize(pIfR3->pDrvMedia);
6909 AssertLogRelMsgReturn(pIf->cbSector > 0 && pIf->cbSector <= ATA_MAX_SECTOR_SIZE,
6910 ("Unsupported sector size on LUN#%u: %#x (%d)\n", pIf->iLUN, pIf->cbSector, pIf->cbSector),
6911 VERR_OUT_OF_RANGE);
6912 }
6913
6914 if (pIf->cbIOBuffer)
6915 {
6916 /* Buffer is (probably) already allocated. Validate the fields,
6917 * because memory corruption can also overwrite pIf->cbIOBuffer. */
6918 if (pIf->fATAPI)
6919 AssertLogRelReturn(pIf->cbIOBuffer == _128K, VERR_BUFFER_OVERFLOW);
6920 else
6921 AssertLogRelReturn(pIf->cbIOBuffer == ATA_MAX_MULT_SECTORS * pIf->cbSector, VERR_BUFFER_OVERFLOW);
6922 }
6923 else
6924 {
6925 if (pIf->fATAPI)
6926 pIf->cbIOBuffer = _128K;
6927 else
6928 pIf->cbIOBuffer = ATA_MAX_MULT_SECTORS * pIf->cbSector;
6929 }
6930 AssertCompile(_128K <= ATA_MAX_IO_BUFFER_SIZE);
6931 AssertCompileSize(pIf->abIOBuffer, ATA_MAX_IO_BUFFER_SIZE);
6932 AssertLogRelMsgReturn(pIf->cbIOBuffer <= ATA_MAX_IO_BUFFER_SIZE,
6933 ("LUN#%u: cbIOBuffer=%#x (%u)\n", pIf->iLUN, pIf->cbIOBuffer, pIf->cbIOBuffer),
6934 VERR_BUFFER_OVERFLOW);
6935
6936 /*
6937 * Init geometry (only for non-CD/DVD media).
6938 */
6939 int rc = VINF_SUCCESS;
6940 uint32_t cRegions = pIfR3->pDrvMedia->pfnGetRegionCount(pIfR3->pDrvMedia);
6941 pIf->cTotalSectors = 0;
6942 for (uint32_t i = 0; i < cRegions; i++)
6943 {
6944 uint64_t cBlocks = 0;
6945 rc = pIfR3->pDrvMedia->pfnQueryRegionProperties(pIfR3->pDrvMedia, i, NULL, &cBlocks, NULL, NULL);
6946 AssertRC(rc);
6947 pIf->cTotalSectors += cBlocks;
6948 }
6949
6950 if (pIf->fATAPI)
6951 {
6952 pIf->PCHSGeometry.cCylinders = 0; /* dummy */
6953 pIf->PCHSGeometry.cHeads = 0; /* dummy */
6954 pIf->PCHSGeometry.cSectors = 0; /* dummy */
6955 LogRel(("PIIX3 ATA: LUN#%d: CD/DVD, total number of sectors %Ld, passthrough %s\n",
6956 pIf->iLUN, pIf->cTotalSectors, (pIf->fATAPIPassthrough ? "enabled" : "disabled")));
6957 }
6958 else
6959 {
6960 rc = pIfR3->pDrvMedia->pfnBiosGetPCHSGeometry(pIfR3->pDrvMedia, &pIf->PCHSGeometry);
6961 if (rc == VERR_PDM_MEDIA_NOT_MOUNTED)
6962 {
6963 pIf->PCHSGeometry.cCylinders = 0;
6964 pIf->PCHSGeometry.cHeads = 16; /*??*/
6965 pIf->PCHSGeometry.cSectors = 63; /*??*/
6966 }
6967 else if (rc == VERR_PDM_GEOMETRY_NOT_SET)
6968 {
6969 pIf->PCHSGeometry.cCylinders = 0; /* autodetect marker */
6970 rc = VINF_SUCCESS;
6971 }
6972 AssertRC(rc);
6973
6974 if ( pIf->PCHSGeometry.cCylinders == 0
6975 || pIf->PCHSGeometry.cHeads == 0
6976 || pIf->PCHSGeometry.cSectors == 0
6977 )
6978 {
6979 uint64_t cCylinders = pIf->cTotalSectors / (16 * 63);
6980 pIf->PCHSGeometry.cCylinders = RT_MAX(RT_MIN(cCylinders, 16383), 1);
6981 pIf->PCHSGeometry.cHeads = 16;
6982 pIf->PCHSGeometry.cSectors = 63;
6983 /* Set the disk geometry information. Ignore errors. */
6984 pIfR3->pDrvMedia->pfnBiosSetPCHSGeometry(pIfR3->pDrvMedia, &pIf->PCHSGeometry);
6985 rc = VINF_SUCCESS;
6986 }
6987 LogRel(("PIIX3 ATA: LUN#%d: disk, PCHS=%u/%u/%u, total number of sectors %Ld\n",
6988 pIf->iLUN, pIf->PCHSGeometry.cCylinders, pIf->PCHSGeometry.cHeads, pIf->PCHSGeometry.cSectors,
6989 pIf->cTotalSectors));
6990
6991 if (pIfR3->pDrvMedia->pfnDiscard)
6992 LogRel(("PIIX3 ATA: LUN#%d: TRIM enabled\n", pIf->iLUN));
6993 }
6994 /* Initialize the translated geometry. */
6995 pIf->XCHSGeometry = pIf->PCHSGeometry;
6996
6997 /*
6998 * Check if SMP system to adjust the agressiveness of the busy yield hack (@bugref{1960}).
6999 *
7000 * The hack is an ancient (2006?) one for dealing with UNI CPU systems where EMT
7001 * would potentially monopolise the CPU and starve I/O threads. It causes the EMT to
7002 * yield it's timeslice if the guest polls the status register during I/O. On modern
7003 * multicore and multithreaded systems, yielding EMT too often may have adverse
7004 * effects (slow grub) so we aim at avoiding repeating the yield there too often.
7005 */
7006 RTCPUID cCpus = RTMpGetOnlineCount();
7007 if (cCpus <= 1)
7008 {
7009 pIf->cBusyStatusHackR3Rate = 1;
7010 pIf->cBusyStatusHackRZRate = 7;
7011 }
7012 else if (cCpus <= 2)
7013 {
7014 pIf->cBusyStatusHackR3Rate = 3;
7015 pIf->cBusyStatusHackRZRate = 15;
7016 }
7017 else if (cCpus <= 4)
7018 {
7019 pIf->cBusyStatusHackR3Rate = 15;
7020 pIf->cBusyStatusHackRZRate = 31;
7021 }
7022 else
7023 {
7024 pIf->cBusyStatusHackR3Rate = 127;
7025 pIf->cBusyStatusHackRZRate = 127;
7026 }
7027
7028 return rc;
7029}
7030
7031
7032/**
7033 * Attach command.
7034 *
7035 * This is called when we change block driver for the DVD drive.
7036 *
7037 * @returns VBox status code.
7038 * @param pDevIns The device instance.
7039 * @param iLUN The logical unit which is being detached.
7040 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
7041 */
7042static DECLCALLBACK(int) ataR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
7043{
7044 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE);
7045 PATASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PATASTATECC);
7046
7047 AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
7048 ("PIIX3IDE: Device does not support hotplugging\n"),
7049 VERR_INVALID_PARAMETER);
7050
7051 /*
7052 * Locate the controller and stuff.
7053 */
7054 unsigned const iController = iLUN / RT_ELEMENTS(pThis->aCts[0].aIfs);
7055 AssertReleaseMsg(iController < RT_ELEMENTS(pThis->aCts), ("iController=%d iLUN=%d\n", iController, iLUN));
7056 PATACONTROLLER pCtl = &pThis->aCts[iController];
7057 PATACONTROLLERR3 pCtlR3 = &pThisCC->aCts[iController];
7058
7059 unsigned const iInterface = iLUN % RT_ELEMENTS(pThis->aCts[0].aIfs);
7060 PATADEVSTATE pIf = &pCtl->aIfs[iInterface];
7061 PATADEVSTATER3 pIfR3 = &pCtlR3->aIfs[iInterface];
7062
7063 /* the usual paranoia */
7064 AssertRelease(!pIfR3->pDrvBase);
7065 AssertRelease(!pIfR3->pDrvMedia);
7066 Assert(pIf->iLUN == iLUN);
7067
7068 /*
7069 * Try attach the block device and get the interfaces,
7070 * required as well as optional.
7071 */
7072 int rc = PDMDevHlpDriverAttach(pDevIns, pIf->iLUN, &pIfR3->IBase, &pIfR3->pDrvBase, NULL);
7073 if (RT_SUCCESS(rc))
7074 {
7075 rc = ataR3ConfigLun(pIf, pIfR3);
7076 /*
7077 * In case there is a medium inserted.
7078 */
7079 ataR3MediumInserted(pIf);
7080 ataR3MediumTypeSet(pIf, ATA_MEDIA_TYPE_UNKNOWN);
7081 }
7082 else
7083 AssertMsgFailed(("Failed to attach LUN#%d. rc=%Rrc\n", pIf->iLUN, rc));
7084
7085 if (RT_FAILURE(rc))
7086 {
7087 pIfR3->pDrvBase = NULL;
7088 pIfR3->pDrvMedia = NULL;
7089 pIfR3->pDrvMount = NULL;
7090 pIf->fPresent = false;
7091 }
7092 return rc;
7093}
7094
7095
7096/**
7097 * Resume notification.
7098 *
7099 * @returns VBox status code.
7100 * @param pDevIns The device instance data.
7101 */
7102static DECLCALLBACK(void) ataR3Resume(PPDMDEVINS pDevIns)
7103{
7104 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE);
7105 PATASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PATASTATECC);
7106
7107 Log(("%s:\n", __FUNCTION__));
7108 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
7109 {
7110 if (pThis->aCts[i].fRedo && pThis->aCts[i].fRedoIdle)
7111 {
7112 int rc = RTSemEventSignal(pThisCC->aCts[i].hSuspendIOSem);
7113 AssertRC(rc);
7114 }
7115 }
7116 return;
7117}
7118
7119
7120/**
7121 * Checks if all (both) the async I/O threads have quiesced.
7122 *
7123 * @returns true on success.
7124 * @returns false when one or more threads is still processing.
7125 * @param pDevIns Pointer to the PDM device instance.
7126 */
7127static bool ataR3AllAsyncIOIsIdle(PPDMDEVINS pDevIns)
7128{
7129 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE);
7130 PATASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PATASTATECC);
7131
7132 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
7133 if (pThisCC->aCts[i].hAsyncIOThread != NIL_RTTHREAD)
7134 {
7135 bool fRc = ataR3AsyncIOIsIdle(pDevIns, &pThis->aCts[i], false /*fStrict*/);
7136 if (!fRc)
7137 {
7138 /* Make it signal PDM & itself when its done */
7139 int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->aCts[i].AsyncIORequestLock, VERR_IGNORED);
7140 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->aCts[i].AsyncIORequestLock, rcLock);
7141
7142 ASMAtomicWriteBool(&pThisCC->aCts[i].fSignalIdle, true);
7143
7144 PDMDevHlpCritSectLeave(pDevIns, &pThis->aCts[i].AsyncIORequestLock);
7145
7146 fRc = ataR3AsyncIOIsIdle(pDevIns, &pThis->aCts[i], false /*fStrict*/);
7147 if (!fRc)
7148 {
7149#if 0 /** @todo Need to do some time tracking here... */
7150 LogRel(("PIIX3 ATA: Ctl#%u is still executing, DevSel=%d AIOIf=%d CmdIf0=%#04x CmdIf1=%#04x\n",
7151 i, pThis->aCts[i].iSelectedIf, pThis->aCts[i].iAIOIf,
7152 pThis->aCts[i].aIfs[0].uATARegCommand, pThis->aCts[i].aIfs[1].uATARegCommand));
7153#endif
7154 return false;
7155 }
7156 }
7157 ASMAtomicWriteBool(&pThisCC->aCts[i].fSignalIdle, false);
7158 }
7159 return true;
7160}
7161
7162/**
7163 * Prepare state save and load operation.
7164 *
7165 * @returns VBox status code.
7166 * @param pDevIns Device instance of the device which registered the data unit.
7167 * @param pSSM SSM operation handle.
7168 */
7169static DECLCALLBACK(int) ataR3SaveLoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
7170{
7171 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE);
7172 RT_NOREF(pSSM);
7173
7174 /* sanity - the suspend notification will wait on the async stuff. */
7175 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
7176 AssertLogRelMsgReturn(ataR3AsyncIOIsIdle(pDevIns, &pThis->aCts[i], false /*fStrict*/),
7177 ("i=%u\n", i),
7178 VERR_SSM_IDE_ASYNC_TIMEOUT);
7179 return VINF_SUCCESS;
7180}
7181
7182/**
7183 * @copydoc FNSSMDEVLIVEEXEC
7184 */
7185static DECLCALLBACK(int) ataR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
7186{
7187 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE);
7188 PATASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PATASTATECC);
7189 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
7190 RT_NOREF(uPass);
7191
7192 pHlp->pfnSSMPutU8(pSSM, (uint8_t)pThis->enmChipset);
7193 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
7194 {
7195 pHlp->pfnSSMPutBool(pSSM, true); /* For controller enabled / disabled. */
7196 for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++)
7197 {
7198 pHlp->pfnSSMPutBool(pSSM, pThisCC->aCts[i].aIfs[j].pDrvBase != NULL);
7199 pHlp->pfnSSMPutStrZ(pSSM, pThis->aCts[i].aIfs[j].szSerialNumber);
7200 pHlp->pfnSSMPutStrZ(pSSM, pThis->aCts[i].aIfs[j].szFirmwareRevision);
7201 pHlp->pfnSSMPutStrZ(pSSM, pThis->aCts[i].aIfs[j].szModelNumber);
7202 }
7203 }
7204
7205 return VINF_SSM_DONT_CALL_AGAIN;
7206}
7207
7208/**
7209 * @copydoc FNSSMDEVSAVEEXEC
7210 */
7211static DECLCALLBACK(int) ataR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
7212{
7213 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE);
7214 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
7215
7216 ataR3LiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
7217
7218 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
7219 {
7220 pHlp->pfnSSMPutU8(pSSM, pThis->aCts[i].iSelectedIf);
7221 pHlp->pfnSSMPutU8(pSSM, pThis->aCts[i].iAIOIf);
7222 pHlp->pfnSSMPutU8(pSSM, pThis->aCts[i].uAsyncIOState);
7223 pHlp->pfnSSMPutBool(pSSM, pThis->aCts[i].fChainedTransfer);
7224 pHlp->pfnSSMPutBool(pSSM, pThis->aCts[i].fReset);
7225 pHlp->pfnSSMPutBool(pSSM, pThis->aCts[i].fRedo);
7226 pHlp->pfnSSMPutBool(pSSM, pThis->aCts[i].fRedoIdle);
7227 pHlp->pfnSSMPutBool(pSSM, pThis->aCts[i].fRedoDMALastDesc);
7228 pHlp->pfnSSMPutMem(pSSM, &pThis->aCts[i].BmDma, sizeof(pThis->aCts[i].BmDma));
7229 pHlp->pfnSSMPutGCPhys32(pSSM, pThis->aCts[i].GCPhysFirstDMADesc);
7230 pHlp->pfnSSMPutGCPhys32(pSSM, pThis->aCts[i].GCPhysLastDMADesc);
7231 pHlp->pfnSSMPutGCPhys32(pSSM, pThis->aCts[i].GCPhysRedoDMABuffer);
7232 pHlp->pfnSSMPutU32(pSSM, pThis->aCts[i].cbRedoDMABuffer);
7233
7234 for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++)
7235 {
7236 pHlp->pfnSSMPutBool(pSSM, pThis->aCts[i].aIfs[j].fLBA48);
7237 pHlp->pfnSSMPutBool(pSSM, pThis->aCts[i].aIfs[j].fATAPI);
7238 pHlp->pfnSSMPutBool(pSSM, pThis->aCts[i].aIfs[j].fIrqPending);
7239 pHlp->pfnSSMPutU8(pSSM, pThis->aCts[i].aIfs[j].cMultSectors);
7240 pHlp->pfnSSMPutU32(pSSM, pThis->aCts[i].aIfs[j].XCHSGeometry.cCylinders);
7241 pHlp->pfnSSMPutU32(pSSM, pThis->aCts[i].aIfs[j].XCHSGeometry.cHeads);
7242 pHlp->pfnSSMPutU32(pSSM, pThis->aCts[i].aIfs[j].XCHSGeometry.cSectors);
7243 pHlp->pfnSSMPutU32(pSSM, pThis->aCts[i].aIfs[j].cSectorsPerIRQ);
7244 pHlp->pfnSSMPutU64(pSSM, pThis->aCts[i].aIfs[j].cTotalSectors);
7245 pHlp->pfnSSMPutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegFeature);
7246 pHlp->pfnSSMPutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegFeatureHOB);
7247 pHlp->pfnSSMPutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegError);
7248 pHlp->pfnSSMPutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegNSector);
7249 pHlp->pfnSSMPutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegNSectorHOB);
7250 pHlp->pfnSSMPutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegSector);
7251 pHlp->pfnSSMPutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegSectorHOB);
7252 pHlp->pfnSSMPutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegLCyl);
7253 pHlp->pfnSSMPutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegLCylHOB);
7254 pHlp->pfnSSMPutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegHCyl);
7255 pHlp->pfnSSMPutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegHCylHOB);
7256 pHlp->pfnSSMPutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegSelect);
7257 pHlp->pfnSSMPutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegStatus);
7258 pHlp->pfnSSMPutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegCommand);
7259 pHlp->pfnSSMPutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegDevCtl);
7260 pHlp->pfnSSMPutU8(pSSM, pThis->aCts[i].aIfs[j].uATATransferMode);
7261 pHlp->pfnSSMPutU8(pSSM, pThis->aCts[i].aIfs[j].uTxDir);
7262 pHlp->pfnSSMPutU8(pSSM, pThis->aCts[i].aIfs[j].iBeginTransfer);
7263 pHlp->pfnSSMPutU8(pSSM, pThis->aCts[i].aIfs[j].iSourceSink);
7264 pHlp->pfnSSMPutBool(pSSM, pThis->aCts[i].aIfs[j].fDMA);
7265 pHlp->pfnSSMPutBool(pSSM, pThis->aCts[i].aIfs[j].fATAPITransfer);
7266 pHlp->pfnSSMPutU32(pSSM, pThis->aCts[i].aIfs[j].cbTotalTransfer);
7267 pHlp->pfnSSMPutU32(pSSM, pThis->aCts[i].aIfs[j].cbElementaryTransfer);
7268 pHlp->pfnSSMPutU32(pSSM, pThis->aCts[i].aIfs[j].iIOBufferCur);
7269 pHlp->pfnSSMPutU32(pSSM, pThis->aCts[i].aIfs[j].iIOBufferEnd);
7270 pHlp->pfnSSMPutU32(pSSM, pThis->aCts[i].aIfs[j].iIOBufferPIODataStart);
7271 pHlp->pfnSSMPutU32(pSSM, pThis->aCts[i].aIfs[j].iIOBufferPIODataEnd);
7272 pHlp->pfnSSMPutU32(pSSM, pThis->aCts[i].aIfs[j].iCurLBA);
7273 pHlp->pfnSSMPutU32(pSSM, pThis->aCts[i].aIfs[j].cbATAPISector);
7274 pHlp->pfnSSMPutMem(pSSM, &pThis->aCts[i].aIfs[j].abATAPICmd, sizeof(pThis->aCts[i].aIfs[j].abATAPICmd));
7275 pHlp->pfnSSMPutMem(pSSM, &pThis->aCts[i].aIfs[j].abATAPISense, sizeof(pThis->aCts[i].aIfs[j].abATAPISense));
7276 pHlp->pfnSSMPutU8(pSSM, pThis->aCts[i].aIfs[j].cNotifiedMediaChange);
7277 pHlp->pfnSSMPutU32(pSSM, pThis->aCts[i].aIfs[j].MediaEventStatus);
7278 pHlp->pfnSSMPutMem(pSSM, &pThis->aCts[i].aIfs[j].Led, sizeof(pThis->aCts[i].aIfs[j].Led));
7279 pHlp->pfnSSMPutU32(pSSM, pThis->aCts[i].aIfs[j].cbIOBuffer);
7280 if (pThis->aCts[i].aIfs[j].cbIOBuffer)
7281 pHlp->pfnSSMPutMem(pSSM, pThis->aCts[i].aIfs[j].abIOBuffer, pThis->aCts[i].aIfs[j].cbIOBuffer);
7282 }
7283 }
7284
7285 return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX); /* sanity/terminator */
7286}
7287
7288/**
7289 * Converts the LUN number into a message string.
7290 */
7291static const char *ataR3StringifyLun(unsigned iLun)
7292{
7293 switch (iLun)
7294 {
7295 case 0: return "primary master";
7296 case 1: return "primary slave";
7297 case 2: return "secondary master";
7298 case 3: return "secondary slave";
7299 default: AssertFailedReturn("unknown lun");
7300 }
7301}
7302
7303/**
7304 * FNSSMDEVLOADEXEC
7305 */
7306static DECLCALLBACK(int) ataR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
7307{
7308 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE);
7309 PATASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PATASTATECC);
7310 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
7311 int rc;
7312 uint32_t u32;
7313
7314 if ( uVersion != ATA_SAVED_STATE_VERSION
7315 && uVersion != ATA_SAVED_STATE_VERSION_WITHOUT_ATA_ILBA
7316 && uVersion != ATA_SAVED_STATE_VERSION_VBOX_30
7317 && uVersion != ATA_SAVED_STATE_VERSION_WITHOUT_FULL_SENSE
7318 && uVersion != ATA_SAVED_STATE_VERSION_WITHOUT_EVENT_STATUS
7319 && uVersion != ATA_SAVED_STATE_VERSION_WITH_BOOL_TYPE)
7320 {
7321 AssertMsgFailed(("uVersion=%d\n", uVersion));
7322 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
7323 }
7324
7325 /*
7326 * Verify the configuration.
7327 */
7328 if (uVersion > ATA_SAVED_STATE_VERSION_VBOX_30)
7329 {
7330 uint8_t u8Type;
7331 rc = pHlp->pfnSSMGetU8(pSSM, &u8Type);
7332 AssertRCReturn(rc, rc);
7333 if ((CHIPSET)u8Type != pThis->enmChipset)
7334 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: enmChipset - saved=%u config=%u"), u8Type, pThis->enmChipset);
7335
7336 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
7337 {
7338 bool fEnabled;
7339 rc = pHlp->pfnSSMGetBool(pSSM, &fEnabled);
7340 AssertRCReturn(rc, rc);
7341 if (!fEnabled)
7342 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Ctr#%u onfig mismatch: fEnabled != true"), i);
7343
7344 for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++)
7345 {
7346 ATADEVSTATE const *pIf = &pThis->aCts[i].aIfs[j];
7347 ATADEVSTATER3 const *pIfR3 = &pThisCC->aCts[i].aIfs[j];
7348
7349 bool fInUse;
7350 rc = pHlp->pfnSSMGetBool(pSSM, &fInUse);
7351 AssertRCReturn(rc, rc);
7352 if (fInUse != (pIfR3->pDrvBase != NULL))
7353 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS,
7354 N_("The %s VM is missing a %s device. Please make sure the source and target VMs have compatible storage configurations"),
7355 fInUse ? "target" : "source", ataR3StringifyLun(pIf->iLUN) );
7356
7357 char szSerialNumber[ATA_SERIAL_NUMBER_LENGTH+1];
7358 rc = pHlp->pfnSSMGetStrZ(pSSM, szSerialNumber, sizeof(szSerialNumber));
7359 AssertRCReturn(rc, rc);
7360 if (strcmp(szSerialNumber, pIf->szSerialNumber))
7361 LogRel(("PIIX3 ATA: LUN#%u config mismatch: Serial number - saved='%s' config='%s'\n",
7362 pIf->iLUN, szSerialNumber, pIf->szSerialNumber));
7363
7364 char szFirmwareRevision[ATA_FIRMWARE_REVISION_LENGTH+1];
7365 rc = pHlp->pfnSSMGetStrZ(pSSM, szFirmwareRevision, sizeof(szFirmwareRevision));
7366 AssertRCReturn(rc, rc);
7367 if (strcmp(szFirmwareRevision, pIf->szFirmwareRevision))
7368 LogRel(("PIIX3 ATA: LUN#%u config mismatch: Firmware revision - saved='%s' config='%s'\n",
7369 pIf->iLUN, szFirmwareRevision, pIf->szFirmwareRevision));
7370
7371 char szModelNumber[ATA_MODEL_NUMBER_LENGTH+1];
7372 rc = pHlp->pfnSSMGetStrZ(pSSM, szModelNumber, sizeof(szModelNumber));
7373 AssertRCReturn(rc, rc);
7374 if (strcmp(szModelNumber, pIf->szModelNumber))
7375 LogRel(("PIIX3 ATA: LUN#%u config mismatch: Model number - saved='%s' config='%s'\n",
7376 pIf->iLUN, szModelNumber, pIf->szModelNumber));
7377 }
7378 }
7379 }
7380 if (uPass != SSM_PASS_FINAL)
7381 return VINF_SUCCESS;
7382
7383 /*
7384 * Restore valid parts of the ATASTATE structure
7385 */
7386 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
7387 {
7388 /* integrity check */
7389 if (!ataR3AsyncIOIsIdle(pDevIns, &pThis->aCts[i], false))
7390 {
7391 AssertMsgFailed(("Async I/O for controller %d is active\n", i));
7392 return VERR_INTERNAL_ERROR_4;
7393 }
7394
7395 rc = pHlp->pfnSSMGetU8(pSSM, &pThis->aCts[i].iSelectedIf);
7396 AssertRCReturn(rc, rc);
7397 AssertLogRelMsgStmt(pThis->aCts[i].iSelectedIf == (pThis->aCts[i].iSelectedIf & ATA_SELECTED_IF_MASK),
7398 ("iSelectedIf = %d\n", pThis->aCts[i].iSelectedIf),
7399 pThis->aCts[i].iSelectedIf &= ATA_SELECTED_IF_MASK);
7400 rc = pHlp->pfnSSMGetU8(pSSM, &pThis->aCts[i].iAIOIf);
7401 AssertRCReturn(rc, rc);
7402 AssertLogRelMsgStmt(pThis->aCts[i].iAIOIf == (pThis->aCts[i].iAIOIf & ATA_SELECTED_IF_MASK),
7403 ("iAIOIf = %d\n", pThis->aCts[i].iAIOIf),
7404 pThis->aCts[i].iAIOIf &= ATA_SELECTED_IF_MASK);
7405 pHlp->pfnSSMGetU8(pSSM, &pThis->aCts[i].uAsyncIOState);
7406 pHlp->pfnSSMGetBool(pSSM, &pThis->aCts[i].fChainedTransfer);
7407 pHlp->pfnSSMGetBool(pSSM, &pThis->aCts[i].fReset);
7408 pHlp->pfnSSMGetBool(pSSM, &pThis->aCts[i].fRedo);
7409 pHlp->pfnSSMGetBool(pSSM, &pThis->aCts[i].fRedoIdle);
7410 pHlp->pfnSSMGetBool(pSSM, &pThis->aCts[i].fRedoDMALastDesc);
7411 pHlp->pfnSSMGetMem(pSSM, &pThis->aCts[i].BmDma, sizeof(pThis->aCts[i].BmDma));
7412 pHlp->pfnSSMGetGCPhys32(pSSM, &pThis->aCts[i].GCPhysFirstDMADesc);
7413 pHlp->pfnSSMGetGCPhys32(pSSM, &pThis->aCts[i].GCPhysLastDMADesc);
7414 pHlp->pfnSSMGetGCPhys32(pSSM, &pThis->aCts[i].GCPhysRedoDMABuffer);
7415 pHlp->pfnSSMGetU32(pSSM, &pThis->aCts[i].cbRedoDMABuffer);
7416
7417 for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++)
7418 {
7419 pHlp->pfnSSMGetBool(pSSM, &pThis->aCts[i].aIfs[j].fLBA48);
7420 pHlp->pfnSSMGetBool(pSSM, &pThis->aCts[i].aIfs[j].fATAPI);
7421 pHlp->pfnSSMGetBool(pSSM, &pThis->aCts[i].aIfs[j].fIrqPending);
7422 pHlp->pfnSSMGetU8(pSSM, &pThis->aCts[i].aIfs[j].cMultSectors);
7423 pHlp->pfnSSMGetU32(pSSM, &pThis->aCts[i].aIfs[j].XCHSGeometry.cCylinders);
7424 pHlp->pfnSSMGetU32(pSSM, &pThis->aCts[i].aIfs[j].XCHSGeometry.cHeads);
7425 pHlp->pfnSSMGetU32(pSSM, &pThis->aCts[i].aIfs[j].XCHSGeometry.cSectors);
7426 pHlp->pfnSSMGetU32(pSSM, &pThis->aCts[i].aIfs[j].cSectorsPerIRQ);
7427 pHlp->pfnSSMGetU64(pSSM, &pThis->aCts[i].aIfs[j].cTotalSectors);
7428 pHlp->pfnSSMGetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegFeature);
7429 pHlp->pfnSSMGetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegFeatureHOB);
7430 pHlp->pfnSSMGetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegError);
7431 pHlp->pfnSSMGetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegNSector);
7432 pHlp->pfnSSMGetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegNSectorHOB);
7433 pHlp->pfnSSMGetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegSector);
7434 pHlp->pfnSSMGetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegSectorHOB);
7435 pHlp->pfnSSMGetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegLCyl);
7436 pHlp->pfnSSMGetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegLCylHOB);
7437 pHlp->pfnSSMGetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegHCyl);
7438 pHlp->pfnSSMGetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegHCylHOB);
7439 pHlp->pfnSSMGetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegSelect);
7440 pHlp->pfnSSMGetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegStatus);
7441 pHlp->pfnSSMGetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegCommand);
7442 pHlp->pfnSSMGetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegDevCtl);
7443 pHlp->pfnSSMGetU8(pSSM, &pThis->aCts[i].aIfs[j].uATATransferMode);
7444 pHlp->pfnSSMGetU8(pSSM, &pThis->aCts[i].aIfs[j].uTxDir);
7445 pHlp->pfnSSMGetU8(pSSM, &pThis->aCts[i].aIfs[j].iBeginTransfer);
7446 pHlp->pfnSSMGetU8(pSSM, &pThis->aCts[i].aIfs[j].iSourceSink);
7447 pHlp->pfnSSMGetBool(pSSM, &pThis->aCts[i].aIfs[j].fDMA);
7448 pHlp->pfnSSMGetBool(pSSM, &pThis->aCts[i].aIfs[j].fATAPITransfer);
7449 pHlp->pfnSSMGetU32(pSSM, &pThis->aCts[i].aIfs[j].cbTotalTransfer);
7450 pHlp->pfnSSMGetU32(pSSM, &pThis->aCts[i].aIfs[j].cbElementaryTransfer);
7451 /* NB: cbPIOTransferLimit could be saved/restored but it's sufficient
7452 * to re-calculate it here, with a tiny risk that it could be
7453 * unnecessarily low for the current transfer only. Could be changed
7454 * when changing the saved state in the future.
7455 */
7456 pThis->aCts[i].aIfs[j].cbPIOTransferLimit = (pThis->aCts[i].aIfs[j].uATARegHCyl << 8) | pThis->aCts[i].aIfs[j].uATARegLCyl;
7457 pHlp->pfnSSMGetU32(pSSM, &pThis->aCts[i].aIfs[j].iIOBufferCur);
7458 pHlp->pfnSSMGetU32(pSSM, &pThis->aCts[i].aIfs[j].iIOBufferEnd);
7459 pHlp->pfnSSMGetU32(pSSM, &pThis->aCts[i].aIfs[j].iIOBufferPIODataStart);
7460 pHlp->pfnSSMGetU32(pSSM, &pThis->aCts[i].aIfs[j].iIOBufferPIODataEnd);
7461 pHlp->pfnSSMGetU32(pSSM, &pThis->aCts[i].aIfs[j].iCurLBA);
7462 pHlp->pfnSSMGetU32(pSSM, &pThis->aCts[i].aIfs[j].cbATAPISector);
7463 pHlp->pfnSSMGetMem(pSSM, &pThis->aCts[i].aIfs[j].abATAPICmd, sizeof(pThis->aCts[i].aIfs[j].abATAPICmd));
7464 if (uVersion > ATA_SAVED_STATE_VERSION_WITHOUT_FULL_SENSE)
7465 pHlp->pfnSSMGetMem(pSSM, pThis->aCts[i].aIfs[j].abATAPISense, sizeof(pThis->aCts[i].aIfs[j].abATAPISense));
7466 else
7467 {
7468 uint8_t uATAPISenseKey, uATAPIASC;
7469 memset(pThis->aCts[i].aIfs[j].abATAPISense, '\0', sizeof(pThis->aCts[i].aIfs[j].abATAPISense));
7470 pThis->aCts[i].aIfs[j].abATAPISense[0] = 0x70 | (1 << 7);
7471 pThis->aCts[i].aIfs[j].abATAPISense[7] = 10;
7472 pHlp->pfnSSMGetU8(pSSM, &uATAPISenseKey);
7473 pHlp->pfnSSMGetU8(pSSM, &uATAPIASC);
7474 pThis->aCts[i].aIfs[j].abATAPISense[2] = uATAPISenseKey & 0x0f;
7475 pThis->aCts[i].aIfs[j].abATAPISense[12] = uATAPIASC;
7476 }
7477 /** @todo triple-check this hack after passthrough is working */
7478 pHlp->pfnSSMGetU8(pSSM, &pThis->aCts[i].aIfs[j].cNotifiedMediaChange);
7479 if (uVersion > ATA_SAVED_STATE_VERSION_WITHOUT_EVENT_STATUS)
7480 pHlp->pfnSSMGetU32V(pSSM, &pThis->aCts[i].aIfs[j].MediaEventStatus);
7481 else
7482 pThis->aCts[i].aIfs[j].MediaEventStatus = ATA_EVENT_STATUS_UNCHANGED;
7483 pHlp->pfnSSMGetMem(pSSM, &pThis->aCts[i].aIfs[j].Led, sizeof(pThis->aCts[i].aIfs[j].Led));
7484
7485 uint32_t cbIOBuffer = 0;
7486 rc = pHlp->pfnSSMGetU32(pSSM, &cbIOBuffer);
7487 AssertRCReturn(rc, rc);
7488
7489 if ( (uVersion <= ATA_SAVED_STATE_VERSION_WITHOUT_ATA_ILBA)
7490 && !pThis->aCts[i].aIfs[j].fATAPI)
7491 {
7492 pThis->aCts[i].aIfs[j].iCurLBA = ataR3GetSector(&pThis->aCts[i].aIfs[j]);
7493 }
7494
7495 if (cbIOBuffer)
7496 {
7497 if (cbIOBuffer <= sizeof(pThis->aCts[i].aIfs[j].abIOBuffer))
7498 {
7499 if (pThis->aCts[i].aIfs[j].cbIOBuffer != cbIOBuffer)
7500 LogRel(("ATA: %u/%u: Restoring cbIOBuffer=%u; constructor set up %u!\n", i, j, cbIOBuffer, pThis->aCts[i].aIfs[j].cbIOBuffer));
7501 pThis->aCts[i].aIfs[j].cbIOBuffer = cbIOBuffer;
7502 pHlp->pfnSSMGetMem(pSSM, pThis->aCts[i].aIfs[j].abIOBuffer, cbIOBuffer);
7503 }
7504 else
7505 {
7506 LogRel(("ATA: %u/%u: Restoring cbIOBuffer=%u, only prepared %u!\n", i, j, cbIOBuffer, pThis->aCts[i].aIfs[j].cbIOBuffer));
7507 if (pHlp->pfnSSMHandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
7508 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS,
7509 N_("ATA: %u/%u: Restoring cbIOBuffer=%u, only prepared %u"),
7510 i, j, cbIOBuffer, pThis->aCts[i].aIfs[j].cbIOBuffer);
7511
7512 /* skip the buffer if we're loading for the debugger / animator. */
7513 pHlp->pfnSSMSkip(pSSM, cbIOBuffer);
7514 }
7515 }
7516 else
7517 AssertLogRelMsgStmt(pThis->aCts[i].aIfs[j].cbIOBuffer == 0,
7518 ("ATA: %u/%u: cbIOBuffer=%u restoring zero!\n", i, j, pThis->aCts[i].aIfs[j].cbIOBuffer),
7519 pThis->aCts[i].aIfs[j].cbIOBuffer = 0);
7520 }
7521 }
7522 if (uVersion <= ATA_SAVED_STATE_VERSION_VBOX_30)
7523 PDMDEVHLP_SSM_GET_ENUM8_RET(pHlp, pSSM, pThis->enmChipset, CHIPSET);
7524
7525 rc = pHlp->pfnSSMGetU32(pSSM, &u32);
7526 if (RT_FAILURE(rc))
7527 return rc;
7528 if (u32 != ~0U)
7529 {
7530 AssertMsgFailed(("u32=%#x expected ~0\n", u32));
7531 rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
7532 return rc;
7533 }
7534
7535 return VINF_SUCCESS;
7536}
7537
7538
7539/**
7540 * Callback employed by ataSuspend and ataR3PowerOff.
7541 *
7542 * @returns true if we've quiesced, false if we're still working.
7543 * @param pDevIns The device instance.
7544 */
7545static DECLCALLBACK(bool) ataR3IsAsyncSuspendOrPowerOffDone(PPDMDEVINS pDevIns)
7546{
7547 return ataR3AllAsyncIOIsIdle(pDevIns);
7548}
7549
7550
7551/**
7552 * Common worker for ataSuspend and ataR3PowerOff.
7553 */
7554static void ataR3SuspendOrPowerOff(PPDMDEVINS pDevIns)
7555{
7556 if (!ataR3AllAsyncIOIsIdle(pDevIns))
7557 PDMDevHlpSetAsyncNotification(pDevIns, ataR3IsAsyncSuspendOrPowerOffDone);
7558}
7559
7560
7561/**
7562 * Power Off notification.
7563 *
7564 * @returns VBox status code.
7565 * @param pDevIns The device instance data.
7566 */
7567static DECLCALLBACK(void) ataR3PowerOff(PPDMDEVINS pDevIns)
7568{
7569 Log(("%s:\n", __FUNCTION__));
7570 ataR3SuspendOrPowerOff(pDevIns);
7571}
7572
7573
7574/**
7575 * Suspend notification.
7576 *
7577 * @returns VBox status code.
7578 * @param pDevIns The device instance data.
7579 */
7580static DECLCALLBACK(void) ataR3Suspend(PPDMDEVINS pDevIns)
7581{
7582 Log(("%s:\n", __FUNCTION__));
7583 ataR3SuspendOrPowerOff(pDevIns);
7584}
7585
7586
7587/**
7588 * Callback employed by ataR3Reset.
7589 *
7590 * @returns true if we've quiesced, false if we're still working.
7591 * @param pDevIns The device instance.
7592 */
7593static DECLCALLBACK(bool) ataR3IsAsyncResetDone(PPDMDEVINS pDevIns)
7594{
7595 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE);
7596
7597 if (!ataR3AllAsyncIOIsIdle(pDevIns))
7598 return false;
7599
7600 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
7601 {
7602 int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->aCts[i].lock, VERR_INTERNAL_ERROR);
7603 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->aCts[i].lock, rcLock);
7604
7605 for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++)
7606 ataR3ResetDevice(pDevIns, &pThis->aCts[i], &pThis->aCts[i].aIfs[j]);
7607
7608 PDMDevHlpCritSectLeave(pDevIns, &pThis->aCts[i].lock);
7609 }
7610 return true;
7611}
7612
7613
7614/**
7615 * Common reset worker for ataR3Reset and ataR3Construct.
7616 *
7617 * @returns VBox status code.
7618 * @param pDevIns The device instance data.
7619 * @param fConstruct Indicates who is calling.
7620 */
7621static int ataR3ResetCommon(PPDMDEVINS pDevIns, bool fConstruct)
7622{
7623 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE);
7624 PATASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PATASTATECC);
7625
7626 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
7627 {
7628 int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->aCts[i].lock, VERR_INTERNAL_ERROR);
7629 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->aCts[i].lock, rcLock);
7630
7631 pThis->aCts[i].iSelectedIf = 0;
7632 pThis->aCts[i].iAIOIf = 0;
7633 pThis->aCts[i].BmDma.u8Cmd = 0;
7634 /* Report that both drives present on the bus are in DMA mode. This
7635 * pretends that there is a BIOS that has set it up. Normal reset
7636 * default is 0x00. */
7637 pThis->aCts[i].BmDma.u8Status = (pThisCC->aCts[i].aIfs[0].pDrvBase != NULL ? BM_STATUS_D0DMA : 0)
7638 | (pThisCC->aCts[i].aIfs[1].pDrvBase != NULL ? BM_STATUS_D1DMA : 0);
7639 pThis->aCts[i].BmDma.GCPhysAddr = 0;
7640
7641 pThis->aCts[i].fReset = true;
7642 pThis->aCts[i].fRedo = false;
7643 pThis->aCts[i].fRedoIdle = false;
7644 ataR3AsyncIOClearRequests(pDevIns, &pThis->aCts[i]);
7645 Log2(("%s: Ctl#%d: message to async I/O thread, reset controller\n", __FUNCTION__, i));
7646 ataHCAsyncIOPutRequest(pDevIns, &pThis->aCts[i], &g_ataResetARequest);
7647 ataHCAsyncIOPutRequest(pDevIns, &pThis->aCts[i], &g_ataResetCRequest);
7648
7649 PDMDevHlpCritSectLeave(pDevIns, &pThis->aCts[i].lock);
7650 }
7651
7652 int rcRet = VINF_SUCCESS;
7653 if (!fConstruct)
7654 {
7655 /*
7656 * Setup asynchronous notification completion if the requests haven't
7657 * completed yet.
7658 */
7659 if (!ataR3IsAsyncResetDone(pDevIns))
7660 PDMDevHlpSetAsyncNotification(pDevIns, ataR3IsAsyncResetDone);
7661 }
7662 else
7663 {
7664 /*
7665 * Wait for the requests for complete.
7666 *
7667 * Would be real nice if we could do it all from EMT(0) and not
7668 * involve the worker threads, then we could dispense with all the
7669 * waiting and semaphore ping-pong here...
7670 */
7671 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
7672 {
7673 if (pThisCC->aCts[i].hAsyncIOThread != NIL_RTTHREAD)
7674 {
7675 int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->aCts[i].AsyncIORequestLock, VERR_IGNORED);
7676 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->aCts[i].AsyncIORequestLock, rc);
7677
7678 ASMAtomicWriteBool(&pThisCC->aCts[i].fSignalIdle, true);
7679 rc = RTThreadUserReset(pThisCC->aCts[i].hAsyncIOThread);
7680 AssertRC(rc);
7681
7682 rc = PDMDevHlpCritSectLeave(pDevIns, &pThis->aCts[i].AsyncIORequestLock);
7683 AssertRC(rc);
7684
7685 if (!ataR3AsyncIOIsIdle(pDevIns, &pThis->aCts[i], false /*fStrict*/))
7686 {
7687 rc = RTThreadUserWait(pThisCC->aCts[i].hAsyncIOThread, 30*1000 /*ms*/);
7688 if (RT_FAILURE(rc))
7689 rc = RTThreadUserWait(pThisCC->aCts[i].hAsyncIOThread, 1000 /*ms*/);
7690 if (RT_FAILURE(rc))
7691 {
7692 AssertRC(rc);
7693 rcRet = rc;
7694 }
7695 }
7696 }
7697 ASMAtomicWriteBool(&pThisCC->aCts[i].fSignalIdle, false);
7698 }
7699 if (RT_SUCCESS(rcRet))
7700 {
7701 rcRet = ataR3IsAsyncResetDone(pDevIns) ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
7702 AssertRC(rcRet);
7703 }
7704 }
7705 return rcRet;
7706}
7707
7708/**
7709 * Reset notification.
7710 *
7711 * @param pDevIns The device instance data.
7712 */
7713static DECLCALLBACK(void) ataR3Reset(PPDMDEVINS pDevIns)
7714{
7715 ataR3ResetCommon(pDevIns, false /*fConstruct*/);
7716}
7717
7718/**
7719 * Destroy a driver instance.
7720 *
7721 * Most VM resources are freed by the VM. This callback is provided so that any non-VM
7722 * resources can be freed correctly.
7723 *
7724 * @param pDevIns The device instance data.
7725 */
7726static DECLCALLBACK(int) ataR3Destruct(PPDMDEVINS pDevIns)
7727{
7728 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
7729 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE);
7730 PATASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PATASTATECC);
7731 int rc;
7732
7733 Log(("ataR3Destruct\n"));
7734
7735 /*
7736 * Tell the async I/O threads to terminate.
7737 */
7738 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
7739 {
7740 if (pThisCC->aCts[i].hAsyncIOThread != NIL_RTTHREAD)
7741 {
7742 ASMAtomicWriteU32(&pThisCC->aCts[i].fShutdown, true);
7743 rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->aCts[i].hAsyncIOSem);
7744 AssertRC(rc);
7745 rc = RTSemEventSignal(pThisCC->aCts[i].hSuspendIOSem);
7746 AssertRC(rc);
7747 }
7748 }
7749
7750 /*
7751 * Wait for the threads to terminate before destroying their resources.
7752 */
7753 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
7754 {
7755 if (pThisCC->aCts[i].hAsyncIOThread != NIL_RTTHREAD)
7756 {
7757 rc = RTThreadWait(pThisCC->aCts[i].hAsyncIOThread, 30000 /* 30 s*/, NULL);
7758 if (RT_SUCCESS(rc))
7759 pThisCC->aCts[i].hAsyncIOThread = NIL_RTTHREAD;
7760 else
7761 LogRel(("PIIX3 ATA Dtor: Ctl#%u is still executing, DevSel=%d AIOIf=%d CmdIf0=%#04x CmdIf1=%#04x rc=%Rrc\n",
7762 i, pThis->aCts[i].iSelectedIf, pThis->aCts[i].iAIOIf,
7763 pThis->aCts[i].aIfs[0].uATARegCommand, pThis->aCts[i].aIfs[1].uATARegCommand, rc));
7764 }
7765 }
7766
7767 /*
7768 * Free resources.
7769 */
7770 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
7771 {
7772 if (PDMDevHlpCritSectIsInitialized(pDevIns, &pThis->aCts[i].AsyncIORequestLock))
7773 PDMDevHlpCritSectDelete(pDevIns, &pThis->aCts[i].AsyncIORequestLock);
7774 if (pThis->aCts[i].hAsyncIOSem != NIL_SUPSEMEVENT)
7775 {
7776 PDMDevHlpSUPSemEventClose(pDevIns, pThis->aCts[i].hAsyncIOSem);
7777 pThis->aCts[i].hAsyncIOSem = NIL_SUPSEMEVENT;
7778 }
7779 if (pThisCC->aCts[i].hSuspendIOSem != NIL_RTSEMEVENT)
7780 {
7781 RTSemEventDestroy(pThisCC->aCts[i].hSuspendIOSem);
7782 pThisCC->aCts[i].hSuspendIOSem = NIL_RTSEMEVENT;
7783 }
7784
7785 /* try one final time */
7786 if (pThisCC->aCts[i].hAsyncIOThread != NIL_RTTHREAD)
7787 {
7788 rc = RTThreadWait(pThisCC->aCts[i].hAsyncIOThread, 1 /*ms*/, NULL);
7789 if (RT_SUCCESS(rc))
7790 {
7791 pThisCC->aCts[i].hAsyncIOThread = NIL_RTTHREAD;
7792 LogRel(("PIIX3 ATA Dtor: Ctl#%u actually completed.\n", i));
7793 }
7794 }
7795
7796 for (uint32_t iIf = 0; iIf < RT_ELEMENTS(pThis->aCts[i].aIfs); iIf++)
7797 {
7798 if (pThisCC->aCts[i].aIfs[iIf].pTrackList)
7799 {
7800 ATAPIPassthroughTrackListDestroy(pThisCC->aCts[i].aIfs[iIf].pTrackList);
7801 pThisCC->aCts[i].aIfs[iIf].pTrackList = NULL;
7802 }
7803 }
7804 }
7805
7806 return VINF_SUCCESS;
7807}
7808
7809/**
7810 * Convert config value to DEVPCBIOSBOOT.
7811 *
7812 * @returns VBox status code.
7813 * @param pDevIns The device instance data.
7814 * @param pCfg Configuration handle.
7815 * @param penmChipset Where to store the chipset type.
7816 */
7817static int ataR3ControllerFromCfg(PPDMDEVINS pDevIns, PCFGMNODE pCfg, CHIPSET *penmChipset)
7818{
7819 char szType[20];
7820
7821 int rc = pDevIns->pHlpR3->pfnCFGMQueryStringDef(pCfg, "Type", &szType[0], sizeof(szType), "PIIX4");
7822 if (RT_FAILURE(rc))
7823 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
7824 N_("Configuration error: Querying \"Type\" as a string failed"));
7825 if (!strcmp(szType, "PIIX3"))
7826 *penmChipset = CHIPSET_PIIX3;
7827 else if (!strcmp(szType, "PIIX4"))
7828 *penmChipset = CHIPSET_PIIX4;
7829 else if (!strcmp(szType, "ICH6"))
7830 *penmChipset = CHIPSET_ICH6;
7831 else
7832 {
7833 PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
7834 N_("Configuration error: The \"Type\" value \"%s\" is unknown"),
7835 szType);
7836 rc = VERR_INTERNAL_ERROR;
7837 }
7838 return rc;
7839}
7840
7841/**
7842 * @interface_method_impl{PDMDEVREG,pfnConstruct}
7843 */
7844static DECLCALLBACK(int) ataR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
7845{
7846 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
7847 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE);
7848 PATASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PATASTATER3);
7849 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
7850 PPDMIBASE pBase;
7851 int rc;
7852 uint32_t msDelayIRQ;
7853
7854 Assert(iInstance == 0);
7855
7856 /*
7857 * Initialize NIL handle values (for the destructor).
7858 */
7859 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
7860 {
7861 pThis->aCts[i].iCtl = i;
7862 pThis->aCts[i].hAsyncIOSem = NIL_SUPSEMEVENT;
7863 pThis->aCts[i].hIoPorts1First = NIL_IOMIOPORTHANDLE;
7864 pThis->aCts[i].hIoPorts1Other = NIL_IOMIOPORTHANDLE;
7865 pThis->aCts[i].hIoPorts2 = NIL_IOMIOPORTHANDLE;
7866 pThis->aCts[i].hIoPortsEmpty1 = NIL_IOMIOPORTHANDLE;
7867 pThis->aCts[i].hIoPortsEmpty2 = NIL_IOMIOPORTHANDLE;
7868
7869 pThisCC->aCts[i].iCtl = i;
7870 pThisCC->aCts[i].hSuspendIOSem = NIL_RTSEMEVENT;
7871 pThisCC->aCts[i].hAsyncIOThread = NIL_RTTHREAD;
7872 }
7873
7874 /*
7875 * Validate and read configuration.
7876 */
7877 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "IRQDelay|Type", "PrimaryMaster|PrimarySlave|SecondaryMaster|SecondarySlave");
7878
7879 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "IRQDelay", &msDelayIRQ, 0);
7880 if (RT_FAILURE(rc))
7881 return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 configuration error: failed to read IRQDelay as integer"));
7882 Log(("%s: msDelayIRQ=%d\n", __FUNCTION__, msDelayIRQ));
7883 Assert(msDelayIRQ < 50);
7884
7885 CHIPSET enmChipset = CHIPSET_PIIX3;
7886 rc = ataR3ControllerFromCfg(pDevIns, pCfg, &enmChipset);
7887 if (RT_FAILURE(rc))
7888 return rc;
7889 pThis->enmChipset = enmChipset;
7890
7891 /*
7892 * Initialize data (most of it anyway).
7893 */
7894 /* Status LUN. */
7895 pThisCC->IBase.pfnQueryInterface = ataR3Status_QueryInterface;
7896 pThisCC->ILeds.pfnQueryStatusLed = ataR3Status_QueryStatusLed;
7897
7898 /* PCI configuration space. */
7899 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
7900 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
7901 PDMPciDevSetVendorId(pPciDev, 0x8086); /* Intel */
7902
7903 /*
7904 * When adding more IDE chipsets, don't forget to update pci_bios_init_device()
7905 * as it explicitly checks for PCI id for IDE controllers.
7906 */
7907 switch (enmChipset)
7908 {
7909 case CHIPSET_ICH6:
7910 PDMPciDevSetDeviceId(pPciDev, 0x269e); /* ICH6 IDE */
7911 /** @todo do we need it? Do we need anything else? */
7912 PDMPciDevSetByte(pPciDev, 0x48, 0x00); /* UDMACTL */
7913 PDMPciDevSetByte(pPciDev, 0x4A, 0x00); /* UDMATIM */
7914 PDMPciDevSetByte(pPciDev, 0x4B, 0x00);
7915 {
7916 /*
7917 * See www.intel.com/Assets/PDF/manual/298600.pdf p. 30
7918 * Report
7919 * WR_Ping-Pong_EN: must be set
7920 * PCR0, PCR1: 80-pin primary cable reporting for both disks
7921 * SCR0, SCR1: 80-pin secondary cable reporting for both disks
7922 */
7923 uint16_t u16Config = (1<<10) | (1<<7) | (1<<6) | (1<<5) | (1<<4);
7924 PDMPciDevSetByte(pPciDev, 0x54, u16Config & 0xff);
7925 PDMPciDevSetByte(pPciDev, 0x55, u16Config >> 8);
7926 }
7927 break;
7928 case CHIPSET_PIIX4:
7929 PDMPciDevSetDeviceId(pPciDev, 0x7111); /* PIIX4 IDE */
7930 PDMPciDevSetRevisionId(pPciDev, 0x01); /* PIIX4E */
7931 PDMPciDevSetByte(pPciDev, 0x48, 0x00); /* UDMACTL */
7932 PDMPciDevSetByte(pPciDev, 0x4A, 0x00); /* UDMATIM */
7933 PDMPciDevSetByte(pPciDev, 0x4B, 0x00);
7934 break;
7935 case CHIPSET_PIIX3:
7936 PDMPciDevSetDeviceId(pPciDev, 0x7010); /* PIIX3 IDE */
7937 break;
7938 default:
7939 AssertMsgFailed(("Unsupported IDE chipset type: %d\n", enmChipset));
7940 }
7941
7942 /** @todo
7943 * This is the job of the BIOS / EFI!
7944 *
7945 * The same is done in DevPCI.cpp / pci_bios_init_device() but there is no
7946 * corresponding function in DevPciIch9.cpp. The EFI has corresponding code
7947 * in OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c: NotifyDev() but this
7948 * function assumes that the IDE controller is located at PCI 00:01.1 which
7949 * is not true if the ICH9 chipset is used.
7950 */
7951 PDMPciDevSetWord(pPciDev, 0x40, 0x8000); /* enable IDE0 */
7952 PDMPciDevSetWord(pPciDev, 0x42, 0x8000); /* enable IDE1 */
7953
7954 PDMPciDevSetCommand( pPciDev, PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS | PCI_COMMAND_BUSMASTER);
7955 PDMPciDevSetClassProg( pPciDev, 0x8a); /* programming interface = PCI_IDE bus-master is supported */
7956 PDMPciDevSetClassSub( pPciDev, 0x01); /* class_sub = PCI_IDE */
7957 PDMPciDevSetClassBase( pPciDev, 0x01); /* class_base = PCI_mass_storage */
7958 PDMPciDevSetHeaderType(pPciDev, 0x00);
7959
7960 pThisCC->pDevIns = pDevIns;
7961 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
7962 {
7963 pThisCC->aCts[i].pDevIns = pDevIns;
7964 pThisCC->aCts[i].iCtl = i;
7965 pThis->aCts[i].iCtl = i;
7966 pThis->aCts[i].msDelayIRQ = msDelayIRQ;
7967 for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++)
7968 {
7969 PATADEVSTATE pIf = &pThis->aCts[i].aIfs[j];
7970 PATADEVSTATER3 pIfR3 = &pThisCC->aCts[i].aIfs[j];
7971
7972 pIfR3->iLUN = pIf->iLUN = i * RT_ELEMENTS(pThis->aCts) + j;
7973 pIfR3->iCtl = pIf->iCtl = i;
7974 pIfR3->iDev = pIf->iDev = j;
7975 pIfR3->pDevIns = pDevIns;
7976 pIfR3->IBase.pfnQueryInterface = ataR3QueryInterface;
7977 pIfR3->IMountNotify.pfnMountNotify = ataR3MountNotify;
7978 pIfR3->IMountNotify.pfnUnmountNotify = ataR3UnmountNotify;
7979 pIfR3->IPort.pfnQueryDeviceLocation = ataR3QueryDeviceLocation;
7980 pIf->Led.u32Magic = PDMLED_MAGIC;
7981 }
7982 }
7983
7984 Assert(RT_ELEMENTS(pThis->aCts) == 2);
7985 pThis->aCts[0].irq = 14;
7986 pThis->aCts[0].IOPortBase1 = 0x1f0;
7987 pThis->aCts[0].IOPortBase2 = 0x3f6;
7988 pThis->aCts[1].irq = 15;
7989 pThis->aCts[1].IOPortBase1 = 0x170;
7990 pThis->aCts[1].IOPortBase2 = 0x376;
7991
7992 /*
7993 * Set the default critical section to NOP as we lock on controller level.
7994 */
7995 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
7996 AssertRCReturn(rc, rc);
7997
7998 /*
7999 * Register the PCI device.
8000 */
8001 rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, PDMPCIDEVREG_F_NOT_MANDATORY_NO, 1 /*uPciDevNo*/, 1 /*uPciDevFn*/, "piix3ide");
8002 if (RT_FAILURE(rc))
8003 return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 cannot register PCI device"));
8004
8005 /* Region #4: I/O ports for the two bus-master DMA controllers. */
8006 rc = PDMDevHlpPCIIORegionCreateIo(pDevIns, 4 /*iPciRegion*/, 0x10 /*cPorts*/,
8007 ataBMDMAIOPortWrite, ataBMDMAIOPortRead, NULL /*pvUser*/, "ATA Bus Master DMA",
8008 NULL /*paExtDescs*/, &pThis->hIoPortsBmDma);
8009 AssertRCReturn(rc, rc);
8010
8011 /*
8012 * Register stats, create critical sections.
8013 */
8014 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
8015 {
8016 for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++)
8017 {
8018 PATADEVSTATE pIf = &pThis->aCts[i].aIfs[j];
8019 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatATADMA, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
8020 "Number of ATA DMA transfers.", "/Devices/IDE%d/ATA%d/Unit%d/DMA", iInstance, i, j);
8021 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatATAPIO, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
8022 "Number of ATA PIO transfers.", "/Devices/IDE%d/ATA%d/Unit%d/PIO", iInstance, i, j);
8023 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatATAPIDMA, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
8024 "Number of ATAPI DMA transfers.", "/Devices/IDE%d/ATA%d/Unit%d/AtapiDMA", iInstance, i, j);
8025 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatATAPIPIO, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
8026 "Number of ATAPI PIO transfers.", "/Devices/IDE%d/ATA%d/Unit%d/AtapiPIO", iInstance, i, j);
8027#ifdef VBOX_WITH_STATISTICS /** @todo release too. */
8028 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatReads, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
8029 "Profiling of the read operations.", "/Devices/IDE%d/ATA%d/Unit%d/Reads", iInstance, i, j);
8030#endif
8031 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatBytesRead, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
8032 "Amount of data read.", "/Devices/IDE%d/ATA%d/Unit%d/ReadBytes", iInstance, i, j);
8033#ifdef VBOX_INSTRUMENT_DMA_WRITES
8034 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatInstrVDWrites,STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
8035 "Profiling of the VD DMA write operations.", "/Devices/IDE%d/ATA%d/Unit%d/InstrVDWrites", iInstance, i, j);
8036#endif
8037#ifdef VBOX_WITH_STATISTICS
8038 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatWrites, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
8039 "Profiling of the write operations.", "/Devices/IDE%d/ATA%d/Unit%d/Writes", iInstance, i, j);
8040#endif
8041 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatBytesWritten, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
8042 "Amount of data written.", "/Devices/IDE%d/ATA%d/Unit%d/WrittenBytes", iInstance, i, j);
8043#ifdef VBOX_WITH_STATISTICS
8044 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatFlushes, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
8045 "Profiling of the flush operations.", "/Devices/IDE%d/ATA%d/Unit%d/Flushes", iInstance, i, j);
8046#endif
8047 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatStatusYields, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
8048 "Profiling of status polling yields.", "/Devices/IDE%d/ATA%d/Unit%d/StatusYields", iInstance, i, j);
8049 }
8050#ifdef VBOX_WITH_STATISTICS /** @todo release too. */
8051 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aCts[i].StatAsyncOps, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
8052 "The number of async operations.", "/Devices/IDE%d/ATA%d/Async/Operations", iInstance, i);
8053 /** @todo STAMUNIT_MICROSECS */
8054 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aCts[i].StatAsyncMinWait, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
8055 "Minimum wait in microseconds.", "/Devices/IDE%d/ATA%d/Async/MinWait", iInstance, i);
8056 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aCts[i].StatAsyncMaxWait, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
8057 "Maximum wait in microseconds.", "/Devices/IDE%d/ATA%d/Async/MaxWait", iInstance, i);
8058 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aCts[i].StatAsyncTimeUS, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
8059 "Total time spent in microseconds.", "/Devices/IDE%d/ATA%d/Async/TotalTimeUS", iInstance, i);
8060 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aCts[i].StatAsyncTime, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
8061 "Profiling of async operations.", "/Devices/IDE%d/ATA%d/Async/Time", iInstance, i);
8062 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aCts[i].StatLockWait, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
8063 "Profiling of locks.", "/Devices/IDE%d/ATA%d/Async/LockWait", iInstance, i);
8064#endif /* VBOX_WITH_STATISTICS */
8065
8066 /* Initialize per-controller critical section. */
8067 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->aCts[i].lock, RT_SRC_POS, "ATA#%u-Ctl", i);
8068 AssertLogRelRCReturn(rc, rc);
8069
8070 /* Initialize per-controller async I/O request critical section. */
8071 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->aCts[i].AsyncIORequestLock, RT_SRC_POS, "ATA#%u-Req", i);
8072 AssertLogRelRCReturn(rc, rc);
8073 }
8074
8075 /*
8076 * Attach status driver (optional).
8077 */
8078 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThisCC->IBase, &pBase, "Status Port");
8079 if (RT_SUCCESS(rc))
8080 {
8081 pThisCC->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
8082 pThisCC->pMediaNotify = PDMIBASE_QUERY_INTERFACE(pBase, PDMIMEDIANOTIFY);
8083 }
8084 else if (rc != VERR_PDM_NO_ATTACHED_DRIVER)
8085 {
8086 AssertMsgFailed(("Failed to attach to status driver. rc=%Rrc\n", rc));
8087 return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 cannot attach to status driver"));
8088 }
8089
8090 /*
8091 * Attach the units.
8092 */
8093 uint32_t cbTotalBuffer = 0;
8094 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
8095 {
8096 PATACONTROLLER pCtl = &pThis->aCts[i];
8097 PATACONTROLLERR3 pCtlR3 = &pThisCC->aCts[i];
8098
8099 /*
8100 * Start the worker thread.
8101 */
8102 pCtl->uAsyncIOState = ATA_AIO_NEW;
8103 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pCtl->hAsyncIOSem);
8104 AssertLogRelRCReturn(rc, rc);
8105 rc = RTSemEventCreate(&pCtlR3->hSuspendIOSem);
8106 AssertLogRelRCReturn(rc, rc);
8107
8108 ataR3AsyncIOClearRequests(pDevIns, pCtl);
8109 rc = RTThreadCreateF(&pCtlR3->hAsyncIOThread, ataR3AsyncIOThread, pCtlR3, 0,
8110 RTTHREADTYPE_IO, RTTHREADFLAGS_WAITABLE, "ATA-%u", i);
8111 AssertLogRelRCReturn(rc, rc);
8112 Assert( pCtlR3->hAsyncIOThread != NIL_RTTHREAD && pCtl->hAsyncIOSem != NIL_SUPSEMEVENT
8113 && pCtlR3->hSuspendIOSem != NIL_RTSEMEVENT && PDMDevHlpCritSectIsInitialized(pDevIns, &pCtl->AsyncIORequestLock));
8114 Log(("%s: controller %d AIO thread id %#x; sem %p susp_sem %p\n", __FUNCTION__, i, pCtlR3->hAsyncIOThread, pCtl->hAsyncIOSem, pCtlR3->hSuspendIOSem));
8115
8116 for (uint32_t j = 0; j < RT_ELEMENTS(pCtl->aIfs); j++)
8117 {
8118 static const char *s_apszDescs[RT_ELEMENTS(pThis->aCts)][RT_ELEMENTS(pCtl->aIfs)] =
8119 {
8120 { "Primary Master", "Primary Slave" },
8121 { "Secondary Master", "Secondary Slave" }
8122 };
8123
8124 /*
8125 * Try attach the block device and get the interfaces,
8126 * required as well as optional.
8127 */
8128 PATADEVSTATE pIf = &pCtl->aIfs[j];
8129 PATADEVSTATER3 pIfR3 = &pCtlR3->aIfs[j];
8130
8131 rc = PDMDevHlpDriverAttach(pDevIns, pIf->iLUN, &pIfR3->IBase, &pIfR3->pDrvBase, s_apszDescs[i][j]);
8132 if (RT_SUCCESS(rc))
8133 {
8134 rc = ataR3ConfigLun(pIf, pIfR3);
8135 if (RT_SUCCESS(rc))
8136 {
8137 /*
8138 * Init vendor product data.
8139 */
8140 static const char *s_apszCFGMKeys[RT_ELEMENTS(pThis->aCts)][RT_ELEMENTS(pCtl->aIfs)] =
8141 {
8142 { "PrimaryMaster", "PrimarySlave" },
8143 { "SecondaryMaster", "SecondarySlave" }
8144 };
8145
8146 /* Generate a default serial number. */
8147 char szSerial[ATA_SERIAL_NUMBER_LENGTH+1];
8148 RTUUID Uuid;
8149 if (pIfR3->pDrvMedia)
8150 rc = pIfR3->pDrvMedia->pfnGetUuid(pIfR3->pDrvMedia, &Uuid);
8151 else
8152 RTUuidClear(&Uuid);
8153
8154 if (RT_FAILURE(rc) || RTUuidIsNull(&Uuid))
8155 {
8156 /* Generate a predictable serial for drives which don't have a UUID. */
8157 RTStrPrintf(szSerial, sizeof(szSerial), "VB%x-%04x%04x",
8158 pIf->iLUN + pDevIns->iInstance * 32,
8159 pThis->aCts[i].IOPortBase1, pThis->aCts[i].IOPortBase2);
8160 }
8161 else
8162 RTStrPrintf(szSerial, sizeof(szSerial), "VB%08x-%08x", Uuid.au32[0], Uuid.au32[3]);
8163
8164 /* Get user config if present using defaults otherwise. */
8165 PCFGMNODE pCfgNode = pHlp->pfnCFGMGetChild(pCfg, s_apszCFGMKeys[i][j]);
8166 rc = pHlp->pfnCFGMQueryStringDef(pCfgNode, "SerialNumber", pIf->szSerialNumber, sizeof(pIf->szSerialNumber),
8167 szSerial);
8168 if (RT_FAILURE(rc))
8169 {
8170 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
8171 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
8172 N_("PIIX3 configuration error: \"SerialNumber\" is longer than 20 bytes"));
8173 return PDMDEV_SET_ERROR(pDevIns, rc,
8174 N_("PIIX3 configuration error: failed to read \"SerialNumber\" as string"));
8175 }
8176
8177 rc = pHlp->pfnCFGMQueryStringDef(pCfgNode, "FirmwareRevision", pIf->szFirmwareRevision,
8178 sizeof(pIf->szFirmwareRevision), "1.0");
8179 if (RT_FAILURE(rc))
8180 {
8181 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
8182 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
8183 N_("PIIX3 configuration error: \"FirmwareRevision\" is longer than 8 bytes"));
8184 return PDMDEV_SET_ERROR(pDevIns, rc,
8185 N_("PIIX3 configuration error: failed to read \"FirmwareRevision\" as string"));
8186 }
8187
8188 rc = pHlp->pfnCFGMQueryStringDef(pCfgNode, "ModelNumber", pIf->szModelNumber, sizeof(pIf->szModelNumber),
8189 pIf->fATAPI ? "VBOX CD-ROM" : "VBOX HARDDISK");
8190 if (RT_FAILURE(rc))
8191 {
8192 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
8193 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
8194 N_("PIIX3 configuration error: \"ModelNumber\" is longer than 40 bytes"));
8195 return PDMDEV_SET_ERROR(pDevIns, rc,
8196 N_("PIIX3 configuration error: failed to read \"ModelNumber\" as string"));
8197 }
8198
8199 /* There are three other identification strings for CD drives used for INQUIRY */
8200 if (pIf->fATAPI)
8201 {
8202 rc = pHlp->pfnCFGMQueryStringDef(pCfgNode, "ATAPIVendorId", pIf->szInquiryVendorId,
8203 sizeof(pIf->szInquiryVendorId), "VBOX");
8204 if (RT_FAILURE(rc))
8205 {
8206 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
8207 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
8208 N_("PIIX3 configuration error: \"ATAPIVendorId\" is longer than 16 bytes"));
8209 return PDMDEV_SET_ERROR(pDevIns, rc,
8210 N_("PIIX3 configuration error: failed to read \"ATAPIVendorId\" as string"));
8211 }
8212
8213 rc = pHlp->pfnCFGMQueryStringDef(pCfgNode, "ATAPIProductId", pIf->szInquiryProductId,
8214 sizeof(pIf->szInquiryProductId), "CD-ROM");
8215 if (RT_FAILURE(rc))
8216 {
8217 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
8218 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
8219 N_("PIIX3 configuration error: \"ATAPIProductId\" is longer than 16 bytes"));
8220 return PDMDEV_SET_ERROR(pDevIns, rc,
8221 N_("PIIX3 configuration error: failed to read \"ATAPIProductId\" as string"));
8222 }
8223
8224 rc = pHlp->pfnCFGMQueryStringDef(pCfgNode, "ATAPIRevision", pIf->szInquiryRevision,
8225 sizeof(pIf->szInquiryRevision), "1.0");
8226 if (RT_FAILURE(rc))
8227 {
8228 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
8229 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
8230 N_("PIIX3 configuration error: \"ATAPIRevision\" is longer than 4 bytes"));
8231 return PDMDEV_SET_ERROR(pDevIns, rc,
8232 N_("PIIX3 configuration error: failed to read \"ATAPIRevision\" as string"));
8233 }
8234
8235 rc = pHlp->pfnCFGMQueryBoolDef(pCfgNode, "OverwriteInquiry", &pIf->fOverwriteInquiry, true);
8236 if (RT_FAILURE(rc))
8237 return PDMDEV_SET_ERROR(pDevIns, rc,
8238 N_("PIIX3 configuration error: failed to read \"OverwriteInquiry\" as boolean"));
8239 }
8240 }
8241 }
8242 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
8243 {
8244 pIfR3->pDrvBase = NULL;
8245 pIfR3->pDrvMedia = NULL;
8246 pIf->cbIOBuffer = 0;
8247 pIf->fPresent = false;
8248 LogRel(("PIIX3 ATA: LUN#%d: no unit\n", pIf->iLUN));
8249 }
8250 else
8251 {
8252 switch (rc)
8253 {
8254 case VERR_ACCESS_DENIED:
8255 /* Error already cached by DrvHostBase */
8256 return rc;
8257 default:
8258 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
8259 N_("PIIX3 cannot attach drive to the %s"),
8260 s_apszDescs[i][j]);
8261 }
8262 }
8263 cbTotalBuffer += pIf->cbIOBuffer;
8264 }
8265 }
8266
8267 /*
8268 * Register the I/O ports.
8269 * The ports are all hardcoded and enforced by the PIIX3 host bridge controller.
8270 */
8271 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
8272 {
8273 Assert(pThis->aCts[i].aIfs[0].fPresent == (pThisCC->aCts[i].aIfs[0].pDrvMedia != NULL));
8274 Assert(pThis->aCts[i].aIfs[1].fPresent == (pThisCC->aCts[i].aIfs[1].pDrvMedia != NULL));
8275
8276 if (!pThisCC->aCts[i].aIfs[0].pDrvMedia && !pThisCC->aCts[i].aIfs[1].pDrvMedia)
8277 {
8278 /* No device present on this ATA bus; requires special handling. */
8279 rc = PDMDevHlpIoPortCreateExAndMap(pDevIns, pThis->aCts[i].IOPortBase1, 8 /*cPorts*/, IOM_IOPORT_F_ABS,
8280 ataIOPortWriteEmptyBus, ataIOPortReadEmptyBus, NULL, NULL, (RTHCPTR)(uintptr_t)i,
8281 "ATA I/O Base 1 - Empty Bus", NULL /*paExtDescs*/, &pThis->aCts[i].hIoPortsEmpty1);
8282 AssertLogRelRCReturn(rc, rc);
8283 rc = PDMDevHlpIoPortCreateExAndMap(pDevIns, pThis->aCts[i].IOPortBase2, 1 /*cPorts*/, IOM_IOPORT_F_ABS,
8284 ataIOPortWriteEmptyBus, ataIOPortReadEmptyBus, NULL, NULL, (RTHCPTR)(uintptr_t)i,
8285 "ATA I/O Base 2 - Empty Bus", NULL /*paExtDescs*/, &pThis->aCts[i].hIoPortsEmpty2);
8286 AssertLogRelRCReturn(rc, rc);
8287 }
8288 else
8289 {
8290 /* At least one device present, register regular handlers. */
8291 rc = PDMDevHlpIoPortCreateExAndMap(pDevIns, pThis->aCts[i].IOPortBase1, 1 /*cPorts*/, IOM_IOPORT_F_ABS,
8292 ataIOPortWrite1Data, ataIOPortRead1Data,
8293 ataIOPortWriteStr1Data, ataIOPortReadStr1Data, (RTHCPTR)(uintptr_t)i,
8294 "ATA I/O Base 1 - Data", NULL /*paExtDescs*/, &pThis->aCts[i].hIoPorts1First);
8295 AssertLogRelRCReturn(rc, rc);
8296 rc = PDMDevHlpIoPortCreateExAndMap(pDevIns, pThis->aCts[i].IOPortBase1 + 1, 7 /*cPorts*/, IOM_IOPORT_F_ABS,
8297 ataIOPortWrite1Other, ataIOPortRead1Other, NULL, NULL, (RTHCPTR)(uintptr_t)i,
8298 "ATA I/O Base 1 - Other", NULL /*paExtDescs*/, &pThis->aCts[i].hIoPorts1Other);
8299 AssertLogRelRCReturn(rc, rc);
8300
8301
8302 rc = PDMDevHlpIoPortCreateExAndMap(pDevIns, pThis->aCts[i].IOPortBase2, 1 /*cPorts*/, IOM_IOPORT_F_ABS,
8303 ataIOPortWrite2, ataIOPortRead2, NULL, NULL, (RTHCPTR)(uintptr_t)i,
8304 "ATA I/O Base 2", NULL /*paExtDescs*/, &pThis->aCts[i].hIoPorts2);
8305 AssertLogRelRCReturn(rc, rc);
8306 }
8307 }
8308
8309 rc = PDMDevHlpSSMRegisterEx(pDevIns, ATA_SAVED_STATE_VERSION, sizeof(*pThis) + cbTotalBuffer, NULL,
8310 NULL, ataR3LiveExec, NULL,
8311 ataR3SaveLoadPrep, ataR3SaveExec, NULL,
8312 ataR3SaveLoadPrep, ataR3LoadExec, NULL);
8313 if (RT_FAILURE(rc))
8314 return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 cannot register save state handlers"));
8315
8316 /*
8317 * Initialize the device state.
8318 */
8319 return ataR3ResetCommon(pDevIns, true /*fConstruct*/);
8320}
8321
8322#else /* !IN_RING3 */
8323
8324/**
8325 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
8326 */
8327static DECLCALLBACK(int) ataRZConstruct(PPDMDEVINS pDevIns)
8328{
8329 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
8330 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE);
8331
8332 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
8333 AssertRCReturn(rc, rc);
8334
8335 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortsBmDma, ataBMDMAIOPortWrite, ataBMDMAIOPortRead, NULL /*pvUser*/);
8336 AssertRCReturn(rc, rc);
8337
8338 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
8339 {
8340 if (pThis->aCts[i].hIoPorts1First != NIL_IOMIOPORTHANDLE)
8341 {
8342 rc = PDMDevHlpIoPortSetUpContextEx(pDevIns, pThis->aCts[i].hIoPorts1First,
8343 ataIOPortWrite1Data, ataIOPortRead1Data,
8344 ataIOPortWriteStr1Data, ataIOPortReadStr1Data, (RTHCPTR)(uintptr_t)i);
8345 AssertLogRelRCReturn(rc, rc);
8346 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->aCts[i].hIoPorts1Other,
8347 ataIOPortWrite1Other, ataIOPortRead1Other, (RTHCPTR)(uintptr_t)i);
8348 AssertLogRelRCReturn(rc, rc);
8349 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->aCts[i].hIoPorts2,
8350 ataIOPortWrite2, ataIOPortRead2, (RTHCPTR)(uintptr_t)i);
8351 AssertLogRelRCReturn(rc, rc);
8352 }
8353 else
8354 {
8355 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->aCts[i].hIoPortsEmpty1,
8356 ataIOPortWriteEmptyBus, ataIOPortReadEmptyBus, (void *)(uintptr_t)i /*pvUser*/);
8357 AssertRCReturn(rc, rc);
8358
8359 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->aCts[i].hIoPortsEmpty2,
8360 ataIOPortWriteEmptyBus, ataIOPortReadEmptyBus, (void *)(uintptr_t)i /*pvUser*/);
8361 AssertRCReturn(rc, rc);
8362 }
8363 }
8364
8365 return VINF_SUCCESS;
8366}
8367
8368
8369#endif /* !IN_RING3 */
8370
8371/**
8372 * The device registration structure.
8373 */
8374const PDMDEVREG g_DevicePIIX3IDE =
8375{
8376 /* .u32Version = */ PDM_DEVREG_VERSION,
8377 /* .uReserved0 = */ 0,
8378 /* .szName = */ "piix3ide",
8379 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE
8380 | PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION | PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION
8381 | PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION,
8382 /* .fClass = */ PDM_DEVREG_CLASS_STORAGE,
8383 /* .cMaxInstances = */ 1,
8384 /* .uSharedVersion = */ 42,
8385 /* .cbInstanceShared = */ sizeof(ATASTATE),
8386 /* .cbInstanceCC = */ sizeof(ATASTATECC),
8387 /* .cbInstanceRC = */ sizeof(ATASTATERC),
8388 /* .cMaxPciDevices = */ 1,
8389 /* .cMaxMsixVectors = */ 0,
8390 /* .pszDescription = */ "Intel PIIX3 ATA controller.\n"
8391 " LUN #0 is primary master.\n"
8392 " LUN #1 is primary slave.\n"
8393 " LUN #2 is secondary master.\n"
8394 " LUN #3 is secondary slave.\n"
8395 " LUN #999 is the LED/Status connector.",
8396#if defined(IN_RING3)
8397 /* .pszRCMod = */ "VBoxDDRC.rc",
8398 /* .pszR0Mod = */ "VBoxDDR0.r0",
8399 /* .pfnConstruct = */ ataR3Construct,
8400 /* .pfnDestruct = */ ataR3Destruct,
8401 /* .pfnRelocate = */ NULL,
8402 /* .pfnMemSetup = */ NULL,
8403 /* .pfnPowerOn = */ NULL,
8404 /* .pfnReset = */ ataR3Reset,
8405 /* .pfnSuspend = */ ataR3Suspend,
8406 /* .pfnResume = */ ataR3Resume,
8407 /* .pfnAttach = */ ataR3Attach,
8408 /* .pfnDetach = */ ataR3Detach,
8409 /* .pfnQueryInterface = */ NULL,
8410 /* .pfnInitComplete = */ NULL,
8411 /* .pfnPowerOff = */ ataR3PowerOff,
8412 /* .pfnSoftReset = */ NULL,
8413 /* .pfnReserved0 = */ NULL,
8414 /* .pfnReserved1 = */ NULL,
8415 /* .pfnReserved2 = */ NULL,
8416 /* .pfnReserved3 = */ NULL,
8417 /* .pfnReserved4 = */ NULL,
8418 /* .pfnReserved5 = */ NULL,
8419 /* .pfnReserved6 = */ NULL,
8420 /* .pfnReserved7 = */ NULL,
8421#elif defined(IN_RING0)
8422 /* .pfnEarlyConstruct = */ NULL,
8423 /* .pfnConstruct = */ ataRZConstruct,
8424 /* .pfnDestruct = */ NULL,
8425 /* .pfnFinalDestruct = */ NULL,
8426 /* .pfnRequest = */ NULL,
8427 /* .pfnReserved0 = */ NULL,
8428 /* .pfnReserved1 = */ NULL,
8429 /* .pfnReserved2 = */ NULL,
8430 /* .pfnReserved3 = */ NULL,
8431 /* .pfnReserved4 = */ NULL,
8432 /* .pfnReserved5 = */ NULL,
8433 /* .pfnReserved6 = */ NULL,
8434 /* .pfnReserved7 = */ NULL,
8435#elif defined(IN_RC)
8436 /* .pfnConstruct = */ ataRZConstruct,
8437 /* .pfnReserved0 = */ NULL,
8438 /* .pfnReserved1 = */ NULL,
8439 /* .pfnReserved2 = */ NULL,
8440 /* .pfnReserved3 = */ NULL,
8441 /* .pfnReserved4 = */ NULL,
8442 /* .pfnReserved5 = */ NULL,
8443 /* .pfnReserved6 = */ NULL,
8444 /* .pfnReserved7 = */ NULL,
8445#else
8446# error "Not in IN_RING3, IN_RING0 or IN_RC!"
8447#endif
8448 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
8449};
8450#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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