DevBusLogic.cpp@ 44845

Last change on this file since 44845 was 44719, checked in by vboxsync, 12 years ago
BusLogic: More verbose debug info.
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1	/* $Id: DevBusLogic.cpp 44719 2013-02-15 16:05:51Z vboxsync $ */
2	/** @file
3	* VBox storage devices - BusLogic SCSI host adapter BT-958.
4	*
5	* Based on the Multi-Master Ultra SCSI Systems Technical Reference Manual.
6	*/
7
8	/*
9	* Copyright (C) 2006-2013 Oracle Corporation
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*/
19
20
21	/*******************************************************************************
22	* Header Files *
23	*******************************************************************************/
24	#define LOG_GROUP LOG_GROUP_DEV_BUSLOGIC
25	#include <VBox/vmm/pdmdev.h>
26	#include <VBox/vmm/pdmifs.h>
27	#include <VBox/vmm/pdmcritsect.h>
28	#include <VBox/scsi.h>
29	#include <iprt/asm.h>
30	#include <iprt/assert.h>
31	#include <iprt/string.h>
32	#include <iprt/log.h>
33	#ifdef IN_RING3
34	# include <iprt/alloc.h>
35	# include <iprt/memcache.h>
36	# include <iprt/param.h>
37	# include <iprt/uuid.h>
38	#endif
39
40	#include "VBoxSCSI.h"
41	#include "VBoxDD.h"
42
43
44	/*******************************************************************************
45	* Defined Constants And Macros *
46	*******************************************************************************/
47	/** Maximum number of attached devices the adapter can handle. */
48	#define BUSLOGIC_MAX_DEVICES 16
49
50	/** Maximum number of scatter gather elements this device can handle. */
51	#define BUSLOGIC_MAX_SCATTER_GATHER_LIST_SIZE 128
52
53	/** Size of the command buffer. */
54	#define BUSLOGIC_COMMAND_SIZE_MAX 5
55
56	/** Size of the reply buffer. */
57	#define BUSLOGIC_REPLY_SIZE_MAX 64
58
59	/** Custom fixed I/O ports for BIOS controller access.
60	* Note that these should not be in the ISA range (below 400h) to avoid
61	* conflicts with ISA device probing. Addresses in the 300h-340h range should be
62	* especially avoided.
63	*/
64	#define BUSLOGIC_BIOS_IO_PORT 0x430
65
66	/** State saved version. */
67	#define BUSLOGIC_SAVED_STATE_MINOR_VERSION 3
68
69	/** Saved state version before the suspend on error feature was implemented. */
70	#define BUSLOGIC_SAVED_STATE_MINOR_PRE_ERROR_HANDLING 1
71	/** Saved state version before 24-bit mailbox support was implemented. */
72	#define BUSLOGIC_SAVED_STATE_MINOR_PRE_24BIT_MBOX 2
73
74	/** The duration of software-initiated reset (in nano seconds).
75	* Not documented, set to 50 ms. */
76	#define BUSLOGIC_RESET_DURATION_NS UINT64_C(50000000)
77
78
79	/*******************************************************************************
80	* Structures and Typedefs *
81	*******************************************************************************/
82	/**
83	* State of a device attached to the buslogic host adapter.
84	*
85	* @implements PDMIBASE
86	* @implements PDMISCSIPORT
87	* @implements PDMILEDPORTS
88	*/
89	typedef struct BUSLOGICDEVICE
90	{
91	/** Pointer to the owning buslogic device instance. - R3 pointer */
92	R3PTRTYPE(struct BUSLOGIC *) pBusLogicR3;
93	/** Pointer to the owning buslogic device instance. - R0 pointer */
94	R0PTRTYPE(struct BUSLOGIC *) pBusLogicR0;
95	/** Pointer to the owning buslogic device instance. - RC pointer */
96	RCPTRTYPE(struct BUSLOGIC *) pBusLogicRC;
97
98	/** Flag whether device is present. */
99	bool fPresent;
100	/** LUN of the device. */
101	RTUINT iLUN;
102
103	#if HC_ARCH_BITS == 64
104	uint32_t Alignment0;
105	#endif
106
107	/** Our base interface. */
108	PDMIBASE IBase;
109	/** SCSI port interface. */
110	PDMISCSIPORT ISCSIPort;
111	/** Led interface. */
112	PDMILEDPORTS ILed;
113	/** Pointer to the attached driver's base interface. */
114	R3PTRTYPE(PPDMIBASE) pDrvBase;
115	/** Pointer to the underlying SCSI connector interface. */
116	R3PTRTYPE(PPDMISCSICONNECTOR) pDrvSCSIConnector;
117	/** The status LED state for this device. */
118	PDMLED Led;
119
120	#if HC_ARCH_BITS == 64
121	uint32_t Alignment1;
122	#endif
123
124	/** Number of outstanding tasks on the port. */
125	volatile uint32_t cOutstandingRequests;
126
127	} BUSLOGICDEVICE, *PBUSLOGICDEVICE;
128
129	/**
130	* Commands the BusLogic adapter supports.
131	*/
132	enum BUSLOGICCOMMAND
133	{
134	BUSLOGICCOMMAND_TEST_CMDC_INTERRUPT = 0x00,
135	BUSLOGICCOMMAND_INITIALIZE_MAILBOX = 0x01,
136	BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND = 0x02,
137	BUSLOGICCOMMAND_EXECUTE_BIOS_COMMAND = 0x03,
138	BUSLOGICCOMMAND_INQUIRE_BOARD_ID = 0x04,
139	BUSLOGICCOMMAND_ENABLE_OUTGOING_MAILBOX_AVAILABLE_INTERRUPT = 0x05,
140	BUSLOGICCOMMAND_SET_SCSI_SELECTION_TIMEOUT = 0x06,
141	BUSLOGICCOMMAND_SET_PREEMPT_TIME_ON_BUS = 0x07,
142	BUSLOGICCOMMAND_SET_TIME_OFF_BUS = 0x08,
143	BUSLOGICCOMMAND_SET_BUS_TRANSFER_RATE = 0x09,
144	BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_0_TO_7 = 0x0a,
145	BUSLOGICCOMMAND_INQUIRE_CONFIGURATION = 0x0b,
146	BUSLOGICCOMMAND_ENABLE_TARGET_MODE = 0x0c,
147	BUSLOGICCOMMAND_INQUIRE_SETUP_INFORMATION = 0x0d,
148	BUSLOGICCOMMAND_WRITE_ADAPTER_LOCAL_RAM = 0x1a,
149	BUSLOGICCOMMAND_READ_ADAPTER_LOCAL_RAM = 0x1b,
150	BUSLOGICCOMMAND_WRITE_BUSMASTER_CHIP_FIFO = 0x1c,
151	BUSLOGICCOMMAND_READ_BUSMASTER_CHIP_FIFO = 0x1d,
152	BUSLOGICCOMMAND_ECHO_COMMAND_DATA = 0x1f,
153	BUSLOGICCOMMAND_HOST_ADAPTER_DIAGNOSTIC = 0x20,
154	BUSLOGICCOMMAND_SET_ADAPTER_OPTIONS = 0x21,
155	BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_8_TO_15 = 0x23,
156	BUSLOGICCOMMAND_INQUIRE_TARGET_DEVICES = 0x24,
157	BUSLOGICCOMMAND_DISABLE_HOST_ADAPTER_INTERRUPT = 0x25,
158	BUSLOGICCOMMAND_EXT_BIOS_INFO = 0x28,
159	BUSLOGICCOMMAND_UNLOCK_MAILBOX = 0x29,
160	BUSLOGICCOMMAND_INITIALIZE_EXTENDED_MAILBOX = 0x81,
161	BUSLOGICCOMMAND_EXECUTE_SCSI_COMMAND = 0x83,
162	BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_3RD_LETTER = 0x84,
163	BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_LETTER = 0x85,
164	BUSLOGICCOMMAND_INQUIRE_PCI_HOST_ADAPTER_INFORMATION = 0x86,
165	BUSLOGICCOMMAND_INQUIRE_HOST_ADAPTER_MODEL_NUMBER = 0x8b,
166	BUSLOGICCOMMAND_INQUIRE_SYNCHRONOUS_PERIOD = 0x8c,
167	BUSLOGICCOMMAND_INQUIRE_EXTENDED_SETUP_INFORMATION = 0x8d,
168	BUSLOGICCOMMAND_ENABLE_STRICT_ROUND_ROBIN_MODE = 0x8f,
169	BUSLOGICCOMMAND_STORE_HOST_ADAPTER_LOCAL_RAM = 0x90,
170	BUSLOGICCOMMAND_FETCH_HOST_ADAPTER_LOCAL_RAM = 0x91,
171	BUSLOGICCOMMAND_STORE_LOCAL_DATA_IN_EEPROM = 0x92,
172	BUSLOGICCOMMAND_UPLOAD_AUTO_SCSI_CODE = 0x94,
173	BUSLOGICCOMMAND_MODIFY_IO_ADDRESS = 0x95,
174	BUSLOGICCOMMAND_SET_CCB_FORMAT = 0x96,
175	BUSLOGICCOMMAND_WRITE_INQUIRY_BUFFER = 0x9a,
176	BUSLOGICCOMMAND_READ_INQUIRY_BUFFER = 0x9b,
177	BUSLOGICCOMMAND_FLASH_ROM_UPLOAD_DOWNLOAD = 0xa7,
178	BUSLOGICCOMMAND_READ_SCAM_DATA = 0xa8,
179	BUSLOGICCOMMAND_WRITE_SCAM_DATA = 0xa9
180	} BUSLOGICCOMMAND;
181
182	#pragma pack(1)
183	/**
184	* Auto SCSI structure which is located
185	* in host adapter RAM and contains several
186	* configuration parameters.
187	*/
188	typedef struct AutoSCSIRam
189	{
190	uint8_t aInternalSignature[2];
191	uint8_t cbInformation;
192	uint8_t aHostAdaptertype[6];
193	uint8_t uReserved1;
194	bool fFloppyEnabled : 1;
195	bool fFloppySecondary : 1;
196	bool fLevelSensitiveInterrupt : 1;
197	unsigned char uReserved2 : 2;
198	unsigned char uSystemRAMAreForBIOS : 3;
199	unsigned char uDMAChannel : 7;
200	bool fDMAAutoConfiguration : 1;
201	unsigned char uIrqChannel : 7;
202	bool fIrqAutoConfiguration : 1;
203	uint8_t uDMATransferRate;
204	uint8_t uSCSIId;
205	bool fLowByteTerminated : 1;
206	bool fParityCheckingEnabled : 1;
207	bool fHighByteTerminated : 1;
208	bool fNoisyCablingEnvironment : 1;
209	bool fFastSynchronousNeogtiation : 1;
210	bool fBusResetEnabled : 1;
211	bool fReserved3 : 1;
212	bool fActiveNegotiationEnabled : 1;
213	uint8_t uBusOnDelay;
214	uint8_t uBusOffDelay;
215	bool fHostAdapterBIOSEnabled : 1;
216	bool fBIOSRedirectionOfInt19 : 1;
217	bool fExtendedTranslation : 1;
218	bool fMapRemovableAsFixed : 1;
219	bool fReserved4 : 1;
220	bool fBIOSSupportsMoreThan2Drives : 1;
221	bool fBIOSInterruptMode : 1;
222	bool fFlopticalSupport : 1;
223	uint16_t u16DeviceEnabledMask;
224	uint16_t u16WidePermittedMask;
225	uint16_t u16FastPermittedMask;
226	uint16_t u16SynchronousPermittedMask;
227	uint16_t u16DisconnectPermittedMask;
228	uint16_t u16SendStartUnitCommandMask;
229	uint16_t u16IgnoreInBIOSScanMask;
230	unsigned char uPCIInterruptPin : 2;
231	unsigned char uHostAdapterIoPortAddress : 2;
232	bool fStrictRoundRobinMode : 1;
233	bool fVesaBusSpeedGreaterThan33MHz : 1;
234	bool fVesaBurstWrite : 1;
235	bool fVesaBurstRead : 1;
236	uint16_t u16UltraPermittedMask;
237	uint32_t uReserved5;
238	uint8_t uReserved6;
239	uint8_t uAutoSCSIMaximumLUN;
240	bool fReserved7 : 1;
241	bool fSCAMDominant : 1;
242	bool fSCAMenabled : 1;
243	bool fSCAMLevel2 : 1;
244	unsigned char uReserved8 : 4;
245	bool fInt13Extension : 1;
246	bool fReserved9 : 1;
247	bool fCDROMBoot : 1;
248	unsigned char uReserved10 : 5;
249	unsigned char uBootTargetId : 4;
250	unsigned char uBootChannel : 4;
251	bool fForceBusDeviceScanningOrder : 1;
252	unsigned char uReserved11 : 7;
253	uint16_t u16NonTaggedToAlternateLunPermittedMask;
254	uint16_t u16RenegotiateSyncAfterCheckConditionMask;
255	uint8_t aReserved12[10];
256	uint8_t aManufacturingDiagnostic[2];
257	uint16_t u16Checksum;
258	} AutoSCSIRam, *PAutoSCSIRam;
259	AssertCompileSize(AutoSCSIRam, 64);
260	#pragma pack()
261
262	/**
263	* The local Ram.
264	*/
265	typedef union HostAdapterLocalRam
266	{
267	/** Byte view. */
268	uint8_t u8View[256];
269	/** Structured view. */
270	struct
271	{
272	/** Offset 0 - 63 is for BIOS. */
273	uint8_t u8Bios[64];
274	/** Auto SCSI structure. */
275	AutoSCSIRam autoSCSIData;
276	} structured;
277	} HostAdapterLocalRam, *PHostAdapterLocalRam;
278	AssertCompileSize(HostAdapterLocalRam, 256);
279
280
281	/** Ugly 24-bit big-endian addressing. */
282	typedef struct
283	{
284	uint8_t hi;
285	uint8_t mid;
286	uint8_t lo;
287	} Addr24, Len24;
288	AssertCompileSize(Addr24, 3);
289
290	#define ADDR_TO_U32(x) (((x).hi << 16) \| ((x).mid << 8) \| (x).lo)
291	#define LEN_TO_U32 ADDR_TO_U32
292	#define U32_TO_ADDR(a, x) do {(a).hi = (x) >> 16; (a).mid = (x) >> 8; (a).lo = (x);} while(0)
293	#define U32_TO_LEN U32_TO_ADDR
294
295	/** @name Compatible ISA base I/O port addresses. Disabled if zero.
296	* @{ */
297	#define NUM_ISA_BASES 8
298	#define MAX_ISA_BASE (NUM_ISA_BASES - 1)
299	#define ISA_BASE_DISABLED 6
300
301	static uint16_t const g_aISABases[NUM_ISA_BASES] =
302	{
303	0x330, 0x334, 0x230, 0x234, 0x130, 0x134, 0, 0
304	};
305	/** @} */
306
307	/** Pointer to a task state structure. */
308	typedef struct BUSLOGICTASKSTATE *PBUSLOGICTASKSTATE;
309
310	/**
311	* Main BusLogic device state.
312	*
313	* @extends PCIDEVICE
314	* @implements PDMILEDPORTS
315	*/
316	typedef struct BUSLOGIC
317	{
318	/** The PCI device structure. */
319	PCIDEVICE dev;
320	/** Pointer to the device instance - HC ptr */
321	PPDMDEVINSR3 pDevInsR3;
322	/** Pointer to the device instance - R0 ptr */
323	PPDMDEVINSR0 pDevInsR0;
324	/** Pointer to the device instance - RC ptr. */
325	PPDMDEVINSRC pDevInsRC;
326
327	/** Whether R0 is enabled. */
328	bool fR0Enabled;
329	/** Whether RC is enabled. */
330	bool fGCEnabled;
331
332	/** Base address of the I/O ports. */
333	RTIOPORT IOPortBase;
334	/** Base address of the memory mapping. */
335	RTGCPHYS MMIOBase;
336	/** Status register - Readonly. */
337	volatile uint8_t regStatus;
338	/** Interrupt register - Readonly. */
339	volatile uint8_t regInterrupt;
340	/** Geometry register - Readonly. */
341	volatile uint8_t regGeometry;
342	/** Pending (delayed) interrupt. */
343	uint8_t uPendingIntr;
344
345	/** Local RAM for the fetch hostadapter local RAM request.
346	* I don't know how big the buffer really is but the maximum
347	* seems to be 256 bytes because the offset and count field in the command request
348	* are only one byte big.
349	*/
350	HostAdapterLocalRam LocalRam;
351
352	/** Command code the guest issued. */
353	uint8_t uOperationCode;
354	/** Buffer for the command parameters the adapter is currently receiving from the guest.
355	* Size of the largest command which is possible.
356	*/
357	uint8_t aCommandBuffer[BUSLOGIC_COMMAND_SIZE_MAX]; /* Size of the biggest request. */
358	/** Current position in the command buffer. */
359	uint8_t iParameter;
360	/** Parameters left until the command is complete. */
361	uint8_t cbCommandParametersLeft;
362
363	/** Whether we are using the RAM or reply buffer. */
364	bool fUseLocalRam;
365	/** Buffer to store reply data from the controller to the guest. */
366	uint8_t aReplyBuffer[BUSLOGIC_REPLY_SIZE_MAX]; /* Size of the biggest reply. */
367	/** Position in the buffer we are reading next. */
368	uint8_t iReply;
369	/** Bytes left until the reply buffer is empty. */
370	uint8_t cbReplyParametersLeft;
371
372	/** Flag whether IRQs are enabled. */
373	bool fIRQEnabled;
374	/** Flag whether the ISA I/O port range is disabled
375	* to prevent the BIOS to access the device. */
376	bool fISAEnabled; /*< @todo unused, to be removed /
377	/** Flag whether 24-bit mailboxes are in use (default is 32-bit). */
378	bool fMbxIs24Bit; /*< @todo save? /
379	/** ISA I/O port base (encoded in FW-compatible format). */
380	uint8_t uISABaseCode;
381
382	/** ISA I/O port base (disabled if zero). */
383	RTIOPORT IOISABase;
384	/** Default ISA I/O port base in FW-compatible format. */
385	uint8_t uDefaultISABaseCode;
386
387	/** Number of mailboxes the guest set up. */
388	uint32_t cMailbox;
389
390	#if HC_ARCH_BITS == 64
391	uint32_t Alignment0;
392	#endif
393
394	/** Time when HBA reset was last initiated. / /< @todo does this need to be saved? /
395	uint64_t u64ResetTime;
396	/** Physical base address of the outgoing mailboxes. */
397	RTGCPHYS GCPhysAddrMailboxOutgoingBase;
398	/** Current outgoing mailbox position. */
399	uint32_t uMailboxOutgoingPositionCurrent;
400	/** Number of mailboxes ready. */
401	volatile uint32_t cMailboxesReady;
402	/** Whether a notification to R3 was send. */
403	volatile bool fNotificationSend;
404
405	#if HC_ARCH_BITS == 64
406	uint32_t Alignment1;
407	#endif
408
409	/** Physical base address of the incoming mailboxes. */
410	RTGCPHYS GCPhysAddrMailboxIncomingBase;
411	/** Current incoming mailbox position. */
412	uint32_t uMailboxIncomingPositionCurrent;
413
414	/** Whether strict round robin is enabled. */
415	bool fStrictRoundRobinMode;
416	/** Whether the extended LUN CCB format is enabled for 32 possible logical units. */
417	bool fExtendedLunCCBFormat;
418
419	/** Queue to send tasks to R3. - HC ptr */
420	R3PTRTYPE(PPDMQUEUE) pNotifierQueueR3;
421	/** Queue to send tasks to R3. - HC ptr */
422	R0PTRTYPE(PPDMQUEUE) pNotifierQueueR0;
423	/** Queue to send tasks to R3. - RC ptr */
424	RCPTRTYPE(PPDMQUEUE) pNotifierQueueRC;
425
426	uint32_t Alignment2;
427
428	/** Critical section protecting access to the interrupt status register. */
429	PDMCRITSECT CritSectIntr;
430
431	/** Cache for task states. */
432	R3PTRTYPE(RTMEMCACHE) hTaskCache;
433
434	/** Device state for BIOS access. */
435	VBOXSCSI VBoxSCSI;
436
437	/** BusLogic device states. */
438	BUSLOGICDEVICE aDeviceStates[BUSLOGIC_MAX_DEVICES];
439
440	/** The base interface.
441	* @todo use PDMDEVINS::IBase */
442	PDMIBASE IBase;
443	/** Status Port - Leds interface. */
444	PDMILEDPORTS ILeds;
445	/** Partner of ILeds. */
446	R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
447
448	#if HC_ARCH_BITS == 64
449	uint32_t Alignment3;
450	#endif
451
452	/** Indicates that PDMDevHlpAsyncNotificationCompleted should be called when
453	* a port is entering the idle state. */
454	bool volatile fSignalIdle;
455	/** Flag whether we have tasks which need to be processed again. */
456	bool volatile fRedo;
457	/** List of tasks which can be redone. */
458	R3PTRTYPE(volatile PBUSLOGICTASKSTATE) pTasksRedoHead;
459
460	#ifdef LOG_ENABLED
461	# if HC_ARCH_BITS == 64
462	uint32_t Alignment4;
463	# endif
464
465	volatile uint32_t cInMailboxesReady;
466	#endif
467
468	} BUSLOGIC, *PBUSLOGIC;
469
470	/** Register offsets in the I/O port space. */
471	#define BUSLOGIC_REGISTER_CONTROL 0 /*< Writeonly /
472	/** Fields for the control register. */
473	# define BUSLOGIC_REGISTER_CONTROL_SCSI_BUSRESET RT_BIT(4)
474	# define BUSLOGIC_REGISTER_CONTROL_INTERRUPT_RESET RT_BIT(5)
475	# define BUSLOGIC_REGISTER_CONTROL_SOFT_RESET RT_BIT(6)
476	# define BUSLOGIC_REGISTER_CONTROL_HARD_RESET RT_BIT(7)
477
478	#define BUSLOGIC_REGISTER_STATUS 0 /*< Readonly /
479	/** Fields for the status register. */
480	# define BUSLOGIC_REGISTER_STATUS_COMMAND_INVALID RT_BIT(0)
481	# define BUSLOGIC_REGISTER_STATUS_DATA_IN_REGISTER_READY RT_BIT(2)
482	# define BUSLOGIC_REGISTER_STATUS_COMMAND_PARAMETER_REGISTER_BUSY RT_BIT(3)
483	# define BUSLOGIC_REGISTER_STATUS_HOST_ADAPTER_READY RT_BIT(4)
484	# define BUSLOGIC_REGISTER_STATUS_INITIALIZATION_REQUIRED RT_BIT(5)
485	# define BUSLOGIC_REGISTER_STATUS_DIAGNOSTIC_FAILURE RT_BIT(6)
486	# define BUSLOGIC_REGISTER_STATUS_DIAGNOSTIC_ACTIVE RT_BIT(7)
487
488	#define BUSLOGIC_REGISTER_COMMAND 1 /*< Writeonly /
489	#define BUSLOGIC_REGISTER_DATAIN 1 /*< Readonly /
490	#define BUSLOGIC_REGISTER_INTERRUPT 2 /*< Readonly /
491	/** Fields for the interrupt register. */
492	# define BUSLOGIC_REGISTER_INTERRUPT_INCOMING_MAILBOX_LOADED RT_BIT(0)
493	# define BUSLOGIC_REGISTER_INTERRUPT_OUTGOING_MAILBOX_AVAILABLE RT_BIT(1)
494	# define BUSLOGIC_REGISTER_INTERRUPT_COMMAND_COMPLETE RT_BIT(2)
495	# define BUSLOGIC_REGISTER_INTERRUPT_EXTERNAL_BUS_RESET RT_BIT(3)
496	# define BUSLOGIC_REGISTER_INTERRUPT_INTERRUPT_VALID RT_BIT(7)
497
498	#define BUSLOGIC_REGISTER_GEOMETRY 3 /* Readonly */
499	# define BUSLOGIC_REGISTER_GEOMETRY_EXTENTED_TRANSLATION_ENABLED RT_BIT(7)
500
501	/** Structure for the INQUIRE_PCI_HOST_ADAPTER_INFORMATION reply. */
502	typedef struct ReplyInquirePCIHostAdapterInformation
503	{
504	uint8_t IsaIOPort;
505	uint8_t IRQ;
506	unsigned char LowByteTerminated : 1;
507	unsigned char HighByteTerminated : 1;
508	unsigned char uReserved : 2; /* Reserved. */
509	unsigned char JP1 : 1; /* Whatever that means. */
510	unsigned char JP2 : 1; /* Whatever that means. */
511	unsigned char JP3 : 1; /* Whatever that means. */
512	/** Whether the provided info is valid. */
513	unsigned char InformationIsValid: 1;
514	uint8_t uReserved2; /* Reserved. */
515	} ReplyInquirePCIHostAdapterInformation, *PReplyInquirePCIHostAdapterInformation;
516	AssertCompileSize(ReplyInquirePCIHostAdapterInformation, 4);
517
518	/** Structure for the INQUIRE_CONFIGURATION reply. */
519	typedef struct ReplyInquireConfiguration
520	{
521	unsigned char uReserved1 : 5;
522	bool fDmaChannel5 : 1;
523	bool fDmaChannel6 : 1;
524	bool fDmaChannel7 : 1;
525	bool fIrqChannel9 : 1;
526	bool fIrqChannel10 : 1;
527	bool fIrqChannel11 : 1;
528	bool fIrqChannel12 : 1;
529	unsigned char uReserved2 : 1;
530	bool fIrqChannel14 : 1;
531	bool fIrqChannel15 : 1;
532	unsigned char uReserved3 : 1;
533	unsigned char uHostAdapterId : 4;
534	unsigned char uReserved4 : 4;
535	} ReplyInquireConfiguration, *PReplyInquireConfiguration;
536	AssertCompileSize(ReplyInquireConfiguration, 3);
537
538	/** Structure for the INQUIRE_SETUP_INFORMATION reply. */
539	typedef struct ReplyInquireSetupInformationSynchronousValue
540	{
541	unsigned char uOffset : 4;
542	unsigned char uTransferPeriod : 3;
543	bool fSynchronous : 1;
544	}ReplyInquireSetupInformationSynchronousValue, *PReplyInquireSetupInformationSynchronousValue;
545	AssertCompileSize(ReplyInquireSetupInformationSynchronousValue, 1);
546
547	typedef struct ReplyInquireSetupInformation
548	{
549	bool fSynchronousInitiationEnabled : 1;
550	bool fParityCheckingEnabled : 1;
551	unsigned char uReserved1 : 6;
552	uint8_t uBusTransferRate;
553	uint8_t uPreemptTimeOnBus;
554	uint8_t uTimeOffBus;
555	uint8_t cMailbox;
556	Addr24 MailboxAddress;
557	ReplyInquireSetupInformationSynchronousValue SynchronousValuesId0To7[8];
558	uint8_t uDisconnectPermittedId0To7;
559	uint8_t uSignature;
560	uint8_t uCharacterD;
561	uint8_t uHostBusType;
562	uint8_t uWideTransferPermittedId0To7;
563	uint8_t uWideTransfersActiveId0To7;
564	ReplyInquireSetupInformationSynchronousValue SynchronousValuesId8To15[8];
565	uint8_t uDisconnectPermittedId8To15;
566	uint8_t uReserved2;
567	uint8_t uWideTransferPermittedId8To15;
568	uint8_t uWideTransfersActiveId8To15;
569	} ReplyInquireSetupInformation, *PReplyInquireSetupInformation;
570	AssertCompileSize(ReplyInquireSetupInformation, 34);
571
572	/** Structure for the INQUIRE_EXTENDED_SETUP_INFORMATION. */
573	#pragma pack(1)
574	typedef struct ReplyInquireExtendedSetupInformation
575	{
576	uint8_t uBusType;
577	uint8_t uBiosAddress;
578	uint16_t u16ScatterGatherLimit;
579	uint8_t cMailbox;
580	uint32_t uMailboxAddressBase;
581	unsigned char uReserved1 : 2;
582	bool fFastEISA : 1;
583	unsigned char uReserved2 : 3;
584	bool fLevelSensitiveInterrupt : 1;
585	unsigned char uReserved3 : 1;
586	unsigned char aFirmwareRevision[3];
587	bool fHostWideSCSI : 1;
588	bool fHostDifferentialSCSI : 1;
589	bool fHostSupportsSCAM : 1;
590	bool fHostUltraSCSI : 1;
591	bool fHostSmartTermination : 1;
592	unsigned char uReserved4 : 3;
593	} ReplyInquireExtendedSetupInformation, *PReplyInquireExtendedSetupInformation;
594	AssertCompileSize(ReplyInquireExtendedSetupInformation, 14);
595	#pragma pack()
596
597	/** Structure for the INITIALIZE EXTENDED MAILBOX request. */
598	#pragma pack(1)
599	typedef struct RequestInitializeExtendedMailbox
600	{
601	/** Number of mailboxes in guest memory. */
602	uint8_t cMailbox;
603	/** Physical address of the first mailbox. */
604	uint32_t uMailboxBaseAddress;
605	} RequestInitializeExtendedMailbox, *PRequestInitializeExtendedMailbox;
606	AssertCompileSize(RequestInitializeExtendedMailbox, 5);
607	#pragma pack()
608
609	/** Structure for the INITIALIZE MAILBOX request. */
610	typedef struct
611	{
612	/** Number of mailboxes to set up. */
613	uint8_t cMailbox;
614	/** Physical address of the first mailbox. */
615	Addr24 aMailboxBaseAddr;
616	} RequestInitMbx, *PRequestInitMbx;
617	AssertCompileSize(RequestInitMbx, 4);
618
619	/**
620	* Structure of a mailbox in guest memory.
621	* The incoming and outgoing mailbox have the same size
622	* but the incoming one has some more fields defined which
623	* are marked as reserved in the outgoing one.
624	* The last field is also different from the type.
625	* For outgoing mailboxes it is the action and
626	* for incoming ones the completion status code for the task.
627	* We use one structure for both types.
628	*/
629	typedef struct Mailbox32
630	{
631	/** Physical address of the CCB structure in the guest memory. */
632	uint32_t u32PhysAddrCCB;
633	/** Type specific data. */
634	union
635	{
636	/** For outgoing mailboxes. */
637	struct
638	{
639	/** Reserved */
640	uint8_t uReserved[3];
641	/** Action code. */
642	uint8_t uActionCode;
643	} out;
644	/** For incoming mailboxes. */
645	struct
646	{
647	/** The host adapter status after finishing the request. */
648	uint8_t uHostAdapterStatus;
649	/** The status of the device which executed the request after executing it. */
650	uint8_t uTargetDeviceStatus;
651	/** Reserved. */
652	uint8_t uReserved;
653	/** The completion status code of the request. */
654	uint8_t uCompletionCode;
655	} in;
656	} u;
657	} Mailbox32, *PMailbox32;
658	AssertCompileSize(Mailbox32, 8);
659
660	/** Old style 24-bit mailbox entry. */
661	typedef struct Mailbox24
662	{
663	/** Mailbox command (incoming) or state (outgoing). */
664	uint8_t uCmdState;
665	/** Physical address of the CCB structure in the guest memory. */
666	Addr24 aPhysAddrCCB;
667	} Mailbox24, *PMailbox24;
668	AssertCompileSize(Mailbox24, 4);
669
670	/**
671	* Action codes for outgoing mailboxes.
672	*/
673	enum BUSLOGIC_MAILBOX_OUTGOING_ACTION
674	{
675	BUSLOGIC_MAILBOX_OUTGOING_ACTION_FREE = 0x00,
676	BUSLOGIC_MAILBOX_OUTGOING_ACTION_START_COMMAND = 0x01,
677	BUSLOGIC_MAILBOX_OUTGOING_ACTION_ABORT_COMMAND = 0x02
678	};
679
680	/**
681	* Completion codes for incoming mailboxes.
682	*/
683	enum BUSLOGIC_MAILBOX_INCOMING_COMPLETION
684	{
685	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_FREE = 0x00,
686	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITHOUT_ERROR = 0x01,
687	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_ABORTED = 0x02,
688	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_ABORTED_NOT_FOUND = 0x03,
689	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITH_ERROR = 0x04,
690	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_INVALID_CCB = 0x05
691	};
692
693	/**
694	* Host adapter status for incoming mailboxes.
695	*/
696	enum BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS
697	{
698	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_CMD_COMPLETED = 0x00,
699	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_LINKED_CMD_COMPLETED = 0x0a,
700	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_LINKED_CMD_COMPLETED_WITH_FLAG = 0x0b,
701	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_DATA_UNDERUN = 0x0c,
702	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_SCSI_SELECTION_TIMEOUT = 0x11,
703	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_DATA_OVERRUN = 0x12,
704	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_UNEXPECTED_BUS_FREE = 0x13,
705	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_INVALID_BUS_PHASE_REQUESTED = 0x14,
706	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_INVALID_OUTGOING_MAILBOX_ACTION_CODE = 0x15,
707	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_INVALID_COMMAND_OPERATION_CODE = 0x16,
708	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_LINKED_CCB_HAS_INVALID_LUN = 0x17,
709	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_INVALID_COMMAND_PARAMETER = 0x1a,
710	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_AUTO_REQUEST_SENSE_FAILED = 0x1b,
711	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_TAGGED_QUEUING_MESSAGE_REJECTED = 0x1c,
712	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_UNSUPPORTED_MESSAGE_RECEIVED = 0x1d,
713	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_HARDWARE_FAILED = 0x20,
714	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_TARGET_FAILED_RESPONSE_TO_ATN = 0x21,
715	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_ASSERTED_RST = 0x22,
716	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_OTHER_DEVICE_ASSERTED_RST = 0x23,
717	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_TARGET_DEVICE_RECONNECTED_IMPROPERLY = 0x24,
718	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_ASSERTED_BUS_DEVICE_RESET = 0x25,
719	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_ABORT_QUEUE_GENERATED = 0x26,
720	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_SOFTWARE_ERROR = 0x27,
721	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_HARDWARE_TIMEOUT_ERROR = 0x30,
722	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_SCSI_PARITY_ERROR_DETECTED = 0x34
723	};
724
725	/**
726	* Device status codes for incoming mailboxes.
727	*/
728	enum BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS
729	{
730	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_OPERATION_GOOD = 0x00,
731	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_CHECK_CONDITION = 0x02,
732	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_DEVICE_BUSY = 0x08
733	};
734
735	/**
736	* Opcode types for CCB.
737	*/
738	enum BUSLOGIC_CCB_OPCODE
739	{
740	BUSLOGIC_CCB_OPCODE_INITIATOR_CCB = 0x00,
741	BUSLOGIC_CCB_OPCODE_TARGET_CCB = 0x01,
742	BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_SCATTER_GATHER = 0x02,
743	BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_DATA_LENGTH = 0x03,
744	BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_SCATTER_GATHER = 0x04,
745	BUSLOGIC_CCB_OPCODE_BUS_DEVICE_RESET = 0x81
746	};
747
748	/**
749	* Data transfer direction.
750	*/
751	enum BUSLOGIC_CCB_DIRECTION
752	{
753	BUSLOGIC_CCB_DIRECTION_UNKNOWN = 0x00,
754	BUSLOGIC_CCB_DIRECTION_IN = 0x01,
755	BUSLOGIC_CCB_DIRECTION_OUT = 0x02,
756	BUSLOGIC_CCB_DIRECTION_NO_DATA = 0x03
757	};
758
759	/**
760	* The command control block for a SCSI request.
761	*/
762	typedef struct CCB32
763	{
764	/** Opcode. */
765	uint8_t uOpcode;
766	/** Reserved */
767	unsigned char uReserved1 : 3;
768	/** Data direction for the request. */
769	unsigned char uDataDirection : 2;
770	/** Whether the request is tag queued. */
771	bool fTagQueued : 1;
772	/** Queue tag mode. */
773	unsigned char uQueueTag : 2;
774	/** Length of the SCSI CDB. */
775	uint8_t cbCDB;
776	/** Sense data length. */
777	uint8_t cbSenseData;
778	/** Data length. */
779	uint32_t cbData;
780	/** Data pointer.
781	* This points to the data region or a scatter gather list based on the opcode.
782	*/
783	uint32_t u32PhysAddrData;
784	/** Reserved. */
785	uint8_t uReserved2[2];
786	/** Host adapter status. */
787	uint8_t uHostAdapterStatus;
788	/** Device adapter status. */
789	uint8_t uDeviceStatus;
790	/** The device the request is sent to. */
791	uint8_t uTargetId;
792	/*The LUN in the device. /
793	unsigned char uLogicalUnit : 5;
794	/** Legacy tag. */
795	bool fLegacyTagEnable : 1;
796	/** Legacy queue tag. */
797	unsigned char uLegacyQueueTag : 2;
798	/** The SCSI CDB. (A CDB can be 12 bytes long.) */
799	uint8_t abCDB[12];
800	/** Reserved. */
801	uint8_t uReserved3[6];
802	/** Sense data pointer. */
803	uint32_t u32PhysAddrSenseData;
804	} CCB32, *PCCB32;
805	AssertCompileSize(CCB32, 40);
806
807
808	/**
809	* The 24-bit command control block.
810	*/
811	typedef struct CCB24
812	{
813	/** Opcode. */
814	uint8_t uOpcode;
815	/** The LUN in the device. */
816	unsigned char uLogicalUnit : 3;
817	/** Data direction for the request. */
818	unsigned char uDataDirection : 2;
819	/** The target device ID. */
820	unsigned char uTargetId : 3;
821	/** Length of the SCSI CDB. */
822	uint8_t cbCDB;
823	/** Sense data length. */
824	uint8_t cbSenseData;
825	/** Data length. */
826	Len24 acbData;
827	/** Data pointer.
828	* This points to the data region or a scatter gather list based on the opc
829	*/
830	Addr24 aPhysAddrData;
831	/** Pointer to next CCB for linked commands. */
832	Addr24 aPhysAddrLink;
833	/** Command linking identifier. */
834	uint8_t uLinkId;
835	/** Host adapter status. */
836	uint8_t uHostAdapterStatus;
837	/** Device adapter status. */
838	uint8_t uDeviceStatus;
839	/** Two unused bytes. */
840	uint8_t aReserved[2];
841	/** The SCSI CDB. (A CDB can be 12 bytes long.) */
842	uint8_t abCDB[12];
843	} CCB24, *PCCB24;
844	AssertCompileSize(CCB24, 30);
845
846	/**
847	* The common 24-bit/32-bit command control block. The 32-bit CCB is laid out
848	* such that many fields are in the same location as in the older 24-bit CCB.
849	*/
850	typedef struct CCBC
851	{
852	/** Opcode. */
853	uint8_t uOpcode;
854	/** The LUN in the device. */
855	unsigned char uPad1 : 3;
856	/** Data direction for the request. */
857	unsigned char uDataDirection : 2;
858	/** The target device ID. */
859	unsigned char uPad2 : 3;
860	/** Length of the SCSI CDB. */
861	uint8_t cbCDB;
862	/** Sense data length. */
863	uint8_t cbSenseData;
864	uint8_t aPad1[10];
865	/** Host adapter status. */
866	uint8_t uHostAdapterStatus;
867	/** Device adapter status. */
868	uint8_t uDeviceStatus;
869	uint8_t aPad2[2];
870	/** The SCSI CDB (up to 12 bytes). */
871	uint8_t abCDB[12];
872	} CCBC, *PCCBC;
873	AssertCompileSize(CCB24, 30);
874
875	/* Make sure that the 24-bit/32-bit/common CCB offsets match. */
876	AssertCompileMemberOffset(CCBC, cbCDB, 2);
877	AssertCompileMemberOffset(CCB24, cbCDB, 2);
878	AssertCompileMemberOffset(CCB32, cbCDB, 2);
879	AssertCompileMemberOffset(CCBC, uHostAdapterStatus, 14);
880	AssertCompileMemberOffset(CCB24, uHostAdapterStatus, 14);
881	AssertCompileMemberOffset(CCB32, uHostAdapterStatus, 14);
882	AssertCompileMemberOffset(CCBC, abCDB, 18);
883	AssertCompileMemberOffset(CCB24, abCDB, 18);
884	AssertCompileMemberOffset(CCB32, abCDB, 18);
885
886	/** A union of all CCB types (24-bit/32-bit/common). */
887	typedef union CCBU
888	{
889	CCB32 n; /*< New 32-bit CCB. /
890	CCB24 o; /*< Old 24-bit CCB. /
891	CCBC c; /*< Common CCB subset. /
892	} CCBU, *PCCBU;
893
894	/** 32-bit scatter-gather list entry. */
895	typedef struct SGE32
896	{
897	uint32_t cbSegment;
898	uint32_t u32PhysAddrSegmentBase;
899	} SGE32, *PSGE32;
900	AssertCompileSize(SGE32, 8);
901
902	/** 24-bit scatter-gather list entry. */
903	typedef struct SGE24
904	{
905	Len24 acbSegment;
906	Addr24 aPhysAddrSegmentBase;
907	} SGE24, *PSGE24;
908	AssertCompileSize(SGE24, 6);
909
910	/**
911	* The structure for the "Execute SCSI Command" command.
912	*/
913	typedef struct ESCMD
914	{
915	/** Data length. */
916	uint32_t cbData;
917	/** Data pointer. */
918	uint32_t u32PhysAddrData;
919	/** The device the request is sent to. */
920	uint8_t uTargetId;
921	/** The LUN in the device. */
922	uint8_t uLogicalUnit;
923	/** Reserved */
924	unsigned char uReserved1 : 3;
925	/** Data direction for the request. */
926	unsigned char uDataDirection : 2;
927	/** Reserved */
928	unsigned char uReserved2 : 3;
929	/** Length of the SCSI CDB. */
930	uint8_t cbCDB;
931	/** The SCSI CDB. (A CDB can be 12 bytes long.) */
932	uint8_t abCDB[12];
933	} ESCMD, *PESCMD;
934	AssertCompileSize(ESCMD, 24);
935
936	/**
937	* Task state for a CCB request.
938	*/
939	typedef struct BUSLOGICTASKSTATE
940	{
941	/** Next in the redo list. */
942	PBUSLOGICTASKSTATE pRedoNext;
943	/** Device this task is assigned to. */
944	R3PTRTYPE(PBUSLOGICDEVICE) pTargetDeviceR3;
945	/** The command control block from the guest. */
946	CCBU CommandControlBlockGuest;
947	/** Mailbox read from guest memory. */
948	Mailbox32 MailboxGuest;
949	/** The SCSI request we pass to the underlying SCSI engine. */
950	PDMSCSIREQUEST PDMScsiRequest;
951	/** Data buffer segment */
952	RTSGSEG DataSeg;
953	/** Pointer to the R3 sense buffer. */
954	uint8_t *pbSenseBuffer;
955	/** Flag whether this is a request from the BIOS. */
956	bool fBIOS;
957	/** 24-bit request flag (default is 32-bit). */
958	bool fIs24Bit;
959	/** S/G entry size (depends on the above flag). */
960	uint8_t cbSGEntry;
961	} BUSLOGICTASKSTATE;
962
963	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
964
965	#define PDMIBASE_2_PBUSLOGICDEVICE(pInterface) ( (PBUSLOGICDEVICE)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGICDEVICE, IBase)) )
966	#define PDMISCSIPORT_2_PBUSLOGICDEVICE(pInterface) ( (PBUSLOGICDEVICE)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGICDEVICE, ISCSIPort)) )
967	#define PDMILEDPORTS_2_PBUSLOGICDEVICE(pInterface) ( (PBUSLOGICDEVICE)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGICDEVICE, ILed)) )
968	#define PDMIBASE_2_PBUSLOGIC(pInterface) ( (PBUSLOGIC)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGIC, IBase)) )
969	#define PDMILEDPORTS_2_PBUSLOGIC(pInterface) ( (PBUSLOGIC)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGIC, ILeds)) )
970
971	/*******************************************************************************
972	* Internal Functions *
973	*******************************************************************************/
974	static int buslogicR3RegisterISARange(PBUSLOGIC pBusLogic, uint8_t uBaseCode);
975
976
977	/**
978	* Assert IRQ line of the BusLogic adapter.
979	*
980	* @returns nothing.
981	* @param pBusLogic Pointer to the BusLogic device instance.
982	* @param fSuppressIrq Flag to suppress IRQ generation regardless of fIRQEnabled
983	* @param uFlag Type of interrupt being generated.
984	*/
985	static void buslogicSetInterrupt(PBUSLOGIC pBusLogic, bool fSuppressIrq, uint8_t uIrqType)
986	{
987	LogFlowFunc(("pBusLogic=%#p\n", pBusLogic));
988
989	/* The CMDC interrupt has priority over IMBL and MBOR. */
990	if (uIrqType & (BUSLOGIC_REGISTER_INTERRUPT_INCOMING_MAILBOX_LOADED \| BUSLOGIC_REGISTER_INTERRUPT_OUTGOING_MAILBOX_AVAILABLE))
991	{
992	if (!(pBusLogic->regInterrupt & BUSLOGIC_REGISTER_INTERRUPT_COMMAND_COMPLETE))
993	pBusLogic->regInterrupt \|= uIrqType; /* Report now. */
994	else
995	pBusLogic->uPendingIntr \|= uIrqType; /* Report later. */
996	}
997	else if (uIrqType & BUSLOGIC_REGISTER_INTERRUPT_COMMAND_COMPLETE)
998	{
999	Assert(!pBusLogic->regInterrupt);
1000	pBusLogic->regInterrupt \|= uIrqType;
1001	}
1002	else
1003	AssertMsgFailed(("Invalid interrupt state!\n"));
1004
1005	pBusLogic->regInterrupt \|= BUSLOGIC_REGISTER_INTERRUPT_INTERRUPT_VALID;
1006	if (pBusLogic->fIRQEnabled && !fSuppressIrq)
1007	PDMDevHlpPCISetIrq(pBusLogic->CTX_SUFF(pDevIns), 0, 1);
1008	}
1009
1010	/**
1011	* Deasserts the interrupt line of the BusLogic adapter.
1012	*
1013	* @returns nothing
1014	* @param pBuslogic Pointer to the BusLogic device instance.
1015	*/
1016	static void buslogicClearInterrupt(PBUSLOGIC pBusLogic)
1017	{
1018	LogFlowFunc(("pBusLogic=%#p\n", pBusLogic));
1019	pBusLogic->regInterrupt = 0;
1020	PDMDevHlpPCISetIrq(pBusLogic->CTX_SUFF(pDevIns), 0, 0);
1021	/* If there's another pending interrupt, report it now. */
1022	if (pBusLogic->uPendingIntr)
1023	{
1024	buslogicSetInterrupt(pBusLogic, false, pBusLogic->uPendingIntr);
1025	pBusLogic->uPendingIntr = 0;
1026	}
1027	}
1028
1029	#if defined(IN_RING3)
1030
1031	/**
1032	* Advances the mailbox pointer to the next slot.
1033	*/
1034	DECLINLINE(void) buslogicR3OutgoingMailboxAdvance(PBUSLOGIC pBusLogic)
1035	{
1036	pBusLogic->uMailboxOutgoingPositionCurrent = (pBusLogic->uMailboxOutgoingPositionCurrent + 1) % pBusLogic->cMailbox;
1037	}
1038
1039	/**
1040	* Initialize local RAM of host adapter with default values.
1041	*
1042	* @returns nothing.
1043	* @param pBusLogic.
1044	*/
1045	static void buslogicR3InitializeLocalRam(PBUSLOGIC pBusLogic)
1046	{
1047	/*
1048	* These values are mostly from what I think is right
1049	* looking at the dmesg output from a Linux guest inside
1050	* a VMware server VM.
1051	*
1052	* So they don't have to be right :)
1053	*/
1054	memset(pBusLogic->LocalRam.u8View, 0, sizeof(HostAdapterLocalRam));
1055	pBusLogic->LocalRam.structured.autoSCSIData.fLevelSensitiveInterrupt = true;
1056	pBusLogic->LocalRam.structured.autoSCSIData.fParityCheckingEnabled = true;
1057	pBusLogic->LocalRam.structured.autoSCSIData.fExtendedTranslation = true; /* Same as in geometry register. */
1058	pBusLogic->LocalRam.structured.autoSCSIData.u16DeviceEnabledMask = ~0; /* All enabled. Maybe mask out non present devices? */
1059	pBusLogic->LocalRam.structured.autoSCSIData.u16WidePermittedMask = ~0;
1060	pBusLogic->LocalRam.structured.autoSCSIData.u16FastPermittedMask = ~0;
1061	pBusLogic->LocalRam.structured.autoSCSIData.u16SynchronousPermittedMask = ~0;
1062	pBusLogic->LocalRam.structured.autoSCSIData.u16DisconnectPermittedMask = ~0;
1063	pBusLogic->LocalRam.structured.autoSCSIData.fStrictRoundRobinMode = pBusLogic->fStrictRoundRobinMode;
1064	pBusLogic->LocalRam.structured.autoSCSIData.u16UltraPermittedMask = ~0;
1065	/** @todo calculate checksum? */
1066	}
1067
1068	/**
1069	* Do a hardware reset of the buslogic adapter.
1070	*
1071	* @returns VBox status code.
1072	* @param pBusLogic Pointer to the BusLogic device instance.
1073	* @param fResetIO Flag determining whether ISA I/O should be reset.
1074	*/
1075	static int buslogicR3HwReset(PBUSLOGIC pBusLogic, bool fResetIO)
1076	{
1077	LogFlowFunc(("pBusLogic=%#p\n", pBusLogic));
1078
1079	/* Reset registers to default value. */
1080	pBusLogic->regStatus = BUSLOGIC_REGISTER_STATUS_HOST_ADAPTER_READY \| BUSLOGIC_REGISTER_STATUS_INITIALIZATION_REQUIRED;
1081	pBusLogic->regInterrupt = 0;
1082	pBusLogic->uPendingIntr = 0;
1083	pBusLogic->regGeometry = BUSLOGIC_REGISTER_GEOMETRY_EXTENTED_TRANSLATION_ENABLED;
1084	pBusLogic->uOperationCode = 0xff; /* No command executing. */
1085	pBusLogic->iParameter = 0;
1086	pBusLogic->cbCommandParametersLeft = 0;
1087	pBusLogic->fIRQEnabled = true;
1088	pBusLogic->uMailboxOutgoingPositionCurrent = 0;
1089	pBusLogic->uMailboxIncomingPositionCurrent = 0;
1090
1091	/* Guest-initiated HBA reset does not affect ISA port I/O. */
1092	if (fResetIO)
1093	{
1094	buslogicR3RegisterISARange(pBusLogic, pBusLogic->uDefaultISABaseCode);
1095	}
1096	buslogicR3InitializeLocalRam(pBusLogic);
1097	vboxscsiInitialize(&pBusLogic->VBoxSCSI);
1098
1099	return VINF_SUCCESS;
1100	}
1101
1102	#endif /* IN_RING3 */
1103
1104	/**
1105	* Resets the command state machine for the next command and notifies the guest.
1106	*
1107	* @returns nothing.
1108	* @param pBusLogic Pointer to the BusLogic device instance
1109	* @param fSuppressIrq Flag to suppress IRQ generation regardless of current state
1110	*/
1111	static void buslogicCommandComplete(PBUSLOGIC pBusLogic, bool fSuppressIrq)
1112	{
1113	LogFlowFunc(("pBusLogic=%#p\n", pBusLogic));
1114
1115	pBusLogic->fUseLocalRam = false;
1116	pBusLogic->regStatus \|= BUSLOGIC_REGISTER_STATUS_HOST_ADAPTER_READY;
1117	pBusLogic->iReply = 0;
1118
1119	/* Modify I/O address does not generate an interrupt. */
1120	if (pBusLogic->uOperationCode != BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND)
1121	{
1122	/* Notify that the command is complete. */
1123	pBusLogic->regStatus &= ~BUSLOGIC_REGISTER_STATUS_DATA_IN_REGISTER_READY;
1124	buslogicSetInterrupt(pBusLogic, fSuppressIrq, BUSLOGIC_REGISTER_INTERRUPT_COMMAND_COMPLETE);
1125	}
1126
1127	pBusLogic->uOperationCode = 0xff;
1128	pBusLogic->iParameter = 0;
1129	}
1130
1131	#if defined(IN_RING3)
1132
1133	/**
1134	* Initiates a hard reset which was issued from the guest.
1135	*
1136	* @returns nothing
1137	* @param pBusLogic Pointer to the BusLogic device instance.
1138	* @param fHardReset Flag initiating a hard (vs. soft) reset.
1139	*/
1140	static void buslogicR3InitiateReset(PBUSLOGIC pBusLogic, bool fHardReset)
1141	{
1142	LogFlowFunc(("pBusLogic=%#p fHardReset=%d\n", pBusLogic, fHardReset));
1143
1144	buslogicR3HwReset(pBusLogic, false);
1145
1146	if (fHardReset)
1147	{
1148	/* Set the diagnostic active bit in the status register and clear the ready state. */
1149	pBusLogic->regStatus \|= BUSLOGIC_REGISTER_STATUS_DIAGNOSTIC_ACTIVE;
1150	pBusLogic->regStatus &= ~BUSLOGIC_REGISTER_STATUS_HOST_ADAPTER_READY;
1151
1152	/* Remember when the guest initiated a reset (after we're done resetting). */
1153	pBusLogic->u64ResetTime = PDMDevHlpTMTimeVirtGetNano(pBusLogic->CTX_SUFF(pDevIns));
1154	}
1155	}
1156
1157	/**
1158	* Send a mailbox with set status codes to the guest.
1159	*
1160	* @returns nothing.
1161	* @param pBusLogic Pointer to the BusLogic device instance.
1162	* @param pTaskState Pointer to the task state with the mailbox to send.
1163	* @param uHostAdapterStatus The host adapter status code to set.
1164	* @param uDeviceStatus The target device status to set.
1165	* @param uMailboxCompletionCode Completion status code to set in the mailbox.
1166	*/
1167	static void buslogicR3SendIncomingMailbox(PBUSLOGIC pBusLogic, PBUSLOGICTASKSTATE pTaskState,
1168	uint8_t uHostAdapterStatus, uint8_t uDeviceStatus,
1169	uint8_t uMailboxCompletionCode)
1170	{
1171	pTaskState->MailboxGuest.u.in.uHostAdapterStatus = uHostAdapterStatus;
1172	pTaskState->MailboxGuest.u.in.uTargetDeviceStatus = uDeviceStatus;
1173	pTaskState->MailboxGuest.u.in.uCompletionCode = uMailboxCompletionCode;
1174
1175	int rc = PDMCritSectEnter(&pBusLogic->CritSectIntr, VINF_SUCCESS);
1176	AssertRC(rc);
1177	RTGCPHYS GCPhysAddrCCB = pTaskState->MailboxGuest.u32PhysAddrCCB;
1178	RTGCPHYS GCPhysAddrMailboxIncoming = pBusLogic->GCPhysAddrMailboxIncomingBase
1179	+ ( pBusLogic->uMailboxIncomingPositionCurrent
1180	* (pTaskState->fIs24Bit ? sizeof(Mailbox24) : sizeof(Mailbox32)) );
1181	LogFlowFunc(("Completing CCB %RGp hstat=%u, dstat=%u, outgoing mailbox at %RGp\n", GCPhysAddrCCB,
1182	uHostAdapterStatus, uDeviceStatus, GCPhysAddrMailboxIncoming));
1183
1184	/* Update CCB. */
1185	pTaskState->CommandControlBlockGuest.c.uHostAdapterStatus = uHostAdapterStatus;
1186	pTaskState->CommandControlBlockGuest.c.uDeviceStatus = uDeviceStatus;
1187	/* Rewrite CCB up to the CDB; perhaps more than necessary. */
1188	PDMDevHlpPhysWrite(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrCCB, &pTaskState->CommandControlBlockGuest, RT_OFFSETOF(CCBC, abCDB));
1189
1190	# ifdef RT_STRICT
1191	uint8_t uCode;
1192	unsigned uCodeOffs = pTaskState->fIs24Bit ? RT_OFFSETOF(Mailbox24, uCmdState) : RT_OFFSETOF(Mailbox32, u.out.uActionCode);
1193	PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrMailboxIncoming + uCodeOffs, &uCode, sizeof(uCode));
1194	Assert(uCode == BUSLOGIC_MAILBOX_INCOMING_COMPLETION_FREE);
1195	# endif
1196
1197	/* Update mailbox. */
1198	if (pTaskState->fIs24Bit)
1199	{
1200	Mailbox24 Mbx24;
1201
1202	Mbx24.uCmdState = pTaskState->MailboxGuest.u.in.uCompletionCode;
1203	U32_TO_ADDR(Mbx24.aPhysAddrCCB, pTaskState->MailboxGuest.u32PhysAddrCCB);
1204	Log(("24-bit mailbox: completion code=%u, CCB at %RGp\n", Mbx24.uCmdState, (RTGCPHYS)ADDR_TO_U32(Mbx24.aPhysAddrCCB)));
1205	PDMDevHlpPhysWrite(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrMailboxIncoming, &Mbx24, sizeof(Mailbox24));
1206	}
1207	else
1208	{
1209	Log(("32-bit mailbox: completion code=%u, CCB at %RGp\n", pTaskState->MailboxGuest.u.in.uCompletionCode, (RTGCPHYS)pTaskState->MailboxGuest.u32PhysAddrCCB));
1210	PDMDevHlpPhysWrite(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrMailboxIncoming, &pTaskState->MailboxGuest, sizeof(Mailbox32));
1211	}
1212
1213	/* Advance to next mailbox position. */
1214	pBusLogic->uMailboxIncomingPositionCurrent++;
1215	if (pBusLogic->uMailboxIncomingPositionCurrent >= pBusLogic->cMailbox)
1216	pBusLogic->uMailboxIncomingPositionCurrent = 0;
1217
1218	# ifdef LOG_ENABLED
1219	ASMAtomicIncU32(&pBusLogic->cInMailboxesReady);
1220	# endif
1221
1222	buslogicSetInterrupt(pBusLogic, false, BUSLOGIC_REGISTER_INTERRUPT_INCOMING_MAILBOX_LOADED);
1223
1224	PDMCritSectLeave(&pBusLogic->CritSectIntr);
1225	}
1226
1227	# ifdef LOG_ENABLED
1228
1229	/**
1230	* Dumps the content of a mailbox for debugging purposes.
1231	*
1232	* @return nothing
1233	* @param pMailbox The mailbox to dump.
1234	* @param fOutgoing true if dumping the outgoing state.
1235	* false if dumping the incoming state.
1236	*/
1237	static void buslogicR3DumpMailboxInfo(PMailbox32 pMailbox, bool fOutgoing)
1238	{
1239	Log(("%s: Dump for %s mailbox:\n", __FUNCTION__, fOutgoing ? "outgoing" : "incoming"));
1240	Log(("%s: u32PhysAddrCCB=%#x\n", __FUNCTION__, pMailbox->u32PhysAddrCCB));
1241	if (fOutgoing)
1242	{
1243	Log(("%s: uActionCode=%u\n", __FUNCTION__, pMailbox->u.out.uActionCode));
1244	}
1245	else
1246	{
1247	Log(("%s: uHostAdapterStatus=%u\n", __FUNCTION__, pMailbox->u.in.uHostAdapterStatus));
1248	Log(("%s: uTargetDeviceStatus=%u\n", __FUNCTION__, pMailbox->u.in.uTargetDeviceStatus));
1249	Log(("%s: uCompletionCode=%u\n", __FUNCTION__, pMailbox->u.in.uCompletionCode));
1250	}
1251	}
1252
1253	/**
1254	* Dumps the content of a command control block for debugging purposes.
1255	*
1256	* @returns nothing.
1257	* @param pCCB Pointer to the command control block to dump.
1258	* @param fIs24BitCCB Flag to determine CCB format.
1259	*/
1260	static void buslogicR3DumpCCBInfo(PCCBU pCCB, bool fIs24BitCCB)
1261	{
1262	Log(("%s: Dump for %s Command Control Block:\n", __FUNCTION__, fIs24BitCCB ? "24-bit" : "32-bit"));
1263	Log(("%s: uOpCode=%#x\n", __FUNCTION__, pCCB->c.uOpcode));
1264	Log(("%s: uDataDirection=%u\n", __FUNCTION__, pCCB->c.uDataDirection));
1265	Log(("%s: cbCDB=%u\n", __FUNCTION__, pCCB->c.cbCDB));
1266	Log(("%s: cbSenseData=%u\n", __FUNCTION__, pCCB->c.cbSenseData));
1267	Log(("%s: uHostAdapterStatus=%u\n", __FUNCTION__, pCCB->c.uHostAdapterStatus));
1268	Log(("%s: uDeviceStatus=%u\n", __FUNCTION__, pCCB->c.uDeviceStatus));
1269	if (fIs24BitCCB)
1270	{
1271	Log(("%s: cbData=%u\n", __FUNCTION__, LEN_TO_U32(pCCB->o.acbData)));
1272	Log(("%s: PhysAddrData=%#x\n", __FUNCTION__, ADDR_TO_U32(pCCB->o.aPhysAddrData)));
1273	Log(("%s: uTargetId=%u\n", __FUNCTION__, pCCB->o.uTargetId));
1274	Log(("%s: uLogicalUnit=%u\n", __FUNCTION__, pCCB->o.uLogicalUnit));
1275	}
1276	else
1277	{
1278	Log(("%s: cbData=%u\n", __FUNCTION__, pCCB->n.cbData));
1279	Log(("%s: PhysAddrData=%#x\n", __FUNCTION__, pCCB->n.u32PhysAddrData));
1280	Log(("%s: uTargetId=%u\n", __FUNCTION__, pCCB->n.uTargetId));
1281	Log(("%s: uLogicalUnit=%u\n", __FUNCTION__, pCCB->n.uLogicalUnit));
1282	Log(("%s: fTagQueued=%d\n", __FUNCTION__, pCCB->n.fTagQueued));
1283	Log(("%s: uQueueTag=%u\n", __FUNCTION__, pCCB->n.uQueueTag));
1284	Log(("%s: fLegacyTagEnable=%u\n", __FUNCTION__, pCCB->n.fLegacyTagEnable));
1285	Log(("%s: uLegacyQueueTag=%u\n", __FUNCTION__, pCCB->n.uLegacyQueueTag));
1286	Log(("%s: PhysAddrSenseData=%#x\n", __FUNCTION__, pCCB->n.u32PhysAddrSenseData));
1287	}
1288	Log(("%s: uCDB[0]=%#x\n", __FUNCTION__, pCCB->c.abCDB[0]));
1289	for (int i = 1; i < pCCB->c.cbCDB; i++)
1290	Log(("%s: uCDB[%d]=%u\n", __FUNCTION__, i, pCCB->c.abCDB[i]));
1291	}
1292
1293	# endif /* LOG_ENABLED */
1294
1295	/**
1296	* Allocate data buffer.
1297	*
1298	* @param pTaskState Pointer to the task state.
1299	* @param GCSGList Guest physical address of S/G list.
1300	* @param cEntries Number of list entries to read.
1301	* @param pSGEList Pointer to 32-bit S/G list storage.
1302	*/
1303	static void buslogicR3ReadSGEntries(PBUSLOGICTASKSTATE pTaskState, RTGCPHYS GCSGList, uint32_t cEntries, SGE32 *pSGEList)
1304	{
1305	PPDMDEVINS pDevIns = pTaskState->CTX_SUFF(pTargetDevice)->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);
1306	SGE24 aSGE24[32];
1307	Assert(cEntries <= RT_ELEMENTS(aSGE24));
1308
1309	/* Read the S/G entries. Convert 24-bit entries to 32-bit format. */
1310	if (pTaskState->fIs24Bit)
1311	{
1312	Log2(("Converting %u 24-bit S/G entries to 32-bit\n", cEntries));
1313	PDMDevHlpPhysRead(pDevIns, GCSGList, &aSGE24, cEntries * sizeof(SGE24));
1314	for (uint32_t i = 0; i < cEntries; ++i)
1315	{
1316	pSGEList[i].cbSegment = LEN_TO_U32(aSGE24[i].acbSegment);
1317	pSGEList[i].u32PhysAddrSegmentBase = ADDR_TO_U32(aSGE24[i].aPhysAddrSegmentBase);
1318	}
1319	}
1320	else
1321	PDMDevHlpPhysRead(pDevIns, GCSGList, pSGEList, cEntries * sizeof(SGE32));
1322	}
1323
1324	/**
1325	* Allocate data buffer.
1326	*
1327	* @returns VBox status code.
1328	* @param pTaskState Pointer to the task state.
1329	*/
1330	static int buslogicR3DataBufferAlloc(PBUSLOGICTASKSTATE pTaskState)
1331	{
1332	PPDMDEVINS pDevIns = pTaskState->CTX_SUFF(pTargetDevice)->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);
1333	uint32_t cbDataCCB;
1334	uint32_t u32PhysAddrCCB;
1335
1336	/* Extract the data length and physical address from the CCB. */
1337	if (pTaskState->fIs24Bit)
1338	{
1339	u32PhysAddrCCB = ADDR_TO_U32(pTaskState->CommandControlBlockGuest.o.aPhysAddrData);
1340	cbDataCCB = LEN_TO_U32(pTaskState->CommandControlBlockGuest.o.acbData);
1341	}
1342	else
1343	{
1344	u32PhysAddrCCB = pTaskState->CommandControlBlockGuest.n.u32PhysAddrData;
1345	cbDataCCB = pTaskState->CommandControlBlockGuest.n.cbData;
1346	}
1347
1348	if ( (pTaskState->CommandControlBlockGuest.c.uDataDirection != BUSLOGIC_CCB_DIRECTION_NO_DATA)
1349	&& cbDataCCB)
1350	{
1351	/** @todo Check following assumption and what residual means. */
1352	/*
1353	* The BusLogic adapter can handle two different data buffer formats.
1354	* The first one is that the data pointer entry in the CCB points to
1355	* the buffer directly. In second mode the data pointer points to a
1356	* scatter gather list which describes the buffer.
1357	*/
1358	if ( (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_SCATTER_GATHER)
1359	\|\| (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_SCATTER_GATHER))
1360	{
1361	uint32_t cScatterGatherGCRead;
1362	uint32_t iScatterGatherEntry;
1363	SGE32 aScatterGatherReadGC[32]; /* A buffer for scatter gather list entries read from guest memory. */
1364	uint32_t cScatterGatherGCLeft = cbDataCCB / pTaskState->cbSGEntry;
1365	RTGCPHYS GCPhysAddrScatterGatherCurrent = u32PhysAddrCCB;
1366	size_t cbDataToTransfer = 0;
1367
1368	/* Count number of bytes to transfer. */
1369	do
1370	{
1371	cScatterGatherGCRead = (cScatterGatherGCLeft < RT_ELEMENTS(aScatterGatherReadGC))
1372	? cScatterGatherGCLeft
1373	: RT_ELEMENTS(aScatterGatherReadGC);
1374	cScatterGatherGCLeft -= cScatterGatherGCRead;
1375
1376	buslogicR3ReadSGEntries(pTaskState, GCPhysAddrScatterGatherCurrent, cScatterGatherGCRead, aScatterGatherReadGC);
1377
1378	for (iScatterGatherEntry = 0; iScatterGatherEntry < cScatterGatherGCRead; iScatterGatherEntry++)
1379	{
1380	RTGCPHYS GCPhysAddrDataBase;
1381
1382	Log(("%s: iScatterGatherEntry=%u\n", __FUNCTION__, iScatterGatherEntry));
1383
1384	GCPhysAddrDataBase = (RTGCPHYS)aScatterGatherReadGC[iScatterGatherEntry].u32PhysAddrSegmentBase;
1385	cbDataToTransfer += aScatterGatherReadGC[iScatterGatherEntry].cbSegment;
1386
1387	Log(("%s: GCPhysAddrDataBase=%RGp cbDataToTransfer=%u\n",
1388	__FUNCTION__, GCPhysAddrDataBase,
1389	aScatterGatherReadGC[iScatterGatherEntry].cbSegment));
1390	}
1391
1392	/* Set address to the next entries to read. */
1393	GCPhysAddrScatterGatherCurrent += cScatterGatherGCRead * pTaskState->cbSGEntry;
1394	} while (cScatterGatherGCLeft > 0);
1395
1396	Log(("%s: cbDataToTransfer=%d\n", __FUNCTION__, cbDataToTransfer));
1397
1398	/* Allocate buffer */
1399	pTaskState->DataSeg.cbSeg = cbDataToTransfer;
1400	pTaskState->DataSeg.pvSeg = RTMemAlloc(pTaskState->DataSeg.cbSeg);
1401	if (!pTaskState->DataSeg.pvSeg)
1402	return VERR_NO_MEMORY;
1403
1404	/* Copy the data if needed */
1405	if ( (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_OUT)
1406	\|\| (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_UNKNOWN))
1407	{
1408	cScatterGatherGCLeft = cbDataCCB / pTaskState->cbSGEntry;
1409	GCPhysAddrScatterGatherCurrent = u32PhysAddrCCB;
1410	uint8_t pbData = (uint8_t )pTaskState->DataSeg.pvSeg;
1411
1412	do
1413	{
1414	cScatterGatherGCRead = (cScatterGatherGCLeft < RT_ELEMENTS(aScatterGatherReadGC))
1415	? cScatterGatherGCLeft
1416	: RT_ELEMENTS(aScatterGatherReadGC);
1417	cScatterGatherGCLeft -= cScatterGatherGCRead;
1418
1419	buslogicR3ReadSGEntries(pTaskState, GCPhysAddrScatterGatherCurrent, cScatterGatherGCRead, aScatterGatherReadGC);
1420
1421	for (iScatterGatherEntry = 0; iScatterGatherEntry < cScatterGatherGCRead; iScatterGatherEntry++)
1422	{
1423	RTGCPHYS GCPhysAddrDataBase;
1424
1425	Log(("%s: iScatterGatherEntry=%u\n", __FUNCTION__, iScatterGatherEntry));
1426
1427	GCPhysAddrDataBase = (RTGCPHYS)aScatterGatherReadGC[iScatterGatherEntry].u32PhysAddrSegmentBase;
1428	cbDataToTransfer = aScatterGatherReadGC[iScatterGatherEntry].cbSegment;
1429
1430	Log(("%s: GCPhysAddrDataBase=%RGp cbDataToTransfer=%u\n", __FUNCTION__, GCPhysAddrDataBase, cbDataToTransfer));
1431
1432	PDMDevHlpPhysRead(pDevIns, GCPhysAddrDataBase, pbData, cbDataToTransfer);
1433	pbData += cbDataToTransfer;
1434	}
1435
1436	/* Set address to the next entries to read. */
1437	GCPhysAddrScatterGatherCurrent += cScatterGatherGCRead * pTaskState->cbSGEntry;
1438	} while (cScatterGatherGCLeft > 0);
1439	}
1440
1441	}
1442	else if ( pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB
1443	\|\| pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_DATA_LENGTH)
1444	{
1445	/* The buffer is not scattered. */
1446	RTGCPHYS GCPhysAddrDataBase = u32PhysAddrCCB;
1447
1448	AssertMsg(GCPhysAddrDataBase != 0, ("Physical address is 0\n"));
1449
1450	pTaskState->DataSeg.cbSeg = cbDataCCB;
1451	pTaskState->DataSeg.pvSeg = RTMemAlloc(pTaskState->DataSeg.cbSeg);
1452	if (!pTaskState->DataSeg.pvSeg)
1453	return VERR_NO_MEMORY;
1454
1455	Log(("Non scattered buffer:\n"));
1456	Log(("u32PhysAddrData=%#x\n", u32PhysAddrCCB));
1457	Log(("cbData=%u\n", cbDataCCB));
1458	Log(("GCPhysAddrDataBase=0x%RGp\n", GCPhysAddrDataBase));
1459
1460	/* Copy the data into the buffer. */
1461	PDMDevHlpPhysRead(pDevIns, GCPhysAddrDataBase, pTaskState->DataSeg.pvSeg, pTaskState->DataSeg.cbSeg);
1462	}
1463	}
1464
1465	return VINF_SUCCESS;
1466	}
1467
1468	/**
1469	* Free allocated resources used for the scatter gather list.
1470	*
1471	* @returns nothing.
1472	* @param pTaskState Pointer to the task state.
1473	*/
1474	static void buslogicR3DataBufferFree(PBUSLOGICTASKSTATE pTaskState)
1475	{
1476	PPDMDEVINS pDevIns = pTaskState->CTX_SUFF(pTargetDevice)->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);
1477	uint32_t cbDataCCB;
1478	uint32_t u32PhysAddrCCB;
1479
1480	/* Extract the data length and physical address from the CCB. */
1481	if (pTaskState->fIs24Bit)
1482	{
1483	u32PhysAddrCCB = ADDR_TO_U32(pTaskState->CommandControlBlockGuest.o.aPhysAddrData);
1484	cbDataCCB = LEN_TO_U32(pTaskState->CommandControlBlockGuest.o.acbData);
1485	}
1486	else
1487	{
1488	u32PhysAddrCCB = pTaskState->CommandControlBlockGuest.n.u32PhysAddrData;
1489	cbDataCCB = pTaskState->CommandControlBlockGuest.n.cbData;
1490	}
1491
1492	#if 1
1493	/* Hack for NT 10/91: A CCB describes a 2K buffer, but TEST UNIT READY is executed. This command
1494	* returns no data, hence the buffer must be left alone!
1495	*/
1496	if (pTaskState->CommandControlBlockGuest.c.abCDB[0] == 0)
1497	cbDataCCB = 0;
1498	#endif
1499
1500	LogFlowFunc(("pTaskState=%#p cbDataCCB=%u direction=%u cbSeg=%u\n", pTaskState, cbDataCCB,
1501	pTaskState->CommandControlBlockGuest.c.uDataDirection, pTaskState->DataSeg.cbSeg));
1502
1503	if ( (cbDataCCB > 0)
1504	&& ( (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_IN)
1505	\|\| (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_UNKNOWN)))
1506	{
1507	if ( (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_SCATTER_GATHER)
1508	\|\| (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_SCATTER_GATHER))
1509	{
1510	uint32_t cScatterGatherGCRead;
1511	uint32_t iScatterGatherEntry;
1512	SGE32 aScatterGatherReadGC[32]; /* Number of scatter gather list entries read from guest memory. */
1513	uint32_t cScatterGatherGCLeft = cbDataCCB / pTaskState->cbSGEntry;
1514	RTGCPHYS GCPhysAddrScatterGatherCurrent = u32PhysAddrCCB;
1515	uint8_t pbData = (uint8_t )pTaskState->DataSeg.pvSeg;
1516
1517	do
1518	{
1519	cScatterGatherGCRead = (cScatterGatherGCLeft < RT_ELEMENTS(aScatterGatherReadGC))
1520	? cScatterGatherGCLeft
1521	: RT_ELEMENTS(aScatterGatherReadGC);
1522	cScatterGatherGCLeft -= cScatterGatherGCRead;
1523
1524	buslogicR3ReadSGEntries(pTaskState, GCPhysAddrScatterGatherCurrent, cScatterGatherGCRead, aScatterGatherReadGC);
1525
1526	for (iScatterGatherEntry = 0; iScatterGatherEntry < cScatterGatherGCRead; iScatterGatherEntry++)
1527	{
1528	RTGCPHYS GCPhysAddrDataBase;
1529	size_t cbDataToTransfer;
1530
1531	Log(("%s: iScatterGatherEntry=%u\n", __FUNCTION__, iScatterGatherEntry));
1532
1533	GCPhysAddrDataBase = (RTGCPHYS)aScatterGatherReadGC[iScatterGatherEntry].u32PhysAddrSegmentBase;
1534	cbDataToTransfer = aScatterGatherReadGC[iScatterGatherEntry].cbSegment;
1535
1536	Log(("%s: GCPhysAddrDataBase=%RGp cbDataToTransfer=%u\n", __FUNCTION__, GCPhysAddrDataBase, cbDataToTransfer));
1537
1538	PDMDevHlpPhysWrite(pDevIns, GCPhysAddrDataBase, pbData, cbDataToTransfer);
1539	pbData += cbDataToTransfer;
1540	}
1541
1542	/* Set address to the next entries to read. */
1543	GCPhysAddrScatterGatherCurrent += cScatterGatherGCRead * pTaskState->cbSGEntry;
1544	} while (cScatterGatherGCLeft > 0);
1545
1546	}
1547	else if ( pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB
1548	\|\| pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_DATA_LENGTH)
1549	{
1550	/* The buffer is not scattered. */
1551	RTGCPHYS GCPhysAddrDataBase = u32PhysAddrCCB;
1552
1553	AssertMsg(GCPhysAddrDataBase != 0, ("Physical address is 0\n"));
1554
1555	Log(("Non-scattered buffer:\n"));
1556	Log(("u32PhysAddrData=%#x\n", u32PhysAddrCCB));
1557	Log(("cbData=%u\n", cbDataCCB));
1558	Log(("GCPhysAddrDataBase=0x%RGp\n", GCPhysAddrDataBase));
1559
1560	/* Copy the data into the guest memory. */
1561	PDMDevHlpPhysWrite(pDevIns, GCPhysAddrDataBase, pTaskState->DataSeg.pvSeg, pTaskState->DataSeg.cbSeg);
1562	}
1563
1564	}
1565	/* Update residual data length. */
1566	if ( (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_DATA_LENGTH)
1567	\|\| (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_SCATTER_GATHER))
1568	{
1569	uint32_t cbResidual;
1570
1571	/** @todo we need to get the actual transfer length from the VSCSI layer?! */
1572	cbResidual = 0; //LEN_TO_U32(pTaskState->CCBGuest.acbData) - ???;
1573	if (pTaskState->fIs24Bit)
1574	U32_TO_LEN(pTaskState->CommandControlBlockGuest.o.acbData, cbResidual);
1575	else
1576	pTaskState->CommandControlBlockGuest.n.cbData = cbResidual;
1577	}
1578
1579	RTMemFree(pTaskState->DataSeg.pvSeg);
1580	pTaskState->DataSeg.pvSeg = NULL;
1581	pTaskState->DataSeg.cbSeg = 0;
1582	}
1583
1584	/** Convert sense buffer length taking into account shortcut values. */
1585	static uint32_t buslogicR3ConvertSenseBufferLength(uint32_t cbSense)
1586	{
1587	/* Convert special sense buffer length values. */
1588	if (cbSense == 0)
1589	cbSense = 14; /* 0 means standard 14-byte buffer. */
1590	else if (cbSense == 1)
1591	cbSense = 0; /* 1 means no sense data. */
1592	else if (cbSense < 8)
1593	AssertMsgFailed(("Reserved cbSense value of %d used!\n", cbSense));
1594
1595	return cbSense;
1596	}
1597
1598	/**
1599	* Free the sense buffer.
1600	*
1601	* @returns nothing.
1602	* @param pTaskState Pointer to the task state.
1603	* @param fCopy If sense data should be copied to guest memory.
1604	*/
1605	static void buslogicR3SenseBufferFree(PBUSLOGICTASKSTATE pTaskState, bool fCopy)
1606	{
1607	uint32_t cbSenseBuffer;
1608
1609	cbSenseBuffer = buslogicR3ConvertSenseBufferLength(pTaskState->CommandControlBlockGuest.c.cbSenseData);
1610
1611	/* Copy the sense buffer into guest memory if requested. */
1612	if (fCopy && cbSenseBuffer)
1613	{
1614	PPDMDEVINS pDevIns = pTaskState->CTX_SUFF(pTargetDevice)->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);
1615	RTGCPHYS GCPhysAddrSenseBuffer;
1616
1617	/* With 32-bit CCBs, the (optional) sense buffer physical address is provided separately.
1618	* On the other hand, with 24-bit CCBs, the sense buffer is simply located at the end of
1619	* the CCB, right after the variable-length CDB.
1620	*/
1621	if (pTaskState->fIs24Bit)
1622	{
1623	GCPhysAddrSenseBuffer = pTaskState->MailboxGuest.u32PhysAddrCCB;
1624	GCPhysAddrSenseBuffer += pTaskState->CommandControlBlockGuest.c.cbCDB + RT_OFFSETOF(CCB24, abCDB);
1625	}
1626	else
1627	GCPhysAddrSenseBuffer = pTaskState->CommandControlBlockGuest.n.u32PhysAddrSenseData;
1628
1629	PDMDevHlpPhysWrite(pDevIns, GCPhysAddrSenseBuffer, pTaskState->pbSenseBuffer, cbSenseBuffer);
1630	}
1631
1632	RTMemFree(pTaskState->pbSenseBuffer);
1633	pTaskState->pbSenseBuffer = NULL;
1634	}
1635
1636	/**
1637	* Alloc the sense buffer.
1638	*
1639	* @returns VBox status code.
1640	* @param pTaskState Pointer to the task state.
1641	* @note Current assumption is that the sense buffer is not scattered and does not cross a page boundary.
1642	*/
1643	static int buslogicR3SenseBufferAlloc(PBUSLOGICTASKSTATE pTaskState)
1644	{
1645	PPDMDEVINS pDevIns = pTaskState->CTX_SUFF(pTargetDevice)->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);
1646	uint32_t cbSenseBuffer;
1647
1648	pTaskState->pbSenseBuffer = NULL;
1649
1650	cbSenseBuffer = buslogicR3ConvertSenseBufferLength(pTaskState->CommandControlBlockGuest.c.cbSenseData);
1651	if (cbSenseBuffer)
1652	{
1653	pTaskState->pbSenseBuffer = (uint8_t *)RTMemAllocZ(cbSenseBuffer);
1654	if (!pTaskState->pbSenseBuffer)
1655	return VERR_NO_MEMORY;
1656	}
1657
1658	return VINF_SUCCESS;
1659	}
1660
1661	#endif /* IN_RING3 */
1662
1663	/**
1664	* Parses the command buffer and executes it.
1665	*
1666	* @returns VBox status code.
1667	* @param pBusLogic Pointer to the BusLogic device instance.
1668	*/
1669	static int buslogicProcessCommand(PBUSLOGIC pBusLogic)
1670	{
1671	int rc = VINF_SUCCESS;
1672	bool fSuppressIrq = false;
1673
1674	LogFlowFunc(("pBusLogic=%#p\n", pBusLogic));
1675	AssertMsg(pBusLogic->uOperationCode != 0xff, ("There is no command to execute\n"));
1676
1677	switch (pBusLogic->uOperationCode)
1678	{
1679	case BUSLOGICCOMMAND_TEST_CMDC_INTERRUPT:
1680	/* Valid command, no reply. */
1681	pBusLogic->cbReplyParametersLeft = 0;
1682	break;
1683	case BUSLOGICCOMMAND_INQUIRE_PCI_HOST_ADAPTER_INFORMATION:
1684	{
1685	PReplyInquirePCIHostAdapterInformation pReply = (PReplyInquirePCIHostAdapterInformation)pBusLogic->aReplyBuffer;
1686	memset(pReply, 0, sizeof(ReplyInquirePCIHostAdapterInformation));
1687
1688	/* It seems VMware does not provide valid information here too, lets do the same :) */
1689	pReply->InformationIsValid = 0;
1690	pReply->IsaIOPort = pBusLogic->uISABaseCode;
1691	pReply->IRQ = PCIDevGetInterruptLine(&pBusLogic->dev);
1692	pBusLogic->cbReplyParametersLeft = sizeof(ReplyInquirePCIHostAdapterInformation);
1693	break;
1694	}
1695	case BUSLOGICCOMMAND_MODIFY_IO_ADDRESS:
1696	{
1697	/* Modify the ISA-compatible I/O port base. Note that this technically
1698	* violates the PCI spec, as this address is not reported through PCI.
1699	* However, it is required for compatibility with old drivers.
1700	*/
1701	#ifdef IN_RING3
1702	Log(("ISA I/O for PCI (code %x)\n", pBusLogic->aCommandBuffer[0]));
1703	buslogicR3RegisterISARange(pBusLogic, pBusLogic->aCommandBuffer[0]);
1704	pBusLogic->cbReplyParametersLeft = 0;
1705	fSuppressIrq = true;
1706	break;
1707	#else
1708	AssertMsgFailed(("Must never get here!\n"));
1709	#endif
1710	}
1711	case BUSLOGICCOMMAND_INQUIRE_BOARD_ID:
1712	{
1713	/* The special option byte is important: If it is '0' or 'B', Windows NT drivers
1714	* for Adaptec AHA-154x may claim the adapter. The BusLogic drivers will claim
1715	* the adapter only when the byte is not '0' or 'B'.
1716	*/
1717	pBusLogic->aReplyBuffer[0] = 'A'; /* Firmware option bytes */
1718	pBusLogic->aReplyBuffer[1] = 'A'; /* Special option byte */
1719
1720	/* We report version 5.07B. This reply will provide the first two digits. */
1721	pBusLogic->aReplyBuffer[2] = '5'; /* Major version 5 */
1722	pBusLogic->aReplyBuffer[3] = '0'; /* Minor version 0 */
1723	pBusLogic->cbReplyParametersLeft = 4; /* Reply is 4 bytes long */
1724	break;
1725	}
1726	case BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_3RD_LETTER:
1727	{
1728	pBusLogic->aReplyBuffer[0] = '7';
1729	pBusLogic->cbReplyParametersLeft = 1;
1730	break;
1731	}
1732	case BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_LETTER:
1733	{
1734	pBusLogic->aReplyBuffer[0] = 'B';
1735	pBusLogic->cbReplyParametersLeft = 1;
1736	break;
1737	}
1738	case BUSLOGICCOMMAND_SET_ADAPTER_OPTIONS:
1739	/* The parameter list length is determined by the first byte of the command buffer. */
1740	if (pBusLogic->iParameter == 1)
1741	{
1742	/* First pass - set the number of following parameter bytes. */
1743	pBusLogic->cbCommandParametersLeft = pBusLogic->aCommandBuffer[0];
1744	Log(("Set HA options: %u bytes follow\n", pBusLogic->cbCommandParametersLeft));
1745	}
1746	else
1747	{
1748	/* Second pass - process received data. */
1749	Log(("Set HA options: received %u bytes\n", pBusLogic->aCommandBuffer[0]));
1750	/* We ignore the data - it only concerns the SCSI hardware protocol. */
1751	}
1752	pBusLogic->cbReplyParametersLeft = 0;
1753	break;
1754
1755	case BUSLOGICCOMMAND_INQUIRE_HOST_ADAPTER_MODEL_NUMBER:
1756	{
1757	/* The reply length is set by the guest and is found in the first byte of the command buffer. */
1758	pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[0];
1759	memset(pBusLogic->aReplyBuffer, ' ', pBusLogic->cbReplyParametersLeft);
1760	const char aModelName[] = "958";
1761	int cCharsToTransfer = (pBusLogic->cbReplyParametersLeft <= (sizeof(aModelName) - 1))
1762	? pBusLogic->cbReplyParametersLeft
1763	: sizeof(aModelName) - 1;
1764
1765	for (int i = 0; i < cCharsToTransfer; i++)
1766	pBusLogic->aReplyBuffer[i] = aModelName[i];
1767
1768	break;
1769	}
1770	case BUSLOGICCOMMAND_INQUIRE_CONFIGURATION:
1771	{
1772	uint8_t uPciIrq = PCIDevGetInterruptLine(&pBusLogic->dev);
1773
1774	pBusLogic->cbReplyParametersLeft = sizeof(ReplyInquireConfiguration);
1775	PReplyInquireConfiguration pReply = (PReplyInquireConfiguration)pBusLogic->aReplyBuffer;
1776	memset(pReply, 0, sizeof(ReplyInquireConfiguration));
1777
1778	pReply->uHostAdapterId = 7; /* The controller has always 7 as ID. */
1779	pReply->fDmaChannel6 = 1; /* DMA channel 6 is a good default. */
1780	/* The PCI IRQ is not necessarily representable in this structure.
1781	* If that is the case, the guest likely won't function correctly,
1782	* therefore we log a warning.
1783	*/
1784	switch (uPciIrq)
1785	{
1786	case 9: pReply->fIrqChannel9 = 1; break;
1787	case 10: pReply->fIrqChannel10 = 1; break;
1788	case 11: pReply->fIrqChannel11 = 1; break;
1789	case 12: pReply->fIrqChannel12 = 1; break;
1790	case 14: pReply->fIrqChannel14 = 1; break;
1791	case 15: pReply->fIrqChannel15 = 1; break;
1792	default:
1793	LogRel(("Warning: PCI IRQ %d cannot be represented as ISA!\n", uPciIrq));
1794	break;
1795	}
1796	break;
1797	}
1798	case BUSLOGICCOMMAND_INQUIRE_EXTENDED_SETUP_INFORMATION:
1799	{
1800	/* Some Adaptec AHA-154x drivers (e.g. OS/2) execute this command and expect
1801	* it to fail. If it succeeds, the drivers refuse to load. However, some newer
1802	* Adaptec 154x models supposedly support it too??
1803	*/
1804
1805	/* The reply length is set by the guest and is found in the first byte of the command buffer. */
1806	pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[0];
1807	PReplyInquireExtendedSetupInformation pReply = (PReplyInquireExtendedSetupInformation)pBusLogic->aReplyBuffer;
1808	memset(pReply, 0, sizeof(ReplyInquireExtendedSetupInformation));
1809
1810	/** @todo should this reflect the RAM contents (AutoSCSIRam)? */
1811	pReply->uBusType = 'E'; /* EISA style */
1812	pReply->u16ScatterGatherLimit = 8192;
1813	pReply->cMailbox = pBusLogic->cMailbox;
1814	pReply->uMailboxAddressBase = (uint32_t)pBusLogic->GCPhysAddrMailboxOutgoingBase;
1815	pReply->fLevelSensitiveInterrupt = true;
1816	pReply->fHostWideSCSI = true;
1817	pReply->fHostUltraSCSI = true;
1818	memcpy(pReply->aFirmwareRevision, "07B", sizeof(pReply->aFirmwareRevision));
1819
1820	break;
1821	}
1822	case BUSLOGICCOMMAND_INQUIRE_SETUP_INFORMATION:
1823	{
1824	/* The reply length is set by the guest and is found in the first byte of the command buffer. */
1825	pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[0];
1826	PReplyInquireSetupInformation pReply = (PReplyInquireSetupInformation)pBusLogic->aReplyBuffer;
1827	memset(pReply, 0, sizeof(ReplyInquireSetupInformation));
1828	pReply->fSynchronousInitiationEnabled = true;
1829	pReply->fParityCheckingEnabled = true;
1830	pReply->cMailbox = pBusLogic->cMailbox;
1831	U32_TO_ADDR(pReply->MailboxAddress, pBusLogic->GCPhysAddrMailboxOutgoingBase);
1832	pReply->uSignature = 'B';
1833	/* The 'D' signature prevents Adaptec's OS/2 drivers from getting too
1834	* friendly with BusLogic hardware and upsetting the HBA state.
1835	*/
1836	pReply->uCharacterD = 'D'; /* BusLogic model. */
1837	pReply->uHostBusType = 'F'; /* PCI bus. */
1838	break;
1839	}
1840	case BUSLOGICCOMMAND_FETCH_HOST_ADAPTER_LOCAL_RAM:
1841	{
1842	/*
1843	* First element in the command buffer contains start offset to read from
1844	* and second one the number of bytes to read.
1845	*/
1846	uint8_t uOffset = pBusLogic->aCommandBuffer[0];
1847	pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[1];
1848
1849	pBusLogic->fUseLocalRam = true;
1850	pBusLogic->iReply = uOffset;
1851	break;
1852	}
1853	case BUSLOGICCOMMAND_INITIALIZE_MAILBOX:
1854	{
1855	PRequestInitMbx pRequest = (PRequestInitMbx)pBusLogic->aCommandBuffer;
1856
1857	pBusLogic->fMbxIs24Bit = true;
1858	pBusLogic->cMailbox = pRequest->cMailbox;
1859	pBusLogic->GCPhysAddrMailboxOutgoingBase = (RTGCPHYS)ADDR_TO_U32(pRequest->aMailboxBaseAddr);
1860	/* The area for incoming mailboxes is right after the last entry of outgoing mailboxes. */
1861	pBusLogic->GCPhysAddrMailboxIncomingBase = pBusLogic->GCPhysAddrMailboxOutgoingBase + (pBusLogic->cMailbox * sizeof(Mailbox24));
1862
1863	Log(("GCPhysAddrMailboxOutgoingBase=%RGp\n", pBusLogic->GCPhysAddrMailboxOutgoingBase));
1864	Log(("GCPhysAddrMailboxIncomingBase=%RGp\n", pBusLogic->GCPhysAddrMailboxIncomingBase));
1865	Log(("cMailboxes=%u (24-bit mode)\n", pBusLogic->cMailbox));
1866	LogRel(("Initialized 24-bit mailbox, %d entries at %08x\n", pRequest->cMailbox, ADDR_TO_U32(pRequest->aMailboxBaseAddr)));
1867
1868	pBusLogic->regStatus &= ~BUSLOGIC_REGISTER_STATUS_INITIALIZATION_REQUIRED;
1869	pBusLogic->cbReplyParametersLeft = 0;
1870	break;
1871	}
1872	case BUSLOGICCOMMAND_INITIALIZE_EXTENDED_MAILBOX:
1873	{
1874	PRequestInitializeExtendedMailbox pRequest = (PRequestInitializeExtendedMailbox)pBusLogic->aCommandBuffer;
1875
1876	pBusLogic->fMbxIs24Bit = false;
1877	pBusLogic->cMailbox = pRequest->cMailbox;
1878	pBusLogic->GCPhysAddrMailboxOutgoingBase = (RTGCPHYS)pRequest->uMailboxBaseAddress;
1879	/* The area for incoming mailboxes is right after the last entry of outgoing mailboxes. */
1880	pBusLogic->GCPhysAddrMailboxIncomingBase = (RTGCPHYS)pRequest->uMailboxBaseAddress + (pBusLogic->cMailbox * sizeof(Mailbox32));
1881
1882	Log(("GCPhysAddrMailboxOutgoingBase=%RGp\n", pBusLogic->GCPhysAddrMailboxOutgoingBase));
1883	Log(("GCPhysAddrMailboxIncomingBase=%RGp\n", pBusLogic->GCPhysAddrMailboxIncomingBase));
1884	Log(("cMailboxes=%u (32-bit mode)\n", pBusLogic->cMailbox));
1885	LogRel(("Initialized 32-bit mailbox, %d entries at %08x\n", pRequest->cMailbox, pRequest->uMailboxBaseAddress));
1886
1887	pBusLogic->regStatus &= ~BUSLOGIC_REGISTER_STATUS_INITIALIZATION_REQUIRED;
1888	pBusLogic->cbReplyParametersLeft = 0;
1889	break;
1890	}
1891	case BUSLOGICCOMMAND_ENABLE_STRICT_ROUND_ROBIN_MODE:
1892	{
1893	if (pBusLogic->aCommandBuffer[0] == 0)
1894	pBusLogic->fStrictRoundRobinMode = false;
1895	else if (pBusLogic->aCommandBuffer[0] == 1)
1896	pBusLogic->fStrictRoundRobinMode = true;
1897	else
1898	AssertMsgFailed(("Invalid round robin mode %d\n", pBusLogic->aCommandBuffer[0]));
1899
1900	pBusLogic->cbReplyParametersLeft = 0;
1901	break;
1902	}
1903	case BUSLOGICCOMMAND_SET_CCB_FORMAT:
1904	{
1905	if (pBusLogic->aCommandBuffer[0] == 0)
1906	pBusLogic->fExtendedLunCCBFormat = false;
1907	else if (pBusLogic->aCommandBuffer[0] == 1)
1908	pBusLogic->fExtendedLunCCBFormat = true;
1909	else
1910	AssertMsgFailed(("Invalid CCB format %d\n", pBusLogic->aCommandBuffer[0]));
1911
1912	pBusLogic->cbReplyParametersLeft = 0;
1913	break;
1914	}
1915	case BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_0_TO_7:
1916	/* This is supposed to send TEST UNIT READY to each target/LUN.
1917	* We cheat and skip that, since we already know what's attached
1918	*/
1919	memset(pBusLogic->aReplyBuffer, 0, 8);
1920	for (int i = 0; i < 8; ++i)
1921	{
1922	if (pBusLogic->aDeviceStates[i].fPresent)
1923	pBusLogic->aReplyBuffer[i] = 1;
1924	}
1925	pBusLogic->aReplyBuffer[7] = 0; /* HA hardcoded at ID 7. */
1926	pBusLogic->cbReplyParametersLeft = 8;
1927	break;
1928	case BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_8_TO_15:
1929	/* See note about cheating above. */
1930	memset(pBusLogic->aReplyBuffer, 0, 8);
1931	for (int i = 0; i < 8; ++i)
1932	{
1933	if (pBusLogic->aDeviceStates[i + 8].fPresent)
1934	pBusLogic->aReplyBuffer[i] = 1;
1935	}
1936	pBusLogic->cbReplyParametersLeft = 8;
1937	break;
1938	case BUSLOGICCOMMAND_INQUIRE_TARGET_DEVICES:
1939	{
1940	/* Each bit which is set in the 16bit wide variable means a present device. */
1941	uint16_t u16TargetsPresentMask = 0;
1942
1943	for (uint8_t i = 0; i < RT_ELEMENTS(pBusLogic->aDeviceStates); i++)
1944	{
1945	if (pBusLogic->aDeviceStates[i].fPresent)
1946	u16TargetsPresentMask \|= (1 << i);
1947	}
1948	pBusLogic->aReplyBuffer[0] = (uint8_t)u16TargetsPresentMask;
1949	pBusLogic->aReplyBuffer[1] = (uint8_t)(u16TargetsPresentMask >> 8);
1950	pBusLogic->cbReplyParametersLeft = 2;
1951	break;
1952	}
1953	case BUSLOGICCOMMAND_INQUIRE_SYNCHRONOUS_PERIOD:
1954	{
1955	pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[0];
1956
1957	for (uint8_t i = 0; i < pBusLogic->cbReplyParametersLeft; i++)
1958	pBusLogic->aReplyBuffer[i] = 0; /** @todo Figure if we need something other here. It's not needed for the linux driver */
1959
1960	break;
1961	}
1962	case BUSLOGICCOMMAND_DISABLE_HOST_ADAPTER_INTERRUPT:
1963	{
1964	if (pBusLogic->aCommandBuffer[0] == 0)
1965	pBusLogic->fIRQEnabled = false;
1966	else
1967	pBusLogic->fIRQEnabled = true;
1968	/* No interrupt signaled regardless of enable/disable. */
1969	fSuppressIrq = true;
1970	break;
1971	}
1972	case BUSLOGICCOMMAND_ECHO_COMMAND_DATA:
1973	{
1974	pBusLogic->aReplyBuffer[0] = pBusLogic->aCommandBuffer[0];
1975	pBusLogic->cbReplyParametersLeft = 1;
1976	break;
1977	}
1978	case BUSLOGICCOMMAND_SET_PREEMPT_TIME_ON_BUS:
1979	{
1980	pBusLogic->cbReplyParametersLeft = 0;
1981	pBusLogic->LocalRam.structured.autoSCSIData.uBusOnDelay = pBusLogic->aCommandBuffer[0];
1982	Log(("Bus-on time: %d\n", pBusLogic->aCommandBuffer[0]));
1983	break;
1984	}
1985	case BUSLOGICCOMMAND_SET_TIME_OFF_BUS:
1986	{
1987	pBusLogic->cbReplyParametersLeft = 0;
1988	pBusLogic->LocalRam.structured.autoSCSIData.uBusOffDelay = pBusLogic->aCommandBuffer[0];
1989	Log(("Bus-off time: %d\n", pBusLogic->aCommandBuffer[0]));
1990	break;
1991	}
1992	case BUSLOGICCOMMAND_SET_BUS_TRANSFER_RATE:
1993	{
1994	pBusLogic->cbReplyParametersLeft = 0;
1995	pBusLogic->LocalRam.structured.autoSCSIData.uDMATransferRate = pBusLogic->aCommandBuffer[0];
1996	Log(("Bus transfer rate: %02X\n", pBusLogic->aCommandBuffer[0]));
1997	break;
1998	}
1999	default:
2000	AssertMsgFailed(("Invalid command %#x\n", pBusLogic->uOperationCode));
2001	case BUSLOGICCOMMAND_EXT_BIOS_INFO:
2002	case BUSLOGICCOMMAND_UNLOCK_MAILBOX:
2003	/* Commands valid for Adaptec 154xC which we don't handle since
2004	* we pretend being 154xB compatible. Just mark the command as invalid.
2005	*/
2006	Log(("Command %#x not valid for this adapter\n", pBusLogic->uOperationCode));
2007	pBusLogic->cbReplyParametersLeft = 0;
2008	pBusLogic->regStatus \|= BUSLOGIC_REGISTER_STATUS_COMMAND_INVALID;
2009	break;
2010	case BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND: /* Should be handled already. */
2011	AssertMsgFailed(("Invalid mailbox execute state!\n"));
2012	}
2013
2014	Log(("uOperationCode=%#x, cbReplyParametersLeft=%d\n", pBusLogic->uOperationCode, pBusLogic->cbReplyParametersLeft));
2015
2016	/* Set the data in ready bit in the status register in case the command has a reply. */
2017	if (pBusLogic->cbReplyParametersLeft)
2018	pBusLogic->regStatus \|= BUSLOGIC_REGISTER_STATUS_DATA_IN_REGISTER_READY;
2019	else if (!pBusLogic->cbCommandParametersLeft)
2020	buslogicCommandComplete(pBusLogic, fSuppressIrq);
2021
2022	return rc;
2023	}
2024
2025	/**
2026	* Read a register from the BusLogic adapter.
2027	*
2028	* @returns VBox status code.
2029	* @param pBusLogic Pointer to the BusLogic instance data.
2030	* @param iRegister The index of the register to read.
2031	* @param pu32 Where to store the register content.
2032	*/
2033	static int buslogicRegisterRead(PBUSLOGIC pBusLogic, unsigned iRegister, uint32_t *pu32)
2034	{
2035	int rc = VINF_SUCCESS;
2036
2037	switch (iRegister)
2038	{
2039	case BUSLOGIC_REGISTER_STATUS:
2040	{
2041	*pu32 = pBusLogic->regStatus;
2042
2043	/* If the diagnostic active bit is set, we are in a guest-initiated
2044	* hard reset. If the guest reads the status register and waits for
2045	* the host adapter ready bit to be set, we terminate the reset right
2046	* away. However, guests may also expect the reset condition to clear
2047	* automatically after a period of time, in which case we can't show
2048	* the DIAG bit at all.
2049	*/
2050	if (pBusLogic->regStatus & BUSLOGIC_REGISTER_STATUS_DIAGNOSTIC_ACTIVE)
2051	{
2052	uint64_t u64AccessTime = PDMDevHlpTMTimeVirtGetNano(pBusLogic->CTX_SUFF(pDevIns));
2053
2054	pBusLogic->regStatus &= ~BUSLOGIC_REGISTER_STATUS_DIAGNOSTIC_ACTIVE;
2055	pBusLogic->regStatus \|= BUSLOGIC_REGISTER_STATUS_HOST_ADAPTER_READY;
2056
2057	if (u64AccessTime - pBusLogic->u64ResetTime > BUSLOGIC_RESET_DURATION_NS)
2058	{
2059	/* If reset already expired, let the guest see that right away. */
2060	*pu32 = pBusLogic->regStatus;
2061	pBusLogic->u64ResetTime = 0;
2062	}
2063	}
2064	break;
2065	}
2066	case BUSLOGIC_REGISTER_DATAIN:
2067	{
2068	if (pBusLogic->fUseLocalRam)
2069	*pu32 = pBusLogic->LocalRam.u8View[pBusLogic->iReply];
2070	else
2071	*pu32 = pBusLogic->aReplyBuffer[pBusLogic->iReply];
2072
2073	/* Careful about underflow - guest can read data register even if
2074	* no data is available.
2075	*/
2076	if (pBusLogic->cbReplyParametersLeft)
2077	{
2078	pBusLogic->iReply++;
2079	pBusLogic->cbReplyParametersLeft--;
2080	if (!pBusLogic->cbReplyParametersLeft)
2081	{
2082	/*
2083	* Reply finished, set command complete bit, unset data-in ready bit and
2084	* interrupt the guest if enabled.
2085	*/
2086	buslogicCommandComplete(pBusLogic, false);
2087	}
2088	}
2089	LogFlowFunc(("data=%02x, iReply=%d, cbReplyParametersLeft=%u\n", *pu32,
2090	pBusLogic->iReply, pBusLogic->cbReplyParametersLeft));
2091	break;
2092	}
2093	case BUSLOGIC_REGISTER_INTERRUPT:
2094	{
2095	*pu32 = pBusLogic->regInterrupt;
2096	break;
2097	}
2098	case BUSLOGIC_REGISTER_GEOMETRY:
2099	{
2100	*pu32 = pBusLogic->regGeometry;
2101	break;
2102	}
2103	default:
2104	*pu32 = UINT32_C(0xffffffff);
2105	}
2106
2107	Log2(("%s: pu32=%p:{%.*Rhxs} iRegister=%d rc=%Rrc\n",
2108	__FUNCTION__, pu32, 1, pu32, iRegister, rc));
2109
2110	return rc;
2111	}
2112
2113	/**
2114	* Write a value to a register.
2115	*
2116	* @returns VBox status code.
2117	* @param pBusLogic Pointer to the BusLogic instance data.
2118	* @param iRegister The index of the register to read.
2119	* @param uVal The value to write.
2120	*/
2121	static int buslogicRegisterWrite(PBUSLOGIC pBusLogic, unsigned iRegister, uint8_t uVal)
2122	{
2123	int rc = VINF_SUCCESS;
2124
2125	switch (iRegister)
2126	{
2127	case BUSLOGIC_REGISTER_CONTROL:
2128	{
2129	if ((uVal & BUSLOGIC_REGISTER_CONTROL_HARD_RESET) \|\| (uVal & BUSLOGIC_REGISTER_CONTROL_SOFT_RESET))
2130	{
2131	#ifdef IN_RING3
2132	bool fHardReset = !!(uVal & BUSLOGIC_REGISTER_CONTROL_HARD_RESET);
2133
2134	LogRel(("BusLogic: %s reset\n", fHardReset ? "hard" : "soft"));
2135	buslogicR3InitiateReset(pBusLogic, fHardReset);
2136	#else
2137	rc = VINF_IOM_R3_IOPORT_WRITE;
2138	#endif
2139	break;
2140	}
2141
2142	rc = PDMCritSectEnter(&pBusLogic->CritSectIntr, VINF_IOM_R3_IOPORT_WRITE);
2143	if (rc != VINF_SUCCESS)
2144	return rc;
2145
2146	#ifdef LOG_ENABLED
2147	uint32_t cMailboxesReady = ASMAtomicXchgU32(&pBusLogic->cInMailboxesReady, 0);
2148	Log(("%u incoming mailboxes were ready when this interrupt was cleared\n", cMailboxesReady));
2149	#endif
2150
2151	if (uVal & BUSLOGIC_REGISTER_CONTROL_INTERRUPT_RESET)
2152	buslogicClearInterrupt(pBusLogic);
2153
2154	PDMCritSectLeave(&pBusLogic->CritSectIntr);
2155
2156	break;
2157	}
2158	case BUSLOGIC_REGISTER_COMMAND:
2159	{
2160	/* Fast path for mailbox execution command. */
2161	if ((uVal == BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND) && (pBusLogic->uOperationCode == 0xff))
2162	{
2163	ASMAtomicIncU32(&pBusLogic->cMailboxesReady);
2164	if (!ASMAtomicXchgBool(&pBusLogic->fNotificationSend, true))
2165	{
2166	/* Send new notification to the queue. */
2167	PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pBusLogic->CTX_SUFF(pNotifierQueue));
2168	AssertMsg(pItem, ("Allocating item for queue failed\n"));
2169	PDMQueueInsert(pBusLogic->CTX_SUFF(pNotifierQueue), (PPDMQUEUEITEMCORE)pItem);
2170	}
2171
2172	return rc;
2173	}
2174
2175	/*
2176	* Check if we are already fetch command parameters from the guest.
2177	* If not we initialize executing a new command.
2178	*/
2179	if (pBusLogic->uOperationCode == 0xff)
2180	{
2181	pBusLogic->uOperationCode = uVal;
2182	pBusLogic->iParameter = 0;
2183
2184	/* Mark host adapter as busy and clear the invalid status bit. */
2185	pBusLogic->regStatus &= ~(BUSLOGIC_REGISTER_STATUS_HOST_ADAPTER_READY \| BUSLOGIC_REGISTER_STATUS_COMMAND_INVALID);
2186
2187	/* Get the number of bytes for parameters from the command code. */
2188	switch (pBusLogic->uOperationCode)
2189	{
2190	case BUSLOGICCOMMAND_TEST_CMDC_INTERRUPT:
2191	case BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_LETTER:
2192	case BUSLOGICCOMMAND_INQUIRE_BOARD_ID:
2193	case BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_3RD_LETTER:
2194	case BUSLOGICCOMMAND_INQUIRE_PCI_HOST_ADAPTER_INFORMATION:
2195	case BUSLOGICCOMMAND_INQUIRE_CONFIGURATION:
2196	case BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_0_TO_7:
2197	case BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_8_TO_15:
2198	case BUSLOGICCOMMAND_INQUIRE_TARGET_DEVICES:
2199	pBusLogic->cbCommandParametersLeft = 0;
2200	break;
2201	case BUSLOGICCOMMAND_MODIFY_IO_ADDRESS:
2202	case BUSLOGICCOMMAND_INQUIRE_EXTENDED_SETUP_INFORMATION:
2203	case BUSLOGICCOMMAND_INQUIRE_SETUP_INFORMATION:
2204	case BUSLOGICCOMMAND_INQUIRE_HOST_ADAPTER_MODEL_NUMBER:
2205	case BUSLOGICCOMMAND_ENABLE_STRICT_ROUND_ROBIN_MODE:
2206	case BUSLOGICCOMMAND_SET_CCB_FORMAT:
2207	case BUSLOGICCOMMAND_INQUIRE_SYNCHRONOUS_PERIOD:
2208	case BUSLOGICCOMMAND_DISABLE_HOST_ADAPTER_INTERRUPT:
2209	case BUSLOGICCOMMAND_ECHO_COMMAND_DATA:
2210	case BUSLOGICCOMMAND_SET_PREEMPT_TIME_ON_BUS:
2211	case BUSLOGICCOMMAND_SET_TIME_OFF_BUS:
2212	case BUSLOGICCOMMAND_SET_BUS_TRANSFER_RATE:
2213	pBusLogic->cbCommandParametersLeft = 1;
2214	break;
2215	case BUSLOGICCOMMAND_FETCH_HOST_ADAPTER_LOCAL_RAM:
2216	pBusLogic->cbCommandParametersLeft = 2;
2217	break;
2218	case BUSLOGICCOMMAND_INITIALIZE_MAILBOX:
2219	pBusLogic->cbCommandParametersLeft = sizeof(RequestInitMbx);
2220	break;
2221	case BUSLOGICCOMMAND_INITIALIZE_EXTENDED_MAILBOX:
2222	pBusLogic->cbCommandParametersLeft = sizeof(RequestInitializeExtendedMailbox);
2223	break;
2224	case BUSLOGICCOMMAND_SET_ADAPTER_OPTIONS:
2225	/* There must be at least one byte following this command. */
2226	pBusLogic->cbCommandParametersLeft = 1;
2227	break;
2228	case BUSLOGICCOMMAND_EXT_BIOS_INFO:
2229	case BUSLOGICCOMMAND_UNLOCK_MAILBOX:
2230	/* Invalid commands. */
2231	pBusLogic->cbCommandParametersLeft = 0;
2232	break;
2233	case BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND: /* Should not come here anymore. */
2234	default:
2235	AssertMsgFailed(("Invalid operation code %#x\n", uVal));
2236	}
2237	}
2238	else
2239	{
2240	#ifndef IN_RING3
2241	/* This command must be executed in R3 as it rehooks the ISA I/O port. */
2242	if (pBusLogic->uOperationCode == BUSLOGICCOMMAND_MODIFY_IO_ADDRESS)
2243	{
2244	rc = VINF_IOM_R3_IOPORT_WRITE;
2245	break;
2246	}
2247	#endif
2248	/*
2249	* The real adapter would set the Command register busy bit in the status register.
2250	* The guest has to wait until it is unset.
2251	* We don't need to do it because the guest does not continue execution while we are in this
2252	* function.
2253	*/
2254	pBusLogic->aCommandBuffer[pBusLogic->iParameter] = uVal;
2255	pBusLogic->iParameter++;
2256	pBusLogic->cbCommandParametersLeft--;
2257	}
2258
2259	/* Start execution of command if there are no parameters left. */
2260	if (!pBusLogic->cbCommandParametersLeft)
2261	{
2262	rc = buslogicProcessCommand(pBusLogic);
2263	AssertMsgRC(rc, ("Processing command failed rc=%Rrc\n", rc));
2264	}
2265	break;
2266	}
2267
2268	/* On BusLogic adapters, the interrupt and geometry registers are R/W.
2269	* That is different from Adaptec 154x where those are read only.
2270	*/
2271	case BUSLOGIC_REGISTER_INTERRUPT:
2272	pBusLogic->regInterrupt = uVal;
2273	break;
2274
2275	case BUSLOGIC_REGISTER_GEOMETRY:
2276	pBusLogic->regGeometry = uVal;
2277	break;
2278
2279	default:
2280	AssertMsgFailed(("Register not available\n"));
2281	rc = VERR_IOM_IOPORT_UNUSED;
2282	}
2283
2284	return rc;
2285	}
2286
2287	/**
2288	* Memory mapped I/O Handler for read operations.
2289	*
2290	* @returns VBox status code.
2291	*
2292	* @param pDevIns The device instance.
2293	* @param pvUser User argument.
2294	* @param GCPhysAddr Physical address (in GC) where the read starts.
2295	* @param pv Where to store the result.
2296	* @param cb Number of bytes read.
2297	*/
2298	PDMBOTHCBDECL(int) buslogicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2299	{
2300	/* the linux driver does not make use of the MMIO area. */
2301	AssertMsgFailed(("MMIO Read\n"));
2302	return VINF_SUCCESS;
2303	}
2304
2305	/**
2306	* Memory mapped I/O Handler for write operations.
2307	*
2308	* @returns VBox status code.
2309	*
2310	* @param pDevIns The device instance.
2311	* @param pvUser User argument.
2312	* @param GCPhysAddr Physical address (in GC) where the read starts.
2313	* @param pv Where to fetch the result.
2314	* @param cb Number of bytes to write.
2315	*/
2316	PDMBOTHCBDECL(int) buslogicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
2317	{
2318	/* the linux driver does not make use of the MMIO area. */
2319	AssertMsgFailed(("MMIO Write\n"));
2320	return VINF_SUCCESS;
2321	}
2322
2323	/**
2324	* Port I/O Handler for IN operations.
2325	*
2326	* @returns VBox status code.
2327	*
2328	* @param pDevIns The device instance.
2329	* @param pvUser User argument.
2330	* @param uPort Port number used for the IN operation.
2331	* @param pu32 Where to store the result.
2332	* @param cb Number of bytes read.
2333	*/
2334	PDMBOTHCBDECL(int) buslogicIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
2335	{
2336	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2337	unsigned iRegister = Port % 4;
2338
2339	Assert(cb == 1);
2340
2341	return buslogicRegisterRead(pBusLogic, iRegister, pu32);
2342	}
2343
2344	/**
2345	* Port I/O Handler for OUT operations.
2346	*
2347	* @returns VBox status code.
2348	*
2349	* @param pDevIns The device instance.
2350	* @param pvUser User argument.
2351	* @param uPort Port number used for the IN operation.
2352	* @param u32 The value to output.
2353	* @param cb The value size in bytes.
2354	*/
2355	PDMBOTHCBDECL(int) buslogicIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2356	{
2357	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2358	int rc = VINF_SUCCESS;
2359	unsigned iRegister = Port % 4;
2360	uint8_t uVal = (uint8_t)u32;
2361
2362	Assert(cb == 1);
2363
2364	rc = buslogicRegisterWrite(pBusLogic, iRegister, (uint8_t)uVal);
2365
2366	Log2(("#%d %s: pvUser=%#p cb=%d u32=%#x Port=%#x rc=%Rrc\n",
2367	pDevIns->iInstance, __FUNCTION__, pvUser, cb, u32, Port, rc));
2368
2369	return rc;
2370	}
2371
2372	#ifdef IN_RING3
2373
2374	static int buslogicR3PrepareBIOSSCSIRequest(PBUSLOGIC pBusLogic)
2375	{
2376	int rc;
2377	PBUSLOGICTASKSTATE pTaskState;
2378	uint32_t uTargetDevice;
2379
2380	rc = RTMemCacheAllocEx(pBusLogic->hTaskCache, (void **)&pTaskState);
2381	AssertMsgRCReturn(rc, ("Getting task from cache failed rc=%Rrc\n", rc), rc);
2382
2383	pTaskState->fBIOS = true;
2384
2385	rc = vboxscsiSetupRequest(&pBusLogic->VBoxSCSI, &pTaskState->PDMScsiRequest, &uTargetDevice);
2386	AssertMsgRCReturn(rc, ("Setting up SCSI request failed rc=%Rrc\n", rc), rc);
2387
2388	pTaskState->PDMScsiRequest.pvUser = pTaskState;
2389
2390	pTaskState->CTX_SUFF(pTargetDevice) = &pBusLogic->aDeviceStates[uTargetDevice];
2391
2392	if (!pTaskState->CTX_SUFF(pTargetDevice)->fPresent)
2393	{
2394	/* Device is not present. */
2395	AssertMsg(pTaskState->PDMScsiRequest.pbCDB[0] == SCSI_INQUIRY,
2396	("Device is not present but command is not inquiry\n"));
2397
2398	SCSIINQUIRYDATA ScsiInquiryData;
2399
2400	memset(&ScsiInquiryData, 0, sizeof(SCSIINQUIRYDATA));
2401	ScsiInquiryData.u5PeripheralDeviceType = SCSI_INQUIRY_DATA_PERIPHERAL_DEVICE_TYPE_UNKNOWN;
2402	ScsiInquiryData.u3PeripheralQualifier = SCSI_INQUIRY_DATA_PERIPHERAL_QUALIFIER_NOT_CONNECTED_NOT_SUPPORTED;
2403
2404	memcpy(pBusLogic->VBoxSCSI.pbBuf, &ScsiInquiryData, 5);
2405
2406	rc = vboxscsiRequestFinished(&pBusLogic->VBoxSCSI, &pTaskState->PDMScsiRequest, SCSI_STATUS_OK);
2407	AssertMsgRCReturn(rc, ("Finishing BIOS SCSI request failed rc=%Rrc\n", rc), rc);
2408
2409	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
2410	}
2411	else
2412	{
2413	LogFlowFunc(("before increment %u\n", pTaskState->CTX_SUFF(pTargetDevice)->cOutstandingRequests));
2414	ASMAtomicIncU32(&pTaskState->CTX_SUFF(pTargetDevice)->cOutstandingRequests);
2415	LogFlowFunc(("after increment %u\n", pTaskState->CTX_SUFF(pTargetDevice)->cOutstandingRequests));
2416
2417	rc = pTaskState->CTX_SUFF(pTargetDevice)->pDrvSCSIConnector->pfnSCSIRequestSend(pTaskState->CTX_SUFF(pTargetDevice)->pDrvSCSIConnector,
2418	&pTaskState->PDMScsiRequest);
2419	AssertMsgRC(rc, ("Sending request to SCSI layer failed rc=%Rrc\n", rc));
2420	}
2421
2422	return rc;
2423	}
2424
2425
2426	/**
2427	* Port I/O Handler for IN operations - BIOS port.
2428	*
2429	* @returns VBox status code.
2430	*
2431	* @param pDevIns The device instance.
2432	* @param pvUser User argument.
2433	* @param uPort Port number used for the IN operation.
2434	* @param pu32 Where to store the result.
2435	* @param cb Number of bytes read.
2436	*/
2437	static DECLCALLBACK(int) buslogicR3BiosIoPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
2438	{
2439	int rc;
2440	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2441
2442	Assert(cb == 1);
2443
2444	rc = vboxscsiReadRegister(&pBusLogic->VBoxSCSI, (Port - BUSLOGIC_BIOS_IO_PORT), pu32);
2445
2446	//Log2(("%s: pu32=%p:{%.*Rhxs} iRegister=%d rc=%Rrc\n",
2447	// __FUNCTION__, pu32, 1, pu32, (Port - BUSLOGIC_BIOS_IO_PORT), rc));
2448
2449	return rc;
2450	}
2451
2452	/**
2453	* Port I/O Handler for OUT operations - BIOS port.
2454	*
2455	* @returns VBox status code.
2456	*
2457	* @param pDevIns The device instance.
2458	* @param pvUser User argument.
2459	* @param uPort Port number used for the IN operation.
2460	* @param u32 The value to output.
2461	* @param cb The value size in bytes.
2462	*/
2463	static DECLCALLBACK(int) buslogicR3BiosIoPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2464	{
2465	int rc;
2466	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2467
2468	Log2(("#%d %s: pvUser=%#p cb=%d u32=%#x Port=%#x\n",
2469	pDevIns->iInstance, __FUNCTION__, pvUser, cb, u32, Port));
2470
2471	Assert(cb == 1);
2472
2473	rc = vboxscsiWriteRegister(&pBusLogic->VBoxSCSI, (Port - BUSLOGIC_BIOS_IO_PORT), (uint8_t)u32);
2474	if (rc == VERR_MORE_DATA)
2475	{
2476	rc = buslogicR3PrepareBIOSSCSIRequest(pBusLogic);
2477	AssertRC(rc);
2478	}
2479	else if (RT_FAILURE(rc))
2480	AssertMsgFailed(("Writing BIOS register failed %Rrc\n", rc));
2481
2482	return VINF_SUCCESS;
2483	}
2484
2485	/**
2486	* Port I/O Handler for primary port range OUT string operations.
2487	* @see FNIOMIOPORTOUTSTRING for details.
2488	*/
2489	static DECLCALLBACK(int) buslogicR3BiosIoPortWriteStr(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, RTGCPTR pGCPtrSrc,
2490	PRTGCUINTREG pcTransfer, unsigned cb)
2491	{
2492	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2493	int rc;
2494
2495	Log2(("#%d %s: pvUser=%#p cb=%d Port=%#x\n",
2496	pDevIns->iInstance, __FUNCTION__, pvUser, cb, Port));
2497
2498	rc = vboxscsiWriteString(pDevIns, &pBusLogic->VBoxSCSI, (Port - BUSLOGIC_BIOS_IO_PORT),
2499	pGCPtrSrc, pcTransfer, cb);
2500	if (rc == VERR_MORE_DATA)
2501	{
2502	rc = buslogicR3PrepareBIOSSCSIRequest(pBusLogic);
2503	AssertRC(rc);
2504	}
2505	else if (RT_FAILURE(rc))
2506	AssertMsgFailed(("Writing BIOS register failed %Rrc\n", rc));
2507
2508	return rc;
2509	}
2510
2511	/**
2512	* Port I/O Handler for primary port range IN string operations.
2513	* @see FNIOMIOPORTINSTRING for details.
2514	*/
2515	static DECLCALLBACK(int) buslogicR3BiosIoPortReadStr(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, RTGCPTR pGCPtrDst,
2516	PRTGCUINTREG pcTransfer, unsigned cb)
2517	{
2518	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2519
2520	LogFlowFunc(("#%d %s: pvUser=%#p cb=%d Port=%#x\n",
2521	pDevIns->iInstance, __FUNCTION__, pvUser, cb, Port));
2522
2523	return vboxscsiReadString(pDevIns, &pBusLogic->VBoxSCSI, (Port - BUSLOGIC_BIOS_IO_PORT),
2524	pGCPtrDst, pcTransfer, cb);
2525	}
2526
2527	/**
2528	* Update the ISA I/O range.
2529	*
2530	* @returns nothing.
2531	* @param pBusLogic Pointer to the BusLogic device instance.
2532	* @param uBaseCode Encoded ISA I/O base; only low 3 bits are used.
2533	*/
2534	static int buslogicR3RegisterISARange(PBUSLOGIC pBusLogic, uint8_t uBaseCode)
2535	{
2536	uint8_t uCode = uBaseCode & MAX_ISA_BASE;
2537	uint16_t uNewBase = g_aISABases[uCode];
2538	int rc = VINF_SUCCESS;
2539
2540	LogFlowFunc(("ISA I/O code %02X, new base %X\n", uBaseCode, uNewBase));
2541
2542	/* Check if the same port range is already registered. */
2543	if (uNewBase != pBusLogic->IOISABase)
2544	{
2545	/* Unregister the old range, if any. */
2546	if (pBusLogic->IOISABase)
2547	rc = PDMDevHlpIOPortDeregister(pBusLogic->CTX_SUFF(pDevIns), pBusLogic->IOISABase, 4);
2548
2549	if (RT_SUCCESS(rc))
2550	{
2551	pBusLogic->IOISABase = 0; /* First mark as unregistered. */
2552	pBusLogic->uISABaseCode = ISA_BASE_DISABLED;
2553
2554	if (uNewBase)
2555	{
2556	/* Register the new range if requested. */
2557	rc = PDMDevHlpIOPortRegister(pBusLogic->CTX_SUFF(pDevIns), uNewBase, 4, NULL,
2558	buslogicIOPortWrite, buslogicIOPortRead,
2559	NULL, NULL,
2560	"BusLogic ISA");
2561	if (RT_SUCCESS(rc))
2562	{
2563	pBusLogic->IOISABase = uNewBase;
2564	pBusLogic->uISABaseCode = uCode;
2565	}
2566	}
2567	}
2568	if (RT_SUCCESS(rc))
2569	{
2570	if (uNewBase)
2571	{
2572	Log(("ISA I/O base: %x\n", uNewBase));
2573	LogRel(("BusLogic: ISA I/O base: %x\n", uNewBase));
2574	}
2575	else
2576	{
2577	Log(("Disabling ISA I/O ports.\n"));
2578	LogRel(("BusLogic: ISA I/O disabled\n"));
2579	}
2580	}
2581
2582	}
2583	return rc;
2584	}
2585
2586	static void buslogicR3WarningDiskFull(PPDMDEVINS pDevIns)
2587	{
2588	int rc;
2589	LogRel(("BusLogic#%d: Host disk full\n", pDevIns->iInstance));
2590	rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND \| VMSETRTERR_FLAGS_NO_WAIT, "DevBusLogic_DISKFULL",
2591	N_("Host system reported disk full. VM execution is suspended. You can resume after freeing some space"));
2592	AssertRC(rc);
2593	}
2594
2595	static void buslogicR3WarningFileTooBig(PPDMDEVINS pDevIns)
2596	{
2597	int rc;
2598	LogRel(("BusLogic#%d: File too big\n", pDevIns->iInstance));
2599	rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND \| VMSETRTERR_FLAGS_NO_WAIT, "DevBusLogic_FILETOOBIG",
2600	N_("Host system reported that the file size limit of the host file system has been exceeded. VM execution is suspended. You need to move your virtual hard disk to a filesystem which allows bigger files"));
2601	AssertRC(rc);
2602	}
2603
2604	static void buslogicR3WarningISCSI(PPDMDEVINS pDevIns)
2605	{
2606	int rc;
2607	LogRel(("BusLogic#%d: iSCSI target unavailable\n", pDevIns->iInstance));
2608	rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND \| VMSETRTERR_FLAGS_NO_WAIT, "DevBusLogic_ISCSIDOWN",
2609	N_("The iSCSI target has stopped responding. VM execution is suspended. You can resume when it is available again"));
2610	AssertRC(rc);
2611	}
2612
2613	static void buslogicR3WarningUnknown(PPDMDEVINS pDevIns, int rc)
2614	{
2615	int rc2;
2616	LogRel(("BusLogic#%d: Unknown but recoverable error has occurred (rc=%Rrc)\n", pDevIns->iInstance, rc));
2617	rc2 = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND \| VMSETRTERR_FLAGS_NO_WAIT, "DevBusLogic_UNKNOWN",
2618	N_("An unknown but recoverable I/O error has occurred (rc=%Rrc). VM execution is suspended. You can resume when the error is fixed"), rc);
2619	AssertRC(rc2);
2620	}
2621
2622	static void buslogicR3RedoSetWarning(PBUSLOGIC pThis, int rc)
2623	{
2624	if (rc == VERR_DISK_FULL)
2625	buslogicR3WarningDiskFull(pThis->CTX_SUFF(pDevIns));
2626	else if (rc == VERR_FILE_TOO_BIG)
2627	buslogicR3WarningFileTooBig(pThis->CTX_SUFF(pDevIns));
2628	else if (rc == VERR_BROKEN_PIPE \|\| rc == VERR_NET_CONNECTION_REFUSED)
2629	{
2630	/* iSCSI connection abort (first error) or failure to reestablish
2631	* connection (second error). Pause VM. On resume we'll retry. */
2632	buslogicR3WarningISCSI(pThis->CTX_SUFF(pDevIns));
2633	}
2634	else
2635	buslogicR3WarningUnknown(pThis->CTX_SUFF(pDevIns), rc);
2636	}
2637
2638
2639	static DECLCALLBACK(int) buslogicR3MmioMap(PPCIDEVICE pPciDev, /unsigned/ int iRegion,
2640	RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
2641	{
2642	PPDMDEVINS pDevIns = pPciDev->pDevIns;
2643	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2644	int rc = VINF_SUCCESS;
2645
2646	Log2(("%s: registering MMIO area at GCPhysAddr=%RGp cb=%u\n", __FUNCTION__, GCPhysAddress, cb));
2647
2648	Assert(cb >= 32);
2649
2650	if (enmType == PCI_ADDRESS_SPACE_MEM)
2651	{
2652	/* We use the assigned size here, because we currently only support page aligned MMIO ranges. */
2653	rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /pvUser/,
2654	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
2655	buslogicMMIOWrite, buslogicMMIORead, "BusLogic MMIO");
2656	if (RT_FAILURE(rc))
2657	return rc;
2658
2659	if (pThis->fR0Enabled)
2660	{
2661	rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /pvUser/,
2662	"buslogicMMIOWrite", "buslogicMMIORead");
2663	if (RT_FAILURE(rc))
2664	return rc;
2665	}
2666
2667	if (pThis->fGCEnabled)
2668	{
2669	rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /pvUser/,
2670	"buslogicMMIOWrite", "buslogicMMIORead");
2671	if (RT_FAILURE(rc))
2672	return rc;
2673	}
2674
2675	pThis->MMIOBase = GCPhysAddress;
2676	}
2677	else if (enmType == PCI_ADDRESS_SPACE_IO)
2678	{
2679	rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, 32,
2680	NULL, buslogicIOPortWrite, buslogicIOPortRead, NULL, NULL, "BusLogic PCI");
2681	if (RT_FAILURE(rc))
2682	return rc;
2683
2684	if (pThis->fR0Enabled)
2685	{
2686	rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, 32,
2687	0, "buslogicIOPortWrite", "buslogicIOPortRead", NULL, NULL, "BusLogic PCI");
2688	if (RT_FAILURE(rc))
2689	return rc;
2690	}
2691
2692	if (pThis->fGCEnabled)
2693	{
2694	rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, 32,
2695	0, "buslogicIOPortWrite", "buslogicIOPortRead", NULL, NULL, "BusLogic PCI");
2696	if (RT_FAILURE(rc))
2697	return rc;
2698	}
2699
2700	pThis->IOPortBase = (RTIOPORT)GCPhysAddress;
2701	}
2702	else
2703	AssertMsgFailed(("Invalid enmType=%d\n", enmType));
2704
2705	return rc;
2706	}
2707
2708	static DECLCALLBACK(int) buslogicR3DeviceSCSIRequestCompleted(PPDMISCSIPORT pInterface, PPDMSCSIREQUEST pSCSIRequest,
2709	int rcCompletion, bool fRedo, int rcReq)
2710	{
2711	int rc;
2712	PBUSLOGICTASKSTATE pTaskState = (PBUSLOGICTASKSTATE)pSCSIRequest->pvUser;
2713	PBUSLOGICDEVICE pBusLogicDevice = pTaskState->CTX_SUFF(pTargetDevice);
2714	PBUSLOGIC pBusLogic = pBusLogicDevice->CTX_SUFF(pBusLogic);
2715
2716	LogFlowFunc(("before decrement %u\n", pBusLogicDevice->cOutstandingRequests));
2717	ASMAtomicDecU32(&pBusLogicDevice->cOutstandingRequests);
2718	LogFlowFunc(("after decrement %u\n", pBusLogicDevice->cOutstandingRequests));
2719
2720	if (fRedo)
2721	{
2722	if (!pTaskState->fBIOS)
2723	{
2724	buslogicR3DataBufferFree(pTaskState);
2725
2726	if (pTaskState->pbSenseBuffer)
2727	buslogicR3SenseBufferFree(pTaskState, false /* fCopy */);
2728	}
2729
2730	/* Add to the list. */
2731	do
2732	{
2733	pTaskState->pRedoNext = ASMAtomicReadPtrT(&pBusLogic->pTasksRedoHead, PBUSLOGICTASKSTATE);
2734	} while (!ASMAtomicCmpXchgPtr(&pBusLogic->pTasksRedoHead, pTaskState, pTaskState->pRedoNext));
2735
2736	/* Suspend the VM if not done already. */
2737	if (!ASMAtomicXchgBool(&pBusLogic->fRedo, true))
2738	buslogicR3RedoSetWarning(pBusLogic, rcReq);
2739	}
2740	else
2741	{
2742	if (pTaskState->fBIOS)
2743	{
2744	rc = vboxscsiRequestFinished(&pBusLogic->VBoxSCSI, pSCSIRequest, rcCompletion);
2745	AssertMsgRC(rc, ("Finishing BIOS SCSI request failed rc=%Rrc\n", rc));
2746	}
2747	else
2748	{
2749	buslogicR3DataBufferFree(pTaskState);
2750
2751	if (pTaskState->pbSenseBuffer)
2752	buslogicR3SenseBufferFree(pTaskState, (rcCompletion != SCSI_STATUS_OK));
2753
2754	if (rcCompletion == SCSI_STATUS_OK)
2755	buslogicR3SendIncomingMailbox(pBusLogic, pTaskState,
2756	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_CMD_COMPLETED,
2757	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_OPERATION_GOOD,
2758	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITHOUT_ERROR);
2759	else if (rcCompletion == SCSI_STATUS_CHECK_CONDITION)
2760	buslogicR3SendIncomingMailbox(pBusLogic, pTaskState,
2761	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_CMD_COMPLETED,
2762	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_CHECK_CONDITION,
2763	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITH_ERROR);
2764	else
2765	AssertMsgFailed(("invalid completion status %d\n", rcCompletion));
2766	}
2767	#ifdef LOG_ENABLED
2768	buslogicR3DumpCCBInfo(&pTaskState->CommandControlBlockGuest, pTaskState->fIs24Bit);
2769	#endif
2770
2771	/* Remove task from the cache. */
2772	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
2773	}
2774
2775	if (pBusLogicDevice->cOutstandingRequests == 0 && pBusLogic->fSignalIdle)
2776	PDMDevHlpAsyncNotificationCompleted(pBusLogic->pDevInsR3);
2777
2778	return VINF_SUCCESS;
2779	}
2780
2781	static DECLCALLBACK(int) buslogicR3QueryDeviceLocation(PPDMISCSIPORT pInterface, const char **ppcszController,
2782	uint32_t piInstance, uint32_t piLUN)
2783	{
2784	PBUSLOGICDEVICE pBusLogicDevice = PDMISCSIPORT_2_PBUSLOGICDEVICE(pInterface);
2785	PPDMDEVINS pDevIns = pBusLogicDevice->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);
2786
2787	AssertPtrReturn(ppcszController, VERR_INVALID_POINTER);
2788	AssertPtrReturn(piInstance, VERR_INVALID_POINTER);
2789	AssertPtrReturn(piLUN, VERR_INVALID_POINTER);
2790
2791	*ppcszController = pDevIns->pReg->szName;
2792	*piInstance = pDevIns->iInstance;
2793	*piLUN = pBusLogicDevice->iLUN;
2794
2795	return VINF_SUCCESS;
2796	}
2797
2798	static int buslogicR3DeviceSCSIRequestSetup(PBUSLOGIC pBusLogic, PBUSLOGICTASKSTATE pTaskState)
2799	{
2800	int rc = VINF_SUCCESS;
2801	uint8_t uTargetIdCCB;
2802	PBUSLOGICDEVICE pTargetDevice;
2803
2804	/* Fetch the CCB from guest memory. */
2805	/** @todo How much do we really have to read? */
2806	RTGCPHYS GCPhysAddrCCB = (RTGCPHYS)pTaskState->MailboxGuest.u32PhysAddrCCB;
2807	PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrCCB,
2808	&pTaskState->CommandControlBlockGuest, sizeof(CCB32));
2809
2810	uTargetIdCCB = pTaskState->fIs24Bit ? pTaskState->CommandControlBlockGuest.o.uTargetId : pTaskState->CommandControlBlockGuest.n.uTargetId;
2811	pTargetDevice = &pBusLogic->aDeviceStates[uTargetIdCCB];
2812	pTaskState->CTX_SUFF(pTargetDevice) = pTargetDevice;
2813
2814	#ifdef LOG_ENABLED
2815	buslogicR3DumpCCBInfo(&pTaskState->CommandControlBlockGuest, pTaskState->fIs24Bit);
2816	#endif
2817
2818	/* Alloc required buffers. */
2819	rc = buslogicR3DataBufferAlloc(pTaskState);
2820	AssertMsgRC(rc, ("Alloc failed rc=%Rrc\n", rc));
2821
2822	rc = buslogicR3SenseBufferAlloc(pTaskState);
2823	AssertMsgRC(rc, ("Mapping sense buffer failed rc=%Rrc\n", rc));
2824
2825	/* Check if device is present on bus. If not return error immediately and don't process this further. */
2826	if (!pBusLogic->aDeviceStates[uTargetIdCCB].fPresent)
2827	{
2828	buslogicR3DataBufferFree(pTaskState);
2829
2830	if (pTaskState->pbSenseBuffer)
2831	buslogicR3SenseBufferFree(pTaskState, true);
2832
2833	buslogicR3SendIncomingMailbox(pBusLogic, pTaskState,
2834	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_SCSI_SELECTION_TIMEOUT,
2835	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_OPERATION_GOOD,
2836	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITH_ERROR);
2837
2838	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
2839	}
2840	else
2841	{
2842	/* Setup SCSI request. */
2843	pTaskState->PDMScsiRequest.uLogicalUnit = pTaskState->fIs24Bit ? pTaskState->CommandControlBlockGuest.o.uLogicalUnit
2844	: pTaskState->CommandControlBlockGuest.n.uLogicalUnit;
2845
2846	if (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_UNKNOWN)
2847	pTaskState->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_UNKNOWN;
2848	else if (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_IN)
2849	pTaskState->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_FROM_DEVICE;
2850	else if (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_OUT)
2851	pTaskState->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_TO_DEVICE;
2852	else if (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_NO_DATA)
2853	pTaskState->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_NONE;
2854	else
2855	AssertMsgFailed(("Invalid data direction type %d\n", pTaskState->CommandControlBlockGuest.c.uDataDirection));
2856
2857	pTaskState->PDMScsiRequest.cbCDB = pTaskState->CommandControlBlockGuest.c.cbCDB;
2858	pTaskState->PDMScsiRequest.pbCDB = pTaskState->CommandControlBlockGuest.c.abCDB;
2859	if (pTaskState->DataSeg.cbSeg)
2860	{
2861	pTaskState->PDMScsiRequest.cbScatterGather = pTaskState->DataSeg.cbSeg;
2862	pTaskState->PDMScsiRequest.cScatterGatherEntries = 1;
2863	pTaskState->PDMScsiRequest.paScatterGatherHead = &pTaskState->DataSeg;
2864	}
2865	else
2866	{
2867	pTaskState->PDMScsiRequest.cbScatterGather = 0;
2868	pTaskState->PDMScsiRequest.cScatterGatherEntries = 0;
2869	pTaskState->PDMScsiRequest.paScatterGatherHead = NULL;
2870	}
2871	pTaskState->PDMScsiRequest.cbSenseBuffer = buslogicR3ConvertSenseBufferLength(pTaskState->CommandControlBlockGuest.c.cbSenseData);
2872	pTaskState->PDMScsiRequest.pbSenseBuffer = pTaskState->pbSenseBuffer;
2873	pTaskState->PDMScsiRequest.pvUser = pTaskState;
2874
2875	ASMAtomicIncU32(&pTargetDevice->cOutstandingRequests);
2876	rc = pTargetDevice->pDrvSCSIConnector->pfnSCSIRequestSend(pTargetDevice->pDrvSCSIConnector, &pTaskState->PDMScsiRequest);
2877	AssertMsgRC(rc, ("Sending request to SCSI layer failed rc=%Rrc\n", rc));
2878	}
2879
2880	return rc;
2881	}
2882
2883	/**
2884	* Read a mailbox from guest memory. Convert 24-bit mailboxes to
2885	* 32-bit format.
2886	*
2887	* @returns Mailbox guest physical address.
2888	* @param pBusLogic Pointer to the BusLogic instance data.
2889	* @param pTaskStat Pointer to the task state being set up.
2890	*/
2891	static RTGCPHYS buslogicR3ReadOutgoingMailbox(PBUSLOGIC pBusLogic, PBUSLOGICTASKSTATE pTaskState)
2892	{
2893	RTGCPHYS GCMailbox;
2894
2895	if (pBusLogic->fMbxIs24Bit)
2896	{
2897	Mailbox24 Mbx24;
2898
2899	GCMailbox = pBusLogic->GCPhysAddrMailboxOutgoingBase + (pBusLogic->uMailboxOutgoingPositionCurrent * sizeof(Mailbox24));
2900	PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCMailbox, &Mbx24, sizeof(Mailbox24));
2901	pTaskState->MailboxGuest.u32PhysAddrCCB = ADDR_TO_U32(Mbx24.aPhysAddrCCB);
2902	pTaskState->MailboxGuest.u.out.uActionCode = Mbx24.uCmdState;
2903	}
2904	else
2905	{
2906	GCMailbox = pBusLogic->GCPhysAddrMailboxOutgoingBase + (pBusLogic->uMailboxOutgoingPositionCurrent * sizeof(Mailbox32));
2907	PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCMailbox, &pTaskState->MailboxGuest, sizeof(Mailbox32));
2908	}
2909
2910	return GCMailbox;
2911	}
2912
2913	/**
2914	* Read mailbox from the guest and execute command.
2915	*
2916	* @returns VBox status code.
2917	* @param pBusLogic Pointer to the BusLogic instance data.
2918	*/
2919	static int buslogicR3ProcessMailboxNext(PBUSLOGIC pBusLogic)
2920	{
2921	PBUSLOGICTASKSTATE pTaskState = NULL;
2922	RTGCPHYS GCPhysAddrMailboxCurrent;
2923	int rc;
2924
2925	rc = RTMemCacheAllocEx(pBusLogic->hTaskCache, (void **)&pTaskState);
2926	AssertMsgReturn(RT_SUCCESS(rc) && (pTaskState != NULL), ("Failed to get task state from cache\n"), rc);
2927
2928	pTaskState->fBIOS = false;
2929	pTaskState->fIs24Bit = pBusLogic->fMbxIs24Bit;
2930	pTaskState->cbSGEntry = pBusLogic->fMbxIs24Bit ? sizeof(SGE24) : sizeof(SGE32);
2931
2932	if (!pBusLogic->fStrictRoundRobinMode)
2933	{
2934	/* Search for a filled mailbox - stop if we have scanned all mailboxes. */
2935	uint8_t uMailboxPosCur = pBusLogic->uMailboxOutgoingPositionCurrent;
2936
2937	do
2938	{
2939	/* Fetch mailbox from guest memory. */
2940	GCPhysAddrMailboxCurrent = buslogicR3ReadOutgoingMailbox(pBusLogic,pTaskState);
2941
2942	/* Check the next mailbox. */
2943	buslogicR3OutgoingMailboxAdvance(pBusLogic);
2944	} while ( pTaskState->MailboxGuest.u.out.uActionCode == BUSLOGIC_MAILBOX_OUTGOING_ACTION_FREE
2945	&& uMailboxPosCur != pBusLogic->uMailboxOutgoingPositionCurrent);
2946	}
2947	else
2948	{
2949	/* Fetch mailbox from guest memory. */
2950	GCPhysAddrMailboxCurrent = buslogicR3ReadOutgoingMailbox(pBusLogic,pTaskState);
2951	}
2952
2953	/*
2954	* Check if the mailbox is actually loaded.
2955	* It might be possible that the guest notified us without
2956	* a loaded mailbox. Do nothing in that case but leave a
2957	* log entry.
2958	*/
2959	if (pTaskState->MailboxGuest.u.out.uActionCode == BUSLOGIC_MAILBOX_OUTGOING_ACTION_FREE)
2960	{
2961	Log(("No loaded mailbox left\n"));
2962	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
2963	return VERR_NO_DATA;
2964	}
2965
2966	LogFlow(("Got loaded mailbox at slot %u, CCB phys %RGp\n", pBusLogic->uMailboxOutgoingPositionCurrent, (RTGCPHYS)pTaskState->MailboxGuest.u32PhysAddrCCB));
2967	#ifdef LOG_ENABLED
2968	buslogicR3DumpMailboxInfo(&pTaskState->MailboxGuest, true);
2969	#endif
2970
2971	/* We got the mailbox, mark it as free in the guest. */
2972	uint8_t uActionCode = BUSLOGIC_MAILBOX_OUTGOING_ACTION_FREE;
2973	unsigned uCodeOffs = pTaskState->fIs24Bit ? RT_OFFSETOF(Mailbox24, uCmdState) : RT_OFFSETOF(Mailbox32, u.out.uActionCode);
2974	PDMDevHlpPhysWrite(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrMailboxCurrent + uCodeOffs, &uActionCode, sizeof(uActionCode));
2975
2976	if (pTaskState->MailboxGuest.u.out.uActionCode == BUSLOGIC_MAILBOX_OUTGOING_ACTION_START_COMMAND)
2977	rc = buslogicR3DeviceSCSIRequestSetup(pBusLogic, pTaskState);
2978	else if (pTaskState->MailboxGuest.u.out.uActionCode == BUSLOGIC_MAILBOX_OUTGOING_ACTION_ABORT_COMMAND)
2979	{
2980	AssertMsgFailed(("Not implemented yet\n"));
2981	}
2982	else
2983	AssertMsgFailed(("Invalid outgoing mailbox action code %u\n", pTaskState->MailboxGuest.u.out.uActionCode));
2984
2985	AssertRC(rc);
2986
2987	/* Advance to the next mailbox. */
2988	if (pBusLogic->fStrictRoundRobinMode)
2989	buslogicR3OutgoingMailboxAdvance(pBusLogic);
2990
2991	return rc;
2992	}
2993
2994	/**
2995	* Transmit queue consumer
2996	* Queue a new async task.
2997	*
2998	* @returns Success indicator.
2999	* If false the item will not be removed and the flushing will stop.
3000	* @param pDevIns The device instance.
3001	* @param pItem The item to consume. Upon return this item will be freed.
3002	*/
3003	static DECLCALLBACK(bool) buslogicR3NotifyQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
3004	{
3005	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3006
3007	/* Reset notification send flag now. */
3008	Assert(pBusLogic->fNotificationSend);
3009	ASMAtomicXchgBool(&pBusLogic->fNotificationSend, false);
3010	ASMAtomicXchgU32(&pBusLogic->cMailboxesReady, 0); /** @todo Actually not required anymore but to stay compatible with older saved states. */
3011
3012	/* Process mailboxes. */
3013	int rc;
3014	do
3015	{
3016	rc = buslogicR3ProcessMailboxNext(pBusLogic);
3017	AssertMsg(RT_SUCCESS(rc) \|\| rc == VERR_NO_DATA, ("Processing mailbox failed rc=%Rrc\n", rc));
3018	} while (RT_SUCCESS(rc));
3019
3020	return true;
3021	}
3022
3023	/**
3024	* Kicks the controller to process pending tasks after the VM was resumed
3025	* or loaded from a saved state.
3026	*
3027	* @returns nothing.
3028	* @param pThis The BusLogic device instance.
3029	*/
3030	static void buslogicR3Kick(PBUSLOGIC pThis)
3031	{
3032	if (pThis->fRedo)
3033	{
3034	pThis->fRedo = false;
3035	if (pThis->VBoxSCSI.fBusy)
3036	{
3037
3038	/* The BIOS had a request active when we got suspended. Resume it. */
3039	int rc = buslogicR3PrepareBIOSSCSIRequest(pThis);
3040	AssertRC(rc);
3041	}
3042	else
3043	{
3044	/* Queue all pending tasks again. */
3045	PBUSLOGICTASKSTATE pTaskState = pThis->pTasksRedoHead;
3046
3047	pThis->pTasksRedoHead = NULL;
3048
3049	while (pTaskState)
3050	{
3051	PBUSLOGICTASKSTATE pCur = pTaskState;
3052
3053	int rc = buslogicR3DeviceSCSIRequestSetup(pThis, pCur);
3054	AssertRC(rc);
3055
3056	pTaskState = pTaskState->pRedoNext;
3057	}
3058	}
3059	}
3060	}
3061
3062	/** @callback_method_impl{FNSSMDEVLIVEEXEC} */
3063	static DECLCALLBACK(int) buslogicR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
3064	{
3065	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3066
3067	/* Save the device config. */
3068	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDeviceStates); i++)
3069	SSMR3PutBool(pSSM, pThis->aDeviceStates[i].fPresent);
3070
3071	return VINF_SSM_DONT_CALL_AGAIN;
3072	}
3073
3074	/** @callback_method_impl{FNSSMDEVSAVEEXEC} */
3075	static DECLCALLBACK(int) buslogicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3076	{
3077	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3078
3079	/* Every device first. */
3080	for (unsigned i = 0; i < RT_ELEMENTS(pBusLogic->aDeviceStates); i++)
3081	{
3082	PBUSLOGICDEVICE pDevice = &pBusLogic->aDeviceStates[i];
3083
3084	AssertMsg(!pDevice->cOutstandingRequests,
3085	("There are still outstanding requests on this device\n"));
3086	SSMR3PutBool(pSSM, pDevice->fPresent);
3087	SSMR3PutU32(pSSM, pDevice->cOutstandingRequests);
3088	}
3089	/* Now the main device state. */
3090	SSMR3PutU8 (pSSM, pBusLogic->regStatus);
3091	SSMR3PutU8 (pSSM, pBusLogic->regInterrupt);
3092	SSMR3PutU8 (pSSM, pBusLogic->regGeometry);
3093	SSMR3PutMem (pSSM, &pBusLogic->LocalRam, sizeof(pBusLogic->LocalRam));
3094	SSMR3PutU8 (pSSM, pBusLogic->uOperationCode);
3095	SSMR3PutMem (pSSM, &pBusLogic->aCommandBuffer, sizeof(pBusLogic->aCommandBuffer));
3096	SSMR3PutU8 (pSSM, pBusLogic->iParameter);
3097	SSMR3PutU8 (pSSM, pBusLogic->cbCommandParametersLeft);
3098	SSMR3PutBool (pSSM, pBusLogic->fUseLocalRam);
3099	SSMR3PutMem (pSSM, pBusLogic->aReplyBuffer, sizeof(pBusLogic->aReplyBuffer));
3100	SSMR3PutU8 (pSSM, pBusLogic->iReply);
3101	SSMR3PutU8 (pSSM, pBusLogic->cbReplyParametersLeft);
3102	SSMR3PutBool (pSSM, pBusLogic->fIRQEnabled);
3103	SSMR3PutU8 (pSSM, pBusLogic->uISABaseCode);
3104	SSMR3PutU32 (pSSM, pBusLogic->cMailbox);
3105	SSMR3PutBool (pSSM, pBusLogic->fMbxIs24Bit);
3106	SSMR3PutGCPhys(pSSM, pBusLogic->GCPhysAddrMailboxOutgoingBase);
3107	SSMR3PutU32 (pSSM, pBusLogic->uMailboxOutgoingPositionCurrent);
3108	SSMR3PutU32 (pSSM, pBusLogic->cMailboxesReady);
3109	SSMR3PutBool (pSSM, pBusLogic->fNotificationSend);
3110	SSMR3PutGCPhys(pSSM, pBusLogic->GCPhysAddrMailboxIncomingBase);
3111	SSMR3PutU32 (pSSM, pBusLogic->uMailboxIncomingPositionCurrent);
3112	SSMR3PutBool (pSSM, pBusLogic->fStrictRoundRobinMode);
3113	SSMR3PutBool (pSSM, pBusLogic->fExtendedLunCCBFormat);
3114	/* Now the data for the BIOS interface. */
3115	SSMR3PutU8 (pSSM, pBusLogic->VBoxSCSI.regIdentify);
3116	SSMR3PutU8 (pSSM, pBusLogic->VBoxSCSI.uTargetDevice);
3117	SSMR3PutU8 (pSSM, pBusLogic->VBoxSCSI.uTxDir);
3118	SSMR3PutU8 (pSSM, pBusLogic->VBoxSCSI.cbCDB);
3119	SSMR3PutMem (pSSM, pBusLogic->VBoxSCSI.abCDB, sizeof(pBusLogic->VBoxSCSI.abCDB));
3120	SSMR3PutU8 (pSSM, pBusLogic->VBoxSCSI.iCDB);
3121	SSMR3PutU32 (pSSM, pBusLogic->VBoxSCSI.cbBuf);
3122	SSMR3PutU32 (pSSM, pBusLogic->VBoxSCSI.iBuf);
3123	SSMR3PutBool (pSSM, pBusLogic->VBoxSCSI.fBusy);
3124	SSMR3PutU8 (pSSM, pBusLogic->VBoxSCSI.enmState);
3125	if (pBusLogic->VBoxSCSI.cbBuf)
3126	SSMR3PutMem(pSSM, pBusLogic->VBoxSCSI.pbBuf, pBusLogic->VBoxSCSI.cbBuf);
3127
3128	/*
3129	* Save the physical addresses of the command control blocks of still pending tasks.
3130	* They are processed again on resume.
3131	*
3132	* The number of pending tasks needs to be determined first.
3133	*/
3134	uint32_t cTasks = 0;
3135
3136	PBUSLOGICTASKSTATE pTaskState = pBusLogic->pTasksRedoHead;
3137	if (pBusLogic->fRedo)
3138	{
3139	while (pTaskState)
3140	{
3141	cTasks++;
3142	pTaskState = pTaskState->pRedoNext;
3143	}
3144	}
3145	SSMR3PutU32(pSSM, cTasks);
3146
3147	/* Write the address of every task now. */
3148	pTaskState = pBusLogic->pTasksRedoHead;
3149	while (pTaskState)
3150	{
3151	SSMR3PutU32(pSSM, pTaskState->MailboxGuest.u32PhysAddrCCB);
3152	pTaskState = pTaskState->pRedoNext;
3153	}
3154
3155	return SSMR3PutU32(pSSM, ~0);
3156	}
3157
3158	/** @callback_method_impl{FNSSMDEVLOADDONE} */
3159	static DECLCALLBACK(int) buslogicR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3160	{
3161	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3162
3163	buslogicR3RegisterISARange(pThis, pThis->uISABaseCode);
3164	buslogicR3Kick(pThis);
3165	return VINF_SUCCESS;
3166	}
3167
3168	/** @callback_method_impl{FNSSMDEVLOADEXEC} */
3169	static DECLCALLBACK(int) buslogicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3170	{
3171	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3172	int rc = VINF_SUCCESS;
3173
3174	/* We support saved states only from this and older versions. */
3175	if (uVersion > BUSLOGIC_SAVED_STATE_MINOR_VERSION)
3176	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3177
3178	/* Every device first. */
3179	for (unsigned i = 0; i < RT_ELEMENTS(pBusLogic->aDeviceStates); i++)
3180	{
3181	PBUSLOGICDEVICE pDevice = &pBusLogic->aDeviceStates[i];
3182
3183	AssertMsg(!pDevice->cOutstandingRequests,
3184	("There are still outstanding requests on this device\n"));
3185	bool fPresent;
3186	rc = SSMR3GetBool(pSSM, &fPresent);
3187	AssertRCReturn(rc, rc);
3188	if (pDevice->fPresent != fPresent)
3189	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Target %u config mismatch: config=%RTbool state=%RTbool"), i, pDevice->fPresent, fPresent);
3190
3191	if (uPass == SSM_PASS_FINAL)
3192	SSMR3GetU32(pSSM, (uint32_t *)&pDevice->cOutstandingRequests);
3193	}
3194
3195	if (uPass != SSM_PASS_FINAL)
3196	return VINF_SUCCESS;
3197
3198	/* Now the main device state. */
3199	SSMR3GetU8 (pSSM, (uint8_t *)&pBusLogic->regStatus);
3200	SSMR3GetU8 (pSSM, (uint8_t *)&pBusLogic->regInterrupt);
3201	SSMR3GetU8 (pSSM, (uint8_t *)&pBusLogic->regGeometry);
3202	SSMR3GetMem (pSSM, &pBusLogic->LocalRam, sizeof(pBusLogic->LocalRam));
3203	SSMR3GetU8 (pSSM, &pBusLogic->uOperationCode);
3204	SSMR3GetMem (pSSM, &pBusLogic->aCommandBuffer, sizeof(pBusLogic->aCommandBuffer));
3205	SSMR3GetU8 (pSSM, &pBusLogic->iParameter);
3206	SSMR3GetU8 (pSSM, &pBusLogic->cbCommandParametersLeft);
3207	SSMR3GetBool (pSSM, &pBusLogic->fUseLocalRam);
3208	SSMR3GetMem (pSSM, pBusLogic->aReplyBuffer, sizeof(pBusLogic->aReplyBuffer));
3209	SSMR3GetU8 (pSSM, &pBusLogic->iReply);
3210	SSMR3GetU8 (pSSM, &pBusLogic->cbReplyParametersLeft);
3211	SSMR3GetBool (pSSM, &pBusLogic->fIRQEnabled);
3212	SSMR3GetU8 (pSSM, &pBusLogic->uISABaseCode);
3213	SSMR3GetU32 (pSSM, &pBusLogic->cMailbox);
3214	if (uVersion > BUSLOGIC_SAVED_STATE_MINOR_PRE_24BIT_MBOX)
3215	SSMR3GetBool (pSSM, &pBusLogic->fMbxIs24Bit);
3216	SSMR3GetGCPhys(pSSM, &pBusLogic->GCPhysAddrMailboxOutgoingBase);
3217	SSMR3GetU32 (pSSM, &pBusLogic->uMailboxOutgoingPositionCurrent);
3218	SSMR3GetU32 (pSSM, (uint32_t *)&pBusLogic->cMailboxesReady);
3219	SSMR3GetBool (pSSM, (bool *)&pBusLogic->fNotificationSend);
3220	SSMR3GetGCPhys(pSSM, &pBusLogic->GCPhysAddrMailboxIncomingBase);
3221	SSMR3GetU32 (pSSM, &pBusLogic->uMailboxIncomingPositionCurrent);
3222	SSMR3GetBool (pSSM, &pBusLogic->fStrictRoundRobinMode);
3223	SSMR3GetBool (pSSM, &pBusLogic->fExtendedLunCCBFormat);
3224	/* Now the data for the BIOS interface. */
3225	SSMR3GetU8 (pSSM, &pBusLogic->VBoxSCSI.regIdentify);
3226	SSMR3GetU8 (pSSM, &pBusLogic->VBoxSCSI.uTargetDevice);
3227	SSMR3GetU8 (pSSM, &pBusLogic->VBoxSCSI.uTxDir);
3228	SSMR3GetU8 (pSSM, &pBusLogic->VBoxSCSI.cbCDB);
3229	SSMR3GetMem (pSSM, pBusLogic->VBoxSCSI.abCDB, sizeof(pBusLogic->VBoxSCSI.abCDB));
3230	SSMR3GetU8 (pSSM, &pBusLogic->VBoxSCSI.iCDB);
3231	SSMR3GetU32 (pSSM, &pBusLogic->VBoxSCSI.cbBuf);
3232	SSMR3GetU32 (pSSM, &pBusLogic->VBoxSCSI.iBuf);
3233	SSMR3GetBool(pSSM, (bool *)&pBusLogic->VBoxSCSI.fBusy);
3234	SSMR3GetU8 (pSSM, (uint8_t *)&pBusLogic->VBoxSCSI.enmState);
3235	if (pBusLogic->VBoxSCSI.cbBuf)
3236	{
3237	pBusLogic->VBoxSCSI.pbBuf = (uint8_t *)RTMemAllocZ(pBusLogic->VBoxSCSI.cbBuf);
3238	if (!pBusLogic->VBoxSCSI.pbBuf)
3239	{
3240	LogRel(("BusLogic: Out of memory during restore.\n"));
3241	return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY,
3242	N_("BusLogic: Out of memory during restore\n"));
3243	}
3244	SSMR3GetMem(pSSM, pBusLogic->VBoxSCSI.pbBuf, pBusLogic->VBoxSCSI.cbBuf);
3245	}
3246
3247	if (pBusLogic->VBoxSCSI.fBusy)
3248	pBusLogic->fRedo = true;
3249
3250	if (uVersion > BUSLOGIC_SAVED_STATE_MINOR_PRE_ERROR_HANDLING)
3251	{
3252	/* Check if there are pending tasks saved. */
3253	uint32_t cTasks = 0;
3254
3255	SSMR3GetU32(pSSM, &cTasks);
3256
3257	if (cTasks)
3258	pBusLogic->fRedo = true;
3259
3260	for (uint32_t i = 0; i < cTasks; i++)
3261	{
3262	PBUSLOGICTASKSTATE pTaskState = (PBUSLOGICTASKSTATE)RTMemCacheAlloc(pBusLogic->hTaskCache);
3263	if (!pTaskState)
3264	{
3265	rc = VERR_NO_MEMORY;
3266	break;
3267	}
3268
3269	rc = SSMR3GetU32(pSSM, &pTaskState->MailboxGuest.u32PhysAddrCCB);
3270	if (RT_FAILURE(rc))
3271	{
3272	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
3273	break;
3274	}
3275
3276	/* Link into the list. */
3277	pTaskState->pRedoNext = pBusLogic->pTasksRedoHead;
3278	pBusLogic->pTasksRedoHead = pTaskState;
3279	}
3280	}
3281
3282	if (RT_SUCCESS(rc))
3283	{
3284	uint32_t u32;
3285	rc = SSMR3GetU32(pSSM, &u32);
3286	if (RT_SUCCESS(rc))
3287	AssertMsgReturn(u32 == ~0U, ("%#x\n", u32), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
3288	}
3289
3290	return rc;
3291	}
3292
3293	/**
3294	* Gets the pointer to the status LED of a device - called from the SCSI driver.
3295	*
3296	* @returns VBox status code.
3297	* @param pInterface Pointer to the interface structure containing the called function pointer.
3298	* @param iLUN The unit which status LED we desire. Always 0 here as the driver
3299	* doesn't know about other LUN's.
3300	* @param ppLed Where to store the LED pointer.
3301	*/
3302	static DECLCALLBACK(int) buslogicR3DeviceQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
3303	{
3304	PBUSLOGICDEVICE pDevice = PDMILEDPORTS_2_PBUSLOGICDEVICE(pInterface);
3305	if (iLUN == 0)
3306	{
3307	*ppLed = &pDevice->Led;
3308	Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
3309	return VINF_SUCCESS;
3310	}
3311	return VERR_PDM_LUN_NOT_FOUND;
3312	}
3313
3314	/**
3315	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
3316	*/
3317	static DECLCALLBACK(void ) buslogicR3DeviceQueryInterface(PPDMIBASE pInterface, const char pszIID)
3318	{
3319	PBUSLOGICDEVICE pDevice = PDMIBASE_2_PBUSLOGICDEVICE(pInterface);
3320	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevice->IBase);
3321	PDMIBASE_RETURN_INTERFACE(pszIID, PDMISCSIPORT, &pDevice->ISCSIPort);
3322	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pDevice->ILed);
3323	return NULL;
3324	}
3325
3326	/**
3327	* Gets the pointer to the status LED of a unit.
3328	*
3329	* @returns VBox status code.
3330	* @param pInterface Pointer to the interface structure containing the called function pointer.
3331	* @param iLUN The unit which status LED we desire.
3332	* @param ppLed Where to store the LED pointer.
3333	*/
3334	static DECLCALLBACK(int) buslogicR3StatusQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
3335	{
3336	PBUSLOGIC pBusLogic = PDMILEDPORTS_2_PBUSLOGIC(pInterface);
3337	if (iLUN < BUSLOGIC_MAX_DEVICES)
3338	{
3339	*ppLed = &pBusLogic->aDeviceStates[iLUN].Led;
3340	Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
3341	return VINF_SUCCESS;
3342	}
3343	return VERR_PDM_LUN_NOT_FOUND;
3344	}
3345
3346	/**
3347	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
3348	*/
3349	static DECLCALLBACK(void ) buslogicR3StatusQueryInterface(PPDMIBASE pInterface, const char pszIID)
3350	{
3351	PBUSLOGIC pThis = PDMIBASE_2_PBUSLOGIC(pInterface);
3352	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
3353	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
3354	return NULL;
3355	}
3356
3357	/**
3358	* BusLogic debugger info callback.
3359	*
3360	* @param pDevIns The device instance.
3361	* @param pHlp The output helpers.
3362	* @param pszArgs The arguments.
3363	*/
3364	static DECLCALLBACK(void) buslogicR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3365	{
3366	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3367	unsigned i;
3368	bool fVerbose = false;
3369
3370	/* Parse arguments. */
3371	if (pszArgs)
3372	fVerbose = strstr(pszArgs, "verbose") != NULL;
3373
3374	/* Show basic information. */
3375	pHlp->pfnPrintf(pHlp,
3376	"%s#%d: PCI I/O=%RTiop ISA I/O=%RTiop MMIO=%RGp IRQ=%u GC=%RTbool R0=%RTbool\n",
3377	pDevIns->pReg->szName,
3378	pDevIns->iInstance,
3379	pThis->IOPortBase, pThis->IOISABase, pThis->MMIOBase,
3380	PCIDevGetInterruptLine(&pThis->dev),
3381	!!pThis->fGCEnabled, !!pThis->fR0Enabled);
3382
3383	/* Print mailbox state. */
3384	if (pThis->regStatus & BUSLOGIC_REGISTER_STATUS_INITIALIZATION_REQUIRED)
3385	pHlp->pfnPrintf(pHlp, "Mailbox not initialized\n");
3386	else
3387	pHlp->pfnPrintf(pHlp, "%u-bit mailbox with %u entries at %RGp\n",
3388	pThis->fMbxIs24Bit ? 24 : 32, pThis->cMailbox,
3389	pThis->GCPhysAddrMailboxOutgoingBase);
3390
3391	/* Print register contents. */
3392	pHlp->pfnPrintf(pHlp, "Registers: STAT=%02x INTR=%02x GEOM=%02x\n",
3393	pThis->regStatus, pThis->regInterrupt, pThis->regGeometry);
3394
3395	/* Print the current command, if any. */
3396	if (pThis->uOperationCode != 0xff )
3397	pHlp->pfnPrintf(pHlp, "Current command: %02X\n", pThis->uOperationCode);
3398
3399	if (fVerbose && (pThis->regStatus & BUSLOGIC_REGISTER_STATUS_INITIALIZATION_REQUIRED) == 0)
3400	{
3401	RTGCPHYS GCMailbox;
3402
3403	/* Dump the mailbox contents. */
3404	if (pThis->fMbxIs24Bit)
3405	{
3406	Mailbox24 Mbx24;
3407
3408	/* Outgoing mailbox, 24-bit format. */
3409	GCMailbox = pThis->GCPhysAddrMailboxOutgoingBase;
3410	pHlp->pfnPrintf(pHlp, " Outgoing mailbox entries (24-bit) at %06X:\n", GCMailbox);
3411	for (i = 0; i < pThis->cMailbox; ++i)
3412	{
3413	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCMailbox, &Mbx24, sizeof(Mailbox24));
3414	pHlp->pfnPrintf(pHlp, " slot %03d: CCB at %06X action code %02X", i, ADDR_TO_U32(Mbx24.aPhysAddrCCB), Mbx24.uCmdState);
3415	pHlp->pfnPrintf(pHlp, "%s\n", pThis->uMailboxOutgoingPositionCurrent == i ? " *" : "");
3416	GCMailbox += sizeof(Mailbox24);
3417	}
3418
3419	/* Incoming mailbox, 24-bit format. */
3420	GCMailbox = pThis->GCPhysAddrMailboxOutgoingBase + (pThis->cMailbox * sizeof(Mailbox24));
3421	pHlp->pfnPrintf(pHlp, " Incoming mailbox entries (24-bit) at %06X:\n", GCMailbox);
3422	for (i = 0; i < pThis->cMailbox; ++i)
3423	{
3424	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCMailbox, &Mbx24, sizeof(Mailbox24));
3425	pHlp->pfnPrintf(pHlp, " slot %03d: CCB at %06X completion code %02X", i, ADDR_TO_U32(Mbx24.aPhysAddrCCB), Mbx24.uCmdState);
3426	pHlp->pfnPrintf(pHlp, "%s\n", pThis->uMailboxIncomingPositionCurrent == i ? " *" : "");
3427	GCMailbox += sizeof(Mailbox24);
3428	}
3429
3430	}
3431	else
3432	{
3433	Mailbox32 Mbx32;
3434
3435	/* Outgoing mailbox, 32-bit format. */
3436	GCMailbox = pThis->GCPhysAddrMailboxOutgoingBase;
3437	pHlp->pfnPrintf(pHlp, " Outgoing mailbox entries (32-bit) at %08X:\n", (uint32_t)GCMailbox);
3438	for (i = 0; i < pThis->cMailbox; ++i)
3439	{
3440	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCMailbox, &Mbx32, sizeof(Mailbox32));
3441	pHlp->pfnPrintf(pHlp, " slot %03d: CCB at %08X action code %02X", i, Mbx32.u32PhysAddrCCB, Mbx32.u.out.uActionCode);
3442	pHlp->pfnPrintf(pHlp, "%s\n", pThis->uMailboxOutgoingPositionCurrent == i ? " *" : "");
3443	GCMailbox += sizeof(Mailbox32);
3444	}
3445
3446	/* Incoming mailbox, 32-bit format. */
3447	GCMailbox = pThis->GCPhysAddrMailboxOutgoingBase;
3448	pHlp->pfnPrintf(pHlp, " Outgoing mailbox entries (32-bit) at %08X:\n", (uint32_t)GCMailbox);
3449	for (i = 0; i < pThis->cMailbox; ++i)
3450	{
3451	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCMailbox, &Mbx32, sizeof(Mailbox32));
3452	pHlp->pfnPrintf(pHlp, " slot %03d: CCB at %08X completion code %02X BTSTAT %02X SDSTAT %02X", i,
3453	Mbx32.u32PhysAddrCCB, Mbx32.u.in.uCompletionCode, Mbx32.u.in.uHostAdapterStatus, Mbx32.u.in.uTargetDeviceStatus);
3454	pHlp->pfnPrintf(pHlp, "%s\n", pThis->uMailboxOutgoingPositionCurrent == i ? " *" : "");
3455	GCMailbox += sizeof(Mailbox32);
3456	}
3457
3458	}
3459	}
3460	}
3461
3462	/* -=-=-=-=- Helper -=-=-=-=- */
3463
3464	/**
3465	* Checks if all asynchronous I/O is finished.
3466	*
3467	* Used by buslogicR3Reset, buslogicR3Suspend and buslogicR3PowerOff.
3468	*
3469	* @returns true if quiesced, false if busy.
3470	* @param pDevIns The device instance.
3471	*/
3472	static bool buslogicR3AllAsyncIOIsFinished(PPDMDEVINS pDevIns)
3473	{
3474	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3475
3476	for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aDeviceStates); i++)
3477	{
3478	PBUSLOGICDEVICE pThisDevice = &pThis->aDeviceStates[i];
3479	if (pThisDevice->pDrvBase)
3480	{
3481	if (pThisDevice->cOutstandingRequests != 0)
3482	return false;
3483	}
3484	}
3485
3486	return true;
3487	}
3488
3489	/**
3490	* Callback employed by buslogicR3Suspend and buslogicR3PowerOff..
3491	*
3492	* @returns true if we've quiesced, false if we're still working.
3493	* @param pDevIns The device instance.
3494	*/
3495	static DECLCALLBACK(bool) buslogicR3IsAsyncSuspendOrPowerOffDone(PPDMDEVINS pDevIns)
3496	{
3497	if (!buslogicR3AllAsyncIOIsFinished(pDevIns))
3498	return false;
3499
3500	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3501	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
3502	return true;
3503	}
3504
3505	/**
3506	* Common worker for ahciR3Suspend and ahciR3PowerOff.
3507	*/
3508	static void buslogicR3SuspendOrPowerOff(PPDMDEVINS pDevIns, bool fPowerOff)
3509	{
3510	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3511
3512	ASMAtomicWriteBool(&pThis->fSignalIdle, true);
3513	if (!buslogicR3AllAsyncIOIsFinished(pDevIns))
3514	PDMDevHlpSetAsyncNotification(pDevIns, buslogicR3IsAsyncSuspendOrPowerOffDone);
3515	else
3516	{
3517	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
3518
3519	AssertMsg(!pThis->fNotificationSend, ("The PDM Queue should be empty at this point\n"));
3520
3521	if (pThis->fRedo)
3522	{
3523	if (fPowerOff)
3524	{
3525	/* Free tasks which would have been queued again on resume. */
3526	PBUSLOGICTASKSTATE pTaskState = pThis->pTasksRedoHead;
3527
3528	pThis->pTasksRedoHead = NULL;
3529
3530	while (pTaskState)
3531	{
3532	PBUSLOGICTASKSTATE pFree;
3533
3534	pFree = pTaskState;
3535	pTaskState = pTaskState->pRedoNext;
3536
3537	RTMemCacheFree(pThis->hTaskCache, pFree);
3538	}
3539	pThis->fRedo = false;
3540	}
3541	else if (pThis->VBoxSCSI.fBusy)
3542	{
3543	/* Destroy the task because the BIOS interface has all necessary information. */
3544	Assert(pThis->pTasksRedoHead->fBIOS);
3545	Assert(!pThis->pTasksRedoHead->pRedoNext);
3546
3547	RTMemCacheFree(pThis->hTaskCache, pThis->pTasksRedoHead);
3548	pThis->pTasksRedoHead = NULL;
3549	}
3550	}
3551	}
3552	}
3553
3554	/**
3555	* Suspend notification.
3556	*
3557	* @param pDevIns The device instance data.
3558	*/
3559	static DECLCALLBACK(void) buslogicR3Suspend(PPDMDEVINS pDevIns)
3560	{
3561	Log(("buslogicR3Suspend\n"));
3562	buslogicR3SuspendOrPowerOff(pDevIns, false /* fPoweroff */);
3563	}
3564
3565	/**
3566	* Resume notification.
3567	*
3568	* @param pDevIns The device instance data.
3569	*/
3570	static DECLCALLBACK(void) buslogicR3Resume(PPDMDEVINS pDevIns)
3571	{
3572	Log(("buslogicR3Resume\n"));
3573	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3574	buslogicR3Kick(pThis);
3575	}
3576
3577
3578	/**
3579	* Detach notification.
3580	*
3581	* One harddisk at one port has been unplugged.
3582	* The VM is suspended at this point.
3583	*
3584	* @param pDevIns The device instance.
3585	* @param iLUN The logical unit which is being detached.
3586	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3587	*/
3588	static DECLCALLBACK(void) buslogicR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3589	{
3590	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3591	PBUSLOGICDEVICE pDevice = &pThis->aDeviceStates[iLUN];
3592
3593	Log(("%s:\n", __FUNCTION__));
3594
3595	AssertMsg(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
3596	("BusLogic: Device does not support hotplugging\n"));
3597
3598	/*
3599	* Zero some important members.
3600	*/
3601	pDevice->pDrvBase = NULL;
3602	pDevice->fPresent = false;
3603	pDevice->pDrvSCSIConnector = NULL;
3604	}
3605
3606	/**
3607	* Attach command.
3608	*
3609	* This is called when we change block driver.
3610	*
3611	* @returns VBox status code.
3612	* @param pDevIns The device instance.
3613	* @param iLUN The logical unit which is being detached.
3614	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3615	*/
3616	static DECLCALLBACK(int) buslogicR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3617	{
3618	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3619	PBUSLOGICDEVICE pDevice = &pThis->aDeviceStates[iLUN];
3620	int rc;
3621
3622	AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
3623	("BusLogic: Device does not support hotplugging\n"),
3624	VERR_INVALID_PARAMETER);
3625
3626	/* the usual paranoia */
3627	AssertRelease(!pDevice->pDrvBase);
3628	AssertRelease(!pDevice->pDrvSCSIConnector);
3629	Assert(pDevice->iLUN == iLUN);
3630
3631	/*
3632	* Try attach the block device and get the interfaces,
3633	* required as well as optional.
3634	*/
3635	rc = PDMDevHlpDriverAttach(pDevIns, pDevice->iLUN, &pDevice->IBase, &pDevice->pDrvBase, NULL);
3636	if (RT_SUCCESS(rc))
3637	{
3638	/* Get SCSI connector interface. */
3639	pDevice->pDrvSCSIConnector = PDMIBASE_QUERY_INTERFACE(pDevice->pDrvBase, PDMISCSICONNECTOR);
3640	AssertMsgReturn(pDevice->pDrvSCSIConnector, ("Missing SCSI interface below\n"), VERR_PDM_MISSING_INTERFACE);
3641	pDevice->fPresent = true;
3642	}
3643	else
3644	AssertMsgFailed(("Failed to attach LUN#%d. rc=%Rrc\n", pDevice->iLUN, rc));
3645
3646	if (RT_FAILURE(rc))
3647	{
3648	pDevice->pDrvBase = NULL;
3649	pDevice->pDrvSCSIConnector = NULL;
3650	}
3651	return rc;
3652	}
3653
3654	/**
3655	* Callback employed by buslogicR3Reset.
3656	*
3657	* @returns true if we've quiesced, false if we're still working.
3658	* @param pDevIns The device instance.
3659	*/
3660	static DECLCALLBACK(bool) buslogicR3IsAsyncResetDone(PPDMDEVINS pDevIns)
3661	{
3662	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3663
3664	if (!buslogicR3AllAsyncIOIsFinished(pDevIns))
3665	return false;
3666	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
3667
3668	buslogicR3HwReset(pThis, true);
3669	return true;
3670	}
3671
3672	/**
3673	* @copydoc FNPDMDEVRESET
3674	*/
3675	static DECLCALLBACK(void) buslogicR3Reset(PPDMDEVINS pDevIns)
3676	{
3677	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3678
3679	ASMAtomicWriteBool(&pThis->fSignalIdle, true);
3680	if (!buslogicR3AllAsyncIOIsFinished(pDevIns))
3681	PDMDevHlpSetAsyncNotification(pDevIns, buslogicR3IsAsyncResetDone);
3682	else
3683	{
3684	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
3685	buslogicR3HwReset(pThis, true);
3686	}
3687	}
3688
3689	static DECLCALLBACK(void) buslogicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
3690	{
3691	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3692
3693	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3694	pThis->pNotifierQueueRC = PDMQueueRCPtr(pThis->pNotifierQueueR3);
3695
3696	for (uint32_t i = 0; i < BUSLOGIC_MAX_DEVICES; i++)
3697	{
3698	PBUSLOGICDEVICE pDevice = &pThis->aDeviceStates[i];
3699
3700	pDevice->pBusLogicRC = PDMINS_2_DATA_RCPTR(pDevIns);
3701	}
3702
3703	}
3704
3705	/**
3706	* Poweroff notification.
3707	*
3708	* @param pDevIns Pointer to the device instance
3709	*/
3710	static DECLCALLBACK(void) buslogicR3PowerOff(PPDMDEVINS pDevIns)
3711	{
3712	Log(("buslogicR3PowerOff\n"));
3713	buslogicR3SuspendOrPowerOff(pDevIns, true /* fPoweroff */);
3714	}
3715
3716	/**
3717	* Destroy a driver instance.
3718	*
3719	* Most VM resources are freed by the VM. This callback is provided so that any non-VM
3720	* resources can be freed correctly.
3721	*
3722	* @param pDevIns The device instance data.
3723	*/
3724	static DECLCALLBACK(int) buslogicR3Destruct(PPDMDEVINS pDevIns)
3725	{
3726	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3727	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
3728
3729	PDMR3CritSectDelete(&pThis->CritSectIntr);
3730
3731	/*
3732	* Free all tasks which are still hanging around
3733	* (Power off after the VM was suspended).
3734	*/
3735	if (pThis->fRedo)
3736	{
3737	/* Free tasks which would have been queued again on resume. */
3738	PBUSLOGICTASKSTATE pTaskState = pThis->pTasksRedoHead;
3739
3740	pThis->pTasksRedoHead = NULL;
3741
3742	while (pTaskState)
3743	{
3744	PBUSLOGICTASKSTATE pFree;
3745
3746	pFree = pTaskState;
3747	pTaskState = pTaskState->pRedoNext;
3748
3749	RTMemCacheFree(pThis->hTaskCache, pFree);
3750	}
3751	pThis->fRedo = false;
3752	}
3753
3754	int rc = RTMemCacheDestroy(pThis->hTaskCache);
3755	AssertMsgRC(rc, ("Destroying task cache failed rc=%Rrc\n", rc));
3756
3757	return rc;
3758	}
3759
3760	/**
3761	* @interface_method_impl{PDMDEVREG,pfnConstruct}
3762	*/
3763	static DECLCALLBACK(int) buslogicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
3764	{
3765	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3766	int rc = VINF_SUCCESS;
3767	bool fBootable = true;
3768	char achISACompat[16];
3769	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3770
3771	/*
3772	* Init instance data (do early because of constructor).
3773	*/
3774	pThis->hTaskCache = NIL_RTMEMCACHE;
3775	pThis->pDevInsR3 = pDevIns;
3776	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
3777	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3778	pThis->IBase.pfnQueryInterface = buslogicR3StatusQueryInterface;
3779	pThis->ILeds.pfnQueryStatusLed = buslogicR3StatusQueryStatusLed;
3780
3781	PCIDevSetVendorId (&pThis->dev, 0x104b); /* BusLogic */
3782	PCIDevSetDeviceId (&pThis->dev, 0x1040); /* BT-958 */
3783	PCIDevSetCommand (&pThis->dev, 0x0003);
3784	PCIDevSetRevisionId (&pThis->dev, 0x01);
3785	PCIDevSetClassProg (&pThis->dev, 0x00); /* SCSI */
3786	PCIDevSetClassSub (&pThis->dev, 0x00); /* SCSI */
3787	PCIDevSetClassBase (&pThis->dev, 0x01); /* Mass storage */
3788	PCIDevSetBaseAddress (&pThis->dev, 0, true /IO/, false /Pref/, false /64-bit/, 0x00000000);
3789	PCIDevSetBaseAddress (&pThis->dev, 1, false /IO/, false /Pref/, false /64-bit/, 0x00000000);
3790	PCIDevSetSubSystemVendorId(&pThis->dev, 0x104b);
3791	PCIDevSetSubSystemId (&pThis->dev, 0x1040);
3792	PCIDevSetInterruptLine (&pThis->dev, 0x00);
3793	PCIDevSetInterruptPin (&pThis->dev, 0x01);
3794
3795	/*
3796	* Validate and read configuration.
3797	*/
3798	if (!CFGMR3AreValuesValid(pCfg,
3799	"GCEnabled\0"
3800	"R0Enabled\0"
3801	"Bootable\0"
3802	"ISACompat\0"))
3803	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
3804	N_("BusLogic configuration error: unknown option specified"));
3805
3806	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &pThis->fGCEnabled, true);
3807	if (RT_FAILURE(rc))
3808	return PDMDEV_SET_ERROR(pDevIns, rc,
3809	N_("BusLogic configuration error: failed to read GCEnabled as boolean"));
3810	Log(("%s: fGCEnabled=%d\n", __FUNCTION__, pThis->fGCEnabled));
3811
3812	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, true);
3813	if (RT_FAILURE(rc))
3814	return PDMDEV_SET_ERROR(pDevIns, rc,
3815	N_("BusLogic configuration error: failed to read R0Enabled as boolean"));
3816	Log(("%s: fR0Enabled=%d\n", __FUNCTION__, pThis->fR0Enabled));
3817	rc = CFGMR3QueryBoolDef(pCfg, "Bootable", &fBootable, true);
3818	if (RT_FAILURE(rc))
3819	return PDMDEV_SET_ERROR(pDevIns, rc,
3820	N_("BusLogic configuration error: failed to read Bootable as boolean"));
3821	Log(("%s: fBootable=%RTbool\n", __FUNCTION__, fBootable));
3822	rc = CFGMR3QueryStringDef(pCfg, "ISACompat", achISACompat, sizeof(achISACompat), "Alternate");
3823	if (RT_FAILURE(rc))
3824	return PDMDEV_SET_ERROR(pDevIns, rc,
3825	N_("BusLogic configuration error: failed to read ISACompat as string"));
3826	Log(("%s: ISACompat=%s\n", __FUNCTION__, achISACompat));
3827
3828	/* Grok the ISACompat setting. */
3829	if (!strcmp(achISACompat, "Disabled"))
3830	pThis->uDefaultISABaseCode = ISA_BASE_DISABLED;
3831	else if (!strcmp(achISACompat, "Primary"))
3832	pThis->uDefaultISABaseCode = 0; /* I/O base at 330h. */
3833	else if (!strcmp(achISACompat, "Alternate"))
3834	pThis->uDefaultISABaseCode = 1; /* I/O base at 334h. */
3835	else
3836	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
3837	N_("BusLogic configuration error: invalid ISACompat setting"));
3838
3839	/*
3840	* Register the PCI device and its I/O regions.
3841	*/
3842	rc = PDMDevHlpPCIRegister(pDevIns, &pThis->dev);
3843	if (RT_FAILURE(rc))
3844	return rc;
3845
3846	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 32, PCI_ADDRESS_SPACE_IO, buslogicR3MmioMap);
3847	if (RT_FAILURE(rc))
3848	return rc;
3849
3850	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 1, 32, PCI_ADDRESS_SPACE_MEM, buslogicR3MmioMap);
3851	if (RT_FAILURE(rc))
3852	return rc;
3853
3854	if (fBootable)
3855	{
3856	/* Register I/O port space for BIOS access. */
3857	rc = PDMDevHlpIOPortRegister(pDevIns, BUSLOGIC_BIOS_IO_PORT, 4, NULL,
3858	buslogicR3BiosIoPortWrite, buslogicR3BiosIoPortRead,
3859	buslogicR3BiosIoPortWriteStr, buslogicR3BiosIoPortReadStr,
3860	"BusLogic BIOS");
3861	if (RT_FAILURE(rc))
3862	return PDMDEV_SET_ERROR(pDevIns, rc, N_("BusLogic cannot register BIOS I/O handlers"));
3863	}
3864
3865	/* Set up the compatibility I/O range. */
3866	rc = buslogicR3RegisterISARange(pThis, pThis->uDefaultISABaseCode);
3867	if (RT_FAILURE(rc))
3868	return PDMDEV_SET_ERROR(pDevIns, rc, N_("BusLogic cannot register ISA I/O handlers"));
3869
3870	/* Initialize task cache. */
3871	rc = RTMemCacheCreate(&pThis->hTaskCache, sizeof(BUSLOGICTASKSTATE), 0, UINT32_MAX,
3872	NULL, NULL, NULL, 0);
3873	if (RT_FAILURE(rc))
3874	return PDMDEV_SET_ERROR(pDevIns, rc,
3875	N_("BusLogic: Failed to initialize task cache\n"));
3876
3877	/* Initialize task queue. */
3878	rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 5, 0,
3879	buslogicR3NotifyQueueConsumer, true, "BusLogicTask", &pThis->pNotifierQueueR3);
3880	if (RT_FAILURE(rc))
3881	return rc;
3882	pThis->pNotifierQueueR0 = PDMQueueR0Ptr(pThis->pNotifierQueueR3);
3883	pThis->pNotifierQueueRC = PDMQueueRCPtr(pThis->pNotifierQueueR3);
3884
3885	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSectIntr, RT_SRC_POS, "BusLogic-Intr#%u", pDevIns->iInstance);
3886	if (RT_FAILURE(rc))
3887	return PDMDEV_SET_ERROR(pDevIns, rc, N_("BusLogic: cannot create critical section"));
3888
3889	/* Initialize per device state. */
3890	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDeviceStates); i++)
3891	{
3892	char szName[24];
3893	PBUSLOGICDEVICE pDevice = &pThis->aDeviceStates[i];
3894
3895	RTStrPrintf(szName, sizeof(szName), "Device%u", i);
3896
3897	/* Initialize static parts of the device. */
3898	pDevice->iLUN = i;
3899	pDevice->pBusLogicR3 = pThis;
3900	pDevice->pBusLogicR0 = PDMINS_2_DATA_R0PTR(pDevIns);
3901	pDevice->pBusLogicRC = PDMINS_2_DATA_RCPTR(pDevIns);
3902	pDevice->Led.u32Magic = PDMLED_MAGIC;
3903	pDevice->IBase.pfnQueryInterface = buslogicR3DeviceQueryInterface;
3904	pDevice->ISCSIPort.pfnSCSIRequestCompleted = buslogicR3DeviceSCSIRequestCompleted;
3905	pDevice->ISCSIPort.pfnQueryDeviceLocation = buslogicR3QueryDeviceLocation;
3906	pDevice->ILed.pfnQueryStatusLed = buslogicR3DeviceQueryStatusLed;
3907
3908	/* Attach SCSI driver. */
3909	rc = PDMDevHlpDriverAttach(pDevIns, pDevice->iLUN, &pDevice->IBase, &pDevice->pDrvBase, szName);
3910	if (RT_SUCCESS(rc))
3911	{
3912	/* Get SCSI connector interface. */
3913	pDevice->pDrvSCSIConnector = PDMIBASE_QUERY_INTERFACE(pDevice->pDrvBase, PDMISCSICONNECTOR);
3914	AssertMsgReturn(pDevice->pDrvSCSIConnector, ("Missing SCSI interface below\n"), VERR_PDM_MISSING_INTERFACE);
3915
3916	pDevice->fPresent = true;
3917	}
3918	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3919	{
3920	pDevice->pDrvBase = NULL;
3921	pDevice->fPresent = false;
3922	rc = VINF_SUCCESS;
3923	Log(("BusLogic: no driver attached to device %s\n", szName));
3924	}
3925	else
3926	{
3927	AssertLogRelMsgFailed(("BusLogic: Failed to attach %s\n", szName));
3928	return rc;
3929	}
3930	}
3931
3932	/*
3933	* Attach status driver (optional).
3934	*/
3935	PPDMIBASE pBase;
3936	rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThis->IBase, &pBase, "Status Port");
3937	if (RT_SUCCESS(rc))
3938	pThis->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
3939	else if (rc != VERR_PDM_NO_ATTACHED_DRIVER)
3940	{
3941	AssertMsgFailed(("Failed to attach to status driver. rc=%Rrc\n", rc));
3942	return PDMDEV_SET_ERROR(pDevIns, rc, N_("BusLogic cannot attach to status driver"));
3943	}
3944
3945	rc = PDMDevHlpSSMRegisterEx(pDevIns, BUSLOGIC_SAVED_STATE_MINOR_VERSION, sizeof(*pThis), NULL,
3946	NULL, buslogicR3LiveExec, NULL,
3947	NULL, buslogicR3SaveExec, NULL,
3948	NULL, buslogicR3LoadExec, buslogicR3LoadDone);
3949	if (RT_FAILURE(rc))
3950	return PDMDEV_SET_ERROR(pDevIns, rc, N_("BusLogic cannot register save state handlers"));
3951
3952	/*
3953	* Register the debugger info callback.
3954	*/
3955	char szTmp[128];
3956	RTStrPrintf(szTmp, sizeof(szTmp), "%s%d", pDevIns->pReg->szName, pDevIns->iInstance);
3957	PDMDevHlpDBGFInfoRegister(pDevIns, szTmp, "BusLogic HBA info", buslogicR3Info);
3958
3959	rc = buslogicR3HwReset(pThis, true);
3960	AssertMsgRC(rc, ("hardware reset of BusLogic host adapter failed rc=%Rrc\n", rc));
3961
3962	return rc;
3963	}
3964
3965	/**
3966	* The device registration structure.
3967	*/
3968	const PDMDEVREG g_DeviceBusLogic =
3969	{
3970	/* u32Version */
3971	PDM_DEVREG_VERSION,
3972	/* szName */
3973	"buslogic",
3974	/* szRCMod */
3975	"VBoxDDGC.gc",
3976	/* szR0Mod */
3977	"VBoxDDR0.r0",
3978	/* pszDescription */
3979	"BusLogic BT-958 SCSI host adapter.\n",
3980	/* fFlags */
3981	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0 \|
3982	PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION \| PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION \|
3983	PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION,
3984	/* fClass */
3985	PDM_DEVREG_CLASS_STORAGE,
3986	/* cMaxInstances */
3987	~0U,
3988	/* cbInstance */
3989	sizeof(BUSLOGIC),
3990	/* pfnConstruct */
3991	buslogicR3Construct,
3992	/* pfnDestruct */
3993	buslogicR3Destruct,
3994	/* pfnRelocate */
3995	buslogicR3Relocate,
3996	/* pfnIOCtl */
3997	NULL,
3998	/* pfnPowerOn */
3999	NULL,
4000	/* pfnReset */
4001	buslogicR3Reset,
4002	/* pfnSuspend */
4003	buslogicR3Suspend,
4004	/* pfnResume */
4005	buslogicR3Resume,
4006	/* pfnAttach */
4007	buslogicR3Attach,
4008	/* pfnDetach */
4009	buslogicR3Detach,
4010	/* pfnQueryInterface. */
4011	NULL,
4012	/* pfnInitComplete */
4013	NULL,
4014	/* pfnPowerOff */
4015	buslogicR3PowerOff,
4016	/* pfnSoftReset */
4017	NULL,
4018	/* u32VersionEnd */
4019	PDM_DEVREG_VERSION
4020	};
4021
4022	#endif /* IN_RING3 */
4023	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Storage/DevBusLogic.cpp@ 44845

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