DevBusLogic.cpp@ 61541

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1	/* $Id: DevBusLogic.cpp 60890 2016-05-09 12:35:19Z vboxsync $ */
2	/** @file
3	* VBox storage devices - BusLogic SCSI host adapter BT-958.
4	*
5	* Based on the Multi-Master Ultra SCSI Systems Technical Reference Manual.
6	*/
7
8	/*
9	* Copyright (C) 2006-2015 Oracle Corporation
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*/
19
20
21	/*********************************************************************************************************************************
22	* Header Files *
23	*********************************************************************************************************************************/
24	#define LOG_GROUP LOG_GROUP_DEV_BUSLOGIC
25	#include <VBox/vmm/pdmdev.h>
26	#include <VBox/vmm/pdmstorageifs.h>
27	#include <VBox/vmm/pdmcritsect.h>
28	#include <VBox/scsi.h>
29	#include <iprt/asm.h>
30	#include <iprt/assert.h>
31	#include <iprt/string.h>
32	#include <iprt/log.h>
33	#ifdef IN_RING3
34	# include <iprt/alloc.h>
35	# include <iprt/memcache.h>
36	# include <iprt/param.h>
37	# include <iprt/uuid.h>
38	#endif
39
40	#include "VBoxSCSI.h"
41	#include "VBoxDD.h"
42
43
44	/*********************************************************************************************************************************
45	* Defined Constants And Macros *
46	*********************************************************************************************************************************/
47	/** Maximum number of attached devices the adapter can handle. */
48	#define BUSLOGIC_MAX_DEVICES 16
49
50	/** Maximum number of scatter gather elements this device can handle. */
51	#define BUSLOGIC_MAX_SCATTER_GATHER_LIST_SIZE 128
52
53	/** Size of the command buffer. */
54	#define BUSLOGIC_COMMAND_SIZE_MAX 53
55
56	/** Size of the reply buffer. */
57	#define BUSLOGIC_REPLY_SIZE_MAX 64
58
59	/** Custom fixed I/O ports for BIOS controller access.
60	* Note that these should not be in the ISA range (below 400h) to avoid
61	* conflicts with ISA device probing. Addresses in the 300h-340h range should be
62	* especially avoided.
63	*/
64	#define BUSLOGIC_BIOS_IO_PORT 0x430
65
66	/** State saved version. */
67	#define BUSLOGIC_SAVED_STATE_MINOR_VERSION 4
68
69	/** Saved state version before the suspend on error feature was implemented. */
70	#define BUSLOGIC_SAVED_STATE_MINOR_PRE_ERROR_HANDLING 1
71	/** Saved state version before 24-bit mailbox support was implemented. */
72	#define BUSLOGIC_SAVED_STATE_MINOR_PRE_24BIT_MBOX 2
73	/** Saved state version before command buffer size was raised. */
74	#define BUSLOGIC_SAVED_STATE_MINOR_PRE_CMDBUF_RESIZE 3
75
76	/** Command buffer size in old saved states. */
77	#define BUSLOGIC_COMMAND_SIZE_OLD 5
78
79	/** The duration of software-initiated reset (in nano seconds).
80	* Not documented, set to 50 ms. */
81	#define BUSLOGIC_RESET_DURATION_NS UINT64_C(50000000)
82
83
84	/*********************************************************************************************************************************
85	* Structures and Typedefs *
86	*********************************************************************************************************************************/
87	/**
88	* State of a device attached to the buslogic host adapter.
89	*
90	* @implements PDMIBASE
91	* @implements PDMISCSIPORT
92	* @implements PDMILEDPORTS
93	*/
94	typedef struct BUSLOGICDEVICE
95	{
96	/** Pointer to the owning buslogic device instance. - R3 pointer */
97	R3PTRTYPE(struct BUSLOGIC *) pBusLogicR3;
98	/** Pointer to the owning buslogic device instance. - R0 pointer */
99	R0PTRTYPE(struct BUSLOGIC *) pBusLogicR0;
100	/** Pointer to the owning buslogic device instance. - RC pointer */
101	RCPTRTYPE(struct BUSLOGIC *) pBusLogicRC;
102
103	/** Flag whether device is present. */
104	bool fPresent;
105	/** LUN of the device. */
106	RTUINT iLUN;
107
108	#if HC_ARCH_BITS == 64
109	uint32_t Alignment0;
110	#endif
111
112	/** Our base interface. */
113	PDMIBASE IBase;
114	/** SCSI port interface. */
115	PDMISCSIPORT ISCSIPort;
116	/** Led interface. */
117	PDMILEDPORTS ILed;
118	/** Pointer to the attached driver's base interface. */
119	R3PTRTYPE(PPDMIBASE) pDrvBase;
120	/** Pointer to the underlying SCSI connector interface. */
121	R3PTRTYPE(PPDMISCSICONNECTOR) pDrvSCSIConnector;
122	/** The status LED state for this device. */
123	PDMLED Led;
124
125	#if HC_ARCH_BITS == 64
126	uint32_t Alignment1;
127	#endif
128
129	/** Number of outstanding tasks on the port. */
130	volatile uint32_t cOutstandingRequests;
131
132	} BUSLOGICDEVICE, *PBUSLOGICDEVICE;
133
134	/**
135	* Commands the BusLogic adapter supports.
136	*/
137	enum BUSLOGICCOMMAND
138	{
139	BUSLOGICCOMMAND_TEST_CMDC_INTERRUPT = 0x00,
140	BUSLOGICCOMMAND_INITIALIZE_MAILBOX = 0x01,
141	BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND = 0x02,
142	BUSLOGICCOMMAND_EXECUTE_BIOS_COMMAND = 0x03,
143	BUSLOGICCOMMAND_INQUIRE_BOARD_ID = 0x04,
144	BUSLOGICCOMMAND_ENABLE_OUTGOING_MAILBOX_AVAILABLE_INTERRUPT = 0x05,
145	BUSLOGICCOMMAND_SET_SCSI_SELECTION_TIMEOUT = 0x06,
146	BUSLOGICCOMMAND_SET_PREEMPT_TIME_ON_BUS = 0x07,
147	BUSLOGICCOMMAND_SET_TIME_OFF_BUS = 0x08,
148	BUSLOGICCOMMAND_SET_BUS_TRANSFER_RATE = 0x09,
149	BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_0_TO_7 = 0x0a,
150	BUSLOGICCOMMAND_INQUIRE_CONFIGURATION = 0x0b,
151	BUSLOGICCOMMAND_ENABLE_TARGET_MODE = 0x0c,
152	BUSLOGICCOMMAND_INQUIRE_SETUP_INFORMATION = 0x0d,
153	BUSLOGICCOMMAND_WRITE_ADAPTER_LOCAL_RAM = 0x1a,
154	BUSLOGICCOMMAND_READ_ADAPTER_LOCAL_RAM = 0x1b,
155	BUSLOGICCOMMAND_WRITE_BUSMASTER_CHIP_FIFO = 0x1c,
156	BUSLOGICCOMMAND_READ_BUSMASTER_CHIP_FIFO = 0x1d,
157	BUSLOGICCOMMAND_ECHO_COMMAND_DATA = 0x1f,
158	BUSLOGICCOMMAND_HOST_ADAPTER_DIAGNOSTIC = 0x20,
159	BUSLOGICCOMMAND_SET_ADAPTER_OPTIONS = 0x21,
160	BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_8_TO_15 = 0x23,
161	BUSLOGICCOMMAND_INQUIRE_TARGET_DEVICES = 0x24,
162	BUSLOGICCOMMAND_DISABLE_HOST_ADAPTER_INTERRUPT = 0x25,
163	BUSLOGICCOMMAND_EXT_BIOS_INFO = 0x28,
164	BUSLOGICCOMMAND_UNLOCK_MAILBOX = 0x29,
165	BUSLOGICCOMMAND_INITIALIZE_EXTENDED_MAILBOX = 0x81,
166	BUSLOGICCOMMAND_EXECUTE_SCSI_COMMAND = 0x83,
167	BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_3RD_LETTER = 0x84,
168	BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_LETTER = 0x85,
169	BUSLOGICCOMMAND_INQUIRE_PCI_HOST_ADAPTER_INFORMATION = 0x86,
170	BUSLOGICCOMMAND_INQUIRE_HOST_ADAPTER_MODEL_NUMBER = 0x8b,
171	BUSLOGICCOMMAND_INQUIRE_SYNCHRONOUS_PERIOD = 0x8c,
172	BUSLOGICCOMMAND_INQUIRE_EXTENDED_SETUP_INFORMATION = 0x8d,
173	BUSLOGICCOMMAND_ENABLE_STRICT_ROUND_ROBIN_MODE = 0x8f,
174	BUSLOGICCOMMAND_STORE_HOST_ADAPTER_LOCAL_RAM = 0x90,
175	BUSLOGICCOMMAND_FETCH_HOST_ADAPTER_LOCAL_RAM = 0x91,
176	BUSLOGICCOMMAND_STORE_LOCAL_DATA_IN_EEPROM = 0x92,
177	BUSLOGICCOMMAND_UPLOAD_AUTO_SCSI_CODE = 0x94,
178	BUSLOGICCOMMAND_MODIFY_IO_ADDRESS = 0x95,
179	BUSLOGICCOMMAND_SET_CCB_FORMAT = 0x96,
180	BUSLOGICCOMMAND_WRITE_INQUIRY_BUFFER = 0x9a,
181	BUSLOGICCOMMAND_READ_INQUIRY_BUFFER = 0x9b,
182	BUSLOGICCOMMAND_FLASH_ROM_UPLOAD_DOWNLOAD = 0xa7,
183	BUSLOGICCOMMAND_READ_SCAM_DATA = 0xa8,
184	BUSLOGICCOMMAND_WRITE_SCAM_DATA = 0xa9
185	} BUSLOGICCOMMAND;
186
187	#pragma pack(1)
188	/**
189	* Auto SCSI structure which is located
190	* in host adapter RAM and contains several
191	* configuration parameters.
192	*/
193	typedef struct AutoSCSIRam
194	{
195	uint8_t aInternalSignature[2];
196	uint8_t cbInformation;
197	uint8_t aHostAdaptertype[6];
198	uint8_t uReserved1;
199	bool fFloppyEnabled : 1;
200	bool fFloppySecondary : 1;
201	bool fLevelSensitiveInterrupt : 1;
202	unsigned char uReserved2 : 2;
203	unsigned char uSystemRAMAreForBIOS : 3;
204	unsigned char uDMAChannel : 7;
205	bool fDMAAutoConfiguration : 1;
206	unsigned char uIrqChannel : 7;
207	bool fIrqAutoConfiguration : 1;
208	uint8_t uDMATransferRate;
209	uint8_t uSCSIId;
210	bool fLowByteTerminated : 1;
211	bool fParityCheckingEnabled : 1;
212	bool fHighByteTerminated : 1;
213	bool fNoisyCablingEnvironment : 1;
214	bool fFastSynchronousNeogtiation : 1;
215	bool fBusResetEnabled : 1;
216	bool fReserved3 : 1;
217	bool fActiveNegotiationEnabled : 1;
218	uint8_t uBusOnDelay;
219	uint8_t uBusOffDelay;
220	bool fHostAdapterBIOSEnabled : 1;
221	bool fBIOSRedirectionOfInt19 : 1;
222	bool fExtendedTranslation : 1;
223	bool fMapRemovableAsFixed : 1;
224	bool fReserved4 : 1;
225	bool fBIOSSupportsMoreThan2Drives : 1;
226	bool fBIOSInterruptMode : 1;
227	bool fFlopticalSupport : 1;
228	uint16_t u16DeviceEnabledMask;
229	uint16_t u16WidePermittedMask;
230	uint16_t u16FastPermittedMask;
231	uint16_t u16SynchronousPermittedMask;
232	uint16_t u16DisconnectPermittedMask;
233	uint16_t u16SendStartUnitCommandMask;
234	uint16_t u16IgnoreInBIOSScanMask;
235	unsigned char uPCIInterruptPin : 2;
236	unsigned char uHostAdapterIoPortAddress : 2;
237	bool fStrictRoundRobinMode : 1;
238	bool fVesaBusSpeedGreaterThan33MHz : 1;
239	bool fVesaBurstWrite : 1;
240	bool fVesaBurstRead : 1;
241	uint16_t u16UltraPermittedMask;
242	uint32_t uReserved5;
243	uint8_t uReserved6;
244	uint8_t uAutoSCSIMaximumLUN;
245	bool fReserved7 : 1;
246	bool fSCAMDominant : 1;
247	bool fSCAMenabled : 1;
248	bool fSCAMLevel2 : 1;
249	unsigned char uReserved8 : 4;
250	bool fInt13Extension : 1;
251	bool fReserved9 : 1;
252	bool fCDROMBoot : 1;
253	unsigned char uReserved10 : 5;
254	unsigned char uBootTargetId : 4;
255	unsigned char uBootChannel : 4;
256	bool fForceBusDeviceScanningOrder : 1;
257	unsigned char uReserved11 : 7;
258	uint16_t u16NonTaggedToAlternateLunPermittedMask;
259	uint16_t u16RenegotiateSyncAfterCheckConditionMask;
260	uint8_t aReserved12[10];
261	uint8_t aManufacturingDiagnostic[2];
262	uint16_t u16Checksum;
263	} AutoSCSIRam, *PAutoSCSIRam;
264	AssertCompileSize(AutoSCSIRam, 64);
265	#pragma pack()
266
267	/**
268	* The local Ram.
269	*/
270	typedef union HostAdapterLocalRam
271	{
272	/** Byte view. */
273	uint8_t u8View[256];
274	/** Structured view. */
275	struct
276	{
277	/** Offset 0 - 63 is for BIOS. */
278	uint8_t u8Bios[64];
279	/** Auto SCSI structure. */
280	AutoSCSIRam autoSCSIData;
281	} structured;
282	} HostAdapterLocalRam, *PHostAdapterLocalRam;
283	AssertCompileSize(HostAdapterLocalRam, 256);
284
285
286	/** Ugly 24-bit big-endian addressing. */
287	typedef struct
288	{
289	uint8_t hi;
290	uint8_t mid;
291	uint8_t lo;
292	} Addr24, Len24;
293	AssertCompileSize(Addr24, 3);
294
295	#define ADDR_TO_U32(x) (((x).hi << 16) \| ((x).mid << 8) \| (x).lo)
296	#define LEN_TO_U32 ADDR_TO_U32
297	#define U32_TO_ADDR(a, x) do {(a).hi = (x) >> 16; (a).mid = (x) >> 8; (a).lo = (x);} while(0)
298	#define U32_TO_LEN U32_TO_ADDR
299
300	/** @name Compatible ISA base I/O port addresses. Disabled if zero.
301	* @{ */
302	#define NUM_ISA_BASES 8
303	#define MAX_ISA_BASE (NUM_ISA_BASES - 1)
304	#define ISA_BASE_DISABLED 6
305
306	static uint16_t const g_aISABases[NUM_ISA_BASES] =
307	{
308	0x330, 0x334, 0x230, 0x234, 0x130, 0x134, 0, 0
309	};
310	/** @} */
311
312	/** Pointer to a task state structure. */
313	typedef struct BUSLOGICTASKSTATE *PBUSLOGICTASKSTATE;
314
315	/**
316	* Main BusLogic device state.
317	*
318	* @extends PCIDEVICE
319	* @implements PDMILEDPORTS
320	*/
321	typedef struct BUSLOGIC
322	{
323	/** The PCI device structure. */
324	PCIDEVICE dev;
325	/** Pointer to the device instance - HC ptr */
326	PPDMDEVINSR3 pDevInsR3;
327	/** Pointer to the device instance - R0 ptr */
328	PPDMDEVINSR0 pDevInsR0;
329	/** Pointer to the device instance - RC ptr. */
330	PPDMDEVINSRC pDevInsRC;
331
332	/** Whether R0 is enabled. */
333	bool fR0Enabled;
334	/** Whether RC is enabled. */
335	bool fGCEnabled;
336
337	/** Base address of the I/O ports. */
338	RTIOPORT IOPortBase;
339	/** Base address of the memory mapping. */
340	RTGCPHYS MMIOBase;
341	/** Status register - Readonly. */
342	volatile uint8_t regStatus;
343	/** Interrupt register - Readonly. */
344	volatile uint8_t regInterrupt;
345	/** Geometry register - Readonly. */
346	volatile uint8_t regGeometry;
347	/** Pending (delayed) interrupt. */
348	uint8_t uPendingIntr;
349
350	/** Local RAM for the fetch hostadapter local RAM request.
351	* I don't know how big the buffer really is but the maximum
352	* seems to be 256 bytes because the offset and count field in the command request
353	* are only one byte big.
354	*/
355	HostAdapterLocalRam LocalRam;
356
357	/** Command code the guest issued. */
358	uint8_t uOperationCode;
359	/** Buffer for the command parameters the adapter is currently receiving from the guest.
360	* Size of the largest command which is possible.
361	*/
362	uint8_t aCommandBuffer[BUSLOGIC_COMMAND_SIZE_MAX]; /* Size of the biggest request. */
363	/** Current position in the command buffer. */
364	uint8_t iParameter;
365	/** Parameters left until the command is complete. */
366	uint8_t cbCommandParametersLeft;
367
368	/** Whether we are using the RAM or reply buffer. */
369	bool fUseLocalRam;
370	/** Buffer to store reply data from the controller to the guest. */
371	uint8_t aReplyBuffer[BUSLOGIC_REPLY_SIZE_MAX]; /* Size of the biggest reply. */
372	/** Position in the buffer we are reading next. */
373	uint8_t iReply;
374	/** Bytes left until the reply buffer is empty. */
375	uint8_t cbReplyParametersLeft;
376
377	/** Flag whether IRQs are enabled. */
378	bool fIRQEnabled;
379	/** Flag whether the ISA I/O port range is disabled
380	* to prevent the BIOS to access the device. */
381	bool fISAEnabled; /*< @todo unused, to be removed /
382	/** Flag whether 24-bit mailboxes are in use (default is 32-bit). */
383	bool fMbxIs24Bit;
384	/** ISA I/O port base (encoded in FW-compatible format). */
385	uint8_t uISABaseCode;
386
387	/** ISA I/O port base (disabled if zero). */
388	RTIOPORT IOISABase;
389	/** Default ISA I/O port base in FW-compatible format. */
390	uint8_t uDefaultISABaseCode;
391
392	/** Number of mailboxes the guest set up. */
393	uint32_t cMailbox;
394
395	#if HC_ARCH_BITS == 64
396	uint32_t Alignment0;
397	#endif
398
399	/** Time when HBA reset was last initiated. / /< @todo does this need to be saved? /
400	uint64_t u64ResetTime;
401	/** Physical base address of the outgoing mailboxes. */
402	RTGCPHYS GCPhysAddrMailboxOutgoingBase;
403	/** Current outgoing mailbox position. */
404	uint32_t uMailboxOutgoingPositionCurrent;
405	/** Number of mailboxes ready. */
406	volatile uint32_t cMailboxesReady;
407	/** Whether a notification to R3 was sent. */
408	volatile bool fNotificationSent;
409
410	#if HC_ARCH_BITS == 64
411	uint32_t Alignment1;
412	#endif
413
414	/** Physical base address of the incoming mailboxes. */
415	RTGCPHYS GCPhysAddrMailboxIncomingBase;
416	/** Current incoming mailbox position. */
417	uint32_t uMailboxIncomingPositionCurrent;
418
419	/** Whether strict round robin is enabled. */
420	bool fStrictRoundRobinMode;
421	/** Whether the extended LUN CCB format is enabled for 32 possible logical units. */
422	bool fExtendedLunCCBFormat;
423
424	/** Queue to send tasks to R3. - HC ptr */
425	R3PTRTYPE(PPDMQUEUE) pNotifierQueueR3;
426	/** Queue to send tasks to R3. - HC ptr */
427	R0PTRTYPE(PPDMQUEUE) pNotifierQueueR0;
428	/** Queue to send tasks to R3. - RC ptr */
429	RCPTRTYPE(PPDMQUEUE) pNotifierQueueRC;
430
431	uint32_t Alignment2;
432
433	/** Critical section protecting access to the interrupt status register. */
434	PDMCRITSECT CritSectIntr;
435
436	/** Cache for task states. */
437	R3PTRTYPE(RTMEMCACHE) hTaskCache;
438
439	/** Device state for BIOS access. */
440	VBOXSCSI VBoxSCSI;
441
442	/** BusLogic device states. */
443	BUSLOGICDEVICE aDeviceStates[BUSLOGIC_MAX_DEVICES];
444
445	/** The base interface.
446	* @todo use PDMDEVINS::IBase */
447	PDMIBASE IBase;
448	/** Status Port - Leds interface. */
449	PDMILEDPORTS ILeds;
450	/** Partner of ILeds. */
451	R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
452
453	#if HC_ARCH_BITS == 64
454	uint32_t Alignment3;
455	#endif
456
457	/** Indicates that PDMDevHlpAsyncNotificationCompleted should be called when
458	* a port is entering the idle state. */
459	bool volatile fSignalIdle;
460	/** Flag whether we have tasks which need to be processed again. */
461	bool volatile fRedo;
462	/** Flag whether the worker thread is sleeping. */
463	volatile bool fWrkThreadSleeping;
464	/** Flag whether a request from the BIOS is pending which the
465	* worker thread needs to process. */
466	volatile bool fBiosReqPending;
467	/** List of tasks which can be redone. */
468	R3PTRTYPE(volatile PBUSLOGICTASKSTATE) pTasksRedoHead;
469
470	/** The support driver session handle. */
471	R3R0PTRTYPE(PSUPDRVSESSION) pSupDrvSession;
472	/** Worker thread. */
473	R3PTRTYPE(PPDMTHREAD) pThreadWrk;
474	/** The event semaphore the processing thread waits on. */
475	SUPSEMEVENT hEvtProcess;
476
477	#ifdef LOG_ENABLED
478	# if HC_ARCH_BITS == 64
479	uint32_t Alignment4;
480	# endif
481
482	volatile uint32_t cInMailboxesReady;
483	#endif
484
485	} BUSLOGIC, *PBUSLOGIC;
486
487	/** Register offsets in the I/O port space. */
488	#define BUSLOGIC_REGISTER_CONTROL 0 /*< Writeonly /
489	/** Fields for the control register. */
490	# define BL_CTRL_RSBUS RT_BIT(4) /* Reset SCSI Bus. */
491	# define BL_CTRL_RINT RT_BIT(5) /* Reset Interrupt. */
492	# define BL_CTRL_RSOFT RT_BIT(6) /* Soft Reset. */
493	# define BL_CTRL_RHARD RT_BIT(7) /* Hard Reset. */
494
495	#define BUSLOGIC_REGISTER_STATUS 0 /*< Readonly /
496	/** Fields for the status register. */
497	# define BL_STAT_CMDINV RT_BIT(0) /* Command Invalid. */
498	# define BL_STAT_DIRRDY RT_BIT(2) /* Data In Register Ready. */
499	# define BL_STAT_CPRBSY RT_BIT(3) /* Command/Parameter Out Register Busy. */
500	# define BL_STAT_HARDY RT_BIT(4) /* Host Adapter Ready. */
501	# define BL_STAT_INREQ RT_BIT(5) /* Initialization Required. */
502	# define BL_STAT_DFAIL RT_BIT(6) /* Diagnostic Failure. */
503	# define BL_STAT_DACT RT_BIT(7) /* Diagnistic Active. */
504
505	#define BUSLOGIC_REGISTER_COMMAND 1 /*< Writeonly /
506	#define BUSLOGIC_REGISTER_DATAIN 1 /*< Readonly /
507	#define BUSLOGIC_REGISTER_INTERRUPT 2 /*< Readonly /
508	/** Fields for the interrupt register. */
509	# define BL_INTR_IMBL RT_BIT(0) /* Incoming Mailbox Loaded. */
510	# define BL_INTR_OMBR RT_BIT(1) /* Outgoing Mailbox Available. */
511	# define BL_INTR_CMDC RT_BIT(2) /* Command Complete. */
512	# define BL_INTR_RSTS RT_BIT(3) /* SCSI Bus Reset State. */
513	# define BL_INTR_INTV RT_BIT(7) /* Interrupt Valid. */
514
515	#define BUSLOGIC_REGISTER_GEOMETRY 3 /* Readonly */
516	# define BL_GEOM_XLATEN RT_BIT(7) /* Extended geometry translation enabled. */
517
518	/** Structure for the INQUIRE_PCI_HOST_ADAPTER_INFORMATION reply. */
519	typedef struct ReplyInquirePCIHostAdapterInformation
520	{
521	uint8_t IsaIOPort;
522	uint8_t IRQ;
523	unsigned char LowByteTerminated : 1;
524	unsigned char HighByteTerminated : 1;
525	unsigned char uReserved : 2; /* Reserved. */
526	unsigned char JP1 : 1; /* Whatever that means. */
527	unsigned char JP2 : 1; /* Whatever that means. */
528	unsigned char JP3 : 1; /* Whatever that means. */
529	/** Whether the provided info is valid. */
530	unsigned char InformationIsValid: 1;
531	uint8_t uReserved2; /* Reserved. */
532	} ReplyInquirePCIHostAdapterInformation, *PReplyInquirePCIHostAdapterInformation;
533	AssertCompileSize(ReplyInquirePCIHostAdapterInformation, 4);
534
535	/** Structure for the INQUIRE_CONFIGURATION reply. */
536	typedef struct ReplyInquireConfiguration
537	{
538	unsigned char uReserved1 : 5;
539	bool fDmaChannel5 : 1;
540	bool fDmaChannel6 : 1;
541	bool fDmaChannel7 : 1;
542	bool fIrqChannel9 : 1;
543	bool fIrqChannel10 : 1;
544	bool fIrqChannel11 : 1;
545	bool fIrqChannel12 : 1;
546	unsigned char uReserved2 : 1;
547	bool fIrqChannel14 : 1;
548	bool fIrqChannel15 : 1;
549	unsigned char uReserved3 : 1;
550	unsigned char uHostAdapterId : 4;
551	unsigned char uReserved4 : 4;
552	} ReplyInquireConfiguration, *PReplyInquireConfiguration;
553	AssertCompileSize(ReplyInquireConfiguration, 3);
554
555	/** Structure for the INQUIRE_SETUP_INFORMATION reply. */
556	typedef struct ReplyInquireSetupInformationSynchronousValue
557	{
558	unsigned char uOffset : 4;
559	unsigned char uTransferPeriod : 3;
560	bool fSynchronous : 1;
561	}ReplyInquireSetupInformationSynchronousValue, *PReplyInquireSetupInformationSynchronousValue;
562	AssertCompileSize(ReplyInquireSetupInformationSynchronousValue, 1);
563
564	typedef struct ReplyInquireSetupInformation
565	{
566	bool fSynchronousInitiationEnabled : 1;
567	bool fParityCheckingEnabled : 1;
568	unsigned char uReserved1 : 6;
569	uint8_t uBusTransferRate;
570	uint8_t uPreemptTimeOnBus;
571	uint8_t uTimeOffBus;
572	uint8_t cMailbox;
573	Addr24 MailboxAddress;
574	ReplyInquireSetupInformationSynchronousValue SynchronousValuesId0To7[8];
575	uint8_t uDisconnectPermittedId0To7;
576	uint8_t uSignature;
577	uint8_t uCharacterD;
578	uint8_t uHostBusType;
579	uint8_t uWideTransferPermittedId0To7;
580	uint8_t uWideTransfersActiveId0To7;
581	ReplyInquireSetupInformationSynchronousValue SynchronousValuesId8To15[8];
582	uint8_t uDisconnectPermittedId8To15;
583	uint8_t uReserved2;
584	uint8_t uWideTransferPermittedId8To15;
585	uint8_t uWideTransfersActiveId8To15;
586	} ReplyInquireSetupInformation, *PReplyInquireSetupInformation;
587	AssertCompileSize(ReplyInquireSetupInformation, 34);
588
589	/** Structure for the INQUIRE_EXTENDED_SETUP_INFORMATION. */
590	#pragma pack(1)
591	typedef struct ReplyInquireExtendedSetupInformation
592	{
593	uint8_t uBusType;
594	uint8_t uBiosAddress;
595	uint16_t u16ScatterGatherLimit;
596	uint8_t cMailbox;
597	uint32_t uMailboxAddressBase;
598	unsigned char uReserved1 : 2;
599	bool fFastEISA : 1;
600	unsigned char uReserved2 : 3;
601	bool fLevelSensitiveInterrupt : 1;
602	unsigned char uReserved3 : 1;
603	unsigned char aFirmwareRevision[3];
604	bool fHostWideSCSI : 1;
605	bool fHostDifferentialSCSI : 1;
606	bool fHostSupportsSCAM : 1;
607	bool fHostUltraSCSI : 1;
608	bool fHostSmartTermination : 1;
609	unsigned char uReserved4 : 3;
610	} ReplyInquireExtendedSetupInformation, *PReplyInquireExtendedSetupInformation;
611	AssertCompileSize(ReplyInquireExtendedSetupInformation, 14);
612	#pragma pack()
613
614	/** Structure for the INITIALIZE EXTENDED MAILBOX request. */
615	#pragma pack(1)
616	typedef struct RequestInitializeExtendedMailbox
617	{
618	/** Number of mailboxes in guest memory. */
619	uint8_t cMailbox;
620	/** Physical address of the first mailbox. */
621	uint32_t uMailboxBaseAddress;
622	} RequestInitializeExtendedMailbox, *PRequestInitializeExtendedMailbox;
623	AssertCompileSize(RequestInitializeExtendedMailbox, 5);
624	#pragma pack()
625
626	/** Structure for the INITIALIZE MAILBOX request. */
627	typedef struct
628	{
629	/** Number of mailboxes to set up. */
630	uint8_t cMailbox;
631	/** Physical address of the first mailbox. */
632	Addr24 aMailboxBaseAddr;
633	} RequestInitMbx, *PRequestInitMbx;
634	AssertCompileSize(RequestInitMbx, 4);
635
636	/**
637	* Structure of a mailbox in guest memory.
638	* The incoming and outgoing mailbox have the same size
639	* but the incoming one has some more fields defined which
640	* are marked as reserved in the outgoing one.
641	* The last field is also different from the type.
642	* For outgoing mailboxes it is the action and
643	* for incoming ones the completion status code for the task.
644	* We use one structure for both types.
645	*/
646	typedef struct Mailbox32
647	{
648	/** Physical address of the CCB structure in the guest memory. */
649	uint32_t u32PhysAddrCCB;
650	/** Type specific data. */
651	union
652	{
653	/** For outgoing mailboxes. */
654	struct
655	{
656	/** Reserved */
657	uint8_t uReserved[3];
658	/** Action code. */
659	uint8_t uActionCode;
660	} out;
661	/** For incoming mailboxes. */
662	struct
663	{
664	/** The host adapter status after finishing the request. */
665	uint8_t uHostAdapterStatus;
666	/** The status of the device which executed the request after executing it. */
667	uint8_t uTargetDeviceStatus;
668	/** Reserved. */
669	uint8_t uReserved;
670	/** The completion status code of the request. */
671	uint8_t uCompletionCode;
672	} in;
673	} u;
674	} Mailbox32, *PMailbox32;
675	AssertCompileSize(Mailbox32, 8);
676
677	/** Old style 24-bit mailbox entry. */
678	typedef struct Mailbox24
679	{
680	/** Mailbox command (incoming) or state (outgoing). */
681	uint8_t uCmdState;
682	/** Physical address of the CCB structure in the guest memory. */
683	Addr24 aPhysAddrCCB;
684	} Mailbox24, *PMailbox24;
685	AssertCompileSize(Mailbox24, 4);
686
687	/**
688	* Action codes for outgoing mailboxes.
689	*/
690	enum BUSLOGIC_MAILBOX_OUTGOING_ACTION
691	{
692	BUSLOGIC_MAILBOX_OUTGOING_ACTION_FREE = 0x00,
693	BUSLOGIC_MAILBOX_OUTGOING_ACTION_START_COMMAND = 0x01,
694	BUSLOGIC_MAILBOX_OUTGOING_ACTION_ABORT_COMMAND = 0x02
695	};
696
697	/**
698	* Completion codes for incoming mailboxes.
699	*/
700	enum BUSLOGIC_MAILBOX_INCOMING_COMPLETION
701	{
702	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_FREE = 0x00,
703	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITHOUT_ERROR = 0x01,
704	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_ABORTED = 0x02,
705	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_ABORTED_NOT_FOUND = 0x03,
706	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITH_ERROR = 0x04,
707	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_INVALID_CCB = 0x05
708	};
709
710	/**
711	* Host adapter status for incoming mailboxes.
712	*/
713	enum BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS
714	{
715	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_CMD_COMPLETED = 0x00,
716	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_LINKED_CMD_COMPLETED = 0x0a,
717	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_LINKED_CMD_COMPLETED_WITH_FLAG = 0x0b,
718	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_DATA_UNDERUN = 0x0c,
719	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_SCSI_SELECTION_TIMEOUT = 0x11,
720	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_DATA_OVERRUN = 0x12,
721	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_UNEXPECTED_BUS_FREE = 0x13,
722	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_INVALID_BUS_PHASE_REQUESTED = 0x14,
723	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_INVALID_OUTGOING_MAILBOX_ACTION_CODE = 0x15,
724	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_INVALID_COMMAND_OPERATION_CODE = 0x16,
725	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_LINKED_CCB_HAS_INVALID_LUN = 0x17,
726	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_INVALID_COMMAND_PARAMETER = 0x1a,
727	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_AUTO_REQUEST_SENSE_FAILED = 0x1b,
728	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_TAGGED_QUEUING_MESSAGE_REJECTED = 0x1c,
729	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_UNSUPPORTED_MESSAGE_RECEIVED = 0x1d,
730	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_HARDWARE_FAILED = 0x20,
731	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_TARGET_FAILED_RESPONSE_TO_ATN = 0x21,
732	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_ASSERTED_RST = 0x22,
733	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_OTHER_DEVICE_ASSERTED_RST = 0x23,
734	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_TARGET_DEVICE_RECONNECTED_IMPROPERLY = 0x24,
735	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_ASSERTED_BUS_DEVICE_RESET = 0x25,
736	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_ABORT_QUEUE_GENERATED = 0x26,
737	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_SOFTWARE_ERROR = 0x27,
738	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_HARDWARE_TIMEOUT_ERROR = 0x30,
739	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_SCSI_PARITY_ERROR_DETECTED = 0x34
740	};
741
742	/**
743	* Device status codes for incoming mailboxes.
744	*/
745	enum BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS
746	{
747	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_OPERATION_GOOD = 0x00,
748	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_CHECK_CONDITION = 0x02,
749	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_DEVICE_BUSY = 0x08
750	};
751
752	/**
753	* Opcode types for CCB.
754	*/
755	enum BUSLOGIC_CCB_OPCODE
756	{
757	BUSLOGIC_CCB_OPCODE_INITIATOR_CCB = 0x00,
758	BUSLOGIC_CCB_OPCODE_TARGET_CCB = 0x01,
759	BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_SCATTER_GATHER = 0x02,
760	BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_DATA_LENGTH = 0x03,
761	BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_SCATTER_GATHER = 0x04,
762	BUSLOGIC_CCB_OPCODE_BUS_DEVICE_RESET = 0x81
763	};
764
765	/**
766	* Data transfer direction.
767	*/
768	enum BUSLOGIC_CCB_DIRECTION
769	{
770	BUSLOGIC_CCB_DIRECTION_UNKNOWN = 0x00,
771	BUSLOGIC_CCB_DIRECTION_IN = 0x01,
772	BUSLOGIC_CCB_DIRECTION_OUT = 0x02,
773	BUSLOGIC_CCB_DIRECTION_NO_DATA = 0x03
774	};
775
776	/**
777	* The command control block for a SCSI request.
778	*/
779	typedef struct CCB32
780	{
781	/** Opcode. */
782	uint8_t uOpcode;
783	/** Reserved */
784	unsigned char uReserved1 : 3;
785	/** Data direction for the request. */
786	unsigned char uDataDirection : 2;
787	/** Whether the request is tag queued. */
788	bool fTagQueued : 1;
789	/** Queue tag mode. */
790	unsigned char uQueueTag : 2;
791	/** Length of the SCSI CDB. */
792	uint8_t cbCDB;
793	/** Sense data length. */
794	uint8_t cbSenseData;
795	/** Data length. */
796	uint32_t cbData;
797	/** Data pointer.
798	* This points to the data region or a scatter gather list based on the opcode.
799	*/
800	uint32_t u32PhysAddrData;
801	/** Reserved. */
802	uint8_t uReserved2[2];
803	/** Host adapter status. */
804	uint8_t uHostAdapterStatus;
805	/** Device adapter status. */
806	uint8_t uDeviceStatus;
807	/** The device the request is sent to. */
808	uint8_t uTargetId;
809	/*The LUN in the device. /
810	unsigned char uLogicalUnit : 5;
811	/** Legacy tag. */
812	bool fLegacyTagEnable : 1;
813	/** Legacy queue tag. */
814	unsigned char uLegacyQueueTag : 2;
815	/** The SCSI CDB. (A CDB can be 12 bytes long.) */
816	uint8_t abCDB[12];
817	/** Reserved. */
818	uint8_t uReserved3[6];
819	/** Sense data pointer. */
820	uint32_t u32PhysAddrSenseData;
821	} CCB32, *PCCB32;
822	AssertCompileSize(CCB32, 40);
823
824
825	/**
826	* The 24-bit command control block.
827	*/
828	typedef struct CCB24
829	{
830	/** Opcode. */
831	uint8_t uOpcode;
832	/** The LUN in the device. */
833	unsigned char uLogicalUnit : 3;
834	/** Data direction for the request. */
835	unsigned char uDataDirection : 2;
836	/** The target device ID. */
837	unsigned char uTargetId : 3;
838	/** Length of the SCSI CDB. */
839	uint8_t cbCDB;
840	/** Sense data length. */
841	uint8_t cbSenseData;
842	/** Data length. */
843	Len24 acbData;
844	/** Data pointer.
845	* This points to the data region or a scatter gather list based on the opc
846	*/
847	Addr24 aPhysAddrData;
848	/** Pointer to next CCB for linked commands. */
849	Addr24 aPhysAddrLink;
850	/** Command linking identifier. */
851	uint8_t uLinkId;
852	/** Host adapter status. */
853	uint8_t uHostAdapterStatus;
854	/** Device adapter status. */
855	uint8_t uDeviceStatus;
856	/** Two unused bytes. */
857	uint8_t aReserved[2];
858	/** The SCSI CDB. (A CDB can be 12 bytes long.) */
859	uint8_t abCDB[12];
860	} CCB24, *PCCB24;
861	AssertCompileSize(CCB24, 30);
862
863	/**
864	* The common 24-bit/32-bit command control block. The 32-bit CCB is laid out
865	* such that many fields are in the same location as in the older 24-bit CCB.
866	*/
867	typedef struct CCBC
868	{
869	/** Opcode. */
870	uint8_t uOpcode;
871	/** The LUN in the device. */
872	unsigned char uPad1 : 3;
873	/** Data direction for the request. */
874	unsigned char uDataDirection : 2;
875	/** The target device ID. */
876	unsigned char uPad2 : 3;
877	/** Length of the SCSI CDB. */
878	uint8_t cbCDB;
879	/** Sense data length. */
880	uint8_t cbSenseData;
881	uint8_t aPad1[10];
882	/** Host adapter status. */
883	uint8_t uHostAdapterStatus;
884	/** Device adapter status. */
885	uint8_t uDeviceStatus;
886	uint8_t aPad2[2];
887	/** The SCSI CDB (up to 12 bytes). */
888	uint8_t abCDB[12];
889	} CCBC, *PCCBC;
890	AssertCompileSize(CCBC, 30);
891
892	/* Make sure that the 24-bit/32-bit/common CCB offsets match. */
893	AssertCompileMemberOffset(CCBC, cbCDB, 2);
894	AssertCompileMemberOffset(CCB24, cbCDB, 2);
895	AssertCompileMemberOffset(CCB32, cbCDB, 2);
896	AssertCompileMemberOffset(CCBC, uHostAdapterStatus, 14);
897	AssertCompileMemberOffset(CCB24, uHostAdapterStatus, 14);
898	AssertCompileMemberOffset(CCB32, uHostAdapterStatus, 14);
899	AssertCompileMemberOffset(CCBC, abCDB, 18);
900	AssertCompileMemberOffset(CCB24, abCDB, 18);
901	AssertCompileMemberOffset(CCB32, abCDB, 18);
902
903	/** A union of all CCB types (24-bit/32-bit/common). */
904	typedef union CCBU
905	{
906	CCB32 n; /*< New 32-bit CCB. /
907	CCB24 o; /*< Old 24-bit CCB. /
908	CCBC c; /*< Common CCB subset. /
909	} CCBU, *PCCBU;
910
911	/** 32-bit scatter-gather list entry. */
912	typedef struct SGE32
913	{
914	uint32_t cbSegment;
915	uint32_t u32PhysAddrSegmentBase;
916	} SGE32, *PSGE32;
917	AssertCompileSize(SGE32, 8);
918
919	/** 24-bit scatter-gather list entry. */
920	typedef struct SGE24
921	{
922	Len24 acbSegment;
923	Addr24 aPhysAddrSegmentBase;
924	} SGE24, *PSGE24;
925	AssertCompileSize(SGE24, 6);
926
927	/**
928	* The structure for the "Execute SCSI Command" command.
929	*/
930	typedef struct ESCMD
931	{
932	/** Data length. */
933	uint32_t cbData;
934	/** Data pointer. */
935	uint32_t u32PhysAddrData;
936	/** The device the request is sent to. */
937	uint8_t uTargetId;
938	/** The LUN in the device. */
939	uint8_t uLogicalUnit;
940	/** Reserved */
941	unsigned char uReserved1 : 3;
942	/** Data direction for the request. */
943	unsigned char uDataDirection : 2;
944	/** Reserved */
945	unsigned char uReserved2 : 3;
946	/** Length of the SCSI CDB. */
947	uint8_t cbCDB;
948	/** The SCSI CDB. (A CDB can be 12 bytes long.) */
949	uint8_t abCDB[12];
950	} ESCMD, *PESCMD;
951	AssertCompileSize(ESCMD, 24);
952
953	/**
954	* Task state for a CCB request.
955	*/
956	typedef struct BUSLOGICTASKSTATE
957	{
958	/** Next in the redo list. */
959	PBUSLOGICTASKSTATE pRedoNext;
960	/** Device this task is assigned to. */
961	R3PTRTYPE(PBUSLOGICDEVICE) pTargetDeviceR3;
962	/** The command control block from the guest. */
963	CCBU CommandControlBlockGuest;
964	/** Mailbox read from guest memory. */
965	Mailbox32 MailboxGuest;
966	/** The SCSI request we pass to the underlying SCSI engine. */
967	PDMSCSIREQUEST PDMScsiRequest;
968	/** Data buffer segment */
969	RTSGSEG DataSeg;
970	/** Pointer to the R3 sense buffer. */
971	uint8_t *pbSenseBuffer;
972	/** Flag whether this is a request from the BIOS. */
973	bool fBIOS;
974	/** 24-bit request flag (default is 32-bit). */
975	bool fIs24Bit;
976	/** S/G entry size (depends on the above flag). */
977	uint8_t cbSGEntry;
978	} BUSLOGICTASKSTATE;
979
980	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
981
982	#define PDMIBASE_2_PBUSLOGICDEVICE(pInterface) ( (PBUSLOGICDEVICE)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGICDEVICE, IBase)) )
983	#define PDMISCSIPORT_2_PBUSLOGICDEVICE(pInterface) ( (PBUSLOGICDEVICE)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGICDEVICE, ISCSIPort)) )
984	#define PDMILEDPORTS_2_PBUSLOGICDEVICE(pInterface) ( (PBUSLOGICDEVICE)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGICDEVICE, ILed)) )
985	#define PDMIBASE_2_PBUSLOGIC(pInterface) ( (PBUSLOGIC)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGIC, IBase)) )
986	#define PDMILEDPORTS_2_PBUSLOGIC(pInterface) ( (PBUSLOGIC)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGIC, ILeds)) )
987
988
989	/*********************************************************************************************************************************
990	* Internal Functions *
991	*********************************************************************************************************************************/
992	static int buslogicR3RegisterISARange(PBUSLOGIC pBusLogic, uint8_t uBaseCode);
993
994
995	/**
996	* Assert IRQ line of the BusLogic adapter.
997	*
998	* @returns nothing.
999	* @param pBusLogic Pointer to the BusLogic device instance.
1000	* @param fSuppressIrq Flag to suppress IRQ generation regardless of fIRQEnabled
1001	* @param uFlag Type of interrupt being generated.
1002	*/
1003	static void buslogicSetInterrupt(PBUSLOGIC pBusLogic, bool fSuppressIrq, uint8_t uIrqType)
1004	{
1005	LogFlowFunc(("pBusLogic=%#p\n", pBusLogic));
1006
1007	/* The CMDC interrupt has priority over IMBL and OMBR. */
1008	if (uIrqType & (BL_INTR_IMBL \| BL_INTR_OMBR))
1009	{
1010	if (!(pBusLogic->regInterrupt & BL_INTR_CMDC))
1011	pBusLogic->regInterrupt \|= uIrqType; /* Report now. */
1012	else
1013	pBusLogic->uPendingIntr \|= uIrqType; /* Report later. */
1014	}
1015	else if (uIrqType & BL_INTR_CMDC)
1016	{
1017	AssertMsg(pBusLogic->regInterrupt == 0 \|\| pBusLogic->regInterrupt == (BL_INTR_INTV \| BL_INTR_CMDC),
1018	("regInterrupt=%02X\n", pBusLogic->regInterrupt));
1019	pBusLogic->regInterrupt \|= uIrqType;
1020	}
1021	else
1022	AssertMsgFailed(("Invalid interrupt state!\n"));
1023
1024	pBusLogic->regInterrupt \|= BL_INTR_INTV;
1025	if (pBusLogic->fIRQEnabled && !fSuppressIrq)
1026	PDMDevHlpPCISetIrq(pBusLogic->CTX_SUFF(pDevIns), 0, 1);
1027	}
1028
1029	/**
1030	* Deasserts the interrupt line of the BusLogic adapter.
1031	*
1032	* @returns nothing
1033	* @param pBuslogic Pointer to the BusLogic device instance.
1034	*/
1035	static void buslogicClearInterrupt(PBUSLOGIC pBusLogic)
1036	{
1037	LogFlowFunc(("pBusLogic=%#p, clearing %#02x (pending %#02x)\n",
1038	pBusLogic, pBusLogic->regInterrupt, pBusLogic->uPendingIntr));
1039	pBusLogic->regInterrupt = 0;
1040	PDMDevHlpPCISetIrq(pBusLogic->CTX_SUFF(pDevIns), 0, 0);
1041	/* If there's another pending interrupt, report it now. */
1042	if (pBusLogic->uPendingIntr)
1043	{
1044	buslogicSetInterrupt(pBusLogic, false, pBusLogic->uPendingIntr);
1045	pBusLogic->uPendingIntr = 0;
1046	}
1047	}
1048
1049	#if defined(IN_RING3)
1050
1051	/**
1052	* Advances the mailbox pointer to the next slot.
1053	*/
1054	DECLINLINE(void) buslogicR3OutgoingMailboxAdvance(PBUSLOGIC pBusLogic)
1055	{
1056	pBusLogic->uMailboxOutgoingPositionCurrent = (pBusLogic->uMailboxOutgoingPositionCurrent + 1) % pBusLogic->cMailbox;
1057	}
1058
1059	/**
1060	* Initialize local RAM of host adapter with default values.
1061	*
1062	* @returns nothing.
1063	* @param pBusLogic.
1064	*/
1065	static void buslogicR3InitializeLocalRam(PBUSLOGIC pBusLogic)
1066	{
1067	/*
1068	* These values are mostly from what I think is right
1069	* looking at the dmesg output from a Linux guest inside
1070	* a VMware server VM.
1071	*
1072	* So they don't have to be right :)
1073	*/
1074	memset(pBusLogic->LocalRam.u8View, 0, sizeof(HostAdapterLocalRam));
1075	pBusLogic->LocalRam.structured.autoSCSIData.fLevelSensitiveInterrupt = true;
1076	pBusLogic->LocalRam.structured.autoSCSIData.fParityCheckingEnabled = true;
1077	pBusLogic->LocalRam.structured.autoSCSIData.fExtendedTranslation = true; /* Same as in geometry register. */
1078	pBusLogic->LocalRam.structured.autoSCSIData.u16DeviceEnabledMask = ~0; /* All enabled. Maybe mask out non present devices? */
1079	pBusLogic->LocalRam.structured.autoSCSIData.u16WidePermittedMask = ~0;
1080	pBusLogic->LocalRam.structured.autoSCSIData.u16FastPermittedMask = ~0;
1081	pBusLogic->LocalRam.structured.autoSCSIData.u16SynchronousPermittedMask = ~0;
1082	pBusLogic->LocalRam.structured.autoSCSIData.u16DisconnectPermittedMask = ~0;
1083	pBusLogic->LocalRam.structured.autoSCSIData.fStrictRoundRobinMode = pBusLogic->fStrictRoundRobinMode;
1084	pBusLogic->LocalRam.structured.autoSCSIData.u16UltraPermittedMask = ~0;
1085	/** @todo calculate checksum? */
1086	}
1087
1088	/**
1089	* Do a hardware reset of the buslogic adapter.
1090	*
1091	* @returns VBox status code.
1092	* @param pBusLogic Pointer to the BusLogic device instance.
1093	* @param fResetIO Flag determining whether ISA I/O should be reset.
1094	*/
1095	static int buslogicR3HwReset(PBUSLOGIC pBusLogic, bool fResetIO)
1096	{
1097	LogFlowFunc(("pBusLogic=%#p\n", pBusLogic));
1098
1099	/* Reset registers to default values. */
1100	pBusLogic->regStatus = BL_STAT_HARDY \| BL_STAT_INREQ;
1101	pBusLogic->regGeometry = BL_GEOM_XLATEN;
1102	pBusLogic->uOperationCode = 0xff; /* No command executing. */
1103	pBusLogic->iParameter = 0;
1104	pBusLogic->cbCommandParametersLeft = 0;
1105	pBusLogic->fIRQEnabled = true;
1106	pBusLogic->fStrictRoundRobinMode = false;
1107	pBusLogic->fExtendedLunCCBFormat = false;
1108	pBusLogic->uMailboxOutgoingPositionCurrent = 0;
1109	pBusLogic->uMailboxIncomingPositionCurrent = 0;
1110
1111	/* Clear any active/pending interrupts. */
1112	pBusLogic->uPendingIntr = 0;
1113	buslogicClearInterrupt(pBusLogic);
1114
1115	/* Guest-initiated HBA reset does not affect ISA port I/O. */
1116	if (fResetIO)
1117	{
1118	buslogicR3RegisterISARange(pBusLogic, pBusLogic->uDefaultISABaseCode);
1119	}
1120	buslogicR3InitializeLocalRam(pBusLogic);
1121	vboxscsiInitialize(&pBusLogic->VBoxSCSI);
1122
1123	return VINF_SUCCESS;
1124	}
1125
1126	#endif /* IN_RING3 */
1127
1128	/**
1129	* Resets the command state machine for the next command and notifies the guest.
1130	*
1131	* @returns nothing.
1132	* @param pBusLogic Pointer to the BusLogic device instance
1133	* @param fSuppressIrq Flag to suppress IRQ generation regardless of current state
1134	*/
1135	static void buslogicCommandComplete(PBUSLOGIC pBusLogic, bool fSuppressIrq)
1136	{
1137	LogFlowFunc(("pBusLogic=%#p\n", pBusLogic));
1138
1139	pBusLogic->fUseLocalRam = false;
1140	pBusLogic->regStatus \|= BL_STAT_HARDY;
1141	pBusLogic->iReply = 0;
1142
1143	/* Modify I/O address does not generate an interrupt. */
1144	if (pBusLogic->uOperationCode != BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND)
1145	{
1146	/* Notify that the command is complete. */
1147	pBusLogic->regStatus &= ~BL_STAT_DIRRDY;
1148	buslogicSetInterrupt(pBusLogic, fSuppressIrq, BL_INTR_CMDC);
1149	}
1150
1151	pBusLogic->uOperationCode = 0xff;
1152	pBusLogic->iParameter = 0;
1153	}
1154
1155	#if defined(IN_RING3)
1156
1157	/**
1158	* Initiates a hard reset which was issued from the guest.
1159	*
1160	* @returns nothing
1161	* @param pBusLogic Pointer to the BusLogic device instance.
1162	* @param fHardReset Flag initiating a hard (vs. soft) reset.
1163	*/
1164	static void buslogicR3InitiateReset(PBUSLOGIC pBusLogic, bool fHardReset)
1165	{
1166	LogFlowFunc(("pBusLogic=%#p fHardReset=%d\n", pBusLogic, fHardReset));
1167
1168	buslogicR3HwReset(pBusLogic, false);
1169
1170	if (fHardReset)
1171	{
1172	/* Set the diagnostic active bit in the status register and clear the ready state. */
1173	pBusLogic->regStatus \|= BL_STAT_DACT;
1174	pBusLogic->regStatus &= ~BL_STAT_HARDY;
1175
1176	/* Remember when the guest initiated a reset (after we're done resetting). */
1177	pBusLogic->u64ResetTime = PDMDevHlpTMTimeVirtGetNano(pBusLogic->CTX_SUFF(pDevIns));
1178	}
1179	}
1180
1181	/**
1182	* Send a mailbox with set status codes to the guest.
1183	*
1184	* @returns nothing.
1185	* @param pBusLogic Pointer to the BusLogic device instance.
1186	* @param pTaskState Pointer to the task state with the mailbox to send.
1187	* @param uHostAdapterStatus The host adapter status code to set.
1188	* @param uDeviceStatus The target device status to set.
1189	* @param uMailboxCompletionCode Completion status code to set in the mailbox.
1190	*/
1191	static void buslogicR3SendIncomingMailbox(PBUSLOGIC pBusLogic, PBUSLOGICTASKSTATE pTaskState,
1192	uint8_t uHostAdapterStatus, uint8_t uDeviceStatus,
1193	uint8_t uMailboxCompletionCode)
1194	{
1195	pTaskState->MailboxGuest.u.in.uHostAdapterStatus = uHostAdapterStatus;
1196	pTaskState->MailboxGuest.u.in.uTargetDeviceStatus = uDeviceStatus;
1197	pTaskState->MailboxGuest.u.in.uCompletionCode = uMailboxCompletionCode;
1198
1199	int rc = PDMCritSectEnter(&pBusLogic->CritSectIntr, VINF_SUCCESS);
1200	AssertRC(rc);
1201
1202	RTGCPHYS GCPhysAddrMailboxIncoming = pBusLogic->GCPhysAddrMailboxIncomingBase
1203	+ ( pBusLogic->uMailboxIncomingPositionCurrent
1204	* (pTaskState->fIs24Bit ? sizeof(Mailbox24) : sizeof(Mailbox32)) );
1205
1206	if (uMailboxCompletionCode != BUSLOGIC_MAILBOX_INCOMING_COMPLETION_ABORTED_NOT_FOUND)
1207	{
1208	RTGCPHYS GCPhysAddrCCB = pTaskState->MailboxGuest.u32PhysAddrCCB;
1209	LogFlowFunc(("Completing CCB %RGp hstat=%u, dstat=%u, outgoing mailbox at %RGp\n", GCPhysAddrCCB,
1210	uHostAdapterStatus, uDeviceStatus, GCPhysAddrMailboxIncoming));
1211
1212	/* Update CCB. */
1213	pTaskState->CommandControlBlockGuest.c.uHostAdapterStatus = uHostAdapterStatus;
1214	pTaskState->CommandControlBlockGuest.c.uDeviceStatus = uDeviceStatus;
1215	/* Rewrite CCB up to the CDB; perhaps more than necessary. */
1216	PDMDevHlpPCIPhysWrite(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrCCB,
1217	&pTaskState->CommandControlBlockGuest, RT_OFFSETOF(CCBC, abCDB));
1218	}
1219
1220	# ifdef RT_STRICT
1221	uint8_t uCode;
1222	unsigned uCodeOffs = pTaskState->fIs24Bit ? RT_OFFSETOF(Mailbox24, uCmdState) : RT_OFFSETOF(Mailbox32, u.out.uActionCode);
1223	PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrMailboxIncoming + uCodeOffs, &uCode, sizeof(uCode));
1224	Assert(uCode == BUSLOGIC_MAILBOX_INCOMING_COMPLETION_FREE);
1225	# endif
1226
1227	/* Update mailbox. */
1228	if (pTaskState->fIs24Bit)
1229	{
1230	Mailbox24 Mbx24;
1231
1232	Mbx24.uCmdState = pTaskState->MailboxGuest.u.in.uCompletionCode;
1233	U32_TO_ADDR(Mbx24.aPhysAddrCCB, pTaskState->MailboxGuest.u32PhysAddrCCB);
1234	Log(("24-bit mailbox: completion code=%u, CCB at %RGp\n", Mbx24.uCmdState, (RTGCPHYS)ADDR_TO_U32(Mbx24.aPhysAddrCCB)));
1235	PDMDevHlpPCIPhysWrite(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrMailboxIncoming, &Mbx24, sizeof(Mailbox24));
1236	}
1237	else
1238	{
1239	Log(("32-bit mailbox: completion code=%u, CCB at %RGp\n", pTaskState->MailboxGuest.u.in.uCompletionCode, (RTGCPHYS)pTaskState->MailboxGuest.u32PhysAddrCCB));
1240	PDMDevHlpPCIPhysWrite(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrMailboxIncoming,
1241	&pTaskState->MailboxGuest, sizeof(Mailbox32));
1242	}
1243
1244	/* Advance to next mailbox position. */
1245	pBusLogic->uMailboxIncomingPositionCurrent++;
1246	if (pBusLogic->uMailboxIncomingPositionCurrent >= pBusLogic->cMailbox)
1247	pBusLogic->uMailboxIncomingPositionCurrent = 0;
1248
1249	# ifdef LOG_ENABLED
1250	ASMAtomicIncU32(&pBusLogic->cInMailboxesReady);
1251	# endif
1252
1253	buslogicSetInterrupt(pBusLogic, false, BL_INTR_IMBL);
1254
1255	PDMCritSectLeave(&pBusLogic->CritSectIntr);
1256	}
1257
1258	# ifdef LOG_ENABLED
1259
1260	/**
1261	* Dumps the content of a mailbox for debugging purposes.
1262	*
1263	* @return nothing
1264	* @param pMailbox The mailbox to dump.
1265	* @param fOutgoing true if dumping the outgoing state.
1266	* false if dumping the incoming state.
1267	*/
1268	static void buslogicR3DumpMailboxInfo(PMailbox32 pMailbox, bool fOutgoing)
1269	{
1270	Log(("%s: Dump for %s mailbox:\n", __FUNCTION__, fOutgoing ? "outgoing" : "incoming"));
1271	Log(("%s: u32PhysAddrCCB=%#x\n", __FUNCTION__, pMailbox->u32PhysAddrCCB));
1272	if (fOutgoing)
1273	{
1274	Log(("%s: uActionCode=%u\n", __FUNCTION__, pMailbox->u.out.uActionCode));
1275	}
1276	else
1277	{
1278	Log(("%s: uHostAdapterStatus=%u\n", __FUNCTION__, pMailbox->u.in.uHostAdapterStatus));
1279	Log(("%s: uTargetDeviceStatus=%u\n", __FUNCTION__, pMailbox->u.in.uTargetDeviceStatus));
1280	Log(("%s: uCompletionCode=%u\n", __FUNCTION__, pMailbox->u.in.uCompletionCode));
1281	}
1282	}
1283
1284	/**
1285	* Dumps the content of a command control block for debugging purposes.
1286	*
1287	* @returns nothing.
1288	* @param pCCB Pointer to the command control block to dump.
1289	* @param fIs24BitCCB Flag to determine CCB format.
1290	*/
1291	static void buslogicR3DumpCCBInfo(PCCBU pCCB, bool fIs24BitCCB)
1292	{
1293	Log(("%s: Dump for %s Command Control Block:\n", __FUNCTION__, fIs24BitCCB ? "24-bit" : "32-bit"));
1294	Log(("%s: uOpCode=%#x\n", __FUNCTION__, pCCB->c.uOpcode));
1295	Log(("%s: uDataDirection=%u\n", __FUNCTION__, pCCB->c.uDataDirection));
1296	Log(("%s: cbCDB=%u\n", __FUNCTION__, pCCB->c.cbCDB));
1297	Log(("%s: cbSenseData=%u\n", __FUNCTION__, pCCB->c.cbSenseData));
1298	Log(("%s: uHostAdapterStatus=%u\n", __FUNCTION__, pCCB->c.uHostAdapterStatus));
1299	Log(("%s: uDeviceStatus=%u\n", __FUNCTION__, pCCB->c.uDeviceStatus));
1300	if (fIs24BitCCB)
1301	{
1302	Log(("%s: cbData=%u\n", __FUNCTION__, LEN_TO_U32(pCCB->o.acbData)));
1303	Log(("%s: PhysAddrData=%#x\n", __FUNCTION__, ADDR_TO_U32(pCCB->o.aPhysAddrData)));
1304	Log(("%s: uTargetId=%u\n", __FUNCTION__, pCCB->o.uTargetId));
1305	Log(("%s: uLogicalUnit=%u\n", __FUNCTION__, pCCB->o.uLogicalUnit));
1306	}
1307	else
1308	{
1309	Log(("%s: cbData=%u\n", __FUNCTION__, pCCB->n.cbData));
1310	Log(("%s: PhysAddrData=%#x\n", __FUNCTION__, pCCB->n.u32PhysAddrData));
1311	Log(("%s: uTargetId=%u\n", __FUNCTION__, pCCB->n.uTargetId));
1312	Log(("%s: uLogicalUnit=%u\n", __FUNCTION__, pCCB->n.uLogicalUnit));
1313	Log(("%s: fTagQueued=%d\n", __FUNCTION__, pCCB->n.fTagQueued));
1314	Log(("%s: uQueueTag=%u\n", __FUNCTION__, pCCB->n.uQueueTag));
1315	Log(("%s: fLegacyTagEnable=%u\n", __FUNCTION__, pCCB->n.fLegacyTagEnable));
1316	Log(("%s: uLegacyQueueTag=%u\n", __FUNCTION__, pCCB->n.uLegacyQueueTag));
1317	Log(("%s: PhysAddrSenseData=%#x\n", __FUNCTION__, pCCB->n.u32PhysAddrSenseData));
1318	}
1319	Log(("%s: uCDB[0]=%#x\n", __FUNCTION__, pCCB->c.abCDB[0]));
1320	for (int i = 1; i < pCCB->c.cbCDB; i++)
1321	Log(("%s: uCDB[%d]=%u\n", __FUNCTION__, i, pCCB->c.abCDB[i]));
1322	}
1323
1324	# endif /* LOG_ENABLED */
1325
1326	/**
1327	* Allocate data buffer.
1328	*
1329	* @param pTaskState Pointer to the task state.
1330	* @param GCSGList Guest physical address of S/G list.
1331	* @param cEntries Number of list entries to read.
1332	* @param pSGEList Pointer to 32-bit S/G list storage.
1333	*/
1334	static void buslogicR3ReadSGEntries(PBUSLOGICTASKSTATE pTaskState, RTGCPHYS GCSGList, uint32_t cEntries, SGE32 *pSGEList)
1335	{
1336	PPDMDEVINS pDevIns = pTaskState->CTX_SUFF(pTargetDevice)->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);
1337	SGE24 aSGE24[32];
1338	Assert(cEntries <= RT_ELEMENTS(aSGE24));
1339
1340	/* Read the S/G entries. Convert 24-bit entries to 32-bit format. */
1341	if (pTaskState->fIs24Bit)
1342	{
1343	Log2(("Converting %u 24-bit S/G entries to 32-bit\n", cEntries));
1344	PDMDevHlpPhysRead(pDevIns, GCSGList, &aSGE24, cEntries * sizeof(SGE24));
1345	for (uint32_t i = 0; i < cEntries; ++i)
1346	{
1347	pSGEList[i].cbSegment = LEN_TO_U32(aSGE24[i].acbSegment);
1348	pSGEList[i].u32PhysAddrSegmentBase = ADDR_TO_U32(aSGE24[i].aPhysAddrSegmentBase);
1349	}
1350	}
1351	else
1352	PDMDevHlpPhysRead(pDevIns, GCSGList, pSGEList, cEntries * sizeof(SGE32));
1353	}
1354
1355	/**
1356	* Allocate data buffer.
1357	*
1358	* @returns VBox status code.
1359	* @param pTaskState Pointer to the task state.
1360	*/
1361	static int buslogicR3DataBufferAlloc(PBUSLOGICTASKSTATE pTaskState)
1362	{
1363	PPDMDEVINS pDevIns = pTaskState->CTX_SUFF(pTargetDevice)->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);
1364	uint32_t cbDataCCB;
1365	uint32_t u32PhysAddrCCB;
1366
1367	/* Extract the data length and physical address from the CCB. */
1368	if (pTaskState->fIs24Bit)
1369	{
1370	u32PhysAddrCCB = ADDR_TO_U32(pTaskState->CommandControlBlockGuest.o.aPhysAddrData);
1371	cbDataCCB = LEN_TO_U32(pTaskState->CommandControlBlockGuest.o.acbData);
1372	}
1373	else
1374	{
1375	u32PhysAddrCCB = pTaskState->CommandControlBlockGuest.n.u32PhysAddrData;
1376	cbDataCCB = pTaskState->CommandControlBlockGuest.n.cbData;
1377	}
1378
1379	if ( (pTaskState->CommandControlBlockGuest.c.uDataDirection != BUSLOGIC_CCB_DIRECTION_NO_DATA)
1380	&& cbDataCCB)
1381	{
1382	/** @todo Check following assumption and what residual means. */
1383	/*
1384	* The BusLogic adapter can handle two different data buffer formats.
1385	* The first one is that the data pointer entry in the CCB points to
1386	* the buffer directly. In second mode the data pointer points to a
1387	* scatter gather list which describes the buffer.
1388	*/
1389	if ( (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_SCATTER_GATHER)
1390	\|\| (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_SCATTER_GATHER))
1391	{
1392	uint32_t cScatterGatherGCRead;
1393	uint32_t iScatterGatherEntry;
1394	SGE32 aScatterGatherReadGC[32]; /* A buffer for scatter gather list entries read from guest memory. */
1395	uint32_t cScatterGatherGCLeft = cbDataCCB / pTaskState->cbSGEntry;
1396	RTGCPHYS GCPhysAddrScatterGatherCurrent = u32PhysAddrCCB;
1397	size_t cbDataToTransfer = 0;
1398
1399	/* Count number of bytes to transfer. */
1400	do
1401	{
1402	cScatterGatherGCRead = (cScatterGatherGCLeft < RT_ELEMENTS(aScatterGatherReadGC))
1403	? cScatterGatherGCLeft
1404	: RT_ELEMENTS(aScatterGatherReadGC);
1405	cScatterGatherGCLeft -= cScatterGatherGCRead;
1406
1407	buslogicR3ReadSGEntries(pTaskState, GCPhysAddrScatterGatherCurrent, cScatterGatherGCRead, aScatterGatherReadGC);
1408
1409	for (iScatterGatherEntry = 0; iScatterGatherEntry < cScatterGatherGCRead; iScatterGatherEntry++)
1410	{
1411	RTGCPHYS GCPhysAddrDataBase;
1412
1413	Log(("%s: iScatterGatherEntry=%u\n", __FUNCTION__, iScatterGatherEntry));
1414
1415	GCPhysAddrDataBase = (RTGCPHYS)aScatterGatherReadGC[iScatterGatherEntry].u32PhysAddrSegmentBase;
1416	cbDataToTransfer += aScatterGatherReadGC[iScatterGatherEntry].cbSegment;
1417
1418	Log(("%s: GCPhysAddrDataBase=%RGp cbDataToTransfer=%u\n",
1419	__FUNCTION__, GCPhysAddrDataBase,
1420	aScatterGatherReadGC[iScatterGatherEntry].cbSegment));
1421	}
1422
1423	/* Set address to the next entries to read. */
1424	GCPhysAddrScatterGatherCurrent += cScatterGatherGCRead * pTaskState->cbSGEntry;
1425	} while (cScatterGatherGCLeft > 0);
1426
1427	Log(("%s: cbDataToTransfer=%d\n", __FUNCTION__, cbDataToTransfer));
1428
1429	/* Allocate buffer */
1430	pTaskState->DataSeg.cbSeg = cbDataToTransfer;
1431	pTaskState->DataSeg.pvSeg = RTMemAlloc(pTaskState->DataSeg.cbSeg);
1432	if (!pTaskState->DataSeg.pvSeg)
1433	return VERR_NO_MEMORY;
1434
1435	/* Copy the data if needed */
1436	if ( (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_OUT)
1437	\|\| (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_UNKNOWN))
1438	{
1439	cScatterGatherGCLeft = cbDataCCB / pTaskState->cbSGEntry;
1440	GCPhysAddrScatterGatherCurrent = u32PhysAddrCCB;
1441	uint8_t pbData = (uint8_t )pTaskState->DataSeg.pvSeg;
1442
1443	do
1444	{
1445	cScatterGatherGCRead = (cScatterGatherGCLeft < RT_ELEMENTS(aScatterGatherReadGC))
1446	? cScatterGatherGCLeft
1447	: RT_ELEMENTS(aScatterGatherReadGC);
1448	cScatterGatherGCLeft -= cScatterGatherGCRead;
1449
1450	buslogicR3ReadSGEntries(pTaskState, GCPhysAddrScatterGatherCurrent, cScatterGatherGCRead, aScatterGatherReadGC);
1451
1452	for (iScatterGatherEntry = 0; iScatterGatherEntry < cScatterGatherGCRead; iScatterGatherEntry++)
1453	{
1454	RTGCPHYS GCPhysAddrDataBase;
1455
1456	Log(("%s: iScatterGatherEntry=%u\n", __FUNCTION__, iScatterGatherEntry));
1457
1458	GCPhysAddrDataBase = (RTGCPHYS)aScatterGatherReadGC[iScatterGatherEntry].u32PhysAddrSegmentBase;
1459	cbDataToTransfer = aScatterGatherReadGC[iScatterGatherEntry].cbSegment;
1460
1461	Log(("%s: GCPhysAddrDataBase=%RGp cbDataToTransfer=%u\n", __FUNCTION__, GCPhysAddrDataBase, cbDataToTransfer));
1462
1463	PDMDevHlpPhysRead(pDevIns, GCPhysAddrDataBase, pbData, cbDataToTransfer);
1464	pbData += cbDataToTransfer;
1465	}
1466
1467	/* Set address to the next entries to read. */
1468	GCPhysAddrScatterGatherCurrent += cScatterGatherGCRead * pTaskState->cbSGEntry;
1469	} while (cScatterGatherGCLeft > 0);
1470	}
1471
1472	}
1473	else if ( pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB
1474	\|\| pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_DATA_LENGTH)
1475	{
1476	/* The buffer is not scattered. */
1477	RTGCPHYS GCPhysAddrDataBase = u32PhysAddrCCB;
1478
1479	AssertMsg(GCPhysAddrDataBase != 0, ("Physical address is 0\n"));
1480
1481	pTaskState->DataSeg.cbSeg = cbDataCCB;
1482	pTaskState->DataSeg.pvSeg = RTMemAlloc(pTaskState->DataSeg.cbSeg);
1483	if (!pTaskState->DataSeg.pvSeg)
1484	return VERR_NO_MEMORY;
1485
1486	Log(("Non scattered buffer:\n"));
1487	Log(("u32PhysAddrData=%#x\n", u32PhysAddrCCB));
1488	Log(("cbData=%u\n", cbDataCCB));
1489	Log(("GCPhysAddrDataBase=0x%RGp\n", GCPhysAddrDataBase));
1490
1491	/* Copy the data into the buffer. */
1492	PDMDevHlpPhysRead(pDevIns, GCPhysAddrDataBase, pTaskState->DataSeg.pvSeg, pTaskState->DataSeg.cbSeg);
1493	}
1494	}
1495
1496	return VINF_SUCCESS;
1497	}
1498
1499	/**
1500	* Free allocated resources used for the scatter gather list.
1501	*
1502	* @returns nothing.
1503	* @param pTaskState Pointer to the task state.
1504	*/
1505	static void buslogicR3DataBufferFree(PBUSLOGICTASKSTATE pTaskState)
1506	{
1507	PPDMDEVINS pDevIns = pTaskState->CTX_SUFF(pTargetDevice)->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);
1508	uint32_t cbDataCCB;
1509	uint32_t u32PhysAddrCCB;
1510
1511	/* Extract the data length and physical address from the CCB. */
1512	if (pTaskState->fIs24Bit)
1513	{
1514	u32PhysAddrCCB = ADDR_TO_U32(pTaskState->CommandControlBlockGuest.o.aPhysAddrData);
1515	cbDataCCB = LEN_TO_U32(pTaskState->CommandControlBlockGuest.o.acbData);
1516	}
1517	else
1518	{
1519	u32PhysAddrCCB = pTaskState->CommandControlBlockGuest.n.u32PhysAddrData;
1520	cbDataCCB = pTaskState->CommandControlBlockGuest.n.cbData;
1521	}
1522
1523	#if 1
1524	/* Hack for NT 10/91: A CCB describes a 2K buffer, but TEST UNIT READY is executed. This command
1525	* returns no data, hence the buffer must be left alone!
1526	*/
1527	if (pTaskState->CommandControlBlockGuest.c.abCDB[0] == 0)
1528	cbDataCCB = 0;
1529	#endif
1530
1531	LogFlowFunc(("pTaskState=%#p cbDataCCB=%u direction=%u cbSeg=%u\n", pTaskState, cbDataCCB,
1532	pTaskState->CommandControlBlockGuest.c.uDataDirection, pTaskState->DataSeg.cbSeg));
1533
1534	if ( (cbDataCCB > 0)
1535	&& ( (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_IN)
1536	\|\| (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_UNKNOWN)))
1537	{
1538	if ( (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_SCATTER_GATHER)
1539	\|\| (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_SCATTER_GATHER))
1540	{
1541	uint32_t cScatterGatherGCRead;
1542	uint32_t iScatterGatherEntry;
1543	SGE32 aScatterGatherReadGC[32]; /* Number of scatter gather list entries read from guest memory. */
1544	uint32_t cScatterGatherGCLeft = cbDataCCB / pTaskState->cbSGEntry;
1545	RTGCPHYS GCPhysAddrScatterGatherCurrent = u32PhysAddrCCB;
1546	uint8_t pbData = (uint8_t )pTaskState->DataSeg.pvSeg;
1547
1548	do
1549	{
1550	cScatterGatherGCRead = (cScatterGatherGCLeft < RT_ELEMENTS(aScatterGatherReadGC))
1551	? cScatterGatherGCLeft
1552	: RT_ELEMENTS(aScatterGatherReadGC);
1553	cScatterGatherGCLeft -= cScatterGatherGCRead;
1554
1555	buslogicR3ReadSGEntries(pTaskState, GCPhysAddrScatterGatherCurrent, cScatterGatherGCRead, aScatterGatherReadGC);
1556
1557	for (iScatterGatherEntry = 0; iScatterGatherEntry < cScatterGatherGCRead; iScatterGatherEntry++)
1558	{
1559	RTGCPHYS GCPhysAddrDataBase;
1560	size_t cbDataToTransfer;
1561
1562	Log(("%s: iScatterGatherEntry=%u\n", __FUNCTION__, iScatterGatherEntry));
1563
1564	GCPhysAddrDataBase = (RTGCPHYS)aScatterGatherReadGC[iScatterGatherEntry].u32PhysAddrSegmentBase;
1565	cbDataToTransfer = aScatterGatherReadGC[iScatterGatherEntry].cbSegment;
1566
1567	Log(("%s: GCPhysAddrDataBase=%RGp cbDataToTransfer=%u\n", __FUNCTION__, GCPhysAddrDataBase, cbDataToTransfer));
1568
1569	PDMDevHlpPCIPhysWrite(pDevIns, GCPhysAddrDataBase, pbData, cbDataToTransfer);
1570	pbData += cbDataToTransfer;
1571	}
1572
1573	/* Set address to the next entries to read. */
1574	GCPhysAddrScatterGatherCurrent += cScatterGatherGCRead * pTaskState->cbSGEntry;
1575	} while (cScatterGatherGCLeft > 0);
1576
1577	}
1578	else if ( pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB
1579	\|\| pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_DATA_LENGTH)
1580	{
1581	/* The buffer is not scattered. */
1582	RTGCPHYS GCPhysAddrDataBase = u32PhysAddrCCB;
1583
1584	AssertMsg(GCPhysAddrDataBase != 0, ("Physical address is 0\n"));
1585
1586	Log(("Non-scattered buffer:\n"));
1587	Log(("u32PhysAddrData=%#x\n", u32PhysAddrCCB));
1588	Log(("cbData=%u\n", cbDataCCB));
1589	Log(("GCPhysAddrDataBase=0x%RGp\n", GCPhysAddrDataBase));
1590
1591	/* Copy the data into the guest memory. */
1592	PDMDevHlpPCIPhysWrite(pDevIns, GCPhysAddrDataBase, pTaskState->DataSeg.pvSeg, pTaskState->DataSeg.cbSeg);
1593	}
1594
1595	}
1596	/* Update residual data length. */
1597	if ( (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_DATA_LENGTH)
1598	\|\| (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_SCATTER_GATHER))
1599	{
1600	uint32_t cbResidual;
1601
1602	/** @todo we need to get the actual transfer length from the VSCSI layer?! */
1603	cbResidual = 0; //LEN_TO_U32(pTaskState->CCBGuest.acbData) - ???;
1604	if (pTaskState->fIs24Bit)
1605	U32_TO_LEN(pTaskState->CommandControlBlockGuest.o.acbData, cbResidual);
1606	else
1607	pTaskState->CommandControlBlockGuest.n.cbData = cbResidual;
1608	}
1609
1610	RTMemFree(pTaskState->DataSeg.pvSeg);
1611	pTaskState->DataSeg.pvSeg = NULL;
1612	pTaskState->DataSeg.cbSeg = 0;
1613	}
1614
1615	/** Convert sense buffer length taking into account shortcut values. */
1616	static uint32_t buslogicR3ConvertSenseBufferLength(uint32_t cbSense)
1617	{
1618	/* Convert special sense buffer length values. */
1619	if (cbSense == 0)
1620	cbSense = 14; /* 0 means standard 14-byte buffer. */
1621	else if (cbSense == 1)
1622	cbSense = 0; /* 1 means no sense data. */
1623	else if (cbSense < 8)
1624	AssertMsgFailed(("Reserved cbSense value of %d used!\n", cbSense));
1625
1626	return cbSense;
1627	}
1628
1629	/**
1630	* Free the sense buffer.
1631	*
1632	* @returns nothing.
1633	* @param pTaskState Pointer to the task state.
1634	* @param fCopy If sense data should be copied to guest memory.
1635	*/
1636	static void buslogicR3SenseBufferFree(PBUSLOGICTASKSTATE pTaskState, bool fCopy)
1637	{
1638	uint32_t cbSenseBuffer;
1639
1640	cbSenseBuffer = buslogicR3ConvertSenseBufferLength(pTaskState->CommandControlBlockGuest.c.cbSenseData);
1641
1642	/* Copy the sense buffer into guest memory if requested. */
1643	if (fCopy && cbSenseBuffer)
1644	{
1645	PPDMDEVINS pDevIns = pTaskState->CTX_SUFF(pTargetDevice)->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);
1646	RTGCPHYS GCPhysAddrSenseBuffer;
1647
1648	/* With 32-bit CCBs, the (optional) sense buffer physical address is provided separately.
1649	* On the other hand, with 24-bit CCBs, the sense buffer is simply located at the end of
1650	* the CCB, right after the variable-length CDB.
1651	*/
1652	if (pTaskState->fIs24Bit)
1653	{
1654	GCPhysAddrSenseBuffer = pTaskState->MailboxGuest.u32PhysAddrCCB;
1655	GCPhysAddrSenseBuffer += pTaskState->CommandControlBlockGuest.c.cbCDB + RT_OFFSETOF(CCB24, abCDB);
1656	}
1657	else
1658	GCPhysAddrSenseBuffer = pTaskState->CommandControlBlockGuest.n.u32PhysAddrSenseData;
1659
1660	Log3(("%s: sense buffer: %.*Rhxs\n", __FUNCTION__, cbSenseBuffer, pTaskState->pbSenseBuffer));
1661	PDMDevHlpPCIPhysWrite(pDevIns, GCPhysAddrSenseBuffer, pTaskState->pbSenseBuffer, cbSenseBuffer);
1662	}
1663
1664	RTMemFree(pTaskState->pbSenseBuffer);
1665	pTaskState->pbSenseBuffer = NULL;
1666	}
1667
1668	/**
1669	* Alloc the sense buffer.
1670	*
1671	* @returns VBox status code.
1672	* @param pTaskState Pointer to the task state.
1673	* @note Current assumption is that the sense buffer is not scattered and does not cross a page boundary.
1674	*/
1675	static int buslogicR3SenseBufferAlloc(PBUSLOGICTASKSTATE pTaskState)
1676	{
1677	PPDMDEVINS pDevIns = pTaskState->CTX_SUFF(pTargetDevice)->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);
1678	uint32_t cbSenseBuffer;
1679
1680	pTaskState->pbSenseBuffer = NULL;
1681
1682	cbSenseBuffer = buslogicR3ConvertSenseBufferLength(pTaskState->CommandControlBlockGuest.c.cbSenseData);
1683	if (cbSenseBuffer)
1684	{
1685	pTaskState->pbSenseBuffer = (uint8_t *)RTMemAllocZ(cbSenseBuffer);
1686	if (!pTaskState->pbSenseBuffer)
1687	return VERR_NO_MEMORY;
1688	}
1689
1690	return VINF_SUCCESS;
1691	}
1692
1693	#endif /* IN_RING3 */
1694
1695	/**
1696	* Parses the command buffer and executes it.
1697	*
1698	* @returns VBox status code.
1699	* @param pBusLogic Pointer to the BusLogic device instance.
1700	*/
1701	static int buslogicProcessCommand(PBUSLOGIC pBusLogic)
1702	{
1703	int rc = VINF_SUCCESS;
1704	bool fSuppressIrq = false;
1705
1706	LogFlowFunc(("pBusLogic=%#p\n", pBusLogic));
1707	AssertMsg(pBusLogic->uOperationCode != 0xff, ("There is no command to execute\n"));
1708
1709	switch (pBusLogic->uOperationCode)
1710	{
1711	case BUSLOGICCOMMAND_TEST_CMDC_INTERRUPT:
1712	/* Valid command, no reply. */
1713	pBusLogic->cbReplyParametersLeft = 0;
1714	break;
1715	case BUSLOGICCOMMAND_INQUIRE_PCI_HOST_ADAPTER_INFORMATION:
1716	{
1717	PReplyInquirePCIHostAdapterInformation pReply = (PReplyInquirePCIHostAdapterInformation)pBusLogic->aReplyBuffer;
1718	memset(pReply, 0, sizeof(ReplyInquirePCIHostAdapterInformation));
1719
1720	/* It seems VMware does not provide valid information here too, lets do the same :) */
1721	pReply->InformationIsValid = 0;
1722	pReply->IsaIOPort = pBusLogic->uISABaseCode;
1723	pReply->IRQ = PCIDevGetInterruptLine(&pBusLogic->dev);
1724	pBusLogic->cbReplyParametersLeft = sizeof(ReplyInquirePCIHostAdapterInformation);
1725	break;
1726	}
1727	case BUSLOGICCOMMAND_SET_SCSI_SELECTION_TIMEOUT:
1728	{
1729	/* no-op */
1730	pBusLogic->cbReplyParametersLeft = 0;
1731	break;
1732	}
1733	case BUSLOGICCOMMAND_MODIFY_IO_ADDRESS:
1734	{
1735	/* Modify the ISA-compatible I/O port base. Note that this technically
1736	* violates the PCI spec, as this address is not reported through PCI.
1737	* However, it is required for compatibility with old drivers.
1738	*/
1739	#ifdef IN_RING3
1740	Log(("ISA I/O for PCI (code %x)\n", pBusLogic->aCommandBuffer[0]));
1741	buslogicR3RegisterISARange(pBusLogic, pBusLogic->aCommandBuffer[0]);
1742	pBusLogic->cbReplyParametersLeft = 0;
1743	fSuppressIrq = true;
1744	break;
1745	#else
1746	AssertMsgFailed(("Must never get here!\n"));
1747	#endif
1748	}
1749	case BUSLOGICCOMMAND_INQUIRE_BOARD_ID:
1750	{
1751	/* The special option byte is important: If it is '0' or 'B', Windows NT drivers
1752	* for Adaptec AHA-154x may claim the adapter. The BusLogic drivers will claim
1753	* the adapter only when the byte is not '0' or 'B'.
1754	*/
1755	pBusLogic->aReplyBuffer[0] = 'A'; /* Firmware option bytes */
1756	pBusLogic->aReplyBuffer[1] = 'A'; /* Special option byte */
1757
1758	/* We report version 5.07B. This reply will provide the first two digits. */
1759	pBusLogic->aReplyBuffer[2] = '5'; /* Major version 5 */
1760	pBusLogic->aReplyBuffer[3] = '0'; /* Minor version 0 */
1761	pBusLogic->cbReplyParametersLeft = 4; /* Reply is 4 bytes long */
1762	break;
1763	}
1764	case BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_3RD_LETTER:
1765	{
1766	pBusLogic->aReplyBuffer[0] = '7';
1767	pBusLogic->cbReplyParametersLeft = 1;
1768	break;
1769	}
1770	case BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_LETTER:
1771	{
1772	pBusLogic->aReplyBuffer[0] = 'B';
1773	pBusLogic->cbReplyParametersLeft = 1;
1774	break;
1775	}
1776	case BUSLOGICCOMMAND_SET_ADAPTER_OPTIONS:
1777	/* The parameter list length is determined by the first byte of the command buffer. */
1778	if (pBusLogic->iParameter == 1)
1779	{
1780	/* First pass - set the number of following parameter bytes. */
1781	pBusLogic->cbCommandParametersLeft = pBusLogic->aCommandBuffer[0];
1782	Log(("Set HA options: %u bytes follow\n", pBusLogic->cbCommandParametersLeft));
1783	}
1784	else
1785	{
1786	/* Second pass - process received data. */
1787	Log(("Set HA options: received %u bytes\n", pBusLogic->aCommandBuffer[0]));
1788	/* We ignore the data - it only concerns the SCSI hardware protocol. */
1789	}
1790	pBusLogic->cbReplyParametersLeft = 0;
1791	break;
1792
1793	case BUSLOGICCOMMAND_EXECUTE_SCSI_COMMAND:
1794	/* The parameter list length is at least 12 bytes; the 12th byte determines
1795	* the number of additional CDB bytes that will follow.
1796	*/
1797	if (pBusLogic->iParameter == 12)
1798	{
1799	/* First pass - set the number of following CDB bytes. */
1800	pBusLogic->cbCommandParametersLeft = pBusLogic->aCommandBuffer[11];
1801	Log(("Execute SCSI cmd: %u more bytes follow\n", pBusLogic->cbCommandParametersLeft));
1802	}
1803	else
1804	{
1805	PESCMD pCmd;
1806
1807	/* Second pass - process received data. */
1808	Log(("Execute SCSI cmd: received %u bytes\n", pBusLogic->aCommandBuffer[0]));
1809
1810	pCmd = (PESCMD)pBusLogic->aCommandBuffer;
1811	Log(("Addr %08X, cbData %08X, cbCDB=%u\n", pCmd->u32PhysAddrData, pCmd->cbData, pCmd->cbCDB));
1812	}
1813	// This is currently a dummy - just fails every command.
1814	pBusLogic->cbReplyParametersLeft = 4;
1815	pBusLogic->aReplyBuffer[0] = pBusLogic->aReplyBuffer[1] = 0;
1816	pBusLogic->aReplyBuffer[2] = 0x11; /* HBA status (timeout). */
1817	pBusLogic->aReplyBuffer[3] = 0; /* Device status. */
1818	break;
1819
1820	case BUSLOGICCOMMAND_INQUIRE_HOST_ADAPTER_MODEL_NUMBER:
1821	{
1822	/* The reply length is set by the guest and is found in the first byte of the command buffer. */
1823	pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[0];
1824	memset(pBusLogic->aReplyBuffer, 0, pBusLogic->cbReplyParametersLeft);
1825	const char aModelName[] = "958D "; /* Trailing \0 is fine, that's the filler anyway. */
1826	int cCharsToTransfer = pBusLogic->cbReplyParametersLeft <= sizeof(aModelName)
1827	? pBusLogic->cbReplyParametersLeft
1828	: sizeof(aModelName);
1829
1830	for (int i = 0; i < cCharsToTransfer; i++)
1831	pBusLogic->aReplyBuffer[i] = aModelName[i];
1832
1833	break;
1834	}
1835	case BUSLOGICCOMMAND_INQUIRE_CONFIGURATION:
1836	{
1837	uint8_t uPciIrq = PCIDevGetInterruptLine(&pBusLogic->dev);
1838
1839	pBusLogic->cbReplyParametersLeft = sizeof(ReplyInquireConfiguration);
1840	PReplyInquireConfiguration pReply = (PReplyInquireConfiguration)pBusLogic->aReplyBuffer;
1841	memset(pReply, 0, sizeof(ReplyInquireConfiguration));
1842
1843	pReply->uHostAdapterId = 7; /* The controller has always 7 as ID. */
1844	pReply->fDmaChannel6 = 1; /* DMA channel 6 is a good default. */
1845	/* The PCI IRQ is not necessarily representable in this structure.
1846	* If that is the case, the guest likely won't function correctly,
1847	* therefore we log a warning.
1848	*/
1849	switch (uPciIrq)
1850	{
1851	case 9: pReply->fIrqChannel9 = 1; break;
1852	case 10: pReply->fIrqChannel10 = 1; break;
1853	case 11: pReply->fIrqChannel11 = 1; break;
1854	case 12: pReply->fIrqChannel12 = 1; break;
1855	case 14: pReply->fIrqChannel14 = 1; break;
1856	case 15: pReply->fIrqChannel15 = 1; break;
1857	default:
1858	LogRel(("Warning: PCI IRQ %d cannot be represented as ISA!\n", uPciIrq));
1859	break;
1860	}
1861	break;
1862	}
1863	case BUSLOGICCOMMAND_INQUIRE_EXTENDED_SETUP_INFORMATION:
1864	{
1865	/* Some Adaptec AHA-154x drivers (e.g. OS/2) execute this command and expect
1866	* it to fail. If it succeeds, the drivers refuse to load. However, some newer
1867	* Adaptec 154x models supposedly support it too??
1868	*/
1869
1870	/* The reply length is set by the guest and is found in the first byte of the command buffer. */
1871	pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[0];
1872	PReplyInquireExtendedSetupInformation pReply = (PReplyInquireExtendedSetupInformation)pBusLogic->aReplyBuffer;
1873	memset(pReply, 0, sizeof(ReplyInquireExtendedSetupInformation));
1874
1875	/** @todo should this reflect the RAM contents (AutoSCSIRam)? */
1876	pReply->uBusType = 'E'; /* EISA style */
1877	pReply->u16ScatterGatherLimit = 8192;
1878	pReply->cMailbox = pBusLogic->cMailbox;
1879	pReply->uMailboxAddressBase = (uint32_t)pBusLogic->GCPhysAddrMailboxOutgoingBase;
1880	pReply->fLevelSensitiveInterrupt = true;
1881	pReply->fHostWideSCSI = true;
1882	pReply->fHostUltraSCSI = true;
1883	memcpy(pReply->aFirmwareRevision, "07B", sizeof(pReply->aFirmwareRevision));
1884
1885	break;
1886	}
1887	case BUSLOGICCOMMAND_INQUIRE_SETUP_INFORMATION:
1888	{
1889	/* The reply length is set by the guest and is found in the first byte of the command buffer. */
1890	pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[0];
1891	PReplyInquireSetupInformation pReply = (PReplyInquireSetupInformation)pBusLogic->aReplyBuffer;
1892	memset(pReply, 0, sizeof(ReplyInquireSetupInformation));
1893	pReply->fSynchronousInitiationEnabled = true;
1894	pReply->fParityCheckingEnabled = true;
1895	pReply->cMailbox = pBusLogic->cMailbox;
1896	U32_TO_ADDR(pReply->MailboxAddress, pBusLogic->GCPhysAddrMailboxOutgoingBase);
1897	pReply->uSignature = 'B';
1898	/* The 'D' signature prevents Adaptec's OS/2 drivers from getting too
1899	* friendly with BusLogic hardware and upsetting the HBA state.
1900	*/
1901	pReply->uCharacterD = 'D'; /* BusLogic model. */
1902	pReply->uHostBusType = 'F'; /* PCI bus. */
1903	break;
1904	}
1905	case BUSLOGICCOMMAND_FETCH_HOST_ADAPTER_LOCAL_RAM:
1906	{
1907	/*
1908	* First element in the command buffer contains start offset to read from
1909	* and second one the number of bytes to read.
1910	*/
1911	uint8_t uOffset = pBusLogic->aCommandBuffer[0];
1912	pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[1];
1913
1914	pBusLogic->fUseLocalRam = true;
1915	pBusLogic->iReply = uOffset;
1916	break;
1917	}
1918	case BUSLOGICCOMMAND_INITIALIZE_MAILBOX:
1919	{
1920	PRequestInitMbx pRequest = (PRequestInitMbx)pBusLogic->aCommandBuffer;
1921
1922	pBusLogic->fMbxIs24Bit = true;
1923	pBusLogic->cMailbox = pRequest->cMailbox;
1924	pBusLogic->GCPhysAddrMailboxOutgoingBase = (RTGCPHYS)ADDR_TO_U32(pRequest->aMailboxBaseAddr);
1925	/* The area for incoming mailboxes is right after the last entry of outgoing mailboxes. */
1926	pBusLogic->GCPhysAddrMailboxIncomingBase = pBusLogic->GCPhysAddrMailboxOutgoingBase + (pBusLogic->cMailbox * sizeof(Mailbox24));
1927
1928	Log(("GCPhysAddrMailboxOutgoingBase=%RGp\n", pBusLogic->GCPhysAddrMailboxOutgoingBase));
1929	Log(("GCPhysAddrMailboxIncomingBase=%RGp\n", pBusLogic->GCPhysAddrMailboxIncomingBase));
1930	Log(("cMailboxes=%u (24-bit mode)\n", pBusLogic->cMailbox));
1931	LogRel(("Initialized 24-bit mailbox, %d entries at %08x\n", pRequest->cMailbox, ADDR_TO_U32(pRequest->aMailboxBaseAddr)));
1932
1933	pBusLogic->regStatus &= ~BL_STAT_INREQ;
1934	pBusLogic->cbReplyParametersLeft = 0;
1935	break;
1936	}
1937	case BUSLOGICCOMMAND_INITIALIZE_EXTENDED_MAILBOX:
1938	{
1939	PRequestInitializeExtendedMailbox pRequest = (PRequestInitializeExtendedMailbox)pBusLogic->aCommandBuffer;
1940
1941	pBusLogic->fMbxIs24Bit = false;
1942	pBusLogic->cMailbox = pRequest->cMailbox;
1943	pBusLogic->GCPhysAddrMailboxOutgoingBase = (RTGCPHYS)pRequest->uMailboxBaseAddress;
1944	/* The area for incoming mailboxes is right after the last entry of outgoing mailboxes. */
1945	pBusLogic->GCPhysAddrMailboxIncomingBase = (RTGCPHYS)pRequest->uMailboxBaseAddress + (pBusLogic->cMailbox * sizeof(Mailbox32));
1946
1947	Log(("GCPhysAddrMailboxOutgoingBase=%RGp\n", pBusLogic->GCPhysAddrMailboxOutgoingBase));
1948	Log(("GCPhysAddrMailboxIncomingBase=%RGp\n", pBusLogic->GCPhysAddrMailboxIncomingBase));
1949	Log(("cMailboxes=%u (32-bit mode)\n", pBusLogic->cMailbox));
1950	LogRel(("Initialized 32-bit mailbox, %d entries at %08x\n", pRequest->cMailbox, pRequest->uMailboxBaseAddress));
1951
1952	pBusLogic->regStatus &= ~BL_STAT_INREQ;
1953	pBusLogic->cbReplyParametersLeft = 0;
1954	break;
1955	}
1956	case BUSLOGICCOMMAND_ENABLE_STRICT_ROUND_ROBIN_MODE:
1957	{
1958	if (pBusLogic->aCommandBuffer[0] == 0)
1959	pBusLogic->fStrictRoundRobinMode = false;
1960	else if (pBusLogic->aCommandBuffer[0] == 1)
1961	pBusLogic->fStrictRoundRobinMode = true;
1962	else
1963	AssertMsgFailed(("Invalid round robin mode %d\n", pBusLogic->aCommandBuffer[0]));
1964
1965	pBusLogic->cbReplyParametersLeft = 0;
1966	break;
1967	}
1968	case BUSLOGICCOMMAND_SET_CCB_FORMAT:
1969	{
1970	if (pBusLogic->aCommandBuffer[0] == 0)
1971	pBusLogic->fExtendedLunCCBFormat = false;
1972	else if (pBusLogic->aCommandBuffer[0] == 1)
1973	pBusLogic->fExtendedLunCCBFormat = true;
1974	else
1975	AssertMsgFailed(("Invalid CCB format %d\n", pBusLogic->aCommandBuffer[0]));
1976
1977	pBusLogic->cbReplyParametersLeft = 0;
1978	break;
1979	}
1980	case BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_0_TO_7:
1981	/* This is supposed to send TEST UNIT READY to each target/LUN.
1982	* We cheat and skip that, since we already know what's attached
1983	*/
1984	memset(pBusLogic->aReplyBuffer, 0, 8);
1985	for (int i = 0; i < 8; ++i)
1986	{
1987	if (pBusLogic->aDeviceStates[i].fPresent)
1988	pBusLogic->aReplyBuffer[i] = 1;
1989	}
1990	pBusLogic->aReplyBuffer[7] = 0; /* HA hardcoded at ID 7. */
1991	pBusLogic->cbReplyParametersLeft = 8;
1992	break;
1993	case BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_8_TO_15:
1994	/* See note about cheating above. */
1995	memset(pBusLogic->aReplyBuffer, 0, 8);
1996	for (int i = 0; i < 8; ++i)
1997	{
1998	if (pBusLogic->aDeviceStates[i + 8].fPresent)
1999	pBusLogic->aReplyBuffer[i] = 1;
2000	}
2001	pBusLogic->cbReplyParametersLeft = 8;
2002	break;
2003	case BUSLOGICCOMMAND_INQUIRE_TARGET_DEVICES:
2004	{
2005	/* Each bit which is set in the 16bit wide variable means a present device. */
2006	uint16_t u16TargetsPresentMask = 0;
2007
2008	for (uint8_t i = 0; i < RT_ELEMENTS(pBusLogic->aDeviceStates); i++)
2009	{
2010	if (pBusLogic->aDeviceStates[i].fPresent)
2011	u16TargetsPresentMask \|= (1 << i);
2012	}
2013	pBusLogic->aReplyBuffer[0] = (uint8_t)u16TargetsPresentMask;
2014	pBusLogic->aReplyBuffer[1] = (uint8_t)(u16TargetsPresentMask >> 8);
2015	pBusLogic->cbReplyParametersLeft = 2;
2016	break;
2017	}
2018	case BUSLOGICCOMMAND_INQUIRE_SYNCHRONOUS_PERIOD:
2019	{
2020	pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[0];
2021
2022	for (uint8_t i = 0; i < pBusLogic->cbReplyParametersLeft; i++)
2023	pBusLogic->aReplyBuffer[i] = 0; /** @todo Figure if we need something other here. It's not needed for the linux driver */
2024
2025	break;
2026	}
2027	case BUSLOGICCOMMAND_DISABLE_HOST_ADAPTER_INTERRUPT:
2028	{
2029	if (pBusLogic->aCommandBuffer[0] == 0)
2030	pBusLogic->fIRQEnabled = false;
2031	else
2032	pBusLogic->fIRQEnabled = true;
2033	/* No interrupt signaled regardless of enable/disable. */
2034	fSuppressIrq = true;
2035	break;
2036	}
2037	case BUSLOGICCOMMAND_ECHO_COMMAND_DATA:
2038	{
2039	pBusLogic->aReplyBuffer[0] = pBusLogic->aCommandBuffer[0];
2040	pBusLogic->cbReplyParametersLeft = 1;
2041	break;
2042	}
2043	case BUSLOGICCOMMAND_SET_PREEMPT_TIME_ON_BUS:
2044	{
2045	pBusLogic->cbReplyParametersLeft = 0;
2046	pBusLogic->LocalRam.structured.autoSCSIData.uBusOnDelay = pBusLogic->aCommandBuffer[0];
2047	Log(("Bus-on time: %d\n", pBusLogic->aCommandBuffer[0]));
2048	break;
2049	}
2050	case BUSLOGICCOMMAND_SET_TIME_OFF_BUS:
2051	{
2052	pBusLogic->cbReplyParametersLeft = 0;
2053	pBusLogic->LocalRam.structured.autoSCSIData.uBusOffDelay = pBusLogic->aCommandBuffer[0];
2054	Log(("Bus-off time: %d\n", pBusLogic->aCommandBuffer[0]));
2055	break;
2056	}
2057	case BUSLOGICCOMMAND_SET_BUS_TRANSFER_RATE:
2058	{
2059	pBusLogic->cbReplyParametersLeft = 0;
2060	pBusLogic->LocalRam.structured.autoSCSIData.uDMATransferRate = pBusLogic->aCommandBuffer[0];
2061	Log(("Bus transfer rate: %02X\n", pBusLogic->aCommandBuffer[0]));
2062	break;
2063	}
2064	case BUSLOGICCOMMAND_WRITE_BUSMASTER_CHIP_FIFO:
2065	{
2066	RTGCPHYS GCPhysFifoBuf;
2067	Addr24 addr;
2068
2069	pBusLogic->cbReplyParametersLeft = 0;
2070	addr.hi = pBusLogic->aCommandBuffer[0];
2071	addr.mid = pBusLogic->aCommandBuffer[1];
2072	addr.lo = pBusLogic->aCommandBuffer[2];
2073	GCPhysFifoBuf = (RTGCPHYS)ADDR_TO_U32(addr);
2074	Log(("Write busmaster FIFO at: %04X\n", ADDR_TO_U32(addr)));
2075	PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCPhysFifoBuf,
2076	&pBusLogic->LocalRam.u8View[64], 64);
2077	break;
2078	}
2079	case BUSLOGICCOMMAND_READ_BUSMASTER_CHIP_FIFO:
2080	{
2081	RTGCPHYS GCPhysFifoBuf;
2082	Addr24 addr;
2083
2084	pBusLogic->cbReplyParametersLeft = 0;
2085	addr.hi = pBusLogic->aCommandBuffer[0];
2086	addr.mid = pBusLogic->aCommandBuffer[1];
2087	addr.lo = pBusLogic->aCommandBuffer[2];
2088	GCPhysFifoBuf = (RTGCPHYS)ADDR_TO_U32(addr);
2089	Log(("Read busmaster FIFO at: %04X\n", ADDR_TO_U32(addr)));
2090	PDMDevHlpPCIPhysWrite(pBusLogic->CTX_SUFF(pDevIns), GCPhysFifoBuf,
2091	&pBusLogic->LocalRam.u8View[64], 64);
2092	break;
2093	}
2094	default:
2095	AssertMsgFailed(("Invalid command %#x\n", pBusLogic->uOperationCode));
2096	case BUSLOGICCOMMAND_EXT_BIOS_INFO:
2097	case BUSLOGICCOMMAND_UNLOCK_MAILBOX:
2098	/* Commands valid for Adaptec 154xC which we don't handle since
2099	* we pretend being 154xB compatible. Just mark the command as invalid.
2100	*/
2101	Log(("Command %#x not valid for this adapter\n", pBusLogic->uOperationCode));
2102	pBusLogic->cbReplyParametersLeft = 0;
2103	pBusLogic->regStatus \|= BL_STAT_CMDINV;
2104	break;
2105	case BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND: /* Should be handled already. */
2106	AssertMsgFailed(("Invalid mailbox execute state!\n"));
2107	}
2108
2109	Log(("uOperationCode=%#x, cbReplyParametersLeft=%d\n", pBusLogic->uOperationCode, pBusLogic->cbReplyParametersLeft));
2110
2111	/* Set the data in ready bit in the status register in case the command has a reply. */
2112	if (pBusLogic->cbReplyParametersLeft)
2113	pBusLogic->regStatus \|= BL_STAT_DIRRDY;
2114	else if (!pBusLogic->cbCommandParametersLeft)
2115	buslogicCommandComplete(pBusLogic, fSuppressIrq);
2116
2117	return rc;
2118	}
2119
2120	/**
2121	* Read a register from the BusLogic adapter.
2122	*
2123	* @returns VBox status code.
2124	* @param pBusLogic Pointer to the BusLogic instance data.
2125	* @param iRegister The index of the register to read.
2126	* @param pu32 Where to store the register content.
2127	*/
2128	static int buslogicRegisterRead(PBUSLOGIC pBusLogic, unsigned iRegister, uint32_t *pu32)
2129	{
2130	int rc = VINF_SUCCESS;
2131
2132	switch (iRegister)
2133	{
2134	case BUSLOGIC_REGISTER_STATUS:
2135	{
2136	*pu32 = pBusLogic->regStatus;
2137
2138	/* If the diagnostic active bit is set, we are in a guest-initiated
2139	* hard reset. If the guest reads the status register and waits for
2140	* the host adapter ready bit to be set, we terminate the reset right
2141	* away. However, guests may also expect the reset condition to clear
2142	* automatically after a period of time, in which case we can't show
2143	* the DIAG bit at all.
2144	*/
2145	if (pBusLogic->regStatus & BL_STAT_DACT)
2146	{
2147	uint64_t u64AccessTime = PDMDevHlpTMTimeVirtGetNano(pBusLogic->CTX_SUFF(pDevIns));
2148
2149	pBusLogic->regStatus &= ~BL_STAT_DACT;
2150	pBusLogic->regStatus \|= BL_STAT_HARDY;
2151
2152	if (u64AccessTime - pBusLogic->u64ResetTime > BUSLOGIC_RESET_DURATION_NS)
2153	{
2154	/* If reset already expired, let the guest see that right away. */
2155	*pu32 = pBusLogic->regStatus;
2156	pBusLogic->u64ResetTime = 0;
2157	}
2158	}
2159	break;
2160	}
2161	case BUSLOGIC_REGISTER_DATAIN:
2162	{
2163	if (pBusLogic->fUseLocalRam)
2164	*pu32 = pBusLogic->LocalRam.u8View[pBusLogic->iReply];
2165	else
2166	*pu32 = pBusLogic->aReplyBuffer[pBusLogic->iReply];
2167
2168	/* Careful about underflow - guest can read data register even if
2169	* no data is available.
2170	*/
2171	if (pBusLogic->cbReplyParametersLeft)
2172	{
2173	pBusLogic->iReply++;
2174	pBusLogic->cbReplyParametersLeft--;
2175	if (!pBusLogic->cbReplyParametersLeft)
2176	{
2177	/*
2178	* Reply finished, set command complete bit, unset data-in ready bit and
2179	* interrupt the guest if enabled.
2180	*/
2181	buslogicCommandComplete(pBusLogic, false);
2182	}
2183	}
2184	LogFlowFunc(("data=%02x, iReply=%d, cbReplyParametersLeft=%u\n", *pu32,
2185	pBusLogic->iReply, pBusLogic->cbReplyParametersLeft));
2186	break;
2187	}
2188	case BUSLOGIC_REGISTER_INTERRUPT:
2189	{
2190	*pu32 = pBusLogic->regInterrupt;
2191	break;
2192	}
2193	case BUSLOGIC_REGISTER_GEOMETRY:
2194	{
2195	*pu32 = pBusLogic->regGeometry;
2196	break;
2197	}
2198	default:
2199	*pu32 = UINT32_C(0xffffffff);
2200	}
2201
2202	Log2(("%s: pu32=%p:{%.*Rhxs} iRegister=%d rc=%Rrc\n",
2203	__FUNCTION__, pu32, 1, pu32, iRegister, rc));
2204
2205	return rc;
2206	}
2207
2208	/**
2209	* Write a value to a register.
2210	*
2211	* @returns VBox status code.
2212	* @param pBusLogic Pointer to the BusLogic instance data.
2213	* @param iRegister The index of the register to read.
2214	* @param uVal The value to write.
2215	*/
2216	static int buslogicRegisterWrite(PBUSLOGIC pBusLogic, unsigned iRegister, uint8_t uVal)
2217	{
2218	int rc = VINF_SUCCESS;
2219
2220	switch (iRegister)
2221	{
2222	case BUSLOGIC_REGISTER_CONTROL:
2223	{
2224	if ((uVal & BL_CTRL_RHARD) \|\| (uVal & BL_CTRL_RSOFT))
2225	{
2226	#ifdef IN_RING3
2227	bool fHardReset = !!(uVal & BL_CTRL_RHARD);
2228
2229	LogRel(("BusLogic: %s reset\n", fHardReset ? "hard" : "soft"));
2230	buslogicR3InitiateReset(pBusLogic, fHardReset);
2231	#else
2232	rc = VINF_IOM_R3_IOPORT_WRITE;
2233	#endif
2234	break;
2235	}
2236
2237	rc = PDMCritSectEnter(&pBusLogic->CritSectIntr, VINF_IOM_R3_IOPORT_WRITE);
2238	if (rc != VINF_SUCCESS)
2239	return rc;
2240
2241	#ifdef LOG_ENABLED
2242	uint32_t cMailboxesReady = ASMAtomicXchgU32(&pBusLogic->cInMailboxesReady, 0);
2243	Log(("%u incoming mailboxes were ready when this interrupt was cleared\n", cMailboxesReady));
2244	#endif
2245
2246	if (uVal & BL_CTRL_RINT)
2247	buslogicClearInterrupt(pBusLogic);
2248
2249	PDMCritSectLeave(&pBusLogic->CritSectIntr);
2250
2251	break;
2252	}
2253	case BUSLOGIC_REGISTER_COMMAND:
2254	{
2255	/* Fast path for mailbox execution command. */
2256	if ((uVal == BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND) && (pBusLogic->uOperationCode == 0xff))
2257	{
2258	/* If there are no mailboxes configured, don't even try to do anything. */
2259	if (pBusLogic->cMailbox)
2260	{
2261	ASMAtomicIncU32(&pBusLogic->cMailboxesReady);
2262	if (!ASMAtomicXchgBool(&pBusLogic->fNotificationSent, true))
2263	{
2264	/* Send new notification to the queue. */
2265	PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pBusLogic->CTX_SUFF(pNotifierQueue));
2266	AssertMsg(pItem, ("Allocating item for queue failed\n"));
2267	PDMQueueInsert(pBusLogic->CTX_SUFF(pNotifierQueue), (PPDMQUEUEITEMCORE)pItem);
2268	}
2269	}
2270
2271	return rc;
2272	}
2273
2274	/*
2275	* Check if we are already fetch command parameters from the guest.
2276	* If not we initialize executing a new command.
2277	*/
2278	if (pBusLogic->uOperationCode == 0xff)
2279	{
2280	pBusLogic->uOperationCode = uVal;
2281	pBusLogic->iParameter = 0;
2282
2283	/* Mark host adapter as busy and clear the invalid status bit. */
2284	pBusLogic->regStatus &= ~(BL_STAT_HARDY \| BL_STAT_CMDINV);
2285
2286	/* Get the number of bytes for parameters from the command code. */
2287	switch (pBusLogic->uOperationCode)
2288	{
2289	case BUSLOGICCOMMAND_TEST_CMDC_INTERRUPT:
2290	case BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_LETTER:
2291	case BUSLOGICCOMMAND_INQUIRE_BOARD_ID:
2292	case BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_3RD_LETTER:
2293	case BUSLOGICCOMMAND_INQUIRE_PCI_HOST_ADAPTER_INFORMATION:
2294	case BUSLOGICCOMMAND_INQUIRE_CONFIGURATION:
2295	case BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_0_TO_7:
2296	case BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_8_TO_15:
2297	case BUSLOGICCOMMAND_INQUIRE_TARGET_DEVICES:
2298	pBusLogic->cbCommandParametersLeft = 0;
2299	break;
2300	case BUSLOGICCOMMAND_MODIFY_IO_ADDRESS:
2301	case BUSLOGICCOMMAND_INQUIRE_EXTENDED_SETUP_INFORMATION:
2302	case BUSLOGICCOMMAND_INQUIRE_SETUP_INFORMATION:
2303	case BUSLOGICCOMMAND_INQUIRE_HOST_ADAPTER_MODEL_NUMBER:
2304	case BUSLOGICCOMMAND_ENABLE_STRICT_ROUND_ROBIN_MODE:
2305	case BUSLOGICCOMMAND_SET_CCB_FORMAT:
2306	case BUSLOGICCOMMAND_INQUIRE_SYNCHRONOUS_PERIOD:
2307	case BUSLOGICCOMMAND_DISABLE_HOST_ADAPTER_INTERRUPT:
2308	case BUSLOGICCOMMAND_ECHO_COMMAND_DATA:
2309	case BUSLOGICCOMMAND_SET_PREEMPT_TIME_ON_BUS:
2310	case BUSLOGICCOMMAND_SET_TIME_OFF_BUS:
2311	case BUSLOGICCOMMAND_SET_BUS_TRANSFER_RATE:
2312	pBusLogic->cbCommandParametersLeft = 1;
2313	break;
2314	case BUSLOGICCOMMAND_FETCH_HOST_ADAPTER_LOCAL_RAM:
2315	pBusLogic->cbCommandParametersLeft = 2;
2316	break;
2317	case BUSLOGICCOMMAND_READ_BUSMASTER_CHIP_FIFO:
2318	case BUSLOGICCOMMAND_WRITE_BUSMASTER_CHIP_FIFO:
2319	pBusLogic->cbCommandParametersLeft = 3;
2320	break;
2321	case BUSLOGICCOMMAND_SET_SCSI_SELECTION_TIMEOUT:
2322	pBusLogic->cbCommandParametersLeft = 4;
2323	break;
2324	case BUSLOGICCOMMAND_INITIALIZE_MAILBOX:
2325	pBusLogic->cbCommandParametersLeft = sizeof(RequestInitMbx);
2326	break;
2327	case BUSLOGICCOMMAND_INITIALIZE_EXTENDED_MAILBOX:
2328	pBusLogic->cbCommandParametersLeft = sizeof(RequestInitializeExtendedMailbox);
2329	break;
2330	case BUSLOGICCOMMAND_SET_ADAPTER_OPTIONS:
2331	/* There must be at least one byte following this command. */
2332	pBusLogic->cbCommandParametersLeft = 1;
2333	break;
2334	case BUSLOGICCOMMAND_EXECUTE_SCSI_COMMAND:
2335	/* 12 bytes + variable-length CDB. */
2336	pBusLogic->cbCommandParametersLeft = 12;
2337	break;
2338	case BUSLOGICCOMMAND_EXT_BIOS_INFO:
2339	case BUSLOGICCOMMAND_UNLOCK_MAILBOX:
2340	/* Invalid commands. */
2341	pBusLogic->cbCommandParametersLeft = 0;
2342	break;
2343	case BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND: /* Should not come here anymore. */
2344	default:
2345	AssertMsgFailed(("Invalid operation code %#x\n", uVal));
2346	}
2347	}
2348	else
2349	{
2350	#ifndef IN_RING3
2351	/* This command must be executed in R3 as it rehooks the ISA I/O port. */
2352	if (pBusLogic->uOperationCode == BUSLOGICCOMMAND_MODIFY_IO_ADDRESS)
2353	{
2354	rc = VINF_IOM_R3_IOPORT_WRITE;
2355	break;
2356	}
2357	#endif
2358	/*
2359	* The real adapter would set the Command register busy bit in the status register.
2360	* The guest has to wait until it is unset.
2361	* We don't need to do it because the guest does not continue execution while we are in this
2362	* function.
2363	*/
2364	pBusLogic->aCommandBuffer[pBusLogic->iParameter] = uVal;
2365	pBusLogic->iParameter++;
2366	pBusLogic->cbCommandParametersLeft--;
2367	}
2368
2369	/* Start execution of command if there are no parameters left. */
2370	if (!pBusLogic->cbCommandParametersLeft)
2371	{
2372	rc = buslogicProcessCommand(pBusLogic);
2373	AssertMsgRC(rc, ("Processing command failed rc=%Rrc\n", rc));
2374	}
2375	break;
2376	}
2377
2378	/* On BusLogic adapters, the interrupt and geometry registers are R/W.
2379	* That is different from Adaptec 154x where those are read only.
2380	*/
2381	case BUSLOGIC_REGISTER_INTERRUPT:
2382	pBusLogic->regInterrupt = uVal;
2383	break;
2384
2385	case BUSLOGIC_REGISTER_GEOMETRY:
2386	pBusLogic->regGeometry = uVal;
2387	break;
2388
2389	default:
2390	AssertMsgFailed(("Register not available\n"));
2391	rc = VERR_IOM_IOPORT_UNUSED;
2392	}
2393
2394	return rc;
2395	}
2396
2397	/**
2398	* Memory mapped I/O Handler for read operations.
2399	*
2400	* @returns VBox status code.
2401	*
2402	* @param pDevIns The device instance.
2403	* @param pvUser User argument.
2404	* @param GCPhysAddr Physical address (in GC) where the read starts.
2405	* @param pv Where to store the result.
2406	* @param cb Number of bytes read.
2407	*/
2408	PDMBOTHCBDECL(int) buslogicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2409	{
2410	/* the linux driver does not make use of the MMIO area. */
2411	AssertMsgFailed(("MMIO Read\n"));
2412	return VINF_SUCCESS;
2413	}
2414
2415	/**
2416	* Memory mapped I/O Handler for write operations.
2417	*
2418	* @returns VBox status code.
2419	*
2420	* @param pDevIns The device instance.
2421	* @param pvUser User argument.
2422	* @param GCPhysAddr Physical address (in GC) where the read starts.
2423	* @param pv Where to fetch the result.
2424	* @param cb Number of bytes to write.
2425	*/
2426	PDMBOTHCBDECL(int) buslogicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
2427	{
2428	/* the linux driver does not make use of the MMIO area. */
2429	AssertMsgFailed(("MMIO Write\n"));
2430	return VINF_SUCCESS;
2431	}
2432
2433	/**
2434	* Port I/O Handler for IN operations.
2435	*
2436	* @returns VBox status code.
2437	*
2438	* @param pDevIns The device instance.
2439	* @param pvUser User argument.
2440	* @param uPort Port number used for the IN operation.
2441	* @param pu32 Where to store the result.
2442	* @param cb Number of bytes read.
2443	*/
2444	PDMBOTHCBDECL(int) buslogicIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
2445	{
2446	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2447	unsigned iRegister = Port % 4;
2448
2449	Assert(cb == 1);
2450
2451	return buslogicRegisterRead(pBusLogic, iRegister, pu32);
2452	}
2453
2454	/**
2455	* Port I/O Handler for OUT operations.
2456	*
2457	* @returns VBox status code.
2458	*
2459	* @param pDevIns The device instance.
2460	* @param pvUser User argument.
2461	* @param uPort Port number used for the IN operation.
2462	* @param u32 The value to output.
2463	* @param cb The value size in bytes.
2464	*/
2465	PDMBOTHCBDECL(int) buslogicIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2466	{
2467	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2468	int rc = VINF_SUCCESS;
2469	unsigned iRegister = Port % 4;
2470	uint8_t uVal = (uint8_t)u32;
2471
2472	Assert(cb == 1);
2473
2474	rc = buslogicRegisterWrite(pBusLogic, iRegister, (uint8_t)uVal);
2475
2476	Log2(("#%d %s: pvUser=%#p cb=%d u32=%#x Port=%#x rc=%Rrc\n",
2477	pDevIns->iInstance, __FUNCTION__, pvUser, cb, u32, Port, rc));
2478
2479	return rc;
2480	}
2481
2482	#ifdef IN_RING3
2483
2484	static int buslogicR3PrepareBIOSSCSIRequest(PBUSLOGIC pBusLogic)
2485	{
2486	int rc;
2487	PBUSLOGICTASKSTATE pTaskState;
2488	uint32_t uTargetDevice;
2489
2490	rc = RTMemCacheAllocEx(pBusLogic->hTaskCache, (void **)&pTaskState);
2491	AssertMsgRCReturn(rc, ("Getting task from cache failed rc=%Rrc\n", rc), rc);
2492
2493	pTaskState->fBIOS = true;
2494
2495	rc = vboxscsiSetupRequest(&pBusLogic->VBoxSCSI, &pTaskState->PDMScsiRequest, &uTargetDevice);
2496	AssertMsgRCReturn(rc, ("Setting up SCSI request failed rc=%Rrc\n", rc), rc);
2497
2498	pTaskState->PDMScsiRequest.pvUser = pTaskState;
2499
2500	pTaskState->CTX_SUFF(pTargetDevice) = &pBusLogic->aDeviceStates[uTargetDevice];
2501
2502	if (!pTaskState->CTX_SUFF(pTargetDevice)->fPresent)
2503	{
2504	/* Device is not present. */
2505	AssertMsg(pTaskState->PDMScsiRequest.pbCDB[0] == SCSI_INQUIRY,
2506	("Device is not present but command is not inquiry\n"));
2507
2508	SCSIINQUIRYDATA ScsiInquiryData;
2509
2510	memset(&ScsiInquiryData, 0, sizeof(SCSIINQUIRYDATA));
2511	ScsiInquiryData.u5PeripheralDeviceType = SCSI_INQUIRY_DATA_PERIPHERAL_DEVICE_TYPE_UNKNOWN;
2512	ScsiInquiryData.u3PeripheralQualifier = SCSI_INQUIRY_DATA_PERIPHERAL_QUALIFIER_NOT_CONNECTED_NOT_SUPPORTED;
2513
2514	memcpy(pBusLogic->VBoxSCSI.pbBuf, &ScsiInquiryData, 5);
2515
2516	rc = vboxscsiRequestFinished(&pBusLogic->VBoxSCSI, &pTaskState->PDMScsiRequest, SCSI_STATUS_OK);
2517	AssertMsgRCReturn(rc, ("Finishing BIOS SCSI request failed rc=%Rrc\n", rc), rc);
2518
2519	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
2520	}
2521	else
2522	{
2523	LogFlowFunc(("before increment %u\n", pTaskState->CTX_SUFF(pTargetDevice)->cOutstandingRequests));
2524	ASMAtomicIncU32(&pTaskState->CTX_SUFF(pTargetDevice)->cOutstandingRequests);
2525	LogFlowFunc(("after increment %u\n", pTaskState->CTX_SUFF(pTargetDevice)->cOutstandingRequests));
2526
2527	rc = pTaskState->CTX_SUFF(pTargetDevice)->pDrvSCSIConnector->pfnSCSIRequestSend(pTaskState->CTX_SUFF(pTargetDevice)->pDrvSCSIConnector,
2528	&pTaskState->PDMScsiRequest);
2529	AssertMsgRC(rc, ("Sending request to SCSI layer failed rc=%Rrc\n", rc));
2530	}
2531
2532	return rc;
2533	}
2534
2535
2536	/**
2537	* Port I/O Handler for IN operations - BIOS port.
2538	*
2539	* @returns VBox status code.
2540	*
2541	* @param pDevIns The device instance.
2542	* @param pvUser User argument.
2543	* @param uPort Port number used for the IN operation.
2544	* @param pu32 Where to store the result.
2545	* @param cb Number of bytes read.
2546	*/
2547	static DECLCALLBACK(int) buslogicR3BiosIoPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
2548	{
2549	int rc;
2550	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2551
2552	Assert(cb == 1);
2553
2554	rc = vboxscsiReadRegister(&pBusLogic->VBoxSCSI, (Port - BUSLOGIC_BIOS_IO_PORT), pu32);
2555
2556	//Log2(("%s: pu32=%p:{%.*Rhxs} iRegister=%d rc=%Rrc\n",
2557	// __FUNCTION__, pu32, 1, pu32, (Port - BUSLOGIC_BIOS_IO_PORT), rc));
2558
2559	return rc;
2560	}
2561
2562	/**
2563	* Port I/O Handler for OUT operations - BIOS port.
2564	*
2565	* @returns VBox status code.
2566	*
2567	* @param pDevIns The device instance.
2568	* @param pvUser User argument.
2569	* @param uPort Port number used for the IN operation.
2570	* @param u32 The value to output.
2571	* @param cb The value size in bytes.
2572	*/
2573	static DECLCALLBACK(int) buslogicR3BiosIoPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2574	{
2575	int rc;
2576	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2577
2578	Log2(("#%d %s: pvUser=%#p cb=%d u32=%#x Port=%#x\n",
2579	pDevIns->iInstance, __FUNCTION__, pvUser, cb, u32, Port));
2580
2581	/*
2582	* If there is already a request form the BIOS pending ignore this write
2583	* because it should not happen.
2584	*/
2585	if (ASMAtomicReadBool(&pThis->fBiosReqPending))
2586	return VINF_SUCCESS;
2587
2588	Assert(cb == 1);
2589
2590	rc = vboxscsiWriteRegister(&pThis->VBoxSCSI, (Port - BUSLOGIC_BIOS_IO_PORT), (uint8_t)u32);
2591	if (rc == VERR_MORE_DATA)
2592	{
2593	ASMAtomicXchgBool(&pThis->fBiosReqPending, true);
2594	/* Send a notifier to the PDM queue that there are pending requests. */
2595	PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pNotifierQueue));
2596	AssertMsg(pItem, ("Allocating item for queue failed\n"));
2597	PDMQueueInsert(pThis->CTX_SUFF(pNotifierQueue), (PPDMQUEUEITEMCORE)pItem);
2598	rc = VINF_SUCCESS;
2599	}
2600	else if (RT_FAILURE(rc))
2601	AssertMsgFailed(("Writing BIOS register failed %Rrc\n", rc));
2602
2603	return VINF_SUCCESS;
2604	}
2605
2606	/**
2607	* Port I/O Handler for primary port range OUT string operations.
2608	* @see FNIOMIOPORTOUTSTRING for details.
2609	*/
2610	static DECLCALLBACK(int) buslogicR3BiosIoPortWriteStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port,
2611	uint8_t const pbSrc, uint32_t pcTransfers, unsigned cb)
2612	{
2613	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2614	Log2(("#%d %s: pvUser=%#p cb=%d Port=%#x\n", pDevIns->iInstance, __FUNCTION__, pvUser, cb, Port));
2615
2616	/*
2617	* If there is already a request form the BIOS pending ignore this write
2618	* because it should not happen.
2619	*/
2620	if (ASMAtomicReadBool(&pThis->fBiosReqPending))
2621	return VINF_SUCCESS;
2622
2623	int rc = vboxscsiWriteString(pDevIns, &pThis->VBoxSCSI, (Port - BUSLOGIC_BIOS_IO_PORT), pbSrc, pcTransfers, cb);
2624	if (rc == VERR_MORE_DATA)
2625	{
2626	ASMAtomicXchgBool(&pThis->fBiosReqPending, true);
2627	/* Send a notifier to the PDM queue that there are pending requests. */
2628	PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pNotifierQueue));
2629	AssertMsg(pItem, ("Allocating item for queue failed\n"));
2630	PDMQueueInsert(pThis->CTX_SUFF(pNotifierQueue), (PPDMQUEUEITEMCORE)pItem);
2631	}
2632	else if (RT_FAILURE(rc))
2633	AssertMsgFailed(("Writing BIOS register failed %Rrc\n", rc));
2634
2635	return VINF_SUCCESS;
2636	}
2637
2638	/**
2639	* Port I/O Handler for primary port range IN string operations.
2640	* @see FNIOMIOPORTINSTRING for details.
2641	*/
2642	static DECLCALLBACK(int) buslogicR3BiosIoPortReadStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port,
2643	uint8_t pbDst, uint32_t pcTransfers, unsigned cb)
2644	{
2645	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2646	LogFlowFunc(("#%d %s: pvUser=%#p cb=%d Port=%#x\n", pDevIns->iInstance, __FUNCTION__, pvUser, cb, Port));
2647
2648	return vboxscsiReadString(pDevIns, &pBusLogic->VBoxSCSI, (Port - BUSLOGIC_BIOS_IO_PORT),
2649	pbDst, pcTransfers, cb);
2650	}
2651
2652	/**
2653	* Update the ISA I/O range.
2654	*
2655	* @returns nothing.
2656	* @param pBusLogic Pointer to the BusLogic device instance.
2657	* @param uBaseCode Encoded ISA I/O base; only low 3 bits are used.
2658	*/
2659	static int buslogicR3RegisterISARange(PBUSLOGIC pBusLogic, uint8_t uBaseCode)
2660	{
2661	uint8_t uCode = uBaseCode & MAX_ISA_BASE;
2662	uint16_t uNewBase = g_aISABases[uCode];
2663	int rc = VINF_SUCCESS;
2664
2665	LogFlowFunc(("ISA I/O code %02X, new base %X\n", uBaseCode, uNewBase));
2666
2667	/* Check if the same port range is already registered. */
2668	if (uNewBase != pBusLogic->IOISABase)
2669	{
2670	/* Unregister the old range, if any. */
2671	if (pBusLogic->IOISABase)
2672	rc = PDMDevHlpIOPortDeregister(pBusLogic->CTX_SUFF(pDevIns), pBusLogic->IOISABase, 4);
2673
2674	if (RT_SUCCESS(rc))
2675	{
2676	pBusLogic->IOISABase = 0; /* First mark as unregistered. */
2677	pBusLogic->uISABaseCode = ISA_BASE_DISABLED;
2678
2679	if (uNewBase)
2680	{
2681	/* Register the new range if requested. */
2682	rc = PDMDevHlpIOPortRegister(pBusLogic->CTX_SUFF(pDevIns), uNewBase, 4, NULL,
2683	buslogicIOPortWrite, buslogicIOPortRead,
2684	NULL, NULL,
2685	"BusLogic ISA");
2686	if (RT_SUCCESS(rc))
2687	{
2688	pBusLogic->IOISABase = uNewBase;
2689	pBusLogic->uISABaseCode = uCode;
2690	}
2691	}
2692	}
2693	if (RT_SUCCESS(rc))
2694	{
2695	if (uNewBase)
2696	{
2697	Log(("ISA I/O base: %x\n", uNewBase));
2698	LogRel(("BusLogic: ISA I/O base: %x\n", uNewBase));
2699	}
2700	else
2701	{
2702	Log(("Disabling ISA I/O ports.\n"));
2703	LogRel(("BusLogic: ISA I/O disabled\n"));
2704	}
2705	}
2706
2707	}
2708	return rc;
2709	}
2710
2711	static void buslogicR3WarningDiskFull(PPDMDEVINS pDevIns)
2712	{
2713	int rc;
2714	LogRel(("BusLogic#%d: Host disk full\n", pDevIns->iInstance));
2715	rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND \| VMSETRTERR_FLAGS_NO_WAIT, "DevBusLogic_DISKFULL",
2716	N_("Host system reported disk full. VM execution is suspended. You can resume after freeing some space"));
2717	AssertRC(rc);
2718	}
2719
2720	static void buslogicR3WarningFileTooBig(PPDMDEVINS pDevIns)
2721	{
2722	int rc;
2723	LogRel(("BusLogic#%d: File too big\n", pDevIns->iInstance));
2724	rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND \| VMSETRTERR_FLAGS_NO_WAIT, "DevBusLogic_FILETOOBIG",
2725	N_("Host system reported that the file size limit of the host file system has been exceeded. VM execution is suspended. You need to move your virtual hard disk to a filesystem which allows bigger files"));
2726	AssertRC(rc);
2727	}
2728
2729	static void buslogicR3WarningISCSI(PPDMDEVINS pDevIns)
2730	{
2731	int rc;
2732	LogRel(("BusLogic#%d: iSCSI target unavailable\n", pDevIns->iInstance));
2733	rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND \| VMSETRTERR_FLAGS_NO_WAIT, "DevBusLogic_ISCSIDOWN",
2734	N_("The iSCSI target has stopped responding. VM execution is suspended. You can resume when it is available again"));
2735	AssertRC(rc);
2736	}
2737
2738	static void buslogicR3WarningUnknown(PPDMDEVINS pDevIns, int rc)
2739	{
2740	int rc2;
2741	LogRel(("BusLogic#%d: Unknown but recoverable error has occurred (rc=%Rrc)\n", pDevIns->iInstance, rc));
2742	rc2 = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND \| VMSETRTERR_FLAGS_NO_WAIT, "DevBusLogic_UNKNOWN",
2743	N_("An unknown but recoverable I/O error has occurred (rc=%Rrc). VM execution is suspended. You can resume when the error is fixed"), rc);
2744	AssertRC(rc2);
2745	}
2746
2747	static void buslogicR3RedoSetWarning(PBUSLOGIC pThis, int rc)
2748	{
2749	if (rc == VERR_DISK_FULL)
2750	buslogicR3WarningDiskFull(pThis->CTX_SUFF(pDevIns));
2751	else if (rc == VERR_FILE_TOO_BIG)
2752	buslogicR3WarningFileTooBig(pThis->CTX_SUFF(pDevIns));
2753	else if (rc == VERR_BROKEN_PIPE \|\| rc == VERR_NET_CONNECTION_REFUSED)
2754	{
2755	/* iSCSI connection abort (first error) or failure to reestablish
2756	* connection (second error). Pause VM. On resume we'll retry. */
2757	buslogicR3WarningISCSI(pThis->CTX_SUFF(pDevIns));
2758	}
2759	else if (rc != VERR_VD_DEK_MISSING)
2760	buslogicR3WarningUnknown(pThis->CTX_SUFF(pDevIns), rc);
2761	}
2762
2763
2764	static DECLCALLBACK(int) buslogicR3MmioMap(PPCIDEVICE pPciDev, /unsigned/ int iRegion,
2765	RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
2766	{
2767	PPDMDEVINS pDevIns = pPciDev->pDevIns;
2768	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2769	int rc = VINF_SUCCESS;
2770
2771	Log2(("%s: registering MMIO area at GCPhysAddr=%RGp cb=%u\n", __FUNCTION__, GCPhysAddress, cb));
2772
2773	Assert(cb >= 32);
2774
2775	if (enmType == PCI_ADDRESS_SPACE_MEM)
2776	{
2777	/* We use the assigned size here, because we currently only support page aligned MMIO ranges. */
2778	rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /pvUser/,
2779	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
2780	buslogicMMIOWrite, buslogicMMIORead, "BusLogic MMIO");
2781	if (RT_FAILURE(rc))
2782	return rc;
2783
2784	if (pThis->fR0Enabled)
2785	{
2786	rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /pvUser/,
2787	"buslogicMMIOWrite", "buslogicMMIORead");
2788	if (RT_FAILURE(rc))
2789	return rc;
2790	}
2791
2792	if (pThis->fGCEnabled)
2793	{
2794	rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /pvUser/,
2795	"buslogicMMIOWrite", "buslogicMMIORead");
2796	if (RT_FAILURE(rc))
2797	return rc;
2798	}
2799
2800	pThis->MMIOBase = GCPhysAddress;
2801	}
2802	else if (enmType == PCI_ADDRESS_SPACE_IO)
2803	{
2804	rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, 32,
2805	NULL, buslogicIOPortWrite, buslogicIOPortRead, NULL, NULL, "BusLogic PCI");
2806	if (RT_FAILURE(rc))
2807	return rc;
2808
2809	if (pThis->fR0Enabled)
2810	{
2811	rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, 32,
2812	0, "buslogicIOPortWrite", "buslogicIOPortRead", NULL, NULL, "BusLogic PCI");
2813	if (RT_FAILURE(rc))
2814	return rc;
2815	}
2816
2817	if (pThis->fGCEnabled)
2818	{
2819	rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, 32,
2820	0, "buslogicIOPortWrite", "buslogicIOPortRead", NULL, NULL, "BusLogic PCI");
2821	if (RT_FAILURE(rc))
2822	return rc;
2823	}
2824
2825	pThis->IOPortBase = (RTIOPORT)GCPhysAddress;
2826	}
2827	else
2828	AssertMsgFailed(("Invalid enmType=%d\n", enmType));
2829
2830	return rc;
2831	}
2832
2833	static DECLCALLBACK(int) buslogicR3DeviceSCSIRequestCompleted(PPDMISCSIPORT pInterface, PPDMSCSIREQUEST pSCSIRequest,
2834	int rcCompletion, bool fRedo, int rcReq)
2835	{
2836	int rc;
2837	PBUSLOGICTASKSTATE pTaskState = (PBUSLOGICTASKSTATE)pSCSIRequest->pvUser;
2838	PBUSLOGICDEVICE pBusLogicDevice = pTaskState->CTX_SUFF(pTargetDevice);
2839	PBUSLOGIC pBusLogic = pBusLogicDevice->CTX_SUFF(pBusLogic);
2840
2841	LogFlowFunc(("before decrement %u\n", pBusLogicDevice->cOutstandingRequests));
2842	ASMAtomicDecU32(&pBusLogicDevice->cOutstandingRequests);
2843	LogFlowFunc(("after decrement %u\n", pBusLogicDevice->cOutstandingRequests));
2844
2845	if (fRedo)
2846	{
2847	if (!pTaskState->fBIOS)
2848	{
2849	buslogicR3DataBufferFree(pTaskState);
2850
2851	if (pTaskState->pbSenseBuffer)
2852	buslogicR3SenseBufferFree(pTaskState, false /* fCopy */);
2853	}
2854
2855	/* Add to the list. */
2856	do
2857	{
2858	pTaskState->pRedoNext = ASMAtomicReadPtrT(&pBusLogic->pTasksRedoHead, PBUSLOGICTASKSTATE);
2859	} while (!ASMAtomicCmpXchgPtr(&pBusLogic->pTasksRedoHead, pTaskState, pTaskState->pRedoNext));
2860
2861	/* Suspend the VM if not done already. */
2862	if (!ASMAtomicXchgBool(&pBusLogic->fRedo, true))
2863	buslogicR3RedoSetWarning(pBusLogic, rcReq);
2864	}
2865	else
2866	{
2867	if (pTaskState->fBIOS)
2868	{
2869	rc = vboxscsiRequestFinished(&pBusLogic->VBoxSCSI, pSCSIRequest, rcCompletion);
2870	AssertMsgRC(rc, ("Finishing BIOS SCSI request failed rc=%Rrc\n", rc));
2871	}
2872	else
2873	{
2874	buslogicR3DataBufferFree(pTaskState);
2875
2876	if (pTaskState->pbSenseBuffer)
2877	buslogicR3SenseBufferFree(pTaskState, (rcCompletion != SCSI_STATUS_OK));
2878
2879	if (rcCompletion == SCSI_STATUS_OK)
2880	buslogicR3SendIncomingMailbox(pBusLogic, pTaskState,
2881	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_CMD_COMPLETED,
2882	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_OPERATION_GOOD,
2883	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITHOUT_ERROR);
2884	else if (rcCompletion == SCSI_STATUS_CHECK_CONDITION)
2885	buslogicR3SendIncomingMailbox(pBusLogic, pTaskState,
2886	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_CMD_COMPLETED,
2887	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_CHECK_CONDITION,
2888	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITH_ERROR);
2889	else
2890	AssertMsgFailed(("invalid completion status %d\n", rcCompletion));
2891	}
2892	#ifdef LOG_ENABLED
2893	buslogicR3DumpCCBInfo(&pTaskState->CommandControlBlockGuest, pTaskState->fIs24Bit);
2894	#endif
2895
2896	/* Remove task from the cache. */
2897	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
2898	}
2899
2900	if (pBusLogicDevice->cOutstandingRequests == 0 && pBusLogic->fSignalIdle)
2901	PDMDevHlpAsyncNotificationCompleted(pBusLogic->pDevInsR3);
2902
2903	return VINF_SUCCESS;
2904	}
2905
2906	static DECLCALLBACK(int) buslogicR3QueryDeviceLocation(PPDMISCSIPORT pInterface, const char **ppcszController,
2907	uint32_t piInstance, uint32_t piLUN)
2908	{
2909	PBUSLOGICDEVICE pBusLogicDevice = PDMISCSIPORT_2_PBUSLOGICDEVICE(pInterface);
2910	PPDMDEVINS pDevIns = pBusLogicDevice->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);
2911
2912	AssertPtrReturn(ppcszController, VERR_INVALID_POINTER);
2913	AssertPtrReturn(piInstance, VERR_INVALID_POINTER);
2914	AssertPtrReturn(piLUN, VERR_INVALID_POINTER);
2915
2916	*ppcszController = pDevIns->pReg->szName;
2917	*piInstance = pDevIns->iInstance;
2918	*piLUN = pBusLogicDevice->iLUN;
2919
2920	return VINF_SUCCESS;
2921	}
2922
2923	static int buslogicR3DeviceSCSIRequestSetup(PBUSLOGIC pBusLogic, PBUSLOGICTASKSTATE pTaskState)
2924	{
2925	int rc = VINF_SUCCESS;
2926	uint8_t uTargetIdCCB;
2927	PBUSLOGICDEVICE pTargetDevice;
2928
2929	/* Fetch the CCB from guest memory. */
2930	/** @todo How much do we really have to read? */
2931	RTGCPHYS GCPhysAddrCCB = (RTGCPHYS)pTaskState->MailboxGuest.u32PhysAddrCCB;
2932	PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrCCB,
2933	&pTaskState->CommandControlBlockGuest, sizeof(CCB32));
2934
2935	uTargetIdCCB = pTaskState->fIs24Bit ? pTaskState->CommandControlBlockGuest.o.uTargetId : pTaskState->CommandControlBlockGuest.n.uTargetId;
2936	if (RT_LIKELY(uTargetIdCCB < RT_ELEMENTS(pBusLogic->aDeviceStates)))
2937	{
2938	pTargetDevice = &pBusLogic->aDeviceStates[uTargetIdCCB];
2939	pTaskState->CTX_SUFF(pTargetDevice) = pTargetDevice;
2940
2941	#ifdef LOG_ENABLED
2942	buslogicR3DumpCCBInfo(&pTaskState->CommandControlBlockGuest, pTaskState->fIs24Bit);
2943	#endif
2944
2945	/* Alloc required buffers. */
2946	rc = buslogicR3DataBufferAlloc(pTaskState);
2947	AssertMsgRC(rc, ("Alloc failed rc=%Rrc\n", rc));
2948
2949	rc = buslogicR3SenseBufferAlloc(pTaskState);
2950	AssertMsgRC(rc, ("Mapping sense buffer failed rc=%Rrc\n", rc));
2951
2952	/* Check if device is present on bus. If not return error immediately and don't process this further. */
2953	if (!pBusLogic->aDeviceStates[uTargetIdCCB].fPresent)
2954	{
2955	buslogicR3DataBufferFree(pTaskState);
2956
2957	if (pTaskState->pbSenseBuffer)
2958	buslogicR3SenseBufferFree(pTaskState, true);
2959
2960	buslogicR3SendIncomingMailbox(pBusLogic, pTaskState,
2961	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_SCSI_SELECTION_TIMEOUT,
2962	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_OPERATION_GOOD,
2963	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITH_ERROR);
2964
2965	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
2966	}
2967	else
2968	{
2969	/* Setup SCSI request. */
2970	pTaskState->PDMScsiRequest.uLogicalUnit = pTaskState->fIs24Bit ? pTaskState->CommandControlBlockGuest.o.uLogicalUnit
2971	: pTaskState->CommandControlBlockGuest.n.uLogicalUnit;
2972
2973	if (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_UNKNOWN)
2974	pTaskState->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_UNKNOWN;
2975	else if (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_IN)
2976	pTaskState->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_FROM_DEVICE;
2977	else if (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_OUT)
2978	pTaskState->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_TO_DEVICE;
2979	else if (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_NO_DATA)
2980	pTaskState->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_NONE;
2981	else
2982	AssertMsgFailed(("Invalid data direction type %d\n", pTaskState->CommandControlBlockGuest.c.uDataDirection));
2983
2984	pTaskState->PDMScsiRequest.cbCDB = pTaskState->CommandControlBlockGuest.c.cbCDB;
2985	pTaskState->PDMScsiRequest.pbCDB = pTaskState->CommandControlBlockGuest.c.abCDB;
2986	if (pTaskState->DataSeg.cbSeg)
2987	{
2988	pTaskState->PDMScsiRequest.cbScatterGather = pTaskState->DataSeg.cbSeg;
2989	pTaskState->PDMScsiRequest.cScatterGatherEntries = 1;
2990	pTaskState->PDMScsiRequest.paScatterGatherHead = &pTaskState->DataSeg;
2991	}
2992	else
2993	{
2994	pTaskState->PDMScsiRequest.cbScatterGather = 0;
2995	pTaskState->PDMScsiRequest.cScatterGatherEntries = 0;
2996	pTaskState->PDMScsiRequest.paScatterGatherHead = NULL;
2997	}
2998	pTaskState->PDMScsiRequest.cbSenseBuffer = buslogicR3ConvertSenseBufferLength(pTaskState->CommandControlBlockGuest.c.cbSenseData);
2999	pTaskState->PDMScsiRequest.pbSenseBuffer = pTaskState->pbSenseBuffer;
3000	pTaskState->PDMScsiRequest.pvUser = pTaskState;
3001
3002	ASMAtomicIncU32(&pTargetDevice->cOutstandingRequests);
3003	rc = pTargetDevice->pDrvSCSIConnector->pfnSCSIRequestSend(pTargetDevice->pDrvSCSIConnector, &pTaskState->PDMScsiRequest);
3004	AssertMsgRC(rc, ("Sending request to SCSI layer failed rc=%Rrc\n", rc));
3005	}
3006	}
3007	else
3008	{
3009	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
3010
3011	buslogicR3SendIncomingMailbox(pBusLogic, pTaskState,
3012	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_INVALID_COMMAND_PARAMETER,
3013	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_OPERATION_GOOD,
3014	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITH_ERROR);
3015	}
3016
3017	return rc;
3018	}
3019
3020	static int buslogicR3DeviceSCSIRequestAbort(PBUSLOGIC pBusLogic, PBUSLOGICTASKSTATE pTaskState)
3021	{
3022	int rc = VINF_SUCCESS;
3023	uint8_t uTargetIdCCB;
3024	PBUSLOGICDEVICE pTargetDevice;
3025	RTGCPHYS GCPhysAddrCCB = (RTGCPHYS)pTaskState->MailboxGuest.u32PhysAddrCCB;
3026
3027	PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrCCB,
3028	&pTaskState->CommandControlBlockGuest, sizeof(CCB32));
3029
3030	uTargetIdCCB = pTaskState->fIs24Bit ? pTaskState->CommandControlBlockGuest.o.uTargetId : pTaskState->CommandControlBlockGuest.n.uTargetId;
3031	if (RT_LIKELY(uTargetIdCCB < RT_ELEMENTS(pBusLogic->aDeviceStates)))
3032	{
3033	pTargetDevice = &pBusLogic->aDeviceStates[uTargetIdCCB];
3034	pTaskState->CTX_SUFF(pTargetDevice) = pTargetDevice;
3035
3036	buslogicR3SendIncomingMailbox(pBusLogic, pTaskState,
3037	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_ABORT_QUEUE_GENERATED,
3038	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_OPERATION_GOOD,
3039	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_ABORTED_NOT_FOUND);
3040
3041	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
3042	}
3043	else
3044	{
3045	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
3046
3047	buslogicR3SendIncomingMailbox(pBusLogic, pTaskState,
3048	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_INVALID_COMMAND_PARAMETER,
3049	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_OPERATION_GOOD,
3050	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITH_ERROR);
3051	}
3052
3053	return rc;
3054	}
3055
3056	/**
3057	* Read a mailbox from guest memory. Convert 24-bit mailboxes to
3058	* 32-bit format.
3059	*
3060	* @returns Mailbox guest physical address.
3061	* @param pBusLogic Pointer to the BusLogic instance data.
3062	* @param pTaskStat Pointer to the task state being set up.
3063	*/
3064	static RTGCPHYS buslogicR3ReadOutgoingMailbox(PBUSLOGIC pBusLogic, PBUSLOGICTASKSTATE pTaskState)
3065	{
3066	RTGCPHYS GCMailbox;
3067
3068	if (pBusLogic->fMbxIs24Bit)
3069	{
3070	Mailbox24 Mbx24;
3071
3072	GCMailbox = pBusLogic->GCPhysAddrMailboxOutgoingBase + (pBusLogic->uMailboxOutgoingPositionCurrent * sizeof(Mailbox24));
3073	PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCMailbox, &Mbx24, sizeof(Mailbox24));
3074	pTaskState->MailboxGuest.u32PhysAddrCCB = ADDR_TO_U32(Mbx24.aPhysAddrCCB);
3075	pTaskState->MailboxGuest.u.out.uActionCode = Mbx24.uCmdState;
3076	}
3077	else
3078	{
3079	GCMailbox = pBusLogic->GCPhysAddrMailboxOutgoingBase + (pBusLogic->uMailboxOutgoingPositionCurrent * sizeof(Mailbox32));
3080	PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCMailbox, &pTaskState->MailboxGuest, sizeof(Mailbox32));
3081	}
3082
3083	return GCMailbox;
3084	}
3085
3086	/**
3087	* Read mailbox from the guest and execute command.
3088	*
3089	* @returns VBox status code.
3090	* @param pBusLogic Pointer to the BusLogic instance data.
3091	*/
3092	static int buslogicR3ProcessMailboxNext(PBUSLOGIC pBusLogic)
3093	{
3094	PBUSLOGICTASKSTATE pTaskState = NULL;
3095	RTGCPHYS GCPhysAddrMailboxCurrent;
3096	int rc;
3097
3098	rc = RTMemCacheAllocEx(pBusLogic->hTaskCache, (void **)&pTaskState);
3099	AssertMsgReturn(RT_SUCCESS(rc) && (pTaskState != NULL), ("Failed to get task state from cache\n"), rc);
3100
3101	pTaskState->fBIOS = false;
3102	pTaskState->fIs24Bit = pBusLogic->fMbxIs24Bit;
3103	pTaskState->cbSGEntry = pBusLogic->fMbxIs24Bit ? sizeof(SGE24) : sizeof(SGE32);
3104
3105	if (!pBusLogic->fStrictRoundRobinMode)
3106	{
3107	/* Search for a filled mailbox - stop if we have scanned all mailboxes. */
3108	uint8_t uMailboxPosCur = pBusLogic->uMailboxOutgoingPositionCurrent;
3109
3110	do
3111	{
3112	/* Fetch mailbox from guest memory. */
3113	GCPhysAddrMailboxCurrent = buslogicR3ReadOutgoingMailbox(pBusLogic,pTaskState);
3114
3115	/* Check the next mailbox. */
3116	buslogicR3OutgoingMailboxAdvance(pBusLogic);
3117	} while ( pTaskState->MailboxGuest.u.out.uActionCode == BUSLOGIC_MAILBOX_OUTGOING_ACTION_FREE
3118	&& uMailboxPosCur != pBusLogic->uMailboxOutgoingPositionCurrent);
3119	}
3120	else
3121	{
3122	/* Fetch mailbox from guest memory. */
3123	GCPhysAddrMailboxCurrent = buslogicR3ReadOutgoingMailbox(pBusLogic,pTaskState);
3124	}
3125
3126	/*
3127	* Check if the mailbox is actually loaded.
3128	* It might be possible that the guest notified us without
3129	* a loaded mailbox. Do nothing in that case but leave a
3130	* log entry.
3131	*/
3132	if (pTaskState->MailboxGuest.u.out.uActionCode == BUSLOGIC_MAILBOX_OUTGOING_ACTION_FREE)
3133	{
3134	Log(("No loaded mailbox left\n"));
3135	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
3136	return VERR_NO_DATA;
3137	}
3138
3139	LogFlow(("Got loaded mailbox at slot %u, CCB phys %RGp\n", pBusLogic->uMailboxOutgoingPositionCurrent, (RTGCPHYS)pTaskState->MailboxGuest.u32PhysAddrCCB));
3140	#ifdef LOG_ENABLED
3141	buslogicR3DumpMailboxInfo(&pTaskState->MailboxGuest, true);
3142	#endif
3143
3144	/* We got the mailbox, mark it as free in the guest. */
3145	uint8_t uActionCode = BUSLOGIC_MAILBOX_OUTGOING_ACTION_FREE;
3146	unsigned uCodeOffs = pTaskState->fIs24Bit ? RT_OFFSETOF(Mailbox24, uCmdState) : RT_OFFSETOF(Mailbox32, u.out.uActionCode);
3147	PDMDevHlpPCIPhysWrite(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrMailboxCurrent + uCodeOffs, &uActionCode, sizeof(uActionCode));
3148
3149	if (pTaskState->MailboxGuest.u.out.uActionCode == BUSLOGIC_MAILBOX_OUTGOING_ACTION_START_COMMAND)
3150	rc = buslogicR3DeviceSCSIRequestSetup(pBusLogic, pTaskState);
3151	else if (pTaskState->MailboxGuest.u.out.uActionCode == BUSLOGIC_MAILBOX_OUTGOING_ACTION_ABORT_COMMAND)
3152	{
3153	LogFlow(("Aborting mailbox\n"));
3154	rc = buslogicR3DeviceSCSIRequestAbort(pBusLogic, pTaskState);
3155	}
3156	else
3157	AssertMsgFailed(("Invalid outgoing mailbox action code %u\n", pTaskState->MailboxGuest.u.out.uActionCode));
3158
3159	AssertRC(rc);
3160
3161	/* Advance to the next mailbox. */
3162	if (pBusLogic->fStrictRoundRobinMode)
3163	buslogicR3OutgoingMailboxAdvance(pBusLogic);
3164
3165	return rc;
3166	}
3167
3168	/**
3169	* Transmit queue consumer
3170	* Queue a new async task.
3171	*
3172	* @returns Success indicator.
3173	* If false the item will not be removed and the flushing will stop.
3174	* @param pDevIns The device instance.
3175	* @param pItem The item to consume. Upon return this item will be freed.
3176	*/
3177	static DECLCALLBACK(bool) buslogicR3NotifyQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
3178	{
3179	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3180
3181	int rc = SUPSemEventSignal(pThis->pSupDrvSession, pThis->hEvtProcess);
3182	AssertRC(rc);
3183
3184	return true;
3185	}
3186
3187	/**
3188	* Kicks the controller to process pending tasks after the VM was resumed
3189	* or loaded from a saved state.
3190	*
3191	* @returns nothing.
3192	* @param pThis The BusLogic device instance.
3193	*/
3194	static void buslogicR3Kick(PBUSLOGIC pThis)
3195	{
3196	if (pThis->fRedo)
3197	{
3198	pThis->fRedo = false;
3199	if (pThis->VBoxSCSI.fBusy)
3200	{
3201
3202	/* The BIOS had a request active when we got suspended. Resume it. */
3203	int rc = buslogicR3PrepareBIOSSCSIRequest(pThis);
3204	AssertRC(rc);
3205	}
3206	else
3207	{
3208	/* Queue all pending tasks again. */
3209	PBUSLOGICTASKSTATE pTaskState = pThis->pTasksRedoHead;
3210
3211	pThis->pTasksRedoHead = NULL;
3212
3213	while (pTaskState)
3214	{
3215	PBUSLOGICTASKSTATE pCur = pTaskState;
3216
3217	int rc = buslogicR3DeviceSCSIRequestSetup(pThis, pCur);
3218	AssertRC(rc);
3219
3220	pTaskState = pTaskState->pRedoNext;
3221	}
3222	}
3223	}
3224	}
3225
3226	/** @callback_method_impl{FNSSMDEVLIVEEXEC} */
3227	static DECLCALLBACK(int) buslogicR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
3228	{
3229	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3230
3231	/* Save the device config. */
3232	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDeviceStates); i++)
3233	SSMR3PutBool(pSSM, pThis->aDeviceStates[i].fPresent);
3234
3235	return VINF_SSM_DONT_CALL_AGAIN;
3236	}
3237
3238	/** @callback_method_impl{FNSSMDEVSAVEEXEC} */
3239	static DECLCALLBACK(int) buslogicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3240	{
3241	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3242
3243	/* Every device first. */
3244	for (unsigned i = 0; i < RT_ELEMENTS(pBusLogic->aDeviceStates); i++)
3245	{
3246	PBUSLOGICDEVICE pDevice = &pBusLogic->aDeviceStates[i];
3247
3248	AssertMsg(!pDevice->cOutstandingRequests,
3249	("There are still outstanding requests on this device\n"));
3250	SSMR3PutBool(pSSM, pDevice->fPresent);
3251	SSMR3PutU32(pSSM, pDevice->cOutstandingRequests);
3252	}
3253	/* Now the main device state. */
3254	SSMR3PutU8 (pSSM, pBusLogic->regStatus);
3255	SSMR3PutU8 (pSSM, pBusLogic->regInterrupt);
3256	SSMR3PutU8 (pSSM, pBusLogic->regGeometry);
3257	SSMR3PutMem (pSSM, &pBusLogic->LocalRam, sizeof(pBusLogic->LocalRam));
3258	SSMR3PutU8 (pSSM, pBusLogic->uOperationCode);
3259	SSMR3PutMem (pSSM, &pBusLogic->aCommandBuffer, sizeof(pBusLogic->aCommandBuffer));
3260	SSMR3PutU8 (pSSM, pBusLogic->iParameter);
3261	SSMR3PutU8 (pSSM, pBusLogic->cbCommandParametersLeft);
3262	SSMR3PutBool (pSSM, pBusLogic->fUseLocalRam);
3263	SSMR3PutMem (pSSM, pBusLogic->aReplyBuffer, sizeof(pBusLogic->aReplyBuffer));
3264	SSMR3PutU8 (pSSM, pBusLogic->iReply);
3265	SSMR3PutU8 (pSSM, pBusLogic->cbReplyParametersLeft);
3266	SSMR3PutBool (pSSM, pBusLogic->fIRQEnabled);
3267	SSMR3PutU8 (pSSM, pBusLogic->uISABaseCode);
3268	SSMR3PutU32 (pSSM, pBusLogic->cMailbox);
3269	SSMR3PutBool (pSSM, pBusLogic->fMbxIs24Bit);
3270	SSMR3PutGCPhys(pSSM, pBusLogic->GCPhysAddrMailboxOutgoingBase);
3271	SSMR3PutU32 (pSSM, pBusLogic->uMailboxOutgoingPositionCurrent);
3272	SSMR3PutU32 (pSSM, pBusLogic->cMailboxesReady);
3273	SSMR3PutBool (pSSM, pBusLogic->fNotificationSent);
3274	SSMR3PutGCPhys(pSSM, pBusLogic->GCPhysAddrMailboxIncomingBase);
3275	SSMR3PutU32 (pSSM, pBusLogic->uMailboxIncomingPositionCurrent);
3276	SSMR3PutBool (pSSM, pBusLogic->fStrictRoundRobinMode);
3277	SSMR3PutBool (pSSM, pBusLogic->fExtendedLunCCBFormat);
3278
3279	vboxscsiR3SaveExec(&pBusLogic->VBoxSCSI, pSSM);
3280
3281	/*
3282	* Save the physical addresses of the command control blocks of still pending tasks.
3283	* They are processed again on resume.
3284	*
3285	* The number of pending tasks needs to be determined first.
3286	*/
3287	uint32_t cTasks = 0;
3288
3289	PBUSLOGICTASKSTATE pTaskState = pBusLogic->pTasksRedoHead;
3290	if (pBusLogic->fRedo)
3291	{
3292	while (pTaskState)
3293	{
3294	cTasks++;
3295	pTaskState = pTaskState->pRedoNext;
3296	}
3297	}
3298	SSMR3PutU32(pSSM, cTasks);
3299
3300	/* Write the address of every task now. */
3301	pTaskState = pBusLogic->pTasksRedoHead;
3302	while (pTaskState)
3303	{
3304	SSMR3PutU32(pSSM, pTaskState->MailboxGuest.u32PhysAddrCCB);
3305	pTaskState = pTaskState->pRedoNext;
3306	}
3307
3308	return SSMR3PutU32(pSSM, ~0);
3309	}
3310
3311	/** @callback_method_impl{FNSSMDEVLOADDONE} */
3312	static DECLCALLBACK(int) buslogicR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3313	{
3314	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3315
3316	buslogicR3RegisterISARange(pThis, pThis->uISABaseCode);
3317	buslogicR3Kick(pThis);
3318	return VINF_SUCCESS;
3319	}
3320
3321	/** @callback_method_impl{FNSSMDEVLOADEXEC} */
3322	static DECLCALLBACK(int) buslogicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3323	{
3324	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3325	int rc = VINF_SUCCESS;
3326
3327	/* We support saved states only from this and older versions. */
3328	if (uVersion > BUSLOGIC_SAVED_STATE_MINOR_VERSION)
3329	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3330
3331	/* Every device first. */
3332	for (unsigned i = 0; i < RT_ELEMENTS(pBusLogic->aDeviceStates); i++)
3333	{
3334	PBUSLOGICDEVICE pDevice = &pBusLogic->aDeviceStates[i];
3335
3336	AssertMsg(!pDevice->cOutstandingRequests,
3337	("There are still outstanding requests on this device\n"));
3338	bool fPresent;
3339	rc = SSMR3GetBool(pSSM, &fPresent);
3340	AssertRCReturn(rc, rc);
3341	if (pDevice->fPresent != fPresent)
3342	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Target %u config mismatch: config=%RTbool state=%RTbool"), i, pDevice->fPresent, fPresent);
3343
3344	if (uPass == SSM_PASS_FINAL)
3345	SSMR3GetU32(pSSM, (uint32_t *)&pDevice->cOutstandingRequests);
3346	}
3347
3348	if (uPass != SSM_PASS_FINAL)
3349	return VINF_SUCCESS;
3350
3351	/* Now the main device state. */
3352	SSMR3GetU8 (pSSM, (uint8_t *)&pBusLogic->regStatus);
3353	SSMR3GetU8 (pSSM, (uint8_t *)&pBusLogic->regInterrupt);
3354	SSMR3GetU8 (pSSM, (uint8_t *)&pBusLogic->regGeometry);
3355	SSMR3GetMem (pSSM, &pBusLogic->LocalRam, sizeof(pBusLogic->LocalRam));
3356	SSMR3GetU8 (pSSM, &pBusLogic->uOperationCode);
3357	if (uVersion > BUSLOGIC_SAVED_STATE_MINOR_PRE_CMDBUF_RESIZE)
3358	SSMR3GetMem (pSSM, &pBusLogic->aCommandBuffer, sizeof(pBusLogic->aCommandBuffer));
3359	else
3360	SSMR3GetMem (pSSM, &pBusLogic->aCommandBuffer, BUSLOGIC_COMMAND_SIZE_OLD);
3361	SSMR3GetU8 (pSSM, &pBusLogic->iParameter);
3362	SSMR3GetU8 (pSSM, &pBusLogic->cbCommandParametersLeft);
3363	SSMR3GetBool (pSSM, &pBusLogic->fUseLocalRam);
3364	SSMR3GetMem (pSSM, pBusLogic->aReplyBuffer, sizeof(pBusLogic->aReplyBuffer));
3365	SSMR3GetU8 (pSSM, &pBusLogic->iReply);
3366	SSMR3GetU8 (pSSM, &pBusLogic->cbReplyParametersLeft);
3367	SSMR3GetBool (pSSM, &pBusLogic->fIRQEnabled);
3368	SSMR3GetU8 (pSSM, &pBusLogic->uISABaseCode);
3369	SSMR3GetU32 (pSSM, &pBusLogic->cMailbox);
3370	if (uVersion > BUSLOGIC_SAVED_STATE_MINOR_PRE_24BIT_MBOX)
3371	SSMR3GetBool (pSSM, &pBusLogic->fMbxIs24Bit);
3372	SSMR3GetGCPhys(pSSM, &pBusLogic->GCPhysAddrMailboxOutgoingBase);
3373	SSMR3GetU32 (pSSM, &pBusLogic->uMailboxOutgoingPositionCurrent);
3374	SSMR3GetU32 (pSSM, (uint32_t *)&pBusLogic->cMailboxesReady);
3375	SSMR3GetBool (pSSM, (bool *)&pBusLogic->fNotificationSent);
3376	SSMR3GetGCPhys(pSSM, &pBusLogic->GCPhysAddrMailboxIncomingBase);
3377	SSMR3GetU32 (pSSM, &pBusLogic->uMailboxIncomingPositionCurrent);
3378	SSMR3GetBool (pSSM, &pBusLogic->fStrictRoundRobinMode);
3379	SSMR3GetBool (pSSM, &pBusLogic->fExtendedLunCCBFormat);
3380
3381	rc = vboxscsiR3LoadExec(&pBusLogic->VBoxSCSI, pSSM);
3382	if (RT_FAILURE(rc))
3383	{
3384	LogRel(("BusLogic: Failed to restore BIOS state: %Rrc.\n", rc));
3385	return PDMDEV_SET_ERROR(pDevIns, rc,
3386	N_("BusLogic: Failed to restore BIOS state\n"));
3387	}
3388
3389	if (pBusLogic->VBoxSCSI.fBusy)
3390	pBusLogic->fRedo = true;
3391
3392	if (uVersion > BUSLOGIC_SAVED_STATE_MINOR_PRE_ERROR_HANDLING)
3393	{
3394	/* Check if there are pending tasks saved. */
3395	uint32_t cTasks = 0;
3396
3397	SSMR3GetU32(pSSM, &cTasks);
3398
3399	if (cTasks)
3400	pBusLogic->fRedo = true;
3401
3402	for (uint32_t i = 0; i < cTasks; i++)
3403	{
3404	PBUSLOGICTASKSTATE pTaskState = (PBUSLOGICTASKSTATE)RTMemCacheAlloc(pBusLogic->hTaskCache);
3405	if (!pTaskState)
3406	{
3407	rc = VERR_NO_MEMORY;
3408	break;
3409	}
3410
3411	rc = SSMR3GetU32(pSSM, &pTaskState->MailboxGuest.u32PhysAddrCCB);
3412	if (RT_FAILURE(rc))
3413	{
3414	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
3415	break;
3416	}
3417
3418	/* Link into the list. */
3419	pTaskState->pRedoNext = pBusLogic->pTasksRedoHead;
3420	pBusLogic->pTasksRedoHead = pTaskState;
3421	}
3422	}
3423
3424	if (RT_SUCCESS(rc))
3425	{
3426	uint32_t u32;
3427	rc = SSMR3GetU32(pSSM, &u32);
3428	if (RT_SUCCESS(rc))
3429	AssertMsgReturn(u32 == ~0U, ("%#x\n", u32), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
3430	}
3431
3432	return rc;
3433	}
3434
3435	/**
3436	* Gets the pointer to the status LED of a device - called from the SCSI driver.
3437	*
3438	* @returns VBox status code.
3439	* @param pInterface Pointer to the interface structure containing the called function pointer.
3440	* @param iLUN The unit which status LED we desire. Always 0 here as the driver
3441	* doesn't know about other LUN's.
3442	* @param ppLed Where to store the LED pointer.
3443	*/
3444	static DECLCALLBACK(int) buslogicR3DeviceQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
3445	{
3446	PBUSLOGICDEVICE pDevice = PDMILEDPORTS_2_PBUSLOGICDEVICE(pInterface);
3447	if (iLUN == 0)
3448	{
3449	*ppLed = &pDevice->Led;
3450	Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
3451	return VINF_SUCCESS;
3452	}
3453	return VERR_PDM_LUN_NOT_FOUND;
3454	}
3455
3456	/**
3457	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
3458	*/
3459	static DECLCALLBACK(void ) buslogicR3DeviceQueryInterface(PPDMIBASE pInterface, const char pszIID)
3460	{
3461	PBUSLOGICDEVICE pDevice = PDMIBASE_2_PBUSLOGICDEVICE(pInterface);
3462	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevice->IBase);
3463	PDMIBASE_RETURN_INTERFACE(pszIID, PDMISCSIPORT, &pDevice->ISCSIPort);
3464	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pDevice->ILed);
3465	return NULL;
3466	}
3467
3468	/**
3469	* Gets the pointer to the status LED of a unit.
3470	*
3471	* @returns VBox status code.
3472	* @param pInterface Pointer to the interface structure containing the called function pointer.
3473	* @param iLUN The unit which status LED we desire.
3474	* @param ppLed Where to store the LED pointer.
3475	*/
3476	static DECLCALLBACK(int) buslogicR3StatusQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
3477	{
3478	PBUSLOGIC pBusLogic = PDMILEDPORTS_2_PBUSLOGIC(pInterface);
3479	if (iLUN < BUSLOGIC_MAX_DEVICES)
3480	{
3481	*ppLed = &pBusLogic->aDeviceStates[iLUN].Led;
3482	Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
3483	return VINF_SUCCESS;
3484	}
3485	return VERR_PDM_LUN_NOT_FOUND;
3486	}
3487
3488	/**
3489	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
3490	*/
3491	static DECLCALLBACK(void ) buslogicR3StatusQueryInterface(PPDMIBASE pInterface, const char pszIID)
3492	{
3493	PBUSLOGIC pThis = PDMIBASE_2_PBUSLOGIC(pInterface);
3494	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
3495	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
3496	return NULL;
3497	}
3498
3499	/**
3500	* The worker thread processing requests from the guest.
3501	*
3502	* @returns VBox status code.
3503	* @param pDevIns The device instance.
3504	* @param pThread The thread structure.
3505	*/
3506	static DECLCALLBACK(int) buslogicR3Worker(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3507	{
3508	PBUSLOGIC pThis = (PBUSLOGIC)pThread->pvUser;
3509	int rc = VINF_SUCCESS;
3510
3511	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3512	return VINF_SUCCESS;
3513
3514	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3515	{
3516	ASMAtomicWriteBool(&pThis->fWrkThreadSleeping, true);
3517	bool fNotificationSent = ASMAtomicXchgBool(&pThis->fNotificationSent, false);
3518	if (!fNotificationSent)
3519	{
3520	Assert(ASMAtomicReadBool(&pThis->fWrkThreadSleeping));
3521	rc = SUPSemEventWaitNoResume(pThis->pSupDrvSession, pThis->hEvtProcess, RT_INDEFINITE_WAIT);
3522	AssertLogRelMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
3523	if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
3524	break;
3525	LogFlowFunc(("Woken up with rc=%Rrc\n", rc));
3526	ASMAtomicWriteBool(&pThis->fNotificationSent, false);
3527	}
3528
3529	ASMAtomicWriteBool(&pThis->fWrkThreadSleeping, false);
3530
3531	/* Check whether there is a BIOS request pending and process it first. */
3532	if (ASMAtomicReadBool(&pThis->fBiosReqPending))
3533	{
3534	rc = buslogicR3PrepareBIOSSCSIRequest(pThis);
3535	AssertRC(rc);
3536	ASMAtomicXchgBool(&pThis->fBiosReqPending, false);
3537	}
3538	else
3539	{
3540	ASMAtomicXchgU32(&pThis->cMailboxesReady, 0); /** @todo Actually not required anymore but to stay compatible with older saved states. */
3541
3542	/* Process mailboxes. */
3543	do
3544	{
3545	rc = buslogicR3ProcessMailboxNext(pThis);
3546	AssertMsg(RT_SUCCESS(rc) \|\| rc == VERR_NO_DATA, ("Processing mailbox failed rc=%Rrc\n", rc));
3547	} while (RT_SUCCESS(rc));
3548	}
3549	} /* While running */
3550
3551	return VINF_SUCCESS;
3552	}
3553
3554
3555	/**
3556	* Unblock the worker thread so it can respond to a state change.
3557	*
3558	* @returns VBox status code.
3559	* @param pDevIns The device instance.
3560	* @param pThread The send thread.
3561	*/
3562	static DECLCALLBACK(int) buslogicR3WorkerWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3563	{
3564	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3565	return SUPSemEventSignal(pThis->pSupDrvSession, pThis->hEvtProcess);
3566	}
3567
3568	/**
3569	* BusLogic debugger info callback.
3570	*
3571	* @param pDevIns The device instance.
3572	* @param pHlp The output helpers.
3573	* @param pszArgs The arguments.
3574	*/
3575	static DECLCALLBACK(void) buslogicR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3576	{
3577	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3578	unsigned i;
3579	bool fVerbose = false;
3580
3581	/* Parse arguments. */
3582	if (pszArgs)
3583	fVerbose = strstr(pszArgs, "verbose") != NULL;
3584
3585	/* Show basic information. */
3586	pHlp->pfnPrintf(pHlp,
3587	"%s#%d: PCI I/O=%RTiop ISA I/O=%RTiop MMIO=%RGp IRQ=%u GC=%RTbool R0=%RTbool\n",
3588	pDevIns->pReg->szName,
3589	pDevIns->iInstance,
3590	pThis->IOPortBase, pThis->IOISABase, pThis->MMIOBase,
3591	PCIDevGetInterruptLine(&pThis->dev),
3592	!!pThis->fGCEnabled, !!pThis->fR0Enabled);
3593
3594	/* Print mailbox state. */
3595	if (pThis->regStatus & BL_STAT_INREQ)
3596	pHlp->pfnPrintf(pHlp, "Mailbox not initialized\n");
3597	else
3598	pHlp->pfnPrintf(pHlp, "%u-bit mailbox with %u entries at %RGp (%d LUN CCBs)\n",
3599	pThis->fMbxIs24Bit ? 24 : 32, pThis->cMailbox,
3600	pThis->GCPhysAddrMailboxOutgoingBase,
3601	pThis->fMbxIs24Bit ? 8 : pThis->fExtendedLunCCBFormat ? 64 : 8);
3602
3603	/* Print register contents. */
3604	pHlp->pfnPrintf(pHlp, "Registers: STAT=%02x INTR=%02x GEOM=%02x\n",
3605	pThis->regStatus, pThis->regInterrupt, pThis->regGeometry);
3606
3607	/* Print miscellaneous state. */
3608	pHlp->pfnPrintf(pHlp, "HAC interrupts: %s\n",
3609	pThis->fIRQEnabled ? "on" : "off");
3610
3611	/* Print the current command, if any. */
3612	if (pThis->uOperationCode != 0xff )
3613	pHlp->pfnPrintf(pHlp, "Current command: %02X\n", pThis->uOperationCode);
3614
3615	if (fVerbose && (pThis->regStatus & BL_STAT_INREQ) == 0)
3616	{
3617	RTGCPHYS GCMailbox;
3618
3619	/* Dump the mailbox contents. */
3620	if (pThis->fMbxIs24Bit)
3621	{
3622	Mailbox24 Mbx24;
3623
3624	/* Outgoing mailbox, 24-bit format. */
3625	GCMailbox = pThis->GCPhysAddrMailboxOutgoingBase;
3626	pHlp->pfnPrintf(pHlp, " Outgoing mailbox entries (24-bit) at %06X:\n", GCMailbox);
3627	for (i = 0; i < pThis->cMailbox; ++i)
3628	{
3629	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCMailbox, &Mbx24, sizeof(Mailbox24));
3630	pHlp->pfnPrintf(pHlp, " slot %03d: CCB at %06X action code %02X", i, ADDR_TO_U32(Mbx24.aPhysAddrCCB), Mbx24.uCmdState);
3631	pHlp->pfnPrintf(pHlp, "%s\n", pThis->uMailboxOutgoingPositionCurrent == i ? " *" : "");
3632	GCMailbox += sizeof(Mailbox24);
3633	}
3634
3635	/* Incoming mailbox, 24-bit format. */
3636	GCMailbox = pThis->GCPhysAddrMailboxOutgoingBase + (pThis->cMailbox * sizeof(Mailbox24));
3637	pHlp->pfnPrintf(pHlp, " Incoming mailbox entries (24-bit) at %06X:\n", GCMailbox);
3638	for (i = 0; i < pThis->cMailbox; ++i)
3639	{
3640	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCMailbox, &Mbx24, sizeof(Mailbox24));
3641	pHlp->pfnPrintf(pHlp, " slot %03d: CCB at %06X completion code %02X", i, ADDR_TO_U32(Mbx24.aPhysAddrCCB), Mbx24.uCmdState);
3642	pHlp->pfnPrintf(pHlp, "%s\n", pThis->uMailboxIncomingPositionCurrent == i ? " *" : "");
3643	GCMailbox += sizeof(Mailbox24);
3644	}
3645
3646	}
3647	else
3648	{
3649	Mailbox32 Mbx32;
3650
3651	/* Outgoing mailbox, 32-bit format. */
3652	GCMailbox = pThis->GCPhysAddrMailboxOutgoingBase;
3653	pHlp->pfnPrintf(pHlp, " Outgoing mailbox entries (32-bit) at %08X:\n", (uint32_t)GCMailbox);
3654	for (i = 0; i < pThis->cMailbox; ++i)
3655	{
3656	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCMailbox, &Mbx32, sizeof(Mailbox32));
3657	pHlp->pfnPrintf(pHlp, " slot %03d: CCB at %08X action code %02X", i, Mbx32.u32PhysAddrCCB, Mbx32.u.out.uActionCode);
3658	pHlp->pfnPrintf(pHlp, "%s\n", pThis->uMailboxOutgoingPositionCurrent == i ? " *" : "");
3659	GCMailbox += sizeof(Mailbox32);
3660	}
3661
3662	/* Incoming mailbox, 32-bit format. */
3663	GCMailbox = pThis->GCPhysAddrMailboxOutgoingBase + (pThis->cMailbox * sizeof(Mailbox32));
3664	pHlp->pfnPrintf(pHlp, " Outgoing mailbox entries (32-bit) at %08X:\n", (uint32_t)GCMailbox);
3665	for (i = 0; i < pThis->cMailbox; ++i)
3666	{
3667	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCMailbox, &Mbx32, sizeof(Mailbox32));
3668	pHlp->pfnPrintf(pHlp, " slot %03d: CCB at %08X completion code %02X BTSTAT %02X SDSTAT %02X", i,
3669	Mbx32.u32PhysAddrCCB, Mbx32.u.in.uCompletionCode, Mbx32.u.in.uHostAdapterStatus, Mbx32.u.in.uTargetDeviceStatus);
3670	pHlp->pfnPrintf(pHlp, "%s\n", pThis->uMailboxOutgoingPositionCurrent == i ? " *" : "");
3671	GCMailbox += sizeof(Mailbox32);
3672	}
3673
3674	}
3675	}
3676	}
3677
3678	/* -=-=-=-=- Helper -=-=-=-=- */
3679
3680	/**
3681	* Checks if all asynchronous I/O is finished.
3682	*
3683	* Used by buslogicR3Reset, buslogicR3Suspend and buslogicR3PowerOff.
3684	*
3685	* @returns true if quiesced, false if busy.
3686	* @param pDevIns The device instance.
3687	*/
3688	static bool buslogicR3AllAsyncIOIsFinished(PPDMDEVINS pDevIns)
3689	{
3690	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3691
3692	for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aDeviceStates); i++)
3693	{
3694	PBUSLOGICDEVICE pThisDevice = &pThis->aDeviceStates[i];
3695	if (pThisDevice->pDrvBase)
3696	{
3697	if (pThisDevice->cOutstandingRequests != 0)
3698	return false;
3699	}
3700	}
3701
3702	return true;
3703	}
3704
3705	/**
3706	* Callback employed by buslogicR3Suspend and buslogicR3PowerOff..
3707	*
3708	* @returns true if we've quiesced, false if we're still working.
3709	* @param pDevIns The device instance.
3710	*/
3711	static DECLCALLBACK(bool) buslogicR3IsAsyncSuspendOrPowerOffDone(PPDMDEVINS pDevIns)
3712	{
3713	if (!buslogicR3AllAsyncIOIsFinished(pDevIns))
3714	return false;
3715
3716	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3717	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
3718	return true;
3719	}
3720
3721	/**
3722	* Common worker for ahciR3Suspend and ahciR3PowerOff.
3723	*/
3724	static void buslogicR3SuspendOrPowerOff(PPDMDEVINS pDevIns, bool fPowerOff)
3725	{
3726	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3727
3728	ASMAtomicWriteBool(&pThis->fSignalIdle, true);
3729	if (!buslogicR3AllAsyncIOIsFinished(pDevIns))
3730	PDMDevHlpSetAsyncNotification(pDevIns, buslogicR3IsAsyncSuspendOrPowerOffDone);
3731	else
3732	{
3733	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
3734
3735	AssertMsg(!pThis->fNotificationSent, ("The PDM Queue should be empty at this point\n"));
3736
3737	if (pThis->fRedo)
3738	{
3739	if (fPowerOff)
3740	{
3741	/* Free tasks which would have been queued again on resume. */
3742	PBUSLOGICTASKSTATE pTaskState = pThis->pTasksRedoHead;
3743
3744	pThis->pTasksRedoHead = NULL;
3745
3746	while (pTaskState)
3747	{
3748	PBUSLOGICTASKSTATE pFree;
3749
3750	pFree = pTaskState;
3751	pTaskState = pTaskState->pRedoNext;
3752
3753	RTMemCacheFree(pThis->hTaskCache, pFree);
3754	}
3755	pThis->fRedo = false;
3756	}
3757	else if (pThis->VBoxSCSI.fBusy)
3758	{
3759	/* Destroy the task because the BIOS interface has all necessary information. */
3760	Assert(pThis->pTasksRedoHead->fBIOS);
3761	Assert(!pThis->pTasksRedoHead->pRedoNext);
3762
3763	RTMemCacheFree(pThis->hTaskCache, pThis->pTasksRedoHead);
3764	pThis->pTasksRedoHead = NULL;
3765	}
3766	}
3767	}
3768	}
3769
3770	/**
3771	* Suspend notification.
3772	*
3773	* @param pDevIns The device instance data.
3774	*/
3775	static DECLCALLBACK(void) buslogicR3Suspend(PPDMDEVINS pDevIns)
3776	{
3777	Log(("buslogicR3Suspend\n"));
3778	buslogicR3SuspendOrPowerOff(pDevIns, false /* fPoweroff */);
3779	}
3780
3781	/**
3782	* Resume notification.
3783	*
3784	* @param pDevIns The device instance data.
3785	*/
3786	static DECLCALLBACK(void) buslogicR3Resume(PPDMDEVINS pDevIns)
3787	{
3788	Log(("buslogicR3Resume\n"));
3789	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3790	buslogicR3Kick(pThis);
3791	}
3792
3793
3794	/**
3795	* Detach notification.
3796	*
3797	* One harddisk at one port has been unplugged.
3798	* The VM is suspended at this point.
3799	*
3800	* @param pDevIns The device instance.
3801	* @param iLUN The logical unit which is being detached.
3802	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3803	*/
3804	static DECLCALLBACK(void) buslogicR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3805	{
3806	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3807	PBUSLOGICDEVICE pDevice = &pThis->aDeviceStates[iLUN];
3808
3809	Log(("%s:\n", __FUNCTION__));
3810
3811	AssertMsg(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
3812	("BusLogic: Device does not support hotplugging\n"));
3813
3814	/*
3815	* Zero some important members.
3816	*/
3817	pDevice->pDrvBase = NULL;
3818	pDevice->fPresent = false;
3819	pDevice->pDrvSCSIConnector = NULL;
3820	}
3821
3822	/**
3823	* Attach command.
3824	*
3825	* This is called when we change block driver.
3826	*
3827	* @returns VBox status code.
3828	* @param pDevIns The device instance.
3829	* @param iLUN The logical unit which is being detached.
3830	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3831	*/
3832	static DECLCALLBACK(int) buslogicR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3833	{
3834	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3835	PBUSLOGICDEVICE pDevice = &pThis->aDeviceStates[iLUN];
3836	int rc;
3837
3838	AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
3839	("BusLogic: Device does not support hotplugging\n"),
3840	VERR_INVALID_PARAMETER);
3841
3842	/* the usual paranoia */
3843	AssertRelease(!pDevice->pDrvBase);
3844	AssertRelease(!pDevice->pDrvSCSIConnector);
3845	Assert(pDevice->iLUN == iLUN);
3846
3847	/*
3848	* Try attach the block device and get the interfaces,
3849	* required as well as optional.
3850	*/
3851	rc = PDMDevHlpDriverAttach(pDevIns, pDevice->iLUN, &pDevice->IBase, &pDevice->pDrvBase, NULL);
3852	if (RT_SUCCESS(rc))
3853	{
3854	/* Get SCSI connector interface. */
3855	pDevice->pDrvSCSIConnector = PDMIBASE_QUERY_INTERFACE(pDevice->pDrvBase, PDMISCSICONNECTOR);
3856	AssertMsgReturn(pDevice->pDrvSCSIConnector, ("Missing SCSI interface below\n"), VERR_PDM_MISSING_INTERFACE);
3857	pDevice->fPresent = true;
3858	}
3859	else
3860	AssertMsgFailed(("Failed to attach LUN#%d. rc=%Rrc\n", pDevice->iLUN, rc));
3861
3862	if (RT_FAILURE(rc))
3863	{
3864	pDevice->pDrvBase = NULL;
3865	pDevice->pDrvSCSIConnector = NULL;
3866	}
3867	return rc;
3868	}
3869
3870	/**
3871	* Callback employed by buslogicR3Reset.
3872	*
3873	* @returns true if we've quiesced, false if we're still working.
3874	* @param pDevIns The device instance.
3875	*/
3876	static DECLCALLBACK(bool) buslogicR3IsAsyncResetDone(PPDMDEVINS pDevIns)
3877	{
3878	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3879
3880	if (!buslogicR3AllAsyncIOIsFinished(pDevIns))
3881	return false;
3882	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
3883
3884	buslogicR3HwReset(pThis, true);
3885	return true;
3886	}
3887
3888	/**
3889	* @copydoc FNPDMDEVRESET
3890	*/
3891	static DECLCALLBACK(void) buslogicR3Reset(PPDMDEVINS pDevIns)
3892	{
3893	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3894
3895	ASMAtomicWriteBool(&pThis->fSignalIdle, true);
3896	if (!buslogicR3AllAsyncIOIsFinished(pDevIns))
3897	PDMDevHlpSetAsyncNotification(pDevIns, buslogicR3IsAsyncResetDone);
3898	else
3899	{
3900	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
3901	buslogicR3HwReset(pThis, true);
3902	}
3903	}
3904
3905	static DECLCALLBACK(void) buslogicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
3906	{
3907	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3908
3909	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3910	pThis->pNotifierQueueRC = PDMQueueRCPtr(pThis->pNotifierQueueR3);
3911
3912	for (uint32_t i = 0; i < BUSLOGIC_MAX_DEVICES; i++)
3913	{
3914	PBUSLOGICDEVICE pDevice = &pThis->aDeviceStates[i];
3915
3916	pDevice->pBusLogicRC = PDMINS_2_DATA_RCPTR(pDevIns);
3917	}
3918
3919	}
3920
3921	/**
3922	* Poweroff notification.
3923	*
3924	* @param pDevIns Pointer to the device instance
3925	*/
3926	static DECLCALLBACK(void) buslogicR3PowerOff(PPDMDEVINS pDevIns)
3927	{
3928	Log(("buslogicR3PowerOff\n"));
3929	buslogicR3SuspendOrPowerOff(pDevIns, true /* fPoweroff */);
3930	}
3931
3932	/**
3933	* Destroy a driver instance.
3934	*
3935	* Most VM resources are freed by the VM. This callback is provided so that any non-VM
3936	* resources can be freed correctly.
3937	*
3938	* @param pDevIns The device instance data.
3939	*/
3940	static DECLCALLBACK(int) buslogicR3Destruct(PPDMDEVINS pDevIns)
3941	{
3942	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3943	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
3944
3945	PDMR3CritSectDelete(&pThis->CritSectIntr);
3946
3947	/*
3948	* Free all tasks which are still hanging around
3949	* (Power off after the VM was suspended).
3950	*/
3951	if (pThis->fRedo)
3952	{
3953	/* Free tasks which would have been queued again on resume. */
3954	PBUSLOGICTASKSTATE pTaskState = pThis->pTasksRedoHead;
3955
3956	pThis->pTasksRedoHead = NULL;
3957
3958	while (pTaskState)
3959	{
3960	PBUSLOGICTASKSTATE pFree;
3961
3962	pFree = pTaskState;
3963	pTaskState = pTaskState->pRedoNext;
3964
3965	RTMemCacheFree(pThis->hTaskCache, pFree);
3966	}
3967	pThis->fRedo = false;
3968	}
3969
3970	if (pThis->hEvtProcess != NIL_SUPSEMEVENT)
3971	{
3972	SUPSemEventClose(pThis->pSupDrvSession, pThis->hEvtProcess);
3973	pThis->hEvtProcess = NIL_SUPSEMEVENT;
3974	}
3975
3976	int rc = RTMemCacheDestroy(pThis->hTaskCache);
3977	AssertMsgRC(rc, ("Destroying task cache failed rc=%Rrc\n", rc));
3978
3979	return rc;
3980	}
3981
3982	/**
3983	* @interface_method_impl{PDMDEVREG,pfnConstruct}
3984	*/
3985	static DECLCALLBACK(int) buslogicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
3986	{
3987	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3988	int rc = VINF_SUCCESS;
3989	bool fBootable = true;
3990	char achISACompat[16];
3991	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3992
3993	/*
3994	* Init instance data (do early because of constructor).
3995	*/
3996	pThis->hTaskCache = NIL_RTMEMCACHE;
3997	pThis->pDevInsR3 = pDevIns;
3998	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
3999	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
4000	pThis->IBase.pfnQueryInterface = buslogicR3StatusQueryInterface;
4001	pThis->ILeds.pfnQueryStatusLed = buslogicR3StatusQueryStatusLed;
4002
4003	PCIDevSetVendorId (&pThis->dev, 0x104b); /* BusLogic */
4004	PCIDevSetDeviceId (&pThis->dev, 0x1040); /* BT-958 */
4005	PCIDevSetCommand (&pThis->dev, 0x0003);
4006	PCIDevSetRevisionId (&pThis->dev, 0x01);
4007	PCIDevSetClassProg (&pThis->dev, 0x00); /* SCSI */
4008	PCIDevSetClassSub (&pThis->dev, 0x00); /* SCSI */
4009	PCIDevSetClassBase (&pThis->dev, 0x01); /* Mass storage */
4010	PCIDevSetBaseAddress (&pThis->dev, 0, true /IO/, false /Pref/, false /64-bit/, 0x00000000);
4011	PCIDevSetBaseAddress (&pThis->dev, 1, false /IO/, false /Pref/, false /64-bit/, 0x00000000);
4012	PCIDevSetSubSystemVendorId(&pThis->dev, 0x104b);
4013	PCIDevSetSubSystemId (&pThis->dev, 0x1040);
4014	PCIDevSetInterruptLine (&pThis->dev, 0x00);
4015	PCIDevSetInterruptPin (&pThis->dev, 0x01);
4016
4017	/*
4018	* Validate and read configuration.
4019	*/
4020	if (!CFGMR3AreValuesValid(pCfg,
4021	"GCEnabled\0"
4022	"R0Enabled\0"
4023	"Bootable\0"
4024	"ISACompat\0"))
4025	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4026	N_("BusLogic configuration error: unknown option specified"));
4027
4028	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &pThis->fGCEnabled, true);
4029	if (RT_FAILURE(rc))
4030	return PDMDEV_SET_ERROR(pDevIns, rc,
4031	N_("BusLogic configuration error: failed to read GCEnabled as boolean"));
4032	Log(("%s: fGCEnabled=%d\n", __FUNCTION__, pThis->fGCEnabled));
4033
4034	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, true);
4035	if (RT_FAILURE(rc))
4036	return PDMDEV_SET_ERROR(pDevIns, rc,
4037	N_("BusLogic configuration error: failed to read R0Enabled as boolean"));
4038	Log(("%s: fR0Enabled=%d\n", __FUNCTION__, pThis->fR0Enabled));
4039	rc = CFGMR3QueryBoolDef(pCfg, "Bootable", &fBootable, true);
4040	if (RT_FAILURE(rc))
4041	return PDMDEV_SET_ERROR(pDevIns, rc,
4042	N_("BusLogic configuration error: failed to read Bootable as boolean"));
4043	Log(("%s: fBootable=%RTbool\n", __FUNCTION__, fBootable));
4044
4045	/* Only the first instance defaults to having the ISA compatibility ports enabled. */
4046	if (iInstance == 0)
4047	rc = CFGMR3QueryStringDef(pCfg, "ISACompat", achISACompat, sizeof(achISACompat), "Alternate");
4048	else
4049	rc = CFGMR3QueryStringDef(pCfg, "ISACompat", achISACompat, sizeof(achISACompat), "Disabled");
4050	if (RT_FAILURE(rc))
4051	return PDMDEV_SET_ERROR(pDevIns, rc,
4052	N_("BusLogic configuration error: failed to read ISACompat as string"));
4053	Log(("%s: ISACompat=%s\n", __FUNCTION__, achISACompat));
4054
4055	/* Grok the ISACompat setting. */
4056	if (!strcmp(achISACompat, "Disabled"))
4057	pThis->uDefaultISABaseCode = ISA_BASE_DISABLED;
4058	else if (!strcmp(achISACompat, "Primary"))
4059	pThis->uDefaultISABaseCode = 0; /* I/O base at 330h. */
4060	else if (!strcmp(achISACompat, "Alternate"))
4061	pThis->uDefaultISABaseCode = 1; /* I/O base at 334h. */
4062	else
4063	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4064	N_("BusLogic configuration error: invalid ISACompat setting"));
4065
4066	/*
4067	* Register the PCI device and its I/O regions.
4068	*/
4069	rc = PDMDevHlpPCIRegister(pDevIns, &pThis->dev);
4070	if (RT_FAILURE(rc))
4071	return rc;
4072
4073	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 32, PCI_ADDRESS_SPACE_IO, buslogicR3MmioMap);
4074	if (RT_FAILURE(rc))
4075	return rc;
4076
4077	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 1, 32, PCI_ADDRESS_SPACE_MEM, buslogicR3MmioMap);
4078	if (RT_FAILURE(rc))
4079	return rc;
4080
4081	if (fBootable)
4082	{
4083	/* Register I/O port space for BIOS access. */
4084	rc = PDMDevHlpIOPortRegister(pDevIns, BUSLOGIC_BIOS_IO_PORT, 4, NULL,
4085	buslogicR3BiosIoPortWrite, buslogicR3BiosIoPortRead,
4086	buslogicR3BiosIoPortWriteStr, buslogicR3BiosIoPortReadStr,
4087	"BusLogic BIOS");
4088	if (RT_FAILURE(rc))
4089	return PDMDEV_SET_ERROR(pDevIns, rc, N_("BusLogic cannot register BIOS I/O handlers"));
4090	}
4091
4092	/* Set up the compatibility I/O range. */
4093	rc = buslogicR3RegisterISARange(pThis, pThis->uDefaultISABaseCode);
4094	if (RT_FAILURE(rc))
4095	return PDMDEV_SET_ERROR(pDevIns, rc, N_("BusLogic cannot register ISA I/O handlers"));
4096
4097	/* Initialize task cache. */
4098	rc = RTMemCacheCreate(&pThis->hTaskCache, sizeof(BUSLOGICTASKSTATE), 0, UINT32_MAX,
4099	NULL, NULL, NULL, 0);
4100	if (RT_FAILURE(rc))
4101	return PDMDEV_SET_ERROR(pDevIns, rc,
4102	N_("BusLogic: Failed to initialize task cache\n"));
4103
4104	/* Initialize task queue. */
4105	rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 5, 0,
4106	buslogicR3NotifyQueueConsumer, true, "BusLogicTask", &pThis->pNotifierQueueR3);
4107	if (RT_FAILURE(rc))
4108	return rc;
4109	pThis->pNotifierQueueR0 = PDMQueueR0Ptr(pThis->pNotifierQueueR3);
4110	pThis->pNotifierQueueRC = PDMQueueRCPtr(pThis->pNotifierQueueR3);
4111
4112	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSectIntr, RT_SRC_POS, "BusLogic-Intr#%u", pDevIns->iInstance);
4113	if (RT_FAILURE(rc))
4114	return PDMDEV_SET_ERROR(pDevIns, rc, N_("BusLogic: cannot create critical section"));
4115
4116	/*
4117	* Create event semaphore and worker thread.
4118	*/
4119	rc = SUPSemEventCreate(pThis->pSupDrvSession, &pThis->hEvtProcess);
4120	if (RT_FAILURE(rc))
4121	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
4122	N_("BusLogic: Failed to create SUP event semaphore"));
4123
4124	char szDevTag[20];
4125	RTStrPrintf(szDevTag, sizeof(szDevTag), "BUSLOGIC-%u", iInstance);
4126
4127	rc = PDMDevHlpThreadCreate(pDevIns, &pThis->pThreadWrk, pThis, buslogicR3Worker,
4128	buslogicR3WorkerWakeUp, 0, RTTHREADTYPE_IO, szDevTag);
4129	if (RT_FAILURE(rc))
4130	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
4131	N_("BusLogic: Failed to create worker thread %s"), szDevTag);
4132
4133	/* Initialize per device state. */
4134	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDeviceStates); i++)
4135	{
4136	char szName[24];
4137	PBUSLOGICDEVICE pDevice = &pThis->aDeviceStates[i];
4138
4139	RTStrPrintf(szName, sizeof(szName), "Device%u", i);
4140
4141	/* Initialize static parts of the device. */
4142	pDevice->iLUN = i;
4143	pDevice->pBusLogicR3 = pThis;
4144	pDevice->pBusLogicR0 = PDMINS_2_DATA_R0PTR(pDevIns);
4145	pDevice->pBusLogicRC = PDMINS_2_DATA_RCPTR(pDevIns);
4146	pDevice->Led.u32Magic = PDMLED_MAGIC;
4147	pDevice->IBase.pfnQueryInterface = buslogicR3DeviceQueryInterface;
4148	pDevice->ISCSIPort.pfnSCSIRequestCompleted = buslogicR3DeviceSCSIRequestCompleted;
4149	pDevice->ISCSIPort.pfnQueryDeviceLocation = buslogicR3QueryDeviceLocation;
4150	pDevice->ILed.pfnQueryStatusLed = buslogicR3DeviceQueryStatusLed;
4151
4152	/* Attach SCSI driver. */
4153	rc = PDMDevHlpDriverAttach(pDevIns, pDevice->iLUN, &pDevice->IBase, &pDevice->pDrvBase, szName);
4154	if (RT_SUCCESS(rc))
4155	{
4156	/* Get SCSI connector interface. */
4157	pDevice->pDrvSCSIConnector = PDMIBASE_QUERY_INTERFACE(pDevice->pDrvBase, PDMISCSICONNECTOR);
4158	AssertMsgReturn(pDevice->pDrvSCSIConnector, ("Missing SCSI interface below\n"), VERR_PDM_MISSING_INTERFACE);
4159
4160	pDevice->fPresent = true;
4161	}
4162	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4163	{
4164	pDevice->pDrvBase = NULL;
4165	pDevice->fPresent = false;
4166	rc = VINF_SUCCESS;
4167	Log(("BusLogic: no driver attached to device %s\n", szName));
4168	}
4169	else
4170	{
4171	AssertLogRelMsgFailed(("BusLogic: Failed to attach %s\n", szName));
4172	return rc;
4173	}
4174	}
4175
4176	/*
4177	* Attach status driver (optional).
4178	*/
4179	PPDMIBASE pBase;
4180	rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThis->IBase, &pBase, "Status Port");
4181	if (RT_SUCCESS(rc))
4182	pThis->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
4183	else if (rc != VERR_PDM_NO_ATTACHED_DRIVER)
4184	{
4185	AssertMsgFailed(("Failed to attach to status driver. rc=%Rrc\n", rc));
4186	return PDMDEV_SET_ERROR(pDevIns, rc, N_("BusLogic cannot attach to status driver"));
4187	}
4188
4189	rc = PDMDevHlpSSMRegisterEx(pDevIns, BUSLOGIC_SAVED_STATE_MINOR_VERSION, sizeof(*pThis), NULL,
4190	NULL, buslogicR3LiveExec, NULL,
4191	NULL, buslogicR3SaveExec, NULL,
4192	NULL, buslogicR3LoadExec, buslogicR3LoadDone);
4193	if (RT_FAILURE(rc))
4194	return PDMDEV_SET_ERROR(pDevIns, rc, N_("BusLogic cannot register save state handlers"));
4195
4196	/*
4197	* Register the debugger info callback.
4198	*/
4199	char szTmp[128];
4200	RTStrPrintf(szTmp, sizeof(szTmp), "%s%d", pDevIns->pReg->szName, pDevIns->iInstance);
4201	PDMDevHlpDBGFInfoRegister(pDevIns, szTmp, "BusLogic HBA info", buslogicR3Info);
4202
4203	rc = buslogicR3HwReset(pThis, true);
4204	AssertMsgRC(rc, ("hardware reset of BusLogic host adapter failed rc=%Rrc\n", rc));
4205
4206	return rc;
4207	}
4208
4209	/**
4210	* The device registration structure.
4211	*/
4212	const PDMDEVREG g_DeviceBusLogic =
4213	{
4214	/* u32Version */
4215	PDM_DEVREG_VERSION,
4216	/* szName */
4217	"buslogic",
4218	/* szRCMod */
4219	"VBoxDDRC.rc",
4220	/* szR0Mod */
4221	"VBoxDDR0.r0",
4222	/* pszDescription */
4223	"BusLogic BT-958 SCSI host adapter.\n",
4224	/* fFlags */
4225	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0 \|
4226	PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION \| PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION \|
4227	PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION,
4228	/* fClass */
4229	PDM_DEVREG_CLASS_STORAGE,
4230	/* cMaxInstances */
4231	~0U,
4232	/* cbInstance */
4233	sizeof(BUSLOGIC),
4234	/* pfnConstruct */
4235	buslogicR3Construct,
4236	/* pfnDestruct */
4237	buslogicR3Destruct,
4238	/* pfnRelocate */
4239	buslogicR3Relocate,
4240	/* pfnMemSetup */
4241	NULL,
4242	/* pfnPowerOn */
4243	NULL,
4244	/* pfnReset */
4245	buslogicR3Reset,
4246	/* pfnSuspend */
4247	buslogicR3Suspend,
4248	/* pfnResume */
4249	buslogicR3Resume,
4250	/* pfnAttach */
4251	buslogicR3Attach,
4252	/* pfnDetach */
4253	buslogicR3Detach,
4254	/* pfnQueryInterface. */
4255	NULL,
4256	/* pfnInitComplete */
4257	NULL,
4258	/* pfnPowerOff */
4259	buslogicR3PowerOff,
4260	/* pfnSoftReset */
4261	NULL,
4262	/* u32VersionEnd */
4263	PDM_DEVREG_VERSION
4264	};
4265
4266	#endif /* IN_RING3 */
4267	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Storage/DevBusLogic.cpp@ 61541

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