DevBusLogic.cpp@ 46243

Last change on this file since 46243 was 46243, checked in by vboxsync, 12 years ago
BusLogic: Implemented busmaster fifo r/w commands.
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1	/* $Id: DevBusLogic.cpp 46243 2013-05-23 16:09:52Z vboxsync $ */
2	/** @file
3	* VBox storage devices - BusLogic SCSI host adapter BT-958.
4	*
5	* Based on the Multi-Master Ultra SCSI Systems Technical Reference Manual.
6	*/
7
8	/*
9	* Copyright (C) 2006-2013 Oracle Corporation
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*/
19
20
21	/*******************************************************************************
22	* Header Files *
23	*******************************************************************************/
24	#define LOG_GROUP LOG_GROUP_DEV_BUSLOGIC
25	#include <VBox/vmm/pdmdev.h>
26	#include <VBox/vmm/pdmifs.h>
27	#include <VBox/vmm/pdmcritsect.h>
28	#include <VBox/scsi.h>
29	#include <iprt/asm.h>
30	#include <iprt/assert.h>
31	#include <iprt/string.h>
32	#include <iprt/log.h>
33	#ifdef IN_RING3
34	# include <iprt/alloc.h>
35	# include <iprt/memcache.h>
36	# include <iprt/param.h>
37	# include <iprt/uuid.h>
38	#endif
39
40	#include "VBoxSCSI.h"
41	#include "VBoxDD.h"
42
43
44	/*******************************************************************************
45	* Defined Constants And Macros *
46	*******************************************************************************/
47	/** Maximum number of attached devices the adapter can handle. */
48	#define BUSLOGIC_MAX_DEVICES 16
49
50	/** Maximum number of scatter gather elements this device can handle. */
51	#define BUSLOGIC_MAX_SCATTER_GATHER_LIST_SIZE 128
52
53	/** Size of the command buffer. */
54	#define BUSLOGIC_COMMAND_SIZE_MAX 5
55
56	/** Size of the reply buffer. */
57	#define BUSLOGIC_REPLY_SIZE_MAX 64
58
59	/** Custom fixed I/O ports for BIOS controller access.
60	* Note that these should not be in the ISA range (below 400h) to avoid
61	* conflicts with ISA device probing. Addresses in the 300h-340h range should be
62	* especially avoided.
63	*/
64	#define BUSLOGIC_BIOS_IO_PORT 0x430
65
66	/** State saved version. */
67	#define BUSLOGIC_SAVED_STATE_MINOR_VERSION 3
68
69	/** Saved state version before the suspend on error feature was implemented. */
70	#define BUSLOGIC_SAVED_STATE_MINOR_PRE_ERROR_HANDLING 1
71	/** Saved state version before 24-bit mailbox support was implemented. */
72	#define BUSLOGIC_SAVED_STATE_MINOR_PRE_24BIT_MBOX 2
73
74	/** The duration of software-initiated reset (in nano seconds).
75	* Not documented, set to 50 ms. */
76	#define BUSLOGIC_RESET_DURATION_NS UINT64_C(50000000)
77
78
79	/*******************************************************************************
80	* Structures and Typedefs *
81	*******************************************************************************/
82	/**
83	* State of a device attached to the buslogic host adapter.
84	*
85	* @implements PDMIBASE
86	* @implements PDMISCSIPORT
87	* @implements PDMILEDPORTS
88	*/
89	typedef struct BUSLOGICDEVICE
90	{
91	/** Pointer to the owning buslogic device instance. - R3 pointer */
92	R3PTRTYPE(struct BUSLOGIC *) pBusLogicR3;
93	/** Pointer to the owning buslogic device instance. - R0 pointer */
94	R0PTRTYPE(struct BUSLOGIC *) pBusLogicR0;
95	/** Pointer to the owning buslogic device instance. - RC pointer */
96	RCPTRTYPE(struct BUSLOGIC *) pBusLogicRC;
97
98	/** Flag whether device is present. */
99	bool fPresent;
100	/** LUN of the device. */
101	RTUINT iLUN;
102
103	#if HC_ARCH_BITS == 64
104	uint32_t Alignment0;
105	#endif
106
107	/** Our base interface. */
108	PDMIBASE IBase;
109	/** SCSI port interface. */
110	PDMISCSIPORT ISCSIPort;
111	/** Led interface. */
112	PDMILEDPORTS ILed;
113	/** Pointer to the attached driver's base interface. */
114	R3PTRTYPE(PPDMIBASE) pDrvBase;
115	/** Pointer to the underlying SCSI connector interface. */
116	R3PTRTYPE(PPDMISCSICONNECTOR) pDrvSCSIConnector;
117	/** The status LED state for this device. */
118	PDMLED Led;
119
120	#if HC_ARCH_BITS == 64
121	uint32_t Alignment1;
122	#endif
123
124	/** Number of outstanding tasks on the port. */
125	volatile uint32_t cOutstandingRequests;
126
127	} BUSLOGICDEVICE, *PBUSLOGICDEVICE;
128
129	/**
130	* Commands the BusLogic adapter supports.
131	*/
132	enum BUSLOGICCOMMAND
133	{
134	BUSLOGICCOMMAND_TEST_CMDC_INTERRUPT = 0x00,
135	BUSLOGICCOMMAND_INITIALIZE_MAILBOX = 0x01,
136	BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND = 0x02,
137	BUSLOGICCOMMAND_EXECUTE_BIOS_COMMAND = 0x03,
138	BUSLOGICCOMMAND_INQUIRE_BOARD_ID = 0x04,
139	BUSLOGICCOMMAND_ENABLE_OUTGOING_MAILBOX_AVAILABLE_INTERRUPT = 0x05,
140	BUSLOGICCOMMAND_SET_SCSI_SELECTION_TIMEOUT = 0x06,
141	BUSLOGICCOMMAND_SET_PREEMPT_TIME_ON_BUS = 0x07,
142	BUSLOGICCOMMAND_SET_TIME_OFF_BUS = 0x08,
143	BUSLOGICCOMMAND_SET_BUS_TRANSFER_RATE = 0x09,
144	BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_0_TO_7 = 0x0a,
145	BUSLOGICCOMMAND_INQUIRE_CONFIGURATION = 0x0b,
146	BUSLOGICCOMMAND_ENABLE_TARGET_MODE = 0x0c,
147	BUSLOGICCOMMAND_INQUIRE_SETUP_INFORMATION = 0x0d,
148	BUSLOGICCOMMAND_WRITE_ADAPTER_LOCAL_RAM = 0x1a,
149	BUSLOGICCOMMAND_READ_ADAPTER_LOCAL_RAM = 0x1b,
150	BUSLOGICCOMMAND_WRITE_BUSMASTER_CHIP_FIFO = 0x1c,
151	BUSLOGICCOMMAND_READ_BUSMASTER_CHIP_FIFO = 0x1d,
152	BUSLOGICCOMMAND_ECHO_COMMAND_DATA = 0x1f,
153	BUSLOGICCOMMAND_HOST_ADAPTER_DIAGNOSTIC = 0x20,
154	BUSLOGICCOMMAND_SET_ADAPTER_OPTIONS = 0x21,
155	BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_8_TO_15 = 0x23,
156	BUSLOGICCOMMAND_INQUIRE_TARGET_DEVICES = 0x24,
157	BUSLOGICCOMMAND_DISABLE_HOST_ADAPTER_INTERRUPT = 0x25,
158	BUSLOGICCOMMAND_EXT_BIOS_INFO = 0x28,
159	BUSLOGICCOMMAND_UNLOCK_MAILBOX = 0x29,
160	BUSLOGICCOMMAND_INITIALIZE_EXTENDED_MAILBOX = 0x81,
161	BUSLOGICCOMMAND_EXECUTE_SCSI_COMMAND = 0x83,
162	BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_3RD_LETTER = 0x84,
163	BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_LETTER = 0x85,
164	BUSLOGICCOMMAND_INQUIRE_PCI_HOST_ADAPTER_INFORMATION = 0x86,
165	BUSLOGICCOMMAND_INQUIRE_HOST_ADAPTER_MODEL_NUMBER = 0x8b,
166	BUSLOGICCOMMAND_INQUIRE_SYNCHRONOUS_PERIOD = 0x8c,
167	BUSLOGICCOMMAND_INQUIRE_EXTENDED_SETUP_INFORMATION = 0x8d,
168	BUSLOGICCOMMAND_ENABLE_STRICT_ROUND_ROBIN_MODE = 0x8f,
169	BUSLOGICCOMMAND_STORE_HOST_ADAPTER_LOCAL_RAM = 0x90,
170	BUSLOGICCOMMAND_FETCH_HOST_ADAPTER_LOCAL_RAM = 0x91,
171	BUSLOGICCOMMAND_STORE_LOCAL_DATA_IN_EEPROM = 0x92,
172	BUSLOGICCOMMAND_UPLOAD_AUTO_SCSI_CODE = 0x94,
173	BUSLOGICCOMMAND_MODIFY_IO_ADDRESS = 0x95,
174	BUSLOGICCOMMAND_SET_CCB_FORMAT = 0x96,
175	BUSLOGICCOMMAND_WRITE_INQUIRY_BUFFER = 0x9a,
176	BUSLOGICCOMMAND_READ_INQUIRY_BUFFER = 0x9b,
177	BUSLOGICCOMMAND_FLASH_ROM_UPLOAD_DOWNLOAD = 0xa7,
178	BUSLOGICCOMMAND_READ_SCAM_DATA = 0xa8,
179	BUSLOGICCOMMAND_WRITE_SCAM_DATA = 0xa9
180	} BUSLOGICCOMMAND;
181
182	#pragma pack(1)
183	/**
184	* Auto SCSI structure which is located
185	* in host adapter RAM and contains several
186	* configuration parameters.
187	*/
188	typedef struct AutoSCSIRam
189	{
190	uint8_t aInternalSignature[2];
191	uint8_t cbInformation;
192	uint8_t aHostAdaptertype[6];
193	uint8_t uReserved1;
194	bool fFloppyEnabled : 1;
195	bool fFloppySecondary : 1;
196	bool fLevelSensitiveInterrupt : 1;
197	unsigned char uReserved2 : 2;
198	unsigned char uSystemRAMAreForBIOS : 3;
199	unsigned char uDMAChannel : 7;
200	bool fDMAAutoConfiguration : 1;
201	unsigned char uIrqChannel : 7;
202	bool fIrqAutoConfiguration : 1;
203	uint8_t uDMATransferRate;
204	uint8_t uSCSIId;
205	bool fLowByteTerminated : 1;
206	bool fParityCheckingEnabled : 1;
207	bool fHighByteTerminated : 1;
208	bool fNoisyCablingEnvironment : 1;
209	bool fFastSynchronousNeogtiation : 1;
210	bool fBusResetEnabled : 1;
211	bool fReserved3 : 1;
212	bool fActiveNegotiationEnabled : 1;
213	uint8_t uBusOnDelay;
214	uint8_t uBusOffDelay;
215	bool fHostAdapterBIOSEnabled : 1;
216	bool fBIOSRedirectionOfInt19 : 1;
217	bool fExtendedTranslation : 1;
218	bool fMapRemovableAsFixed : 1;
219	bool fReserved4 : 1;
220	bool fBIOSSupportsMoreThan2Drives : 1;
221	bool fBIOSInterruptMode : 1;
222	bool fFlopticalSupport : 1;
223	uint16_t u16DeviceEnabledMask;
224	uint16_t u16WidePermittedMask;
225	uint16_t u16FastPermittedMask;
226	uint16_t u16SynchronousPermittedMask;
227	uint16_t u16DisconnectPermittedMask;
228	uint16_t u16SendStartUnitCommandMask;
229	uint16_t u16IgnoreInBIOSScanMask;
230	unsigned char uPCIInterruptPin : 2;
231	unsigned char uHostAdapterIoPortAddress : 2;
232	bool fStrictRoundRobinMode : 1;
233	bool fVesaBusSpeedGreaterThan33MHz : 1;
234	bool fVesaBurstWrite : 1;
235	bool fVesaBurstRead : 1;
236	uint16_t u16UltraPermittedMask;
237	uint32_t uReserved5;
238	uint8_t uReserved6;
239	uint8_t uAutoSCSIMaximumLUN;
240	bool fReserved7 : 1;
241	bool fSCAMDominant : 1;
242	bool fSCAMenabled : 1;
243	bool fSCAMLevel2 : 1;
244	unsigned char uReserved8 : 4;
245	bool fInt13Extension : 1;
246	bool fReserved9 : 1;
247	bool fCDROMBoot : 1;
248	unsigned char uReserved10 : 5;
249	unsigned char uBootTargetId : 4;
250	unsigned char uBootChannel : 4;
251	bool fForceBusDeviceScanningOrder : 1;
252	unsigned char uReserved11 : 7;
253	uint16_t u16NonTaggedToAlternateLunPermittedMask;
254	uint16_t u16RenegotiateSyncAfterCheckConditionMask;
255	uint8_t aReserved12[10];
256	uint8_t aManufacturingDiagnostic[2];
257	uint16_t u16Checksum;
258	} AutoSCSIRam, *PAutoSCSIRam;
259	AssertCompileSize(AutoSCSIRam, 64);
260	#pragma pack()
261
262	/**
263	* The local Ram.
264	*/
265	typedef union HostAdapterLocalRam
266	{
267	/** Byte view. */
268	uint8_t u8View[256];
269	/** Structured view. */
270	struct
271	{
272	/** Offset 0 - 63 is for BIOS. */
273	uint8_t u8Bios[64];
274	/** Auto SCSI structure. */
275	AutoSCSIRam autoSCSIData;
276	} structured;
277	} HostAdapterLocalRam, *PHostAdapterLocalRam;
278	AssertCompileSize(HostAdapterLocalRam, 256);
279
280
281	/** Ugly 24-bit big-endian addressing. */
282	typedef struct
283	{
284	uint8_t hi;
285	uint8_t mid;
286	uint8_t lo;
287	} Addr24, Len24;
288	AssertCompileSize(Addr24, 3);
289
290	#define ADDR_TO_U32(x) (((x).hi << 16) \| ((x).mid << 8) \| (x).lo)
291	#define LEN_TO_U32 ADDR_TO_U32
292	#define U32_TO_ADDR(a, x) do {(a).hi = (x) >> 16; (a).mid = (x) >> 8; (a).lo = (x);} while(0)
293	#define U32_TO_LEN U32_TO_ADDR
294
295	/** @name Compatible ISA base I/O port addresses. Disabled if zero.
296	* @{ */
297	#define NUM_ISA_BASES 8
298	#define MAX_ISA_BASE (NUM_ISA_BASES - 1)
299	#define ISA_BASE_DISABLED 6
300
301	static uint16_t const g_aISABases[NUM_ISA_BASES] =
302	{
303	0x330, 0x334, 0x230, 0x234, 0x130, 0x134, 0, 0
304	};
305	/** @} */
306
307	/** Pointer to a task state structure. */
308	typedef struct BUSLOGICTASKSTATE *PBUSLOGICTASKSTATE;
309
310	/**
311	* Main BusLogic device state.
312	*
313	* @extends PCIDEVICE
314	* @implements PDMILEDPORTS
315	*/
316	typedef struct BUSLOGIC
317	{
318	/** The PCI device structure. */
319	PCIDEVICE dev;
320	/** Pointer to the device instance - HC ptr */
321	PPDMDEVINSR3 pDevInsR3;
322	/** Pointer to the device instance - R0 ptr */
323	PPDMDEVINSR0 pDevInsR0;
324	/** Pointer to the device instance - RC ptr. */
325	PPDMDEVINSRC pDevInsRC;
326
327	/** Whether R0 is enabled. */
328	bool fR0Enabled;
329	/** Whether RC is enabled. */
330	bool fGCEnabled;
331
332	/** Base address of the I/O ports. */
333	RTIOPORT IOPortBase;
334	/** Base address of the memory mapping. */
335	RTGCPHYS MMIOBase;
336	/** Status register - Readonly. */
337	volatile uint8_t regStatus;
338	/** Interrupt register - Readonly. */
339	volatile uint8_t regInterrupt;
340	/** Geometry register - Readonly. */
341	volatile uint8_t regGeometry;
342	/** Pending (delayed) interrupt. */
343	uint8_t uPendingIntr;
344
345	/** Local RAM for the fetch hostadapter local RAM request.
346	* I don't know how big the buffer really is but the maximum
347	* seems to be 256 bytes because the offset and count field in the command request
348	* are only one byte big.
349	*/
350	HostAdapterLocalRam LocalRam;
351
352	/** Command code the guest issued. */
353	uint8_t uOperationCode;
354	/** Buffer for the command parameters the adapter is currently receiving from the guest.
355	* Size of the largest command which is possible.
356	*/
357	uint8_t aCommandBuffer[BUSLOGIC_COMMAND_SIZE_MAX]; /* Size of the biggest request. */
358	/** Current position in the command buffer. */
359	uint8_t iParameter;
360	/** Parameters left until the command is complete. */
361	uint8_t cbCommandParametersLeft;
362
363	/** Whether we are using the RAM or reply buffer. */
364	bool fUseLocalRam;
365	/** Buffer to store reply data from the controller to the guest. */
366	uint8_t aReplyBuffer[BUSLOGIC_REPLY_SIZE_MAX]; /* Size of the biggest reply. */
367	/** Position in the buffer we are reading next. */
368	uint8_t iReply;
369	/** Bytes left until the reply buffer is empty. */
370	uint8_t cbReplyParametersLeft;
371
372	/** Flag whether IRQs are enabled. */
373	bool fIRQEnabled;
374	/** Flag whether the ISA I/O port range is disabled
375	* to prevent the BIOS to access the device. */
376	bool fISAEnabled; /*< @todo unused, to be removed /
377	/** Flag whether 24-bit mailboxes are in use (default is 32-bit). */
378	bool fMbxIs24Bit;
379	/** ISA I/O port base (encoded in FW-compatible format). */
380	uint8_t uISABaseCode;
381
382	/** ISA I/O port base (disabled if zero). */
383	RTIOPORT IOISABase;
384	/** Default ISA I/O port base in FW-compatible format. */
385	uint8_t uDefaultISABaseCode;
386
387	/** Number of mailboxes the guest set up. */
388	uint32_t cMailbox;
389
390	#if HC_ARCH_BITS == 64
391	uint32_t Alignment0;
392	#endif
393
394	/** Time when HBA reset was last initiated. / /< @todo does this need to be saved? /
395	uint64_t u64ResetTime;
396	/** Physical base address of the outgoing mailboxes. */
397	RTGCPHYS GCPhysAddrMailboxOutgoingBase;
398	/** Current outgoing mailbox position. */
399	uint32_t uMailboxOutgoingPositionCurrent;
400	/** Number of mailboxes ready. */
401	volatile uint32_t cMailboxesReady;
402	/** Whether a notification to R3 was send. */
403	volatile bool fNotificationSend;
404
405	#if HC_ARCH_BITS == 64
406	uint32_t Alignment1;
407	#endif
408
409	/** Physical base address of the incoming mailboxes. */
410	RTGCPHYS GCPhysAddrMailboxIncomingBase;
411	/** Current incoming mailbox position. */
412	uint32_t uMailboxIncomingPositionCurrent;
413
414	/** Whether strict round robin is enabled. */
415	bool fStrictRoundRobinMode;
416	/** Whether the extended LUN CCB format is enabled for 32 possible logical units. */
417	bool fExtendedLunCCBFormat;
418
419	/** Queue to send tasks to R3. - HC ptr */
420	R3PTRTYPE(PPDMQUEUE) pNotifierQueueR3;
421	/** Queue to send tasks to R3. - HC ptr */
422	R0PTRTYPE(PPDMQUEUE) pNotifierQueueR0;
423	/** Queue to send tasks to R3. - RC ptr */
424	RCPTRTYPE(PPDMQUEUE) pNotifierQueueRC;
425
426	uint32_t Alignment2;
427
428	/** Critical section protecting access to the interrupt status register. */
429	PDMCRITSECT CritSectIntr;
430
431	/** Cache for task states. */
432	R3PTRTYPE(RTMEMCACHE) hTaskCache;
433
434	/** Device state for BIOS access. */
435	VBOXSCSI VBoxSCSI;
436
437	/** BusLogic device states. */
438	BUSLOGICDEVICE aDeviceStates[BUSLOGIC_MAX_DEVICES];
439
440	/** The base interface.
441	* @todo use PDMDEVINS::IBase */
442	PDMIBASE IBase;
443	/** Status Port - Leds interface. */
444	PDMILEDPORTS ILeds;
445	/** Partner of ILeds. */
446	R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
447
448	#if HC_ARCH_BITS == 64
449	uint32_t Alignment3;
450	#endif
451
452	/** Indicates that PDMDevHlpAsyncNotificationCompleted should be called when
453	* a port is entering the idle state. */
454	bool volatile fSignalIdle;
455	/** Flag whether we have tasks which need to be processed again. */
456	bool volatile fRedo;
457	/** List of tasks which can be redone. */
458	R3PTRTYPE(volatile PBUSLOGICTASKSTATE) pTasksRedoHead;
459
460	#ifdef LOG_ENABLED
461	# if HC_ARCH_BITS == 64
462	uint32_t Alignment4;
463	# endif
464
465	volatile uint32_t cInMailboxesReady;
466	#endif
467
468	} BUSLOGIC, *PBUSLOGIC;
469
470	/** Register offsets in the I/O port space. */
471	#define BUSLOGIC_REGISTER_CONTROL 0 /*< Writeonly /
472	/** Fields for the control register. */
473	# define BUSLOGIC_REGISTER_CONTROL_SCSI_BUSRESET RT_BIT(4)
474	# define BUSLOGIC_REGISTER_CONTROL_INTERRUPT_RESET RT_BIT(5)
475	# define BUSLOGIC_REGISTER_CONTROL_SOFT_RESET RT_BIT(6)
476	# define BUSLOGIC_REGISTER_CONTROL_HARD_RESET RT_BIT(7)
477
478	#define BUSLOGIC_REGISTER_STATUS 0 /*< Readonly /
479	/** Fields for the status register. */
480	# define BUSLOGIC_REGISTER_STATUS_COMMAND_INVALID RT_BIT(0)
481	# define BUSLOGIC_REGISTER_STATUS_DATA_IN_REGISTER_READY RT_BIT(2)
482	# define BUSLOGIC_REGISTER_STATUS_COMMAND_PARAMETER_REGISTER_BUSY RT_BIT(3)
483	# define BUSLOGIC_REGISTER_STATUS_HOST_ADAPTER_READY RT_BIT(4)
484	# define BUSLOGIC_REGISTER_STATUS_INITIALIZATION_REQUIRED RT_BIT(5)
485	# define BUSLOGIC_REGISTER_STATUS_DIAGNOSTIC_FAILURE RT_BIT(6)
486	# define BUSLOGIC_REGISTER_STATUS_DIAGNOSTIC_ACTIVE RT_BIT(7)
487
488	#define BUSLOGIC_REGISTER_COMMAND 1 /*< Writeonly /
489	#define BUSLOGIC_REGISTER_DATAIN 1 /*< Readonly /
490	#define BUSLOGIC_REGISTER_INTERRUPT 2 /*< Readonly /
491	/** Fields for the interrupt register. */
492	# define BUSLOGIC_REGISTER_INTERRUPT_INCOMING_MAILBOX_LOADED RT_BIT(0)
493	# define BUSLOGIC_REGISTER_INTERRUPT_OUTGOING_MAILBOX_AVAILABLE RT_BIT(1)
494	# define BUSLOGIC_REGISTER_INTERRUPT_COMMAND_COMPLETE RT_BIT(2)
495	# define BUSLOGIC_REGISTER_INTERRUPT_EXTERNAL_BUS_RESET RT_BIT(3)
496	# define BUSLOGIC_REGISTER_INTERRUPT_INTERRUPT_VALID RT_BIT(7)
497
498	#define BUSLOGIC_REGISTER_GEOMETRY 3 /* Readonly */
499	# define BUSLOGIC_REGISTER_GEOMETRY_EXTENTED_TRANSLATION_ENABLED RT_BIT(7)
500
501	/** Structure for the INQUIRE_PCI_HOST_ADAPTER_INFORMATION reply. */
502	typedef struct ReplyInquirePCIHostAdapterInformation
503	{
504	uint8_t IsaIOPort;
505	uint8_t IRQ;
506	unsigned char LowByteTerminated : 1;
507	unsigned char HighByteTerminated : 1;
508	unsigned char uReserved : 2; /* Reserved. */
509	unsigned char JP1 : 1; /* Whatever that means. */
510	unsigned char JP2 : 1; /* Whatever that means. */
511	unsigned char JP3 : 1; /* Whatever that means. */
512	/** Whether the provided info is valid. */
513	unsigned char InformationIsValid: 1;
514	uint8_t uReserved2; /* Reserved. */
515	} ReplyInquirePCIHostAdapterInformation, *PReplyInquirePCIHostAdapterInformation;
516	AssertCompileSize(ReplyInquirePCIHostAdapterInformation, 4);
517
518	/** Structure for the INQUIRE_CONFIGURATION reply. */
519	typedef struct ReplyInquireConfiguration
520	{
521	unsigned char uReserved1 : 5;
522	bool fDmaChannel5 : 1;
523	bool fDmaChannel6 : 1;
524	bool fDmaChannel7 : 1;
525	bool fIrqChannel9 : 1;
526	bool fIrqChannel10 : 1;
527	bool fIrqChannel11 : 1;
528	bool fIrqChannel12 : 1;
529	unsigned char uReserved2 : 1;
530	bool fIrqChannel14 : 1;
531	bool fIrqChannel15 : 1;
532	unsigned char uReserved3 : 1;
533	unsigned char uHostAdapterId : 4;
534	unsigned char uReserved4 : 4;
535	} ReplyInquireConfiguration, *PReplyInquireConfiguration;
536	AssertCompileSize(ReplyInquireConfiguration, 3);
537
538	/** Structure for the INQUIRE_SETUP_INFORMATION reply. */
539	typedef struct ReplyInquireSetupInformationSynchronousValue
540	{
541	unsigned char uOffset : 4;
542	unsigned char uTransferPeriod : 3;
543	bool fSynchronous : 1;
544	}ReplyInquireSetupInformationSynchronousValue, *PReplyInquireSetupInformationSynchronousValue;
545	AssertCompileSize(ReplyInquireSetupInformationSynchronousValue, 1);
546
547	typedef struct ReplyInquireSetupInformation
548	{
549	bool fSynchronousInitiationEnabled : 1;
550	bool fParityCheckingEnabled : 1;
551	unsigned char uReserved1 : 6;
552	uint8_t uBusTransferRate;
553	uint8_t uPreemptTimeOnBus;
554	uint8_t uTimeOffBus;
555	uint8_t cMailbox;
556	Addr24 MailboxAddress;
557	ReplyInquireSetupInformationSynchronousValue SynchronousValuesId0To7[8];
558	uint8_t uDisconnectPermittedId0To7;
559	uint8_t uSignature;
560	uint8_t uCharacterD;
561	uint8_t uHostBusType;
562	uint8_t uWideTransferPermittedId0To7;
563	uint8_t uWideTransfersActiveId0To7;
564	ReplyInquireSetupInformationSynchronousValue SynchronousValuesId8To15[8];
565	uint8_t uDisconnectPermittedId8To15;
566	uint8_t uReserved2;
567	uint8_t uWideTransferPermittedId8To15;
568	uint8_t uWideTransfersActiveId8To15;
569	} ReplyInquireSetupInformation, *PReplyInquireSetupInformation;
570	AssertCompileSize(ReplyInquireSetupInformation, 34);
571
572	/** Structure for the INQUIRE_EXTENDED_SETUP_INFORMATION. */
573	#pragma pack(1)
574	typedef struct ReplyInquireExtendedSetupInformation
575	{
576	uint8_t uBusType;
577	uint8_t uBiosAddress;
578	uint16_t u16ScatterGatherLimit;
579	uint8_t cMailbox;
580	uint32_t uMailboxAddressBase;
581	unsigned char uReserved1 : 2;
582	bool fFastEISA : 1;
583	unsigned char uReserved2 : 3;
584	bool fLevelSensitiveInterrupt : 1;
585	unsigned char uReserved3 : 1;
586	unsigned char aFirmwareRevision[3];
587	bool fHostWideSCSI : 1;
588	bool fHostDifferentialSCSI : 1;
589	bool fHostSupportsSCAM : 1;
590	bool fHostUltraSCSI : 1;
591	bool fHostSmartTermination : 1;
592	unsigned char uReserved4 : 3;
593	} ReplyInquireExtendedSetupInformation, *PReplyInquireExtendedSetupInformation;
594	AssertCompileSize(ReplyInquireExtendedSetupInformation, 14);
595	#pragma pack()
596
597	/** Structure for the INITIALIZE EXTENDED MAILBOX request. */
598	#pragma pack(1)
599	typedef struct RequestInitializeExtendedMailbox
600	{
601	/** Number of mailboxes in guest memory. */
602	uint8_t cMailbox;
603	/** Physical address of the first mailbox. */
604	uint32_t uMailboxBaseAddress;
605	} RequestInitializeExtendedMailbox, *PRequestInitializeExtendedMailbox;
606	AssertCompileSize(RequestInitializeExtendedMailbox, 5);
607	#pragma pack()
608
609	/** Structure for the INITIALIZE MAILBOX request. */
610	typedef struct
611	{
612	/** Number of mailboxes to set up. */
613	uint8_t cMailbox;
614	/** Physical address of the first mailbox. */
615	Addr24 aMailboxBaseAddr;
616	} RequestInitMbx, *PRequestInitMbx;
617	AssertCompileSize(RequestInitMbx, 4);
618
619	/**
620	* Structure of a mailbox in guest memory.
621	* The incoming and outgoing mailbox have the same size
622	* but the incoming one has some more fields defined which
623	* are marked as reserved in the outgoing one.
624	* The last field is also different from the type.
625	* For outgoing mailboxes it is the action and
626	* for incoming ones the completion status code for the task.
627	* We use one structure for both types.
628	*/
629	typedef struct Mailbox32
630	{
631	/** Physical address of the CCB structure in the guest memory. */
632	uint32_t u32PhysAddrCCB;
633	/** Type specific data. */
634	union
635	{
636	/** For outgoing mailboxes. */
637	struct
638	{
639	/** Reserved */
640	uint8_t uReserved[3];
641	/** Action code. */
642	uint8_t uActionCode;
643	} out;
644	/** For incoming mailboxes. */
645	struct
646	{
647	/** The host adapter status after finishing the request. */
648	uint8_t uHostAdapterStatus;
649	/** The status of the device which executed the request after executing it. */
650	uint8_t uTargetDeviceStatus;
651	/** Reserved. */
652	uint8_t uReserved;
653	/** The completion status code of the request. */
654	uint8_t uCompletionCode;
655	} in;
656	} u;
657	} Mailbox32, *PMailbox32;
658	AssertCompileSize(Mailbox32, 8);
659
660	/** Old style 24-bit mailbox entry. */
661	typedef struct Mailbox24
662	{
663	/** Mailbox command (incoming) or state (outgoing). */
664	uint8_t uCmdState;
665	/** Physical address of the CCB structure in the guest memory. */
666	Addr24 aPhysAddrCCB;
667	} Mailbox24, *PMailbox24;
668	AssertCompileSize(Mailbox24, 4);
669
670	/**
671	* Action codes for outgoing mailboxes.
672	*/
673	enum BUSLOGIC_MAILBOX_OUTGOING_ACTION
674	{
675	BUSLOGIC_MAILBOX_OUTGOING_ACTION_FREE = 0x00,
676	BUSLOGIC_MAILBOX_OUTGOING_ACTION_START_COMMAND = 0x01,
677	BUSLOGIC_MAILBOX_OUTGOING_ACTION_ABORT_COMMAND = 0x02
678	};
679
680	/**
681	* Completion codes for incoming mailboxes.
682	*/
683	enum BUSLOGIC_MAILBOX_INCOMING_COMPLETION
684	{
685	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_FREE = 0x00,
686	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITHOUT_ERROR = 0x01,
687	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_ABORTED = 0x02,
688	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_ABORTED_NOT_FOUND = 0x03,
689	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITH_ERROR = 0x04,
690	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_INVALID_CCB = 0x05
691	};
692
693	/**
694	* Host adapter status for incoming mailboxes.
695	*/
696	enum BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS
697	{
698	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_CMD_COMPLETED = 0x00,
699	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_LINKED_CMD_COMPLETED = 0x0a,
700	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_LINKED_CMD_COMPLETED_WITH_FLAG = 0x0b,
701	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_DATA_UNDERUN = 0x0c,
702	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_SCSI_SELECTION_TIMEOUT = 0x11,
703	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_DATA_OVERRUN = 0x12,
704	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_UNEXPECTED_BUS_FREE = 0x13,
705	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_INVALID_BUS_PHASE_REQUESTED = 0x14,
706	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_INVALID_OUTGOING_MAILBOX_ACTION_CODE = 0x15,
707	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_INVALID_COMMAND_OPERATION_CODE = 0x16,
708	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_LINKED_CCB_HAS_INVALID_LUN = 0x17,
709	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_INVALID_COMMAND_PARAMETER = 0x1a,
710	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_AUTO_REQUEST_SENSE_FAILED = 0x1b,
711	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_TAGGED_QUEUING_MESSAGE_REJECTED = 0x1c,
712	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_UNSUPPORTED_MESSAGE_RECEIVED = 0x1d,
713	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_HARDWARE_FAILED = 0x20,
714	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_TARGET_FAILED_RESPONSE_TO_ATN = 0x21,
715	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_ASSERTED_RST = 0x22,
716	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_OTHER_DEVICE_ASSERTED_RST = 0x23,
717	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_TARGET_DEVICE_RECONNECTED_IMPROPERLY = 0x24,
718	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_ASSERTED_BUS_DEVICE_RESET = 0x25,
719	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_ABORT_QUEUE_GENERATED = 0x26,
720	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_SOFTWARE_ERROR = 0x27,
721	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_HARDWARE_TIMEOUT_ERROR = 0x30,
722	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_SCSI_PARITY_ERROR_DETECTED = 0x34
723	};
724
725	/**
726	* Device status codes for incoming mailboxes.
727	*/
728	enum BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS
729	{
730	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_OPERATION_GOOD = 0x00,
731	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_CHECK_CONDITION = 0x02,
732	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_DEVICE_BUSY = 0x08
733	};
734
735	/**
736	* Opcode types for CCB.
737	*/
738	enum BUSLOGIC_CCB_OPCODE
739	{
740	BUSLOGIC_CCB_OPCODE_INITIATOR_CCB = 0x00,
741	BUSLOGIC_CCB_OPCODE_TARGET_CCB = 0x01,
742	BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_SCATTER_GATHER = 0x02,
743	BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_DATA_LENGTH = 0x03,
744	BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_SCATTER_GATHER = 0x04,
745	BUSLOGIC_CCB_OPCODE_BUS_DEVICE_RESET = 0x81
746	};
747
748	/**
749	* Data transfer direction.
750	*/
751	enum BUSLOGIC_CCB_DIRECTION
752	{
753	BUSLOGIC_CCB_DIRECTION_UNKNOWN = 0x00,
754	BUSLOGIC_CCB_DIRECTION_IN = 0x01,
755	BUSLOGIC_CCB_DIRECTION_OUT = 0x02,
756	BUSLOGIC_CCB_DIRECTION_NO_DATA = 0x03
757	};
758
759	/**
760	* The command control block for a SCSI request.
761	*/
762	typedef struct CCB32
763	{
764	/** Opcode. */
765	uint8_t uOpcode;
766	/** Reserved */
767	unsigned char uReserved1 : 3;
768	/** Data direction for the request. */
769	unsigned char uDataDirection : 2;
770	/** Whether the request is tag queued. */
771	bool fTagQueued : 1;
772	/** Queue tag mode. */
773	unsigned char uQueueTag : 2;
774	/** Length of the SCSI CDB. */
775	uint8_t cbCDB;
776	/** Sense data length. */
777	uint8_t cbSenseData;
778	/** Data length. */
779	uint32_t cbData;
780	/** Data pointer.
781	* This points to the data region or a scatter gather list based on the opcode.
782	*/
783	uint32_t u32PhysAddrData;
784	/** Reserved. */
785	uint8_t uReserved2[2];
786	/** Host adapter status. */
787	uint8_t uHostAdapterStatus;
788	/** Device adapter status. */
789	uint8_t uDeviceStatus;
790	/** The device the request is sent to. */
791	uint8_t uTargetId;
792	/*The LUN in the device. /
793	unsigned char uLogicalUnit : 5;
794	/** Legacy tag. */
795	bool fLegacyTagEnable : 1;
796	/** Legacy queue tag. */
797	unsigned char uLegacyQueueTag : 2;
798	/** The SCSI CDB. (A CDB can be 12 bytes long.) */
799	uint8_t abCDB[12];
800	/** Reserved. */
801	uint8_t uReserved3[6];
802	/** Sense data pointer. */
803	uint32_t u32PhysAddrSenseData;
804	} CCB32, *PCCB32;
805	AssertCompileSize(CCB32, 40);
806
807
808	/**
809	* The 24-bit command control block.
810	*/
811	typedef struct CCB24
812	{
813	/** Opcode. */
814	uint8_t uOpcode;
815	/** The LUN in the device. */
816	unsigned char uLogicalUnit : 3;
817	/** Data direction for the request. */
818	unsigned char uDataDirection : 2;
819	/** The target device ID. */
820	unsigned char uTargetId : 3;
821	/** Length of the SCSI CDB. */
822	uint8_t cbCDB;
823	/** Sense data length. */
824	uint8_t cbSenseData;
825	/** Data length. */
826	Len24 acbData;
827	/** Data pointer.
828	* This points to the data region or a scatter gather list based on the opc
829	*/
830	Addr24 aPhysAddrData;
831	/** Pointer to next CCB for linked commands. */
832	Addr24 aPhysAddrLink;
833	/** Command linking identifier. */
834	uint8_t uLinkId;
835	/** Host adapter status. */
836	uint8_t uHostAdapterStatus;
837	/** Device adapter status. */
838	uint8_t uDeviceStatus;
839	/** Two unused bytes. */
840	uint8_t aReserved[2];
841	/** The SCSI CDB. (A CDB can be 12 bytes long.) */
842	uint8_t abCDB[12];
843	} CCB24, *PCCB24;
844	AssertCompileSize(CCB24, 30);
845
846	/**
847	* The common 24-bit/32-bit command control block. The 32-bit CCB is laid out
848	* such that many fields are in the same location as in the older 24-bit CCB.
849	*/
850	typedef struct CCBC
851	{
852	/** Opcode. */
853	uint8_t uOpcode;
854	/** The LUN in the device. */
855	unsigned char uPad1 : 3;
856	/** Data direction for the request. */
857	unsigned char uDataDirection : 2;
858	/** The target device ID. */
859	unsigned char uPad2 : 3;
860	/** Length of the SCSI CDB. */
861	uint8_t cbCDB;
862	/** Sense data length. */
863	uint8_t cbSenseData;
864	uint8_t aPad1[10];
865	/** Host adapter status. */
866	uint8_t uHostAdapterStatus;
867	/** Device adapter status. */
868	uint8_t uDeviceStatus;
869	uint8_t aPad2[2];
870	/** The SCSI CDB (up to 12 bytes). */
871	uint8_t abCDB[12];
872	} CCBC, *PCCBC;
873	AssertCompileSize(CCB24, 30);
874
875	/* Make sure that the 24-bit/32-bit/common CCB offsets match. */
876	AssertCompileMemberOffset(CCBC, cbCDB, 2);
877	AssertCompileMemberOffset(CCB24, cbCDB, 2);
878	AssertCompileMemberOffset(CCB32, cbCDB, 2);
879	AssertCompileMemberOffset(CCBC, uHostAdapterStatus, 14);
880	AssertCompileMemberOffset(CCB24, uHostAdapterStatus, 14);
881	AssertCompileMemberOffset(CCB32, uHostAdapterStatus, 14);
882	AssertCompileMemberOffset(CCBC, abCDB, 18);
883	AssertCompileMemberOffset(CCB24, abCDB, 18);
884	AssertCompileMemberOffset(CCB32, abCDB, 18);
885
886	/** A union of all CCB types (24-bit/32-bit/common). */
887	typedef union CCBU
888	{
889	CCB32 n; /*< New 32-bit CCB. /
890	CCB24 o; /*< Old 24-bit CCB. /
891	CCBC c; /*< Common CCB subset. /
892	} CCBU, *PCCBU;
893
894	/** 32-bit scatter-gather list entry. */
895	typedef struct SGE32
896	{
897	uint32_t cbSegment;
898	uint32_t u32PhysAddrSegmentBase;
899	} SGE32, *PSGE32;
900	AssertCompileSize(SGE32, 8);
901
902	/** 24-bit scatter-gather list entry. */
903	typedef struct SGE24
904	{
905	Len24 acbSegment;
906	Addr24 aPhysAddrSegmentBase;
907	} SGE24, *PSGE24;
908	AssertCompileSize(SGE24, 6);
909
910	/**
911	* The structure for the "Execute SCSI Command" command.
912	*/
913	typedef struct ESCMD
914	{
915	/** Data length. */
916	uint32_t cbData;
917	/** Data pointer. */
918	uint32_t u32PhysAddrData;
919	/** The device the request is sent to. */
920	uint8_t uTargetId;
921	/** The LUN in the device. */
922	uint8_t uLogicalUnit;
923	/** Reserved */
924	unsigned char uReserved1 : 3;
925	/** Data direction for the request. */
926	unsigned char uDataDirection : 2;
927	/** Reserved */
928	unsigned char uReserved2 : 3;
929	/** Length of the SCSI CDB. */
930	uint8_t cbCDB;
931	/** The SCSI CDB. (A CDB can be 12 bytes long.) */
932	uint8_t abCDB[12];
933	} ESCMD, *PESCMD;
934	AssertCompileSize(ESCMD, 24);
935
936	/**
937	* Task state for a CCB request.
938	*/
939	typedef struct BUSLOGICTASKSTATE
940	{
941	/** Next in the redo list. */
942	PBUSLOGICTASKSTATE pRedoNext;
943	/** Device this task is assigned to. */
944	R3PTRTYPE(PBUSLOGICDEVICE) pTargetDeviceR3;
945	/** The command control block from the guest. */
946	CCBU CommandControlBlockGuest;
947	/** Mailbox read from guest memory. */
948	Mailbox32 MailboxGuest;
949	/** The SCSI request we pass to the underlying SCSI engine. */
950	PDMSCSIREQUEST PDMScsiRequest;
951	/** Data buffer segment */
952	RTSGSEG DataSeg;
953	/** Pointer to the R3 sense buffer. */
954	uint8_t *pbSenseBuffer;
955	/** Flag whether this is a request from the BIOS. */
956	bool fBIOS;
957	/** 24-bit request flag (default is 32-bit). */
958	bool fIs24Bit;
959	/** S/G entry size (depends on the above flag). */
960	uint8_t cbSGEntry;
961	} BUSLOGICTASKSTATE;
962
963	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
964
965	#define PDMIBASE_2_PBUSLOGICDEVICE(pInterface) ( (PBUSLOGICDEVICE)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGICDEVICE, IBase)) )
966	#define PDMISCSIPORT_2_PBUSLOGICDEVICE(pInterface) ( (PBUSLOGICDEVICE)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGICDEVICE, ISCSIPort)) )
967	#define PDMILEDPORTS_2_PBUSLOGICDEVICE(pInterface) ( (PBUSLOGICDEVICE)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGICDEVICE, ILed)) )
968	#define PDMIBASE_2_PBUSLOGIC(pInterface) ( (PBUSLOGIC)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGIC, IBase)) )
969	#define PDMILEDPORTS_2_PBUSLOGIC(pInterface) ( (PBUSLOGIC)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGIC, ILeds)) )
970
971	/*******************************************************************************
972	* Internal Functions *
973	*******************************************************************************/
974	static int buslogicR3RegisterISARange(PBUSLOGIC pBusLogic, uint8_t uBaseCode);
975
976
977	/**
978	* Assert IRQ line of the BusLogic adapter.
979	*
980	* @returns nothing.
981	* @param pBusLogic Pointer to the BusLogic device instance.
982	* @param fSuppressIrq Flag to suppress IRQ generation regardless of fIRQEnabled
983	* @param uFlag Type of interrupt being generated.
984	*/
985	static void buslogicSetInterrupt(PBUSLOGIC pBusLogic, bool fSuppressIrq, uint8_t uIrqType)
986	{
987	LogFlowFunc(("pBusLogic=%#p\n", pBusLogic));
988
989	/* The CMDC interrupt has priority over IMBL and MBOR. */
990	if (uIrqType & (BUSLOGIC_REGISTER_INTERRUPT_INCOMING_MAILBOX_LOADED \| BUSLOGIC_REGISTER_INTERRUPT_OUTGOING_MAILBOX_AVAILABLE))
991	{
992	if (!(pBusLogic->regInterrupt & BUSLOGIC_REGISTER_INTERRUPT_COMMAND_COMPLETE))
993	pBusLogic->regInterrupt \|= uIrqType; /* Report now. */
994	else
995	pBusLogic->uPendingIntr \|= uIrqType; /* Report later. */
996	}
997	else if (uIrqType & BUSLOGIC_REGISTER_INTERRUPT_COMMAND_COMPLETE)
998	{
999	Assert(!pBusLogic->regInterrupt);
1000	pBusLogic->regInterrupt \|= uIrqType;
1001	}
1002	else
1003	AssertMsgFailed(("Invalid interrupt state!\n"));
1004
1005	pBusLogic->regInterrupt \|= BUSLOGIC_REGISTER_INTERRUPT_INTERRUPT_VALID;
1006	if (pBusLogic->fIRQEnabled && !fSuppressIrq)
1007	PDMDevHlpPCISetIrq(pBusLogic->CTX_SUFF(pDevIns), 0, 1);
1008	}
1009
1010	/**
1011	* Deasserts the interrupt line of the BusLogic adapter.
1012	*
1013	* @returns nothing
1014	* @param pBuslogic Pointer to the BusLogic device instance.
1015	*/
1016	static void buslogicClearInterrupt(PBUSLOGIC pBusLogic)
1017	{
1018	LogFlowFunc(("pBusLogic=%#p\n", pBusLogic));
1019	pBusLogic->regInterrupt = 0;
1020	PDMDevHlpPCISetIrq(pBusLogic->CTX_SUFF(pDevIns), 0, 0);
1021	/* If there's another pending interrupt, report it now. */
1022	if (pBusLogic->uPendingIntr)
1023	{
1024	buslogicSetInterrupt(pBusLogic, false, pBusLogic->uPendingIntr);
1025	pBusLogic->uPendingIntr = 0;
1026	}
1027	}
1028
1029	#if defined(IN_RING3)
1030
1031	/**
1032	* Advances the mailbox pointer to the next slot.
1033	*/
1034	DECLINLINE(void) buslogicR3OutgoingMailboxAdvance(PBUSLOGIC pBusLogic)
1035	{
1036	pBusLogic->uMailboxOutgoingPositionCurrent = (pBusLogic->uMailboxOutgoingPositionCurrent + 1) % pBusLogic->cMailbox;
1037	}
1038
1039	/**
1040	* Initialize local RAM of host adapter with default values.
1041	*
1042	* @returns nothing.
1043	* @param pBusLogic.
1044	*/
1045	static void buslogicR3InitializeLocalRam(PBUSLOGIC pBusLogic)
1046	{
1047	/*
1048	* These values are mostly from what I think is right
1049	* looking at the dmesg output from a Linux guest inside
1050	* a VMware server VM.
1051	*
1052	* So they don't have to be right :)
1053	*/
1054	memset(pBusLogic->LocalRam.u8View, 0, sizeof(HostAdapterLocalRam));
1055	pBusLogic->LocalRam.structured.autoSCSIData.fLevelSensitiveInterrupt = true;
1056	pBusLogic->LocalRam.structured.autoSCSIData.fParityCheckingEnabled = true;
1057	pBusLogic->LocalRam.structured.autoSCSIData.fExtendedTranslation = true; /* Same as in geometry register. */
1058	pBusLogic->LocalRam.structured.autoSCSIData.u16DeviceEnabledMask = ~0; /* All enabled. Maybe mask out non present devices? */
1059	pBusLogic->LocalRam.structured.autoSCSIData.u16WidePermittedMask = ~0;
1060	pBusLogic->LocalRam.structured.autoSCSIData.u16FastPermittedMask = ~0;
1061	pBusLogic->LocalRam.structured.autoSCSIData.u16SynchronousPermittedMask = ~0;
1062	pBusLogic->LocalRam.structured.autoSCSIData.u16DisconnectPermittedMask = ~0;
1063	pBusLogic->LocalRam.structured.autoSCSIData.fStrictRoundRobinMode = pBusLogic->fStrictRoundRobinMode;
1064	pBusLogic->LocalRam.structured.autoSCSIData.u16UltraPermittedMask = ~0;
1065	/** @todo calculate checksum? */
1066	}
1067
1068	/**
1069	* Do a hardware reset of the buslogic adapter.
1070	*
1071	* @returns VBox status code.
1072	* @param pBusLogic Pointer to the BusLogic device instance.
1073	* @param fResetIO Flag determining whether ISA I/O should be reset.
1074	*/
1075	static int buslogicR3HwReset(PBUSLOGIC pBusLogic, bool fResetIO)
1076	{
1077	LogFlowFunc(("pBusLogic=%#p\n", pBusLogic));
1078
1079	/* Reset registers to default value. */
1080	pBusLogic->regStatus = BUSLOGIC_REGISTER_STATUS_HOST_ADAPTER_READY \| BUSLOGIC_REGISTER_STATUS_INITIALIZATION_REQUIRED;
1081	pBusLogic->regInterrupt = 0;
1082	pBusLogic->uPendingIntr = 0;
1083	pBusLogic->regGeometry = BUSLOGIC_REGISTER_GEOMETRY_EXTENTED_TRANSLATION_ENABLED;
1084	pBusLogic->uOperationCode = 0xff; /* No command executing. */
1085	pBusLogic->iParameter = 0;
1086	pBusLogic->cbCommandParametersLeft = 0;
1087	pBusLogic->fIRQEnabled = true;
1088	pBusLogic->uMailboxOutgoingPositionCurrent = 0;
1089	pBusLogic->uMailboxIncomingPositionCurrent = 0;
1090
1091	/* Guest-initiated HBA reset does not affect ISA port I/O. */
1092	if (fResetIO)
1093	{
1094	buslogicR3RegisterISARange(pBusLogic, pBusLogic->uDefaultISABaseCode);
1095	}
1096	buslogicR3InitializeLocalRam(pBusLogic);
1097	vboxscsiInitialize(&pBusLogic->VBoxSCSI);
1098
1099	return VINF_SUCCESS;
1100	}
1101
1102	#endif /* IN_RING3 */
1103
1104	/**
1105	* Resets the command state machine for the next command and notifies the guest.
1106	*
1107	* @returns nothing.
1108	* @param pBusLogic Pointer to the BusLogic device instance
1109	* @param fSuppressIrq Flag to suppress IRQ generation regardless of current state
1110	*/
1111	static void buslogicCommandComplete(PBUSLOGIC pBusLogic, bool fSuppressIrq)
1112	{
1113	LogFlowFunc(("pBusLogic=%#p\n", pBusLogic));
1114
1115	pBusLogic->fUseLocalRam = false;
1116	pBusLogic->regStatus \|= BUSLOGIC_REGISTER_STATUS_HOST_ADAPTER_READY;
1117	pBusLogic->iReply = 0;
1118
1119	/* Modify I/O address does not generate an interrupt. */
1120	if (pBusLogic->uOperationCode != BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND)
1121	{
1122	/* Notify that the command is complete. */
1123	pBusLogic->regStatus &= ~BUSLOGIC_REGISTER_STATUS_DATA_IN_REGISTER_READY;
1124	buslogicSetInterrupt(pBusLogic, fSuppressIrq, BUSLOGIC_REGISTER_INTERRUPT_COMMAND_COMPLETE);
1125	}
1126
1127	pBusLogic->uOperationCode = 0xff;
1128	pBusLogic->iParameter = 0;
1129	}
1130
1131	#if defined(IN_RING3)
1132
1133	/**
1134	* Initiates a hard reset which was issued from the guest.
1135	*
1136	* @returns nothing
1137	* @param pBusLogic Pointer to the BusLogic device instance.
1138	* @param fHardReset Flag initiating a hard (vs. soft) reset.
1139	*/
1140	static void buslogicR3InitiateReset(PBUSLOGIC pBusLogic, bool fHardReset)
1141	{
1142	LogFlowFunc(("pBusLogic=%#p fHardReset=%d\n", pBusLogic, fHardReset));
1143
1144	buslogicR3HwReset(pBusLogic, false);
1145
1146	if (fHardReset)
1147	{
1148	/* Set the diagnostic active bit in the status register and clear the ready state. */
1149	pBusLogic->regStatus \|= BUSLOGIC_REGISTER_STATUS_DIAGNOSTIC_ACTIVE;
1150	pBusLogic->regStatus &= ~BUSLOGIC_REGISTER_STATUS_HOST_ADAPTER_READY;
1151
1152	/* Remember when the guest initiated a reset (after we're done resetting). */
1153	pBusLogic->u64ResetTime = PDMDevHlpTMTimeVirtGetNano(pBusLogic->CTX_SUFF(pDevIns));
1154	}
1155	}
1156
1157	/**
1158	* Send a mailbox with set status codes to the guest.
1159	*
1160	* @returns nothing.
1161	* @param pBusLogic Pointer to the BusLogic device instance.
1162	* @param pTaskState Pointer to the task state with the mailbox to send.
1163	* @param uHostAdapterStatus The host adapter status code to set.
1164	* @param uDeviceStatus The target device status to set.
1165	* @param uMailboxCompletionCode Completion status code to set in the mailbox.
1166	*/
1167	static void buslogicR3SendIncomingMailbox(PBUSLOGIC pBusLogic, PBUSLOGICTASKSTATE pTaskState,
1168	uint8_t uHostAdapterStatus, uint8_t uDeviceStatus,
1169	uint8_t uMailboxCompletionCode)
1170	{
1171	pTaskState->MailboxGuest.u.in.uHostAdapterStatus = uHostAdapterStatus;
1172	pTaskState->MailboxGuest.u.in.uTargetDeviceStatus = uDeviceStatus;
1173	pTaskState->MailboxGuest.u.in.uCompletionCode = uMailboxCompletionCode;
1174
1175	int rc = PDMCritSectEnter(&pBusLogic->CritSectIntr, VINF_SUCCESS);
1176	AssertRC(rc);
1177	RTGCPHYS GCPhysAddrCCB = pTaskState->MailboxGuest.u32PhysAddrCCB;
1178	RTGCPHYS GCPhysAddrMailboxIncoming = pBusLogic->GCPhysAddrMailboxIncomingBase
1179	+ ( pBusLogic->uMailboxIncomingPositionCurrent
1180	* (pTaskState->fIs24Bit ? sizeof(Mailbox24) : sizeof(Mailbox32)) );
1181	LogFlowFunc(("Completing CCB %RGp hstat=%u, dstat=%u, outgoing mailbox at %RGp\n", GCPhysAddrCCB,
1182	uHostAdapterStatus, uDeviceStatus, GCPhysAddrMailboxIncoming));
1183
1184	/* Update CCB. */
1185	pTaskState->CommandControlBlockGuest.c.uHostAdapterStatus = uHostAdapterStatus;
1186	pTaskState->CommandControlBlockGuest.c.uDeviceStatus = uDeviceStatus;
1187	/* Rewrite CCB up to the CDB; perhaps more than necessary. */
1188	PDMDevHlpPCIPhysWrite(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrCCB,
1189	&pTaskState->CommandControlBlockGuest, RT_OFFSETOF(CCBC, abCDB));
1190
1191	# ifdef RT_STRICT
1192	uint8_t uCode;
1193	unsigned uCodeOffs = pTaskState->fIs24Bit ? RT_OFFSETOF(Mailbox24, uCmdState) : RT_OFFSETOF(Mailbox32, u.out.uActionCode);
1194	PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrMailboxIncoming + uCodeOffs, &uCode, sizeof(uCode));
1195	Assert(uCode == BUSLOGIC_MAILBOX_INCOMING_COMPLETION_FREE);
1196	# endif
1197
1198	/* Update mailbox. */
1199	if (pTaskState->fIs24Bit)
1200	{
1201	Mailbox24 Mbx24;
1202
1203	Mbx24.uCmdState = pTaskState->MailboxGuest.u.in.uCompletionCode;
1204	U32_TO_ADDR(Mbx24.aPhysAddrCCB, pTaskState->MailboxGuest.u32PhysAddrCCB);
1205	Log(("24-bit mailbox: completion code=%u, CCB at %RGp\n", Mbx24.uCmdState, (RTGCPHYS)ADDR_TO_U32(Mbx24.aPhysAddrCCB)));
1206	PDMDevHlpPCIPhysWrite(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrMailboxIncoming, &Mbx24, sizeof(Mailbox24));
1207	}
1208	else
1209	{
1210	Log(("32-bit mailbox: completion code=%u, CCB at %RGp\n", pTaskState->MailboxGuest.u.in.uCompletionCode, (RTGCPHYS)pTaskState->MailboxGuest.u32PhysAddrCCB));
1211	PDMDevHlpPCIPhysWrite(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrMailboxIncoming,
1212	&pTaskState->MailboxGuest, sizeof(Mailbox32));
1213	}
1214
1215	/* Advance to next mailbox position. */
1216	pBusLogic->uMailboxIncomingPositionCurrent++;
1217	if (pBusLogic->uMailboxIncomingPositionCurrent >= pBusLogic->cMailbox)
1218	pBusLogic->uMailboxIncomingPositionCurrent = 0;
1219
1220	# ifdef LOG_ENABLED
1221	ASMAtomicIncU32(&pBusLogic->cInMailboxesReady);
1222	# endif
1223
1224	buslogicSetInterrupt(pBusLogic, false, BUSLOGIC_REGISTER_INTERRUPT_INCOMING_MAILBOX_LOADED);
1225
1226	PDMCritSectLeave(&pBusLogic->CritSectIntr);
1227	}
1228
1229	# ifdef LOG_ENABLED
1230
1231	/**
1232	* Dumps the content of a mailbox for debugging purposes.
1233	*
1234	* @return nothing
1235	* @param pMailbox The mailbox to dump.
1236	* @param fOutgoing true if dumping the outgoing state.
1237	* false if dumping the incoming state.
1238	*/
1239	static void buslogicR3DumpMailboxInfo(PMailbox32 pMailbox, bool fOutgoing)
1240	{
1241	Log(("%s: Dump for %s mailbox:\n", __FUNCTION__, fOutgoing ? "outgoing" : "incoming"));
1242	Log(("%s: u32PhysAddrCCB=%#x\n", __FUNCTION__, pMailbox->u32PhysAddrCCB));
1243	if (fOutgoing)
1244	{
1245	Log(("%s: uActionCode=%u\n", __FUNCTION__, pMailbox->u.out.uActionCode));
1246	}
1247	else
1248	{
1249	Log(("%s: uHostAdapterStatus=%u\n", __FUNCTION__, pMailbox->u.in.uHostAdapterStatus));
1250	Log(("%s: uTargetDeviceStatus=%u\n", __FUNCTION__, pMailbox->u.in.uTargetDeviceStatus));
1251	Log(("%s: uCompletionCode=%u\n", __FUNCTION__, pMailbox->u.in.uCompletionCode));
1252	}
1253	}
1254
1255	/**
1256	* Dumps the content of a command control block for debugging purposes.
1257	*
1258	* @returns nothing.
1259	* @param pCCB Pointer to the command control block to dump.
1260	* @param fIs24BitCCB Flag to determine CCB format.
1261	*/
1262	static void buslogicR3DumpCCBInfo(PCCBU pCCB, bool fIs24BitCCB)
1263	{
1264	Log(("%s: Dump for %s Command Control Block:\n", __FUNCTION__, fIs24BitCCB ? "24-bit" : "32-bit"));
1265	Log(("%s: uOpCode=%#x\n", __FUNCTION__, pCCB->c.uOpcode));
1266	Log(("%s: uDataDirection=%u\n", __FUNCTION__, pCCB->c.uDataDirection));
1267	Log(("%s: cbCDB=%u\n", __FUNCTION__, pCCB->c.cbCDB));
1268	Log(("%s: cbSenseData=%u\n", __FUNCTION__, pCCB->c.cbSenseData));
1269	Log(("%s: uHostAdapterStatus=%u\n", __FUNCTION__, pCCB->c.uHostAdapterStatus));
1270	Log(("%s: uDeviceStatus=%u\n", __FUNCTION__, pCCB->c.uDeviceStatus));
1271	if (fIs24BitCCB)
1272	{
1273	Log(("%s: cbData=%u\n", __FUNCTION__, LEN_TO_U32(pCCB->o.acbData)));
1274	Log(("%s: PhysAddrData=%#x\n", __FUNCTION__, ADDR_TO_U32(pCCB->o.aPhysAddrData)));
1275	Log(("%s: uTargetId=%u\n", __FUNCTION__, pCCB->o.uTargetId));
1276	Log(("%s: uLogicalUnit=%u\n", __FUNCTION__, pCCB->o.uLogicalUnit));
1277	}
1278	else
1279	{
1280	Log(("%s: cbData=%u\n", __FUNCTION__, pCCB->n.cbData));
1281	Log(("%s: PhysAddrData=%#x\n", __FUNCTION__, pCCB->n.u32PhysAddrData));
1282	Log(("%s: uTargetId=%u\n", __FUNCTION__, pCCB->n.uTargetId));
1283	Log(("%s: uLogicalUnit=%u\n", __FUNCTION__, pCCB->n.uLogicalUnit));
1284	Log(("%s: fTagQueued=%d\n", __FUNCTION__, pCCB->n.fTagQueued));
1285	Log(("%s: uQueueTag=%u\n", __FUNCTION__, pCCB->n.uQueueTag));
1286	Log(("%s: fLegacyTagEnable=%u\n", __FUNCTION__, pCCB->n.fLegacyTagEnable));
1287	Log(("%s: uLegacyQueueTag=%u\n", __FUNCTION__, pCCB->n.uLegacyQueueTag));
1288	Log(("%s: PhysAddrSenseData=%#x\n", __FUNCTION__, pCCB->n.u32PhysAddrSenseData));
1289	}
1290	Log(("%s: uCDB[0]=%#x\n", __FUNCTION__, pCCB->c.abCDB[0]));
1291	for (int i = 1; i < pCCB->c.cbCDB; i++)
1292	Log(("%s: uCDB[%d]=%u\n", __FUNCTION__, i, pCCB->c.abCDB[i]));
1293	}
1294
1295	# endif /* LOG_ENABLED */
1296
1297	/**
1298	* Allocate data buffer.
1299	*
1300	* @param pTaskState Pointer to the task state.
1301	* @param GCSGList Guest physical address of S/G list.
1302	* @param cEntries Number of list entries to read.
1303	* @param pSGEList Pointer to 32-bit S/G list storage.
1304	*/
1305	static void buslogicR3ReadSGEntries(PBUSLOGICTASKSTATE pTaskState, RTGCPHYS GCSGList, uint32_t cEntries, SGE32 *pSGEList)
1306	{
1307	PPDMDEVINS pDevIns = pTaskState->CTX_SUFF(pTargetDevice)->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);
1308	SGE24 aSGE24[32];
1309	Assert(cEntries <= RT_ELEMENTS(aSGE24));
1310
1311	/* Read the S/G entries. Convert 24-bit entries to 32-bit format. */
1312	if (pTaskState->fIs24Bit)
1313	{
1314	Log2(("Converting %u 24-bit S/G entries to 32-bit\n", cEntries));
1315	PDMDevHlpPhysRead(pDevIns, GCSGList, &aSGE24, cEntries * sizeof(SGE24));
1316	for (uint32_t i = 0; i < cEntries; ++i)
1317	{
1318	pSGEList[i].cbSegment = LEN_TO_U32(aSGE24[i].acbSegment);
1319	pSGEList[i].u32PhysAddrSegmentBase = ADDR_TO_U32(aSGE24[i].aPhysAddrSegmentBase);
1320	}
1321	}
1322	else
1323	PDMDevHlpPhysRead(pDevIns, GCSGList, pSGEList, cEntries * sizeof(SGE32));
1324	}
1325
1326	/**
1327	* Allocate data buffer.
1328	*
1329	* @returns VBox status code.
1330	* @param pTaskState Pointer to the task state.
1331	*/
1332	static int buslogicR3DataBufferAlloc(PBUSLOGICTASKSTATE pTaskState)
1333	{
1334	PPDMDEVINS pDevIns = pTaskState->CTX_SUFF(pTargetDevice)->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);
1335	uint32_t cbDataCCB;
1336	uint32_t u32PhysAddrCCB;
1337
1338	/* Extract the data length and physical address from the CCB. */
1339	if (pTaskState->fIs24Bit)
1340	{
1341	u32PhysAddrCCB = ADDR_TO_U32(pTaskState->CommandControlBlockGuest.o.aPhysAddrData);
1342	cbDataCCB = LEN_TO_U32(pTaskState->CommandControlBlockGuest.o.acbData);
1343	}
1344	else
1345	{
1346	u32PhysAddrCCB = pTaskState->CommandControlBlockGuest.n.u32PhysAddrData;
1347	cbDataCCB = pTaskState->CommandControlBlockGuest.n.cbData;
1348	}
1349
1350	if ( (pTaskState->CommandControlBlockGuest.c.uDataDirection != BUSLOGIC_CCB_DIRECTION_NO_DATA)
1351	&& cbDataCCB)
1352	{
1353	/** @todo Check following assumption and what residual means. */
1354	/*
1355	* The BusLogic adapter can handle two different data buffer formats.
1356	* The first one is that the data pointer entry in the CCB points to
1357	* the buffer directly. In second mode the data pointer points to a
1358	* scatter gather list which describes the buffer.
1359	*/
1360	if ( (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_SCATTER_GATHER)
1361	\|\| (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_SCATTER_GATHER))
1362	{
1363	uint32_t cScatterGatherGCRead;
1364	uint32_t iScatterGatherEntry;
1365	SGE32 aScatterGatherReadGC[32]; /* A buffer for scatter gather list entries read from guest memory. */
1366	uint32_t cScatterGatherGCLeft = cbDataCCB / pTaskState->cbSGEntry;
1367	RTGCPHYS GCPhysAddrScatterGatherCurrent = u32PhysAddrCCB;
1368	size_t cbDataToTransfer = 0;
1369
1370	/* Count number of bytes to transfer. */
1371	do
1372	{
1373	cScatterGatherGCRead = (cScatterGatherGCLeft < RT_ELEMENTS(aScatterGatherReadGC))
1374	? cScatterGatherGCLeft
1375	: RT_ELEMENTS(aScatterGatherReadGC);
1376	cScatterGatherGCLeft -= cScatterGatherGCRead;
1377
1378	buslogicR3ReadSGEntries(pTaskState, GCPhysAddrScatterGatherCurrent, cScatterGatherGCRead, aScatterGatherReadGC);
1379
1380	for (iScatterGatherEntry = 0; iScatterGatherEntry < cScatterGatherGCRead; iScatterGatherEntry++)
1381	{
1382	RTGCPHYS GCPhysAddrDataBase;
1383
1384	Log(("%s: iScatterGatherEntry=%u\n", __FUNCTION__, iScatterGatherEntry));
1385
1386	GCPhysAddrDataBase = (RTGCPHYS)aScatterGatherReadGC[iScatterGatherEntry].u32PhysAddrSegmentBase;
1387	cbDataToTransfer += aScatterGatherReadGC[iScatterGatherEntry].cbSegment;
1388
1389	Log(("%s: GCPhysAddrDataBase=%RGp cbDataToTransfer=%u\n",
1390	__FUNCTION__, GCPhysAddrDataBase,
1391	aScatterGatherReadGC[iScatterGatherEntry].cbSegment));
1392	}
1393
1394	/* Set address to the next entries to read. */
1395	GCPhysAddrScatterGatherCurrent += cScatterGatherGCRead * pTaskState->cbSGEntry;
1396	} while (cScatterGatherGCLeft > 0);
1397
1398	Log(("%s: cbDataToTransfer=%d\n", __FUNCTION__, cbDataToTransfer));
1399
1400	/* Allocate buffer */
1401	pTaskState->DataSeg.cbSeg = cbDataToTransfer;
1402	pTaskState->DataSeg.pvSeg = RTMemAlloc(pTaskState->DataSeg.cbSeg);
1403	if (!pTaskState->DataSeg.pvSeg)
1404	return VERR_NO_MEMORY;
1405
1406	/* Copy the data if needed */
1407	if ( (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_OUT)
1408	\|\| (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_UNKNOWN))
1409	{
1410	cScatterGatherGCLeft = cbDataCCB / pTaskState->cbSGEntry;
1411	GCPhysAddrScatterGatherCurrent = u32PhysAddrCCB;
1412	uint8_t pbData = (uint8_t )pTaskState->DataSeg.pvSeg;
1413
1414	do
1415	{
1416	cScatterGatherGCRead = (cScatterGatherGCLeft < RT_ELEMENTS(aScatterGatherReadGC))
1417	? cScatterGatherGCLeft
1418	: RT_ELEMENTS(aScatterGatherReadGC);
1419	cScatterGatherGCLeft -= cScatterGatherGCRead;
1420
1421	buslogicR3ReadSGEntries(pTaskState, GCPhysAddrScatterGatherCurrent, cScatterGatherGCRead, aScatterGatherReadGC);
1422
1423	for (iScatterGatherEntry = 0; iScatterGatherEntry < cScatterGatherGCRead; iScatterGatherEntry++)
1424	{
1425	RTGCPHYS GCPhysAddrDataBase;
1426
1427	Log(("%s: iScatterGatherEntry=%u\n", __FUNCTION__, iScatterGatherEntry));
1428
1429	GCPhysAddrDataBase = (RTGCPHYS)aScatterGatherReadGC[iScatterGatherEntry].u32PhysAddrSegmentBase;
1430	cbDataToTransfer = aScatterGatherReadGC[iScatterGatherEntry].cbSegment;
1431
1432	Log(("%s: GCPhysAddrDataBase=%RGp cbDataToTransfer=%u\n", __FUNCTION__, GCPhysAddrDataBase, cbDataToTransfer));
1433
1434	PDMDevHlpPhysRead(pDevIns, GCPhysAddrDataBase, pbData, cbDataToTransfer);
1435	pbData += cbDataToTransfer;
1436	}
1437
1438	/* Set address to the next entries to read. */
1439	GCPhysAddrScatterGatherCurrent += cScatterGatherGCRead * pTaskState->cbSGEntry;
1440	} while (cScatterGatherGCLeft > 0);
1441	}
1442
1443	}
1444	else if ( pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB
1445	\|\| pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_DATA_LENGTH)
1446	{
1447	/* The buffer is not scattered. */
1448	RTGCPHYS GCPhysAddrDataBase = u32PhysAddrCCB;
1449
1450	AssertMsg(GCPhysAddrDataBase != 0, ("Physical address is 0\n"));
1451
1452	pTaskState->DataSeg.cbSeg = cbDataCCB;
1453	pTaskState->DataSeg.pvSeg = RTMemAlloc(pTaskState->DataSeg.cbSeg);
1454	if (!pTaskState->DataSeg.pvSeg)
1455	return VERR_NO_MEMORY;
1456
1457	Log(("Non scattered buffer:\n"));
1458	Log(("u32PhysAddrData=%#x\n", u32PhysAddrCCB));
1459	Log(("cbData=%u\n", cbDataCCB));
1460	Log(("GCPhysAddrDataBase=0x%RGp\n", GCPhysAddrDataBase));
1461
1462	/* Copy the data into the buffer. */
1463	PDMDevHlpPhysRead(pDevIns, GCPhysAddrDataBase, pTaskState->DataSeg.pvSeg, pTaskState->DataSeg.cbSeg);
1464	}
1465	}
1466
1467	return VINF_SUCCESS;
1468	}
1469
1470	/**
1471	* Free allocated resources used for the scatter gather list.
1472	*
1473	* @returns nothing.
1474	* @param pTaskState Pointer to the task state.
1475	*/
1476	static void buslogicR3DataBufferFree(PBUSLOGICTASKSTATE pTaskState)
1477	{
1478	PPDMDEVINS pDevIns = pTaskState->CTX_SUFF(pTargetDevice)->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);
1479	uint32_t cbDataCCB;
1480	uint32_t u32PhysAddrCCB;
1481
1482	/* Extract the data length and physical address from the CCB. */
1483	if (pTaskState->fIs24Bit)
1484	{
1485	u32PhysAddrCCB = ADDR_TO_U32(pTaskState->CommandControlBlockGuest.o.aPhysAddrData);
1486	cbDataCCB = LEN_TO_U32(pTaskState->CommandControlBlockGuest.o.acbData);
1487	}
1488	else
1489	{
1490	u32PhysAddrCCB = pTaskState->CommandControlBlockGuest.n.u32PhysAddrData;
1491	cbDataCCB = pTaskState->CommandControlBlockGuest.n.cbData;
1492	}
1493
1494	#if 1
1495	/* Hack for NT 10/91: A CCB describes a 2K buffer, but TEST UNIT READY is executed. This command
1496	* returns no data, hence the buffer must be left alone!
1497	*/
1498	if (pTaskState->CommandControlBlockGuest.c.abCDB[0] == 0)
1499	cbDataCCB = 0;
1500	#endif
1501
1502	LogFlowFunc(("pTaskState=%#p cbDataCCB=%u direction=%u cbSeg=%u\n", pTaskState, cbDataCCB,
1503	pTaskState->CommandControlBlockGuest.c.uDataDirection, pTaskState->DataSeg.cbSeg));
1504
1505	if ( (cbDataCCB > 0)
1506	&& ( (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_IN)
1507	\|\| (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_UNKNOWN)))
1508	{
1509	if ( (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_SCATTER_GATHER)
1510	\|\| (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_SCATTER_GATHER))
1511	{
1512	uint32_t cScatterGatherGCRead;
1513	uint32_t iScatterGatherEntry;
1514	SGE32 aScatterGatherReadGC[32]; /* Number of scatter gather list entries read from guest memory. */
1515	uint32_t cScatterGatherGCLeft = cbDataCCB / pTaskState->cbSGEntry;
1516	RTGCPHYS GCPhysAddrScatterGatherCurrent = u32PhysAddrCCB;
1517	uint8_t pbData = (uint8_t )pTaskState->DataSeg.pvSeg;
1518
1519	do
1520	{
1521	cScatterGatherGCRead = (cScatterGatherGCLeft < RT_ELEMENTS(aScatterGatherReadGC))
1522	? cScatterGatherGCLeft
1523	: RT_ELEMENTS(aScatterGatherReadGC);
1524	cScatterGatherGCLeft -= cScatterGatherGCRead;
1525
1526	buslogicR3ReadSGEntries(pTaskState, GCPhysAddrScatterGatherCurrent, cScatterGatherGCRead, aScatterGatherReadGC);
1527
1528	for (iScatterGatherEntry = 0; iScatterGatherEntry < cScatterGatherGCRead; iScatterGatherEntry++)
1529	{
1530	RTGCPHYS GCPhysAddrDataBase;
1531	size_t cbDataToTransfer;
1532
1533	Log(("%s: iScatterGatherEntry=%u\n", __FUNCTION__, iScatterGatherEntry));
1534
1535	GCPhysAddrDataBase = (RTGCPHYS)aScatterGatherReadGC[iScatterGatherEntry].u32PhysAddrSegmentBase;
1536	cbDataToTransfer = aScatterGatherReadGC[iScatterGatherEntry].cbSegment;
1537
1538	Log(("%s: GCPhysAddrDataBase=%RGp cbDataToTransfer=%u\n", __FUNCTION__, GCPhysAddrDataBase, cbDataToTransfer));
1539
1540	PDMDevHlpPCIPhysWrite(pDevIns, GCPhysAddrDataBase, pbData, cbDataToTransfer);
1541	pbData += cbDataToTransfer;
1542	}
1543
1544	/* Set address to the next entries to read. */
1545	GCPhysAddrScatterGatherCurrent += cScatterGatherGCRead * pTaskState->cbSGEntry;
1546	} while (cScatterGatherGCLeft > 0);
1547
1548	}
1549	else if ( pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB
1550	\|\| pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_DATA_LENGTH)
1551	{
1552	/* The buffer is not scattered. */
1553	RTGCPHYS GCPhysAddrDataBase = u32PhysAddrCCB;
1554
1555	AssertMsg(GCPhysAddrDataBase != 0, ("Physical address is 0\n"));
1556
1557	Log(("Non-scattered buffer:\n"));
1558	Log(("u32PhysAddrData=%#x\n", u32PhysAddrCCB));
1559	Log(("cbData=%u\n", cbDataCCB));
1560	Log(("GCPhysAddrDataBase=0x%RGp\n", GCPhysAddrDataBase));
1561
1562	/* Copy the data into the guest memory. */
1563	PDMDevHlpPCIPhysWrite(pDevIns, GCPhysAddrDataBase, pTaskState->DataSeg.pvSeg, pTaskState->DataSeg.cbSeg);
1564	}
1565
1566	}
1567	/* Update residual data length. */
1568	if ( (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_DATA_LENGTH)
1569	\|\| (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_SCATTER_GATHER))
1570	{
1571	uint32_t cbResidual;
1572
1573	/** @todo we need to get the actual transfer length from the VSCSI layer?! */
1574	cbResidual = 0; //LEN_TO_U32(pTaskState->CCBGuest.acbData) - ???;
1575	if (pTaskState->fIs24Bit)
1576	U32_TO_LEN(pTaskState->CommandControlBlockGuest.o.acbData, cbResidual);
1577	else
1578	pTaskState->CommandControlBlockGuest.n.cbData = cbResidual;
1579	}
1580
1581	RTMemFree(pTaskState->DataSeg.pvSeg);
1582	pTaskState->DataSeg.pvSeg = NULL;
1583	pTaskState->DataSeg.cbSeg = 0;
1584	}
1585
1586	/** Convert sense buffer length taking into account shortcut values. */
1587	static uint32_t buslogicR3ConvertSenseBufferLength(uint32_t cbSense)
1588	{
1589	/* Convert special sense buffer length values. */
1590	if (cbSense == 0)
1591	cbSense = 14; /* 0 means standard 14-byte buffer. */
1592	else if (cbSense == 1)
1593	cbSense = 0; /* 1 means no sense data. */
1594	else if (cbSense < 8)
1595	AssertMsgFailed(("Reserved cbSense value of %d used!\n", cbSense));
1596
1597	return cbSense;
1598	}
1599
1600	/**
1601	* Free the sense buffer.
1602	*
1603	* @returns nothing.
1604	* @param pTaskState Pointer to the task state.
1605	* @param fCopy If sense data should be copied to guest memory.
1606	*/
1607	static void buslogicR3SenseBufferFree(PBUSLOGICTASKSTATE pTaskState, bool fCopy)
1608	{
1609	uint32_t cbSenseBuffer;
1610
1611	cbSenseBuffer = buslogicR3ConvertSenseBufferLength(pTaskState->CommandControlBlockGuest.c.cbSenseData);
1612
1613	/* Copy the sense buffer into guest memory if requested. */
1614	if (fCopy && cbSenseBuffer)
1615	{
1616	PPDMDEVINS pDevIns = pTaskState->CTX_SUFF(pTargetDevice)->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);
1617	RTGCPHYS GCPhysAddrSenseBuffer;
1618
1619	/* With 32-bit CCBs, the (optional) sense buffer physical address is provided separately.
1620	* On the other hand, with 24-bit CCBs, the sense buffer is simply located at the end of
1621	* the CCB, right after the variable-length CDB.
1622	*/
1623	if (pTaskState->fIs24Bit)
1624	{
1625	GCPhysAddrSenseBuffer = pTaskState->MailboxGuest.u32PhysAddrCCB;
1626	GCPhysAddrSenseBuffer += pTaskState->CommandControlBlockGuest.c.cbCDB + RT_OFFSETOF(CCB24, abCDB);
1627	}
1628	else
1629	GCPhysAddrSenseBuffer = pTaskState->CommandControlBlockGuest.n.u32PhysAddrSenseData;
1630
1631	PDMDevHlpPCIPhysWrite(pDevIns, GCPhysAddrSenseBuffer, pTaskState->pbSenseBuffer, cbSenseBuffer);
1632	}
1633
1634	RTMemFree(pTaskState->pbSenseBuffer);
1635	pTaskState->pbSenseBuffer = NULL;
1636	}
1637
1638	/**
1639	* Alloc the sense buffer.
1640	*
1641	* @returns VBox status code.
1642	* @param pTaskState Pointer to the task state.
1643	* @note Current assumption is that the sense buffer is not scattered and does not cross a page boundary.
1644	*/
1645	static int buslogicR3SenseBufferAlloc(PBUSLOGICTASKSTATE pTaskState)
1646	{
1647	PPDMDEVINS pDevIns = pTaskState->CTX_SUFF(pTargetDevice)->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);
1648	uint32_t cbSenseBuffer;
1649
1650	pTaskState->pbSenseBuffer = NULL;
1651
1652	cbSenseBuffer = buslogicR3ConvertSenseBufferLength(pTaskState->CommandControlBlockGuest.c.cbSenseData);
1653	if (cbSenseBuffer)
1654	{
1655	pTaskState->pbSenseBuffer = (uint8_t *)RTMemAllocZ(cbSenseBuffer);
1656	if (!pTaskState->pbSenseBuffer)
1657	return VERR_NO_MEMORY;
1658	}
1659
1660	return VINF_SUCCESS;
1661	}
1662
1663	#endif /* IN_RING3 */
1664
1665	/**
1666	* Parses the command buffer and executes it.
1667	*
1668	* @returns VBox status code.
1669	* @param pBusLogic Pointer to the BusLogic device instance.
1670	*/
1671	static int buslogicProcessCommand(PBUSLOGIC pBusLogic)
1672	{
1673	int rc = VINF_SUCCESS;
1674	bool fSuppressIrq = false;
1675
1676	LogFlowFunc(("pBusLogic=%#p\n", pBusLogic));
1677	AssertMsg(pBusLogic->uOperationCode != 0xff, ("There is no command to execute\n"));
1678
1679	switch (pBusLogic->uOperationCode)
1680	{
1681	case BUSLOGICCOMMAND_TEST_CMDC_INTERRUPT:
1682	/* Valid command, no reply. */
1683	pBusLogic->cbReplyParametersLeft = 0;
1684	break;
1685	case BUSLOGICCOMMAND_INQUIRE_PCI_HOST_ADAPTER_INFORMATION:
1686	{
1687	PReplyInquirePCIHostAdapterInformation pReply = (PReplyInquirePCIHostAdapterInformation)pBusLogic->aReplyBuffer;
1688	memset(pReply, 0, sizeof(ReplyInquirePCIHostAdapterInformation));
1689
1690	/* It seems VMware does not provide valid information here too, lets do the same :) */
1691	pReply->InformationIsValid = 0;
1692	pReply->IsaIOPort = pBusLogic->uISABaseCode;
1693	pReply->IRQ = PCIDevGetInterruptLine(&pBusLogic->dev);
1694	pBusLogic->cbReplyParametersLeft = sizeof(ReplyInquirePCIHostAdapterInformation);
1695	break;
1696	}
1697	case BUSLOGICCOMMAND_MODIFY_IO_ADDRESS:
1698	{
1699	/* Modify the ISA-compatible I/O port base. Note that this technically
1700	* violates the PCI spec, as this address is not reported through PCI.
1701	* However, it is required for compatibility with old drivers.
1702	*/
1703	#ifdef IN_RING3
1704	Log(("ISA I/O for PCI (code %x)\n", pBusLogic->aCommandBuffer[0]));
1705	buslogicR3RegisterISARange(pBusLogic, pBusLogic->aCommandBuffer[0]);
1706	pBusLogic->cbReplyParametersLeft = 0;
1707	fSuppressIrq = true;
1708	break;
1709	#else
1710	AssertMsgFailed(("Must never get here!\n"));
1711	#endif
1712	}
1713	case BUSLOGICCOMMAND_INQUIRE_BOARD_ID:
1714	{
1715	/* The special option byte is important: If it is '0' or 'B', Windows NT drivers
1716	* for Adaptec AHA-154x may claim the adapter. The BusLogic drivers will claim
1717	* the adapter only when the byte is not '0' or 'B'.
1718	*/
1719	pBusLogic->aReplyBuffer[0] = 'A'; /* Firmware option bytes */
1720	pBusLogic->aReplyBuffer[1] = 'A'; /* Special option byte */
1721
1722	/* We report version 5.07B. This reply will provide the first two digits. */
1723	pBusLogic->aReplyBuffer[2] = '5'; /* Major version 5 */
1724	pBusLogic->aReplyBuffer[3] = '0'; /* Minor version 0 */
1725	pBusLogic->cbReplyParametersLeft = 4; /* Reply is 4 bytes long */
1726	break;
1727	}
1728	case BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_3RD_LETTER:
1729	{
1730	pBusLogic->aReplyBuffer[0] = '7';
1731	pBusLogic->cbReplyParametersLeft = 1;
1732	break;
1733	}
1734	case BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_LETTER:
1735	{
1736	pBusLogic->aReplyBuffer[0] = 'B';
1737	pBusLogic->cbReplyParametersLeft = 1;
1738	break;
1739	}
1740	case BUSLOGICCOMMAND_SET_ADAPTER_OPTIONS:
1741	/* The parameter list length is determined by the first byte of the command buffer. */
1742	if (pBusLogic->iParameter == 1)
1743	{
1744	/* First pass - set the number of following parameter bytes. */
1745	pBusLogic->cbCommandParametersLeft = pBusLogic->aCommandBuffer[0];
1746	Log(("Set HA options: %u bytes follow\n", pBusLogic->cbCommandParametersLeft));
1747	}
1748	else
1749	{
1750	/* Second pass - process received data. */
1751	Log(("Set HA options: received %u bytes\n", pBusLogic->aCommandBuffer[0]));
1752	/* We ignore the data - it only concerns the SCSI hardware protocol. */
1753	}
1754	pBusLogic->cbReplyParametersLeft = 0;
1755	break;
1756
1757	case BUSLOGICCOMMAND_INQUIRE_HOST_ADAPTER_MODEL_NUMBER:
1758	{
1759	/* The reply length is set by the guest and is found in the first byte of the command buffer. */
1760	pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[0];
1761	memset(pBusLogic->aReplyBuffer, ' ', pBusLogic->cbReplyParametersLeft);
1762	const char aModelName[] = "958";
1763	int cCharsToTransfer = (pBusLogic->cbReplyParametersLeft <= (sizeof(aModelName) - 1))
1764	? pBusLogic->cbReplyParametersLeft
1765	: sizeof(aModelName) - 1;
1766
1767	for (int i = 0; i < cCharsToTransfer; i++)
1768	pBusLogic->aReplyBuffer[i] = aModelName[i];
1769
1770	break;
1771	}
1772	case BUSLOGICCOMMAND_INQUIRE_CONFIGURATION:
1773	{
1774	uint8_t uPciIrq = PCIDevGetInterruptLine(&pBusLogic->dev);
1775
1776	pBusLogic->cbReplyParametersLeft = sizeof(ReplyInquireConfiguration);
1777	PReplyInquireConfiguration pReply = (PReplyInquireConfiguration)pBusLogic->aReplyBuffer;
1778	memset(pReply, 0, sizeof(ReplyInquireConfiguration));
1779
1780	pReply->uHostAdapterId = 7; /* The controller has always 7 as ID. */
1781	pReply->fDmaChannel6 = 1; /* DMA channel 6 is a good default. */
1782	/* The PCI IRQ is not necessarily representable in this structure.
1783	* If that is the case, the guest likely won't function correctly,
1784	* therefore we log a warning.
1785	*/
1786	switch (uPciIrq)
1787	{
1788	case 9: pReply->fIrqChannel9 = 1; break;
1789	case 10: pReply->fIrqChannel10 = 1; break;
1790	case 11: pReply->fIrqChannel11 = 1; break;
1791	case 12: pReply->fIrqChannel12 = 1; break;
1792	case 14: pReply->fIrqChannel14 = 1; break;
1793	case 15: pReply->fIrqChannel15 = 1; break;
1794	default:
1795	LogRel(("Warning: PCI IRQ %d cannot be represented as ISA!\n", uPciIrq));
1796	break;
1797	}
1798	break;
1799	}
1800	case BUSLOGICCOMMAND_INQUIRE_EXTENDED_SETUP_INFORMATION:
1801	{
1802	/* Some Adaptec AHA-154x drivers (e.g. OS/2) execute this command and expect
1803	* it to fail. If it succeeds, the drivers refuse to load. However, some newer
1804	* Adaptec 154x models supposedly support it too??
1805	*/
1806
1807	/* The reply length is set by the guest and is found in the first byte of the command buffer. */
1808	pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[0];
1809	PReplyInquireExtendedSetupInformation pReply = (PReplyInquireExtendedSetupInformation)pBusLogic->aReplyBuffer;
1810	memset(pReply, 0, sizeof(ReplyInquireExtendedSetupInformation));
1811
1812	/** @todo should this reflect the RAM contents (AutoSCSIRam)? */
1813	pReply->uBusType = 'E'; /* EISA style */
1814	pReply->u16ScatterGatherLimit = 8192;
1815	pReply->cMailbox = pBusLogic->cMailbox;
1816	pReply->uMailboxAddressBase = (uint32_t)pBusLogic->GCPhysAddrMailboxOutgoingBase;
1817	pReply->fLevelSensitiveInterrupt = true;
1818	pReply->fHostWideSCSI = true;
1819	pReply->fHostUltraSCSI = true;
1820	memcpy(pReply->aFirmwareRevision, "07B", sizeof(pReply->aFirmwareRevision));
1821
1822	break;
1823	}
1824	case BUSLOGICCOMMAND_INQUIRE_SETUP_INFORMATION:
1825	{
1826	/* The reply length is set by the guest and is found in the first byte of the command buffer. */
1827	pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[0];
1828	PReplyInquireSetupInformation pReply = (PReplyInquireSetupInformation)pBusLogic->aReplyBuffer;
1829	memset(pReply, 0, sizeof(ReplyInquireSetupInformation));
1830	pReply->fSynchronousInitiationEnabled = true;
1831	pReply->fParityCheckingEnabled = true;
1832	pReply->cMailbox = pBusLogic->cMailbox;
1833	U32_TO_ADDR(pReply->MailboxAddress, pBusLogic->GCPhysAddrMailboxOutgoingBase);
1834	pReply->uSignature = 'B';
1835	/* The 'D' signature prevents Adaptec's OS/2 drivers from getting too
1836	* friendly with BusLogic hardware and upsetting the HBA state.
1837	*/
1838	pReply->uCharacterD = 'D'; /* BusLogic model. */
1839	pReply->uHostBusType = 'F'; /* PCI bus. */
1840	break;
1841	}
1842	case BUSLOGICCOMMAND_FETCH_HOST_ADAPTER_LOCAL_RAM:
1843	{
1844	/*
1845	* First element in the command buffer contains start offset to read from
1846	* and second one the number of bytes to read.
1847	*/
1848	uint8_t uOffset = pBusLogic->aCommandBuffer[0];
1849	pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[1];
1850
1851	pBusLogic->fUseLocalRam = true;
1852	pBusLogic->iReply = uOffset;
1853	break;
1854	}
1855	case BUSLOGICCOMMAND_INITIALIZE_MAILBOX:
1856	{
1857	PRequestInitMbx pRequest = (PRequestInitMbx)pBusLogic->aCommandBuffer;
1858
1859	pBusLogic->fMbxIs24Bit = true;
1860	pBusLogic->cMailbox = pRequest->cMailbox;
1861	pBusLogic->GCPhysAddrMailboxOutgoingBase = (RTGCPHYS)ADDR_TO_U32(pRequest->aMailboxBaseAddr);
1862	/* The area for incoming mailboxes is right after the last entry of outgoing mailboxes. */
1863	pBusLogic->GCPhysAddrMailboxIncomingBase = pBusLogic->GCPhysAddrMailboxOutgoingBase + (pBusLogic->cMailbox * sizeof(Mailbox24));
1864
1865	Log(("GCPhysAddrMailboxOutgoingBase=%RGp\n", pBusLogic->GCPhysAddrMailboxOutgoingBase));
1866	Log(("GCPhysAddrMailboxIncomingBase=%RGp\n", pBusLogic->GCPhysAddrMailboxIncomingBase));
1867	Log(("cMailboxes=%u (24-bit mode)\n", pBusLogic->cMailbox));
1868	LogRel(("Initialized 24-bit mailbox, %d entries at %08x\n", pRequest->cMailbox, ADDR_TO_U32(pRequest->aMailboxBaseAddr)));
1869
1870	pBusLogic->regStatus &= ~BUSLOGIC_REGISTER_STATUS_INITIALIZATION_REQUIRED;
1871	pBusLogic->cbReplyParametersLeft = 0;
1872	break;
1873	}
1874	case BUSLOGICCOMMAND_INITIALIZE_EXTENDED_MAILBOX:
1875	{
1876	PRequestInitializeExtendedMailbox pRequest = (PRequestInitializeExtendedMailbox)pBusLogic->aCommandBuffer;
1877
1878	pBusLogic->fMbxIs24Bit = false;
1879	pBusLogic->cMailbox = pRequest->cMailbox;
1880	pBusLogic->GCPhysAddrMailboxOutgoingBase = (RTGCPHYS)pRequest->uMailboxBaseAddress;
1881	/* The area for incoming mailboxes is right after the last entry of outgoing mailboxes. */
1882	pBusLogic->GCPhysAddrMailboxIncomingBase = (RTGCPHYS)pRequest->uMailboxBaseAddress + (pBusLogic->cMailbox * sizeof(Mailbox32));
1883
1884	Log(("GCPhysAddrMailboxOutgoingBase=%RGp\n", pBusLogic->GCPhysAddrMailboxOutgoingBase));
1885	Log(("GCPhysAddrMailboxIncomingBase=%RGp\n", pBusLogic->GCPhysAddrMailboxIncomingBase));
1886	Log(("cMailboxes=%u (32-bit mode)\n", pBusLogic->cMailbox));
1887	LogRel(("Initialized 32-bit mailbox, %d entries at %08x\n", pRequest->cMailbox, pRequest->uMailboxBaseAddress));
1888
1889	pBusLogic->regStatus &= ~BUSLOGIC_REGISTER_STATUS_INITIALIZATION_REQUIRED;
1890	pBusLogic->cbReplyParametersLeft = 0;
1891	break;
1892	}
1893	case BUSLOGICCOMMAND_ENABLE_STRICT_ROUND_ROBIN_MODE:
1894	{
1895	if (pBusLogic->aCommandBuffer[0] == 0)
1896	pBusLogic->fStrictRoundRobinMode = false;
1897	else if (pBusLogic->aCommandBuffer[0] == 1)
1898	pBusLogic->fStrictRoundRobinMode = true;
1899	else
1900	AssertMsgFailed(("Invalid round robin mode %d\n", pBusLogic->aCommandBuffer[0]));
1901
1902	pBusLogic->cbReplyParametersLeft = 0;
1903	break;
1904	}
1905	case BUSLOGICCOMMAND_SET_CCB_FORMAT:
1906	{
1907	if (pBusLogic->aCommandBuffer[0] == 0)
1908	pBusLogic->fExtendedLunCCBFormat = false;
1909	else if (pBusLogic->aCommandBuffer[0] == 1)
1910	pBusLogic->fExtendedLunCCBFormat = true;
1911	else
1912	AssertMsgFailed(("Invalid CCB format %d\n", pBusLogic->aCommandBuffer[0]));
1913
1914	pBusLogic->cbReplyParametersLeft = 0;
1915	break;
1916	}
1917	case BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_0_TO_7:
1918	/* This is supposed to send TEST UNIT READY to each target/LUN.
1919	* We cheat and skip that, since we already know what's attached
1920	*/
1921	memset(pBusLogic->aReplyBuffer, 0, 8);
1922	for (int i = 0; i < 8; ++i)
1923	{
1924	if (pBusLogic->aDeviceStates[i].fPresent)
1925	pBusLogic->aReplyBuffer[i] = 1;
1926	}
1927	pBusLogic->aReplyBuffer[7] = 0; /* HA hardcoded at ID 7. */
1928	pBusLogic->cbReplyParametersLeft = 8;
1929	break;
1930	case BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_8_TO_15:
1931	/* See note about cheating above. */
1932	memset(pBusLogic->aReplyBuffer, 0, 8);
1933	for (int i = 0; i < 8; ++i)
1934	{
1935	if (pBusLogic->aDeviceStates[i + 8].fPresent)
1936	pBusLogic->aReplyBuffer[i] = 1;
1937	}
1938	pBusLogic->cbReplyParametersLeft = 8;
1939	break;
1940	case BUSLOGICCOMMAND_INQUIRE_TARGET_DEVICES:
1941	{
1942	/* Each bit which is set in the 16bit wide variable means a present device. */
1943	uint16_t u16TargetsPresentMask = 0;
1944
1945	for (uint8_t i = 0; i < RT_ELEMENTS(pBusLogic->aDeviceStates); i++)
1946	{
1947	if (pBusLogic->aDeviceStates[i].fPresent)
1948	u16TargetsPresentMask \|= (1 << i);
1949	}
1950	pBusLogic->aReplyBuffer[0] = (uint8_t)u16TargetsPresentMask;
1951	pBusLogic->aReplyBuffer[1] = (uint8_t)(u16TargetsPresentMask >> 8);
1952	pBusLogic->cbReplyParametersLeft = 2;
1953	break;
1954	}
1955	case BUSLOGICCOMMAND_INQUIRE_SYNCHRONOUS_PERIOD:
1956	{
1957	pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[0];
1958
1959	for (uint8_t i = 0; i < pBusLogic->cbReplyParametersLeft; i++)
1960	pBusLogic->aReplyBuffer[i] = 0; /** @todo Figure if we need something other here. It's not needed for the linux driver */
1961
1962	break;
1963	}
1964	case BUSLOGICCOMMAND_DISABLE_HOST_ADAPTER_INTERRUPT:
1965	{
1966	if (pBusLogic->aCommandBuffer[0] == 0)
1967	pBusLogic->fIRQEnabled = false;
1968	else
1969	pBusLogic->fIRQEnabled = true;
1970	/* No interrupt signaled regardless of enable/disable. */
1971	fSuppressIrq = true;
1972	break;
1973	}
1974	case BUSLOGICCOMMAND_ECHO_COMMAND_DATA:
1975	{
1976	pBusLogic->aReplyBuffer[0] = pBusLogic->aCommandBuffer[0];
1977	pBusLogic->cbReplyParametersLeft = 1;
1978	break;
1979	}
1980	case BUSLOGICCOMMAND_SET_PREEMPT_TIME_ON_BUS:
1981	{
1982	pBusLogic->cbReplyParametersLeft = 0;
1983	pBusLogic->LocalRam.structured.autoSCSIData.uBusOnDelay = pBusLogic->aCommandBuffer[0];
1984	Log(("Bus-on time: %d\n", pBusLogic->aCommandBuffer[0]));
1985	break;
1986	}
1987	case BUSLOGICCOMMAND_SET_TIME_OFF_BUS:
1988	{
1989	pBusLogic->cbReplyParametersLeft = 0;
1990	pBusLogic->LocalRam.structured.autoSCSIData.uBusOffDelay = pBusLogic->aCommandBuffer[0];
1991	Log(("Bus-off time: %d\n", pBusLogic->aCommandBuffer[0]));
1992	break;
1993	}
1994	case BUSLOGICCOMMAND_SET_BUS_TRANSFER_RATE:
1995	{
1996	pBusLogic->cbReplyParametersLeft = 0;
1997	pBusLogic->LocalRam.structured.autoSCSIData.uDMATransferRate = pBusLogic->aCommandBuffer[0];
1998	Log(("Bus transfer rate: %02X\n", pBusLogic->aCommandBuffer[0]));
1999	break;
2000	}
2001	case BUSLOGICCOMMAND_WRITE_BUSMASTER_CHIP_FIFO:
2002	{
2003	RTGCPHYS GCPhysFifoBuf;
2004	Addr24 addr;
2005
2006	pBusLogic->cbReplyParametersLeft = 0;
2007	addr.hi = pBusLogic->aCommandBuffer[0];
2008	addr.mid = pBusLogic->aCommandBuffer[1];
2009	addr.lo = pBusLogic->aCommandBuffer[2];
2010	GCPhysFifoBuf = (RTGCPHYS)ADDR_TO_U32(addr);
2011	Log(("Write busmaster FIFO at: %04X\n", ADDR_TO_U32(addr)));
2012	PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCPhysFifoBuf,
2013	&pBusLogic->LocalRam.u8View[64], 64);
2014	break;
2015	}
2016	case BUSLOGICCOMMAND_READ_BUSMASTER_CHIP_FIFO:
2017	{
2018	RTGCPHYS GCPhysFifoBuf;
2019	Addr24 addr;
2020
2021	pBusLogic->cbReplyParametersLeft = 0;
2022	addr.hi = pBusLogic->aCommandBuffer[0];
2023	addr.mid = pBusLogic->aCommandBuffer[1];
2024	addr.lo = pBusLogic->aCommandBuffer[2];
2025	GCPhysFifoBuf = (RTGCPHYS)ADDR_TO_U32(addr);
2026	Log(("Read busmaster FIFO at: %04X\n", ADDR_TO_U32(addr)));
2027	PDMDevHlpPCIPhysWrite(pBusLogic->CTX_SUFF(pDevIns), GCPhysFifoBuf,
2028	&pBusLogic->LocalRam.u8View[64], 64);
2029	break;
2030	}
2031	default:
2032	AssertMsgFailed(("Invalid command %#x\n", pBusLogic->uOperationCode));
2033	case BUSLOGICCOMMAND_EXT_BIOS_INFO:
2034	case BUSLOGICCOMMAND_UNLOCK_MAILBOX:
2035	/* Commands valid for Adaptec 154xC which we don't handle since
2036	* we pretend being 154xB compatible. Just mark the command as invalid.
2037	*/
2038	Log(("Command %#x not valid for this adapter\n", pBusLogic->uOperationCode));
2039	pBusLogic->cbReplyParametersLeft = 0;
2040	pBusLogic->regStatus \|= BUSLOGIC_REGISTER_STATUS_COMMAND_INVALID;
2041	break;
2042	case BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND: /* Should be handled already. */
2043	AssertMsgFailed(("Invalid mailbox execute state!\n"));
2044	}
2045
2046	Log(("uOperationCode=%#x, cbReplyParametersLeft=%d\n", pBusLogic->uOperationCode, pBusLogic->cbReplyParametersLeft));
2047
2048	/* Set the data in ready bit in the status register in case the command has a reply. */
2049	if (pBusLogic->cbReplyParametersLeft)
2050	pBusLogic->regStatus \|= BUSLOGIC_REGISTER_STATUS_DATA_IN_REGISTER_READY;
2051	else if (!pBusLogic->cbCommandParametersLeft)
2052	buslogicCommandComplete(pBusLogic, fSuppressIrq);
2053
2054	return rc;
2055	}
2056
2057	/**
2058	* Read a register from the BusLogic adapter.
2059	*
2060	* @returns VBox status code.
2061	* @param pBusLogic Pointer to the BusLogic instance data.
2062	* @param iRegister The index of the register to read.
2063	* @param pu32 Where to store the register content.
2064	*/
2065	static int buslogicRegisterRead(PBUSLOGIC pBusLogic, unsigned iRegister, uint32_t *pu32)
2066	{
2067	int rc = VINF_SUCCESS;
2068
2069	switch (iRegister)
2070	{
2071	case BUSLOGIC_REGISTER_STATUS:
2072	{
2073	*pu32 = pBusLogic->regStatus;
2074
2075	/* If the diagnostic active bit is set, we are in a guest-initiated
2076	* hard reset. If the guest reads the status register and waits for
2077	* the host adapter ready bit to be set, we terminate the reset right
2078	* away. However, guests may also expect the reset condition to clear
2079	* automatically after a period of time, in which case we can't show
2080	* the DIAG bit at all.
2081	*/
2082	if (pBusLogic->regStatus & BUSLOGIC_REGISTER_STATUS_DIAGNOSTIC_ACTIVE)
2083	{
2084	uint64_t u64AccessTime = PDMDevHlpTMTimeVirtGetNano(pBusLogic->CTX_SUFF(pDevIns));
2085
2086	pBusLogic->regStatus &= ~BUSLOGIC_REGISTER_STATUS_DIAGNOSTIC_ACTIVE;
2087	pBusLogic->regStatus \|= BUSLOGIC_REGISTER_STATUS_HOST_ADAPTER_READY;
2088
2089	if (u64AccessTime - pBusLogic->u64ResetTime > BUSLOGIC_RESET_DURATION_NS)
2090	{
2091	/* If reset already expired, let the guest see that right away. */
2092	*pu32 = pBusLogic->regStatus;
2093	pBusLogic->u64ResetTime = 0;
2094	}
2095	}
2096	break;
2097	}
2098	case BUSLOGIC_REGISTER_DATAIN:
2099	{
2100	if (pBusLogic->fUseLocalRam)
2101	*pu32 = pBusLogic->LocalRam.u8View[pBusLogic->iReply];
2102	else
2103	*pu32 = pBusLogic->aReplyBuffer[pBusLogic->iReply];
2104
2105	/* Careful about underflow - guest can read data register even if
2106	* no data is available.
2107	*/
2108	if (pBusLogic->cbReplyParametersLeft)
2109	{
2110	pBusLogic->iReply++;
2111	pBusLogic->cbReplyParametersLeft--;
2112	if (!pBusLogic->cbReplyParametersLeft)
2113	{
2114	/*
2115	* Reply finished, set command complete bit, unset data-in ready bit and
2116	* interrupt the guest if enabled.
2117	*/
2118	buslogicCommandComplete(pBusLogic, false);
2119	}
2120	}
2121	LogFlowFunc(("data=%02x, iReply=%d, cbReplyParametersLeft=%u\n", *pu32,
2122	pBusLogic->iReply, pBusLogic->cbReplyParametersLeft));
2123	break;
2124	}
2125	case BUSLOGIC_REGISTER_INTERRUPT:
2126	{
2127	*pu32 = pBusLogic->regInterrupt;
2128	break;
2129	}
2130	case BUSLOGIC_REGISTER_GEOMETRY:
2131	{
2132	*pu32 = pBusLogic->regGeometry;
2133	break;
2134	}
2135	default:
2136	*pu32 = UINT32_C(0xffffffff);
2137	}
2138
2139	Log2(("%s: pu32=%p:{%.*Rhxs} iRegister=%d rc=%Rrc\n",
2140	__FUNCTION__, pu32, 1, pu32, iRegister, rc));
2141
2142	return rc;
2143	}
2144
2145	/**
2146	* Write a value to a register.
2147	*
2148	* @returns VBox status code.
2149	* @param pBusLogic Pointer to the BusLogic instance data.
2150	* @param iRegister The index of the register to read.
2151	* @param uVal The value to write.
2152	*/
2153	static int buslogicRegisterWrite(PBUSLOGIC pBusLogic, unsigned iRegister, uint8_t uVal)
2154	{
2155	int rc = VINF_SUCCESS;
2156
2157	switch (iRegister)
2158	{
2159	case BUSLOGIC_REGISTER_CONTROL:
2160	{
2161	if ((uVal & BUSLOGIC_REGISTER_CONTROL_HARD_RESET) \|\| (uVal & BUSLOGIC_REGISTER_CONTROL_SOFT_RESET))
2162	{
2163	#ifdef IN_RING3
2164	bool fHardReset = !!(uVal & BUSLOGIC_REGISTER_CONTROL_HARD_RESET);
2165
2166	LogRel(("BusLogic: %s reset\n", fHardReset ? "hard" : "soft"));
2167	buslogicR3InitiateReset(pBusLogic, fHardReset);
2168	#else
2169	rc = VINF_IOM_R3_IOPORT_WRITE;
2170	#endif
2171	break;
2172	}
2173
2174	rc = PDMCritSectEnter(&pBusLogic->CritSectIntr, VINF_IOM_R3_IOPORT_WRITE);
2175	if (rc != VINF_SUCCESS)
2176	return rc;
2177
2178	#ifdef LOG_ENABLED
2179	uint32_t cMailboxesReady = ASMAtomicXchgU32(&pBusLogic->cInMailboxesReady, 0);
2180	Log(("%u incoming mailboxes were ready when this interrupt was cleared\n", cMailboxesReady));
2181	#endif
2182
2183	if (uVal & BUSLOGIC_REGISTER_CONTROL_INTERRUPT_RESET)
2184	buslogicClearInterrupt(pBusLogic);
2185
2186	PDMCritSectLeave(&pBusLogic->CritSectIntr);
2187
2188	break;
2189	}
2190	case BUSLOGIC_REGISTER_COMMAND:
2191	{
2192	/* Fast path for mailbox execution command. */
2193	if ((uVal == BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND) && (pBusLogic->uOperationCode == 0xff))
2194	{
2195	/* If there are no mailboxes configured, don't even try to do anything. */
2196	if (pBusLogic->cMailbox) {
2197	ASMAtomicIncU32(&pBusLogic->cMailboxesReady);
2198	if (!ASMAtomicXchgBool(&pBusLogic->fNotificationSend, true))
2199	{
2200	/* Send new notification to the queue. */
2201	PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pBusLogic->CTX_SUFF(pNotifierQueue));
2202	AssertMsg(pItem, ("Allocating item for queue failed\n"));
2203	PDMQueueInsert(pBusLogic->CTX_SUFF(pNotifierQueue), (PPDMQUEUEITEMCORE)pItem);
2204	}
2205	}
2206
2207	return rc;
2208	}
2209
2210	/*
2211	* Check if we are already fetch command parameters from the guest.
2212	* If not we initialize executing a new command.
2213	*/
2214	if (pBusLogic->uOperationCode == 0xff)
2215	{
2216	pBusLogic->uOperationCode = uVal;
2217	pBusLogic->iParameter = 0;
2218
2219	/* Mark host adapter as busy and clear the invalid status bit. */
2220	pBusLogic->regStatus &= ~(BUSLOGIC_REGISTER_STATUS_HOST_ADAPTER_READY \| BUSLOGIC_REGISTER_STATUS_COMMAND_INVALID);
2221
2222	/* Get the number of bytes for parameters from the command code. */
2223	switch (pBusLogic->uOperationCode)
2224	{
2225	case BUSLOGICCOMMAND_TEST_CMDC_INTERRUPT:
2226	case BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_LETTER:
2227	case BUSLOGICCOMMAND_INQUIRE_BOARD_ID:
2228	case BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_3RD_LETTER:
2229	case BUSLOGICCOMMAND_INQUIRE_PCI_HOST_ADAPTER_INFORMATION:
2230	case BUSLOGICCOMMAND_INQUIRE_CONFIGURATION:
2231	case BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_0_TO_7:
2232	case BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_8_TO_15:
2233	case BUSLOGICCOMMAND_INQUIRE_TARGET_DEVICES:
2234	pBusLogic->cbCommandParametersLeft = 0;
2235	break;
2236	case BUSLOGICCOMMAND_MODIFY_IO_ADDRESS:
2237	case BUSLOGICCOMMAND_INQUIRE_EXTENDED_SETUP_INFORMATION:
2238	case BUSLOGICCOMMAND_INQUIRE_SETUP_INFORMATION:
2239	case BUSLOGICCOMMAND_INQUIRE_HOST_ADAPTER_MODEL_NUMBER:
2240	case BUSLOGICCOMMAND_ENABLE_STRICT_ROUND_ROBIN_MODE:
2241	case BUSLOGICCOMMAND_SET_CCB_FORMAT:
2242	case BUSLOGICCOMMAND_INQUIRE_SYNCHRONOUS_PERIOD:
2243	case BUSLOGICCOMMAND_DISABLE_HOST_ADAPTER_INTERRUPT:
2244	case BUSLOGICCOMMAND_ECHO_COMMAND_DATA:
2245	case BUSLOGICCOMMAND_SET_PREEMPT_TIME_ON_BUS:
2246	case BUSLOGICCOMMAND_SET_TIME_OFF_BUS:
2247	case BUSLOGICCOMMAND_SET_BUS_TRANSFER_RATE:
2248	pBusLogic->cbCommandParametersLeft = 1;
2249	break;
2250	case BUSLOGICCOMMAND_FETCH_HOST_ADAPTER_LOCAL_RAM:
2251	pBusLogic->cbCommandParametersLeft = 2;
2252	break;
2253	case BUSLOGICCOMMAND_READ_BUSMASTER_CHIP_FIFO:
2254	case BUSLOGICCOMMAND_WRITE_BUSMASTER_CHIP_FIFO:
2255	pBusLogic->cbCommandParametersLeft = 3;
2256	break;
2257	case BUSLOGICCOMMAND_INITIALIZE_MAILBOX:
2258	pBusLogic->cbCommandParametersLeft = sizeof(RequestInitMbx);
2259	break;
2260	case BUSLOGICCOMMAND_INITIALIZE_EXTENDED_MAILBOX:
2261	pBusLogic->cbCommandParametersLeft = sizeof(RequestInitializeExtendedMailbox);
2262	break;
2263	case BUSLOGICCOMMAND_SET_ADAPTER_OPTIONS:
2264	/* There must be at least one byte following this command. */
2265	pBusLogic->cbCommandParametersLeft = 1;
2266	break;
2267	case BUSLOGICCOMMAND_EXT_BIOS_INFO:
2268	case BUSLOGICCOMMAND_UNLOCK_MAILBOX:
2269	/* Invalid commands. */
2270	pBusLogic->cbCommandParametersLeft = 0;
2271	break;
2272	case BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND: /* Should not come here anymore. */
2273	default:
2274	AssertMsgFailed(("Invalid operation code %#x\n", uVal));
2275	}
2276	}
2277	else
2278	{
2279	#ifndef IN_RING3
2280	/* This command must be executed in R3 as it rehooks the ISA I/O port. */
2281	if (pBusLogic->uOperationCode == BUSLOGICCOMMAND_MODIFY_IO_ADDRESS)
2282	{
2283	rc = VINF_IOM_R3_IOPORT_WRITE;
2284	break;
2285	}
2286	#endif
2287	/*
2288	* The real adapter would set the Command register busy bit in the status register.
2289	* The guest has to wait until it is unset.
2290	* We don't need to do it because the guest does not continue execution while we are in this
2291	* function.
2292	*/
2293	pBusLogic->aCommandBuffer[pBusLogic->iParameter] = uVal;
2294	pBusLogic->iParameter++;
2295	pBusLogic->cbCommandParametersLeft--;
2296	}
2297
2298	/* Start execution of command if there are no parameters left. */
2299	if (!pBusLogic->cbCommandParametersLeft)
2300	{
2301	rc = buslogicProcessCommand(pBusLogic);
2302	AssertMsgRC(rc, ("Processing command failed rc=%Rrc\n", rc));
2303	}
2304	break;
2305	}
2306
2307	/* On BusLogic adapters, the interrupt and geometry registers are R/W.
2308	* That is different from Adaptec 154x where those are read only.
2309	*/
2310	case BUSLOGIC_REGISTER_INTERRUPT:
2311	pBusLogic->regInterrupt = uVal;
2312	break;
2313
2314	case BUSLOGIC_REGISTER_GEOMETRY:
2315	pBusLogic->regGeometry = uVal;
2316	break;
2317
2318	default:
2319	AssertMsgFailed(("Register not available\n"));
2320	rc = VERR_IOM_IOPORT_UNUSED;
2321	}
2322
2323	return rc;
2324	}
2325
2326	/**
2327	* Memory mapped I/O Handler for read operations.
2328	*
2329	* @returns VBox status code.
2330	*
2331	* @param pDevIns The device instance.
2332	* @param pvUser User argument.
2333	* @param GCPhysAddr Physical address (in GC) where the read starts.
2334	* @param pv Where to store the result.
2335	* @param cb Number of bytes read.
2336	*/
2337	PDMBOTHCBDECL(int) buslogicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2338	{
2339	/* the linux driver does not make use of the MMIO area. */
2340	AssertMsgFailed(("MMIO Read\n"));
2341	return VINF_SUCCESS;
2342	}
2343
2344	/**
2345	* Memory mapped I/O Handler for write operations.
2346	*
2347	* @returns VBox status code.
2348	*
2349	* @param pDevIns The device instance.
2350	* @param pvUser User argument.
2351	* @param GCPhysAddr Physical address (in GC) where the read starts.
2352	* @param pv Where to fetch the result.
2353	* @param cb Number of bytes to write.
2354	*/
2355	PDMBOTHCBDECL(int) buslogicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
2356	{
2357	/* the linux driver does not make use of the MMIO area. */
2358	AssertMsgFailed(("MMIO Write\n"));
2359	return VINF_SUCCESS;
2360	}
2361
2362	/**
2363	* Port I/O Handler for IN operations.
2364	*
2365	* @returns VBox status code.
2366	*
2367	* @param pDevIns The device instance.
2368	* @param pvUser User argument.
2369	* @param uPort Port number used for the IN operation.
2370	* @param pu32 Where to store the result.
2371	* @param cb Number of bytes read.
2372	*/
2373	PDMBOTHCBDECL(int) buslogicIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
2374	{
2375	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2376	unsigned iRegister = Port % 4;
2377
2378	Assert(cb == 1);
2379
2380	return buslogicRegisterRead(pBusLogic, iRegister, pu32);
2381	}
2382
2383	/**
2384	* Port I/O Handler for OUT operations.
2385	*
2386	* @returns VBox status code.
2387	*
2388	* @param pDevIns The device instance.
2389	* @param pvUser User argument.
2390	* @param uPort Port number used for the IN operation.
2391	* @param u32 The value to output.
2392	* @param cb The value size in bytes.
2393	*/
2394	PDMBOTHCBDECL(int) buslogicIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2395	{
2396	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2397	int rc = VINF_SUCCESS;
2398	unsigned iRegister = Port % 4;
2399	uint8_t uVal = (uint8_t)u32;
2400
2401	Assert(cb == 1);
2402
2403	rc = buslogicRegisterWrite(pBusLogic, iRegister, (uint8_t)uVal);
2404
2405	Log2(("#%d %s: pvUser=%#p cb=%d u32=%#x Port=%#x rc=%Rrc\n",
2406	pDevIns->iInstance, __FUNCTION__, pvUser, cb, u32, Port, rc));
2407
2408	return rc;
2409	}
2410
2411	#ifdef IN_RING3
2412
2413	static int buslogicR3PrepareBIOSSCSIRequest(PBUSLOGIC pBusLogic)
2414	{
2415	int rc;
2416	PBUSLOGICTASKSTATE pTaskState;
2417	uint32_t uTargetDevice;
2418
2419	rc = RTMemCacheAllocEx(pBusLogic->hTaskCache, (void **)&pTaskState);
2420	AssertMsgRCReturn(rc, ("Getting task from cache failed rc=%Rrc\n", rc), rc);
2421
2422	pTaskState->fBIOS = true;
2423
2424	rc = vboxscsiSetupRequest(&pBusLogic->VBoxSCSI, &pTaskState->PDMScsiRequest, &uTargetDevice);
2425	AssertMsgRCReturn(rc, ("Setting up SCSI request failed rc=%Rrc\n", rc), rc);
2426
2427	pTaskState->PDMScsiRequest.pvUser = pTaskState;
2428
2429	pTaskState->CTX_SUFF(pTargetDevice) = &pBusLogic->aDeviceStates[uTargetDevice];
2430
2431	if (!pTaskState->CTX_SUFF(pTargetDevice)->fPresent)
2432	{
2433	/* Device is not present. */
2434	AssertMsg(pTaskState->PDMScsiRequest.pbCDB[0] == SCSI_INQUIRY,
2435	("Device is not present but command is not inquiry\n"));
2436
2437	SCSIINQUIRYDATA ScsiInquiryData;
2438
2439	memset(&ScsiInquiryData, 0, sizeof(SCSIINQUIRYDATA));
2440	ScsiInquiryData.u5PeripheralDeviceType = SCSI_INQUIRY_DATA_PERIPHERAL_DEVICE_TYPE_UNKNOWN;
2441	ScsiInquiryData.u3PeripheralQualifier = SCSI_INQUIRY_DATA_PERIPHERAL_QUALIFIER_NOT_CONNECTED_NOT_SUPPORTED;
2442
2443	memcpy(pBusLogic->VBoxSCSI.pbBuf, &ScsiInquiryData, 5);
2444
2445	rc = vboxscsiRequestFinished(&pBusLogic->VBoxSCSI, &pTaskState->PDMScsiRequest, SCSI_STATUS_OK);
2446	AssertMsgRCReturn(rc, ("Finishing BIOS SCSI request failed rc=%Rrc\n", rc), rc);
2447
2448	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
2449	}
2450	else
2451	{
2452	LogFlowFunc(("before increment %u\n", pTaskState->CTX_SUFF(pTargetDevice)->cOutstandingRequests));
2453	ASMAtomicIncU32(&pTaskState->CTX_SUFF(pTargetDevice)->cOutstandingRequests);
2454	LogFlowFunc(("after increment %u\n", pTaskState->CTX_SUFF(pTargetDevice)->cOutstandingRequests));
2455
2456	rc = pTaskState->CTX_SUFF(pTargetDevice)->pDrvSCSIConnector->pfnSCSIRequestSend(pTaskState->CTX_SUFF(pTargetDevice)->pDrvSCSIConnector,
2457	&pTaskState->PDMScsiRequest);
2458	AssertMsgRC(rc, ("Sending request to SCSI layer failed rc=%Rrc\n", rc));
2459	}
2460
2461	return rc;
2462	}
2463
2464
2465	/**
2466	* Port I/O Handler for IN operations - BIOS port.
2467	*
2468	* @returns VBox status code.
2469	*
2470	* @param pDevIns The device instance.
2471	* @param pvUser User argument.
2472	* @param uPort Port number used for the IN operation.
2473	* @param pu32 Where to store the result.
2474	* @param cb Number of bytes read.
2475	*/
2476	static DECLCALLBACK(int) buslogicR3BiosIoPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
2477	{
2478	int rc;
2479	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2480
2481	Assert(cb == 1);
2482
2483	rc = vboxscsiReadRegister(&pBusLogic->VBoxSCSI, (Port - BUSLOGIC_BIOS_IO_PORT), pu32);
2484
2485	//Log2(("%s: pu32=%p:{%.*Rhxs} iRegister=%d rc=%Rrc\n",
2486	// __FUNCTION__, pu32, 1, pu32, (Port - BUSLOGIC_BIOS_IO_PORT), rc));
2487
2488	return rc;
2489	}
2490
2491	/**
2492	* Port I/O Handler for OUT operations - BIOS port.
2493	*
2494	* @returns VBox status code.
2495	*
2496	* @param pDevIns The device instance.
2497	* @param pvUser User argument.
2498	* @param uPort Port number used for the IN operation.
2499	* @param u32 The value to output.
2500	* @param cb The value size in bytes.
2501	*/
2502	static DECLCALLBACK(int) buslogicR3BiosIoPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2503	{
2504	int rc;
2505	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2506
2507	Log2(("#%d %s: pvUser=%#p cb=%d u32=%#x Port=%#x\n",
2508	pDevIns->iInstance, __FUNCTION__, pvUser, cb, u32, Port));
2509
2510	Assert(cb == 1);
2511
2512	rc = vboxscsiWriteRegister(&pBusLogic->VBoxSCSI, (Port - BUSLOGIC_BIOS_IO_PORT), (uint8_t)u32);
2513	if (rc == VERR_MORE_DATA)
2514	{
2515	rc = buslogicR3PrepareBIOSSCSIRequest(pBusLogic);
2516	AssertRC(rc);
2517	}
2518	else if (RT_FAILURE(rc))
2519	AssertMsgFailed(("Writing BIOS register failed %Rrc\n", rc));
2520
2521	return VINF_SUCCESS;
2522	}
2523
2524	/**
2525	* Port I/O Handler for primary port range OUT string operations.
2526	* @see FNIOMIOPORTOUTSTRING for details.
2527	*/
2528	static DECLCALLBACK(int) buslogicR3BiosIoPortWriteStr(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, RTGCPTR pGCPtrSrc,
2529	PRTGCUINTREG pcTransfer, unsigned cb)
2530	{
2531	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2532	int rc;
2533
2534	Log2(("#%d %s: pvUser=%#p cb=%d Port=%#x\n",
2535	pDevIns->iInstance, __FUNCTION__, pvUser, cb, Port));
2536
2537	rc = vboxscsiWriteString(pDevIns, &pBusLogic->VBoxSCSI, (Port - BUSLOGIC_BIOS_IO_PORT),
2538	pGCPtrSrc, pcTransfer, cb);
2539	if (rc == VERR_MORE_DATA)
2540	{
2541	rc = buslogicR3PrepareBIOSSCSIRequest(pBusLogic);
2542	AssertRC(rc);
2543	}
2544	else if (RT_FAILURE(rc))
2545	AssertMsgFailed(("Writing BIOS register failed %Rrc\n", rc));
2546
2547	return rc;
2548	}
2549
2550	/**
2551	* Port I/O Handler for primary port range IN string operations.
2552	* @see FNIOMIOPORTINSTRING for details.
2553	*/
2554	static DECLCALLBACK(int) buslogicR3BiosIoPortReadStr(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, RTGCPTR pGCPtrDst,
2555	PRTGCUINTREG pcTransfer, unsigned cb)
2556	{
2557	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2558
2559	LogFlowFunc(("#%d %s: pvUser=%#p cb=%d Port=%#x\n",
2560	pDevIns->iInstance, __FUNCTION__, pvUser, cb, Port));
2561
2562	return vboxscsiReadString(pDevIns, &pBusLogic->VBoxSCSI, (Port - BUSLOGIC_BIOS_IO_PORT),
2563	pGCPtrDst, pcTransfer, cb);
2564	}
2565
2566	/**
2567	* Update the ISA I/O range.
2568	*
2569	* @returns nothing.
2570	* @param pBusLogic Pointer to the BusLogic device instance.
2571	* @param uBaseCode Encoded ISA I/O base; only low 3 bits are used.
2572	*/
2573	static int buslogicR3RegisterISARange(PBUSLOGIC pBusLogic, uint8_t uBaseCode)
2574	{
2575	uint8_t uCode = uBaseCode & MAX_ISA_BASE;
2576	uint16_t uNewBase = g_aISABases[uCode];
2577	int rc = VINF_SUCCESS;
2578
2579	LogFlowFunc(("ISA I/O code %02X, new base %X\n", uBaseCode, uNewBase));
2580
2581	/* Check if the same port range is already registered. */
2582	if (uNewBase != pBusLogic->IOISABase)
2583	{
2584	/* Unregister the old range, if any. */
2585	if (pBusLogic->IOISABase)
2586	rc = PDMDevHlpIOPortDeregister(pBusLogic->CTX_SUFF(pDevIns), pBusLogic->IOISABase, 4);
2587
2588	if (RT_SUCCESS(rc))
2589	{
2590	pBusLogic->IOISABase = 0; /* First mark as unregistered. */
2591	pBusLogic->uISABaseCode = ISA_BASE_DISABLED;
2592
2593	if (uNewBase)
2594	{
2595	/* Register the new range if requested. */
2596	rc = PDMDevHlpIOPortRegister(pBusLogic->CTX_SUFF(pDevIns), uNewBase, 4, NULL,
2597	buslogicIOPortWrite, buslogicIOPortRead,
2598	NULL, NULL,
2599	"BusLogic ISA");
2600	if (RT_SUCCESS(rc))
2601	{
2602	pBusLogic->IOISABase = uNewBase;
2603	pBusLogic->uISABaseCode = uCode;
2604	}
2605	}
2606	}
2607	if (RT_SUCCESS(rc))
2608	{
2609	if (uNewBase)
2610	{
2611	Log(("ISA I/O base: %x\n", uNewBase));
2612	LogRel(("BusLogic: ISA I/O base: %x\n", uNewBase));
2613	}
2614	else
2615	{
2616	Log(("Disabling ISA I/O ports.\n"));
2617	LogRel(("BusLogic: ISA I/O disabled\n"));
2618	}
2619	}
2620
2621	}
2622	return rc;
2623	}
2624
2625	static void buslogicR3WarningDiskFull(PPDMDEVINS pDevIns)
2626	{
2627	int rc;
2628	LogRel(("BusLogic#%d: Host disk full\n", pDevIns->iInstance));
2629	rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND \| VMSETRTERR_FLAGS_NO_WAIT, "DevBusLogic_DISKFULL",
2630	N_("Host system reported disk full. VM execution is suspended. You can resume after freeing some space"));
2631	AssertRC(rc);
2632	}
2633
2634	static void buslogicR3WarningFileTooBig(PPDMDEVINS pDevIns)
2635	{
2636	int rc;
2637	LogRel(("BusLogic#%d: File too big\n", pDevIns->iInstance));
2638	rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND \| VMSETRTERR_FLAGS_NO_WAIT, "DevBusLogic_FILETOOBIG",
2639	N_("Host system reported that the file size limit of the host file system has been exceeded. VM execution is suspended. You need to move your virtual hard disk to a filesystem which allows bigger files"));
2640	AssertRC(rc);
2641	}
2642
2643	static void buslogicR3WarningISCSI(PPDMDEVINS pDevIns)
2644	{
2645	int rc;
2646	LogRel(("BusLogic#%d: iSCSI target unavailable\n", pDevIns->iInstance));
2647	rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND \| VMSETRTERR_FLAGS_NO_WAIT, "DevBusLogic_ISCSIDOWN",
2648	N_("The iSCSI target has stopped responding. VM execution is suspended. You can resume when it is available again"));
2649	AssertRC(rc);
2650	}
2651
2652	static void buslogicR3WarningUnknown(PPDMDEVINS pDevIns, int rc)
2653	{
2654	int rc2;
2655	LogRel(("BusLogic#%d: Unknown but recoverable error has occurred (rc=%Rrc)\n", pDevIns->iInstance, rc));
2656	rc2 = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND \| VMSETRTERR_FLAGS_NO_WAIT, "DevBusLogic_UNKNOWN",
2657	N_("An unknown but recoverable I/O error has occurred (rc=%Rrc). VM execution is suspended. You can resume when the error is fixed"), rc);
2658	AssertRC(rc2);
2659	}
2660
2661	static void buslogicR3RedoSetWarning(PBUSLOGIC pThis, int rc)
2662	{
2663	if (rc == VERR_DISK_FULL)
2664	buslogicR3WarningDiskFull(pThis->CTX_SUFF(pDevIns));
2665	else if (rc == VERR_FILE_TOO_BIG)
2666	buslogicR3WarningFileTooBig(pThis->CTX_SUFF(pDevIns));
2667	else if (rc == VERR_BROKEN_PIPE \|\| rc == VERR_NET_CONNECTION_REFUSED)
2668	{
2669	/* iSCSI connection abort (first error) or failure to reestablish
2670	* connection (second error). Pause VM. On resume we'll retry. */
2671	buslogicR3WarningISCSI(pThis->CTX_SUFF(pDevIns));
2672	}
2673	else
2674	buslogicR3WarningUnknown(pThis->CTX_SUFF(pDevIns), rc);
2675	}
2676
2677
2678	static DECLCALLBACK(int) buslogicR3MmioMap(PPCIDEVICE pPciDev, /unsigned/ int iRegion,
2679	RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
2680	{
2681	PPDMDEVINS pDevIns = pPciDev->pDevIns;
2682	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2683	int rc = VINF_SUCCESS;
2684
2685	Log2(("%s: registering MMIO area at GCPhysAddr=%RGp cb=%u\n", __FUNCTION__, GCPhysAddress, cb));
2686
2687	Assert(cb >= 32);
2688
2689	if (enmType == PCI_ADDRESS_SPACE_MEM)
2690	{
2691	/* We use the assigned size here, because we currently only support page aligned MMIO ranges. */
2692	rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /pvUser/,
2693	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
2694	buslogicMMIOWrite, buslogicMMIORead, "BusLogic MMIO");
2695	if (RT_FAILURE(rc))
2696	return rc;
2697
2698	if (pThis->fR0Enabled)
2699	{
2700	rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /pvUser/,
2701	"buslogicMMIOWrite", "buslogicMMIORead");
2702	if (RT_FAILURE(rc))
2703	return rc;
2704	}
2705
2706	if (pThis->fGCEnabled)
2707	{
2708	rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /pvUser/,
2709	"buslogicMMIOWrite", "buslogicMMIORead");
2710	if (RT_FAILURE(rc))
2711	return rc;
2712	}
2713
2714	pThis->MMIOBase = GCPhysAddress;
2715	}
2716	else if (enmType == PCI_ADDRESS_SPACE_IO)
2717	{
2718	rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, 32,
2719	NULL, buslogicIOPortWrite, buslogicIOPortRead, NULL, NULL, "BusLogic PCI");
2720	if (RT_FAILURE(rc))
2721	return rc;
2722
2723	if (pThis->fR0Enabled)
2724	{
2725	rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, 32,
2726	0, "buslogicIOPortWrite", "buslogicIOPortRead", NULL, NULL, "BusLogic PCI");
2727	if (RT_FAILURE(rc))
2728	return rc;
2729	}
2730
2731	if (pThis->fGCEnabled)
2732	{
2733	rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, 32,
2734	0, "buslogicIOPortWrite", "buslogicIOPortRead", NULL, NULL, "BusLogic PCI");
2735	if (RT_FAILURE(rc))
2736	return rc;
2737	}
2738
2739	pThis->IOPortBase = (RTIOPORT)GCPhysAddress;
2740	}
2741	else
2742	AssertMsgFailed(("Invalid enmType=%d\n", enmType));
2743
2744	return rc;
2745	}
2746
2747	static DECLCALLBACK(int) buslogicR3DeviceSCSIRequestCompleted(PPDMISCSIPORT pInterface, PPDMSCSIREQUEST pSCSIRequest,
2748	int rcCompletion, bool fRedo, int rcReq)
2749	{
2750	int rc;
2751	PBUSLOGICTASKSTATE pTaskState = (PBUSLOGICTASKSTATE)pSCSIRequest->pvUser;
2752	PBUSLOGICDEVICE pBusLogicDevice = pTaskState->CTX_SUFF(pTargetDevice);
2753	PBUSLOGIC pBusLogic = pBusLogicDevice->CTX_SUFF(pBusLogic);
2754
2755	LogFlowFunc(("before decrement %u\n", pBusLogicDevice->cOutstandingRequests));
2756	ASMAtomicDecU32(&pBusLogicDevice->cOutstandingRequests);
2757	LogFlowFunc(("after decrement %u\n", pBusLogicDevice->cOutstandingRequests));
2758
2759	if (fRedo)
2760	{
2761	if (!pTaskState->fBIOS)
2762	{
2763	buslogicR3DataBufferFree(pTaskState);
2764
2765	if (pTaskState->pbSenseBuffer)
2766	buslogicR3SenseBufferFree(pTaskState, false /* fCopy */);
2767	}
2768
2769	/* Add to the list. */
2770	do
2771	{
2772	pTaskState->pRedoNext = ASMAtomicReadPtrT(&pBusLogic->pTasksRedoHead, PBUSLOGICTASKSTATE);
2773	} while (!ASMAtomicCmpXchgPtr(&pBusLogic->pTasksRedoHead, pTaskState, pTaskState->pRedoNext));
2774
2775	/* Suspend the VM if not done already. */
2776	if (!ASMAtomicXchgBool(&pBusLogic->fRedo, true))
2777	buslogicR3RedoSetWarning(pBusLogic, rcReq);
2778	}
2779	else
2780	{
2781	if (pTaskState->fBIOS)
2782	{
2783	rc = vboxscsiRequestFinished(&pBusLogic->VBoxSCSI, pSCSIRequest, rcCompletion);
2784	AssertMsgRC(rc, ("Finishing BIOS SCSI request failed rc=%Rrc\n", rc));
2785	}
2786	else
2787	{
2788	buslogicR3DataBufferFree(pTaskState);
2789
2790	if (pTaskState->pbSenseBuffer)
2791	buslogicR3SenseBufferFree(pTaskState, (rcCompletion != SCSI_STATUS_OK));
2792
2793	if (rcCompletion == SCSI_STATUS_OK)
2794	buslogicR3SendIncomingMailbox(pBusLogic, pTaskState,
2795	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_CMD_COMPLETED,
2796	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_OPERATION_GOOD,
2797	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITHOUT_ERROR);
2798	else if (rcCompletion == SCSI_STATUS_CHECK_CONDITION)
2799	buslogicR3SendIncomingMailbox(pBusLogic, pTaskState,
2800	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_CMD_COMPLETED,
2801	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_CHECK_CONDITION,
2802	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITH_ERROR);
2803	else
2804	AssertMsgFailed(("invalid completion status %d\n", rcCompletion));
2805	}
2806	#ifdef LOG_ENABLED
2807	buslogicR3DumpCCBInfo(&pTaskState->CommandControlBlockGuest, pTaskState->fIs24Bit);
2808	#endif
2809
2810	/* Remove task from the cache. */
2811	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
2812	}
2813
2814	if (pBusLogicDevice->cOutstandingRequests == 0 && pBusLogic->fSignalIdle)
2815	PDMDevHlpAsyncNotificationCompleted(pBusLogic->pDevInsR3);
2816
2817	return VINF_SUCCESS;
2818	}
2819
2820	static DECLCALLBACK(int) buslogicR3QueryDeviceLocation(PPDMISCSIPORT pInterface, const char **ppcszController,
2821	uint32_t piInstance, uint32_t piLUN)
2822	{
2823	PBUSLOGICDEVICE pBusLogicDevice = PDMISCSIPORT_2_PBUSLOGICDEVICE(pInterface);
2824	PPDMDEVINS pDevIns = pBusLogicDevice->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);
2825
2826	AssertPtrReturn(ppcszController, VERR_INVALID_POINTER);
2827	AssertPtrReturn(piInstance, VERR_INVALID_POINTER);
2828	AssertPtrReturn(piLUN, VERR_INVALID_POINTER);
2829
2830	*ppcszController = pDevIns->pReg->szName;
2831	*piInstance = pDevIns->iInstance;
2832	*piLUN = pBusLogicDevice->iLUN;
2833
2834	return VINF_SUCCESS;
2835	}
2836
2837	static int buslogicR3DeviceSCSIRequestSetup(PBUSLOGIC pBusLogic, PBUSLOGICTASKSTATE pTaskState)
2838	{
2839	int rc = VINF_SUCCESS;
2840	uint8_t uTargetIdCCB;
2841	PBUSLOGICDEVICE pTargetDevice;
2842
2843	/* Fetch the CCB from guest memory. */
2844	/** @todo How much do we really have to read? */
2845	RTGCPHYS GCPhysAddrCCB = (RTGCPHYS)pTaskState->MailboxGuest.u32PhysAddrCCB;
2846	PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrCCB,
2847	&pTaskState->CommandControlBlockGuest, sizeof(CCB32));
2848
2849	uTargetIdCCB = pTaskState->fIs24Bit ? pTaskState->CommandControlBlockGuest.o.uTargetId : pTaskState->CommandControlBlockGuest.n.uTargetId;
2850	pTargetDevice = &pBusLogic->aDeviceStates[uTargetIdCCB];
2851	pTaskState->CTX_SUFF(pTargetDevice) = pTargetDevice;
2852
2853	#ifdef LOG_ENABLED
2854	buslogicR3DumpCCBInfo(&pTaskState->CommandControlBlockGuest, pTaskState->fIs24Bit);
2855	#endif
2856
2857	/* Alloc required buffers. */
2858	rc = buslogicR3DataBufferAlloc(pTaskState);
2859	AssertMsgRC(rc, ("Alloc failed rc=%Rrc\n", rc));
2860
2861	rc = buslogicR3SenseBufferAlloc(pTaskState);
2862	AssertMsgRC(rc, ("Mapping sense buffer failed rc=%Rrc\n", rc));
2863
2864	/* Check if device is present on bus. If not return error immediately and don't process this further. */
2865	if (!pBusLogic->aDeviceStates[uTargetIdCCB].fPresent)
2866	{
2867	buslogicR3DataBufferFree(pTaskState);
2868
2869	if (pTaskState->pbSenseBuffer)
2870	buslogicR3SenseBufferFree(pTaskState, true);
2871
2872	buslogicR3SendIncomingMailbox(pBusLogic, pTaskState,
2873	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_SCSI_SELECTION_TIMEOUT,
2874	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_OPERATION_GOOD,
2875	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITH_ERROR);
2876
2877	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
2878	}
2879	else
2880	{
2881	/* Setup SCSI request. */
2882	pTaskState->PDMScsiRequest.uLogicalUnit = pTaskState->fIs24Bit ? pTaskState->CommandControlBlockGuest.o.uLogicalUnit
2883	: pTaskState->CommandControlBlockGuest.n.uLogicalUnit;
2884
2885	if (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_UNKNOWN)
2886	pTaskState->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_UNKNOWN;
2887	else if (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_IN)
2888	pTaskState->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_FROM_DEVICE;
2889	else if (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_OUT)
2890	pTaskState->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_TO_DEVICE;
2891	else if (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_NO_DATA)
2892	pTaskState->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_NONE;
2893	else
2894	AssertMsgFailed(("Invalid data direction type %d\n", pTaskState->CommandControlBlockGuest.c.uDataDirection));
2895
2896	pTaskState->PDMScsiRequest.cbCDB = pTaskState->CommandControlBlockGuest.c.cbCDB;
2897	pTaskState->PDMScsiRequest.pbCDB = pTaskState->CommandControlBlockGuest.c.abCDB;
2898	if (pTaskState->DataSeg.cbSeg)
2899	{
2900	pTaskState->PDMScsiRequest.cbScatterGather = pTaskState->DataSeg.cbSeg;
2901	pTaskState->PDMScsiRequest.cScatterGatherEntries = 1;
2902	pTaskState->PDMScsiRequest.paScatterGatherHead = &pTaskState->DataSeg;
2903	}
2904	else
2905	{
2906	pTaskState->PDMScsiRequest.cbScatterGather = 0;
2907	pTaskState->PDMScsiRequest.cScatterGatherEntries = 0;
2908	pTaskState->PDMScsiRequest.paScatterGatherHead = NULL;
2909	}
2910	pTaskState->PDMScsiRequest.cbSenseBuffer = buslogicR3ConvertSenseBufferLength(pTaskState->CommandControlBlockGuest.c.cbSenseData);
2911	pTaskState->PDMScsiRequest.pbSenseBuffer = pTaskState->pbSenseBuffer;
2912	pTaskState->PDMScsiRequest.pvUser = pTaskState;
2913
2914	ASMAtomicIncU32(&pTargetDevice->cOutstandingRequests);
2915	rc = pTargetDevice->pDrvSCSIConnector->pfnSCSIRequestSend(pTargetDevice->pDrvSCSIConnector, &pTaskState->PDMScsiRequest);
2916	AssertMsgRC(rc, ("Sending request to SCSI layer failed rc=%Rrc\n", rc));
2917	}
2918
2919	return rc;
2920	}
2921
2922	/**
2923	* Read a mailbox from guest memory. Convert 24-bit mailboxes to
2924	* 32-bit format.
2925	*
2926	* @returns Mailbox guest physical address.
2927	* @param pBusLogic Pointer to the BusLogic instance data.
2928	* @param pTaskStat Pointer to the task state being set up.
2929	*/
2930	static RTGCPHYS buslogicR3ReadOutgoingMailbox(PBUSLOGIC pBusLogic, PBUSLOGICTASKSTATE pTaskState)
2931	{
2932	RTGCPHYS GCMailbox;
2933
2934	if (pBusLogic->fMbxIs24Bit)
2935	{
2936	Mailbox24 Mbx24;
2937
2938	GCMailbox = pBusLogic->GCPhysAddrMailboxOutgoingBase + (pBusLogic->uMailboxOutgoingPositionCurrent * sizeof(Mailbox24));
2939	PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCMailbox, &Mbx24, sizeof(Mailbox24));
2940	pTaskState->MailboxGuest.u32PhysAddrCCB = ADDR_TO_U32(Mbx24.aPhysAddrCCB);
2941	pTaskState->MailboxGuest.u.out.uActionCode = Mbx24.uCmdState;
2942	}
2943	else
2944	{
2945	GCMailbox = pBusLogic->GCPhysAddrMailboxOutgoingBase + (pBusLogic->uMailboxOutgoingPositionCurrent * sizeof(Mailbox32));
2946	PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCMailbox, &pTaskState->MailboxGuest, sizeof(Mailbox32));
2947	}
2948
2949	return GCMailbox;
2950	}
2951
2952	/**
2953	* Read mailbox from the guest and execute command.
2954	*
2955	* @returns VBox status code.
2956	* @param pBusLogic Pointer to the BusLogic instance data.
2957	*/
2958	static int buslogicR3ProcessMailboxNext(PBUSLOGIC pBusLogic)
2959	{
2960	PBUSLOGICTASKSTATE pTaskState = NULL;
2961	RTGCPHYS GCPhysAddrMailboxCurrent;
2962	int rc;
2963
2964	rc = RTMemCacheAllocEx(pBusLogic->hTaskCache, (void **)&pTaskState);
2965	AssertMsgReturn(RT_SUCCESS(rc) && (pTaskState != NULL), ("Failed to get task state from cache\n"), rc);
2966
2967	pTaskState->fBIOS = false;
2968	pTaskState->fIs24Bit = pBusLogic->fMbxIs24Bit;
2969	pTaskState->cbSGEntry = pBusLogic->fMbxIs24Bit ? sizeof(SGE24) : sizeof(SGE32);
2970
2971	if (!pBusLogic->fStrictRoundRobinMode)
2972	{
2973	/* Search for a filled mailbox - stop if we have scanned all mailboxes. */
2974	uint8_t uMailboxPosCur = pBusLogic->uMailboxOutgoingPositionCurrent;
2975
2976	do
2977	{
2978	/* Fetch mailbox from guest memory. */
2979	GCPhysAddrMailboxCurrent = buslogicR3ReadOutgoingMailbox(pBusLogic,pTaskState);
2980
2981	/* Check the next mailbox. */
2982	buslogicR3OutgoingMailboxAdvance(pBusLogic);
2983	} while ( pTaskState->MailboxGuest.u.out.uActionCode == BUSLOGIC_MAILBOX_OUTGOING_ACTION_FREE
2984	&& uMailboxPosCur != pBusLogic->uMailboxOutgoingPositionCurrent);
2985	}
2986	else
2987	{
2988	/* Fetch mailbox from guest memory. */
2989	GCPhysAddrMailboxCurrent = buslogicR3ReadOutgoingMailbox(pBusLogic,pTaskState);
2990	}
2991
2992	/*
2993	* Check if the mailbox is actually loaded.
2994	* It might be possible that the guest notified us without
2995	* a loaded mailbox. Do nothing in that case but leave a
2996	* log entry.
2997	*/
2998	if (pTaskState->MailboxGuest.u.out.uActionCode == BUSLOGIC_MAILBOX_OUTGOING_ACTION_FREE)
2999	{
3000	Log(("No loaded mailbox left\n"));
3001	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
3002	return VERR_NO_DATA;
3003	}
3004
3005	LogFlow(("Got loaded mailbox at slot %u, CCB phys %RGp\n", pBusLogic->uMailboxOutgoingPositionCurrent, (RTGCPHYS)pTaskState->MailboxGuest.u32PhysAddrCCB));
3006	#ifdef LOG_ENABLED
3007	buslogicR3DumpMailboxInfo(&pTaskState->MailboxGuest, true);
3008	#endif
3009
3010	/* We got the mailbox, mark it as free in the guest. */
3011	uint8_t uActionCode = BUSLOGIC_MAILBOX_OUTGOING_ACTION_FREE;
3012	unsigned uCodeOffs = pTaskState->fIs24Bit ? RT_OFFSETOF(Mailbox24, uCmdState) : RT_OFFSETOF(Mailbox32, u.out.uActionCode);
3013	PDMDevHlpPCIPhysWrite(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrMailboxCurrent + uCodeOffs, &uActionCode, sizeof(uActionCode));
3014
3015	if (pTaskState->MailboxGuest.u.out.uActionCode == BUSLOGIC_MAILBOX_OUTGOING_ACTION_START_COMMAND)
3016	rc = buslogicR3DeviceSCSIRequestSetup(pBusLogic, pTaskState);
3017	else if (pTaskState->MailboxGuest.u.out.uActionCode == BUSLOGIC_MAILBOX_OUTGOING_ACTION_ABORT_COMMAND)
3018	{
3019	AssertMsgFailed(("Not implemented yet\n"));
3020	}
3021	else
3022	AssertMsgFailed(("Invalid outgoing mailbox action code %u\n", pTaskState->MailboxGuest.u.out.uActionCode));
3023
3024	AssertRC(rc);
3025
3026	/* Advance to the next mailbox. */
3027	if (pBusLogic->fStrictRoundRobinMode)
3028	buslogicR3OutgoingMailboxAdvance(pBusLogic);
3029
3030	return rc;
3031	}
3032
3033	/**
3034	* Transmit queue consumer
3035	* Queue a new async task.
3036	*
3037	* @returns Success indicator.
3038	* If false the item will not be removed and the flushing will stop.
3039	* @param pDevIns The device instance.
3040	* @param pItem The item to consume. Upon return this item will be freed.
3041	*/
3042	static DECLCALLBACK(bool) buslogicR3NotifyQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
3043	{
3044	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3045
3046	/* Reset notification send flag now. */
3047	Assert(pBusLogic->fNotificationSend);
3048	ASMAtomicXchgBool(&pBusLogic->fNotificationSend, false);
3049	ASMAtomicXchgU32(&pBusLogic->cMailboxesReady, 0); /** @todo Actually not required anymore but to stay compatible with older saved states. */
3050
3051	/* Process mailboxes. */
3052	int rc;
3053	do
3054	{
3055	rc = buslogicR3ProcessMailboxNext(pBusLogic);
3056	AssertMsg(RT_SUCCESS(rc) \|\| rc == VERR_NO_DATA, ("Processing mailbox failed rc=%Rrc\n", rc));
3057	} while (RT_SUCCESS(rc));
3058
3059	return true;
3060	}
3061
3062	/**
3063	* Kicks the controller to process pending tasks after the VM was resumed
3064	* or loaded from a saved state.
3065	*
3066	* @returns nothing.
3067	* @param pThis The BusLogic device instance.
3068	*/
3069	static void buslogicR3Kick(PBUSLOGIC pThis)
3070	{
3071	if (pThis->fRedo)
3072	{
3073	pThis->fRedo = false;
3074	if (pThis->VBoxSCSI.fBusy)
3075	{
3076
3077	/* The BIOS had a request active when we got suspended. Resume it. */
3078	int rc = buslogicR3PrepareBIOSSCSIRequest(pThis);
3079	AssertRC(rc);
3080	}
3081	else
3082	{
3083	/* Queue all pending tasks again. */
3084	PBUSLOGICTASKSTATE pTaskState = pThis->pTasksRedoHead;
3085
3086	pThis->pTasksRedoHead = NULL;
3087
3088	while (pTaskState)
3089	{
3090	PBUSLOGICTASKSTATE pCur = pTaskState;
3091
3092	int rc = buslogicR3DeviceSCSIRequestSetup(pThis, pCur);
3093	AssertRC(rc);
3094
3095	pTaskState = pTaskState->pRedoNext;
3096	}
3097	}
3098	}
3099	}
3100
3101	/** @callback_method_impl{FNSSMDEVLIVEEXEC} */
3102	static DECLCALLBACK(int) buslogicR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
3103	{
3104	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3105
3106	/* Save the device config. */
3107	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDeviceStates); i++)
3108	SSMR3PutBool(pSSM, pThis->aDeviceStates[i].fPresent);
3109
3110	return VINF_SSM_DONT_CALL_AGAIN;
3111	}
3112
3113	/** @callback_method_impl{FNSSMDEVSAVEEXEC} */
3114	static DECLCALLBACK(int) buslogicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3115	{
3116	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3117
3118	/* Every device first. */
3119	for (unsigned i = 0; i < RT_ELEMENTS(pBusLogic->aDeviceStates); i++)
3120	{
3121	PBUSLOGICDEVICE pDevice = &pBusLogic->aDeviceStates[i];
3122
3123	AssertMsg(!pDevice->cOutstandingRequests,
3124	("There are still outstanding requests on this device\n"));
3125	SSMR3PutBool(pSSM, pDevice->fPresent);
3126	SSMR3PutU32(pSSM, pDevice->cOutstandingRequests);
3127	}
3128	/* Now the main device state. */
3129	SSMR3PutU8 (pSSM, pBusLogic->regStatus);
3130	SSMR3PutU8 (pSSM, pBusLogic->regInterrupt);
3131	SSMR3PutU8 (pSSM, pBusLogic->regGeometry);
3132	SSMR3PutMem (pSSM, &pBusLogic->LocalRam, sizeof(pBusLogic->LocalRam));
3133	SSMR3PutU8 (pSSM, pBusLogic->uOperationCode);
3134	SSMR3PutMem (pSSM, &pBusLogic->aCommandBuffer, sizeof(pBusLogic->aCommandBuffer));
3135	SSMR3PutU8 (pSSM, pBusLogic->iParameter);
3136	SSMR3PutU8 (pSSM, pBusLogic->cbCommandParametersLeft);
3137	SSMR3PutBool (pSSM, pBusLogic->fUseLocalRam);
3138	SSMR3PutMem (pSSM, pBusLogic->aReplyBuffer, sizeof(pBusLogic->aReplyBuffer));
3139	SSMR3PutU8 (pSSM, pBusLogic->iReply);
3140	SSMR3PutU8 (pSSM, pBusLogic->cbReplyParametersLeft);
3141	SSMR3PutBool (pSSM, pBusLogic->fIRQEnabled);
3142	SSMR3PutU8 (pSSM, pBusLogic->uISABaseCode);
3143	SSMR3PutU32 (pSSM, pBusLogic->cMailbox);
3144	SSMR3PutBool (pSSM, pBusLogic->fMbxIs24Bit);
3145	SSMR3PutGCPhys(pSSM, pBusLogic->GCPhysAddrMailboxOutgoingBase);
3146	SSMR3PutU32 (pSSM, pBusLogic->uMailboxOutgoingPositionCurrent);
3147	SSMR3PutU32 (pSSM, pBusLogic->cMailboxesReady);
3148	SSMR3PutBool (pSSM, pBusLogic->fNotificationSend);
3149	SSMR3PutGCPhys(pSSM, pBusLogic->GCPhysAddrMailboxIncomingBase);
3150	SSMR3PutU32 (pSSM, pBusLogic->uMailboxIncomingPositionCurrent);
3151	SSMR3PutBool (pSSM, pBusLogic->fStrictRoundRobinMode);
3152	SSMR3PutBool (pSSM, pBusLogic->fExtendedLunCCBFormat);
3153	/* Now the data for the BIOS interface. */
3154	SSMR3PutU8 (pSSM, pBusLogic->VBoxSCSI.regIdentify);
3155	SSMR3PutU8 (pSSM, pBusLogic->VBoxSCSI.uTargetDevice);
3156	SSMR3PutU8 (pSSM, pBusLogic->VBoxSCSI.uTxDir);
3157	SSMR3PutU8 (pSSM, pBusLogic->VBoxSCSI.cbCDB);
3158	SSMR3PutMem (pSSM, pBusLogic->VBoxSCSI.abCDB, sizeof(pBusLogic->VBoxSCSI.abCDB));
3159	SSMR3PutU8 (pSSM, pBusLogic->VBoxSCSI.iCDB);
3160	SSMR3PutU32 (pSSM, pBusLogic->VBoxSCSI.cbBuf);
3161	SSMR3PutU32 (pSSM, pBusLogic->VBoxSCSI.iBuf);
3162	SSMR3PutBool (pSSM, pBusLogic->VBoxSCSI.fBusy);
3163	SSMR3PutU8 (pSSM, pBusLogic->VBoxSCSI.enmState);
3164	if (pBusLogic->VBoxSCSI.cbBuf)
3165	SSMR3PutMem(pSSM, pBusLogic->VBoxSCSI.pbBuf, pBusLogic->VBoxSCSI.cbBuf);
3166
3167	/*
3168	* Save the physical addresses of the command control blocks of still pending tasks.
3169	* They are processed again on resume.
3170	*
3171	* The number of pending tasks needs to be determined first.
3172	*/
3173	uint32_t cTasks = 0;
3174
3175	PBUSLOGICTASKSTATE pTaskState = pBusLogic->pTasksRedoHead;
3176	if (pBusLogic->fRedo)
3177	{
3178	while (pTaskState)
3179	{
3180	cTasks++;
3181	pTaskState = pTaskState->pRedoNext;
3182	}
3183	}
3184	SSMR3PutU32(pSSM, cTasks);
3185
3186	/* Write the address of every task now. */
3187	pTaskState = pBusLogic->pTasksRedoHead;
3188	while (pTaskState)
3189	{
3190	SSMR3PutU32(pSSM, pTaskState->MailboxGuest.u32PhysAddrCCB);
3191	pTaskState = pTaskState->pRedoNext;
3192	}
3193
3194	return SSMR3PutU32(pSSM, ~0);
3195	}
3196
3197	/** @callback_method_impl{FNSSMDEVLOADDONE} */
3198	static DECLCALLBACK(int) buslogicR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3199	{
3200	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3201
3202	buslogicR3RegisterISARange(pThis, pThis->uISABaseCode);
3203	buslogicR3Kick(pThis);
3204	return VINF_SUCCESS;
3205	}
3206
3207	/** @callback_method_impl{FNSSMDEVLOADEXEC} */
3208	static DECLCALLBACK(int) buslogicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3209	{
3210	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3211	int rc = VINF_SUCCESS;
3212
3213	/* We support saved states only from this and older versions. */
3214	if (uVersion > BUSLOGIC_SAVED_STATE_MINOR_VERSION)
3215	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3216
3217	/* Every device first. */
3218	for (unsigned i = 0; i < RT_ELEMENTS(pBusLogic->aDeviceStates); i++)
3219	{
3220	PBUSLOGICDEVICE pDevice = &pBusLogic->aDeviceStates[i];
3221
3222	AssertMsg(!pDevice->cOutstandingRequests,
3223	("There are still outstanding requests on this device\n"));
3224	bool fPresent;
3225	rc = SSMR3GetBool(pSSM, &fPresent);
3226	AssertRCReturn(rc, rc);
3227	if (pDevice->fPresent != fPresent)
3228	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Target %u config mismatch: config=%RTbool state=%RTbool"), i, pDevice->fPresent, fPresent);
3229
3230	if (uPass == SSM_PASS_FINAL)
3231	SSMR3GetU32(pSSM, (uint32_t *)&pDevice->cOutstandingRequests);
3232	}
3233
3234	if (uPass != SSM_PASS_FINAL)
3235	return VINF_SUCCESS;
3236
3237	/* Now the main device state. */
3238	SSMR3GetU8 (pSSM, (uint8_t *)&pBusLogic->regStatus);
3239	SSMR3GetU8 (pSSM, (uint8_t *)&pBusLogic->regInterrupt);
3240	SSMR3GetU8 (pSSM, (uint8_t *)&pBusLogic->regGeometry);
3241	SSMR3GetMem (pSSM, &pBusLogic->LocalRam, sizeof(pBusLogic->LocalRam));
3242	SSMR3GetU8 (pSSM, &pBusLogic->uOperationCode);
3243	SSMR3GetMem (pSSM, &pBusLogic->aCommandBuffer, sizeof(pBusLogic->aCommandBuffer));
3244	SSMR3GetU8 (pSSM, &pBusLogic->iParameter);
3245	SSMR3GetU8 (pSSM, &pBusLogic->cbCommandParametersLeft);
3246	SSMR3GetBool (pSSM, &pBusLogic->fUseLocalRam);
3247	SSMR3GetMem (pSSM, pBusLogic->aReplyBuffer, sizeof(pBusLogic->aReplyBuffer));
3248	SSMR3GetU8 (pSSM, &pBusLogic->iReply);
3249	SSMR3GetU8 (pSSM, &pBusLogic->cbReplyParametersLeft);
3250	SSMR3GetBool (pSSM, &pBusLogic->fIRQEnabled);
3251	SSMR3GetU8 (pSSM, &pBusLogic->uISABaseCode);
3252	SSMR3GetU32 (pSSM, &pBusLogic->cMailbox);
3253	if (uVersion > BUSLOGIC_SAVED_STATE_MINOR_PRE_24BIT_MBOX)
3254	SSMR3GetBool (pSSM, &pBusLogic->fMbxIs24Bit);
3255	SSMR3GetGCPhys(pSSM, &pBusLogic->GCPhysAddrMailboxOutgoingBase);
3256	SSMR3GetU32 (pSSM, &pBusLogic->uMailboxOutgoingPositionCurrent);
3257	SSMR3GetU32 (pSSM, (uint32_t *)&pBusLogic->cMailboxesReady);
3258	SSMR3GetBool (pSSM, (bool *)&pBusLogic->fNotificationSend);
3259	SSMR3GetGCPhys(pSSM, &pBusLogic->GCPhysAddrMailboxIncomingBase);
3260	SSMR3GetU32 (pSSM, &pBusLogic->uMailboxIncomingPositionCurrent);
3261	SSMR3GetBool (pSSM, &pBusLogic->fStrictRoundRobinMode);
3262	SSMR3GetBool (pSSM, &pBusLogic->fExtendedLunCCBFormat);
3263	/* Now the data for the BIOS interface. */
3264	SSMR3GetU8 (pSSM, &pBusLogic->VBoxSCSI.regIdentify);
3265	SSMR3GetU8 (pSSM, &pBusLogic->VBoxSCSI.uTargetDevice);
3266	SSMR3GetU8 (pSSM, &pBusLogic->VBoxSCSI.uTxDir);
3267	SSMR3GetU8 (pSSM, &pBusLogic->VBoxSCSI.cbCDB);
3268	SSMR3GetMem (pSSM, pBusLogic->VBoxSCSI.abCDB, sizeof(pBusLogic->VBoxSCSI.abCDB));
3269	SSMR3GetU8 (pSSM, &pBusLogic->VBoxSCSI.iCDB);
3270	SSMR3GetU32 (pSSM, &pBusLogic->VBoxSCSI.cbBuf);
3271	SSMR3GetU32 (pSSM, &pBusLogic->VBoxSCSI.iBuf);
3272	SSMR3GetBool(pSSM, (bool *)&pBusLogic->VBoxSCSI.fBusy);
3273	SSMR3GetU8 (pSSM, (uint8_t *)&pBusLogic->VBoxSCSI.enmState);
3274	if (pBusLogic->VBoxSCSI.cbBuf)
3275	{
3276	pBusLogic->VBoxSCSI.pbBuf = (uint8_t *)RTMemAllocZ(pBusLogic->VBoxSCSI.cbBuf);
3277	if (!pBusLogic->VBoxSCSI.pbBuf)
3278	{
3279	LogRel(("BusLogic: Out of memory during restore.\n"));
3280	return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY,
3281	N_("BusLogic: Out of memory during restore\n"));
3282	}
3283	SSMR3GetMem(pSSM, pBusLogic->VBoxSCSI.pbBuf, pBusLogic->VBoxSCSI.cbBuf);
3284	}
3285
3286	if (pBusLogic->VBoxSCSI.fBusy)
3287	pBusLogic->fRedo = true;
3288
3289	if (uVersion > BUSLOGIC_SAVED_STATE_MINOR_PRE_ERROR_HANDLING)
3290	{
3291	/* Check if there are pending tasks saved. */
3292	uint32_t cTasks = 0;
3293
3294	SSMR3GetU32(pSSM, &cTasks);
3295
3296	if (cTasks)
3297	pBusLogic->fRedo = true;
3298
3299	for (uint32_t i = 0; i < cTasks; i++)
3300	{
3301	PBUSLOGICTASKSTATE pTaskState = (PBUSLOGICTASKSTATE)RTMemCacheAlloc(pBusLogic->hTaskCache);
3302	if (!pTaskState)
3303	{
3304	rc = VERR_NO_MEMORY;
3305	break;
3306	}
3307
3308	rc = SSMR3GetU32(pSSM, &pTaskState->MailboxGuest.u32PhysAddrCCB);
3309	if (RT_FAILURE(rc))
3310	{
3311	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
3312	break;
3313	}
3314
3315	/* Link into the list. */
3316	pTaskState->pRedoNext = pBusLogic->pTasksRedoHead;
3317	pBusLogic->pTasksRedoHead = pTaskState;
3318	}
3319	}
3320
3321	if (RT_SUCCESS(rc))
3322	{
3323	uint32_t u32;
3324	rc = SSMR3GetU32(pSSM, &u32);
3325	if (RT_SUCCESS(rc))
3326	AssertMsgReturn(u32 == ~0U, ("%#x\n", u32), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
3327	}
3328
3329	return rc;
3330	}
3331
3332	/**
3333	* Gets the pointer to the status LED of a device - called from the SCSI driver.
3334	*
3335	* @returns VBox status code.
3336	* @param pInterface Pointer to the interface structure containing the called function pointer.
3337	* @param iLUN The unit which status LED we desire. Always 0 here as the driver
3338	* doesn't know about other LUN's.
3339	* @param ppLed Where to store the LED pointer.
3340	*/
3341	static DECLCALLBACK(int) buslogicR3DeviceQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
3342	{
3343	PBUSLOGICDEVICE pDevice = PDMILEDPORTS_2_PBUSLOGICDEVICE(pInterface);
3344	if (iLUN == 0)
3345	{
3346	*ppLed = &pDevice->Led;
3347	Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
3348	return VINF_SUCCESS;
3349	}
3350	return VERR_PDM_LUN_NOT_FOUND;
3351	}
3352
3353	/**
3354	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
3355	*/
3356	static DECLCALLBACK(void ) buslogicR3DeviceQueryInterface(PPDMIBASE pInterface, const char pszIID)
3357	{
3358	PBUSLOGICDEVICE pDevice = PDMIBASE_2_PBUSLOGICDEVICE(pInterface);
3359	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevice->IBase);
3360	PDMIBASE_RETURN_INTERFACE(pszIID, PDMISCSIPORT, &pDevice->ISCSIPort);
3361	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pDevice->ILed);
3362	return NULL;
3363	}
3364
3365	/**
3366	* Gets the pointer to the status LED of a unit.
3367	*
3368	* @returns VBox status code.
3369	* @param pInterface Pointer to the interface structure containing the called function pointer.
3370	* @param iLUN The unit which status LED we desire.
3371	* @param ppLed Where to store the LED pointer.
3372	*/
3373	static DECLCALLBACK(int) buslogicR3StatusQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
3374	{
3375	PBUSLOGIC pBusLogic = PDMILEDPORTS_2_PBUSLOGIC(pInterface);
3376	if (iLUN < BUSLOGIC_MAX_DEVICES)
3377	{
3378	*ppLed = &pBusLogic->aDeviceStates[iLUN].Led;
3379	Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
3380	return VINF_SUCCESS;
3381	}
3382	return VERR_PDM_LUN_NOT_FOUND;
3383	}
3384
3385	/**
3386	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
3387	*/
3388	static DECLCALLBACK(void ) buslogicR3StatusQueryInterface(PPDMIBASE pInterface, const char pszIID)
3389	{
3390	PBUSLOGIC pThis = PDMIBASE_2_PBUSLOGIC(pInterface);
3391	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
3392	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
3393	return NULL;
3394	}
3395
3396	/**
3397	* BusLogic debugger info callback.
3398	*
3399	* @param pDevIns The device instance.
3400	* @param pHlp The output helpers.
3401	* @param pszArgs The arguments.
3402	*/
3403	static DECLCALLBACK(void) buslogicR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3404	{
3405	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3406	unsigned i;
3407	bool fVerbose = false;
3408
3409	/* Parse arguments. */
3410	if (pszArgs)
3411	fVerbose = strstr(pszArgs, "verbose") != NULL;
3412
3413	/* Show basic information. */
3414	pHlp->pfnPrintf(pHlp,
3415	"%s#%d: PCI I/O=%RTiop ISA I/O=%RTiop MMIO=%RGp IRQ=%u GC=%RTbool R0=%RTbool\n",
3416	pDevIns->pReg->szName,
3417	pDevIns->iInstance,
3418	pThis->IOPortBase, pThis->IOISABase, pThis->MMIOBase,
3419	PCIDevGetInterruptLine(&pThis->dev),
3420	!!pThis->fGCEnabled, !!pThis->fR0Enabled);
3421
3422	/* Print mailbox state. */
3423	if (pThis->regStatus & BUSLOGIC_REGISTER_STATUS_INITIALIZATION_REQUIRED)
3424	pHlp->pfnPrintf(pHlp, "Mailbox not initialized\n");
3425	else
3426	pHlp->pfnPrintf(pHlp, "%u-bit mailbox with %u entries at %RGp\n",
3427	pThis->fMbxIs24Bit ? 24 : 32, pThis->cMailbox,
3428	pThis->GCPhysAddrMailboxOutgoingBase);
3429
3430	/* Print register contents. */
3431	pHlp->pfnPrintf(pHlp, "Registers: STAT=%02x INTR=%02x GEOM=%02x\n",
3432	pThis->regStatus, pThis->regInterrupt, pThis->regGeometry);
3433
3434	/* Print the current command, if any. */
3435	if (pThis->uOperationCode != 0xff )
3436	pHlp->pfnPrintf(pHlp, "Current command: %02X\n", pThis->uOperationCode);
3437
3438	if (fVerbose && (pThis->regStatus & BUSLOGIC_REGISTER_STATUS_INITIALIZATION_REQUIRED) == 0)
3439	{
3440	RTGCPHYS GCMailbox;
3441
3442	/* Dump the mailbox contents. */
3443	if (pThis->fMbxIs24Bit)
3444	{
3445	Mailbox24 Mbx24;
3446
3447	/* Outgoing mailbox, 24-bit format. */
3448	GCMailbox = pThis->GCPhysAddrMailboxOutgoingBase;
3449	pHlp->pfnPrintf(pHlp, " Outgoing mailbox entries (24-bit) at %06X:\n", GCMailbox);
3450	for (i = 0; i < pThis->cMailbox; ++i)
3451	{
3452	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCMailbox, &Mbx24, sizeof(Mailbox24));
3453	pHlp->pfnPrintf(pHlp, " slot %03d: CCB at %06X action code %02X", i, ADDR_TO_U32(Mbx24.aPhysAddrCCB), Mbx24.uCmdState);
3454	pHlp->pfnPrintf(pHlp, "%s\n", pThis->uMailboxOutgoingPositionCurrent == i ? " *" : "");
3455	GCMailbox += sizeof(Mailbox24);
3456	}
3457
3458	/* Incoming mailbox, 24-bit format. */
3459	GCMailbox = pThis->GCPhysAddrMailboxOutgoingBase + (pThis->cMailbox * sizeof(Mailbox24));
3460	pHlp->pfnPrintf(pHlp, " Incoming mailbox entries (24-bit) at %06X:\n", GCMailbox);
3461	for (i = 0; i < pThis->cMailbox; ++i)
3462	{
3463	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCMailbox, &Mbx24, sizeof(Mailbox24));
3464	pHlp->pfnPrintf(pHlp, " slot %03d: CCB at %06X completion code %02X", i, ADDR_TO_U32(Mbx24.aPhysAddrCCB), Mbx24.uCmdState);
3465	pHlp->pfnPrintf(pHlp, "%s\n", pThis->uMailboxIncomingPositionCurrent == i ? " *" : "");
3466	GCMailbox += sizeof(Mailbox24);
3467	}
3468
3469	}
3470	else
3471	{
3472	Mailbox32 Mbx32;
3473
3474	/* Outgoing mailbox, 32-bit format. */
3475	GCMailbox = pThis->GCPhysAddrMailboxOutgoingBase;
3476	pHlp->pfnPrintf(pHlp, " Outgoing mailbox entries (32-bit) at %08X:\n", (uint32_t)GCMailbox);
3477	for (i = 0; i < pThis->cMailbox; ++i)
3478	{
3479	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCMailbox, &Mbx32, sizeof(Mailbox32));
3480	pHlp->pfnPrintf(pHlp, " slot %03d: CCB at %08X action code %02X", i, Mbx32.u32PhysAddrCCB, Mbx32.u.out.uActionCode);
3481	pHlp->pfnPrintf(pHlp, "%s\n", pThis->uMailboxOutgoingPositionCurrent == i ? " *" : "");
3482	GCMailbox += sizeof(Mailbox32);
3483	}
3484
3485	/* Incoming mailbox, 32-bit format. */
3486	GCMailbox = pThis->GCPhysAddrMailboxOutgoingBase;
3487	pHlp->pfnPrintf(pHlp, " Outgoing mailbox entries (32-bit) at %08X:\n", (uint32_t)GCMailbox);
3488	for (i = 0; i < pThis->cMailbox; ++i)
3489	{
3490	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCMailbox, &Mbx32, sizeof(Mailbox32));
3491	pHlp->pfnPrintf(pHlp, " slot %03d: CCB at %08X completion code %02X BTSTAT %02X SDSTAT %02X", i,
3492	Mbx32.u32PhysAddrCCB, Mbx32.u.in.uCompletionCode, Mbx32.u.in.uHostAdapterStatus, Mbx32.u.in.uTargetDeviceStatus);
3493	pHlp->pfnPrintf(pHlp, "%s\n", pThis->uMailboxOutgoingPositionCurrent == i ? " *" : "");
3494	GCMailbox += sizeof(Mailbox32);
3495	}
3496
3497	}
3498	}
3499	}
3500
3501	/* -=-=-=-=- Helper -=-=-=-=- */
3502
3503	/**
3504	* Checks if all asynchronous I/O is finished.
3505	*
3506	* Used by buslogicR3Reset, buslogicR3Suspend and buslogicR3PowerOff.
3507	*
3508	* @returns true if quiesced, false if busy.
3509	* @param pDevIns The device instance.
3510	*/
3511	static bool buslogicR3AllAsyncIOIsFinished(PPDMDEVINS pDevIns)
3512	{
3513	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3514
3515	for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aDeviceStates); i++)
3516	{
3517	PBUSLOGICDEVICE pThisDevice = &pThis->aDeviceStates[i];
3518	if (pThisDevice->pDrvBase)
3519	{
3520	if (pThisDevice->cOutstandingRequests != 0)
3521	return false;
3522	}
3523	}
3524
3525	return true;
3526	}
3527
3528	/**
3529	* Callback employed by buslogicR3Suspend and buslogicR3PowerOff..
3530	*
3531	* @returns true if we've quiesced, false if we're still working.
3532	* @param pDevIns The device instance.
3533	*/
3534	static DECLCALLBACK(bool) buslogicR3IsAsyncSuspendOrPowerOffDone(PPDMDEVINS pDevIns)
3535	{
3536	if (!buslogicR3AllAsyncIOIsFinished(pDevIns))
3537	return false;
3538
3539	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3540	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
3541	return true;
3542	}
3543
3544	/**
3545	* Common worker for ahciR3Suspend and ahciR3PowerOff.
3546	*/
3547	static void buslogicR3SuspendOrPowerOff(PPDMDEVINS pDevIns, bool fPowerOff)
3548	{
3549	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3550
3551	ASMAtomicWriteBool(&pThis->fSignalIdle, true);
3552	if (!buslogicR3AllAsyncIOIsFinished(pDevIns))
3553	PDMDevHlpSetAsyncNotification(pDevIns, buslogicR3IsAsyncSuspendOrPowerOffDone);
3554	else
3555	{
3556	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
3557
3558	AssertMsg(!pThis->fNotificationSend, ("The PDM Queue should be empty at this point\n"));
3559
3560	if (pThis->fRedo)
3561	{
3562	if (fPowerOff)
3563	{
3564	/* Free tasks which would have been queued again on resume. */
3565	PBUSLOGICTASKSTATE pTaskState = pThis->pTasksRedoHead;
3566
3567	pThis->pTasksRedoHead = NULL;
3568
3569	while (pTaskState)
3570	{
3571	PBUSLOGICTASKSTATE pFree;
3572
3573	pFree = pTaskState;
3574	pTaskState = pTaskState->pRedoNext;
3575
3576	RTMemCacheFree(pThis->hTaskCache, pFree);
3577	}
3578	pThis->fRedo = false;
3579	}
3580	else if (pThis->VBoxSCSI.fBusy)
3581	{
3582	/* Destroy the task because the BIOS interface has all necessary information. */
3583	Assert(pThis->pTasksRedoHead->fBIOS);
3584	Assert(!pThis->pTasksRedoHead->pRedoNext);
3585
3586	RTMemCacheFree(pThis->hTaskCache, pThis->pTasksRedoHead);
3587	pThis->pTasksRedoHead = NULL;
3588	}
3589	}
3590	}
3591	}
3592
3593	/**
3594	* Suspend notification.
3595	*
3596	* @param pDevIns The device instance data.
3597	*/
3598	static DECLCALLBACK(void) buslogicR3Suspend(PPDMDEVINS pDevIns)
3599	{
3600	Log(("buslogicR3Suspend\n"));
3601	buslogicR3SuspendOrPowerOff(pDevIns, false /* fPoweroff */);
3602	}
3603
3604	/**
3605	* Resume notification.
3606	*
3607	* @param pDevIns The device instance data.
3608	*/
3609	static DECLCALLBACK(void) buslogicR3Resume(PPDMDEVINS pDevIns)
3610	{
3611	Log(("buslogicR3Resume\n"));
3612	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3613	buslogicR3Kick(pThis);
3614	}
3615
3616
3617	/**
3618	* Detach notification.
3619	*
3620	* One harddisk at one port has been unplugged.
3621	* The VM is suspended at this point.
3622	*
3623	* @param pDevIns The device instance.
3624	* @param iLUN The logical unit which is being detached.
3625	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3626	*/
3627	static DECLCALLBACK(void) buslogicR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3628	{
3629	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3630	PBUSLOGICDEVICE pDevice = &pThis->aDeviceStates[iLUN];
3631
3632	Log(("%s:\n", __FUNCTION__));
3633
3634	AssertMsg(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
3635	("BusLogic: Device does not support hotplugging\n"));
3636
3637	/*
3638	* Zero some important members.
3639	*/
3640	pDevice->pDrvBase = NULL;
3641	pDevice->fPresent = false;
3642	pDevice->pDrvSCSIConnector = NULL;
3643	}
3644
3645	/**
3646	* Attach command.
3647	*
3648	* This is called when we change block driver.
3649	*
3650	* @returns VBox status code.
3651	* @param pDevIns The device instance.
3652	* @param iLUN The logical unit which is being detached.
3653	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3654	*/
3655	static DECLCALLBACK(int) buslogicR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3656	{
3657	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3658	PBUSLOGICDEVICE pDevice = &pThis->aDeviceStates[iLUN];
3659	int rc;
3660
3661	AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
3662	("BusLogic: Device does not support hotplugging\n"),
3663	VERR_INVALID_PARAMETER);
3664
3665	/* the usual paranoia */
3666	AssertRelease(!pDevice->pDrvBase);
3667	AssertRelease(!pDevice->pDrvSCSIConnector);
3668	Assert(pDevice->iLUN == iLUN);
3669
3670	/*
3671	* Try attach the block device and get the interfaces,
3672	* required as well as optional.
3673	*/
3674	rc = PDMDevHlpDriverAttach(pDevIns, pDevice->iLUN, &pDevice->IBase, &pDevice->pDrvBase, NULL);
3675	if (RT_SUCCESS(rc))
3676	{
3677	/* Get SCSI connector interface. */
3678	pDevice->pDrvSCSIConnector = PDMIBASE_QUERY_INTERFACE(pDevice->pDrvBase, PDMISCSICONNECTOR);
3679	AssertMsgReturn(pDevice->pDrvSCSIConnector, ("Missing SCSI interface below\n"), VERR_PDM_MISSING_INTERFACE);
3680	pDevice->fPresent = true;
3681	}
3682	else
3683	AssertMsgFailed(("Failed to attach LUN#%d. rc=%Rrc\n", pDevice->iLUN, rc));
3684
3685	if (RT_FAILURE(rc))
3686	{
3687	pDevice->pDrvBase = NULL;
3688	pDevice->pDrvSCSIConnector = NULL;
3689	}
3690	return rc;
3691	}
3692
3693	/**
3694	* Callback employed by buslogicR3Reset.
3695	*
3696	* @returns true if we've quiesced, false if we're still working.
3697	* @param pDevIns The device instance.
3698	*/
3699	static DECLCALLBACK(bool) buslogicR3IsAsyncResetDone(PPDMDEVINS pDevIns)
3700	{
3701	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3702
3703	if (!buslogicR3AllAsyncIOIsFinished(pDevIns))
3704	return false;
3705	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
3706
3707	buslogicR3HwReset(pThis, true);
3708	return true;
3709	}
3710
3711	/**
3712	* @copydoc FNPDMDEVRESET
3713	*/
3714	static DECLCALLBACK(void) buslogicR3Reset(PPDMDEVINS pDevIns)
3715	{
3716	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3717
3718	ASMAtomicWriteBool(&pThis->fSignalIdle, true);
3719	if (!buslogicR3AllAsyncIOIsFinished(pDevIns))
3720	PDMDevHlpSetAsyncNotification(pDevIns, buslogicR3IsAsyncResetDone);
3721	else
3722	{
3723	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
3724	buslogicR3HwReset(pThis, true);
3725	}
3726	}
3727
3728	static DECLCALLBACK(void) buslogicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
3729	{
3730	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3731
3732	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3733	pThis->pNotifierQueueRC = PDMQueueRCPtr(pThis->pNotifierQueueR3);
3734
3735	for (uint32_t i = 0; i < BUSLOGIC_MAX_DEVICES; i++)
3736	{
3737	PBUSLOGICDEVICE pDevice = &pThis->aDeviceStates[i];
3738
3739	pDevice->pBusLogicRC = PDMINS_2_DATA_RCPTR(pDevIns);
3740	}
3741
3742	}
3743
3744	/**
3745	* Poweroff notification.
3746	*
3747	* @param pDevIns Pointer to the device instance
3748	*/
3749	static DECLCALLBACK(void) buslogicR3PowerOff(PPDMDEVINS pDevIns)
3750	{
3751	Log(("buslogicR3PowerOff\n"));
3752	buslogicR3SuspendOrPowerOff(pDevIns, true /* fPoweroff */);
3753	}
3754
3755	/**
3756	* Destroy a driver instance.
3757	*
3758	* Most VM resources are freed by the VM. This callback is provided so that any non-VM
3759	* resources can be freed correctly.
3760	*
3761	* @param pDevIns The device instance data.
3762	*/
3763	static DECLCALLBACK(int) buslogicR3Destruct(PPDMDEVINS pDevIns)
3764	{
3765	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3766	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
3767
3768	PDMR3CritSectDelete(&pThis->CritSectIntr);
3769
3770	/*
3771	* Free all tasks which are still hanging around
3772	* (Power off after the VM was suspended).
3773	*/
3774	if (pThis->fRedo)
3775	{
3776	/* Free tasks which would have been queued again on resume. */
3777	PBUSLOGICTASKSTATE pTaskState = pThis->pTasksRedoHead;
3778
3779	pThis->pTasksRedoHead = NULL;
3780
3781	while (pTaskState)
3782	{
3783	PBUSLOGICTASKSTATE pFree;
3784
3785	pFree = pTaskState;
3786	pTaskState = pTaskState->pRedoNext;
3787
3788	RTMemCacheFree(pThis->hTaskCache, pFree);
3789	}
3790	pThis->fRedo = false;
3791	}
3792
3793	int rc = RTMemCacheDestroy(pThis->hTaskCache);
3794	AssertMsgRC(rc, ("Destroying task cache failed rc=%Rrc\n", rc));
3795
3796	return rc;
3797	}
3798
3799	/**
3800	* @interface_method_impl{PDMDEVREG,pfnConstruct}
3801	*/
3802	static DECLCALLBACK(int) buslogicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
3803	{
3804	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3805	int rc = VINF_SUCCESS;
3806	bool fBootable = true;
3807	char achISACompat[16];
3808	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3809
3810	/*
3811	* Init instance data (do early because of constructor).
3812	*/
3813	pThis->hTaskCache = NIL_RTMEMCACHE;
3814	pThis->pDevInsR3 = pDevIns;
3815	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
3816	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3817	pThis->IBase.pfnQueryInterface = buslogicR3StatusQueryInterface;
3818	pThis->ILeds.pfnQueryStatusLed = buslogicR3StatusQueryStatusLed;
3819
3820	PCIDevSetVendorId (&pThis->dev, 0x104b); /* BusLogic */
3821	PCIDevSetDeviceId (&pThis->dev, 0x1040); /* BT-958 */
3822	PCIDevSetCommand (&pThis->dev, 0x0003);
3823	PCIDevSetRevisionId (&pThis->dev, 0x01);
3824	PCIDevSetClassProg (&pThis->dev, 0x00); /* SCSI */
3825	PCIDevSetClassSub (&pThis->dev, 0x00); /* SCSI */
3826	PCIDevSetClassBase (&pThis->dev, 0x01); /* Mass storage */
3827	PCIDevSetBaseAddress (&pThis->dev, 0, true /IO/, false /Pref/, false /64-bit/, 0x00000000);
3828	PCIDevSetBaseAddress (&pThis->dev, 1, false /IO/, false /Pref/, false /64-bit/, 0x00000000);
3829	PCIDevSetSubSystemVendorId(&pThis->dev, 0x104b);
3830	PCIDevSetSubSystemId (&pThis->dev, 0x1040);
3831	PCIDevSetInterruptLine (&pThis->dev, 0x00);
3832	PCIDevSetInterruptPin (&pThis->dev, 0x01);
3833
3834	/*
3835	* Validate and read configuration.
3836	*/
3837	if (!CFGMR3AreValuesValid(pCfg,
3838	"GCEnabled\0"
3839	"R0Enabled\0"
3840	"Bootable\0"
3841	"ISACompat\0"))
3842	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
3843	N_("BusLogic configuration error: unknown option specified"));
3844
3845	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &pThis->fGCEnabled, true);
3846	if (RT_FAILURE(rc))
3847	return PDMDEV_SET_ERROR(pDevIns, rc,
3848	N_("BusLogic configuration error: failed to read GCEnabled as boolean"));
3849	Log(("%s: fGCEnabled=%d\n", __FUNCTION__, pThis->fGCEnabled));
3850
3851	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, true);
3852	if (RT_FAILURE(rc))
3853	return PDMDEV_SET_ERROR(pDevIns, rc,
3854	N_("BusLogic configuration error: failed to read R0Enabled as boolean"));
3855	Log(("%s: fR0Enabled=%d\n", __FUNCTION__, pThis->fR0Enabled));
3856	rc = CFGMR3QueryBoolDef(pCfg, "Bootable", &fBootable, true);
3857	if (RT_FAILURE(rc))
3858	return PDMDEV_SET_ERROR(pDevIns, rc,
3859	N_("BusLogic configuration error: failed to read Bootable as boolean"));
3860	Log(("%s: fBootable=%RTbool\n", __FUNCTION__, fBootable));
3861	rc = CFGMR3QueryStringDef(pCfg, "ISACompat", achISACompat, sizeof(achISACompat), "Alternate");
3862	if (RT_FAILURE(rc))
3863	return PDMDEV_SET_ERROR(pDevIns, rc,
3864	N_("BusLogic configuration error: failed to read ISACompat as string"));
3865	Log(("%s: ISACompat=%s\n", __FUNCTION__, achISACompat));
3866
3867	/* Grok the ISACompat setting. */
3868	if (!strcmp(achISACompat, "Disabled"))
3869	pThis->uDefaultISABaseCode = ISA_BASE_DISABLED;
3870	else if (!strcmp(achISACompat, "Primary"))
3871	pThis->uDefaultISABaseCode = 0; /* I/O base at 330h. */
3872	else if (!strcmp(achISACompat, "Alternate"))
3873	pThis->uDefaultISABaseCode = 1; /* I/O base at 334h. */
3874	else
3875	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
3876	N_("BusLogic configuration error: invalid ISACompat setting"));
3877
3878	/*
3879	* Register the PCI device and its I/O regions.
3880	*/
3881	rc = PDMDevHlpPCIRegister(pDevIns, &pThis->dev);
3882	if (RT_FAILURE(rc))
3883	return rc;
3884
3885	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 32, PCI_ADDRESS_SPACE_IO, buslogicR3MmioMap);
3886	if (RT_FAILURE(rc))
3887	return rc;
3888
3889	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 1, 32, PCI_ADDRESS_SPACE_MEM, buslogicR3MmioMap);
3890	if (RT_FAILURE(rc))
3891	return rc;
3892
3893	if (fBootable)
3894	{
3895	/* Register I/O port space for BIOS access. */
3896	rc = PDMDevHlpIOPortRegister(pDevIns, BUSLOGIC_BIOS_IO_PORT, 4, NULL,
3897	buslogicR3BiosIoPortWrite, buslogicR3BiosIoPortRead,
3898	buslogicR3BiosIoPortWriteStr, buslogicR3BiosIoPortReadStr,
3899	"BusLogic BIOS");
3900	if (RT_FAILURE(rc))
3901	return PDMDEV_SET_ERROR(pDevIns, rc, N_("BusLogic cannot register BIOS I/O handlers"));
3902	}
3903
3904	/* Set up the compatibility I/O range. */
3905	rc = buslogicR3RegisterISARange(pThis, pThis->uDefaultISABaseCode);
3906	if (RT_FAILURE(rc))
3907	return PDMDEV_SET_ERROR(pDevIns, rc, N_("BusLogic cannot register ISA I/O handlers"));
3908
3909	/* Initialize task cache. */
3910	rc = RTMemCacheCreate(&pThis->hTaskCache, sizeof(BUSLOGICTASKSTATE), 0, UINT32_MAX,
3911	NULL, NULL, NULL, 0);
3912	if (RT_FAILURE(rc))
3913	return PDMDEV_SET_ERROR(pDevIns, rc,
3914	N_("BusLogic: Failed to initialize task cache\n"));
3915
3916	/* Initialize task queue. */
3917	rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 5, 0,
3918	buslogicR3NotifyQueueConsumer, true, "BusLogicTask", &pThis->pNotifierQueueR3);
3919	if (RT_FAILURE(rc))
3920	return rc;
3921	pThis->pNotifierQueueR0 = PDMQueueR0Ptr(pThis->pNotifierQueueR3);
3922	pThis->pNotifierQueueRC = PDMQueueRCPtr(pThis->pNotifierQueueR3);
3923
3924	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSectIntr, RT_SRC_POS, "BusLogic-Intr#%u", pDevIns->iInstance);
3925	if (RT_FAILURE(rc))
3926	return PDMDEV_SET_ERROR(pDevIns, rc, N_("BusLogic: cannot create critical section"));
3927
3928	/* Initialize per device state. */
3929	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDeviceStates); i++)
3930	{
3931	char szName[24];
3932	PBUSLOGICDEVICE pDevice = &pThis->aDeviceStates[i];
3933
3934	RTStrPrintf(szName, sizeof(szName), "Device%u", i);
3935
3936	/* Initialize static parts of the device. */
3937	pDevice->iLUN = i;
3938	pDevice->pBusLogicR3 = pThis;
3939	pDevice->pBusLogicR0 = PDMINS_2_DATA_R0PTR(pDevIns);
3940	pDevice->pBusLogicRC = PDMINS_2_DATA_RCPTR(pDevIns);
3941	pDevice->Led.u32Magic = PDMLED_MAGIC;
3942	pDevice->IBase.pfnQueryInterface = buslogicR3DeviceQueryInterface;
3943	pDevice->ISCSIPort.pfnSCSIRequestCompleted = buslogicR3DeviceSCSIRequestCompleted;
3944	pDevice->ISCSIPort.pfnQueryDeviceLocation = buslogicR3QueryDeviceLocation;
3945	pDevice->ILed.pfnQueryStatusLed = buslogicR3DeviceQueryStatusLed;
3946
3947	/* Attach SCSI driver. */
3948	rc = PDMDevHlpDriverAttach(pDevIns, pDevice->iLUN, &pDevice->IBase, &pDevice->pDrvBase, szName);
3949	if (RT_SUCCESS(rc))
3950	{
3951	/* Get SCSI connector interface. */
3952	pDevice->pDrvSCSIConnector = PDMIBASE_QUERY_INTERFACE(pDevice->pDrvBase, PDMISCSICONNECTOR);
3953	AssertMsgReturn(pDevice->pDrvSCSIConnector, ("Missing SCSI interface below\n"), VERR_PDM_MISSING_INTERFACE);
3954
3955	pDevice->fPresent = true;
3956	}
3957	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3958	{
3959	pDevice->pDrvBase = NULL;
3960	pDevice->fPresent = false;
3961	rc = VINF_SUCCESS;
3962	Log(("BusLogic: no driver attached to device %s\n", szName));
3963	}
3964	else
3965	{
3966	AssertLogRelMsgFailed(("BusLogic: Failed to attach %s\n", szName));
3967	return rc;
3968	}
3969	}
3970
3971	/*
3972	* Attach status driver (optional).
3973	*/
3974	PPDMIBASE pBase;
3975	rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThis->IBase, &pBase, "Status Port");
3976	if (RT_SUCCESS(rc))
3977	pThis->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
3978	else if (rc != VERR_PDM_NO_ATTACHED_DRIVER)
3979	{
3980	AssertMsgFailed(("Failed to attach to status driver. rc=%Rrc\n", rc));
3981	return PDMDEV_SET_ERROR(pDevIns, rc, N_("BusLogic cannot attach to status driver"));
3982	}
3983
3984	rc = PDMDevHlpSSMRegisterEx(pDevIns, BUSLOGIC_SAVED_STATE_MINOR_VERSION, sizeof(*pThis), NULL,
3985	NULL, buslogicR3LiveExec, NULL,
3986	NULL, buslogicR3SaveExec, NULL,
3987	NULL, buslogicR3LoadExec, buslogicR3LoadDone);
3988	if (RT_FAILURE(rc))
3989	return PDMDEV_SET_ERROR(pDevIns, rc, N_("BusLogic cannot register save state handlers"));
3990
3991	/*
3992	* Register the debugger info callback.
3993	*/
3994	char szTmp[128];
3995	RTStrPrintf(szTmp, sizeof(szTmp), "%s%d", pDevIns->pReg->szName, pDevIns->iInstance);
3996	PDMDevHlpDBGFInfoRegister(pDevIns, szTmp, "BusLogic HBA info", buslogicR3Info);
3997
3998	rc = buslogicR3HwReset(pThis, true);
3999	AssertMsgRC(rc, ("hardware reset of BusLogic host adapter failed rc=%Rrc\n", rc));
4000
4001	return rc;
4002	}
4003
4004	/**
4005	* The device registration structure.
4006	*/
4007	const PDMDEVREG g_DeviceBusLogic =
4008	{
4009	/* u32Version */
4010	PDM_DEVREG_VERSION,
4011	/* szName */
4012	"buslogic",
4013	/* szRCMod */
4014	"VBoxDDGC.gc",
4015	/* szR0Mod */
4016	"VBoxDDR0.r0",
4017	/* pszDescription */
4018	"BusLogic BT-958 SCSI host adapter.\n",
4019	/* fFlags */
4020	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0 \|
4021	PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION \| PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION \|
4022	PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION,
4023	/* fClass */
4024	PDM_DEVREG_CLASS_STORAGE,
4025	/* cMaxInstances */
4026	~0U,
4027	/* cbInstance */
4028	sizeof(BUSLOGIC),
4029	/* pfnConstruct */
4030	buslogicR3Construct,
4031	/* pfnDestruct */
4032	buslogicR3Destruct,
4033	/* pfnRelocate */
4034	buslogicR3Relocate,
4035	/* pfnMemSetup */
4036	NULL,
4037	/* pfnPowerOn */
4038	NULL,
4039	/* pfnReset */
4040	buslogicR3Reset,
4041	/* pfnSuspend */
4042	buslogicR3Suspend,
4043	/* pfnResume */
4044	buslogicR3Resume,
4045	/* pfnAttach */
4046	buslogicR3Attach,
4047	/* pfnDetach */
4048	buslogicR3Detach,
4049	/* pfnQueryInterface. */
4050	NULL,
4051	/* pfnInitComplete */
4052	NULL,
4053	/* pfnPowerOff */
4054	buslogicR3PowerOff,
4055	/* pfnSoftReset */
4056	NULL,
4057	/* u32VersionEnd */
4058	PDM_DEVREG_VERSION
4059	};
4060
4061	#endif /* IN_RING3 */
4062	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Storage/DevBusLogic.cpp@ 46243

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