DevBusLogic.cpp@ 52713

Last change on this file since 52713 was 52713, checked in by vboxsync, 10 years ago
BusLogic: Slightly enhanced debug info.
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1	/* $Id: DevBusLogic.cpp 52713 2014-09-12 09:34:39Z vboxsync $ */
2	/** @file
3	* VBox storage devices - BusLogic SCSI host adapter BT-958.
4	*
5	* Based on the Multi-Master Ultra SCSI Systems Technical Reference Manual.
6	*/
7
8	/*
9	* Copyright (C) 2006-2013 Oracle Corporation
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*/
19
20
21	/*******************************************************************************
22	* Header Files *
23	*******************************************************************************/
24	#define LOG_GROUP LOG_GROUP_DEV_BUSLOGIC
25	#include <VBox/vmm/pdmdev.h>
26	#include <VBox/vmm/pdmifs.h>
27	#include <VBox/vmm/pdmcritsect.h>
28	#include <VBox/scsi.h>
29	#include <iprt/asm.h>
30	#include <iprt/assert.h>
31	#include <iprt/string.h>
32	#include <iprt/log.h>
33	#ifdef IN_RING3
34	# include <iprt/alloc.h>
35	# include <iprt/memcache.h>
36	# include <iprt/param.h>
37	# include <iprt/uuid.h>
38	#endif
39
40	#include "VBoxSCSI.h"
41	#include "VBoxDD.h"
42
43
44	/*******************************************************************************
45	* Defined Constants And Macros *
46	*******************************************************************************/
47	/** Maximum number of attached devices the adapter can handle. */
48	#define BUSLOGIC_MAX_DEVICES 16
49
50	/** Maximum number of scatter gather elements this device can handle. */
51	#define BUSLOGIC_MAX_SCATTER_GATHER_LIST_SIZE 128
52
53	/** Size of the command buffer. */
54	#define BUSLOGIC_COMMAND_SIZE_MAX 53
55
56	/** Size of the reply buffer. */
57	#define BUSLOGIC_REPLY_SIZE_MAX 64
58
59	/** Custom fixed I/O ports for BIOS controller access.
60	* Note that these should not be in the ISA range (below 400h) to avoid
61	* conflicts with ISA device probing. Addresses in the 300h-340h range should be
62	* especially avoided.
63	*/
64	#define BUSLOGIC_BIOS_IO_PORT 0x430
65
66	/** State saved version. */
67	#define BUSLOGIC_SAVED_STATE_MINOR_VERSION 4
68
69	/** Saved state version before the suspend on error feature was implemented. */
70	#define BUSLOGIC_SAVED_STATE_MINOR_PRE_ERROR_HANDLING 1
71	/** Saved state version before 24-bit mailbox support was implemented. */
72	#define BUSLOGIC_SAVED_STATE_MINOR_PRE_24BIT_MBOX 2
73	/** Saved state version before command buffer size was raised. */
74	#define BUSLOGIC_SAVED_STATE_MINOR_PRE_CMDBUF_RESIZE 3
75
76	/** Command buffer size in old saved states. */
77	#define BUSLOGIC_COMMAND_SIZE_OLD 5
78
79	/** The duration of software-initiated reset (in nano seconds).
80	* Not documented, set to 50 ms. */
81	#define BUSLOGIC_RESET_DURATION_NS UINT64_C(50000000)
82
83
84	/*******************************************************************************
85	* Structures and Typedefs *
86	*******************************************************************************/
87	/**
88	* State of a device attached to the buslogic host adapter.
89	*
90	* @implements PDMIBASE
91	* @implements PDMISCSIPORT
92	* @implements PDMILEDPORTS
93	*/
94	typedef struct BUSLOGICDEVICE
95	{
96	/** Pointer to the owning buslogic device instance. - R3 pointer */
97	R3PTRTYPE(struct BUSLOGIC *) pBusLogicR3;
98	/** Pointer to the owning buslogic device instance. - R0 pointer */
99	R0PTRTYPE(struct BUSLOGIC *) pBusLogicR0;
100	/** Pointer to the owning buslogic device instance. - RC pointer */
101	RCPTRTYPE(struct BUSLOGIC *) pBusLogicRC;
102
103	/** Flag whether device is present. */
104	bool fPresent;
105	/** LUN of the device. */
106	RTUINT iLUN;
107
108	#if HC_ARCH_BITS == 64
109	uint32_t Alignment0;
110	#endif
111
112	/** Our base interface. */
113	PDMIBASE IBase;
114	/** SCSI port interface. */
115	PDMISCSIPORT ISCSIPort;
116	/** Led interface. */
117	PDMILEDPORTS ILed;
118	/** Pointer to the attached driver's base interface. */
119	R3PTRTYPE(PPDMIBASE) pDrvBase;
120	/** Pointer to the underlying SCSI connector interface. */
121	R3PTRTYPE(PPDMISCSICONNECTOR) pDrvSCSIConnector;
122	/** The status LED state for this device. */
123	PDMLED Led;
124
125	#if HC_ARCH_BITS == 64
126	uint32_t Alignment1;
127	#endif
128
129	/** Number of outstanding tasks on the port. */
130	volatile uint32_t cOutstandingRequests;
131
132	} BUSLOGICDEVICE, *PBUSLOGICDEVICE;
133
134	/**
135	* Commands the BusLogic adapter supports.
136	*/
137	enum BUSLOGICCOMMAND
138	{
139	BUSLOGICCOMMAND_TEST_CMDC_INTERRUPT = 0x00,
140	BUSLOGICCOMMAND_INITIALIZE_MAILBOX = 0x01,
141	BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND = 0x02,
142	BUSLOGICCOMMAND_EXECUTE_BIOS_COMMAND = 0x03,
143	BUSLOGICCOMMAND_INQUIRE_BOARD_ID = 0x04,
144	BUSLOGICCOMMAND_ENABLE_OUTGOING_MAILBOX_AVAILABLE_INTERRUPT = 0x05,
145	BUSLOGICCOMMAND_SET_SCSI_SELECTION_TIMEOUT = 0x06,
146	BUSLOGICCOMMAND_SET_PREEMPT_TIME_ON_BUS = 0x07,
147	BUSLOGICCOMMAND_SET_TIME_OFF_BUS = 0x08,
148	BUSLOGICCOMMAND_SET_BUS_TRANSFER_RATE = 0x09,
149	BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_0_TO_7 = 0x0a,
150	BUSLOGICCOMMAND_INQUIRE_CONFIGURATION = 0x0b,
151	BUSLOGICCOMMAND_ENABLE_TARGET_MODE = 0x0c,
152	BUSLOGICCOMMAND_INQUIRE_SETUP_INFORMATION = 0x0d,
153	BUSLOGICCOMMAND_WRITE_ADAPTER_LOCAL_RAM = 0x1a,
154	BUSLOGICCOMMAND_READ_ADAPTER_LOCAL_RAM = 0x1b,
155	BUSLOGICCOMMAND_WRITE_BUSMASTER_CHIP_FIFO = 0x1c,
156	BUSLOGICCOMMAND_READ_BUSMASTER_CHIP_FIFO = 0x1d,
157	BUSLOGICCOMMAND_ECHO_COMMAND_DATA = 0x1f,
158	BUSLOGICCOMMAND_HOST_ADAPTER_DIAGNOSTIC = 0x20,
159	BUSLOGICCOMMAND_SET_ADAPTER_OPTIONS = 0x21,
160	BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_8_TO_15 = 0x23,
161	BUSLOGICCOMMAND_INQUIRE_TARGET_DEVICES = 0x24,
162	BUSLOGICCOMMAND_DISABLE_HOST_ADAPTER_INTERRUPT = 0x25,
163	BUSLOGICCOMMAND_EXT_BIOS_INFO = 0x28,
164	BUSLOGICCOMMAND_UNLOCK_MAILBOX = 0x29,
165	BUSLOGICCOMMAND_INITIALIZE_EXTENDED_MAILBOX = 0x81,
166	BUSLOGICCOMMAND_EXECUTE_SCSI_COMMAND = 0x83,
167	BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_3RD_LETTER = 0x84,
168	BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_LETTER = 0x85,
169	BUSLOGICCOMMAND_INQUIRE_PCI_HOST_ADAPTER_INFORMATION = 0x86,
170	BUSLOGICCOMMAND_INQUIRE_HOST_ADAPTER_MODEL_NUMBER = 0x8b,
171	BUSLOGICCOMMAND_INQUIRE_SYNCHRONOUS_PERIOD = 0x8c,
172	BUSLOGICCOMMAND_INQUIRE_EXTENDED_SETUP_INFORMATION = 0x8d,
173	BUSLOGICCOMMAND_ENABLE_STRICT_ROUND_ROBIN_MODE = 0x8f,
174	BUSLOGICCOMMAND_STORE_HOST_ADAPTER_LOCAL_RAM = 0x90,
175	BUSLOGICCOMMAND_FETCH_HOST_ADAPTER_LOCAL_RAM = 0x91,
176	BUSLOGICCOMMAND_STORE_LOCAL_DATA_IN_EEPROM = 0x92,
177	BUSLOGICCOMMAND_UPLOAD_AUTO_SCSI_CODE = 0x94,
178	BUSLOGICCOMMAND_MODIFY_IO_ADDRESS = 0x95,
179	BUSLOGICCOMMAND_SET_CCB_FORMAT = 0x96,
180	BUSLOGICCOMMAND_WRITE_INQUIRY_BUFFER = 0x9a,
181	BUSLOGICCOMMAND_READ_INQUIRY_BUFFER = 0x9b,
182	BUSLOGICCOMMAND_FLASH_ROM_UPLOAD_DOWNLOAD = 0xa7,
183	BUSLOGICCOMMAND_READ_SCAM_DATA = 0xa8,
184	BUSLOGICCOMMAND_WRITE_SCAM_DATA = 0xa9
185	} BUSLOGICCOMMAND;
186
187	#pragma pack(1)
188	/**
189	* Auto SCSI structure which is located
190	* in host adapter RAM and contains several
191	* configuration parameters.
192	*/
193	typedef struct AutoSCSIRam
194	{
195	uint8_t aInternalSignature[2];
196	uint8_t cbInformation;
197	uint8_t aHostAdaptertype[6];
198	uint8_t uReserved1;
199	bool fFloppyEnabled : 1;
200	bool fFloppySecondary : 1;
201	bool fLevelSensitiveInterrupt : 1;
202	unsigned char uReserved2 : 2;
203	unsigned char uSystemRAMAreForBIOS : 3;
204	unsigned char uDMAChannel : 7;
205	bool fDMAAutoConfiguration : 1;
206	unsigned char uIrqChannel : 7;
207	bool fIrqAutoConfiguration : 1;
208	uint8_t uDMATransferRate;
209	uint8_t uSCSIId;
210	bool fLowByteTerminated : 1;
211	bool fParityCheckingEnabled : 1;
212	bool fHighByteTerminated : 1;
213	bool fNoisyCablingEnvironment : 1;
214	bool fFastSynchronousNeogtiation : 1;
215	bool fBusResetEnabled : 1;
216	bool fReserved3 : 1;
217	bool fActiveNegotiationEnabled : 1;
218	uint8_t uBusOnDelay;
219	uint8_t uBusOffDelay;
220	bool fHostAdapterBIOSEnabled : 1;
221	bool fBIOSRedirectionOfInt19 : 1;
222	bool fExtendedTranslation : 1;
223	bool fMapRemovableAsFixed : 1;
224	bool fReserved4 : 1;
225	bool fBIOSSupportsMoreThan2Drives : 1;
226	bool fBIOSInterruptMode : 1;
227	bool fFlopticalSupport : 1;
228	uint16_t u16DeviceEnabledMask;
229	uint16_t u16WidePermittedMask;
230	uint16_t u16FastPermittedMask;
231	uint16_t u16SynchronousPermittedMask;
232	uint16_t u16DisconnectPermittedMask;
233	uint16_t u16SendStartUnitCommandMask;
234	uint16_t u16IgnoreInBIOSScanMask;
235	unsigned char uPCIInterruptPin : 2;
236	unsigned char uHostAdapterIoPortAddress : 2;
237	bool fStrictRoundRobinMode : 1;
238	bool fVesaBusSpeedGreaterThan33MHz : 1;
239	bool fVesaBurstWrite : 1;
240	bool fVesaBurstRead : 1;
241	uint16_t u16UltraPermittedMask;
242	uint32_t uReserved5;
243	uint8_t uReserved6;
244	uint8_t uAutoSCSIMaximumLUN;
245	bool fReserved7 : 1;
246	bool fSCAMDominant : 1;
247	bool fSCAMenabled : 1;
248	bool fSCAMLevel2 : 1;
249	unsigned char uReserved8 : 4;
250	bool fInt13Extension : 1;
251	bool fReserved9 : 1;
252	bool fCDROMBoot : 1;
253	unsigned char uReserved10 : 5;
254	unsigned char uBootTargetId : 4;
255	unsigned char uBootChannel : 4;
256	bool fForceBusDeviceScanningOrder : 1;
257	unsigned char uReserved11 : 7;
258	uint16_t u16NonTaggedToAlternateLunPermittedMask;
259	uint16_t u16RenegotiateSyncAfterCheckConditionMask;
260	uint8_t aReserved12[10];
261	uint8_t aManufacturingDiagnostic[2];
262	uint16_t u16Checksum;
263	} AutoSCSIRam, *PAutoSCSIRam;
264	AssertCompileSize(AutoSCSIRam, 64);
265	#pragma pack()
266
267	/**
268	* The local Ram.
269	*/
270	typedef union HostAdapterLocalRam
271	{
272	/** Byte view. */
273	uint8_t u8View[256];
274	/** Structured view. */
275	struct
276	{
277	/** Offset 0 - 63 is for BIOS. */
278	uint8_t u8Bios[64];
279	/** Auto SCSI structure. */
280	AutoSCSIRam autoSCSIData;
281	} structured;
282	} HostAdapterLocalRam, *PHostAdapterLocalRam;
283	AssertCompileSize(HostAdapterLocalRam, 256);
284
285
286	/** Ugly 24-bit big-endian addressing. */
287	typedef struct
288	{
289	uint8_t hi;
290	uint8_t mid;
291	uint8_t lo;
292	} Addr24, Len24;
293	AssertCompileSize(Addr24, 3);
294
295	#define ADDR_TO_U32(x) (((x).hi << 16) \| ((x).mid << 8) \| (x).lo)
296	#define LEN_TO_U32 ADDR_TO_U32
297	#define U32_TO_ADDR(a, x) do {(a).hi = (x) >> 16; (a).mid = (x) >> 8; (a).lo = (x);} while(0)
298	#define U32_TO_LEN U32_TO_ADDR
299
300	/** @name Compatible ISA base I/O port addresses. Disabled if zero.
301	* @{ */
302	#define NUM_ISA_BASES 8
303	#define MAX_ISA_BASE (NUM_ISA_BASES - 1)
304	#define ISA_BASE_DISABLED 6
305
306	static uint16_t const g_aISABases[NUM_ISA_BASES] =
307	{
308	0x330, 0x334, 0x230, 0x234, 0x130, 0x134, 0, 0
309	};
310	/** @} */
311
312	/** Pointer to a task state structure. */
313	typedef struct BUSLOGICTASKSTATE *PBUSLOGICTASKSTATE;
314
315	/**
316	* Main BusLogic device state.
317	*
318	* @extends PCIDEVICE
319	* @implements PDMILEDPORTS
320	*/
321	typedef struct BUSLOGIC
322	{
323	/** The PCI device structure. */
324	PCIDEVICE dev;
325	/** Pointer to the device instance - HC ptr */
326	PPDMDEVINSR3 pDevInsR3;
327	/** Pointer to the device instance - R0 ptr */
328	PPDMDEVINSR0 pDevInsR0;
329	/** Pointer to the device instance - RC ptr. */
330	PPDMDEVINSRC pDevInsRC;
331
332	/** Whether R0 is enabled. */
333	bool fR0Enabled;
334	/** Whether RC is enabled. */
335	bool fGCEnabled;
336
337	/** Base address of the I/O ports. */
338	RTIOPORT IOPortBase;
339	/** Base address of the memory mapping. */
340	RTGCPHYS MMIOBase;
341	/** Status register - Readonly. */
342	volatile uint8_t regStatus;
343	/** Interrupt register - Readonly. */
344	volatile uint8_t regInterrupt;
345	/** Geometry register - Readonly. */
346	volatile uint8_t regGeometry;
347	/** Pending (delayed) interrupt. */
348	uint8_t uPendingIntr;
349
350	/** Local RAM for the fetch hostadapter local RAM request.
351	* I don't know how big the buffer really is but the maximum
352	* seems to be 256 bytes because the offset and count field in the command request
353	* are only one byte big.
354	*/
355	HostAdapterLocalRam LocalRam;
356
357	/** Command code the guest issued. */
358	uint8_t uOperationCode;
359	/** Buffer for the command parameters the adapter is currently receiving from the guest.
360	* Size of the largest command which is possible.
361	*/
362	uint8_t aCommandBuffer[BUSLOGIC_COMMAND_SIZE_MAX]; /* Size of the biggest request. */
363	/** Current position in the command buffer. */
364	uint8_t iParameter;
365	/** Parameters left until the command is complete. */
366	uint8_t cbCommandParametersLeft;
367
368	/** Whether we are using the RAM or reply buffer. */
369	bool fUseLocalRam;
370	/** Buffer to store reply data from the controller to the guest. */
371	uint8_t aReplyBuffer[BUSLOGIC_REPLY_SIZE_MAX]; /* Size of the biggest reply. */
372	/** Position in the buffer we are reading next. */
373	uint8_t iReply;
374	/** Bytes left until the reply buffer is empty. */
375	uint8_t cbReplyParametersLeft;
376
377	/** Flag whether IRQs are enabled. */
378	bool fIRQEnabled;
379	/** Flag whether the ISA I/O port range is disabled
380	* to prevent the BIOS to access the device. */
381	bool fISAEnabled; /*< @todo unused, to be removed /
382	/** Flag whether 24-bit mailboxes are in use (default is 32-bit). */
383	bool fMbxIs24Bit;
384	/** ISA I/O port base (encoded in FW-compatible format). */
385	uint8_t uISABaseCode;
386
387	/** ISA I/O port base (disabled if zero). */
388	RTIOPORT IOISABase;
389	/** Default ISA I/O port base in FW-compatible format. */
390	uint8_t uDefaultISABaseCode;
391
392	/** Number of mailboxes the guest set up. */
393	uint32_t cMailbox;
394
395	#if HC_ARCH_BITS == 64
396	uint32_t Alignment0;
397	#endif
398
399	/** Time when HBA reset was last initiated. / /< @todo does this need to be saved? /
400	uint64_t u64ResetTime;
401	/** Physical base address of the outgoing mailboxes. */
402	RTGCPHYS GCPhysAddrMailboxOutgoingBase;
403	/** Current outgoing mailbox position. */
404	uint32_t uMailboxOutgoingPositionCurrent;
405	/** Number of mailboxes ready. */
406	volatile uint32_t cMailboxesReady;
407	/** Whether a notification to R3 was send. */
408	volatile bool fNotificationSend;
409
410	#if HC_ARCH_BITS == 64
411	uint32_t Alignment1;
412	#endif
413
414	/** Physical base address of the incoming mailboxes. */
415	RTGCPHYS GCPhysAddrMailboxIncomingBase;
416	/** Current incoming mailbox position. */
417	uint32_t uMailboxIncomingPositionCurrent;
418
419	/** Whether strict round robin is enabled. */
420	bool fStrictRoundRobinMode;
421	/** Whether the extended LUN CCB format is enabled for 32 possible logical units. */
422	bool fExtendedLunCCBFormat;
423
424	/** Queue to send tasks to R3. - HC ptr */
425	R3PTRTYPE(PPDMQUEUE) pNotifierQueueR3;
426	/** Queue to send tasks to R3. - HC ptr */
427	R0PTRTYPE(PPDMQUEUE) pNotifierQueueR0;
428	/** Queue to send tasks to R3. - RC ptr */
429	RCPTRTYPE(PPDMQUEUE) pNotifierQueueRC;
430
431	uint32_t Alignment2;
432
433	/** Critical section protecting access to the interrupt status register. */
434	PDMCRITSECT CritSectIntr;
435
436	/** Cache for task states. */
437	R3PTRTYPE(RTMEMCACHE) hTaskCache;
438
439	/** Device state for BIOS access. */
440	VBOXSCSI VBoxSCSI;
441
442	/** BusLogic device states. */
443	BUSLOGICDEVICE aDeviceStates[BUSLOGIC_MAX_DEVICES];
444
445	/** The base interface.
446	* @todo use PDMDEVINS::IBase */
447	PDMIBASE IBase;
448	/** Status Port - Leds interface. */
449	PDMILEDPORTS ILeds;
450	/** Partner of ILeds. */
451	R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
452
453	#if HC_ARCH_BITS == 64
454	uint32_t Alignment3;
455	#endif
456
457	/** Indicates that PDMDevHlpAsyncNotificationCompleted should be called when
458	* a port is entering the idle state. */
459	bool volatile fSignalIdle;
460	/** Flag whether we have tasks which need to be processed again. */
461	bool volatile fRedo;
462	/** List of tasks which can be redone. */
463	R3PTRTYPE(volatile PBUSLOGICTASKSTATE) pTasksRedoHead;
464
465	#ifdef LOG_ENABLED
466	# if HC_ARCH_BITS == 64
467	uint32_t Alignment4;
468	# endif
469
470	volatile uint32_t cInMailboxesReady;
471	#endif
472
473	} BUSLOGIC, *PBUSLOGIC;
474
475	/** Register offsets in the I/O port space. */
476	#define BUSLOGIC_REGISTER_CONTROL 0 /*< Writeonly /
477	/** Fields for the control register. */
478	# define BL_CTRL_RSBUS RT_BIT(4) /* Reset SCSI Bus. */
479	# define BL_CTRL_RINT RT_BIT(5) /* Reset Interrupt. */
480	# define BL_CTRL_RSOFT RT_BIT(6) /* Soft Reset. */
481	# define BL_CTRL_RHARD RT_BIT(7) /* Hard Reset. */
482
483	#define BUSLOGIC_REGISTER_STATUS 0 /*< Readonly /
484	/** Fields for the status register. */
485	# define BL_STAT_CMDINV RT_BIT(0) /* Command Invalid. */
486	# define BL_STAT_DIRRDY RT_BIT(2) /* Data In Register Ready. */
487	# define BL_STAT_CPRBSY RT_BIT(3) /* Command/Parameter Out Register Busy. */
488	# define BL_STAT_HARDY RT_BIT(4) /* Host Adapter Ready. */
489	# define BL_STAT_INREQ RT_BIT(5) /* Initialization Required. */
490	# define BL_STAT_DFAIL RT_BIT(6) /* Diagnostic Failure. */
491	# define BL_STAT_DACT RT_BIT(7) /* Diagnistic Active. */
492
493	#define BUSLOGIC_REGISTER_COMMAND 1 /*< Writeonly /
494	#define BUSLOGIC_REGISTER_DATAIN 1 /*< Readonly /
495	#define BUSLOGIC_REGISTER_INTERRUPT 2 /*< Readonly /
496	/** Fields for the interrupt register. */
497	# define BL_INTR_IMBL RT_BIT(0) /* Incoming Mailbox Loaded. */
498	# define BL_INTR_OMBR RT_BIT(1) /* Outgoing Mailbox Available. */
499	# define BL_INTR_CMDC RT_BIT(2) /* Command Complete. */
500	# define BL_INTR_RSTS RT_BIT(3) /* SCSO Bus Reset State. */
501	# define BL_INTR_INTV RT_BIT(7) /* Interrupt Valid. */
502
503	#define BUSLOGIC_REGISTER_GEOMETRY 3 /* Readonly */
504	# define BL_GEOM_XLATEN RT_BIT(7) /* Extended geometry translation enabled. */
505
506	/** Structure for the INQUIRE_PCI_HOST_ADAPTER_INFORMATION reply. */
507	typedef struct ReplyInquirePCIHostAdapterInformation
508	{
509	uint8_t IsaIOPort;
510	uint8_t IRQ;
511	unsigned char LowByteTerminated : 1;
512	unsigned char HighByteTerminated : 1;
513	unsigned char uReserved : 2; /* Reserved. */
514	unsigned char JP1 : 1; /* Whatever that means. */
515	unsigned char JP2 : 1; /* Whatever that means. */
516	unsigned char JP3 : 1; /* Whatever that means. */
517	/** Whether the provided info is valid. */
518	unsigned char InformationIsValid: 1;
519	uint8_t uReserved2; /* Reserved. */
520	} ReplyInquirePCIHostAdapterInformation, *PReplyInquirePCIHostAdapterInformation;
521	AssertCompileSize(ReplyInquirePCIHostAdapterInformation, 4);
522
523	/** Structure for the INQUIRE_CONFIGURATION reply. */
524	typedef struct ReplyInquireConfiguration
525	{
526	unsigned char uReserved1 : 5;
527	bool fDmaChannel5 : 1;
528	bool fDmaChannel6 : 1;
529	bool fDmaChannel7 : 1;
530	bool fIrqChannel9 : 1;
531	bool fIrqChannel10 : 1;
532	bool fIrqChannel11 : 1;
533	bool fIrqChannel12 : 1;
534	unsigned char uReserved2 : 1;
535	bool fIrqChannel14 : 1;
536	bool fIrqChannel15 : 1;
537	unsigned char uReserved3 : 1;
538	unsigned char uHostAdapterId : 4;
539	unsigned char uReserved4 : 4;
540	} ReplyInquireConfiguration, *PReplyInquireConfiguration;
541	AssertCompileSize(ReplyInquireConfiguration, 3);
542
543	/** Structure for the INQUIRE_SETUP_INFORMATION reply. */
544	typedef struct ReplyInquireSetupInformationSynchronousValue
545	{
546	unsigned char uOffset : 4;
547	unsigned char uTransferPeriod : 3;
548	bool fSynchronous : 1;
549	}ReplyInquireSetupInformationSynchronousValue, *PReplyInquireSetupInformationSynchronousValue;
550	AssertCompileSize(ReplyInquireSetupInformationSynchronousValue, 1);
551
552	typedef struct ReplyInquireSetupInformation
553	{
554	bool fSynchronousInitiationEnabled : 1;
555	bool fParityCheckingEnabled : 1;
556	unsigned char uReserved1 : 6;
557	uint8_t uBusTransferRate;
558	uint8_t uPreemptTimeOnBus;
559	uint8_t uTimeOffBus;
560	uint8_t cMailbox;
561	Addr24 MailboxAddress;
562	ReplyInquireSetupInformationSynchronousValue SynchronousValuesId0To7[8];
563	uint8_t uDisconnectPermittedId0To7;
564	uint8_t uSignature;
565	uint8_t uCharacterD;
566	uint8_t uHostBusType;
567	uint8_t uWideTransferPermittedId0To7;
568	uint8_t uWideTransfersActiveId0To7;
569	ReplyInquireSetupInformationSynchronousValue SynchronousValuesId8To15[8];
570	uint8_t uDisconnectPermittedId8To15;
571	uint8_t uReserved2;
572	uint8_t uWideTransferPermittedId8To15;
573	uint8_t uWideTransfersActiveId8To15;
574	} ReplyInquireSetupInformation, *PReplyInquireSetupInformation;
575	AssertCompileSize(ReplyInquireSetupInformation, 34);
576
577	/** Structure for the INQUIRE_EXTENDED_SETUP_INFORMATION. */
578	#pragma pack(1)
579	typedef struct ReplyInquireExtendedSetupInformation
580	{
581	uint8_t uBusType;
582	uint8_t uBiosAddress;
583	uint16_t u16ScatterGatherLimit;
584	uint8_t cMailbox;
585	uint32_t uMailboxAddressBase;
586	unsigned char uReserved1 : 2;
587	bool fFastEISA : 1;
588	unsigned char uReserved2 : 3;
589	bool fLevelSensitiveInterrupt : 1;
590	unsigned char uReserved3 : 1;
591	unsigned char aFirmwareRevision[3];
592	bool fHostWideSCSI : 1;
593	bool fHostDifferentialSCSI : 1;
594	bool fHostSupportsSCAM : 1;
595	bool fHostUltraSCSI : 1;
596	bool fHostSmartTermination : 1;
597	unsigned char uReserved4 : 3;
598	} ReplyInquireExtendedSetupInformation, *PReplyInquireExtendedSetupInformation;
599	AssertCompileSize(ReplyInquireExtendedSetupInformation, 14);
600	#pragma pack()
601
602	/** Structure for the INITIALIZE EXTENDED MAILBOX request. */
603	#pragma pack(1)
604	typedef struct RequestInitializeExtendedMailbox
605	{
606	/** Number of mailboxes in guest memory. */
607	uint8_t cMailbox;
608	/** Physical address of the first mailbox. */
609	uint32_t uMailboxBaseAddress;
610	} RequestInitializeExtendedMailbox, *PRequestInitializeExtendedMailbox;
611	AssertCompileSize(RequestInitializeExtendedMailbox, 5);
612	#pragma pack()
613
614	/** Structure for the INITIALIZE MAILBOX request. */
615	typedef struct
616	{
617	/** Number of mailboxes to set up. */
618	uint8_t cMailbox;
619	/** Physical address of the first mailbox. */
620	Addr24 aMailboxBaseAddr;
621	} RequestInitMbx, *PRequestInitMbx;
622	AssertCompileSize(RequestInitMbx, 4);
623
624	/**
625	* Structure of a mailbox in guest memory.
626	* The incoming and outgoing mailbox have the same size
627	* but the incoming one has some more fields defined which
628	* are marked as reserved in the outgoing one.
629	* The last field is also different from the type.
630	* For outgoing mailboxes it is the action and
631	* for incoming ones the completion status code for the task.
632	* We use one structure for both types.
633	*/
634	typedef struct Mailbox32
635	{
636	/** Physical address of the CCB structure in the guest memory. */
637	uint32_t u32PhysAddrCCB;
638	/** Type specific data. */
639	union
640	{
641	/** For outgoing mailboxes. */
642	struct
643	{
644	/** Reserved */
645	uint8_t uReserved[3];
646	/** Action code. */
647	uint8_t uActionCode;
648	} out;
649	/** For incoming mailboxes. */
650	struct
651	{
652	/** The host adapter status after finishing the request. */
653	uint8_t uHostAdapterStatus;
654	/** The status of the device which executed the request after executing it. */
655	uint8_t uTargetDeviceStatus;
656	/** Reserved. */
657	uint8_t uReserved;
658	/** The completion status code of the request. */
659	uint8_t uCompletionCode;
660	} in;
661	} u;
662	} Mailbox32, *PMailbox32;
663	AssertCompileSize(Mailbox32, 8);
664
665	/** Old style 24-bit mailbox entry. */
666	typedef struct Mailbox24
667	{
668	/** Mailbox command (incoming) or state (outgoing). */
669	uint8_t uCmdState;
670	/** Physical address of the CCB structure in the guest memory. */
671	Addr24 aPhysAddrCCB;
672	} Mailbox24, *PMailbox24;
673	AssertCompileSize(Mailbox24, 4);
674
675	/**
676	* Action codes for outgoing mailboxes.
677	*/
678	enum BUSLOGIC_MAILBOX_OUTGOING_ACTION
679	{
680	BUSLOGIC_MAILBOX_OUTGOING_ACTION_FREE = 0x00,
681	BUSLOGIC_MAILBOX_OUTGOING_ACTION_START_COMMAND = 0x01,
682	BUSLOGIC_MAILBOX_OUTGOING_ACTION_ABORT_COMMAND = 0x02
683	};
684
685	/**
686	* Completion codes for incoming mailboxes.
687	*/
688	enum BUSLOGIC_MAILBOX_INCOMING_COMPLETION
689	{
690	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_FREE = 0x00,
691	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITHOUT_ERROR = 0x01,
692	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_ABORTED = 0x02,
693	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_ABORTED_NOT_FOUND = 0x03,
694	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITH_ERROR = 0x04,
695	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_INVALID_CCB = 0x05
696	};
697
698	/**
699	* Host adapter status for incoming mailboxes.
700	*/
701	enum BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS
702	{
703	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_CMD_COMPLETED = 0x00,
704	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_LINKED_CMD_COMPLETED = 0x0a,
705	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_LINKED_CMD_COMPLETED_WITH_FLAG = 0x0b,
706	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_DATA_UNDERUN = 0x0c,
707	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_SCSI_SELECTION_TIMEOUT = 0x11,
708	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_DATA_OVERRUN = 0x12,
709	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_UNEXPECTED_BUS_FREE = 0x13,
710	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_INVALID_BUS_PHASE_REQUESTED = 0x14,
711	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_INVALID_OUTGOING_MAILBOX_ACTION_CODE = 0x15,
712	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_INVALID_COMMAND_OPERATION_CODE = 0x16,
713	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_LINKED_CCB_HAS_INVALID_LUN = 0x17,
714	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_INVALID_COMMAND_PARAMETER = 0x1a,
715	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_AUTO_REQUEST_SENSE_FAILED = 0x1b,
716	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_TAGGED_QUEUING_MESSAGE_REJECTED = 0x1c,
717	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_UNSUPPORTED_MESSAGE_RECEIVED = 0x1d,
718	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_HARDWARE_FAILED = 0x20,
719	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_TARGET_FAILED_RESPONSE_TO_ATN = 0x21,
720	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_ASSERTED_RST = 0x22,
721	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_OTHER_DEVICE_ASSERTED_RST = 0x23,
722	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_TARGET_DEVICE_RECONNECTED_IMPROPERLY = 0x24,
723	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_ASSERTED_BUS_DEVICE_RESET = 0x25,
724	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_ABORT_QUEUE_GENERATED = 0x26,
725	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_SOFTWARE_ERROR = 0x27,
726	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_HARDWARE_TIMEOUT_ERROR = 0x30,
727	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_SCSI_PARITY_ERROR_DETECTED = 0x34
728	};
729
730	/**
731	* Device status codes for incoming mailboxes.
732	*/
733	enum BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS
734	{
735	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_OPERATION_GOOD = 0x00,
736	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_CHECK_CONDITION = 0x02,
737	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_DEVICE_BUSY = 0x08
738	};
739
740	/**
741	* Opcode types for CCB.
742	*/
743	enum BUSLOGIC_CCB_OPCODE
744	{
745	BUSLOGIC_CCB_OPCODE_INITIATOR_CCB = 0x00,
746	BUSLOGIC_CCB_OPCODE_TARGET_CCB = 0x01,
747	BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_SCATTER_GATHER = 0x02,
748	BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_DATA_LENGTH = 0x03,
749	BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_SCATTER_GATHER = 0x04,
750	BUSLOGIC_CCB_OPCODE_BUS_DEVICE_RESET = 0x81
751	};
752
753	/**
754	* Data transfer direction.
755	*/
756	enum BUSLOGIC_CCB_DIRECTION
757	{
758	BUSLOGIC_CCB_DIRECTION_UNKNOWN = 0x00,
759	BUSLOGIC_CCB_DIRECTION_IN = 0x01,
760	BUSLOGIC_CCB_DIRECTION_OUT = 0x02,
761	BUSLOGIC_CCB_DIRECTION_NO_DATA = 0x03
762	};
763
764	/**
765	* The command control block for a SCSI request.
766	*/
767	typedef struct CCB32
768	{
769	/** Opcode. */
770	uint8_t uOpcode;
771	/** Reserved */
772	unsigned char uReserved1 : 3;
773	/** Data direction for the request. */
774	unsigned char uDataDirection : 2;
775	/** Whether the request is tag queued. */
776	bool fTagQueued : 1;
777	/** Queue tag mode. */
778	unsigned char uQueueTag : 2;
779	/** Length of the SCSI CDB. */
780	uint8_t cbCDB;
781	/** Sense data length. */
782	uint8_t cbSenseData;
783	/** Data length. */
784	uint32_t cbData;
785	/** Data pointer.
786	* This points to the data region or a scatter gather list based on the opcode.
787	*/
788	uint32_t u32PhysAddrData;
789	/** Reserved. */
790	uint8_t uReserved2[2];
791	/** Host adapter status. */
792	uint8_t uHostAdapterStatus;
793	/** Device adapter status. */
794	uint8_t uDeviceStatus;
795	/** The device the request is sent to. */
796	uint8_t uTargetId;
797	/*The LUN in the device. /
798	unsigned char uLogicalUnit : 5;
799	/** Legacy tag. */
800	bool fLegacyTagEnable : 1;
801	/** Legacy queue tag. */
802	unsigned char uLegacyQueueTag : 2;
803	/** The SCSI CDB. (A CDB can be 12 bytes long.) */
804	uint8_t abCDB[12];
805	/** Reserved. */
806	uint8_t uReserved3[6];
807	/** Sense data pointer. */
808	uint32_t u32PhysAddrSenseData;
809	} CCB32, *PCCB32;
810	AssertCompileSize(CCB32, 40);
811
812
813	/**
814	* The 24-bit command control block.
815	*/
816	typedef struct CCB24
817	{
818	/** Opcode. */
819	uint8_t uOpcode;
820	/** The LUN in the device. */
821	unsigned char uLogicalUnit : 3;
822	/** Data direction for the request. */
823	unsigned char uDataDirection : 2;
824	/** The target device ID. */
825	unsigned char uTargetId : 3;
826	/** Length of the SCSI CDB. */
827	uint8_t cbCDB;
828	/** Sense data length. */
829	uint8_t cbSenseData;
830	/** Data length. */
831	Len24 acbData;
832	/** Data pointer.
833	* This points to the data region or a scatter gather list based on the opc
834	*/
835	Addr24 aPhysAddrData;
836	/** Pointer to next CCB for linked commands. */
837	Addr24 aPhysAddrLink;
838	/** Command linking identifier. */
839	uint8_t uLinkId;
840	/** Host adapter status. */
841	uint8_t uHostAdapterStatus;
842	/** Device adapter status. */
843	uint8_t uDeviceStatus;
844	/** Two unused bytes. */
845	uint8_t aReserved[2];
846	/** The SCSI CDB. (A CDB can be 12 bytes long.) */
847	uint8_t abCDB[12];
848	} CCB24, *PCCB24;
849	AssertCompileSize(CCB24, 30);
850
851	/**
852	* The common 24-bit/32-bit command control block. The 32-bit CCB is laid out
853	* such that many fields are in the same location as in the older 24-bit CCB.
854	*/
855	typedef struct CCBC
856	{
857	/** Opcode. */
858	uint8_t uOpcode;
859	/** The LUN in the device. */
860	unsigned char uPad1 : 3;
861	/** Data direction for the request. */
862	unsigned char uDataDirection : 2;
863	/** The target device ID. */
864	unsigned char uPad2 : 3;
865	/** Length of the SCSI CDB. */
866	uint8_t cbCDB;
867	/** Sense data length. */
868	uint8_t cbSenseData;
869	uint8_t aPad1[10];
870	/** Host adapter status. */
871	uint8_t uHostAdapterStatus;
872	/** Device adapter status. */
873	uint8_t uDeviceStatus;
874	uint8_t aPad2[2];
875	/** The SCSI CDB (up to 12 bytes). */
876	uint8_t abCDB[12];
877	} CCBC, *PCCBC;
878	AssertCompileSize(CCB24, 30);
879
880	/* Make sure that the 24-bit/32-bit/common CCB offsets match. */
881	AssertCompileMemberOffset(CCBC, cbCDB, 2);
882	AssertCompileMemberOffset(CCB24, cbCDB, 2);
883	AssertCompileMemberOffset(CCB32, cbCDB, 2);
884	AssertCompileMemberOffset(CCBC, uHostAdapterStatus, 14);
885	AssertCompileMemberOffset(CCB24, uHostAdapterStatus, 14);
886	AssertCompileMemberOffset(CCB32, uHostAdapterStatus, 14);
887	AssertCompileMemberOffset(CCBC, abCDB, 18);
888	AssertCompileMemberOffset(CCB24, abCDB, 18);
889	AssertCompileMemberOffset(CCB32, abCDB, 18);
890
891	/** A union of all CCB types (24-bit/32-bit/common). */
892	typedef union CCBU
893	{
894	CCB32 n; /*< New 32-bit CCB. /
895	CCB24 o; /*< Old 24-bit CCB. /
896	CCBC c; /*< Common CCB subset. /
897	} CCBU, *PCCBU;
898
899	/** 32-bit scatter-gather list entry. */
900	typedef struct SGE32
901	{
902	uint32_t cbSegment;
903	uint32_t u32PhysAddrSegmentBase;
904	} SGE32, *PSGE32;
905	AssertCompileSize(SGE32, 8);
906
907	/** 24-bit scatter-gather list entry. */
908	typedef struct SGE24
909	{
910	Len24 acbSegment;
911	Addr24 aPhysAddrSegmentBase;
912	} SGE24, *PSGE24;
913	AssertCompileSize(SGE24, 6);
914
915	/**
916	* The structure for the "Execute SCSI Command" command.
917	*/
918	typedef struct ESCMD
919	{
920	/** Data length. */
921	uint32_t cbData;
922	/** Data pointer. */
923	uint32_t u32PhysAddrData;
924	/** The device the request is sent to. */
925	uint8_t uTargetId;
926	/** The LUN in the device. */
927	uint8_t uLogicalUnit;
928	/** Reserved */
929	unsigned char uReserved1 : 3;
930	/** Data direction for the request. */
931	unsigned char uDataDirection : 2;
932	/** Reserved */
933	unsigned char uReserved2 : 3;
934	/** Length of the SCSI CDB. */
935	uint8_t cbCDB;
936	/** The SCSI CDB. (A CDB can be 12 bytes long.) */
937	uint8_t abCDB[12];
938	} ESCMD, *PESCMD;
939	AssertCompileSize(ESCMD, 24);
940
941	/**
942	* Task state for a CCB request.
943	*/
944	typedef struct BUSLOGICTASKSTATE
945	{
946	/** Next in the redo list. */
947	PBUSLOGICTASKSTATE pRedoNext;
948	/** Device this task is assigned to. */
949	R3PTRTYPE(PBUSLOGICDEVICE) pTargetDeviceR3;
950	/** The command control block from the guest. */
951	CCBU CommandControlBlockGuest;
952	/** Mailbox read from guest memory. */
953	Mailbox32 MailboxGuest;
954	/** The SCSI request we pass to the underlying SCSI engine. */
955	PDMSCSIREQUEST PDMScsiRequest;
956	/** Data buffer segment */
957	RTSGSEG DataSeg;
958	/** Pointer to the R3 sense buffer. */
959	uint8_t *pbSenseBuffer;
960	/** Flag whether this is a request from the BIOS. */
961	bool fBIOS;
962	/** 24-bit request flag (default is 32-bit). */
963	bool fIs24Bit;
964	/** S/G entry size (depends on the above flag). */
965	uint8_t cbSGEntry;
966	} BUSLOGICTASKSTATE;
967
968	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
969
970	#define PDMIBASE_2_PBUSLOGICDEVICE(pInterface) ( (PBUSLOGICDEVICE)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGICDEVICE, IBase)) )
971	#define PDMISCSIPORT_2_PBUSLOGICDEVICE(pInterface) ( (PBUSLOGICDEVICE)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGICDEVICE, ISCSIPort)) )
972	#define PDMILEDPORTS_2_PBUSLOGICDEVICE(pInterface) ( (PBUSLOGICDEVICE)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGICDEVICE, ILed)) )
973	#define PDMIBASE_2_PBUSLOGIC(pInterface) ( (PBUSLOGIC)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGIC, IBase)) )
974	#define PDMILEDPORTS_2_PBUSLOGIC(pInterface) ( (PBUSLOGIC)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGIC, ILeds)) )
975
976	/*******************************************************************************
977	* Internal Functions *
978	*******************************************************************************/
979	static int buslogicR3RegisterISARange(PBUSLOGIC pBusLogic, uint8_t uBaseCode);
980
981
982	/**
983	* Assert IRQ line of the BusLogic adapter.
984	*
985	* @returns nothing.
986	* @param pBusLogic Pointer to the BusLogic device instance.
987	* @param fSuppressIrq Flag to suppress IRQ generation regardless of fIRQEnabled
988	* @param uFlag Type of interrupt being generated.
989	*/
990	static void buslogicSetInterrupt(PBUSLOGIC pBusLogic, bool fSuppressIrq, uint8_t uIrqType)
991	{
992	LogFlowFunc(("pBusLogic=%#p\n", pBusLogic));
993
994	/* The CMDC interrupt has priority over IMBL and OMBR. */
995	if (uIrqType & (BL_INTR_IMBL \| BL_INTR_OMBR))
996	{
997	if (!(pBusLogic->regInterrupt & BL_INTR_CMDC))
998	pBusLogic->regInterrupt \|= uIrqType; /* Report now. */
999	else
1000	pBusLogic->uPendingIntr \|= uIrqType; /* Report later. */
1001	}
1002	else if (uIrqType & BL_INTR_CMDC)
1003	{
1004	AssertMsg(pBusLogic->regInterrupt == 0 \|\| pBusLogic->regInterrupt == (BL_INTR_INTV \| BL_INTR_CMDC),
1005	("regInterrupt=%02X\n", pBusLogic->regInterrupt));
1006	pBusLogic->regInterrupt \|= uIrqType;
1007	}
1008	else
1009	AssertMsgFailed(("Invalid interrupt state!\n"));
1010
1011	pBusLogic->regInterrupt \|= BL_INTR_INTV;
1012	if (pBusLogic->fIRQEnabled && !fSuppressIrq)
1013	PDMDevHlpPCISetIrq(pBusLogic->CTX_SUFF(pDevIns), 0, 1);
1014	}
1015
1016	/**
1017	* Deasserts the interrupt line of the BusLogic adapter.
1018	*
1019	* @returns nothing
1020	* @param pBuslogic Pointer to the BusLogic device instance.
1021	*/
1022	static void buslogicClearInterrupt(PBUSLOGIC pBusLogic)
1023	{
1024	LogFlowFunc(("pBusLogic=%#p, clearing %#02x (pending %#02x)\n",
1025	pBusLogic, pBusLogic->regInterrupt, pBusLogic->uPendingIntr));
1026	pBusLogic->regInterrupt = 0;
1027	PDMDevHlpPCISetIrq(pBusLogic->CTX_SUFF(pDevIns), 0, 0);
1028	/* If there's another pending interrupt, report it now. */
1029	if (pBusLogic->uPendingIntr)
1030	{
1031	buslogicSetInterrupt(pBusLogic, false, pBusLogic->uPendingIntr);
1032	pBusLogic->uPendingIntr = 0;
1033	}
1034	}
1035
1036	#if defined(IN_RING3)
1037
1038	/**
1039	* Advances the mailbox pointer to the next slot.
1040	*/
1041	DECLINLINE(void) buslogicR3OutgoingMailboxAdvance(PBUSLOGIC pBusLogic)
1042	{
1043	pBusLogic->uMailboxOutgoingPositionCurrent = (pBusLogic->uMailboxOutgoingPositionCurrent + 1) % pBusLogic->cMailbox;
1044	}
1045
1046	/**
1047	* Initialize local RAM of host adapter with default values.
1048	*
1049	* @returns nothing.
1050	* @param pBusLogic.
1051	*/
1052	static void buslogicR3InitializeLocalRam(PBUSLOGIC pBusLogic)
1053	{
1054	/*
1055	* These values are mostly from what I think is right
1056	* looking at the dmesg output from a Linux guest inside
1057	* a VMware server VM.
1058	*
1059	* So they don't have to be right :)
1060	*/
1061	memset(pBusLogic->LocalRam.u8View, 0, sizeof(HostAdapterLocalRam));
1062	pBusLogic->LocalRam.structured.autoSCSIData.fLevelSensitiveInterrupt = true;
1063	pBusLogic->LocalRam.structured.autoSCSIData.fParityCheckingEnabled = true;
1064	pBusLogic->LocalRam.structured.autoSCSIData.fExtendedTranslation = true; /* Same as in geometry register. */
1065	pBusLogic->LocalRam.structured.autoSCSIData.u16DeviceEnabledMask = ~0; /* All enabled. Maybe mask out non present devices? */
1066	pBusLogic->LocalRam.structured.autoSCSIData.u16WidePermittedMask = ~0;
1067	pBusLogic->LocalRam.structured.autoSCSIData.u16FastPermittedMask = ~0;
1068	pBusLogic->LocalRam.structured.autoSCSIData.u16SynchronousPermittedMask = ~0;
1069	pBusLogic->LocalRam.structured.autoSCSIData.u16DisconnectPermittedMask = ~0;
1070	pBusLogic->LocalRam.structured.autoSCSIData.fStrictRoundRobinMode = pBusLogic->fStrictRoundRobinMode;
1071	pBusLogic->LocalRam.structured.autoSCSIData.u16UltraPermittedMask = ~0;
1072	/** @todo calculate checksum? */
1073	}
1074
1075	/**
1076	* Do a hardware reset of the buslogic adapter.
1077	*
1078	* @returns VBox status code.
1079	* @param pBusLogic Pointer to the BusLogic device instance.
1080	* @param fResetIO Flag determining whether ISA I/O should be reset.
1081	*/
1082	static int buslogicR3HwReset(PBUSLOGIC pBusLogic, bool fResetIO)
1083	{
1084	LogFlowFunc(("pBusLogic=%#p\n", pBusLogic));
1085
1086	/* Reset registers to default values. */
1087	pBusLogic->regStatus = BL_STAT_HARDY \| BL_STAT_INREQ;
1088	pBusLogic->regGeometry = BL_GEOM_XLATEN;
1089	pBusLogic->uOperationCode = 0xff; /* No command executing. */
1090	pBusLogic->iParameter = 0;
1091	pBusLogic->cbCommandParametersLeft = 0;
1092	pBusLogic->fIRQEnabled = true;
1093	pBusLogic->fStrictRoundRobinMode = false;
1094	pBusLogic->fExtendedLunCCBFormat = false;
1095	pBusLogic->uMailboxOutgoingPositionCurrent = 0;
1096	pBusLogic->uMailboxIncomingPositionCurrent = 0;
1097
1098	/* Clear any active/pending interrupts. */
1099	pBusLogic->uPendingIntr = 0;
1100	buslogicClearInterrupt(pBusLogic);
1101
1102	/* Guest-initiated HBA reset does not affect ISA port I/O. */
1103	if (fResetIO)
1104	{
1105	buslogicR3RegisterISARange(pBusLogic, pBusLogic->uDefaultISABaseCode);
1106	}
1107	buslogicR3InitializeLocalRam(pBusLogic);
1108	vboxscsiInitialize(&pBusLogic->VBoxSCSI);
1109
1110	return VINF_SUCCESS;
1111	}
1112
1113	#endif /* IN_RING3 */
1114
1115	/**
1116	* Resets the command state machine for the next command and notifies the guest.
1117	*
1118	* @returns nothing.
1119	* @param pBusLogic Pointer to the BusLogic device instance
1120	* @param fSuppressIrq Flag to suppress IRQ generation regardless of current state
1121	*/
1122	static void buslogicCommandComplete(PBUSLOGIC pBusLogic, bool fSuppressIrq)
1123	{
1124	LogFlowFunc(("pBusLogic=%#p\n", pBusLogic));
1125
1126	pBusLogic->fUseLocalRam = false;
1127	pBusLogic->regStatus \|= BL_STAT_HARDY;
1128	pBusLogic->iReply = 0;
1129
1130	/* Modify I/O address does not generate an interrupt. */
1131	if (pBusLogic->uOperationCode != BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND)
1132	{
1133	/* Notify that the command is complete. */
1134	pBusLogic->regStatus &= ~BL_STAT_DIRRDY;
1135	buslogicSetInterrupt(pBusLogic, fSuppressIrq, BL_INTR_CMDC);
1136	}
1137
1138	pBusLogic->uOperationCode = 0xff;
1139	pBusLogic->iParameter = 0;
1140	}
1141
1142	#if defined(IN_RING3)
1143
1144	/**
1145	* Initiates a hard reset which was issued from the guest.
1146	*
1147	* @returns nothing
1148	* @param pBusLogic Pointer to the BusLogic device instance.
1149	* @param fHardReset Flag initiating a hard (vs. soft) reset.
1150	*/
1151	static void buslogicR3InitiateReset(PBUSLOGIC pBusLogic, bool fHardReset)
1152	{
1153	LogFlowFunc(("pBusLogic=%#p fHardReset=%d\n", pBusLogic, fHardReset));
1154
1155	buslogicR3HwReset(pBusLogic, false);
1156
1157	if (fHardReset)
1158	{
1159	/* Set the diagnostic active bit in the status register and clear the ready state. */
1160	pBusLogic->regStatus \|= BL_STAT_DACT;
1161	pBusLogic->regStatus &= ~BL_STAT_HARDY;
1162
1163	/* Remember when the guest initiated a reset (after we're done resetting). */
1164	pBusLogic->u64ResetTime = PDMDevHlpTMTimeVirtGetNano(pBusLogic->CTX_SUFF(pDevIns));
1165	}
1166	}
1167
1168	/**
1169	* Send a mailbox with set status codes to the guest.
1170	*
1171	* @returns nothing.
1172	* @param pBusLogic Pointer to the BusLogic device instance.
1173	* @param pTaskState Pointer to the task state with the mailbox to send.
1174	* @param uHostAdapterStatus The host adapter status code to set.
1175	* @param uDeviceStatus The target device status to set.
1176	* @param uMailboxCompletionCode Completion status code to set in the mailbox.
1177	*/
1178	static void buslogicR3SendIncomingMailbox(PBUSLOGIC pBusLogic, PBUSLOGICTASKSTATE pTaskState,
1179	uint8_t uHostAdapterStatus, uint8_t uDeviceStatus,
1180	uint8_t uMailboxCompletionCode)
1181	{
1182	pTaskState->MailboxGuest.u.in.uHostAdapterStatus = uHostAdapterStatus;
1183	pTaskState->MailboxGuest.u.in.uTargetDeviceStatus = uDeviceStatus;
1184	pTaskState->MailboxGuest.u.in.uCompletionCode = uMailboxCompletionCode;
1185
1186	int rc = PDMCritSectEnter(&pBusLogic->CritSectIntr, VINF_SUCCESS);
1187	AssertRC(rc);
1188
1189	RTGCPHYS GCPhysAddrMailboxIncoming = pBusLogic->GCPhysAddrMailboxIncomingBase
1190	+ ( pBusLogic->uMailboxIncomingPositionCurrent
1191	* (pTaskState->fIs24Bit ? sizeof(Mailbox24) : sizeof(Mailbox32)) );
1192
1193	if (uMailboxCompletionCode != BUSLOGIC_MAILBOX_INCOMING_COMPLETION_ABORTED_NOT_FOUND)
1194	{
1195	RTGCPHYS GCPhysAddrCCB = pTaskState->MailboxGuest.u32PhysAddrCCB;
1196	LogFlowFunc(("Completing CCB %RGp hstat=%u, dstat=%u, outgoing mailbox at %RGp\n", GCPhysAddrCCB,
1197	uHostAdapterStatus, uDeviceStatus, GCPhysAddrMailboxIncoming));
1198
1199	/* Update CCB. */
1200	pTaskState->CommandControlBlockGuest.c.uHostAdapterStatus = uHostAdapterStatus;
1201	pTaskState->CommandControlBlockGuest.c.uDeviceStatus = uDeviceStatus;
1202	/* Rewrite CCB up to the CDB; perhaps more than necessary. */
1203	PDMDevHlpPCIPhysWrite(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrCCB,
1204	&pTaskState->CommandControlBlockGuest, RT_OFFSETOF(CCBC, abCDB));
1205	}
1206
1207	# ifdef RT_STRICT
1208	uint8_t uCode;
1209	unsigned uCodeOffs = pTaskState->fIs24Bit ? RT_OFFSETOF(Mailbox24, uCmdState) : RT_OFFSETOF(Mailbox32, u.out.uActionCode);
1210	PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrMailboxIncoming + uCodeOffs, &uCode, sizeof(uCode));
1211	Assert(uCode == BUSLOGIC_MAILBOX_INCOMING_COMPLETION_FREE);
1212	# endif
1213
1214	/* Update mailbox. */
1215	if (pTaskState->fIs24Bit)
1216	{
1217	Mailbox24 Mbx24;
1218
1219	Mbx24.uCmdState = pTaskState->MailboxGuest.u.in.uCompletionCode;
1220	U32_TO_ADDR(Mbx24.aPhysAddrCCB, pTaskState->MailboxGuest.u32PhysAddrCCB);
1221	Log(("24-bit mailbox: completion code=%u, CCB at %RGp\n", Mbx24.uCmdState, (RTGCPHYS)ADDR_TO_U32(Mbx24.aPhysAddrCCB)));
1222	PDMDevHlpPCIPhysWrite(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrMailboxIncoming, &Mbx24, sizeof(Mailbox24));
1223	}
1224	else
1225	{
1226	Log(("32-bit mailbox: completion code=%u, CCB at %RGp\n", pTaskState->MailboxGuest.u.in.uCompletionCode, (RTGCPHYS)pTaskState->MailboxGuest.u32PhysAddrCCB));
1227	PDMDevHlpPCIPhysWrite(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrMailboxIncoming,
1228	&pTaskState->MailboxGuest, sizeof(Mailbox32));
1229	}
1230
1231	/* Advance to next mailbox position. */
1232	pBusLogic->uMailboxIncomingPositionCurrent++;
1233	if (pBusLogic->uMailboxIncomingPositionCurrent >= pBusLogic->cMailbox)
1234	pBusLogic->uMailboxIncomingPositionCurrent = 0;
1235
1236	# ifdef LOG_ENABLED
1237	ASMAtomicIncU32(&pBusLogic->cInMailboxesReady);
1238	# endif
1239
1240	buslogicSetInterrupt(pBusLogic, false, BL_INTR_IMBL);
1241
1242	PDMCritSectLeave(&pBusLogic->CritSectIntr);
1243	}
1244
1245	# ifdef LOG_ENABLED
1246
1247	/**
1248	* Dumps the content of a mailbox for debugging purposes.
1249	*
1250	* @return nothing
1251	* @param pMailbox The mailbox to dump.
1252	* @param fOutgoing true if dumping the outgoing state.
1253	* false if dumping the incoming state.
1254	*/
1255	static void buslogicR3DumpMailboxInfo(PMailbox32 pMailbox, bool fOutgoing)
1256	{
1257	Log(("%s: Dump for %s mailbox:\n", __FUNCTION__, fOutgoing ? "outgoing" : "incoming"));
1258	Log(("%s: u32PhysAddrCCB=%#x\n", __FUNCTION__, pMailbox->u32PhysAddrCCB));
1259	if (fOutgoing)
1260	{
1261	Log(("%s: uActionCode=%u\n", __FUNCTION__, pMailbox->u.out.uActionCode));
1262	}
1263	else
1264	{
1265	Log(("%s: uHostAdapterStatus=%u\n", __FUNCTION__, pMailbox->u.in.uHostAdapterStatus));
1266	Log(("%s: uTargetDeviceStatus=%u\n", __FUNCTION__, pMailbox->u.in.uTargetDeviceStatus));
1267	Log(("%s: uCompletionCode=%u\n", __FUNCTION__, pMailbox->u.in.uCompletionCode));
1268	}
1269	}
1270
1271	/**
1272	* Dumps the content of a command control block for debugging purposes.
1273	*
1274	* @returns nothing.
1275	* @param pCCB Pointer to the command control block to dump.
1276	* @param fIs24BitCCB Flag to determine CCB format.
1277	*/
1278	static void buslogicR3DumpCCBInfo(PCCBU pCCB, bool fIs24BitCCB)
1279	{
1280	Log(("%s: Dump for %s Command Control Block:\n", __FUNCTION__, fIs24BitCCB ? "24-bit" : "32-bit"));
1281	Log(("%s: uOpCode=%#x\n", __FUNCTION__, pCCB->c.uOpcode));
1282	Log(("%s: uDataDirection=%u\n", __FUNCTION__, pCCB->c.uDataDirection));
1283	Log(("%s: cbCDB=%u\n", __FUNCTION__, pCCB->c.cbCDB));
1284	Log(("%s: cbSenseData=%u\n", __FUNCTION__, pCCB->c.cbSenseData));
1285	Log(("%s: uHostAdapterStatus=%u\n", __FUNCTION__, pCCB->c.uHostAdapterStatus));
1286	Log(("%s: uDeviceStatus=%u\n", __FUNCTION__, pCCB->c.uDeviceStatus));
1287	if (fIs24BitCCB)
1288	{
1289	Log(("%s: cbData=%u\n", __FUNCTION__, LEN_TO_U32(pCCB->o.acbData)));
1290	Log(("%s: PhysAddrData=%#x\n", __FUNCTION__, ADDR_TO_U32(pCCB->o.aPhysAddrData)));
1291	Log(("%s: uTargetId=%u\n", __FUNCTION__, pCCB->o.uTargetId));
1292	Log(("%s: uLogicalUnit=%u\n", __FUNCTION__, pCCB->o.uLogicalUnit));
1293	}
1294	else
1295	{
1296	Log(("%s: cbData=%u\n", __FUNCTION__, pCCB->n.cbData));
1297	Log(("%s: PhysAddrData=%#x\n", __FUNCTION__, pCCB->n.u32PhysAddrData));
1298	Log(("%s: uTargetId=%u\n", __FUNCTION__, pCCB->n.uTargetId));
1299	Log(("%s: uLogicalUnit=%u\n", __FUNCTION__, pCCB->n.uLogicalUnit));
1300	Log(("%s: fTagQueued=%d\n", __FUNCTION__, pCCB->n.fTagQueued));
1301	Log(("%s: uQueueTag=%u\n", __FUNCTION__, pCCB->n.uQueueTag));
1302	Log(("%s: fLegacyTagEnable=%u\n", __FUNCTION__, pCCB->n.fLegacyTagEnable));
1303	Log(("%s: uLegacyQueueTag=%u\n", __FUNCTION__, pCCB->n.uLegacyQueueTag));
1304	Log(("%s: PhysAddrSenseData=%#x\n", __FUNCTION__, pCCB->n.u32PhysAddrSenseData));
1305	}
1306	Log(("%s: uCDB[0]=%#x\n", __FUNCTION__, pCCB->c.abCDB[0]));
1307	for (int i = 1; i < pCCB->c.cbCDB; i++)
1308	Log(("%s: uCDB[%d]=%u\n", __FUNCTION__, i, pCCB->c.abCDB[i]));
1309	}
1310
1311	# endif /* LOG_ENABLED */
1312
1313	/**
1314	* Allocate data buffer.
1315	*
1316	* @param pTaskState Pointer to the task state.
1317	* @param GCSGList Guest physical address of S/G list.
1318	* @param cEntries Number of list entries to read.
1319	* @param pSGEList Pointer to 32-bit S/G list storage.
1320	*/
1321	static void buslogicR3ReadSGEntries(PBUSLOGICTASKSTATE pTaskState, RTGCPHYS GCSGList, uint32_t cEntries, SGE32 *pSGEList)
1322	{
1323	PPDMDEVINS pDevIns = pTaskState->CTX_SUFF(pTargetDevice)->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);
1324	SGE24 aSGE24[32];
1325	Assert(cEntries <= RT_ELEMENTS(aSGE24));
1326
1327	/* Read the S/G entries. Convert 24-bit entries to 32-bit format. */
1328	if (pTaskState->fIs24Bit)
1329	{
1330	Log2(("Converting %u 24-bit S/G entries to 32-bit\n", cEntries));
1331	PDMDevHlpPhysRead(pDevIns, GCSGList, &aSGE24, cEntries * sizeof(SGE24));
1332	for (uint32_t i = 0; i < cEntries; ++i)
1333	{
1334	pSGEList[i].cbSegment = LEN_TO_U32(aSGE24[i].acbSegment);
1335	pSGEList[i].u32PhysAddrSegmentBase = ADDR_TO_U32(aSGE24[i].aPhysAddrSegmentBase);
1336	}
1337	}
1338	else
1339	PDMDevHlpPhysRead(pDevIns, GCSGList, pSGEList, cEntries * sizeof(SGE32));
1340	}
1341
1342	/**
1343	* Allocate data buffer.
1344	*
1345	* @returns VBox status code.
1346	* @param pTaskState Pointer to the task state.
1347	*/
1348	static int buslogicR3DataBufferAlloc(PBUSLOGICTASKSTATE pTaskState)
1349	{
1350	PPDMDEVINS pDevIns = pTaskState->CTX_SUFF(pTargetDevice)->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);
1351	uint32_t cbDataCCB;
1352	uint32_t u32PhysAddrCCB;
1353
1354	/* Extract the data length and physical address from the CCB. */
1355	if (pTaskState->fIs24Bit)
1356	{
1357	u32PhysAddrCCB = ADDR_TO_U32(pTaskState->CommandControlBlockGuest.o.aPhysAddrData);
1358	cbDataCCB = LEN_TO_U32(pTaskState->CommandControlBlockGuest.o.acbData);
1359	}
1360	else
1361	{
1362	u32PhysAddrCCB = pTaskState->CommandControlBlockGuest.n.u32PhysAddrData;
1363	cbDataCCB = pTaskState->CommandControlBlockGuest.n.cbData;
1364	}
1365
1366	if ( (pTaskState->CommandControlBlockGuest.c.uDataDirection != BUSLOGIC_CCB_DIRECTION_NO_DATA)
1367	&& cbDataCCB)
1368	{
1369	/** @todo Check following assumption and what residual means. */
1370	/*
1371	* The BusLogic adapter can handle two different data buffer formats.
1372	* The first one is that the data pointer entry in the CCB points to
1373	* the buffer directly. In second mode the data pointer points to a
1374	* scatter gather list which describes the buffer.
1375	*/
1376	if ( (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_SCATTER_GATHER)
1377	\|\| (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_SCATTER_GATHER))
1378	{
1379	uint32_t cScatterGatherGCRead;
1380	uint32_t iScatterGatherEntry;
1381	SGE32 aScatterGatherReadGC[32]; /* A buffer for scatter gather list entries read from guest memory. */
1382	uint32_t cScatterGatherGCLeft = cbDataCCB / pTaskState->cbSGEntry;
1383	RTGCPHYS GCPhysAddrScatterGatherCurrent = u32PhysAddrCCB;
1384	size_t cbDataToTransfer = 0;
1385
1386	/* Count number of bytes to transfer. */
1387	do
1388	{
1389	cScatterGatherGCRead = (cScatterGatherGCLeft < RT_ELEMENTS(aScatterGatherReadGC))
1390	? cScatterGatherGCLeft
1391	: RT_ELEMENTS(aScatterGatherReadGC);
1392	cScatterGatherGCLeft -= cScatterGatherGCRead;
1393
1394	buslogicR3ReadSGEntries(pTaskState, GCPhysAddrScatterGatherCurrent, cScatterGatherGCRead, aScatterGatherReadGC);
1395
1396	for (iScatterGatherEntry = 0; iScatterGatherEntry < cScatterGatherGCRead; iScatterGatherEntry++)
1397	{
1398	RTGCPHYS GCPhysAddrDataBase;
1399
1400	Log(("%s: iScatterGatherEntry=%u\n", __FUNCTION__, iScatterGatherEntry));
1401
1402	GCPhysAddrDataBase = (RTGCPHYS)aScatterGatherReadGC[iScatterGatherEntry].u32PhysAddrSegmentBase;
1403	cbDataToTransfer += aScatterGatherReadGC[iScatterGatherEntry].cbSegment;
1404
1405	Log(("%s: GCPhysAddrDataBase=%RGp cbDataToTransfer=%u\n",
1406	__FUNCTION__, GCPhysAddrDataBase,
1407	aScatterGatherReadGC[iScatterGatherEntry].cbSegment));
1408	}
1409
1410	/* Set address to the next entries to read. */
1411	GCPhysAddrScatterGatherCurrent += cScatterGatherGCRead * pTaskState->cbSGEntry;
1412	} while (cScatterGatherGCLeft > 0);
1413
1414	Log(("%s: cbDataToTransfer=%d\n", __FUNCTION__, cbDataToTransfer));
1415
1416	/* Allocate buffer */
1417	pTaskState->DataSeg.cbSeg = cbDataToTransfer;
1418	pTaskState->DataSeg.pvSeg = RTMemAlloc(pTaskState->DataSeg.cbSeg);
1419	if (!pTaskState->DataSeg.pvSeg)
1420	return VERR_NO_MEMORY;
1421
1422	/* Copy the data if needed */
1423	if ( (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_OUT)
1424	\|\| (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_UNKNOWN))
1425	{
1426	cScatterGatherGCLeft = cbDataCCB / pTaskState->cbSGEntry;
1427	GCPhysAddrScatterGatherCurrent = u32PhysAddrCCB;
1428	uint8_t pbData = (uint8_t )pTaskState->DataSeg.pvSeg;
1429
1430	do
1431	{
1432	cScatterGatherGCRead = (cScatterGatherGCLeft < RT_ELEMENTS(aScatterGatherReadGC))
1433	? cScatterGatherGCLeft
1434	: RT_ELEMENTS(aScatterGatherReadGC);
1435	cScatterGatherGCLeft -= cScatterGatherGCRead;
1436
1437	buslogicR3ReadSGEntries(pTaskState, GCPhysAddrScatterGatherCurrent, cScatterGatherGCRead, aScatterGatherReadGC);
1438
1439	for (iScatterGatherEntry = 0; iScatterGatherEntry < cScatterGatherGCRead; iScatterGatherEntry++)
1440	{
1441	RTGCPHYS GCPhysAddrDataBase;
1442
1443	Log(("%s: iScatterGatherEntry=%u\n", __FUNCTION__, iScatterGatherEntry));
1444
1445	GCPhysAddrDataBase = (RTGCPHYS)aScatterGatherReadGC[iScatterGatherEntry].u32PhysAddrSegmentBase;
1446	cbDataToTransfer = aScatterGatherReadGC[iScatterGatherEntry].cbSegment;
1447
1448	Log(("%s: GCPhysAddrDataBase=%RGp cbDataToTransfer=%u\n", __FUNCTION__, GCPhysAddrDataBase, cbDataToTransfer));
1449
1450	PDMDevHlpPhysRead(pDevIns, GCPhysAddrDataBase, pbData, cbDataToTransfer);
1451	pbData += cbDataToTransfer;
1452	}
1453
1454	/* Set address to the next entries to read. */
1455	GCPhysAddrScatterGatherCurrent += cScatterGatherGCRead * pTaskState->cbSGEntry;
1456	} while (cScatterGatherGCLeft > 0);
1457	}
1458
1459	}
1460	else if ( pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB
1461	\|\| pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_DATA_LENGTH)
1462	{
1463	/* The buffer is not scattered. */
1464	RTGCPHYS GCPhysAddrDataBase = u32PhysAddrCCB;
1465
1466	AssertMsg(GCPhysAddrDataBase != 0, ("Physical address is 0\n"));
1467
1468	pTaskState->DataSeg.cbSeg = cbDataCCB;
1469	pTaskState->DataSeg.pvSeg = RTMemAlloc(pTaskState->DataSeg.cbSeg);
1470	if (!pTaskState->DataSeg.pvSeg)
1471	return VERR_NO_MEMORY;
1472
1473	Log(("Non scattered buffer:\n"));
1474	Log(("u32PhysAddrData=%#x\n", u32PhysAddrCCB));
1475	Log(("cbData=%u\n", cbDataCCB));
1476	Log(("GCPhysAddrDataBase=0x%RGp\n", GCPhysAddrDataBase));
1477
1478	/* Copy the data into the buffer. */
1479	PDMDevHlpPhysRead(pDevIns, GCPhysAddrDataBase, pTaskState->DataSeg.pvSeg, pTaskState->DataSeg.cbSeg);
1480	}
1481	}
1482
1483	return VINF_SUCCESS;
1484	}
1485
1486	/**
1487	* Free allocated resources used for the scatter gather list.
1488	*
1489	* @returns nothing.
1490	* @param pTaskState Pointer to the task state.
1491	*/
1492	static void buslogicR3DataBufferFree(PBUSLOGICTASKSTATE pTaskState)
1493	{
1494	PPDMDEVINS pDevIns = pTaskState->CTX_SUFF(pTargetDevice)->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);
1495	uint32_t cbDataCCB;
1496	uint32_t u32PhysAddrCCB;
1497
1498	/* Extract the data length and physical address from the CCB. */
1499	if (pTaskState->fIs24Bit)
1500	{
1501	u32PhysAddrCCB = ADDR_TO_U32(pTaskState->CommandControlBlockGuest.o.aPhysAddrData);
1502	cbDataCCB = LEN_TO_U32(pTaskState->CommandControlBlockGuest.o.acbData);
1503	}
1504	else
1505	{
1506	u32PhysAddrCCB = pTaskState->CommandControlBlockGuest.n.u32PhysAddrData;
1507	cbDataCCB = pTaskState->CommandControlBlockGuest.n.cbData;
1508	}
1509
1510	#if 1
1511	/* Hack for NT 10/91: A CCB describes a 2K buffer, but TEST UNIT READY is executed. This command
1512	* returns no data, hence the buffer must be left alone!
1513	*/
1514	if (pTaskState->CommandControlBlockGuest.c.abCDB[0] == 0)
1515	cbDataCCB = 0;
1516	#endif
1517
1518	LogFlowFunc(("pTaskState=%#p cbDataCCB=%u direction=%u cbSeg=%u\n", pTaskState, cbDataCCB,
1519	pTaskState->CommandControlBlockGuest.c.uDataDirection, pTaskState->DataSeg.cbSeg));
1520
1521	if ( (cbDataCCB > 0)
1522	&& ( (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_IN)
1523	\|\| (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_UNKNOWN)))
1524	{
1525	if ( (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_SCATTER_GATHER)
1526	\|\| (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_SCATTER_GATHER))
1527	{
1528	uint32_t cScatterGatherGCRead;
1529	uint32_t iScatterGatherEntry;
1530	SGE32 aScatterGatherReadGC[32]; /* Number of scatter gather list entries read from guest memory. */
1531	uint32_t cScatterGatherGCLeft = cbDataCCB / pTaskState->cbSGEntry;
1532	RTGCPHYS GCPhysAddrScatterGatherCurrent = u32PhysAddrCCB;
1533	uint8_t pbData = (uint8_t )pTaskState->DataSeg.pvSeg;
1534
1535	do
1536	{
1537	cScatterGatherGCRead = (cScatterGatherGCLeft < RT_ELEMENTS(aScatterGatherReadGC))
1538	? cScatterGatherGCLeft
1539	: RT_ELEMENTS(aScatterGatherReadGC);
1540	cScatterGatherGCLeft -= cScatterGatherGCRead;
1541
1542	buslogicR3ReadSGEntries(pTaskState, GCPhysAddrScatterGatherCurrent, cScatterGatherGCRead, aScatterGatherReadGC);
1543
1544	for (iScatterGatherEntry = 0; iScatterGatherEntry < cScatterGatherGCRead; iScatterGatherEntry++)
1545	{
1546	RTGCPHYS GCPhysAddrDataBase;
1547	size_t cbDataToTransfer;
1548
1549	Log(("%s: iScatterGatherEntry=%u\n", __FUNCTION__, iScatterGatherEntry));
1550
1551	GCPhysAddrDataBase = (RTGCPHYS)aScatterGatherReadGC[iScatterGatherEntry].u32PhysAddrSegmentBase;
1552	cbDataToTransfer = aScatterGatherReadGC[iScatterGatherEntry].cbSegment;
1553
1554	Log(("%s: GCPhysAddrDataBase=%RGp cbDataToTransfer=%u\n", __FUNCTION__, GCPhysAddrDataBase, cbDataToTransfer));
1555
1556	PDMDevHlpPCIPhysWrite(pDevIns, GCPhysAddrDataBase, pbData, cbDataToTransfer);
1557	pbData += cbDataToTransfer;
1558	}
1559
1560	/* Set address to the next entries to read. */
1561	GCPhysAddrScatterGatherCurrent += cScatterGatherGCRead * pTaskState->cbSGEntry;
1562	} while (cScatterGatherGCLeft > 0);
1563
1564	}
1565	else if ( pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB
1566	\|\| pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_DATA_LENGTH)
1567	{
1568	/* The buffer is not scattered. */
1569	RTGCPHYS GCPhysAddrDataBase = u32PhysAddrCCB;
1570
1571	AssertMsg(GCPhysAddrDataBase != 0, ("Physical address is 0\n"));
1572
1573	Log(("Non-scattered buffer:\n"));
1574	Log(("u32PhysAddrData=%#x\n", u32PhysAddrCCB));
1575	Log(("cbData=%u\n", cbDataCCB));
1576	Log(("GCPhysAddrDataBase=0x%RGp\n", GCPhysAddrDataBase));
1577
1578	/* Copy the data into the guest memory. */
1579	PDMDevHlpPCIPhysWrite(pDevIns, GCPhysAddrDataBase, pTaskState->DataSeg.pvSeg, pTaskState->DataSeg.cbSeg);
1580	}
1581
1582	}
1583	/* Update residual data length. */
1584	if ( (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_DATA_LENGTH)
1585	\|\| (pTaskState->CommandControlBlockGuest.c.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_SCATTER_GATHER))
1586	{
1587	uint32_t cbResidual;
1588
1589	/** @todo we need to get the actual transfer length from the VSCSI layer?! */
1590	cbResidual = 0; //LEN_TO_U32(pTaskState->CCBGuest.acbData) - ???;
1591	if (pTaskState->fIs24Bit)
1592	U32_TO_LEN(pTaskState->CommandControlBlockGuest.o.acbData, cbResidual);
1593	else
1594	pTaskState->CommandControlBlockGuest.n.cbData = cbResidual;
1595	}
1596
1597	RTMemFree(pTaskState->DataSeg.pvSeg);
1598	pTaskState->DataSeg.pvSeg = NULL;
1599	pTaskState->DataSeg.cbSeg = 0;
1600	}
1601
1602	/** Convert sense buffer length taking into account shortcut values. */
1603	static uint32_t buslogicR3ConvertSenseBufferLength(uint32_t cbSense)
1604	{
1605	/* Convert special sense buffer length values. */
1606	if (cbSense == 0)
1607	cbSense = 14; /* 0 means standard 14-byte buffer. */
1608	else if (cbSense == 1)
1609	cbSense = 0; /* 1 means no sense data. */
1610	else if (cbSense < 8)
1611	AssertMsgFailed(("Reserved cbSense value of %d used!\n", cbSense));
1612
1613	return cbSense;
1614	}
1615
1616	/**
1617	* Free the sense buffer.
1618	*
1619	* @returns nothing.
1620	* @param pTaskState Pointer to the task state.
1621	* @param fCopy If sense data should be copied to guest memory.
1622	*/
1623	static void buslogicR3SenseBufferFree(PBUSLOGICTASKSTATE pTaskState, bool fCopy)
1624	{
1625	uint32_t cbSenseBuffer;
1626
1627	cbSenseBuffer = buslogicR3ConvertSenseBufferLength(pTaskState->CommandControlBlockGuest.c.cbSenseData);
1628
1629	/* Copy the sense buffer into guest memory if requested. */
1630	if (fCopy && cbSenseBuffer)
1631	{
1632	PPDMDEVINS pDevIns = pTaskState->CTX_SUFF(pTargetDevice)->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);
1633	RTGCPHYS GCPhysAddrSenseBuffer;
1634
1635	/* With 32-bit CCBs, the (optional) sense buffer physical address is provided separately.
1636	* On the other hand, with 24-bit CCBs, the sense buffer is simply located at the end of
1637	* the CCB, right after the variable-length CDB.
1638	*/
1639	if (pTaskState->fIs24Bit)
1640	{
1641	GCPhysAddrSenseBuffer = pTaskState->MailboxGuest.u32PhysAddrCCB;
1642	GCPhysAddrSenseBuffer += pTaskState->CommandControlBlockGuest.c.cbCDB + RT_OFFSETOF(CCB24, abCDB);
1643	}
1644	else
1645	GCPhysAddrSenseBuffer = pTaskState->CommandControlBlockGuest.n.u32PhysAddrSenseData;
1646
1647	Log3(("%s: sense buffer: %.*Rhxs\n", __FUNCTION__, cbSenseBuffer, pTaskState->pbSenseBuffer));
1648	PDMDevHlpPCIPhysWrite(pDevIns, GCPhysAddrSenseBuffer, pTaskState->pbSenseBuffer, cbSenseBuffer);
1649	}
1650
1651	RTMemFree(pTaskState->pbSenseBuffer);
1652	pTaskState->pbSenseBuffer = NULL;
1653	}
1654
1655	/**
1656	* Alloc the sense buffer.
1657	*
1658	* @returns VBox status code.
1659	* @param pTaskState Pointer to the task state.
1660	* @note Current assumption is that the sense buffer is not scattered and does not cross a page boundary.
1661	*/
1662	static int buslogicR3SenseBufferAlloc(PBUSLOGICTASKSTATE pTaskState)
1663	{
1664	PPDMDEVINS pDevIns = pTaskState->CTX_SUFF(pTargetDevice)->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);
1665	uint32_t cbSenseBuffer;
1666
1667	pTaskState->pbSenseBuffer = NULL;
1668
1669	cbSenseBuffer = buslogicR3ConvertSenseBufferLength(pTaskState->CommandControlBlockGuest.c.cbSenseData);
1670	if (cbSenseBuffer)
1671	{
1672	pTaskState->pbSenseBuffer = (uint8_t *)RTMemAllocZ(cbSenseBuffer);
1673	if (!pTaskState->pbSenseBuffer)
1674	return VERR_NO_MEMORY;
1675	}
1676
1677	return VINF_SUCCESS;
1678	}
1679
1680	#endif /* IN_RING3 */
1681
1682	/**
1683	* Parses the command buffer and executes it.
1684	*
1685	* @returns VBox status code.
1686	* @param pBusLogic Pointer to the BusLogic device instance.
1687	*/
1688	static int buslogicProcessCommand(PBUSLOGIC pBusLogic)
1689	{
1690	int rc = VINF_SUCCESS;
1691	bool fSuppressIrq = false;
1692
1693	LogFlowFunc(("pBusLogic=%#p\n", pBusLogic));
1694	AssertMsg(pBusLogic->uOperationCode != 0xff, ("There is no command to execute\n"));
1695
1696	switch (pBusLogic->uOperationCode)
1697	{
1698	case BUSLOGICCOMMAND_TEST_CMDC_INTERRUPT:
1699	/* Valid command, no reply. */
1700	pBusLogic->cbReplyParametersLeft = 0;
1701	break;
1702	case BUSLOGICCOMMAND_INQUIRE_PCI_HOST_ADAPTER_INFORMATION:
1703	{
1704	PReplyInquirePCIHostAdapterInformation pReply = (PReplyInquirePCIHostAdapterInformation)pBusLogic->aReplyBuffer;
1705	memset(pReply, 0, sizeof(ReplyInquirePCIHostAdapterInformation));
1706
1707	/* It seems VMware does not provide valid information here too, lets do the same :) */
1708	pReply->InformationIsValid = 0;
1709	pReply->IsaIOPort = pBusLogic->uISABaseCode;
1710	pReply->IRQ = PCIDevGetInterruptLine(&pBusLogic->dev);
1711	pBusLogic->cbReplyParametersLeft = sizeof(ReplyInquirePCIHostAdapterInformation);
1712	break;
1713	}
1714	case BUSLOGICCOMMAND_MODIFY_IO_ADDRESS:
1715	{
1716	/* Modify the ISA-compatible I/O port base. Note that this technically
1717	* violates the PCI spec, as this address is not reported through PCI.
1718	* However, it is required for compatibility with old drivers.
1719	*/
1720	#ifdef IN_RING3
1721	Log(("ISA I/O for PCI (code %x)\n", pBusLogic->aCommandBuffer[0]));
1722	buslogicR3RegisterISARange(pBusLogic, pBusLogic->aCommandBuffer[0]);
1723	pBusLogic->cbReplyParametersLeft = 0;
1724	fSuppressIrq = true;
1725	break;
1726	#else
1727	AssertMsgFailed(("Must never get here!\n"));
1728	#endif
1729	}
1730	case BUSLOGICCOMMAND_INQUIRE_BOARD_ID:
1731	{
1732	/* The special option byte is important: If it is '0' or 'B', Windows NT drivers
1733	* for Adaptec AHA-154x may claim the adapter. The BusLogic drivers will claim
1734	* the adapter only when the byte is not '0' or 'B'.
1735	*/
1736	pBusLogic->aReplyBuffer[0] = 'A'; /* Firmware option bytes */
1737	pBusLogic->aReplyBuffer[1] = 'A'; /* Special option byte */
1738
1739	/* We report version 5.07B. This reply will provide the first two digits. */
1740	pBusLogic->aReplyBuffer[2] = '5'; /* Major version 5 */
1741	pBusLogic->aReplyBuffer[3] = '0'; /* Minor version 0 */
1742	pBusLogic->cbReplyParametersLeft = 4; /* Reply is 4 bytes long */
1743	break;
1744	}
1745	case BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_3RD_LETTER:
1746	{
1747	pBusLogic->aReplyBuffer[0] = '7';
1748	pBusLogic->cbReplyParametersLeft = 1;
1749	break;
1750	}
1751	case BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_LETTER:
1752	{
1753	pBusLogic->aReplyBuffer[0] = 'B';
1754	pBusLogic->cbReplyParametersLeft = 1;
1755	break;
1756	}
1757	case BUSLOGICCOMMAND_SET_ADAPTER_OPTIONS:
1758	/* The parameter list length is determined by the first byte of the command buffer. */
1759	if (pBusLogic->iParameter == 1)
1760	{
1761	/* First pass - set the number of following parameter bytes. */
1762	pBusLogic->cbCommandParametersLeft = pBusLogic->aCommandBuffer[0];
1763	Log(("Set HA options: %u bytes follow\n", pBusLogic->cbCommandParametersLeft));
1764	}
1765	else
1766	{
1767	/* Second pass - process received data. */
1768	Log(("Set HA options: received %u bytes\n", pBusLogic->aCommandBuffer[0]));
1769	/* We ignore the data - it only concerns the SCSI hardware protocol. */
1770	}
1771	pBusLogic->cbReplyParametersLeft = 0;
1772	break;
1773
1774	case BUSLOGICCOMMAND_EXECUTE_SCSI_COMMAND:
1775	/* The parameter list length is at least 12 bytes; the 12th byte determines
1776	* the number of additional CDB bytes that will follow.
1777	*/
1778	if (pBusLogic->iParameter == 12)
1779	{
1780	/* First pass - set the number of following CDB bytes. */
1781	pBusLogic->cbCommandParametersLeft = pBusLogic->aCommandBuffer[11];
1782	Log(("Execute SCSI cmd: %u more bytes follow\n", pBusLogic->cbCommandParametersLeft));
1783	}
1784	else
1785	{
1786	PESCMD pCmd;
1787
1788	/* Second pass - process received data. */
1789	Log(("Execute SCSI cmd: received %u bytes\n", pBusLogic->aCommandBuffer[0]));
1790
1791	pCmd = (PESCMD)pBusLogic->aCommandBuffer;
1792	Log(("Addr %08X, cbData %08X, cbCDB=%u\n", pCmd->u32PhysAddrData, pCmd->cbData, pCmd->cbCDB));
1793	}
1794	// This is currently a dummy - just fails every command.
1795	pBusLogic->cbReplyParametersLeft = 4;
1796	pBusLogic->aReplyBuffer[0] = pBusLogic->aReplyBuffer[1] = 0;
1797	pBusLogic->aReplyBuffer[2] = 0x11; /* HBA status (timeout). */
1798	pBusLogic->aReplyBuffer[3] = 0; /* Device status. */
1799	break;
1800
1801	case BUSLOGICCOMMAND_INQUIRE_HOST_ADAPTER_MODEL_NUMBER:
1802	{
1803	/* The reply length is set by the guest and is found in the first byte of the command buffer. */
1804	pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[0];
1805	memset(pBusLogic->aReplyBuffer, ' ', pBusLogic->cbReplyParametersLeft);
1806	const char aModelName[] = "958";
1807	int cCharsToTransfer = (pBusLogic->cbReplyParametersLeft <= (sizeof(aModelName) - 1))
1808	? pBusLogic->cbReplyParametersLeft
1809	: sizeof(aModelName) - 1;
1810
1811	for (int i = 0; i < cCharsToTransfer; i++)
1812	pBusLogic->aReplyBuffer[i] = aModelName[i];
1813
1814	break;
1815	}
1816	case BUSLOGICCOMMAND_INQUIRE_CONFIGURATION:
1817	{
1818	uint8_t uPciIrq = PCIDevGetInterruptLine(&pBusLogic->dev);
1819
1820	pBusLogic->cbReplyParametersLeft = sizeof(ReplyInquireConfiguration);
1821	PReplyInquireConfiguration pReply = (PReplyInquireConfiguration)pBusLogic->aReplyBuffer;
1822	memset(pReply, 0, sizeof(ReplyInquireConfiguration));
1823
1824	pReply->uHostAdapterId = 7; /* The controller has always 7 as ID. */
1825	pReply->fDmaChannel6 = 1; /* DMA channel 6 is a good default. */
1826	/* The PCI IRQ is not necessarily representable in this structure.
1827	* If that is the case, the guest likely won't function correctly,
1828	* therefore we log a warning.
1829	*/
1830	switch (uPciIrq)
1831	{
1832	case 9: pReply->fIrqChannel9 = 1; break;
1833	case 10: pReply->fIrqChannel10 = 1; break;
1834	case 11: pReply->fIrqChannel11 = 1; break;
1835	case 12: pReply->fIrqChannel12 = 1; break;
1836	case 14: pReply->fIrqChannel14 = 1; break;
1837	case 15: pReply->fIrqChannel15 = 1; break;
1838	default:
1839	LogRel(("Warning: PCI IRQ %d cannot be represented as ISA!\n", uPciIrq));
1840	break;
1841	}
1842	break;
1843	}
1844	case BUSLOGICCOMMAND_INQUIRE_EXTENDED_SETUP_INFORMATION:
1845	{
1846	/* Some Adaptec AHA-154x drivers (e.g. OS/2) execute this command and expect
1847	* it to fail. If it succeeds, the drivers refuse to load. However, some newer
1848	* Adaptec 154x models supposedly support it too??
1849	*/
1850
1851	/* The reply length is set by the guest and is found in the first byte of the command buffer. */
1852	pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[0];
1853	PReplyInquireExtendedSetupInformation pReply = (PReplyInquireExtendedSetupInformation)pBusLogic->aReplyBuffer;
1854	memset(pReply, 0, sizeof(ReplyInquireExtendedSetupInformation));
1855
1856	/** @todo should this reflect the RAM contents (AutoSCSIRam)? */
1857	pReply->uBusType = 'E'; /* EISA style */
1858	pReply->u16ScatterGatherLimit = 8192;
1859	pReply->cMailbox = pBusLogic->cMailbox;
1860	pReply->uMailboxAddressBase = (uint32_t)pBusLogic->GCPhysAddrMailboxOutgoingBase;
1861	pReply->fLevelSensitiveInterrupt = true;
1862	pReply->fHostWideSCSI = true;
1863	pReply->fHostUltraSCSI = true;
1864	memcpy(pReply->aFirmwareRevision, "07B", sizeof(pReply->aFirmwareRevision));
1865
1866	break;
1867	}
1868	case BUSLOGICCOMMAND_INQUIRE_SETUP_INFORMATION:
1869	{
1870	/* The reply length is set by the guest and is found in the first byte of the command buffer. */
1871	pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[0];
1872	PReplyInquireSetupInformation pReply = (PReplyInquireSetupInformation)pBusLogic->aReplyBuffer;
1873	memset(pReply, 0, sizeof(ReplyInquireSetupInformation));
1874	pReply->fSynchronousInitiationEnabled = true;
1875	pReply->fParityCheckingEnabled = true;
1876	pReply->cMailbox = pBusLogic->cMailbox;
1877	U32_TO_ADDR(pReply->MailboxAddress, pBusLogic->GCPhysAddrMailboxOutgoingBase);
1878	pReply->uSignature = 'B';
1879	/* The 'D' signature prevents Adaptec's OS/2 drivers from getting too
1880	* friendly with BusLogic hardware and upsetting the HBA state.
1881	*/
1882	pReply->uCharacterD = 'D'; /* BusLogic model. */
1883	pReply->uHostBusType = 'F'; /* PCI bus. */
1884	break;
1885	}
1886	case BUSLOGICCOMMAND_FETCH_HOST_ADAPTER_LOCAL_RAM:
1887	{
1888	/*
1889	* First element in the command buffer contains start offset to read from
1890	* and second one the number of bytes to read.
1891	*/
1892	uint8_t uOffset = pBusLogic->aCommandBuffer[0];
1893	pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[1];
1894
1895	pBusLogic->fUseLocalRam = true;
1896	pBusLogic->iReply = uOffset;
1897	break;
1898	}
1899	case BUSLOGICCOMMAND_INITIALIZE_MAILBOX:
1900	{
1901	PRequestInitMbx pRequest = (PRequestInitMbx)pBusLogic->aCommandBuffer;
1902
1903	pBusLogic->fMbxIs24Bit = true;
1904	pBusLogic->cMailbox = pRequest->cMailbox;
1905	pBusLogic->GCPhysAddrMailboxOutgoingBase = (RTGCPHYS)ADDR_TO_U32(pRequest->aMailboxBaseAddr);
1906	/* The area for incoming mailboxes is right after the last entry of outgoing mailboxes. */
1907	pBusLogic->GCPhysAddrMailboxIncomingBase = pBusLogic->GCPhysAddrMailboxOutgoingBase + (pBusLogic->cMailbox * sizeof(Mailbox24));
1908
1909	Log(("GCPhysAddrMailboxOutgoingBase=%RGp\n", pBusLogic->GCPhysAddrMailboxOutgoingBase));
1910	Log(("GCPhysAddrMailboxIncomingBase=%RGp\n", pBusLogic->GCPhysAddrMailboxIncomingBase));
1911	Log(("cMailboxes=%u (24-bit mode)\n", pBusLogic->cMailbox));
1912	LogRel(("Initialized 24-bit mailbox, %d entries at %08x\n", pRequest->cMailbox, ADDR_TO_U32(pRequest->aMailboxBaseAddr)));
1913
1914	pBusLogic->regStatus &= ~BL_STAT_INREQ;
1915	pBusLogic->cbReplyParametersLeft = 0;
1916	break;
1917	}
1918	case BUSLOGICCOMMAND_INITIALIZE_EXTENDED_MAILBOX:
1919	{
1920	PRequestInitializeExtendedMailbox pRequest = (PRequestInitializeExtendedMailbox)pBusLogic->aCommandBuffer;
1921
1922	pBusLogic->fMbxIs24Bit = false;
1923	pBusLogic->cMailbox = pRequest->cMailbox;
1924	pBusLogic->GCPhysAddrMailboxOutgoingBase = (RTGCPHYS)pRequest->uMailboxBaseAddress;
1925	/* The area for incoming mailboxes is right after the last entry of outgoing mailboxes. */
1926	pBusLogic->GCPhysAddrMailboxIncomingBase = (RTGCPHYS)pRequest->uMailboxBaseAddress + (pBusLogic->cMailbox * sizeof(Mailbox32));
1927
1928	Log(("GCPhysAddrMailboxOutgoingBase=%RGp\n", pBusLogic->GCPhysAddrMailboxOutgoingBase));
1929	Log(("GCPhysAddrMailboxIncomingBase=%RGp\n", pBusLogic->GCPhysAddrMailboxIncomingBase));
1930	Log(("cMailboxes=%u (32-bit mode)\n", pBusLogic->cMailbox));
1931	LogRel(("Initialized 32-bit mailbox, %d entries at %08x\n", pRequest->cMailbox, pRequest->uMailboxBaseAddress));
1932
1933	pBusLogic->regStatus &= ~BL_STAT_INREQ;
1934	pBusLogic->cbReplyParametersLeft = 0;
1935	break;
1936	}
1937	case BUSLOGICCOMMAND_ENABLE_STRICT_ROUND_ROBIN_MODE:
1938	{
1939	if (pBusLogic->aCommandBuffer[0] == 0)
1940	pBusLogic->fStrictRoundRobinMode = false;
1941	else if (pBusLogic->aCommandBuffer[0] == 1)
1942	pBusLogic->fStrictRoundRobinMode = true;
1943	else
1944	AssertMsgFailed(("Invalid round robin mode %d\n", pBusLogic->aCommandBuffer[0]));
1945
1946	pBusLogic->cbReplyParametersLeft = 0;
1947	break;
1948	}
1949	case BUSLOGICCOMMAND_SET_CCB_FORMAT:
1950	{
1951	if (pBusLogic->aCommandBuffer[0] == 0)
1952	pBusLogic->fExtendedLunCCBFormat = false;
1953	else if (pBusLogic->aCommandBuffer[0] == 1)
1954	pBusLogic->fExtendedLunCCBFormat = true;
1955	else
1956	AssertMsgFailed(("Invalid CCB format %d\n", pBusLogic->aCommandBuffer[0]));
1957
1958	pBusLogic->cbReplyParametersLeft = 0;
1959	break;
1960	}
1961	case BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_0_TO_7:
1962	/* This is supposed to send TEST UNIT READY to each target/LUN.
1963	* We cheat and skip that, since we already know what's attached
1964	*/
1965	memset(pBusLogic->aReplyBuffer, 0, 8);
1966	for (int i = 0; i < 8; ++i)
1967	{
1968	if (pBusLogic->aDeviceStates[i].fPresent)
1969	pBusLogic->aReplyBuffer[i] = 1;
1970	}
1971	pBusLogic->aReplyBuffer[7] = 0; /* HA hardcoded at ID 7. */
1972	pBusLogic->cbReplyParametersLeft = 8;
1973	break;
1974	case BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_8_TO_15:
1975	/* See note about cheating above. */
1976	memset(pBusLogic->aReplyBuffer, 0, 8);
1977	for (int i = 0; i < 8; ++i)
1978	{
1979	if (pBusLogic->aDeviceStates[i + 8].fPresent)
1980	pBusLogic->aReplyBuffer[i] = 1;
1981	}
1982	pBusLogic->cbReplyParametersLeft = 8;
1983	break;
1984	case BUSLOGICCOMMAND_INQUIRE_TARGET_DEVICES:
1985	{
1986	/* Each bit which is set in the 16bit wide variable means a present device. */
1987	uint16_t u16TargetsPresentMask = 0;
1988
1989	for (uint8_t i = 0; i < RT_ELEMENTS(pBusLogic->aDeviceStates); i++)
1990	{
1991	if (pBusLogic->aDeviceStates[i].fPresent)
1992	u16TargetsPresentMask \|= (1 << i);
1993	}
1994	pBusLogic->aReplyBuffer[0] = (uint8_t)u16TargetsPresentMask;
1995	pBusLogic->aReplyBuffer[1] = (uint8_t)(u16TargetsPresentMask >> 8);
1996	pBusLogic->cbReplyParametersLeft = 2;
1997	break;
1998	}
1999	case BUSLOGICCOMMAND_INQUIRE_SYNCHRONOUS_PERIOD:
2000	{
2001	pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[0];
2002
2003	for (uint8_t i = 0; i < pBusLogic->cbReplyParametersLeft; i++)
2004	pBusLogic->aReplyBuffer[i] = 0; /** @todo Figure if we need something other here. It's not needed for the linux driver */
2005
2006	break;
2007	}
2008	case BUSLOGICCOMMAND_DISABLE_HOST_ADAPTER_INTERRUPT:
2009	{
2010	if (pBusLogic->aCommandBuffer[0] == 0)
2011	pBusLogic->fIRQEnabled = false;
2012	else
2013	pBusLogic->fIRQEnabled = true;
2014	/* No interrupt signaled regardless of enable/disable. */
2015	fSuppressIrq = true;
2016	break;
2017	}
2018	case BUSLOGICCOMMAND_ECHO_COMMAND_DATA:
2019	{
2020	pBusLogic->aReplyBuffer[0] = pBusLogic->aCommandBuffer[0];
2021	pBusLogic->cbReplyParametersLeft = 1;
2022	break;
2023	}
2024	case BUSLOGICCOMMAND_SET_PREEMPT_TIME_ON_BUS:
2025	{
2026	pBusLogic->cbReplyParametersLeft = 0;
2027	pBusLogic->LocalRam.structured.autoSCSIData.uBusOnDelay = pBusLogic->aCommandBuffer[0];
2028	Log(("Bus-on time: %d\n", pBusLogic->aCommandBuffer[0]));
2029	break;
2030	}
2031	case BUSLOGICCOMMAND_SET_TIME_OFF_BUS:
2032	{
2033	pBusLogic->cbReplyParametersLeft = 0;
2034	pBusLogic->LocalRam.structured.autoSCSIData.uBusOffDelay = pBusLogic->aCommandBuffer[0];
2035	Log(("Bus-off time: %d\n", pBusLogic->aCommandBuffer[0]));
2036	break;
2037	}
2038	case BUSLOGICCOMMAND_SET_BUS_TRANSFER_RATE:
2039	{
2040	pBusLogic->cbReplyParametersLeft = 0;
2041	pBusLogic->LocalRam.structured.autoSCSIData.uDMATransferRate = pBusLogic->aCommandBuffer[0];
2042	Log(("Bus transfer rate: %02X\n", pBusLogic->aCommandBuffer[0]));
2043	break;
2044	}
2045	case BUSLOGICCOMMAND_WRITE_BUSMASTER_CHIP_FIFO:
2046	{
2047	RTGCPHYS GCPhysFifoBuf;
2048	Addr24 addr;
2049
2050	pBusLogic->cbReplyParametersLeft = 0;
2051	addr.hi = pBusLogic->aCommandBuffer[0];
2052	addr.mid = pBusLogic->aCommandBuffer[1];
2053	addr.lo = pBusLogic->aCommandBuffer[2];
2054	GCPhysFifoBuf = (RTGCPHYS)ADDR_TO_U32(addr);
2055	Log(("Write busmaster FIFO at: %04X\n", ADDR_TO_U32(addr)));
2056	PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCPhysFifoBuf,
2057	&pBusLogic->LocalRam.u8View[64], 64);
2058	break;
2059	}
2060	case BUSLOGICCOMMAND_READ_BUSMASTER_CHIP_FIFO:
2061	{
2062	RTGCPHYS GCPhysFifoBuf;
2063	Addr24 addr;
2064
2065	pBusLogic->cbReplyParametersLeft = 0;
2066	addr.hi = pBusLogic->aCommandBuffer[0];
2067	addr.mid = pBusLogic->aCommandBuffer[1];
2068	addr.lo = pBusLogic->aCommandBuffer[2];
2069	GCPhysFifoBuf = (RTGCPHYS)ADDR_TO_U32(addr);
2070	Log(("Read busmaster FIFO at: %04X\n", ADDR_TO_U32(addr)));
2071	PDMDevHlpPCIPhysWrite(pBusLogic->CTX_SUFF(pDevIns), GCPhysFifoBuf,
2072	&pBusLogic->LocalRam.u8View[64], 64);
2073	break;
2074	}
2075	default:
2076	AssertMsgFailed(("Invalid command %#x\n", pBusLogic->uOperationCode));
2077	case BUSLOGICCOMMAND_EXT_BIOS_INFO:
2078	case BUSLOGICCOMMAND_UNLOCK_MAILBOX:
2079	/* Commands valid for Adaptec 154xC which we don't handle since
2080	* we pretend being 154xB compatible. Just mark the command as invalid.
2081	*/
2082	Log(("Command %#x not valid for this adapter\n", pBusLogic->uOperationCode));
2083	pBusLogic->cbReplyParametersLeft = 0;
2084	pBusLogic->regStatus \|= BL_STAT_CMDINV;
2085	break;
2086	case BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND: /* Should be handled already. */
2087	AssertMsgFailed(("Invalid mailbox execute state!\n"));
2088	}
2089
2090	Log(("uOperationCode=%#x, cbReplyParametersLeft=%d\n", pBusLogic->uOperationCode, pBusLogic->cbReplyParametersLeft));
2091
2092	/* Set the data in ready bit in the status register in case the command has a reply. */
2093	if (pBusLogic->cbReplyParametersLeft)
2094	pBusLogic->regStatus \|= BL_STAT_DIRRDY;
2095	else if (!pBusLogic->cbCommandParametersLeft)
2096	buslogicCommandComplete(pBusLogic, fSuppressIrq);
2097
2098	return rc;
2099	}
2100
2101	/**
2102	* Read a register from the BusLogic adapter.
2103	*
2104	* @returns VBox status code.
2105	* @param pBusLogic Pointer to the BusLogic instance data.
2106	* @param iRegister The index of the register to read.
2107	* @param pu32 Where to store the register content.
2108	*/
2109	static int buslogicRegisterRead(PBUSLOGIC pBusLogic, unsigned iRegister, uint32_t *pu32)
2110	{
2111	int rc = VINF_SUCCESS;
2112
2113	switch (iRegister)
2114	{
2115	case BUSLOGIC_REGISTER_STATUS:
2116	{
2117	*pu32 = pBusLogic->regStatus;
2118
2119	/* If the diagnostic active bit is set, we are in a guest-initiated
2120	* hard reset. If the guest reads the status register and waits for
2121	* the host adapter ready bit to be set, we terminate the reset right
2122	* away. However, guests may also expect the reset condition to clear
2123	* automatically after a period of time, in which case we can't show
2124	* the DIAG bit at all.
2125	*/
2126	if (pBusLogic->regStatus & BL_STAT_DACT)
2127	{
2128	uint64_t u64AccessTime = PDMDevHlpTMTimeVirtGetNano(pBusLogic->CTX_SUFF(pDevIns));
2129
2130	pBusLogic->regStatus &= ~BL_STAT_DACT;
2131	pBusLogic->regStatus \|= BL_STAT_HARDY;
2132
2133	if (u64AccessTime - pBusLogic->u64ResetTime > BUSLOGIC_RESET_DURATION_NS)
2134	{
2135	/* If reset already expired, let the guest see that right away. */
2136	*pu32 = pBusLogic->regStatus;
2137	pBusLogic->u64ResetTime = 0;
2138	}
2139	}
2140	break;
2141	}
2142	case BUSLOGIC_REGISTER_DATAIN:
2143	{
2144	if (pBusLogic->fUseLocalRam)
2145	*pu32 = pBusLogic->LocalRam.u8View[pBusLogic->iReply];
2146	else
2147	*pu32 = pBusLogic->aReplyBuffer[pBusLogic->iReply];
2148
2149	/* Careful about underflow - guest can read data register even if
2150	* no data is available.
2151	*/
2152	if (pBusLogic->cbReplyParametersLeft)
2153	{
2154	pBusLogic->iReply++;
2155	pBusLogic->cbReplyParametersLeft--;
2156	if (!pBusLogic->cbReplyParametersLeft)
2157	{
2158	/*
2159	* Reply finished, set command complete bit, unset data-in ready bit and
2160	* interrupt the guest if enabled.
2161	*/
2162	buslogicCommandComplete(pBusLogic, false);
2163	}
2164	}
2165	LogFlowFunc(("data=%02x, iReply=%d, cbReplyParametersLeft=%u\n", *pu32,
2166	pBusLogic->iReply, pBusLogic->cbReplyParametersLeft));
2167	break;
2168	}
2169	case BUSLOGIC_REGISTER_INTERRUPT:
2170	{
2171	*pu32 = pBusLogic->regInterrupt;
2172	break;
2173	}
2174	case BUSLOGIC_REGISTER_GEOMETRY:
2175	{
2176	*pu32 = pBusLogic->regGeometry;
2177	break;
2178	}
2179	default:
2180	*pu32 = UINT32_C(0xffffffff);
2181	}
2182
2183	Log2(("%s: pu32=%p:{%.*Rhxs} iRegister=%d rc=%Rrc\n",
2184	__FUNCTION__, pu32, 1, pu32, iRegister, rc));
2185
2186	return rc;
2187	}
2188
2189	/**
2190	* Write a value to a register.
2191	*
2192	* @returns VBox status code.
2193	* @param pBusLogic Pointer to the BusLogic instance data.
2194	* @param iRegister The index of the register to read.
2195	* @param uVal The value to write.
2196	*/
2197	static int buslogicRegisterWrite(PBUSLOGIC pBusLogic, unsigned iRegister, uint8_t uVal)
2198	{
2199	int rc = VINF_SUCCESS;
2200
2201	switch (iRegister)
2202	{
2203	case BUSLOGIC_REGISTER_CONTROL:
2204	{
2205	if ((uVal & BL_CTRL_RHARD) \|\| (uVal & BL_CTRL_RSOFT))
2206	{
2207	#ifdef IN_RING3
2208	bool fHardReset = !!(uVal & BL_CTRL_RHARD);
2209
2210	LogRel(("BusLogic: %s reset\n", fHardReset ? "hard" : "soft"));
2211	buslogicR3InitiateReset(pBusLogic, fHardReset);
2212	#else
2213	rc = VINF_IOM_R3_IOPORT_WRITE;
2214	#endif
2215	break;
2216	}
2217
2218	rc = PDMCritSectEnter(&pBusLogic->CritSectIntr, VINF_IOM_R3_IOPORT_WRITE);
2219	if (rc != VINF_SUCCESS)
2220	return rc;
2221
2222	#ifdef LOG_ENABLED
2223	uint32_t cMailboxesReady = ASMAtomicXchgU32(&pBusLogic->cInMailboxesReady, 0);
2224	Log(("%u incoming mailboxes were ready when this interrupt was cleared\n", cMailboxesReady));
2225	#endif
2226
2227	if (uVal & BL_CTRL_RINT)
2228	buslogicClearInterrupt(pBusLogic);
2229
2230	PDMCritSectLeave(&pBusLogic->CritSectIntr);
2231
2232	break;
2233	}
2234	case BUSLOGIC_REGISTER_COMMAND:
2235	{
2236	/* Fast path for mailbox execution command. */
2237	if ((uVal == BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND) && (pBusLogic->uOperationCode == 0xff))
2238	{
2239	/* If there are no mailboxes configured, don't even try to do anything. */
2240	if (pBusLogic->cMailbox) {
2241	ASMAtomicIncU32(&pBusLogic->cMailboxesReady);
2242	if (!ASMAtomicXchgBool(&pBusLogic->fNotificationSend, true))
2243	{
2244	/* Send new notification to the queue. */
2245	PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pBusLogic->CTX_SUFF(pNotifierQueue));
2246	AssertMsg(pItem, ("Allocating item for queue failed\n"));
2247	PDMQueueInsert(pBusLogic->CTX_SUFF(pNotifierQueue), (PPDMQUEUEITEMCORE)pItem);
2248	}
2249	}
2250
2251	return rc;
2252	}
2253
2254	/*
2255	* Check if we are already fetch command parameters from the guest.
2256	* If not we initialize executing a new command.
2257	*/
2258	if (pBusLogic->uOperationCode == 0xff)
2259	{
2260	pBusLogic->uOperationCode = uVal;
2261	pBusLogic->iParameter = 0;
2262
2263	/* Mark host adapter as busy and clear the invalid status bit. */
2264	pBusLogic->regStatus &= ~(BL_STAT_HARDY \| BL_STAT_CMDINV);
2265
2266	/* Get the number of bytes for parameters from the command code. */
2267	switch (pBusLogic->uOperationCode)
2268	{
2269	case BUSLOGICCOMMAND_TEST_CMDC_INTERRUPT:
2270	case BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_LETTER:
2271	case BUSLOGICCOMMAND_INQUIRE_BOARD_ID:
2272	case BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_3RD_LETTER:
2273	case BUSLOGICCOMMAND_INQUIRE_PCI_HOST_ADAPTER_INFORMATION:
2274	case BUSLOGICCOMMAND_INQUIRE_CONFIGURATION:
2275	case BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_0_TO_7:
2276	case BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_8_TO_15:
2277	case BUSLOGICCOMMAND_INQUIRE_TARGET_DEVICES:
2278	pBusLogic->cbCommandParametersLeft = 0;
2279	break;
2280	case BUSLOGICCOMMAND_MODIFY_IO_ADDRESS:
2281	case BUSLOGICCOMMAND_INQUIRE_EXTENDED_SETUP_INFORMATION:
2282	case BUSLOGICCOMMAND_INQUIRE_SETUP_INFORMATION:
2283	case BUSLOGICCOMMAND_INQUIRE_HOST_ADAPTER_MODEL_NUMBER:
2284	case BUSLOGICCOMMAND_ENABLE_STRICT_ROUND_ROBIN_MODE:
2285	case BUSLOGICCOMMAND_SET_CCB_FORMAT:
2286	case BUSLOGICCOMMAND_INQUIRE_SYNCHRONOUS_PERIOD:
2287	case BUSLOGICCOMMAND_DISABLE_HOST_ADAPTER_INTERRUPT:
2288	case BUSLOGICCOMMAND_ECHO_COMMAND_DATA:
2289	case BUSLOGICCOMMAND_SET_PREEMPT_TIME_ON_BUS:
2290	case BUSLOGICCOMMAND_SET_TIME_OFF_BUS:
2291	case BUSLOGICCOMMAND_SET_BUS_TRANSFER_RATE:
2292	pBusLogic->cbCommandParametersLeft = 1;
2293	break;
2294	case BUSLOGICCOMMAND_FETCH_HOST_ADAPTER_LOCAL_RAM:
2295	pBusLogic->cbCommandParametersLeft = 2;
2296	break;
2297	case BUSLOGICCOMMAND_READ_BUSMASTER_CHIP_FIFO:
2298	case BUSLOGICCOMMAND_WRITE_BUSMASTER_CHIP_FIFO:
2299	pBusLogic->cbCommandParametersLeft = 3;
2300	break;
2301	case BUSLOGICCOMMAND_INITIALIZE_MAILBOX:
2302	pBusLogic->cbCommandParametersLeft = sizeof(RequestInitMbx);
2303	break;
2304	case BUSLOGICCOMMAND_INITIALIZE_EXTENDED_MAILBOX:
2305	pBusLogic->cbCommandParametersLeft = sizeof(RequestInitializeExtendedMailbox);
2306	break;
2307	case BUSLOGICCOMMAND_SET_ADAPTER_OPTIONS:
2308	/* There must be at least one byte following this command. */
2309	pBusLogic->cbCommandParametersLeft = 1;
2310	break;
2311	case BUSLOGICCOMMAND_EXECUTE_SCSI_COMMAND:
2312	/* 12 bytes + variable-length CDB. */
2313	pBusLogic->cbCommandParametersLeft = 12;
2314	break;
2315	case BUSLOGICCOMMAND_EXT_BIOS_INFO:
2316	case BUSLOGICCOMMAND_UNLOCK_MAILBOX:
2317	/* Invalid commands. */
2318	pBusLogic->cbCommandParametersLeft = 0;
2319	break;
2320	case BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND: /* Should not come here anymore. */
2321	default:
2322	AssertMsgFailed(("Invalid operation code %#x\n", uVal));
2323	}
2324	}
2325	else
2326	{
2327	#ifndef IN_RING3
2328	/* This command must be executed in R3 as it rehooks the ISA I/O port. */
2329	if (pBusLogic->uOperationCode == BUSLOGICCOMMAND_MODIFY_IO_ADDRESS)
2330	{
2331	rc = VINF_IOM_R3_IOPORT_WRITE;
2332	break;
2333	}
2334	#endif
2335	/*
2336	* The real adapter would set the Command register busy bit in the status register.
2337	* The guest has to wait until it is unset.
2338	* We don't need to do it because the guest does not continue execution while we are in this
2339	* function.
2340	*/
2341	pBusLogic->aCommandBuffer[pBusLogic->iParameter] = uVal;
2342	pBusLogic->iParameter++;
2343	pBusLogic->cbCommandParametersLeft--;
2344	}
2345
2346	/* Start execution of command if there are no parameters left. */
2347	if (!pBusLogic->cbCommandParametersLeft)
2348	{
2349	rc = buslogicProcessCommand(pBusLogic);
2350	AssertMsgRC(rc, ("Processing command failed rc=%Rrc\n", rc));
2351	}
2352	break;
2353	}
2354
2355	/* On BusLogic adapters, the interrupt and geometry registers are R/W.
2356	* That is different from Adaptec 154x where those are read only.
2357	*/
2358	case BUSLOGIC_REGISTER_INTERRUPT:
2359	pBusLogic->regInterrupt = uVal;
2360	break;
2361
2362	case BUSLOGIC_REGISTER_GEOMETRY:
2363	pBusLogic->regGeometry = uVal;
2364	break;
2365
2366	default:
2367	AssertMsgFailed(("Register not available\n"));
2368	rc = VERR_IOM_IOPORT_UNUSED;
2369	}
2370
2371	return rc;
2372	}
2373
2374	/**
2375	* Memory mapped I/O Handler for read operations.
2376	*
2377	* @returns VBox status code.
2378	*
2379	* @param pDevIns The device instance.
2380	* @param pvUser User argument.
2381	* @param GCPhysAddr Physical address (in GC) where the read starts.
2382	* @param pv Where to store the result.
2383	* @param cb Number of bytes read.
2384	*/
2385	PDMBOTHCBDECL(int) buslogicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2386	{
2387	/* the linux driver does not make use of the MMIO area. */
2388	AssertMsgFailed(("MMIO Read\n"));
2389	return VINF_SUCCESS;
2390	}
2391
2392	/**
2393	* Memory mapped I/O Handler for write operations.
2394	*
2395	* @returns VBox status code.
2396	*
2397	* @param pDevIns The device instance.
2398	* @param pvUser User argument.
2399	* @param GCPhysAddr Physical address (in GC) where the read starts.
2400	* @param pv Where to fetch the result.
2401	* @param cb Number of bytes to write.
2402	*/
2403	PDMBOTHCBDECL(int) buslogicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
2404	{
2405	/* the linux driver does not make use of the MMIO area. */
2406	AssertMsgFailed(("MMIO Write\n"));
2407	return VINF_SUCCESS;
2408	}
2409
2410	/**
2411	* Port I/O Handler for IN operations.
2412	*
2413	* @returns VBox status code.
2414	*
2415	* @param pDevIns The device instance.
2416	* @param pvUser User argument.
2417	* @param uPort Port number used for the IN operation.
2418	* @param pu32 Where to store the result.
2419	* @param cb Number of bytes read.
2420	*/
2421	PDMBOTHCBDECL(int) buslogicIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
2422	{
2423	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2424	unsigned iRegister = Port % 4;
2425
2426	Assert(cb == 1);
2427
2428	return buslogicRegisterRead(pBusLogic, iRegister, pu32);
2429	}
2430
2431	/**
2432	* Port I/O Handler for OUT operations.
2433	*
2434	* @returns VBox status code.
2435	*
2436	* @param pDevIns The device instance.
2437	* @param pvUser User argument.
2438	* @param uPort Port number used for the IN operation.
2439	* @param u32 The value to output.
2440	* @param cb The value size in bytes.
2441	*/
2442	PDMBOTHCBDECL(int) buslogicIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2443	{
2444	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2445	int rc = VINF_SUCCESS;
2446	unsigned iRegister = Port % 4;
2447	uint8_t uVal = (uint8_t)u32;
2448
2449	Assert(cb == 1);
2450
2451	rc = buslogicRegisterWrite(pBusLogic, iRegister, (uint8_t)uVal);
2452
2453	Log2(("#%d %s: pvUser=%#p cb=%d u32=%#x Port=%#x rc=%Rrc\n",
2454	pDevIns->iInstance, __FUNCTION__, pvUser, cb, u32, Port, rc));
2455
2456	return rc;
2457	}
2458
2459	#ifdef IN_RING3
2460
2461	static int buslogicR3PrepareBIOSSCSIRequest(PBUSLOGIC pBusLogic)
2462	{
2463	int rc;
2464	PBUSLOGICTASKSTATE pTaskState;
2465	uint32_t uTargetDevice;
2466
2467	rc = RTMemCacheAllocEx(pBusLogic->hTaskCache, (void **)&pTaskState);
2468	AssertMsgRCReturn(rc, ("Getting task from cache failed rc=%Rrc\n", rc), rc);
2469
2470	pTaskState->fBIOS = true;
2471
2472	rc = vboxscsiSetupRequest(&pBusLogic->VBoxSCSI, &pTaskState->PDMScsiRequest, &uTargetDevice);
2473	AssertMsgRCReturn(rc, ("Setting up SCSI request failed rc=%Rrc\n", rc), rc);
2474
2475	pTaskState->PDMScsiRequest.pvUser = pTaskState;
2476
2477	pTaskState->CTX_SUFF(pTargetDevice) = &pBusLogic->aDeviceStates[uTargetDevice];
2478
2479	if (!pTaskState->CTX_SUFF(pTargetDevice)->fPresent)
2480	{
2481	/* Device is not present. */
2482	AssertMsg(pTaskState->PDMScsiRequest.pbCDB[0] == SCSI_INQUIRY,
2483	("Device is not present but command is not inquiry\n"));
2484
2485	SCSIINQUIRYDATA ScsiInquiryData;
2486
2487	memset(&ScsiInquiryData, 0, sizeof(SCSIINQUIRYDATA));
2488	ScsiInquiryData.u5PeripheralDeviceType = SCSI_INQUIRY_DATA_PERIPHERAL_DEVICE_TYPE_UNKNOWN;
2489	ScsiInquiryData.u3PeripheralQualifier = SCSI_INQUIRY_DATA_PERIPHERAL_QUALIFIER_NOT_CONNECTED_NOT_SUPPORTED;
2490
2491	memcpy(pBusLogic->VBoxSCSI.pbBuf, &ScsiInquiryData, 5);
2492
2493	rc = vboxscsiRequestFinished(&pBusLogic->VBoxSCSI, &pTaskState->PDMScsiRequest, SCSI_STATUS_OK);
2494	AssertMsgRCReturn(rc, ("Finishing BIOS SCSI request failed rc=%Rrc\n", rc), rc);
2495
2496	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
2497	}
2498	else
2499	{
2500	LogFlowFunc(("before increment %u\n", pTaskState->CTX_SUFF(pTargetDevice)->cOutstandingRequests));
2501	ASMAtomicIncU32(&pTaskState->CTX_SUFF(pTargetDevice)->cOutstandingRequests);
2502	LogFlowFunc(("after increment %u\n", pTaskState->CTX_SUFF(pTargetDevice)->cOutstandingRequests));
2503
2504	rc = pTaskState->CTX_SUFF(pTargetDevice)->pDrvSCSIConnector->pfnSCSIRequestSend(pTaskState->CTX_SUFF(pTargetDevice)->pDrvSCSIConnector,
2505	&pTaskState->PDMScsiRequest);
2506	AssertMsgRC(rc, ("Sending request to SCSI layer failed rc=%Rrc\n", rc));
2507	}
2508
2509	return rc;
2510	}
2511
2512
2513	/**
2514	* Port I/O Handler for IN operations - BIOS port.
2515	*
2516	* @returns VBox status code.
2517	*
2518	* @param pDevIns The device instance.
2519	* @param pvUser User argument.
2520	* @param uPort Port number used for the IN operation.
2521	* @param pu32 Where to store the result.
2522	* @param cb Number of bytes read.
2523	*/
2524	static DECLCALLBACK(int) buslogicR3BiosIoPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
2525	{
2526	int rc;
2527	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2528
2529	Assert(cb == 1);
2530
2531	rc = vboxscsiReadRegister(&pBusLogic->VBoxSCSI, (Port - BUSLOGIC_BIOS_IO_PORT), pu32);
2532
2533	//Log2(("%s: pu32=%p:{%.*Rhxs} iRegister=%d rc=%Rrc\n",
2534	// __FUNCTION__, pu32, 1, pu32, (Port - BUSLOGIC_BIOS_IO_PORT), rc));
2535
2536	return rc;
2537	}
2538
2539	/**
2540	* Port I/O Handler for OUT operations - BIOS port.
2541	*
2542	* @returns VBox status code.
2543	*
2544	* @param pDevIns The device instance.
2545	* @param pvUser User argument.
2546	* @param uPort Port number used for the IN operation.
2547	* @param u32 The value to output.
2548	* @param cb The value size in bytes.
2549	*/
2550	static DECLCALLBACK(int) buslogicR3BiosIoPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2551	{
2552	int rc;
2553	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2554
2555	Log2(("#%d %s: pvUser=%#p cb=%d u32=%#x Port=%#x\n",
2556	pDevIns->iInstance, __FUNCTION__, pvUser, cb, u32, Port));
2557
2558	Assert(cb == 1);
2559
2560	rc = vboxscsiWriteRegister(&pBusLogic->VBoxSCSI, (Port - BUSLOGIC_BIOS_IO_PORT), (uint8_t)u32);
2561	if (rc == VERR_MORE_DATA)
2562	{
2563	rc = buslogicR3PrepareBIOSSCSIRequest(pBusLogic);
2564	AssertRC(rc);
2565	}
2566	else if (RT_FAILURE(rc))
2567	AssertMsgFailed(("Writing BIOS register failed %Rrc\n", rc));
2568
2569	return VINF_SUCCESS;
2570	}
2571
2572	/**
2573	* Port I/O Handler for primary port range OUT string operations.
2574	* @see FNIOMIOPORTOUTSTRING for details.
2575	*/
2576	static DECLCALLBACK(int) buslogicR3BiosIoPortWriteStr(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, RTGCPTR pGCPtrSrc,
2577	PRTGCUINTREG pcTransfer, unsigned cb)
2578	{
2579	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2580	int rc;
2581
2582	Log2(("#%d %s: pvUser=%#p cb=%d Port=%#x\n",
2583	pDevIns->iInstance, __FUNCTION__, pvUser, cb, Port));
2584
2585	rc = vboxscsiWriteString(pDevIns, &pBusLogic->VBoxSCSI, (Port - BUSLOGIC_BIOS_IO_PORT),
2586	pGCPtrSrc, pcTransfer, cb);
2587	if (rc == VERR_MORE_DATA)
2588	{
2589	rc = buslogicR3PrepareBIOSSCSIRequest(pBusLogic);
2590	AssertRC(rc);
2591	}
2592	else if (RT_FAILURE(rc))
2593	AssertMsgFailed(("Writing BIOS register failed %Rrc\n", rc));
2594
2595	return rc;
2596	}
2597
2598	/**
2599	* Port I/O Handler for primary port range IN string operations.
2600	* @see FNIOMIOPORTINSTRING for details.
2601	*/
2602	static DECLCALLBACK(int) buslogicR3BiosIoPortReadStr(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, RTGCPTR pGCPtrDst,
2603	PRTGCUINTREG pcTransfer, unsigned cb)
2604	{
2605	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2606
2607	LogFlowFunc(("#%d %s: pvUser=%#p cb=%d Port=%#x\n",
2608	pDevIns->iInstance, __FUNCTION__, pvUser, cb, Port));
2609
2610	return vboxscsiReadString(pDevIns, &pBusLogic->VBoxSCSI, (Port - BUSLOGIC_BIOS_IO_PORT),
2611	pGCPtrDst, pcTransfer, cb);
2612	}
2613
2614	/**
2615	* Update the ISA I/O range.
2616	*
2617	* @returns nothing.
2618	* @param pBusLogic Pointer to the BusLogic device instance.
2619	* @param uBaseCode Encoded ISA I/O base; only low 3 bits are used.
2620	*/
2621	static int buslogicR3RegisterISARange(PBUSLOGIC pBusLogic, uint8_t uBaseCode)
2622	{
2623	uint8_t uCode = uBaseCode & MAX_ISA_BASE;
2624	uint16_t uNewBase = g_aISABases[uCode];
2625	int rc = VINF_SUCCESS;
2626
2627	LogFlowFunc(("ISA I/O code %02X, new base %X\n", uBaseCode, uNewBase));
2628
2629	/* Check if the same port range is already registered. */
2630	if (uNewBase != pBusLogic->IOISABase)
2631	{
2632	/* Unregister the old range, if any. */
2633	if (pBusLogic->IOISABase)
2634	rc = PDMDevHlpIOPortDeregister(pBusLogic->CTX_SUFF(pDevIns), pBusLogic->IOISABase, 4);
2635
2636	if (RT_SUCCESS(rc))
2637	{
2638	pBusLogic->IOISABase = 0; /* First mark as unregistered. */
2639	pBusLogic->uISABaseCode = ISA_BASE_DISABLED;
2640
2641	if (uNewBase)
2642	{
2643	/* Register the new range if requested. */
2644	rc = PDMDevHlpIOPortRegister(pBusLogic->CTX_SUFF(pDevIns), uNewBase, 4, NULL,
2645	buslogicIOPortWrite, buslogicIOPortRead,
2646	NULL, NULL,
2647	"BusLogic ISA");
2648	if (RT_SUCCESS(rc))
2649	{
2650	pBusLogic->IOISABase = uNewBase;
2651	pBusLogic->uISABaseCode = uCode;
2652	}
2653	}
2654	}
2655	if (RT_SUCCESS(rc))
2656	{
2657	if (uNewBase)
2658	{
2659	Log(("ISA I/O base: %x\n", uNewBase));
2660	LogRel(("BusLogic: ISA I/O base: %x\n", uNewBase));
2661	}
2662	else
2663	{
2664	Log(("Disabling ISA I/O ports.\n"));
2665	LogRel(("BusLogic: ISA I/O disabled\n"));
2666	}
2667	}
2668
2669	}
2670	return rc;
2671	}
2672
2673	static void buslogicR3WarningDiskFull(PPDMDEVINS pDevIns)
2674	{
2675	int rc;
2676	LogRel(("BusLogic#%d: Host disk full\n", pDevIns->iInstance));
2677	rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND \| VMSETRTERR_FLAGS_NO_WAIT, "DevBusLogic_DISKFULL",
2678	N_("Host system reported disk full. VM execution is suspended. You can resume after freeing some space"));
2679	AssertRC(rc);
2680	}
2681
2682	static void buslogicR3WarningFileTooBig(PPDMDEVINS pDevIns)
2683	{
2684	int rc;
2685	LogRel(("BusLogic#%d: File too big\n", pDevIns->iInstance));
2686	rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND \| VMSETRTERR_FLAGS_NO_WAIT, "DevBusLogic_FILETOOBIG",
2687	N_("Host system reported that the file size limit of the host file system has been exceeded. VM execution is suspended. You need to move your virtual hard disk to a filesystem which allows bigger files"));
2688	AssertRC(rc);
2689	}
2690
2691	static void buslogicR3WarningISCSI(PPDMDEVINS pDevIns)
2692	{
2693	int rc;
2694	LogRel(("BusLogic#%d: iSCSI target unavailable\n", pDevIns->iInstance));
2695	rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND \| VMSETRTERR_FLAGS_NO_WAIT, "DevBusLogic_ISCSIDOWN",
2696	N_("The iSCSI target has stopped responding. VM execution is suspended. You can resume when it is available again"));
2697	AssertRC(rc);
2698	}
2699
2700	static void buslogicR3WarningUnknown(PPDMDEVINS pDevIns, int rc)
2701	{
2702	int rc2;
2703	LogRel(("BusLogic#%d: Unknown but recoverable error has occurred (rc=%Rrc)\n", pDevIns->iInstance, rc));
2704	rc2 = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND \| VMSETRTERR_FLAGS_NO_WAIT, "DevBusLogic_UNKNOWN",
2705	N_("An unknown but recoverable I/O error has occurred (rc=%Rrc). VM execution is suspended. You can resume when the error is fixed"), rc);
2706	AssertRC(rc2);
2707	}
2708
2709	static void buslogicR3RedoSetWarning(PBUSLOGIC pThis, int rc)
2710	{
2711	if (rc == VERR_DISK_FULL)
2712	buslogicR3WarningDiskFull(pThis->CTX_SUFF(pDevIns));
2713	else if (rc == VERR_FILE_TOO_BIG)
2714	buslogicR3WarningFileTooBig(pThis->CTX_SUFF(pDevIns));
2715	else if (rc == VERR_BROKEN_PIPE \|\| rc == VERR_NET_CONNECTION_REFUSED)
2716	{
2717	/* iSCSI connection abort (first error) or failure to reestablish
2718	* connection (second error). Pause VM. On resume we'll retry. */
2719	buslogicR3WarningISCSI(pThis->CTX_SUFF(pDevIns));
2720	}
2721	else
2722	buslogicR3WarningUnknown(pThis->CTX_SUFF(pDevIns), rc);
2723	}
2724
2725
2726	static DECLCALLBACK(int) buslogicR3MmioMap(PPCIDEVICE pPciDev, /unsigned/ int iRegion,
2727	RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
2728	{
2729	PPDMDEVINS pDevIns = pPciDev->pDevIns;
2730	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
2731	int rc = VINF_SUCCESS;
2732
2733	Log2(("%s: registering MMIO area at GCPhysAddr=%RGp cb=%u\n", __FUNCTION__, GCPhysAddress, cb));
2734
2735	Assert(cb >= 32);
2736
2737	if (enmType == PCI_ADDRESS_SPACE_MEM)
2738	{
2739	/* We use the assigned size here, because we currently only support page aligned MMIO ranges. */
2740	rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /pvUser/,
2741	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
2742	buslogicMMIOWrite, buslogicMMIORead, "BusLogic MMIO");
2743	if (RT_FAILURE(rc))
2744	return rc;
2745
2746	if (pThis->fR0Enabled)
2747	{
2748	rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /pvUser/,
2749	"buslogicMMIOWrite", "buslogicMMIORead");
2750	if (RT_FAILURE(rc))
2751	return rc;
2752	}
2753
2754	if (pThis->fGCEnabled)
2755	{
2756	rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /pvUser/,
2757	"buslogicMMIOWrite", "buslogicMMIORead");
2758	if (RT_FAILURE(rc))
2759	return rc;
2760	}
2761
2762	pThis->MMIOBase = GCPhysAddress;
2763	}
2764	else if (enmType == PCI_ADDRESS_SPACE_IO)
2765	{
2766	rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, 32,
2767	NULL, buslogicIOPortWrite, buslogicIOPortRead, NULL, NULL, "BusLogic PCI");
2768	if (RT_FAILURE(rc))
2769	return rc;
2770
2771	if (pThis->fR0Enabled)
2772	{
2773	rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, 32,
2774	0, "buslogicIOPortWrite", "buslogicIOPortRead", NULL, NULL, "BusLogic PCI");
2775	if (RT_FAILURE(rc))
2776	return rc;
2777	}
2778
2779	if (pThis->fGCEnabled)
2780	{
2781	rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, 32,
2782	0, "buslogicIOPortWrite", "buslogicIOPortRead", NULL, NULL, "BusLogic PCI");
2783	if (RT_FAILURE(rc))
2784	return rc;
2785	}
2786
2787	pThis->IOPortBase = (RTIOPORT)GCPhysAddress;
2788	}
2789	else
2790	AssertMsgFailed(("Invalid enmType=%d\n", enmType));
2791
2792	return rc;
2793	}
2794
2795	static DECLCALLBACK(int) buslogicR3DeviceSCSIRequestCompleted(PPDMISCSIPORT pInterface, PPDMSCSIREQUEST pSCSIRequest,
2796	int rcCompletion, bool fRedo, int rcReq)
2797	{
2798	int rc;
2799	PBUSLOGICTASKSTATE pTaskState = (PBUSLOGICTASKSTATE)pSCSIRequest->pvUser;
2800	PBUSLOGICDEVICE pBusLogicDevice = pTaskState->CTX_SUFF(pTargetDevice);
2801	PBUSLOGIC pBusLogic = pBusLogicDevice->CTX_SUFF(pBusLogic);
2802
2803	LogFlowFunc(("before decrement %u\n", pBusLogicDevice->cOutstandingRequests));
2804	ASMAtomicDecU32(&pBusLogicDevice->cOutstandingRequests);
2805	LogFlowFunc(("after decrement %u\n", pBusLogicDevice->cOutstandingRequests));
2806
2807	if (fRedo)
2808	{
2809	if (!pTaskState->fBIOS)
2810	{
2811	buslogicR3DataBufferFree(pTaskState);
2812
2813	if (pTaskState->pbSenseBuffer)
2814	buslogicR3SenseBufferFree(pTaskState, false /* fCopy */);
2815	}
2816
2817	/* Add to the list. */
2818	do
2819	{
2820	pTaskState->pRedoNext = ASMAtomicReadPtrT(&pBusLogic->pTasksRedoHead, PBUSLOGICTASKSTATE);
2821	} while (!ASMAtomicCmpXchgPtr(&pBusLogic->pTasksRedoHead, pTaskState, pTaskState->pRedoNext));
2822
2823	/* Suspend the VM if not done already. */
2824	if (!ASMAtomicXchgBool(&pBusLogic->fRedo, true))
2825	buslogicR3RedoSetWarning(pBusLogic, rcReq);
2826	}
2827	else
2828	{
2829	if (pTaskState->fBIOS)
2830	{
2831	rc = vboxscsiRequestFinished(&pBusLogic->VBoxSCSI, pSCSIRequest, rcCompletion);
2832	AssertMsgRC(rc, ("Finishing BIOS SCSI request failed rc=%Rrc\n", rc));
2833	}
2834	else
2835	{
2836	buslogicR3DataBufferFree(pTaskState);
2837
2838	if (pTaskState->pbSenseBuffer)
2839	buslogicR3SenseBufferFree(pTaskState, (rcCompletion != SCSI_STATUS_OK));
2840
2841	if (rcCompletion == SCSI_STATUS_OK)
2842	buslogicR3SendIncomingMailbox(pBusLogic, pTaskState,
2843	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_CMD_COMPLETED,
2844	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_OPERATION_GOOD,
2845	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITHOUT_ERROR);
2846	else if (rcCompletion == SCSI_STATUS_CHECK_CONDITION)
2847	buslogicR3SendIncomingMailbox(pBusLogic, pTaskState,
2848	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_CMD_COMPLETED,
2849	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_CHECK_CONDITION,
2850	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITH_ERROR);
2851	else
2852	AssertMsgFailed(("invalid completion status %d\n", rcCompletion));
2853	}
2854	#ifdef LOG_ENABLED
2855	buslogicR3DumpCCBInfo(&pTaskState->CommandControlBlockGuest, pTaskState->fIs24Bit);
2856	#endif
2857
2858	/* Remove task from the cache. */
2859	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
2860	}
2861
2862	if (pBusLogicDevice->cOutstandingRequests == 0 && pBusLogic->fSignalIdle)
2863	PDMDevHlpAsyncNotificationCompleted(pBusLogic->pDevInsR3);
2864
2865	return VINF_SUCCESS;
2866	}
2867
2868	static DECLCALLBACK(int) buslogicR3QueryDeviceLocation(PPDMISCSIPORT pInterface, const char **ppcszController,
2869	uint32_t piInstance, uint32_t piLUN)
2870	{
2871	PBUSLOGICDEVICE pBusLogicDevice = PDMISCSIPORT_2_PBUSLOGICDEVICE(pInterface);
2872	PPDMDEVINS pDevIns = pBusLogicDevice->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);
2873
2874	AssertPtrReturn(ppcszController, VERR_INVALID_POINTER);
2875	AssertPtrReturn(piInstance, VERR_INVALID_POINTER);
2876	AssertPtrReturn(piLUN, VERR_INVALID_POINTER);
2877
2878	*ppcszController = pDevIns->pReg->szName;
2879	*piInstance = pDevIns->iInstance;
2880	*piLUN = pBusLogicDevice->iLUN;
2881
2882	return VINF_SUCCESS;
2883	}
2884
2885	static int buslogicR3DeviceSCSIRequestSetup(PBUSLOGIC pBusLogic, PBUSLOGICTASKSTATE pTaskState)
2886	{
2887	int rc = VINF_SUCCESS;
2888	uint8_t uTargetIdCCB;
2889	PBUSLOGICDEVICE pTargetDevice;
2890
2891	/* Fetch the CCB from guest memory. */
2892	/** @todo How much do we really have to read? */
2893	RTGCPHYS GCPhysAddrCCB = (RTGCPHYS)pTaskState->MailboxGuest.u32PhysAddrCCB;
2894	PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrCCB,
2895	&pTaskState->CommandControlBlockGuest, sizeof(CCB32));
2896
2897	uTargetIdCCB = pTaskState->fIs24Bit ? pTaskState->CommandControlBlockGuest.o.uTargetId : pTaskState->CommandControlBlockGuest.n.uTargetId;
2898	pTargetDevice = &pBusLogic->aDeviceStates[uTargetIdCCB];
2899	pTaskState->CTX_SUFF(pTargetDevice) = pTargetDevice;
2900
2901	#ifdef LOG_ENABLED
2902	buslogicR3DumpCCBInfo(&pTaskState->CommandControlBlockGuest, pTaskState->fIs24Bit);
2903	#endif
2904
2905	/* Alloc required buffers. */
2906	rc = buslogicR3DataBufferAlloc(pTaskState);
2907	AssertMsgRC(rc, ("Alloc failed rc=%Rrc\n", rc));
2908
2909	rc = buslogicR3SenseBufferAlloc(pTaskState);
2910	AssertMsgRC(rc, ("Mapping sense buffer failed rc=%Rrc\n", rc));
2911
2912	/* Check if device is present on bus. If not return error immediately and don't process this further. */
2913	if (!pBusLogic->aDeviceStates[uTargetIdCCB].fPresent)
2914	{
2915	buslogicR3DataBufferFree(pTaskState);
2916
2917	if (pTaskState->pbSenseBuffer)
2918	buslogicR3SenseBufferFree(pTaskState, true);
2919
2920	buslogicR3SendIncomingMailbox(pBusLogic, pTaskState,
2921	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_SCSI_SELECTION_TIMEOUT,
2922	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_OPERATION_GOOD,
2923	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITH_ERROR);
2924
2925	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
2926	}
2927	else
2928	{
2929	/* Setup SCSI request. */
2930	pTaskState->PDMScsiRequest.uLogicalUnit = pTaskState->fIs24Bit ? pTaskState->CommandControlBlockGuest.o.uLogicalUnit
2931	: pTaskState->CommandControlBlockGuest.n.uLogicalUnit;
2932
2933	if (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_UNKNOWN)
2934	pTaskState->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_UNKNOWN;
2935	else if (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_IN)
2936	pTaskState->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_FROM_DEVICE;
2937	else if (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_OUT)
2938	pTaskState->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_TO_DEVICE;
2939	else if (pTaskState->CommandControlBlockGuest.c.uDataDirection == BUSLOGIC_CCB_DIRECTION_NO_DATA)
2940	pTaskState->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_NONE;
2941	else
2942	AssertMsgFailed(("Invalid data direction type %d\n", pTaskState->CommandControlBlockGuest.c.uDataDirection));
2943
2944	pTaskState->PDMScsiRequest.cbCDB = pTaskState->CommandControlBlockGuest.c.cbCDB;
2945	pTaskState->PDMScsiRequest.pbCDB = pTaskState->CommandControlBlockGuest.c.abCDB;
2946	if (pTaskState->DataSeg.cbSeg)
2947	{
2948	pTaskState->PDMScsiRequest.cbScatterGather = pTaskState->DataSeg.cbSeg;
2949	pTaskState->PDMScsiRequest.cScatterGatherEntries = 1;
2950	pTaskState->PDMScsiRequest.paScatterGatherHead = &pTaskState->DataSeg;
2951	}
2952	else
2953	{
2954	pTaskState->PDMScsiRequest.cbScatterGather = 0;
2955	pTaskState->PDMScsiRequest.cScatterGatherEntries = 0;
2956	pTaskState->PDMScsiRequest.paScatterGatherHead = NULL;
2957	}
2958	pTaskState->PDMScsiRequest.cbSenseBuffer = buslogicR3ConvertSenseBufferLength(pTaskState->CommandControlBlockGuest.c.cbSenseData);
2959	pTaskState->PDMScsiRequest.pbSenseBuffer = pTaskState->pbSenseBuffer;
2960	pTaskState->PDMScsiRequest.pvUser = pTaskState;
2961
2962	ASMAtomicIncU32(&pTargetDevice->cOutstandingRequests);
2963	rc = pTargetDevice->pDrvSCSIConnector->pfnSCSIRequestSend(pTargetDevice->pDrvSCSIConnector, &pTaskState->PDMScsiRequest);
2964	AssertMsgRC(rc, ("Sending request to SCSI layer failed rc=%Rrc\n", rc));
2965	}
2966
2967	return rc;
2968	}
2969
2970	static int buslogicR3DeviceSCSIRequestAbort(PBUSLOGIC pBusLogic, PBUSLOGICTASKSTATE pTaskState)
2971	{
2972	int rc = VINF_SUCCESS;
2973	uint8_t uTargetIdCCB;
2974	PBUSLOGICDEVICE pTargetDevice;
2975	RTGCPHYS GCPhysAddrCCB = (RTGCPHYS)pTaskState->MailboxGuest.u32PhysAddrCCB;
2976
2977	PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrCCB,
2978	&pTaskState->CommandControlBlockGuest, sizeof(CCB32));
2979
2980	uTargetIdCCB = pTaskState->fIs24Bit ? pTaskState->CommandControlBlockGuest.o.uTargetId : pTaskState->CommandControlBlockGuest.n.uTargetId;
2981	pTargetDevice = &pBusLogic->aDeviceStates[uTargetIdCCB];
2982	pTaskState->CTX_SUFF(pTargetDevice) = pTargetDevice;
2983
2984	buslogicR3SendIncomingMailbox(pBusLogic, pTaskState,
2985	BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_ABORT_QUEUE_GENERATED,
2986	BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_OPERATION_GOOD,
2987	BUSLOGIC_MAILBOX_INCOMING_COMPLETION_ABORTED_NOT_FOUND);
2988
2989	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
2990
2991	return rc;
2992	}
2993
2994	/**
2995	* Read a mailbox from guest memory. Convert 24-bit mailboxes to
2996	* 32-bit format.
2997	*
2998	* @returns Mailbox guest physical address.
2999	* @param pBusLogic Pointer to the BusLogic instance data.
3000	* @param pTaskStat Pointer to the task state being set up.
3001	*/
3002	static RTGCPHYS buslogicR3ReadOutgoingMailbox(PBUSLOGIC pBusLogic, PBUSLOGICTASKSTATE pTaskState)
3003	{
3004	RTGCPHYS GCMailbox;
3005
3006	if (pBusLogic->fMbxIs24Bit)
3007	{
3008	Mailbox24 Mbx24;
3009
3010	GCMailbox = pBusLogic->GCPhysAddrMailboxOutgoingBase + (pBusLogic->uMailboxOutgoingPositionCurrent * sizeof(Mailbox24));
3011	PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCMailbox, &Mbx24, sizeof(Mailbox24));
3012	pTaskState->MailboxGuest.u32PhysAddrCCB = ADDR_TO_U32(Mbx24.aPhysAddrCCB);
3013	pTaskState->MailboxGuest.u.out.uActionCode = Mbx24.uCmdState;
3014	}
3015	else
3016	{
3017	GCMailbox = pBusLogic->GCPhysAddrMailboxOutgoingBase + (pBusLogic->uMailboxOutgoingPositionCurrent * sizeof(Mailbox32));
3018	PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCMailbox, &pTaskState->MailboxGuest, sizeof(Mailbox32));
3019	}
3020
3021	return GCMailbox;
3022	}
3023
3024	/**
3025	* Read mailbox from the guest and execute command.
3026	*
3027	* @returns VBox status code.
3028	* @param pBusLogic Pointer to the BusLogic instance data.
3029	*/
3030	static int buslogicR3ProcessMailboxNext(PBUSLOGIC pBusLogic)
3031	{
3032	PBUSLOGICTASKSTATE pTaskState = NULL;
3033	RTGCPHYS GCPhysAddrMailboxCurrent;
3034	int rc;
3035
3036	rc = RTMemCacheAllocEx(pBusLogic->hTaskCache, (void **)&pTaskState);
3037	AssertMsgReturn(RT_SUCCESS(rc) && (pTaskState != NULL), ("Failed to get task state from cache\n"), rc);
3038
3039	pTaskState->fBIOS = false;
3040	pTaskState->fIs24Bit = pBusLogic->fMbxIs24Bit;
3041	pTaskState->cbSGEntry = pBusLogic->fMbxIs24Bit ? sizeof(SGE24) : sizeof(SGE32);
3042
3043	if (!pBusLogic->fStrictRoundRobinMode)
3044	{
3045	/* Search for a filled mailbox - stop if we have scanned all mailboxes. */
3046	uint8_t uMailboxPosCur = pBusLogic->uMailboxOutgoingPositionCurrent;
3047
3048	do
3049	{
3050	/* Fetch mailbox from guest memory. */
3051	GCPhysAddrMailboxCurrent = buslogicR3ReadOutgoingMailbox(pBusLogic,pTaskState);
3052
3053	/* Check the next mailbox. */
3054	buslogicR3OutgoingMailboxAdvance(pBusLogic);
3055	} while ( pTaskState->MailboxGuest.u.out.uActionCode == BUSLOGIC_MAILBOX_OUTGOING_ACTION_FREE
3056	&& uMailboxPosCur != pBusLogic->uMailboxOutgoingPositionCurrent);
3057	}
3058	else
3059	{
3060	/* Fetch mailbox from guest memory. */
3061	GCPhysAddrMailboxCurrent = buslogicR3ReadOutgoingMailbox(pBusLogic,pTaskState);
3062	}
3063
3064	/*
3065	* Check if the mailbox is actually loaded.
3066	* It might be possible that the guest notified us without
3067	* a loaded mailbox. Do nothing in that case but leave a
3068	* log entry.
3069	*/
3070	if (pTaskState->MailboxGuest.u.out.uActionCode == BUSLOGIC_MAILBOX_OUTGOING_ACTION_FREE)
3071	{
3072	Log(("No loaded mailbox left\n"));
3073	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
3074	return VERR_NO_DATA;
3075	}
3076
3077	LogFlow(("Got loaded mailbox at slot %u, CCB phys %RGp\n", pBusLogic->uMailboxOutgoingPositionCurrent, (RTGCPHYS)pTaskState->MailboxGuest.u32PhysAddrCCB));
3078	#ifdef LOG_ENABLED
3079	buslogicR3DumpMailboxInfo(&pTaskState->MailboxGuest, true);
3080	#endif
3081
3082	/* We got the mailbox, mark it as free in the guest. */
3083	uint8_t uActionCode = BUSLOGIC_MAILBOX_OUTGOING_ACTION_FREE;
3084	unsigned uCodeOffs = pTaskState->fIs24Bit ? RT_OFFSETOF(Mailbox24, uCmdState) : RT_OFFSETOF(Mailbox32, u.out.uActionCode);
3085	PDMDevHlpPCIPhysWrite(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrMailboxCurrent + uCodeOffs, &uActionCode, sizeof(uActionCode));
3086
3087	if (pTaskState->MailboxGuest.u.out.uActionCode == BUSLOGIC_MAILBOX_OUTGOING_ACTION_START_COMMAND)
3088	rc = buslogicR3DeviceSCSIRequestSetup(pBusLogic, pTaskState);
3089	else if (pTaskState->MailboxGuest.u.out.uActionCode == BUSLOGIC_MAILBOX_OUTGOING_ACTION_ABORT_COMMAND)
3090	{
3091	LogFlow(("Aborting mailbox\n"));
3092	rc = buslogicR3DeviceSCSIRequestAbort(pBusLogic, pTaskState);
3093	}
3094	else
3095	AssertMsgFailed(("Invalid outgoing mailbox action code %u\n", pTaskState->MailboxGuest.u.out.uActionCode));
3096
3097	AssertRC(rc);
3098
3099	/* Advance to the next mailbox. */
3100	if (pBusLogic->fStrictRoundRobinMode)
3101	buslogicR3OutgoingMailboxAdvance(pBusLogic);
3102
3103	return rc;
3104	}
3105
3106	/**
3107	* Transmit queue consumer
3108	* Queue a new async task.
3109	*
3110	* @returns Success indicator.
3111	* If false the item will not be removed and the flushing will stop.
3112	* @param pDevIns The device instance.
3113	* @param pItem The item to consume. Upon return this item will be freed.
3114	*/
3115	static DECLCALLBACK(bool) buslogicR3NotifyQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
3116	{
3117	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3118
3119	/* Reset notification send flag now. */
3120	Assert(pBusLogic->fNotificationSend);
3121	ASMAtomicXchgBool(&pBusLogic->fNotificationSend, false);
3122	ASMAtomicXchgU32(&pBusLogic->cMailboxesReady, 0); /** @todo Actually not required anymore but to stay compatible with older saved states. */
3123
3124	/* Process mailboxes. */
3125	int rc;
3126	do
3127	{
3128	rc = buslogicR3ProcessMailboxNext(pBusLogic);
3129	AssertMsg(RT_SUCCESS(rc) \|\| rc == VERR_NO_DATA, ("Processing mailbox failed rc=%Rrc\n", rc));
3130	} while (RT_SUCCESS(rc));
3131
3132	return true;
3133	}
3134
3135	/**
3136	* Kicks the controller to process pending tasks after the VM was resumed
3137	* or loaded from a saved state.
3138	*
3139	* @returns nothing.
3140	* @param pThis The BusLogic device instance.
3141	*/
3142	static void buslogicR3Kick(PBUSLOGIC pThis)
3143	{
3144	if (pThis->fRedo)
3145	{
3146	pThis->fRedo = false;
3147	if (pThis->VBoxSCSI.fBusy)
3148	{
3149
3150	/* The BIOS had a request active when we got suspended. Resume it. */
3151	int rc = buslogicR3PrepareBIOSSCSIRequest(pThis);
3152	AssertRC(rc);
3153	}
3154	else
3155	{
3156	/* Queue all pending tasks again. */
3157	PBUSLOGICTASKSTATE pTaskState = pThis->pTasksRedoHead;
3158
3159	pThis->pTasksRedoHead = NULL;
3160
3161	while (pTaskState)
3162	{
3163	PBUSLOGICTASKSTATE pCur = pTaskState;
3164
3165	int rc = buslogicR3DeviceSCSIRequestSetup(pThis, pCur);
3166	AssertRC(rc);
3167
3168	pTaskState = pTaskState->pRedoNext;
3169	}
3170	}
3171	}
3172	}
3173
3174	/** @callback_method_impl{FNSSMDEVLIVEEXEC} */
3175	static DECLCALLBACK(int) buslogicR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
3176	{
3177	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3178
3179	/* Save the device config. */
3180	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDeviceStates); i++)
3181	SSMR3PutBool(pSSM, pThis->aDeviceStates[i].fPresent);
3182
3183	return VINF_SSM_DONT_CALL_AGAIN;
3184	}
3185
3186	/** @callback_method_impl{FNSSMDEVSAVEEXEC} */
3187	static DECLCALLBACK(int) buslogicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3188	{
3189	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3190
3191	/* Every device first. */
3192	for (unsigned i = 0; i < RT_ELEMENTS(pBusLogic->aDeviceStates); i++)
3193	{
3194	PBUSLOGICDEVICE pDevice = &pBusLogic->aDeviceStates[i];
3195
3196	AssertMsg(!pDevice->cOutstandingRequests,
3197	("There are still outstanding requests on this device\n"));
3198	SSMR3PutBool(pSSM, pDevice->fPresent);
3199	SSMR3PutU32(pSSM, pDevice->cOutstandingRequests);
3200	}
3201	/* Now the main device state. */
3202	SSMR3PutU8 (pSSM, pBusLogic->regStatus);
3203	SSMR3PutU8 (pSSM, pBusLogic->regInterrupt);
3204	SSMR3PutU8 (pSSM, pBusLogic->regGeometry);
3205	SSMR3PutMem (pSSM, &pBusLogic->LocalRam, sizeof(pBusLogic->LocalRam));
3206	SSMR3PutU8 (pSSM, pBusLogic->uOperationCode);
3207	SSMR3PutMem (pSSM, &pBusLogic->aCommandBuffer, sizeof(pBusLogic->aCommandBuffer));
3208	SSMR3PutU8 (pSSM, pBusLogic->iParameter);
3209	SSMR3PutU8 (pSSM, pBusLogic->cbCommandParametersLeft);
3210	SSMR3PutBool (pSSM, pBusLogic->fUseLocalRam);
3211	SSMR3PutMem (pSSM, pBusLogic->aReplyBuffer, sizeof(pBusLogic->aReplyBuffer));
3212	SSMR3PutU8 (pSSM, pBusLogic->iReply);
3213	SSMR3PutU8 (pSSM, pBusLogic->cbReplyParametersLeft);
3214	SSMR3PutBool (pSSM, pBusLogic->fIRQEnabled);
3215	SSMR3PutU8 (pSSM, pBusLogic->uISABaseCode);
3216	SSMR3PutU32 (pSSM, pBusLogic->cMailbox);
3217	SSMR3PutBool (pSSM, pBusLogic->fMbxIs24Bit);
3218	SSMR3PutGCPhys(pSSM, pBusLogic->GCPhysAddrMailboxOutgoingBase);
3219	SSMR3PutU32 (pSSM, pBusLogic->uMailboxOutgoingPositionCurrent);
3220	SSMR3PutU32 (pSSM, pBusLogic->cMailboxesReady);
3221	SSMR3PutBool (pSSM, pBusLogic->fNotificationSend);
3222	SSMR3PutGCPhys(pSSM, pBusLogic->GCPhysAddrMailboxIncomingBase);
3223	SSMR3PutU32 (pSSM, pBusLogic->uMailboxIncomingPositionCurrent);
3224	SSMR3PutBool (pSSM, pBusLogic->fStrictRoundRobinMode);
3225	SSMR3PutBool (pSSM, pBusLogic->fExtendedLunCCBFormat);
3226	/* Now the data for the BIOS interface. */
3227	SSMR3PutU8 (pSSM, pBusLogic->VBoxSCSI.regIdentify);
3228	SSMR3PutU8 (pSSM, pBusLogic->VBoxSCSI.uTargetDevice);
3229	SSMR3PutU8 (pSSM, pBusLogic->VBoxSCSI.uTxDir);
3230	SSMR3PutU8 (pSSM, pBusLogic->VBoxSCSI.cbCDB);
3231	SSMR3PutMem (pSSM, pBusLogic->VBoxSCSI.abCDB, sizeof(pBusLogic->VBoxSCSI.abCDB));
3232	SSMR3PutU8 (pSSM, pBusLogic->VBoxSCSI.iCDB);
3233	SSMR3PutU32 (pSSM, pBusLogic->VBoxSCSI.cbBuf);
3234	SSMR3PutU32 (pSSM, pBusLogic->VBoxSCSI.iBuf);
3235	SSMR3PutBool (pSSM, pBusLogic->VBoxSCSI.fBusy);
3236	SSMR3PutU8 (pSSM, pBusLogic->VBoxSCSI.enmState);
3237	if (pBusLogic->VBoxSCSI.cbBuf)
3238	SSMR3PutMem(pSSM, pBusLogic->VBoxSCSI.pbBuf, pBusLogic->VBoxSCSI.cbBuf);
3239
3240	/*
3241	* Save the physical addresses of the command control blocks of still pending tasks.
3242	* They are processed again on resume.
3243	*
3244	* The number of pending tasks needs to be determined first.
3245	*/
3246	uint32_t cTasks = 0;
3247
3248	PBUSLOGICTASKSTATE pTaskState = pBusLogic->pTasksRedoHead;
3249	if (pBusLogic->fRedo)
3250	{
3251	while (pTaskState)
3252	{
3253	cTasks++;
3254	pTaskState = pTaskState->pRedoNext;
3255	}
3256	}
3257	SSMR3PutU32(pSSM, cTasks);
3258
3259	/* Write the address of every task now. */
3260	pTaskState = pBusLogic->pTasksRedoHead;
3261	while (pTaskState)
3262	{
3263	SSMR3PutU32(pSSM, pTaskState->MailboxGuest.u32PhysAddrCCB);
3264	pTaskState = pTaskState->pRedoNext;
3265	}
3266
3267	return SSMR3PutU32(pSSM, ~0);
3268	}
3269
3270	/** @callback_method_impl{FNSSMDEVLOADDONE} */
3271	static DECLCALLBACK(int) buslogicR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3272	{
3273	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3274
3275	buslogicR3RegisterISARange(pThis, pThis->uISABaseCode);
3276	buslogicR3Kick(pThis);
3277	return VINF_SUCCESS;
3278	}
3279
3280	/** @callback_method_impl{FNSSMDEVLOADEXEC} */
3281	static DECLCALLBACK(int) buslogicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3282	{
3283	PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3284	int rc = VINF_SUCCESS;
3285
3286	/* We support saved states only from this and older versions. */
3287	if (uVersion > BUSLOGIC_SAVED_STATE_MINOR_VERSION)
3288	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3289
3290	/* Every device first. */
3291	for (unsigned i = 0; i < RT_ELEMENTS(pBusLogic->aDeviceStates); i++)
3292	{
3293	PBUSLOGICDEVICE pDevice = &pBusLogic->aDeviceStates[i];
3294
3295	AssertMsg(!pDevice->cOutstandingRequests,
3296	("There are still outstanding requests on this device\n"));
3297	bool fPresent;
3298	rc = SSMR3GetBool(pSSM, &fPresent);
3299	AssertRCReturn(rc, rc);
3300	if (pDevice->fPresent != fPresent)
3301	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Target %u config mismatch: config=%RTbool state=%RTbool"), i, pDevice->fPresent, fPresent);
3302
3303	if (uPass == SSM_PASS_FINAL)
3304	SSMR3GetU32(pSSM, (uint32_t *)&pDevice->cOutstandingRequests);
3305	}
3306
3307	if (uPass != SSM_PASS_FINAL)
3308	return VINF_SUCCESS;
3309
3310	/* Now the main device state. */
3311	SSMR3GetU8 (pSSM, (uint8_t *)&pBusLogic->regStatus);
3312	SSMR3GetU8 (pSSM, (uint8_t *)&pBusLogic->regInterrupt);
3313	SSMR3GetU8 (pSSM, (uint8_t *)&pBusLogic->regGeometry);
3314	SSMR3GetMem (pSSM, &pBusLogic->LocalRam, sizeof(pBusLogic->LocalRam));
3315	SSMR3GetU8 (pSSM, &pBusLogic->uOperationCode);
3316	if (uVersion > BUSLOGIC_SAVED_STATE_MINOR_PRE_CMDBUF_RESIZE)
3317	SSMR3GetMem (pSSM, &pBusLogic->aCommandBuffer, sizeof(pBusLogic->aCommandBuffer));
3318	else
3319	SSMR3GetMem (pSSM, &pBusLogic->aCommandBuffer, BUSLOGIC_COMMAND_SIZE_OLD);
3320	SSMR3GetU8 (pSSM, &pBusLogic->iParameter);
3321	SSMR3GetU8 (pSSM, &pBusLogic->cbCommandParametersLeft);
3322	SSMR3GetBool (pSSM, &pBusLogic->fUseLocalRam);
3323	SSMR3GetMem (pSSM, pBusLogic->aReplyBuffer, sizeof(pBusLogic->aReplyBuffer));
3324	SSMR3GetU8 (pSSM, &pBusLogic->iReply);
3325	SSMR3GetU8 (pSSM, &pBusLogic->cbReplyParametersLeft);
3326	SSMR3GetBool (pSSM, &pBusLogic->fIRQEnabled);
3327	SSMR3GetU8 (pSSM, &pBusLogic->uISABaseCode);
3328	SSMR3GetU32 (pSSM, &pBusLogic->cMailbox);
3329	if (uVersion > BUSLOGIC_SAVED_STATE_MINOR_PRE_24BIT_MBOX)
3330	SSMR3GetBool (pSSM, &pBusLogic->fMbxIs24Bit);
3331	SSMR3GetGCPhys(pSSM, &pBusLogic->GCPhysAddrMailboxOutgoingBase);
3332	SSMR3GetU32 (pSSM, &pBusLogic->uMailboxOutgoingPositionCurrent);
3333	SSMR3GetU32 (pSSM, (uint32_t *)&pBusLogic->cMailboxesReady);
3334	SSMR3GetBool (pSSM, (bool *)&pBusLogic->fNotificationSend);
3335	SSMR3GetGCPhys(pSSM, &pBusLogic->GCPhysAddrMailboxIncomingBase);
3336	SSMR3GetU32 (pSSM, &pBusLogic->uMailboxIncomingPositionCurrent);
3337	SSMR3GetBool (pSSM, &pBusLogic->fStrictRoundRobinMode);
3338	SSMR3GetBool (pSSM, &pBusLogic->fExtendedLunCCBFormat);
3339	/* Now the data for the BIOS interface. */
3340	SSMR3GetU8 (pSSM, &pBusLogic->VBoxSCSI.regIdentify);
3341	SSMR3GetU8 (pSSM, &pBusLogic->VBoxSCSI.uTargetDevice);
3342	SSMR3GetU8 (pSSM, &pBusLogic->VBoxSCSI.uTxDir);
3343	SSMR3GetU8 (pSSM, &pBusLogic->VBoxSCSI.cbCDB);
3344	SSMR3GetMem (pSSM, pBusLogic->VBoxSCSI.abCDB, sizeof(pBusLogic->VBoxSCSI.abCDB));
3345	SSMR3GetU8 (pSSM, &pBusLogic->VBoxSCSI.iCDB);
3346	SSMR3GetU32 (pSSM, &pBusLogic->VBoxSCSI.cbBuf);
3347	SSMR3GetU32 (pSSM, &pBusLogic->VBoxSCSI.iBuf);
3348	SSMR3GetBool(pSSM, (bool *)&pBusLogic->VBoxSCSI.fBusy);
3349	SSMR3GetU8 (pSSM, (uint8_t *)&pBusLogic->VBoxSCSI.enmState);
3350	if (pBusLogic->VBoxSCSI.cbBuf)
3351	{
3352	pBusLogic->VBoxSCSI.pbBuf = (uint8_t *)RTMemAllocZ(pBusLogic->VBoxSCSI.cbBuf);
3353	if (!pBusLogic->VBoxSCSI.pbBuf)
3354	{
3355	LogRel(("BusLogic: Out of memory during restore.\n"));
3356	return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY,
3357	N_("BusLogic: Out of memory during restore\n"));
3358	}
3359	SSMR3GetMem(pSSM, pBusLogic->VBoxSCSI.pbBuf, pBusLogic->VBoxSCSI.cbBuf);
3360	}
3361
3362	if (pBusLogic->VBoxSCSI.fBusy)
3363	pBusLogic->fRedo = true;
3364
3365	if (uVersion > BUSLOGIC_SAVED_STATE_MINOR_PRE_ERROR_HANDLING)
3366	{
3367	/* Check if there are pending tasks saved. */
3368	uint32_t cTasks = 0;
3369
3370	SSMR3GetU32(pSSM, &cTasks);
3371
3372	if (cTasks)
3373	pBusLogic->fRedo = true;
3374
3375	for (uint32_t i = 0; i < cTasks; i++)
3376	{
3377	PBUSLOGICTASKSTATE pTaskState = (PBUSLOGICTASKSTATE)RTMemCacheAlloc(pBusLogic->hTaskCache);
3378	if (!pTaskState)
3379	{
3380	rc = VERR_NO_MEMORY;
3381	break;
3382	}
3383
3384	rc = SSMR3GetU32(pSSM, &pTaskState->MailboxGuest.u32PhysAddrCCB);
3385	if (RT_FAILURE(rc))
3386	{
3387	RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);
3388	break;
3389	}
3390
3391	/* Link into the list. */
3392	pTaskState->pRedoNext = pBusLogic->pTasksRedoHead;
3393	pBusLogic->pTasksRedoHead = pTaskState;
3394	}
3395	}
3396
3397	if (RT_SUCCESS(rc))
3398	{
3399	uint32_t u32;
3400	rc = SSMR3GetU32(pSSM, &u32);
3401	if (RT_SUCCESS(rc))
3402	AssertMsgReturn(u32 == ~0U, ("%#x\n", u32), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
3403	}
3404
3405	return rc;
3406	}
3407
3408	/**
3409	* Gets the pointer to the status LED of a device - called from the SCSI driver.
3410	*
3411	* @returns VBox status code.
3412	* @param pInterface Pointer to the interface structure containing the called function pointer.
3413	* @param iLUN The unit which status LED we desire. Always 0 here as the driver
3414	* doesn't know about other LUN's.
3415	* @param ppLed Where to store the LED pointer.
3416	*/
3417	static DECLCALLBACK(int) buslogicR3DeviceQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
3418	{
3419	PBUSLOGICDEVICE pDevice = PDMILEDPORTS_2_PBUSLOGICDEVICE(pInterface);
3420	if (iLUN == 0)
3421	{
3422	*ppLed = &pDevice->Led;
3423	Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
3424	return VINF_SUCCESS;
3425	}
3426	return VERR_PDM_LUN_NOT_FOUND;
3427	}
3428
3429	/**
3430	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
3431	*/
3432	static DECLCALLBACK(void ) buslogicR3DeviceQueryInterface(PPDMIBASE pInterface, const char pszIID)
3433	{
3434	PBUSLOGICDEVICE pDevice = PDMIBASE_2_PBUSLOGICDEVICE(pInterface);
3435	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevice->IBase);
3436	PDMIBASE_RETURN_INTERFACE(pszIID, PDMISCSIPORT, &pDevice->ISCSIPort);
3437	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pDevice->ILed);
3438	return NULL;
3439	}
3440
3441	/**
3442	* Gets the pointer to the status LED of a unit.
3443	*
3444	* @returns VBox status code.
3445	* @param pInterface Pointer to the interface structure containing the called function pointer.
3446	* @param iLUN The unit which status LED we desire.
3447	* @param ppLed Where to store the LED pointer.
3448	*/
3449	static DECLCALLBACK(int) buslogicR3StatusQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
3450	{
3451	PBUSLOGIC pBusLogic = PDMILEDPORTS_2_PBUSLOGIC(pInterface);
3452	if (iLUN < BUSLOGIC_MAX_DEVICES)
3453	{
3454	*ppLed = &pBusLogic->aDeviceStates[iLUN].Led;
3455	Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
3456	return VINF_SUCCESS;
3457	}
3458	return VERR_PDM_LUN_NOT_FOUND;
3459	}
3460
3461	/**
3462	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
3463	*/
3464	static DECLCALLBACK(void ) buslogicR3StatusQueryInterface(PPDMIBASE pInterface, const char pszIID)
3465	{
3466	PBUSLOGIC pThis = PDMIBASE_2_PBUSLOGIC(pInterface);
3467	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
3468	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
3469	return NULL;
3470	}
3471
3472	/**
3473	* BusLogic debugger info callback.
3474	*
3475	* @param pDevIns The device instance.
3476	* @param pHlp The output helpers.
3477	* @param pszArgs The arguments.
3478	*/
3479	static DECLCALLBACK(void) buslogicR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3480	{
3481	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3482	unsigned i;
3483	bool fVerbose = false;
3484
3485	/* Parse arguments. */
3486	if (pszArgs)
3487	fVerbose = strstr(pszArgs, "verbose") != NULL;
3488
3489	/* Show basic information. */
3490	pHlp->pfnPrintf(pHlp,
3491	"%s#%d: PCI I/O=%RTiop ISA I/O=%RTiop MMIO=%RGp IRQ=%u GC=%RTbool R0=%RTbool\n",
3492	pDevIns->pReg->szName,
3493	pDevIns->iInstance,
3494	pThis->IOPortBase, pThis->IOISABase, pThis->MMIOBase,
3495	PCIDevGetInterruptLine(&pThis->dev),
3496	!!pThis->fGCEnabled, !!pThis->fR0Enabled);
3497
3498	/* Print mailbox state. */
3499	if (pThis->regStatus & BL_STAT_INREQ)
3500	pHlp->pfnPrintf(pHlp, "Mailbox not initialized\n");
3501	else
3502	pHlp->pfnPrintf(pHlp, "%u-bit mailbox with %u entries at %RGp (%d LUN CCBs)\n",
3503	pThis->fMbxIs24Bit ? 24 : 32, pThis->cMailbox,
3504	pThis->GCPhysAddrMailboxOutgoingBase,
3505	pThis->fMbxIs24Bit ? 8 : pThis->fExtendedLunCCBFormat ? 64 : 8);
3506
3507	/* Print register contents. */
3508	pHlp->pfnPrintf(pHlp, "Registers: STAT=%02x INTR=%02x GEOM=%02x\n",
3509	pThis->regStatus, pThis->regInterrupt, pThis->regGeometry);
3510
3511	/* Print miscellaneous state. */
3512	pHlp->pfnPrintf(pHlp, "HAC interrupts: %s\n",
3513	pThis->fIRQEnabled ? "on" : "off");
3514
3515	/* Print the current command, if any. */
3516	if (pThis->uOperationCode != 0xff )
3517	pHlp->pfnPrintf(pHlp, "Current command: %02X\n", pThis->uOperationCode);
3518
3519	if (fVerbose && (pThis->regStatus & BL_STAT_INREQ) == 0)
3520	{
3521	RTGCPHYS GCMailbox;
3522
3523	/* Dump the mailbox contents. */
3524	if (pThis->fMbxIs24Bit)
3525	{
3526	Mailbox24 Mbx24;
3527
3528	/* Outgoing mailbox, 24-bit format. */
3529	GCMailbox = pThis->GCPhysAddrMailboxOutgoingBase;
3530	pHlp->pfnPrintf(pHlp, " Outgoing mailbox entries (24-bit) at %06X:\n", GCMailbox);
3531	for (i = 0; i < pThis->cMailbox; ++i)
3532	{
3533	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCMailbox, &Mbx24, sizeof(Mailbox24));
3534	pHlp->pfnPrintf(pHlp, " slot %03d: CCB at %06X action code %02X", i, ADDR_TO_U32(Mbx24.aPhysAddrCCB), Mbx24.uCmdState);
3535	pHlp->pfnPrintf(pHlp, "%s\n", pThis->uMailboxOutgoingPositionCurrent == i ? " *" : "");
3536	GCMailbox += sizeof(Mailbox24);
3537	}
3538
3539	/* Incoming mailbox, 24-bit format. */
3540	GCMailbox = pThis->GCPhysAddrMailboxOutgoingBase + (pThis->cMailbox * sizeof(Mailbox24));
3541	pHlp->pfnPrintf(pHlp, " Incoming mailbox entries (24-bit) at %06X:\n", GCMailbox);
3542	for (i = 0; i < pThis->cMailbox; ++i)
3543	{
3544	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCMailbox, &Mbx24, sizeof(Mailbox24));
3545	pHlp->pfnPrintf(pHlp, " slot %03d: CCB at %06X completion code %02X", i, ADDR_TO_U32(Mbx24.aPhysAddrCCB), Mbx24.uCmdState);
3546	pHlp->pfnPrintf(pHlp, "%s\n", pThis->uMailboxIncomingPositionCurrent == i ? " *" : "");
3547	GCMailbox += sizeof(Mailbox24);
3548	}
3549
3550	}
3551	else
3552	{
3553	Mailbox32 Mbx32;
3554
3555	/* Outgoing mailbox, 32-bit format. */
3556	GCMailbox = pThis->GCPhysAddrMailboxOutgoingBase;
3557	pHlp->pfnPrintf(pHlp, " Outgoing mailbox entries (32-bit) at %08X:\n", (uint32_t)GCMailbox);
3558	for (i = 0; i < pThis->cMailbox; ++i)
3559	{
3560	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCMailbox, &Mbx32, sizeof(Mailbox32));
3561	pHlp->pfnPrintf(pHlp, " slot %03d: CCB at %08X action code %02X", i, Mbx32.u32PhysAddrCCB, Mbx32.u.out.uActionCode);
3562	pHlp->pfnPrintf(pHlp, "%s\n", pThis->uMailboxOutgoingPositionCurrent == i ? " *" : "");
3563	GCMailbox += sizeof(Mailbox32);
3564	}
3565
3566	/* Incoming mailbox, 32-bit format. */
3567	GCMailbox = pThis->GCPhysAddrMailboxOutgoingBase + (pThis->cMailbox * sizeof(Mailbox32));
3568	pHlp->pfnPrintf(pHlp, " Outgoing mailbox entries (32-bit) at %08X:\n", (uint32_t)GCMailbox);
3569	for (i = 0; i < pThis->cMailbox; ++i)
3570	{
3571	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCMailbox, &Mbx32, sizeof(Mailbox32));
3572	pHlp->pfnPrintf(pHlp, " slot %03d: CCB at %08X completion code %02X BTSTAT %02X SDSTAT %02X", i,
3573	Mbx32.u32PhysAddrCCB, Mbx32.u.in.uCompletionCode, Mbx32.u.in.uHostAdapterStatus, Mbx32.u.in.uTargetDeviceStatus);
3574	pHlp->pfnPrintf(pHlp, "%s\n", pThis->uMailboxOutgoingPositionCurrent == i ? " *" : "");
3575	GCMailbox += sizeof(Mailbox32);
3576	}
3577
3578	}
3579	}
3580	}
3581
3582	/* -=-=-=-=- Helper -=-=-=-=- */
3583
3584	/**
3585	* Checks if all asynchronous I/O is finished.
3586	*
3587	* Used by buslogicR3Reset, buslogicR3Suspend and buslogicR3PowerOff.
3588	*
3589	* @returns true if quiesced, false if busy.
3590	* @param pDevIns The device instance.
3591	*/
3592	static bool buslogicR3AllAsyncIOIsFinished(PPDMDEVINS pDevIns)
3593	{
3594	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3595
3596	for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aDeviceStates); i++)
3597	{
3598	PBUSLOGICDEVICE pThisDevice = &pThis->aDeviceStates[i];
3599	if (pThisDevice->pDrvBase)
3600	{
3601	if (pThisDevice->cOutstandingRequests != 0)
3602	return false;
3603	}
3604	}
3605
3606	return true;
3607	}
3608
3609	/**
3610	* Callback employed by buslogicR3Suspend and buslogicR3PowerOff..
3611	*
3612	* @returns true if we've quiesced, false if we're still working.
3613	* @param pDevIns The device instance.
3614	*/
3615	static DECLCALLBACK(bool) buslogicR3IsAsyncSuspendOrPowerOffDone(PPDMDEVINS pDevIns)
3616	{
3617	if (!buslogicR3AllAsyncIOIsFinished(pDevIns))
3618	return false;
3619
3620	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3621	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
3622	return true;
3623	}
3624
3625	/**
3626	* Common worker for ahciR3Suspend and ahciR3PowerOff.
3627	*/
3628	static void buslogicR3SuspendOrPowerOff(PPDMDEVINS pDevIns, bool fPowerOff)
3629	{
3630	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3631
3632	ASMAtomicWriteBool(&pThis->fSignalIdle, true);
3633	if (!buslogicR3AllAsyncIOIsFinished(pDevIns))
3634	PDMDevHlpSetAsyncNotification(pDevIns, buslogicR3IsAsyncSuspendOrPowerOffDone);
3635	else
3636	{
3637	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
3638
3639	AssertMsg(!pThis->fNotificationSend, ("The PDM Queue should be empty at this point\n"));
3640
3641	if (pThis->fRedo)
3642	{
3643	if (fPowerOff)
3644	{
3645	/* Free tasks which would have been queued again on resume. */
3646	PBUSLOGICTASKSTATE pTaskState = pThis->pTasksRedoHead;
3647
3648	pThis->pTasksRedoHead = NULL;
3649
3650	while (pTaskState)
3651	{
3652	PBUSLOGICTASKSTATE pFree;
3653
3654	pFree = pTaskState;
3655	pTaskState = pTaskState->pRedoNext;
3656
3657	RTMemCacheFree(pThis->hTaskCache, pFree);
3658	}
3659	pThis->fRedo = false;
3660	}
3661	else if (pThis->VBoxSCSI.fBusy)
3662	{
3663	/* Destroy the task because the BIOS interface has all necessary information. */
3664	Assert(pThis->pTasksRedoHead->fBIOS);
3665	Assert(!pThis->pTasksRedoHead->pRedoNext);
3666
3667	RTMemCacheFree(pThis->hTaskCache, pThis->pTasksRedoHead);
3668	pThis->pTasksRedoHead = NULL;
3669	}
3670	}
3671	}
3672	}
3673
3674	/**
3675	* Suspend notification.
3676	*
3677	* @param pDevIns The device instance data.
3678	*/
3679	static DECLCALLBACK(void) buslogicR3Suspend(PPDMDEVINS pDevIns)
3680	{
3681	Log(("buslogicR3Suspend\n"));
3682	buslogicR3SuspendOrPowerOff(pDevIns, false /* fPoweroff */);
3683	}
3684
3685	/**
3686	* Resume notification.
3687	*
3688	* @param pDevIns The device instance data.
3689	*/
3690	static DECLCALLBACK(void) buslogicR3Resume(PPDMDEVINS pDevIns)
3691	{
3692	Log(("buslogicR3Resume\n"));
3693	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3694	buslogicR3Kick(pThis);
3695	}
3696
3697
3698	/**
3699	* Detach notification.
3700	*
3701	* One harddisk at one port has been unplugged.
3702	* The VM is suspended at this point.
3703	*
3704	* @param pDevIns The device instance.
3705	* @param iLUN The logical unit which is being detached.
3706	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3707	*/
3708	static DECLCALLBACK(void) buslogicR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3709	{
3710	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3711	PBUSLOGICDEVICE pDevice = &pThis->aDeviceStates[iLUN];
3712
3713	Log(("%s:\n", __FUNCTION__));
3714
3715	AssertMsg(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
3716	("BusLogic: Device does not support hotplugging\n"));
3717
3718	/*
3719	* Zero some important members.
3720	*/
3721	pDevice->pDrvBase = NULL;
3722	pDevice->fPresent = false;
3723	pDevice->pDrvSCSIConnector = NULL;
3724	}
3725
3726	/**
3727	* Attach command.
3728	*
3729	* This is called when we change block driver.
3730	*
3731	* @returns VBox status code.
3732	* @param pDevIns The device instance.
3733	* @param iLUN The logical unit which is being detached.
3734	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3735	*/
3736	static DECLCALLBACK(int) buslogicR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3737	{
3738	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3739	PBUSLOGICDEVICE pDevice = &pThis->aDeviceStates[iLUN];
3740	int rc;
3741
3742	AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
3743	("BusLogic: Device does not support hotplugging\n"),
3744	VERR_INVALID_PARAMETER);
3745
3746	/* the usual paranoia */
3747	AssertRelease(!pDevice->pDrvBase);
3748	AssertRelease(!pDevice->pDrvSCSIConnector);
3749	Assert(pDevice->iLUN == iLUN);
3750
3751	/*
3752	* Try attach the block device and get the interfaces,
3753	* required as well as optional.
3754	*/
3755	rc = PDMDevHlpDriverAttach(pDevIns, pDevice->iLUN, &pDevice->IBase, &pDevice->pDrvBase, NULL);
3756	if (RT_SUCCESS(rc))
3757	{
3758	/* Get SCSI connector interface. */
3759	pDevice->pDrvSCSIConnector = PDMIBASE_QUERY_INTERFACE(pDevice->pDrvBase, PDMISCSICONNECTOR);
3760	AssertMsgReturn(pDevice->pDrvSCSIConnector, ("Missing SCSI interface below\n"), VERR_PDM_MISSING_INTERFACE);
3761	pDevice->fPresent = true;
3762	}
3763	else
3764	AssertMsgFailed(("Failed to attach LUN#%d. rc=%Rrc\n", pDevice->iLUN, rc));
3765
3766	if (RT_FAILURE(rc))
3767	{
3768	pDevice->pDrvBase = NULL;
3769	pDevice->pDrvSCSIConnector = NULL;
3770	}
3771	return rc;
3772	}
3773
3774	/**
3775	* Callback employed by buslogicR3Reset.
3776	*
3777	* @returns true if we've quiesced, false if we're still working.
3778	* @param pDevIns The device instance.
3779	*/
3780	static DECLCALLBACK(bool) buslogicR3IsAsyncResetDone(PPDMDEVINS pDevIns)
3781	{
3782	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3783
3784	if (!buslogicR3AllAsyncIOIsFinished(pDevIns))
3785	return false;
3786	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
3787
3788	buslogicR3HwReset(pThis, true);
3789	return true;
3790	}
3791
3792	/**
3793	* @copydoc FNPDMDEVRESET
3794	*/
3795	static DECLCALLBACK(void) buslogicR3Reset(PPDMDEVINS pDevIns)
3796	{
3797	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3798
3799	ASMAtomicWriteBool(&pThis->fSignalIdle, true);
3800	if (!buslogicR3AllAsyncIOIsFinished(pDevIns))
3801	PDMDevHlpSetAsyncNotification(pDevIns, buslogicR3IsAsyncResetDone);
3802	else
3803	{
3804	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
3805	buslogicR3HwReset(pThis, true);
3806	}
3807	}
3808
3809	static DECLCALLBACK(void) buslogicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
3810	{
3811	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3812
3813	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3814	pThis->pNotifierQueueRC = PDMQueueRCPtr(pThis->pNotifierQueueR3);
3815
3816	for (uint32_t i = 0; i < BUSLOGIC_MAX_DEVICES; i++)
3817	{
3818	PBUSLOGICDEVICE pDevice = &pThis->aDeviceStates[i];
3819
3820	pDevice->pBusLogicRC = PDMINS_2_DATA_RCPTR(pDevIns);
3821	}
3822
3823	}
3824
3825	/**
3826	* Poweroff notification.
3827	*
3828	* @param pDevIns Pointer to the device instance
3829	*/
3830	static DECLCALLBACK(void) buslogicR3PowerOff(PPDMDEVINS pDevIns)
3831	{
3832	Log(("buslogicR3PowerOff\n"));
3833	buslogicR3SuspendOrPowerOff(pDevIns, true /* fPoweroff */);
3834	}
3835
3836	/**
3837	* Destroy a driver instance.
3838	*
3839	* Most VM resources are freed by the VM. This callback is provided so that any non-VM
3840	* resources can be freed correctly.
3841	*
3842	* @param pDevIns The device instance data.
3843	*/
3844	static DECLCALLBACK(int) buslogicR3Destruct(PPDMDEVINS pDevIns)
3845	{
3846	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3847	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
3848
3849	PDMR3CritSectDelete(&pThis->CritSectIntr);
3850
3851	/*
3852	* Free all tasks which are still hanging around
3853	* (Power off after the VM was suspended).
3854	*/
3855	if (pThis->fRedo)
3856	{
3857	/* Free tasks which would have been queued again on resume. */
3858	PBUSLOGICTASKSTATE pTaskState = pThis->pTasksRedoHead;
3859
3860	pThis->pTasksRedoHead = NULL;
3861
3862	while (pTaskState)
3863	{
3864	PBUSLOGICTASKSTATE pFree;
3865
3866	pFree = pTaskState;
3867	pTaskState = pTaskState->pRedoNext;
3868
3869	RTMemCacheFree(pThis->hTaskCache, pFree);
3870	}
3871	pThis->fRedo = false;
3872	}
3873
3874	int rc = RTMemCacheDestroy(pThis->hTaskCache);
3875	AssertMsgRC(rc, ("Destroying task cache failed rc=%Rrc\n", rc));
3876
3877	return rc;
3878	}
3879
3880	/**
3881	* @interface_method_impl{PDMDEVREG,pfnConstruct}
3882	*/
3883	static DECLCALLBACK(int) buslogicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
3884	{
3885	PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);
3886	int rc = VINF_SUCCESS;
3887	bool fBootable = true;
3888	char achISACompat[16];
3889	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3890
3891	/*
3892	* Init instance data (do early because of constructor).
3893	*/
3894	pThis->hTaskCache = NIL_RTMEMCACHE;
3895	pThis->pDevInsR3 = pDevIns;
3896	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
3897	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3898	pThis->IBase.pfnQueryInterface = buslogicR3StatusQueryInterface;
3899	pThis->ILeds.pfnQueryStatusLed = buslogicR3StatusQueryStatusLed;
3900
3901	PCIDevSetVendorId (&pThis->dev, 0x104b); /* BusLogic */
3902	PCIDevSetDeviceId (&pThis->dev, 0x1040); /* BT-958 */
3903	PCIDevSetCommand (&pThis->dev, 0x0003);
3904	PCIDevSetRevisionId (&pThis->dev, 0x01);
3905	PCIDevSetClassProg (&pThis->dev, 0x00); /* SCSI */
3906	PCIDevSetClassSub (&pThis->dev, 0x00); /* SCSI */
3907	PCIDevSetClassBase (&pThis->dev, 0x01); /* Mass storage */
3908	PCIDevSetBaseAddress (&pThis->dev, 0, true /IO/, false /Pref/, false /64-bit/, 0x00000000);
3909	PCIDevSetBaseAddress (&pThis->dev, 1, false /IO/, false /Pref/, false /64-bit/, 0x00000000);
3910	PCIDevSetSubSystemVendorId(&pThis->dev, 0x104b);
3911	PCIDevSetSubSystemId (&pThis->dev, 0x1040);
3912	PCIDevSetInterruptLine (&pThis->dev, 0x00);
3913	PCIDevSetInterruptPin (&pThis->dev, 0x01);
3914
3915	/*
3916	* Validate and read configuration.
3917	*/
3918	if (!CFGMR3AreValuesValid(pCfg,
3919	"GCEnabled\0"
3920	"R0Enabled\0"
3921	"Bootable\0"
3922	"ISACompat\0"))
3923	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
3924	N_("BusLogic configuration error: unknown option specified"));
3925
3926	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &pThis->fGCEnabled, true);
3927	if (RT_FAILURE(rc))
3928	return PDMDEV_SET_ERROR(pDevIns, rc,
3929	N_("BusLogic configuration error: failed to read GCEnabled as boolean"));
3930	Log(("%s: fGCEnabled=%d\n", __FUNCTION__, pThis->fGCEnabled));
3931
3932	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, true);
3933	if (RT_FAILURE(rc))
3934	return PDMDEV_SET_ERROR(pDevIns, rc,
3935	N_("BusLogic configuration error: failed to read R0Enabled as boolean"));
3936	Log(("%s: fR0Enabled=%d\n", __FUNCTION__, pThis->fR0Enabled));
3937	rc = CFGMR3QueryBoolDef(pCfg, "Bootable", &fBootable, true);
3938	if (RT_FAILURE(rc))
3939	return PDMDEV_SET_ERROR(pDevIns, rc,
3940	N_("BusLogic configuration error: failed to read Bootable as boolean"));
3941	Log(("%s: fBootable=%RTbool\n", __FUNCTION__, fBootable));
3942
3943	/* Only the first instance defaults to having the ISA compatibility ports enabled. */
3944	if (iInstance == 0)
3945	rc = CFGMR3QueryStringDef(pCfg, "ISACompat", achISACompat, sizeof(achISACompat), "Alternate");
3946	else
3947	rc = CFGMR3QueryStringDef(pCfg, "ISACompat", achISACompat, sizeof(achISACompat), "Disabled");
3948	if (RT_FAILURE(rc))
3949	return PDMDEV_SET_ERROR(pDevIns, rc,
3950	N_("BusLogic configuration error: failed to read ISACompat as string"));
3951	Log(("%s: ISACompat=%s\n", __FUNCTION__, achISACompat));
3952
3953	/* Grok the ISACompat setting. */
3954	if (!strcmp(achISACompat, "Disabled"))
3955	pThis->uDefaultISABaseCode = ISA_BASE_DISABLED;
3956	else if (!strcmp(achISACompat, "Primary"))
3957	pThis->uDefaultISABaseCode = 0; /* I/O base at 330h. */
3958	else if (!strcmp(achISACompat, "Alternate"))
3959	pThis->uDefaultISABaseCode = 1; /* I/O base at 334h. */
3960	else
3961	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
3962	N_("BusLogic configuration error: invalid ISACompat setting"));
3963
3964	/*
3965	* Register the PCI device and its I/O regions.
3966	*/
3967	rc = PDMDevHlpPCIRegister(pDevIns, &pThis->dev);
3968	if (RT_FAILURE(rc))
3969	return rc;
3970
3971	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 32, PCI_ADDRESS_SPACE_IO, buslogicR3MmioMap);
3972	if (RT_FAILURE(rc))
3973	return rc;
3974
3975	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 1, 32, PCI_ADDRESS_SPACE_MEM, buslogicR3MmioMap);
3976	if (RT_FAILURE(rc))
3977	return rc;
3978
3979	if (fBootable)
3980	{
3981	/* Register I/O port space for BIOS access. */
3982	rc = PDMDevHlpIOPortRegister(pDevIns, BUSLOGIC_BIOS_IO_PORT, 4, NULL,
3983	buslogicR3BiosIoPortWrite, buslogicR3BiosIoPortRead,
3984	buslogicR3BiosIoPortWriteStr, buslogicR3BiosIoPortReadStr,
3985	"BusLogic BIOS");
3986	if (RT_FAILURE(rc))
3987	return PDMDEV_SET_ERROR(pDevIns, rc, N_("BusLogic cannot register BIOS I/O handlers"));
3988	}
3989
3990	/* Set up the compatibility I/O range. */
3991	rc = buslogicR3RegisterISARange(pThis, pThis->uDefaultISABaseCode);
3992	if (RT_FAILURE(rc))
3993	return PDMDEV_SET_ERROR(pDevIns, rc, N_("BusLogic cannot register ISA I/O handlers"));
3994
3995	/* Initialize task cache. */
3996	rc = RTMemCacheCreate(&pThis->hTaskCache, sizeof(BUSLOGICTASKSTATE), 0, UINT32_MAX,
3997	NULL, NULL, NULL, 0);
3998	if (RT_FAILURE(rc))
3999	return PDMDEV_SET_ERROR(pDevIns, rc,
4000	N_("BusLogic: Failed to initialize task cache\n"));
4001
4002	/* Initialize task queue. */
4003	rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 5, 0,
4004	buslogicR3NotifyQueueConsumer, true, "BusLogicTask", &pThis->pNotifierQueueR3);
4005	if (RT_FAILURE(rc))
4006	return rc;
4007	pThis->pNotifierQueueR0 = PDMQueueR0Ptr(pThis->pNotifierQueueR3);
4008	pThis->pNotifierQueueRC = PDMQueueRCPtr(pThis->pNotifierQueueR3);
4009
4010	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSectIntr, RT_SRC_POS, "BusLogic-Intr#%u", pDevIns->iInstance);
4011	if (RT_FAILURE(rc))
4012	return PDMDEV_SET_ERROR(pDevIns, rc, N_("BusLogic: cannot create critical section"));
4013
4014	/* Initialize per device state. */
4015	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDeviceStates); i++)
4016	{
4017	char szName[24];
4018	PBUSLOGICDEVICE pDevice = &pThis->aDeviceStates[i];
4019
4020	RTStrPrintf(szName, sizeof(szName), "Device%u", i);
4021
4022	/* Initialize static parts of the device. */
4023	pDevice->iLUN = i;
4024	pDevice->pBusLogicR3 = pThis;
4025	pDevice->pBusLogicR0 = PDMINS_2_DATA_R0PTR(pDevIns);
4026	pDevice->pBusLogicRC = PDMINS_2_DATA_RCPTR(pDevIns);
4027	pDevice->Led.u32Magic = PDMLED_MAGIC;
4028	pDevice->IBase.pfnQueryInterface = buslogicR3DeviceQueryInterface;
4029	pDevice->ISCSIPort.pfnSCSIRequestCompleted = buslogicR3DeviceSCSIRequestCompleted;
4030	pDevice->ISCSIPort.pfnQueryDeviceLocation = buslogicR3QueryDeviceLocation;
4031	pDevice->ILed.pfnQueryStatusLed = buslogicR3DeviceQueryStatusLed;
4032
4033	/* Attach SCSI driver. */
4034	rc = PDMDevHlpDriverAttach(pDevIns, pDevice->iLUN, &pDevice->IBase, &pDevice->pDrvBase, szName);
4035	if (RT_SUCCESS(rc))
4036	{
4037	/* Get SCSI connector interface. */
4038	pDevice->pDrvSCSIConnector = PDMIBASE_QUERY_INTERFACE(pDevice->pDrvBase, PDMISCSICONNECTOR);
4039	AssertMsgReturn(pDevice->pDrvSCSIConnector, ("Missing SCSI interface below\n"), VERR_PDM_MISSING_INTERFACE);
4040
4041	pDevice->fPresent = true;
4042	}
4043	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4044	{
4045	pDevice->pDrvBase = NULL;
4046	pDevice->fPresent = false;
4047	rc = VINF_SUCCESS;
4048	Log(("BusLogic: no driver attached to device %s\n", szName));
4049	}
4050	else
4051	{
4052	AssertLogRelMsgFailed(("BusLogic: Failed to attach %s\n", szName));
4053	return rc;
4054	}
4055	}
4056
4057	/*
4058	* Attach status driver (optional).
4059	*/
4060	PPDMIBASE pBase;
4061	rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThis->IBase, &pBase, "Status Port");
4062	if (RT_SUCCESS(rc))
4063	pThis->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
4064	else if (rc != VERR_PDM_NO_ATTACHED_DRIVER)
4065	{
4066	AssertMsgFailed(("Failed to attach to status driver. rc=%Rrc\n", rc));
4067	return PDMDEV_SET_ERROR(pDevIns, rc, N_("BusLogic cannot attach to status driver"));
4068	}
4069
4070	rc = PDMDevHlpSSMRegisterEx(pDevIns, BUSLOGIC_SAVED_STATE_MINOR_VERSION, sizeof(*pThis), NULL,
4071	NULL, buslogicR3LiveExec, NULL,
4072	NULL, buslogicR3SaveExec, NULL,
4073	NULL, buslogicR3LoadExec, buslogicR3LoadDone);
4074	if (RT_FAILURE(rc))
4075	return PDMDEV_SET_ERROR(pDevIns, rc, N_("BusLogic cannot register save state handlers"));
4076
4077	/*
4078	* Register the debugger info callback.
4079	*/
4080	char szTmp[128];
4081	RTStrPrintf(szTmp, sizeof(szTmp), "%s%d", pDevIns->pReg->szName, pDevIns->iInstance);
4082	PDMDevHlpDBGFInfoRegister(pDevIns, szTmp, "BusLogic HBA info", buslogicR3Info);
4083
4084	rc = buslogicR3HwReset(pThis, true);
4085	AssertMsgRC(rc, ("hardware reset of BusLogic host adapter failed rc=%Rrc\n", rc));
4086
4087	return rc;
4088	}
4089
4090	/**
4091	* The device registration structure.
4092	*/
4093	const PDMDEVREG g_DeviceBusLogic =
4094	{
4095	/* u32Version */
4096	PDM_DEVREG_VERSION,
4097	/* szName */
4098	"buslogic",
4099	/* szRCMod */
4100	"VBoxDDGC.gc",
4101	/* szR0Mod */
4102	"VBoxDDR0.r0",
4103	/* pszDescription */
4104	"BusLogic BT-958 SCSI host adapter.\n",
4105	/* fFlags */
4106	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0 \|
4107	PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION \| PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION \|
4108	PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION,
4109	/* fClass */
4110	PDM_DEVREG_CLASS_STORAGE,
4111	/* cMaxInstances */
4112	~0U,
4113	/* cbInstance */
4114	sizeof(BUSLOGIC),
4115	/* pfnConstruct */
4116	buslogicR3Construct,
4117	/* pfnDestruct */
4118	buslogicR3Destruct,
4119	/* pfnRelocate */
4120	buslogicR3Relocate,
4121	/* pfnMemSetup */
4122	NULL,
4123	/* pfnPowerOn */
4124	NULL,
4125	/* pfnReset */
4126	buslogicR3Reset,
4127	/* pfnSuspend */
4128	buslogicR3Suspend,
4129	/* pfnResume */
4130	buslogicR3Resume,
4131	/* pfnAttach */
4132	buslogicR3Attach,
4133	/* pfnDetach */
4134	buslogicR3Detach,
4135	/* pfnQueryInterface. */
4136	NULL,
4137	/* pfnInitComplete */
4138	NULL,
4139	/* pfnPowerOff */
4140	buslogicR3PowerOff,
4141	/* pfnSoftReset */
4142	NULL,
4143	/* u32VersionEnd */
4144	PDM_DEVREG_VERSION
4145	};
4146
4147	#endif /* IN_RING3 */
4148	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Storage/DevBusLogic.cpp@ 52713

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