VirtualBox

source: vbox/trunk/src/VBox/Devices/Storage/DevLsiLogicSCSI.cpp@ 71963

Last change on this file since 71963 was 71775, checked in by vboxsync, 7 years ago

Devices/Storage: Properly account for requests currently waiting for I/O memory when suspending/resuming to avoid hangs upon suspend (devices would not complete suspending because aiting requests would be marked as active but could not complete)

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1/* $Id: DevLsiLogicSCSI.cpp 71775 2018-04-09 14:54:57Z vboxsync $ */
2/** @file
3 * DevLsiLogicSCSI - LsiLogic LSI53c1030 SCSI controller.
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_LSILOGICSCSI
23#include <VBox/vmm/pdmdev.h>
24#include <VBox/vmm/pdmstorageifs.h>
25#include <VBox/vmm/pdmqueue.h>
26#include <VBox/vmm/pdmthread.h>
27#include <VBox/vmm/pdmcritsect.h>
28#include <VBox/scsi.h>
29#include <VBox/sup.h>
30#include <iprt/assert.h>
31#include <iprt/asm.h>
32#include <iprt/string.h>
33#include <iprt/list.h>
34#ifdef IN_RING3
35# include <iprt/memcache.h>
36# include <iprt/mem.h>
37# include <iprt/param.h>
38# include <iprt/uuid.h>
39# include <iprt/time.h>
40#endif
41
42#include "DevLsiLogicSCSI.h"
43#include "VBoxSCSI.h"
44
45#include "VBoxDD.h"
46
47
48/*********************************************************************************************************************************
49* Defined Constants And Macros *
50*********************************************************************************************************************************/
51/** The current saved state version. */
52#define LSILOGIC_SAVED_STATE_VERSION 5
53/** The saved state version used by VirtualBox before the diagnostic
54 * memory access was implemented. */
55#define LSILOGIC_SAVED_STATE_VERSION_PRE_DIAG_MEM 4
56/** The saved state version used by VirtualBox before the doorbell status flag
57 * was changed from bool to a 32bit enum. */
58#define LSILOGIC_SAVED_STATE_VERSION_BOOL_DOORBELL 3
59/** The saved state version used by VirtualBox before SAS support was added. */
60#define LSILOGIC_SAVED_STATE_VERSION_PRE_SAS 2
61/** The saved state version used by VirtualBox 3.0 and earlier. It does not
62 * include the device config part. */
63#define LSILOGIC_SAVED_STATE_VERSION_VBOX_30 1
64
65/** Maximum number of entries in the release log. */
66#define MAX_REL_LOG_ERRORS 1024
67
68#define LSILOGIC_RTGCPHYS_FROM_U32(Hi, Lo) ( (RTGCPHYS)RT_MAKE_U64(Lo, Hi) )
69
70/** Upper number a buffer is freed if it was too big before. */
71#define LSILOGIC_MAX_ALLOC_TOO_MUCH 20
72
73/** Maximum size of the memory regions (prevents teh guest from DOSing the host by
74 * allocating loadds of memory). */
75#define LSILOGIC_MEMORY_REGIONS_MAX (_1M)
76
77
78/*********************************************************************************************************************************
79* Structures and Typedefs *
80*********************************************************************************************************************************/
81
82/** Pointer to the device instance data of the LsiLogic emulation. */
83typedef struct LSILOGICSCSI *PLSILOGICSCSI;
84
85#ifdef IN_RING3
86/**
87 * Memory buffer callback.
88 *
89 * @returns nothing.
90 * @param pThis The LsiLogic controller instance.
91 * @param GCPhys The guest physical address of the memory buffer.
92 * @param pSgBuf The pointer to the host R3 S/G buffer.
93 * @param cbCopy How many bytes to copy between the two buffers.
94 * @param pcbSkip Initially contains the amount of bytes to skip
95 * starting from the guest physical address before
96 * accessing the S/G buffer and start copying data.
97 * On return this contains the remaining amount if
98 * cbCopy < *pcbSkip or 0 otherwise.
99 */
100typedef DECLCALLBACK(void) LSILOGICR3MEMCOPYCALLBACK(PLSILOGICSCSI pThis, RTGCPHYS GCPhys, PRTSGBUF pSgBuf, size_t cbCopy,
101 size_t *pcbSkip);
102/** Pointer to a memory copy buffer callback. */
103typedef LSILOGICR3MEMCOPYCALLBACK *PLSILOGICR3MEMCOPYCALLBACK;
104#endif
105
106/**
107 * Reply data.
108 */
109typedef struct LSILOGICSCSIREPLY
110{
111 /** Lower 32 bits of the reply address in memory. */
112 uint32_t u32HostMFALowAddress;
113 /** Full address of the reply in guest memory. */
114 RTGCPHYS GCPhysReplyAddress;
115 /** Size of the reply. */
116 uint32_t cbReply;
117 /** Different views to the reply depending on the request type. */
118 MptReplyUnion Reply;
119} LSILOGICSCSIREPLY;
120/** Pointer to reply data. */
121typedef LSILOGICSCSIREPLY *PLSILOGICSCSIREPLY;
122
123/**
124 * Memory region of the IOC.
125 */
126typedef struct LSILOGICMEMREGN
127{
128 /** List node. */
129 RTLISTNODE NodeList;
130 /** 32bit address the region starts to describe. */
131 uint32_t u32AddrStart;
132 /** 32bit address the region ends (inclusive). */
133 uint32_t u32AddrEnd;
134 /** Data for this region - variable. */
135 uint32_t au32Data[1];
136} LSILOGICMEMREGN;
137/** Pointer to a memory region. */
138typedef LSILOGICMEMREGN *PLSILOGICMEMREGN;
139
140/**
141 * State of a device attached to the buslogic host adapter.
142 *
143 * @implements PDMIBASE
144 * @implements PDMISCSIPORT
145 * @implements PDMILEDPORTS
146 */
147typedef struct LSILOGICDEVICE
148{
149 /** Pointer to the owning lsilogic device instance. - R3 pointer */
150 R3PTRTYPE(PLSILOGICSCSI) pLsiLogicR3;
151
152 /** LUN of the device. */
153 uint32_t iLUN;
154 /** Number of outstanding tasks on the port. */
155 volatile uint32_t cOutstandingRequests;
156
157#if HC_ARCH_BITS == 64
158 uint32_t Alignment0;
159#endif
160
161 /** Our base interface. */
162 PDMIBASE IBase;
163 /** Media port interface. */
164 PDMIMEDIAPORT IMediaPort;
165 /** Extended media port interface. */
166 PDMIMEDIAEXPORT IMediaExPort;
167 /** Led interface. */
168 PDMILEDPORTS ILed;
169 /** Pointer to the attached driver's base interface. */
170 R3PTRTYPE(PPDMIBASE) pDrvBase;
171 /** Pointer to the attached driver's media interface. */
172 R3PTRTYPE(PPDMIMEDIA) pDrvMedia;
173 /** Pointer to the attached driver's extended media interface. */
174 R3PTRTYPE(PPDMIMEDIAEX) pDrvMediaEx;
175 /** The status LED state for this device. */
176 PDMLED Led;
177
178} LSILOGICDEVICE;
179/** Pointer to a device state. */
180typedef LSILOGICDEVICE *PLSILOGICDEVICE;
181
182/** Pointer to a task state. */
183typedef struct LSILOGICREQ *PLSILOGICREQ;
184
185/**
186 * Device instance data for the emulated SCSI controller.
187 */
188typedef struct LSILOGICSCSI
189{
190 /** PCI device structure. */
191 PDMPCIDEV PciDev;
192 /** Pointer to the device instance. - R3 ptr. */
193 PPDMDEVINSR3 pDevInsR3;
194 /** Pointer to the device instance. - R0 ptr. */
195 PPDMDEVINSR0 pDevInsR0;
196 /** Pointer to the device instance. - RC ptr. */
197 PPDMDEVINSRC pDevInsRC;
198
199 /** Flag whether the GC part of the device is enabled. */
200 bool fGCEnabled;
201 /** Flag whether the R0 part of the device is enabled. */
202 bool fR0Enabled;
203
204 /** The state the controller is currently in. */
205 LSILOGICSTATE enmState;
206 /** Who needs to init the driver to get into operational state. */
207 LSILOGICWHOINIT enmWhoInit;
208 /** Flag whether we are in doorbell function. */
209 LSILOGICDOORBELLSTATE enmDoorbellState;
210 /** Flag whether diagnostic access is enabled. */
211 bool fDiagnosticEnabled;
212 /** Flag whether a notification was send to R3. */
213 bool fNotificationSent;
214 /** Flag whether the guest enabled event notification from the IOC. */
215 bool fEventNotificationEnabled;
216 /** Flag whether the diagnostic address and RW registers are enabled. */
217 bool fDiagRegsEnabled;
218
219 /** Queue to send tasks to R3. - R3 ptr */
220 R3PTRTYPE(PPDMQUEUE) pNotificationQueueR3;
221 /** Queue to send tasks to R3. - R0 ptr */
222 R0PTRTYPE(PPDMQUEUE) pNotificationQueueR0;
223 /** Queue to send tasks to R3. - RC ptr */
224 RCPTRTYPE(PPDMQUEUE) pNotificationQueueRC;
225
226 /** Number of device states allocated. */
227 uint32_t cDeviceStates;
228
229 /** States for attached devices. */
230 R3PTRTYPE(PLSILOGICDEVICE) paDeviceStates;
231#if HC_ARCH_BITS == 32
232 RTR3PTR R3PtrPadding0;
233#endif
234
235 /** Interrupt mask. */
236 volatile uint32_t uInterruptMask;
237 /** Interrupt status register. */
238 volatile uint32_t uInterruptStatus;
239
240 /** Buffer for messages which are passed through the doorbell using the
241 * handshake method. */
242 uint32_t aMessage[sizeof(MptConfigurationRequest)]; /** @todo r=bird: Looks like 4 tims the required size? Please explain in comment if this correct... */
243 /** Actual position in the buffer. */
244 uint32_t iMessage;
245 /** Size of the message which is given in the doorbell message in dwords. */
246 uint32_t cMessage;
247
248 /** Reply buffer.
249 * @note 60 bytes */
250 MptReplyUnion ReplyBuffer;
251 /** Next entry to read. */
252 uint32_t uNextReplyEntryRead;
253 /** Size of the reply in the buffer in 16bit words. */
254 uint32_t cReplySize;
255
256 /** The fault code of the I/O controller if we are in the fault state. */
257 uint16_t u16IOCFaultCode;
258
259 /** I/O port address the device is mapped to. */
260 RTIOPORT IOPortBase;
261 /** MMIO address the device is mapped to. */
262 RTGCPHYS GCPhysMMIOBase;
263
264 /** Upper 32 bits of the message frame address to locate requests in guest memory. */
265 uint32_t u32HostMFAHighAddr;
266 /** Upper 32 bits of the sense buffer address. */
267 uint32_t u32SenseBufferHighAddr;
268 /** Maximum number of devices the driver reported he can handle. */
269 uint8_t cMaxDevices;
270 /** Maximum number of buses the driver reported he can handle. */
271 uint8_t cMaxBuses;
272 /** Current size of reply message frames in the guest. */
273 uint16_t cbReplyFrame;
274
275 /** Next key to write in the sequence to get access
276 * to diagnostic memory. */
277 uint32_t iDiagnosticAccess;
278
279 /** Number entries allocated for the reply queue. */
280 uint32_t cReplyQueueEntries;
281 /** Number entries allocated for the outstanding request queue. */
282 uint32_t cRequestQueueEntries;
283
284
285 /** Critical section protecting the reply post queue. */
286 PDMCRITSECT ReplyPostQueueCritSect;
287 /** Critical section protecting the reply free queue. */
288 PDMCRITSECT ReplyFreeQueueCritSect;
289 /** Critical section protecting the request queue against
290 * concurrent access from the guest. */
291 PDMCRITSECT RequestQueueCritSect;
292 /** Critical section protecting the reply free queue against
293 * concurrent write access from the guest. */
294 PDMCRITSECT ReplyFreeQueueWriteCritSect;
295
296 /** Pointer to the start of the reply free queue - R3. */
297 R3PTRTYPE(volatile uint32_t *) pReplyFreeQueueBaseR3;
298 /** Pointer to the start of the reply post queue - R3. */
299 R3PTRTYPE(volatile uint32_t *) pReplyPostQueueBaseR3;
300 /** Pointer to the start of the request queue - R3. */
301 R3PTRTYPE(volatile uint32_t *) pRequestQueueBaseR3;
302
303 /** Pointer to the start of the reply queue - R0. */
304 R0PTRTYPE(volatile uint32_t *) pReplyFreeQueueBaseR0;
305 /** Pointer to the start of the reply queue - R0. */
306 R0PTRTYPE(volatile uint32_t *) pReplyPostQueueBaseR0;
307 /** Pointer to the start of the request queue - R0. */
308 R0PTRTYPE(volatile uint32_t *) pRequestQueueBaseR0;
309
310 /** Pointer to the start of the reply queue - RC. */
311 RCPTRTYPE(volatile uint32_t *) pReplyFreeQueueBaseRC;
312 /** Pointer to the start of the reply queue - RC. */
313 RCPTRTYPE(volatile uint32_t *) pReplyPostQueueBaseRC;
314 /** Pointer to the start of the request queue - RC. */
315 RCPTRTYPE(volatile uint32_t *) pRequestQueueBaseRC;
316 /** End these RC pointers on a 64-bit boundrary. */
317 RTRCPTR RCPtrPadding1;
318
319 /** Next free entry in the reply queue the guest can write a address to. */
320 volatile uint32_t uReplyFreeQueueNextEntryFreeWrite;
321 /** Next valid entry the controller can read a valid address for reply frames from. */
322 volatile uint32_t uReplyFreeQueueNextAddressRead;
323
324 /** Next free entry in the reply queue the guest can write a address to. */
325 volatile uint32_t uReplyPostQueueNextEntryFreeWrite;
326 /** Next valid entry the controller can read a valid address for reply frames from. */
327 volatile uint32_t uReplyPostQueueNextAddressRead;
328
329 /** Next free entry the guest can write a address to a request frame to. */
330 volatile uint32_t uRequestQueueNextEntryFreeWrite;
331 /** Next valid entry the controller can read a valid address for request frames from. */
332 volatile uint32_t uRequestQueueNextAddressRead;
333
334 /** Emulated controller type */
335 LSILOGICCTRLTYPE enmCtrlType;
336 /** Handle counter */
337 uint16_t u16NextHandle;
338
339 /** Number of ports this controller has. */
340 uint8_t cPorts;
341
342 /** BIOS emulation. */
343 VBOXSCSI VBoxSCSI;
344
345 /** Status LUN: The base interface. */
346 PDMIBASE IBase;
347 /** Status LUN: Leds interface. */
348 PDMILEDPORTS ILeds;
349 /** Status LUN: Partner of ILeds. */
350 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
351 /** Status LUN: Media Notifys. */
352 R3PTRTYPE(PPDMIMEDIANOTIFY) pMediaNotify;
353 /** Pointer to the configuration page area. */
354 R3PTRTYPE(PMptConfigurationPagesSupported) pConfigurationPages;
355
356 /** Indicates that PDMDevHlpAsyncNotificationCompleted should be called when
357 * a port is entering the idle state. */
358 bool volatile fSignalIdle;
359 /** Flag whether we have tasks which need to be processed again- */
360 bool volatile fRedo;
361 /** Flag whether the worker thread is sleeping. */
362 volatile bool fWrkThreadSleeping;
363 /** Flag whether a request from the BIOS is pending which the
364 * worker thread needs to process. */
365 volatile bool fBiosReqPending;
366#if HC_ARCH_BITS == 64
367 /** Alignment padding. */
368 bool afPadding2[4];
369#endif
370 /** List of tasks which can be redone. */
371 R3PTRTYPE(volatile PLSILOGICREQ) pTasksRedoHead;
372
373 /** Current address to read from or write to in the diagnostic memory region. */
374 uint32_t u32DiagMemAddr;
375 /** Current size of the memory regions. */
376 uint32_t cbMemRegns;
377
378#if HC_ARCH_BITS ==32
379 uint32_t u32Padding3;
380#endif
381
382 union
383 {
384 /** List of memory regions - PLSILOGICMEMREGN. */
385 RTLISTANCHOR ListMemRegns;
386 uint8_t u8Padding[2 * sizeof(RTUINTPTR)];
387 };
388
389 /** The support driver session handle. */
390 R3R0PTRTYPE(PSUPDRVSESSION) pSupDrvSession;
391 /** Worker thread. */
392 R3PTRTYPE(PPDMTHREAD) pThreadWrk;
393 /** The event semaphore the processing thread waits on. */
394 SUPSEMEVENT hEvtProcess;
395
396} LSILOGISCSI;
397
398/**
399 * Task state object which holds all necessary data while
400 * processing the request from the guest.
401 */
402typedef struct LSILOGICREQ
403{
404 /** I/O request handle. */
405 PDMMEDIAEXIOREQ hIoReq;
406 /** Next in the redo list. */
407 PLSILOGICREQ pRedoNext;
408 /** Target device. */
409 PLSILOGICDEVICE pTargetDevice;
410 /** The message request from the guest. */
411 MptRequestUnion GuestRequest;
412 /** Address of the message request frame in guests memory.
413 * Used to read the S/G entries in the second step. */
414 RTGCPHYS GCPhysMessageFrameAddr;
415 /** Physical start address of the S/G list. */
416 RTGCPHYS GCPhysSgStart;
417 /** Chain offset */
418 uint32_t cChainOffset;
419 /** Pointer to the sense buffer. */
420 uint8_t abSenseBuffer[18];
421 /** Flag whether the request was issued from the BIOS. */
422 bool fBIOS;
423 /** SCSI status code. */
424 uint8_t u8ScsiSts;
425} LSILOGICREQ;
426
427
428#ifndef VBOX_DEVICE_STRUCT_TESTCASE
429
430
431/*********************************************************************************************************************************
432* Internal Functions *
433*********************************************************************************************************************************/
434RT_C_DECLS_BEGIN
435#ifdef IN_RING3
436static void lsilogicR3InitializeConfigurationPages(PLSILOGICSCSI pThis);
437static void lsilogicR3ConfigurationPagesFree(PLSILOGICSCSI pThis);
438static int lsilogicR3ProcessConfigurationRequest(PLSILOGICSCSI pThis, PMptConfigurationRequest pConfigurationReq,
439 PMptConfigurationReply pReply);
440#endif
441RT_C_DECLS_END
442
443
444/*********************************************************************************************************************************
445* Global Variables *
446*********************************************************************************************************************************/
447/** Key sequence the guest has to write to enable access
448 * to diagnostic memory. */
449static const uint8_t g_lsilogicDiagnosticAccess[] = {0x04, 0x0b, 0x02, 0x07, 0x0d};
450
451/**
452 * Updates the status of the interrupt pin of the device.
453 *
454 * @returns nothing.
455 * @param pThis Pointer to the LsiLogic device state.
456 */
457static void lsilogicUpdateInterrupt(PLSILOGICSCSI pThis)
458{
459 uint32_t uIntSts;
460
461 LogFlowFunc(("Updating interrupts\n"));
462
463 /* Mask out doorbell status so that it does not affect interrupt updating. */
464 uIntSts = (ASMAtomicReadU32(&pThis->uInterruptStatus) & ~LSILOGIC_REG_HOST_INTR_STATUS_DOORBELL_STS);
465 /* Check maskable interrupts. */
466 uIntSts &= ~(ASMAtomicReadU32(&pThis->uInterruptMask) & ~LSILOGIC_REG_HOST_INTR_MASK_IRQ_ROUTING);
467
468 if (uIntSts)
469 {
470 LogFlowFunc(("Setting interrupt\n"));
471 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, 1);
472 }
473 else
474 {
475 LogFlowFunc(("Clearing interrupt\n"));
476 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, 0);
477 }
478}
479
480/**
481 * Sets a given interrupt status bit in the status register and
482 * updates the interrupt status.
483 *
484 * @returns nothing.
485 * @param pThis Pointer to the LsiLogic device state.
486 * @param uStatus The status bit to set.
487 */
488DECLINLINE(void) lsilogicSetInterrupt(PLSILOGICSCSI pThis, uint32_t uStatus)
489{
490 ASMAtomicOrU32(&pThis->uInterruptStatus, uStatus);
491 lsilogicUpdateInterrupt(pThis);
492}
493
494/**
495 * Clears a given interrupt status bit in the status register and
496 * updates the interrupt status.
497 *
498 * @returns nothing.
499 * @param pThis Pointer to the LsiLogic device state.
500 * @param uStatus The status bit to set.
501 */
502DECLINLINE(void) lsilogicClearInterrupt(PLSILOGICSCSI pThis, uint32_t uStatus)
503{
504 ASMAtomicAndU32(&pThis->uInterruptStatus, ~uStatus);
505 lsilogicUpdateInterrupt(pThis);
506}
507
508
509#ifdef IN_RING3
510/**
511 * Sets the I/O controller into fault state and sets the fault code.
512 *
513 * @returns nothing
514 * @param pThis Pointer to the LsiLogic device state.
515 * @param uIOCFaultCode Fault code to set.
516 */
517DECLINLINE(void) lsilogicSetIOCFaultCode(PLSILOGICSCSI pThis, uint16_t uIOCFaultCode)
518{
519 if (pThis->enmState != LSILOGICSTATE_FAULT)
520 {
521 LogFunc(("Setting I/O controller into FAULT state: uIOCFaultCode=%u\n", uIOCFaultCode));
522 pThis->enmState = LSILOGICSTATE_FAULT;
523 pThis->u16IOCFaultCode = uIOCFaultCode;
524 }
525 else
526 LogFunc(("We are already in FAULT state\n"));
527}
528#endif /* IN_RING3 */
529
530
531/**
532 * Returns the number of frames in the reply free queue.
533 *
534 * @returns Number of frames in the reply free queue.
535 * @param pThis Pointer to the LsiLogic device state.
536 */
537DECLINLINE(uint32_t) lsilogicReplyFreeQueueGetFrameCount(PLSILOGICSCSI pThis)
538{
539 uint32_t cReplyFrames = 0;
540
541 if (pThis->uReplyFreeQueueNextAddressRead <= pThis->uReplyFreeQueueNextEntryFreeWrite)
542 cReplyFrames = pThis->uReplyFreeQueueNextEntryFreeWrite - pThis->uReplyFreeQueueNextAddressRead;
543 else
544 cReplyFrames = pThis->cReplyQueueEntries - pThis->uReplyFreeQueueNextAddressRead + pThis->uReplyFreeQueueNextEntryFreeWrite;
545
546 return cReplyFrames;
547}
548
549#ifdef IN_RING3
550
551/**
552 * Returns the number of free entries in the reply post queue.
553 *
554 * @returns Number of frames in the reply free queue.
555 * @param pThis Pointer to the LsiLogic device state.
556 */
557DECLINLINE(uint32_t) lsilogicReplyPostQueueGetFrameCount(PLSILOGICSCSI pThis)
558{
559 uint32_t cReplyFrames = 0;
560
561 if (pThis->uReplyPostQueueNextAddressRead <= pThis->uReplyPostQueueNextEntryFreeWrite)
562 cReplyFrames = pThis->cReplyQueueEntries - pThis->uReplyPostQueueNextEntryFreeWrite + pThis->uReplyPostQueueNextAddressRead;
563 else
564 cReplyFrames = pThis->uReplyPostQueueNextEntryFreeWrite - pThis->uReplyPostQueueNextAddressRead;
565
566 return cReplyFrames;
567}
568
569
570/**
571 * Performs a hard reset on the controller.
572 *
573 * @returns VBox status code.
574 * @param pThis Pointer to the LsiLogic device state.
575 */
576static int lsilogicR3HardReset(PLSILOGICSCSI pThis)
577{
578 pThis->enmState = LSILOGICSTATE_RESET;
579 pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_NOT_IN_USE;
580
581 /* The interrupts are masked out. */
582 pThis->uInterruptMask |= LSILOGIC_REG_HOST_INTR_MASK_DOORBELL
583 | LSILOGIC_REG_HOST_INTR_MASK_REPLY;
584 /* Reset interrupt states. */
585 pThis->uInterruptStatus = 0;
586 lsilogicUpdateInterrupt(pThis);
587
588 /* Reset the queues. */
589 pThis->uReplyFreeQueueNextEntryFreeWrite = 0;
590 pThis->uReplyFreeQueueNextAddressRead = 0;
591 pThis->uReplyPostQueueNextEntryFreeWrite = 0;
592 pThis->uReplyPostQueueNextAddressRead = 0;
593 pThis->uRequestQueueNextEntryFreeWrite = 0;
594 pThis->uRequestQueueNextAddressRead = 0;
595
596 /* Disable diagnostic access. */
597 pThis->iDiagnosticAccess = 0;
598 pThis->fDiagnosticEnabled = false;
599 pThis->fDiagRegsEnabled = false;
600
601 /* Set default values. */
602 pThis->cMaxDevices = pThis->cDeviceStates;
603 pThis->cMaxBuses = 1;
604 pThis->cbReplyFrame = 128; /** @todo Figure out where it is needed. */
605 pThis->u16NextHandle = 1;
606 pThis->u32DiagMemAddr = 0;
607
608 lsilogicR3ConfigurationPagesFree(pThis);
609 lsilogicR3InitializeConfigurationPages(pThis);
610
611 /* Mark that we finished performing the reset. */
612 pThis->enmState = LSILOGICSTATE_READY;
613 return VINF_SUCCESS;
614}
615
616/**
617 * Frees the configuration pages if allocated.
618 *
619 * @returns nothing.
620 * @param pThis The LsiLogic controller instance
621 */
622static void lsilogicR3ConfigurationPagesFree(PLSILOGICSCSI pThis)
623{
624
625 if (pThis->pConfigurationPages)
626 {
627 /* Destroy device list if we emulate a SAS controller. */
628 if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
629 {
630 PMptConfigurationPagesSas pSasPages = &pThis->pConfigurationPages->u.SasPages;
631 PMptSASDevice pSASDeviceCurr = pSasPages->pSASDeviceHead;
632
633 while (pSASDeviceCurr)
634 {
635 PMptSASDevice pFree = pSASDeviceCurr;
636
637 pSASDeviceCurr = pSASDeviceCurr->pNext;
638 RTMemFree(pFree);
639 }
640 if (pSasPages->paPHYs)
641 RTMemFree(pSasPages->paPHYs);
642 if (pSasPages->pManufacturingPage7)
643 RTMemFree(pSasPages->pManufacturingPage7);
644 if (pSasPages->pSASIOUnitPage0)
645 RTMemFree(pSasPages->pSASIOUnitPage0);
646 if (pSasPages->pSASIOUnitPage1)
647 RTMemFree(pSasPages->pSASIOUnitPage1);
648 }
649
650 RTMemFree(pThis->pConfigurationPages);
651 }
652}
653
654/**
655 * Finishes a context reply.
656 *
657 * @returns nothing
658 * @param pThis Pointer to the LsiLogic device state.
659 * @param u32MessageContext The message context ID to post.
660 */
661static void lsilogicR3FinishContextReply(PLSILOGICSCSI pThis, uint32_t u32MessageContext)
662{
663 int rc;
664
665 LogFlowFunc(("pThis=%#p u32MessageContext=%#x\n", pThis, u32MessageContext));
666
667 AssertMsg(pThis->enmDoorbellState == LSILOGICDOORBELLSTATE_NOT_IN_USE, ("We are in a doorbell function\n"));
668
669 /* Write message context ID into reply post queue. */
670 rc = PDMCritSectEnter(&pThis->ReplyPostQueueCritSect, VINF_SUCCESS);
671 AssertRC(rc);
672
673 /* Check for a entry in the queue. */
674 if (!lsilogicReplyPostQueueGetFrameCount(pThis))
675 {
676 /* Set error code. */
677 lsilogicSetIOCFaultCode(pThis, LSILOGIC_IOCSTATUS_INSUFFICIENT_RESOURCES);
678 PDMCritSectLeave(&pThis->ReplyPostQueueCritSect);
679 return;
680 }
681
682 /* We have a context reply. */
683 ASMAtomicWriteU32(&pThis->CTX_SUFF(pReplyPostQueueBase)[pThis->uReplyPostQueueNextEntryFreeWrite], u32MessageContext);
684 ASMAtomicIncU32(&pThis->uReplyPostQueueNextEntryFreeWrite);
685 pThis->uReplyPostQueueNextEntryFreeWrite %= pThis->cReplyQueueEntries;
686
687 /* Set interrupt. */
688 lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_REPLY_INTR);
689
690 PDMCritSectLeave(&pThis->ReplyPostQueueCritSect);
691}
692
693
694/**
695 * Takes necessary steps to finish a reply frame.
696 *
697 * @returns nothing
698 * @param pThis Pointer to the LsiLogic device state.
699 * @param pReply Pointer to the reply message.
700 * @param fForceReplyFifo Flag whether the use of the reply post fifo is forced.
701 */
702static void lsilogicFinishAddressReply(PLSILOGICSCSI pThis, PMptReplyUnion pReply, bool fForceReplyFifo)
703{
704 /*
705 * If we are in a doorbell function we set the reply size now and
706 * set the system doorbell status interrupt to notify the guest that
707 * we are ready to send the reply.
708 */
709 if (pThis->enmDoorbellState != LSILOGICDOORBELLSTATE_NOT_IN_USE && !fForceReplyFifo)
710 {
711 /* Set size of the reply in 16bit words. The size in the reply is in 32bit dwords. */
712 pThis->cReplySize = pReply->Header.u8MessageLength * 2;
713 Log(("%s: cReplySize=%u\n", __FUNCTION__, pThis->cReplySize));
714 pThis->uNextReplyEntryRead = 0;
715 lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
716 }
717 else
718 {
719 /*
720 * The reply queues are only used if the request was fetched from the request queue.
721 * Requests from the request queue are always transferred to R3. So it is not possible
722 * that this case happens in R0 or GC.
723 */
724# ifdef IN_RING3
725 int rc;
726 /* Grab a free reply message from the queue. */
727 rc = PDMCritSectEnter(&pThis->ReplyFreeQueueCritSect, VINF_SUCCESS);
728 AssertRC(rc);
729
730 /* Check for a free reply frame. */
731 if (!lsilogicReplyFreeQueueGetFrameCount(pThis))
732 {
733 /* Set error code. */
734 lsilogicSetIOCFaultCode(pThis, LSILOGIC_IOCSTATUS_INSUFFICIENT_RESOURCES);
735 PDMCritSectLeave(&pThis->ReplyFreeQueueCritSect);
736 return;
737 }
738
739 uint32_t u32ReplyFrameAddressLow = pThis->CTX_SUFF(pReplyFreeQueueBase)[pThis->uReplyFreeQueueNextAddressRead];
740
741 pThis->uReplyFreeQueueNextAddressRead++;
742 pThis->uReplyFreeQueueNextAddressRead %= pThis->cReplyQueueEntries;
743
744 PDMCritSectLeave(&pThis->ReplyFreeQueueCritSect);
745
746 /* Build 64bit physical address. */
747 RTGCPHYS GCPhysReplyMessage = LSILOGIC_RTGCPHYS_FROM_U32(pThis->u32HostMFAHighAddr, u32ReplyFrameAddressLow);
748 size_t cbReplyCopied = (pThis->cbReplyFrame < sizeof(MptReplyUnion)) ? pThis->cbReplyFrame : sizeof(MptReplyUnion);
749
750 /* Write reply to guest memory. */
751 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhysReplyMessage, pReply, cbReplyCopied);
752
753 /* Write low 32bits of reply frame into post reply queue. */
754 rc = PDMCritSectEnter(&pThis->ReplyPostQueueCritSect, VINF_SUCCESS);
755 AssertRC(rc);
756
757 /* Check for a entry in the queue. */
758 if (!lsilogicReplyPostQueueGetFrameCount(pThis))
759 {
760 /* Set error code. */
761 lsilogicSetIOCFaultCode(pThis, LSILOGIC_IOCSTATUS_INSUFFICIENT_RESOURCES);
762 PDMCritSectLeave(&pThis->ReplyPostQueueCritSect);
763 return;
764 }
765
766 /* We have a address reply. Set the 31th bit to indicate that. */
767 ASMAtomicWriteU32(&pThis->CTX_SUFF(pReplyPostQueueBase)[pThis->uReplyPostQueueNextEntryFreeWrite],
768 RT_BIT(31) | (u32ReplyFrameAddressLow >> 1));
769 ASMAtomicIncU32(&pThis->uReplyPostQueueNextEntryFreeWrite);
770 pThis->uReplyPostQueueNextEntryFreeWrite %= pThis->cReplyQueueEntries;
771
772 if (fForceReplyFifo)
773 {
774 pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_NOT_IN_USE;
775 lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
776 }
777
778 /* Set interrupt. */
779 lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_REPLY_INTR);
780
781 PDMCritSectLeave(&pThis->ReplyPostQueueCritSect);
782# else
783 AssertMsgFailed(("This is not allowed to happen.\n"));
784# endif
785 }
786}
787
788
789/**
790 * Tries to find a memory region which covers the given address.
791 *
792 * @returns Pointer to memory region or NULL if not found.
793 * @param pThis Pointer to the LsiLogic device state.
794 * @param u32Addr The 32bit address to search for.
795 */
796static PLSILOGICMEMREGN lsilogicR3MemRegionFindByAddr(PLSILOGICSCSI pThis, uint32_t u32Addr)
797{
798 PLSILOGICMEMREGN pRegion = NULL;
799
800 PLSILOGICMEMREGN pIt;
801 RTListForEach(&pThis->ListMemRegns, pIt, LSILOGICMEMREGN, NodeList)
802 {
803 if ( u32Addr >= pIt->u32AddrStart
804 && u32Addr <= pIt->u32AddrEnd)
805 {
806 pRegion = pIt;
807 break;
808 }
809 }
810
811 return pRegion;
812}
813
814/**
815 * Frees all allocated memory regions.
816 *
817 * @returns nothing.
818 * @param pThis Pointer to the LsiLogic device state.
819 */
820static void lsilogicR3MemRegionsFree(PLSILOGICSCSI pThis)
821{
822 PLSILOGICMEMREGN pItNext;
823
824 PLSILOGICMEMREGN pIt;
825 RTListForEachSafe(&pThis->ListMemRegns, pIt, pItNext, LSILOGICMEMREGN, NodeList)
826 {
827 RTListNodeRemove(&pIt->NodeList);
828 RTMemFree(pIt);
829 }
830 pThis->cbMemRegns = 0;
831}
832
833/**
834 * Inserts a given memory region into the list.
835 *
836 * @returns nothing.
837 * @param pThis Pointer to the LsiLogic device state.
838 * @param pRegion The region to insert.
839 */
840static void lsilogicR3MemRegionInsert(PLSILOGICSCSI pThis, PLSILOGICMEMREGN pRegion)
841{
842 bool fInserted = false;
843
844 /* Insert at the right position. */
845 PLSILOGICMEMREGN pIt;
846 RTListForEach(&pThis->ListMemRegns, pIt, LSILOGICMEMREGN, NodeList)
847 {
848 if (pRegion->u32AddrEnd < pIt->u32AddrStart)
849 {
850 RTListNodeInsertBefore(&pIt->NodeList, &pRegion->NodeList);
851 fInserted = true;
852 break;
853 }
854 }
855 if (!fInserted)
856 RTListAppend(&pThis->ListMemRegns, &pRegion->NodeList);
857}
858
859/**
860 * Count number of memory regions.
861 *
862 * @returns Number of memory regions.
863 * @param pThis Pointer to the LsiLogic device state.
864 */
865static uint32_t lsilogicR3MemRegionsCount(PLSILOGICSCSI pThis)
866{
867 uint32_t cRegions = 0;
868
869 PLSILOGICMEMREGN pIt;
870 RTListForEach(&pThis->ListMemRegns, pIt, LSILOGICMEMREGN, NodeList)
871 {
872 cRegions++;
873 }
874
875 return cRegions;
876}
877
878/**
879 * Handles a write to the diagnostic data register.
880 *
881 * @returns nothing.
882 * @param pThis Pointer to the LsiLogic device state.
883 * @param u32Data Data to write.
884 */
885static void lsilogicR3DiagRegDataWrite(PLSILOGICSCSI pThis, uint32_t u32Data)
886{
887 PLSILOGICMEMREGN pRegion = lsilogicR3MemRegionFindByAddr(pThis, pThis->u32DiagMemAddr);
888
889 if (pRegion)
890 {
891 uint32_t offRegion = pThis->u32DiagMemAddr - pRegion->u32AddrStart;
892
893 AssertMsg( offRegion % 4 == 0
894 && pThis->u32DiagMemAddr <= pRegion->u32AddrEnd,
895 ("Region offset not on a word boundary or crosses memory region\n"));
896
897 offRegion /= 4;
898 pRegion->au32Data[offRegion] = u32Data;
899 }
900 else
901 {
902 pRegion = NULL;
903
904 /* Create new region, first check whether we can extend another region. */
905 PLSILOGICMEMREGN pIt;
906 RTListForEach(&pThis->ListMemRegns, pIt, LSILOGICMEMREGN, NodeList)
907 {
908 if (pThis->u32DiagMemAddr == pIt->u32AddrEnd + sizeof(uint32_t))
909 {
910 pRegion = pIt;
911 break;
912 }
913 }
914
915 if (pRegion)
916 {
917 /* Reallocate. */
918 RTListNodeRemove(&pRegion->NodeList);
919
920 uint32_t cRegionSizeOld = (pRegion->u32AddrEnd - pRegion->u32AddrStart) / 4 + 1;
921 uint32_t cRegionSizeNew = cRegionSizeOld + 512;
922
923 if (pThis->cbMemRegns + 512 * sizeof(uint32_t) < LSILOGIC_MEMORY_REGIONS_MAX)
924 {
925 PLSILOGICMEMREGN pRegionNew = (PLSILOGICMEMREGN)RTMemRealloc(pRegion, RT_OFFSETOF(LSILOGICMEMREGN, au32Data[cRegionSizeNew]));
926
927 if (pRegionNew)
928 {
929 pRegion = pRegionNew;
930 memset(&pRegion->au32Data[cRegionSizeOld], 0, 512 * sizeof(uint32_t));
931 pRegion->au32Data[cRegionSizeOld] = u32Data;
932 pRegion->u32AddrEnd = pRegion->u32AddrStart + (cRegionSizeNew - 1) * sizeof(uint32_t);
933 pThis->cbMemRegns += 512 * sizeof(uint32_t);
934 }
935 /* else: Silently fail, there is nothing we can do here and the guest might work nevertheless. */
936
937 lsilogicR3MemRegionInsert(pThis, pRegion);
938 }
939 }
940 else
941 {
942 if (pThis->cbMemRegns + 512 * sizeof(uint32_t) < LSILOGIC_MEMORY_REGIONS_MAX)
943 {
944 /* Create completely new. */
945 pRegion = (PLSILOGICMEMREGN)RTMemAllocZ(RT_OFFSETOF(LSILOGICMEMREGN, au32Data[512]));
946 if (pRegion)
947 {
948 pRegion->u32AddrStart = pThis->u32DiagMemAddr;
949 pRegion->u32AddrEnd = pRegion->u32AddrStart + (512 - 1) * sizeof(uint32_t);
950 pRegion->au32Data[0] = u32Data;
951 pThis->cbMemRegns += 512 * sizeof(uint32_t);
952
953 lsilogicR3MemRegionInsert(pThis, pRegion);
954 }
955 /* else: Silently fail, there is nothing we can do here and the guest might work nevertheless. */
956 }
957 }
958
959 }
960
961 /* Memory access is always 32bit big. */
962 pThis->u32DiagMemAddr += sizeof(uint32_t);
963}
964
965/**
966 * Handles a read from the diagnostic data register.
967 *
968 * @returns nothing.
969 * @param pThis Pointer to the LsiLogic device state.
970 * @param pu32Data Where to store the data.
971 */
972static void lsilogicR3DiagRegDataRead(PLSILOGICSCSI pThis, uint32_t *pu32Data)
973{
974 PLSILOGICMEMREGN pRegion = lsilogicR3MemRegionFindByAddr(pThis, pThis->u32DiagMemAddr);
975
976 if (pRegion)
977 {
978 uint32_t offRegion = pThis->u32DiagMemAddr - pRegion->u32AddrStart;
979
980 AssertMsg( offRegion % 4 == 0
981 && pThis->u32DiagMemAddr <= pRegion->u32AddrEnd,
982 ("Region offset not on a word boundary or crosses memory region\n"));
983
984 offRegion /= 4;
985 *pu32Data = pRegion->au32Data[offRegion];
986 }
987 else /* No region, default value 0. */
988 *pu32Data = 0;
989
990 /* Memory access is always 32bit big. */
991 pThis->u32DiagMemAddr += sizeof(uint32_t);
992}
993
994/**
995 * Handles a write to the diagnostic memory address register.
996 *
997 * @returns nothing.
998 * @param pThis Pointer to the LsiLogic device state.
999 * @param u32Addr Address to write.
1000 */
1001static void lsilogicR3DiagRegAddressWrite(PLSILOGICSCSI pThis, uint32_t u32Addr)
1002{
1003 pThis->u32DiagMemAddr = u32Addr & ~UINT32_C(0x3); /* 32bit alignment. */
1004}
1005
1006/**
1007 * Handles a read from the diagnostic memory address register.
1008 *
1009 * @returns nothing.
1010 * @param pThis Pointer to the LsiLogic device state.
1011 * @param pu32Addr Where to store the current address.
1012 */
1013static void lsilogicR3DiagRegAddressRead(PLSILOGICSCSI pThis, uint32_t *pu32Addr)
1014{
1015 *pu32Addr = pThis->u32DiagMemAddr;
1016}
1017
1018/**
1019 * Processes a given Request from the guest
1020 *
1021 * @returns VBox status code.
1022 * @param pThis Pointer to the LsiLogic device state.
1023 * @param pMessageHdr Pointer to the message header of the request.
1024 * @param pReply Pointer to the reply.
1025 */
1026static int lsilogicR3ProcessMessageRequest(PLSILOGICSCSI pThis, PMptMessageHdr pMessageHdr, PMptReplyUnion pReply)
1027{
1028 int rc = VINF_SUCCESS;
1029 bool fForceReplyPostFifo = false;
1030
1031# ifdef LOG_ENABLED
1032 if (pMessageHdr->u8Function < RT_ELEMENTS(g_apszMPTFunctionNames))
1033 Log(("Message request function: %s\n", g_apszMPTFunctionNames[pMessageHdr->u8Function]));
1034 else
1035 Log(("Message request function: <unknown>\n"));
1036# endif
1037
1038 memset(pReply, 0, sizeof(MptReplyUnion));
1039
1040 switch (pMessageHdr->u8Function)
1041 {
1042 case MPT_MESSAGE_HDR_FUNCTION_SCSI_TASK_MGMT:
1043 {
1044 PMptSCSITaskManagementRequest pTaskMgmtReq = (PMptSCSITaskManagementRequest)pMessageHdr;
1045
1046 LogFlow(("u8TaskType=%u\n", pTaskMgmtReq->u8TaskType));
1047 LogFlow(("u32TaskMessageContext=%#x\n", pTaskMgmtReq->u32TaskMessageContext));
1048
1049 pReply->SCSITaskManagement.u8MessageLength = 6; /* 6 32bit dwords. */
1050 pReply->SCSITaskManagement.u8TaskType = pTaskMgmtReq->u8TaskType;
1051 pReply->SCSITaskManagement.u32TerminationCount = 0;
1052 fForceReplyPostFifo = true;
1053 break;
1054 }
1055 case MPT_MESSAGE_HDR_FUNCTION_IOC_INIT:
1056 {
1057 /*
1058 * This request sets the I/O controller to the
1059 * operational state.
1060 */
1061 PMptIOCInitRequest pIOCInitReq = (PMptIOCInitRequest)pMessageHdr;
1062
1063 /* Update configuration values. */
1064 pThis->enmWhoInit = (LSILOGICWHOINIT)pIOCInitReq->u8WhoInit;
1065 pThis->cbReplyFrame = pIOCInitReq->u16ReplyFrameSize;
1066 pThis->cMaxBuses = pIOCInitReq->u8MaxBuses;
1067 pThis->cMaxDevices = pIOCInitReq->u8MaxDevices;
1068 pThis->u32HostMFAHighAddr = pIOCInitReq->u32HostMfaHighAddr;
1069 pThis->u32SenseBufferHighAddr = pIOCInitReq->u32SenseBufferHighAddr;
1070
1071 if (pThis->enmState == LSILOGICSTATE_READY)
1072 {
1073 pThis->enmState = LSILOGICSTATE_OPERATIONAL;
1074 }
1075
1076 /* Return reply. */
1077 pReply->IOCInit.u8MessageLength = 5;
1078 pReply->IOCInit.u8WhoInit = pThis->enmWhoInit;
1079 pReply->IOCInit.u8MaxDevices = pThis->cMaxDevices;
1080 pReply->IOCInit.u8MaxBuses = pThis->cMaxBuses;
1081 break;
1082 }
1083 case MPT_MESSAGE_HDR_FUNCTION_IOC_FACTS:
1084 {
1085 pReply->IOCFacts.u8MessageLength = 15; /* 15 32bit dwords. */
1086
1087 if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
1088 {
1089 pReply->IOCFacts.u16MessageVersion = 0x0102; /* Version from the specification. */
1090 pReply->IOCFacts.u8NumberOfPorts = pThis->cPorts;
1091 }
1092 else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
1093 {
1094 pReply->IOCFacts.u16MessageVersion = 0x0105; /* Version from the specification. */
1095 pReply->IOCFacts.u8NumberOfPorts = pThis->cPorts;
1096 }
1097 else
1098 AssertMsgFailed(("Invalid controller type %d\n", pThis->enmCtrlType));
1099
1100 pReply->IOCFacts.u8IOCNumber = 0; /* PCI function number. */
1101 pReply->IOCFacts.u16IOCExceptions = 0;
1102 pReply->IOCFacts.u8MaxChainDepth = LSILOGICSCSI_MAXIMUM_CHAIN_DEPTH;
1103 pReply->IOCFacts.u8WhoInit = pThis->enmWhoInit;
1104 pReply->IOCFacts.u8BlockSize = 12; /* Block size in 32bit dwords. This is the largest request we can get (SCSI I/O). */
1105 pReply->IOCFacts.u8Flags = 0; /* Bit 0 is set if the guest must upload the FW prior to using the controller. Obviously not needed here. */
1106 pReply->IOCFacts.u16ReplyQueueDepth = pThis->cReplyQueueEntries - 1; /* One entry is always free. */
1107 pReply->IOCFacts.u16RequestFrameSize = 128; /** @todo Figure out where it is needed. */
1108 pReply->IOCFacts.u32CurrentHostMFAHighAddr = pThis->u32HostMFAHighAddr;
1109 pReply->IOCFacts.u16GlobalCredits = pThis->cRequestQueueEntries - 1; /* One entry is always free. */
1110
1111 pReply->IOCFacts.u8EventState = 0; /* Event notifications not enabled. */
1112 pReply->IOCFacts.u32CurrentSenseBufferHighAddr = pThis->u32SenseBufferHighAddr;
1113 pReply->IOCFacts.u16CurReplyFrameSize = pThis->cbReplyFrame;
1114 pReply->IOCFacts.u8MaxDevices = pThis->cMaxDevices;
1115 pReply->IOCFacts.u8MaxBuses = pThis->cMaxBuses;
1116
1117 /* Check for a valid firmware image in the IOC memory which was downlaoded by tzhe guest earlier. */
1118 PLSILOGICMEMREGN pRegion = lsilogicR3MemRegionFindByAddr(pThis, LSILOGIC_FWIMGHDR_LOAD_ADDRESS);
1119
1120 if (pRegion)
1121 {
1122 uint32_t offImgHdr = (LSILOGIC_FWIMGHDR_LOAD_ADDRESS - pRegion->u32AddrStart) / 4;
1123 PFwImageHdr pFwImgHdr = (PFwImageHdr)&pRegion->au32Data[offImgHdr];
1124
1125 /* Check for the signature. */
1126 /** @todo Checksum validation. */
1127 if ( pFwImgHdr->u32Signature1 == LSILOGIC_FWIMGHDR_SIGNATURE1
1128 && pFwImgHdr->u32Signature2 == LSILOGIC_FWIMGHDR_SIGNATURE2
1129 && pFwImgHdr->u32Signature3 == LSILOGIC_FWIMGHDR_SIGNATURE3)
1130 {
1131 LogFlowFunc(("IOC Facts: Found valid firmware image header in memory, using version (%#x), size (%d) and product ID (%#x) from there\n",
1132 pFwImgHdr->u32FwVersion, pFwImgHdr->u32ImageSize, pFwImgHdr->u16ProductId));
1133
1134 pReply->IOCFacts.u16ProductID = pFwImgHdr->u16ProductId;
1135 pReply->IOCFacts.u32FwImageSize = pFwImgHdr->u32ImageSize;
1136 pReply->IOCFacts.u32FWVersion = pFwImgHdr->u32FwVersion;
1137 }
1138 }
1139 else
1140 {
1141 pReply->IOCFacts.u16ProductID = 0xcafe; /* Our own product ID :) */
1142 pReply->IOCFacts.u32FwImageSize = 0; /* No image needed. */
1143 pReply->IOCFacts.u32FWVersion = 0;
1144 }
1145 break;
1146 }
1147 case MPT_MESSAGE_HDR_FUNCTION_PORT_FACTS:
1148 {
1149 PMptPortFactsRequest pPortFactsReq = (PMptPortFactsRequest)pMessageHdr;
1150
1151 pReply->PortFacts.u8MessageLength = 10;
1152 pReply->PortFacts.u8PortNumber = pPortFactsReq->u8PortNumber;
1153
1154 if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
1155 {
1156 /* This controller only supports one bus with bus number 0. */
1157 if (pPortFactsReq->u8PortNumber >= pThis->cPorts)
1158 {
1159 pReply->PortFacts.u8PortType = 0; /* Not existant. */
1160 }
1161 else
1162 {
1163 pReply->PortFacts.u8PortType = 0x01; /* SCSI Port. */
1164 pReply->PortFacts.u16MaxDevices = LSILOGICSCSI_PCI_SPI_DEVICES_PER_BUS_MAX;
1165 pReply->PortFacts.u16ProtocolFlags = RT_BIT(3) | RT_BIT(0); /* SCSI initiator and LUN supported. */
1166 pReply->PortFacts.u16PortSCSIID = 7; /* Default */
1167 pReply->PortFacts.u16MaxPersistentIDs = 0;
1168 pReply->PortFacts.u16MaxPostedCmdBuffers = 0; /* Only applies for target mode which we dont support. */
1169 pReply->PortFacts.u16MaxLANBuckets = 0; /* Only for the LAN controller. */
1170 }
1171 }
1172 else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
1173 {
1174 if (pPortFactsReq->u8PortNumber >= pThis->cPorts)
1175 {
1176 pReply->PortFacts.u8PortType = 0; /* Not existant. */
1177 }
1178 else
1179 {
1180 pReply->PortFacts.u8PortType = 0x30; /* SAS Port. */
1181 pReply->PortFacts.u16MaxDevices = pThis->cPorts;
1182 pReply->PortFacts.u16ProtocolFlags = RT_BIT(3) | RT_BIT(0); /* SCSI initiator and LUN supported. */
1183 pReply->PortFacts.u16PortSCSIID = pThis->cPorts;
1184 pReply->PortFacts.u16MaxPersistentIDs = 0;
1185 pReply->PortFacts.u16MaxPostedCmdBuffers = 0; /* Only applies for target mode which we dont support. */
1186 pReply->PortFacts.u16MaxLANBuckets = 0; /* Only for the LAN controller. */
1187 }
1188 }
1189 else
1190 AssertMsgFailed(("Invalid controller type %d\n", pThis->enmCtrlType));
1191 break;
1192 }
1193 case MPT_MESSAGE_HDR_FUNCTION_PORT_ENABLE:
1194 {
1195 /*
1196 * The port enable request notifies the IOC to make the port available and perform
1197 * appropriate discovery on the associated link.
1198 */
1199 PMptPortEnableRequest pPortEnableReq = (PMptPortEnableRequest)pMessageHdr;
1200
1201 pReply->PortEnable.u8MessageLength = 5;
1202 pReply->PortEnable.u8PortNumber = pPortEnableReq->u8PortNumber;
1203 break;
1204 }
1205 case MPT_MESSAGE_HDR_FUNCTION_EVENT_NOTIFICATION:
1206 {
1207 PMptEventNotificationRequest pEventNotificationReq = (PMptEventNotificationRequest)pMessageHdr;
1208
1209 if (pEventNotificationReq->u8Switch)
1210 pThis->fEventNotificationEnabled = true;
1211 else
1212 pThis->fEventNotificationEnabled = false;
1213
1214 pReply->EventNotification.u16EventDataLength = 1; /* 1 32bit D-Word. */
1215 pReply->EventNotification.u8MessageLength = 8;
1216 pReply->EventNotification.u8MessageFlags = (1 << 7);
1217 pReply->EventNotification.u8AckRequired = 0;
1218 pReply->EventNotification.u32Event = MPT_EVENT_EVENT_CHANGE;
1219 pReply->EventNotification.u32EventContext = 0;
1220 pReply->EventNotification.u32EventData = pThis->fEventNotificationEnabled ? 1 : 0;
1221
1222 break;
1223 }
1224 case MPT_MESSAGE_HDR_FUNCTION_EVENT_ACK:
1225 {
1226 AssertMsgFailed(("todo"));
1227 break;
1228 }
1229 case MPT_MESSAGE_HDR_FUNCTION_CONFIG:
1230 {
1231 PMptConfigurationRequest pConfigurationReq = (PMptConfigurationRequest)pMessageHdr;
1232
1233 rc = lsilogicR3ProcessConfigurationRequest(pThis, pConfigurationReq, &pReply->Configuration);
1234 AssertRC(rc);
1235 break;
1236 }
1237 case MPT_MESSAGE_HDR_FUNCTION_FW_UPLOAD:
1238 {
1239 PMptFWUploadRequest pFWUploadReq = (PMptFWUploadRequest)pMessageHdr;
1240
1241 pReply->FWUpload.u8ImageType = pFWUploadReq->u8ImageType;
1242 pReply->FWUpload.u8MessageLength = 6;
1243 pReply->FWUpload.u32ActualImageSize = 0;
1244 break;
1245 }
1246 case MPT_MESSAGE_HDR_FUNCTION_FW_DOWNLOAD:
1247 {
1248 //PMptFWDownloadRequest pFWDownloadReq = (PMptFWDownloadRequest)pMessageHdr;
1249
1250 pReply->FWDownload.u8MessageLength = 5;
1251 LogFlowFunc(("FW Download request issued\n"));
1252 break;
1253 }
1254 case MPT_MESSAGE_HDR_FUNCTION_SCSI_IO_REQUEST: /* Should be handled already. */
1255 default:
1256 AssertMsgFailed(("Invalid request function %#x\n", pMessageHdr->u8Function));
1257 }
1258
1259 /* Copy common bits from request message frame to reply. */
1260 pReply->Header.u8Function = pMessageHdr->u8Function;
1261 pReply->Header.u32MessageContext = pMessageHdr->u32MessageContext;
1262
1263 lsilogicFinishAddressReply(pThis, pReply, fForceReplyPostFifo);
1264 return rc;
1265}
1266
1267#endif /* IN_RING3 */
1268
1269/**
1270 * Writes a value to a register at a given offset.
1271 *
1272 * @returns VBox status code.
1273 * @param pThis Pointer to the LsiLogic device state.
1274 * @param offReg Offset of the register to write.
1275 * @param u32 The value being written.
1276 */
1277static int lsilogicRegisterWrite(PLSILOGICSCSI pThis, uint32_t offReg, uint32_t u32)
1278{
1279 LogFlowFunc(("pThis=%#p offReg=%#x u32=%#x\n", pThis, offReg, u32));
1280 switch (offReg)
1281 {
1282 case LSILOGIC_REG_REPLY_QUEUE:
1283 {
1284 int rc = PDMCritSectEnter(&pThis->ReplyFreeQueueWriteCritSect, VINF_IOM_R3_MMIO_WRITE);
1285 if (rc != VINF_SUCCESS)
1286 return rc;
1287 /* Add the entry to the reply free queue. */
1288 ASMAtomicWriteU32(&pThis->CTX_SUFF(pReplyFreeQueueBase)[pThis->uReplyFreeQueueNextEntryFreeWrite], u32);
1289 pThis->uReplyFreeQueueNextEntryFreeWrite++;
1290 pThis->uReplyFreeQueueNextEntryFreeWrite %= pThis->cReplyQueueEntries;
1291 PDMCritSectLeave(&pThis->ReplyFreeQueueWriteCritSect);
1292 break;
1293 }
1294 case LSILOGIC_REG_REQUEST_QUEUE:
1295 {
1296 int rc = PDMCritSectEnter(&pThis->RequestQueueCritSect, VINF_IOM_R3_MMIO_WRITE);
1297 if (rc != VINF_SUCCESS)
1298 return rc;
1299
1300 uint32_t uNextWrite = ASMAtomicReadU32(&pThis->uRequestQueueNextEntryFreeWrite);
1301
1302 ASMAtomicWriteU32(&pThis->CTX_SUFF(pRequestQueueBase)[uNextWrite], u32);
1303
1304 /*
1305 * Don't update the value in place. It can happen that we get preempted
1306 * after the increment but before the modulo.
1307 * Another EMT will read the wrong value when processing the queues
1308 * and hang in an endless loop creating thousands of requests.
1309 */
1310 uNextWrite++;
1311 uNextWrite %= pThis->cRequestQueueEntries;
1312 ASMAtomicWriteU32(&pThis->uRequestQueueNextEntryFreeWrite, uNextWrite);
1313 PDMCritSectLeave(&pThis->RequestQueueCritSect);
1314
1315 /* Send notification to R3 if there is not one sent already. Do this
1316 * only if the worker thread is not sleeping or might go sleeping. */
1317 if (!ASMAtomicXchgBool(&pThis->fNotificationSent, true))
1318 {
1319 if (ASMAtomicReadBool(&pThis->fWrkThreadSleeping))
1320 {
1321#ifdef IN_RC
1322 PPDMQUEUEITEMCORE pNotificationItem = PDMQueueAlloc(pThis->CTX_SUFF(pNotificationQueue));
1323 AssertPtr(pNotificationItem);
1324 PDMQueueInsert(pThis->CTX_SUFF(pNotificationQueue), pNotificationItem);
1325#else
1326 LogFlowFunc(("Signal event semaphore\n"));
1327 rc = SUPSemEventSignal(pThis->pSupDrvSession, pThis->hEvtProcess);
1328 AssertRC(rc);
1329#endif
1330 }
1331 }
1332 break;
1333 }
1334 case LSILOGIC_REG_DOORBELL:
1335 {
1336 /*
1337 * When the guest writes to this register a real device would set the
1338 * doorbell status bit in the interrupt status register to indicate that the IOP
1339 * has still to process the message.
1340 * The guest needs to wait with posting new messages here until the bit is cleared.
1341 * Because the guest is not continuing execution while we are here we can skip this.
1342 */
1343 if (pThis->enmDoorbellState == LSILOGICDOORBELLSTATE_NOT_IN_USE)
1344 {
1345 uint32_t uFunction = LSILOGIC_REG_DOORBELL_GET_FUNCTION(u32);
1346
1347 switch (uFunction)
1348 {
1349 case LSILOGIC_DOORBELL_FUNCTION_IO_UNIT_RESET:
1350 case LSILOGIC_DOORBELL_FUNCTION_IOC_MSG_UNIT_RESET:
1351 {
1352 /*
1353 * The I/O unit reset does much more on real hardware like
1354 * reloading the firmware, nothing we need to do here,
1355 * so this is like the IOC message unit reset.
1356 */
1357 pThis->enmState = LSILOGICSTATE_RESET;
1358
1359 /* Reset interrupt status. */
1360 pThis->uInterruptStatus = 0;
1361 lsilogicUpdateInterrupt(pThis);
1362
1363 /* Reset the queues. */
1364 pThis->uReplyFreeQueueNextEntryFreeWrite = 0;
1365 pThis->uReplyFreeQueueNextAddressRead = 0;
1366 pThis->uReplyPostQueueNextEntryFreeWrite = 0;
1367 pThis->uReplyPostQueueNextAddressRead = 0;
1368 pThis->uRequestQueueNextEntryFreeWrite = 0;
1369 pThis->uRequestQueueNextAddressRead = 0;
1370
1371 /* Only the IOC message unit reset transisionts to the ready state. */
1372 if (uFunction == LSILOGIC_DOORBELL_FUNCTION_IOC_MSG_UNIT_RESET)
1373 pThis->enmState = LSILOGICSTATE_READY;
1374 break;
1375 }
1376 case LSILOGIC_DOORBELL_FUNCTION_HANDSHAKE:
1377 {
1378 pThis->cMessage = LSILOGIC_REG_DOORBELL_GET_SIZE(u32);
1379 pThis->iMessage = 0;
1380 AssertMsg(pThis->cMessage <= RT_ELEMENTS(pThis->aMessage),
1381 ("Message doesn't fit into the buffer, cMessage=%u", pThis->cMessage));
1382 pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_FN_HANDSHAKE;
1383 /* Update the interrupt status to notify the guest that a doorbell function was started. */
1384 lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1385 break;
1386 }
1387 case LSILOGIC_DOORBELL_FUNCTION_REPLY_FRAME_REMOVAL:
1388 {
1389 pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_RFR_FRAME_COUNT_LOW;
1390 /* Update the interrupt status to notify the guest that a doorbell function was started. */
1391 lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1392 break;
1393 }
1394 default:
1395 AssertMsgFailed(("Unknown function %u to perform\n", uFunction));
1396 }
1397 }
1398 else if (pThis->enmDoorbellState == LSILOGICDOORBELLSTATE_FN_HANDSHAKE)
1399 {
1400 /*
1401 * We are already performing a doorbell function.
1402 * Get the remaining parameters.
1403 */
1404 AssertMsg(pThis->iMessage < RT_ELEMENTS(pThis->aMessage), ("Message is too big to fit into the buffer\n"));
1405 /*
1406 * If the last byte of the message is written, force a switch to R3 because some requests might force
1407 * a reply through the FIFO which cannot be handled in GC or R0.
1408 */
1409#ifndef IN_RING3
1410 if (pThis->iMessage == pThis->cMessage - 1)
1411 return VINF_IOM_R3_MMIO_WRITE;
1412#endif
1413 pThis->aMessage[pThis->iMessage++] = u32;
1414#ifdef IN_RING3
1415 if (pThis->iMessage == pThis->cMessage)
1416 {
1417 int rc = lsilogicR3ProcessMessageRequest(pThis, (PMptMessageHdr)pThis->aMessage, &pThis->ReplyBuffer);
1418 AssertRC(rc);
1419 }
1420#endif
1421 }
1422 break;
1423 }
1424 case LSILOGIC_REG_HOST_INTR_STATUS:
1425 {
1426 /*
1427 * Clear the bits the guest wants except the system doorbell interrupt and the IO controller
1428 * status bit.
1429 * The former bit is always cleared no matter what the guest writes to the register and
1430 * the latter one is read only.
1431 */
1432 ASMAtomicAndU32(&pThis->uInterruptStatus, ~LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1433
1434 /*
1435 * Check if there is still a doorbell function in progress. Set the
1436 * system doorbell interrupt bit again if it is.
1437 * We do not use lsilogicSetInterrupt here because the interrupt status
1438 * is updated afterwards anyway.
1439 */
1440 if ( (pThis->enmDoorbellState == LSILOGICDOORBELLSTATE_FN_HANDSHAKE)
1441 && (pThis->cMessage == pThis->iMessage))
1442 {
1443 if (pThis->uNextReplyEntryRead == pThis->cReplySize)
1444 {
1445 /* Reply finished. Reset doorbell in progress status. */
1446 Log(("%s: Doorbell function finished\n", __FUNCTION__));
1447 pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_NOT_IN_USE;
1448 }
1449 ASMAtomicOrU32(&pThis->uInterruptStatus, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1450 }
1451 else if ( pThis->enmDoorbellState != LSILOGICDOORBELLSTATE_NOT_IN_USE
1452 && pThis->enmDoorbellState != LSILOGICDOORBELLSTATE_FN_HANDSHAKE)
1453 {
1454 /* Reply frame removal, check whether the reply free queue is empty. */
1455 if ( pThis->uReplyFreeQueueNextAddressRead == pThis->uReplyFreeQueueNextEntryFreeWrite
1456 && pThis->enmDoorbellState == LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_LOW)
1457 pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_NOT_IN_USE;
1458 ASMAtomicOrU32(&pThis->uInterruptStatus, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1459 }
1460
1461 lsilogicUpdateInterrupt(pThis);
1462 break;
1463 }
1464 case LSILOGIC_REG_HOST_INTR_MASK:
1465 {
1466 ASMAtomicWriteU32(&pThis->uInterruptMask, u32 & LSILOGIC_REG_HOST_INTR_MASK_W_MASK);
1467 lsilogicUpdateInterrupt(pThis);
1468 break;
1469 }
1470 case LSILOGIC_REG_WRITE_SEQUENCE:
1471 {
1472 if (pThis->fDiagnosticEnabled)
1473 {
1474 /* Any value will cause a reset and disabling access. */
1475 pThis->fDiagnosticEnabled = false;
1476 pThis->iDiagnosticAccess = 0;
1477 pThis->fDiagRegsEnabled = false;
1478 }
1479 else if ((u32 & 0xf) == g_lsilogicDiagnosticAccess[pThis->iDiagnosticAccess])
1480 {
1481 pThis->iDiagnosticAccess++;
1482 if (pThis->iDiagnosticAccess == RT_ELEMENTS(g_lsilogicDiagnosticAccess))
1483 {
1484 /*
1485 * Key sequence successfully written. Enable access to diagnostic
1486 * memory and register.
1487 */
1488 pThis->fDiagnosticEnabled = true;
1489 }
1490 }
1491 else
1492 {
1493 /* Wrong value written - reset to beginning. */
1494 pThis->iDiagnosticAccess = 0;
1495 }
1496 break;
1497 }
1498 case LSILOGIC_REG_HOST_DIAGNOSTIC:
1499 {
1500 if (pThis->fDiagnosticEnabled)
1501 {
1502#ifndef IN_RING3
1503 return VINF_IOM_R3_MMIO_WRITE;
1504#else
1505 if (u32 & LSILOGIC_REG_HOST_DIAGNOSTIC_RESET_ADAPTER)
1506 lsilogicR3HardReset(pThis);
1507 else if (u32 & LSILOGIC_REG_HOST_DIAGNOSTIC_DIAG_RW_ENABLE)
1508 pThis->fDiagRegsEnabled = true;
1509#endif
1510 }
1511 break;
1512 }
1513 case LSILOGIC_REG_DIAG_RW_DATA:
1514 {
1515 if (pThis->fDiagRegsEnabled)
1516 {
1517#ifndef IN_RING3
1518 return VINF_IOM_R3_MMIO_WRITE;
1519#else
1520 lsilogicR3DiagRegDataWrite(pThis, u32);
1521#endif
1522 }
1523 break;
1524 }
1525 case LSILOGIC_REG_DIAG_RW_ADDRESS:
1526 {
1527 if (pThis->fDiagRegsEnabled)
1528 {
1529#ifndef IN_RING3
1530 return VINF_IOM_R3_MMIO_WRITE;
1531#else
1532 lsilogicR3DiagRegAddressWrite(pThis, u32);
1533#endif
1534 }
1535 break;
1536 }
1537 default: /* Ignore. */
1538 {
1539 break;
1540 }
1541 }
1542 return VINF_SUCCESS;
1543}
1544
1545/**
1546 * Reads the content of a register at a given offset.
1547 *
1548 * @returns VBox status code.
1549 * @param pThis Pointer to the LsiLogic device state.
1550 * @param offReg Offset of the register to read.
1551 * @param pu32 Where to store the content of the register.
1552 */
1553static int lsilogicRegisterRead(PLSILOGICSCSI pThis, uint32_t offReg, uint32_t *pu32)
1554{
1555 int rc = VINF_SUCCESS;
1556 uint32_t u32 = 0;
1557 Assert(!(offReg & 3));
1558
1559 /* Align to a 4 byte offset. */
1560 switch (offReg)
1561 {
1562 case LSILOGIC_REG_REPLY_QUEUE:
1563 {
1564 rc = PDMCritSectEnter(&pThis->ReplyPostQueueCritSect, VINF_IOM_R3_MMIO_READ);
1565 if (rc != VINF_SUCCESS)
1566 break;
1567
1568 uint32_t idxReplyPostQueueWrite = ASMAtomicUoReadU32(&pThis->uReplyPostQueueNextEntryFreeWrite);
1569 uint32_t idxReplyPostQueueRead = ASMAtomicUoReadU32(&pThis->uReplyPostQueueNextAddressRead);
1570
1571 if (idxReplyPostQueueWrite != idxReplyPostQueueRead)
1572 {
1573 u32 = pThis->CTX_SUFF(pReplyPostQueueBase)[idxReplyPostQueueRead];
1574 idxReplyPostQueueRead++;
1575 idxReplyPostQueueRead %= pThis->cReplyQueueEntries;
1576 ASMAtomicWriteU32(&pThis->uReplyPostQueueNextAddressRead, idxReplyPostQueueRead);
1577 }
1578 else
1579 {
1580 /* The reply post queue is empty. Reset interrupt. */
1581 u32 = UINT32_C(0xffffffff);
1582 lsilogicClearInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_REPLY_INTR);
1583 }
1584 PDMCritSectLeave(&pThis->ReplyPostQueueCritSect);
1585
1586 Log(("%s: Returning address %#x\n", __FUNCTION__, u32));
1587 break;
1588 }
1589 case LSILOGIC_REG_DOORBELL:
1590 {
1591 u32 = LSILOGIC_REG_DOORBELL_SET_STATE(pThis->enmState);
1592 u32 |= LSILOGIC_REG_DOORBELL_SET_USED(pThis->enmDoorbellState);
1593 u32 |= LSILOGIC_REG_DOORBELL_SET_WHOINIT(pThis->enmWhoInit);
1594 /*
1595 * If there is a doorbell function in progress we pass the return value
1596 * instead of the status code. We transfer 16bit of the reply
1597 * during one read.
1598 */
1599 switch (pThis->enmDoorbellState)
1600 {
1601 case LSILOGICDOORBELLSTATE_NOT_IN_USE:
1602 /* We return the status code of the I/O controller. */
1603 u32 |= pThis->u16IOCFaultCode;
1604 break;
1605 case LSILOGICDOORBELLSTATE_FN_HANDSHAKE:
1606 /* Return next 16bit value. */
1607 if (pThis->uNextReplyEntryRead < pThis->cReplySize)
1608 u32 |= pThis->ReplyBuffer.au16Reply[pThis->uNextReplyEntryRead++];
1609 lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1610 break;
1611 case LSILOGICDOORBELLSTATE_RFR_FRAME_COUNT_LOW:
1612 {
1613 uint32_t cReplyFrames = lsilogicReplyFreeQueueGetFrameCount(pThis);
1614
1615 u32 |= cReplyFrames & UINT32_C(0xffff);
1616 pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_RFR_FRAME_COUNT_HIGH;
1617 lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1618 break;
1619 }
1620 case LSILOGICDOORBELLSTATE_RFR_FRAME_COUNT_HIGH:
1621 {
1622 uint32_t cReplyFrames = lsilogicReplyFreeQueueGetFrameCount(pThis);
1623
1624 u32 |= cReplyFrames >> 16;
1625 pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_LOW;
1626 lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1627 break;
1628 }
1629 case LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_LOW:
1630 if (pThis->uReplyFreeQueueNextEntryFreeWrite != pThis->uReplyFreeQueueNextAddressRead)
1631 {
1632 u32 |= pThis->CTX_SUFF(pReplyFreeQueueBase)[pThis->uReplyFreeQueueNextAddressRead] & UINT32_C(0xffff);
1633 pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_HIGH;
1634 lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1635 }
1636 break;
1637 case LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_HIGH:
1638 u32 |= pThis->CTX_SUFF(pReplyFreeQueueBase)[pThis->uReplyFreeQueueNextAddressRead] >> 16;
1639 pThis->uReplyFreeQueueNextAddressRead++;
1640 pThis->uReplyFreeQueueNextAddressRead %= pThis->cReplyQueueEntries;
1641 pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_LOW;
1642 lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1643 break;
1644 default:
1645 AssertMsgFailed(("Invalid doorbell state %d\n", pThis->enmDoorbellState));
1646 }
1647
1648 break;
1649 }
1650 case LSILOGIC_REG_HOST_INTR_STATUS:
1651 {
1652 u32 = ASMAtomicReadU32(&pThis->uInterruptStatus);
1653 break;
1654 }
1655 case LSILOGIC_REG_HOST_INTR_MASK:
1656 {
1657 u32 = ASMAtomicReadU32(&pThis->uInterruptMask);
1658 break;
1659 }
1660 case LSILOGIC_REG_HOST_DIAGNOSTIC:
1661 {
1662 if (pThis->fDiagnosticEnabled)
1663 u32 |= LSILOGIC_REG_HOST_DIAGNOSTIC_DRWE;
1664 if (pThis->fDiagRegsEnabled)
1665 u32 |= LSILOGIC_REG_HOST_DIAGNOSTIC_DIAG_RW_ENABLE;
1666 break;
1667 }
1668 case LSILOGIC_REG_DIAG_RW_DATA:
1669 {
1670 if (pThis->fDiagRegsEnabled)
1671 {
1672#ifndef IN_RING3
1673 return VINF_IOM_R3_MMIO_READ;
1674#else
1675 lsilogicR3DiagRegDataRead(pThis, &u32);
1676#endif
1677 }
1678 }
1679 RT_FALL_THRU();
1680 case LSILOGIC_REG_DIAG_RW_ADDRESS:
1681 {
1682 if (pThis->fDiagRegsEnabled)
1683 {
1684#ifndef IN_RING3
1685 return VINF_IOM_R3_MMIO_READ;
1686#else
1687 lsilogicR3DiagRegAddressRead(pThis, &u32);
1688#endif
1689 }
1690 }
1691 RT_FALL_THRU();
1692 case LSILOGIC_REG_TEST_BASE_ADDRESS: /* The spec doesn't say anything about these registers, so we just ignore them */
1693 default: /* Ignore. */
1694 {
1695 /** @todo LSILOGIC_REG_DIAG_* should return all F's when accessed by MMIO. We
1696 * return 0. Likely to apply to undefined offsets as well. */
1697 break;
1698 }
1699 }
1700
1701 *pu32 = u32;
1702 LogFlowFunc(("pThis=%#p offReg=%#x u32=%#x\n", pThis, offReg, u32));
1703 return rc;
1704}
1705
1706/**
1707 * @callback_method_impl{FNIOMIOPORTOUT}
1708 */
1709PDMBOTHCBDECL(int) lsilogicIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
1710{
1711 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
1712 uint32_t offReg = uPort - pThis->IOPortBase;
1713 int rc;
1714 RT_NOREF2(pvUser, cb);
1715
1716 if (!(offReg & 3))
1717 {
1718 rc = lsilogicRegisterWrite(pThis, offReg, u32);
1719 if (rc == VINF_IOM_R3_MMIO_WRITE)
1720 rc = VINF_IOM_R3_IOPORT_WRITE;
1721 }
1722 else
1723 {
1724 Log(("lsilogicIOPortWrite: Ignoring misaligned write - offReg=%#x u32=%#x cb=%#x\n", offReg, u32, cb));
1725 rc = VINF_SUCCESS;
1726 }
1727
1728 return rc;
1729}
1730
1731/**
1732 * @callback_method_impl{FNIOMIOPORTIN}
1733 */
1734PDMBOTHCBDECL(int) lsilogicIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
1735{
1736 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
1737 uint32_t offReg = uPort - pThis->IOPortBase;
1738 RT_NOREF_PV(pvUser);
1739 RT_NOREF_PV(cb);
1740
1741 int rc = lsilogicRegisterRead(pThis, offReg & ~(uint32_t)3, pu32);
1742 if (rc == VINF_IOM_R3_MMIO_READ)
1743 rc = VINF_IOM_R3_IOPORT_READ;
1744
1745 return rc;
1746}
1747
1748/**
1749 * @callback_method_impl{FNIOMMMIOWRITE}
1750 */
1751PDMBOTHCBDECL(int) lsilogicMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
1752{
1753 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
1754 uint32_t offReg = GCPhysAddr - pThis->GCPhysMMIOBase;
1755 uint32_t u32;
1756 int rc;
1757 RT_NOREF_PV(pvUser);
1758
1759 /* See comments in lsilogicR3Map regarding size and alignment. */
1760 if (cb == 4)
1761 u32 = *(uint32_t const *)pv;
1762 else
1763 {
1764 if (cb > 4)
1765 u32 = *(uint32_t const *)pv;
1766 else if (cb >= 2)
1767 u32 = *(uint16_t const *)pv;
1768 else
1769 u32 = *(uint8_t const *)pv;
1770 Log(("lsilogicMMIOWrite: Non-DWORD write access - offReg=%#x u32=%#x cb=%#x\n", offReg, u32, cb));
1771 }
1772
1773 if (!(offReg & 3))
1774 rc = lsilogicRegisterWrite(pThis, offReg, u32);
1775 else
1776 {
1777 Log(("lsilogicIOPortWrite: Ignoring misaligned write - offReg=%#x u32=%#x cb=%#x\n", offReg, u32, cb));
1778 rc = VINF_SUCCESS;
1779 }
1780 return rc;
1781}
1782
1783/**
1784 * @callback_method_impl{FNIOMMMIOREAD}
1785 */
1786PDMBOTHCBDECL(int) lsilogicMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1787{
1788 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
1789 uint32_t offReg = GCPhysAddr - pThis->GCPhysMMIOBase;
1790 Assert(!(offReg & 3)); Assert(cb == 4);
1791 RT_NOREF2(pvUser, cb);
1792
1793 return lsilogicRegisterRead(pThis, offReg, (uint32_t *)pv);
1794}
1795
1796PDMBOTHCBDECL(int) lsilogicDiagnosticWrite(PPDMDEVINS pDevIns, void *pvUser,
1797 RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
1798{
1799#ifdef LOG_ENABLED
1800 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
1801 LogFlowFunc(("pThis=%#p GCPhysAddr=%RGp pv=%#p{%.*Rhxs} cb=%u\n", pThis, GCPhysAddr, pv, cb, pv, cb));
1802#endif
1803
1804 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pvUser); RT_NOREF_PV(GCPhysAddr); RT_NOREF_PV(pv); RT_NOREF_PV(cb);
1805 return VINF_SUCCESS;
1806}
1807
1808PDMBOTHCBDECL(int) lsilogicDiagnosticRead(PPDMDEVINS pDevIns, void *pvUser,
1809 RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1810{
1811#ifdef LOG_ENABLED
1812 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
1813 LogFlowFunc(("pThis=%#p GCPhysAddr=%RGp pv=%#p{%.*Rhxs} cb=%u\n", pThis, GCPhysAddr, pv, cb, pv, cb));
1814#endif
1815
1816 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pvUser); RT_NOREF_PV(GCPhysAddr); RT_NOREF_PV(pv); RT_NOREF_PV(cb);
1817 return VINF_SUCCESS;
1818}
1819
1820#ifdef IN_RING3
1821
1822# ifdef LOG_ENABLED
1823/**
1824 * Dump an SG entry.
1825 *
1826 * @returns nothing.
1827 * @param pSGEntry Pointer to the SG entry to dump
1828 */
1829static void lsilogicDumpSGEntry(PMptSGEntryUnion pSGEntry)
1830{
1831 if (LogIsEnabled())
1832 {
1833 switch (pSGEntry->Simple32.u2ElementType)
1834 {
1835 case MPTSGENTRYTYPE_SIMPLE:
1836 {
1837 Log(("%s: Dumping info for SIMPLE SG entry:\n", __FUNCTION__));
1838 Log(("%s: u24Length=%u\n", __FUNCTION__, pSGEntry->Simple32.u24Length));
1839 Log(("%s: fEndOfList=%d\n", __FUNCTION__, pSGEntry->Simple32.fEndOfList));
1840 Log(("%s: f64BitAddress=%d\n", __FUNCTION__, pSGEntry->Simple32.f64BitAddress));
1841 Log(("%s: fBufferContainsData=%d\n", __FUNCTION__, pSGEntry->Simple32.fBufferContainsData));
1842 Log(("%s: fLocalAddress=%d\n", __FUNCTION__, pSGEntry->Simple32.fLocalAddress));
1843 Log(("%s: fEndOfBuffer=%d\n", __FUNCTION__, pSGEntry->Simple32.fEndOfBuffer));
1844 Log(("%s: fLastElement=%d\n", __FUNCTION__, pSGEntry->Simple32.fLastElement));
1845 Log(("%s: u32DataBufferAddressLow=%u\n", __FUNCTION__, pSGEntry->Simple32.u32DataBufferAddressLow));
1846 if (pSGEntry->Simple32.f64BitAddress)
1847 {
1848 Log(("%s: u32DataBufferAddressHigh=%u\n", __FUNCTION__, pSGEntry->Simple64.u32DataBufferAddressHigh));
1849 Log(("%s: GCDataBufferAddress=%RGp\n", __FUNCTION__,
1850 ((uint64_t)pSGEntry->Simple64.u32DataBufferAddressHigh << 32)
1851 | pSGEntry->Simple64.u32DataBufferAddressLow));
1852 }
1853 else
1854 Log(("%s: GCDataBufferAddress=%RGp\n", __FUNCTION__, pSGEntry->Simple32.u32DataBufferAddressLow));
1855
1856 break;
1857 }
1858 case MPTSGENTRYTYPE_CHAIN:
1859 {
1860 Log(("%s: Dumping info for CHAIN SG entry:\n", __FUNCTION__));
1861 Log(("%s: u16Length=%u\n", __FUNCTION__, pSGEntry->Chain.u16Length));
1862 Log(("%s: u8NExtChainOffset=%d\n", __FUNCTION__, pSGEntry->Chain.u8NextChainOffset));
1863 Log(("%s: f64BitAddress=%d\n", __FUNCTION__, pSGEntry->Chain.f64BitAddress));
1864 Log(("%s: fLocalAddress=%d\n", __FUNCTION__, pSGEntry->Chain.fLocalAddress));
1865 Log(("%s: u32SegmentAddressLow=%u\n", __FUNCTION__, pSGEntry->Chain.u32SegmentAddressLow));
1866 Log(("%s: u32SegmentAddressHigh=%u\n", __FUNCTION__, pSGEntry->Chain.u32SegmentAddressHigh));
1867 if (pSGEntry->Chain.f64BitAddress)
1868 Log(("%s: GCSegmentAddress=%RGp\n", __FUNCTION__,
1869 ((uint64_t)pSGEntry->Chain.u32SegmentAddressHigh << 32) | pSGEntry->Chain.u32SegmentAddressLow));
1870 else
1871 Log(("%s: GCSegmentAddress=%RGp\n", __FUNCTION__, pSGEntry->Chain.u32SegmentAddressLow));
1872 break;
1873 }
1874 }
1875 }
1876}
1877# endif /* LOG_ENABLED */
1878
1879/**
1880 * Copy from guest to host memory worker.
1881 *
1882 * @copydoc LSILOGICR3MEMCOPYCALLBACK
1883 */
1884static DECLCALLBACK(void) lsilogicR3CopyBufferFromGuestWorker(PLSILOGICSCSI pThis, RTGCPHYS GCPhys, PRTSGBUF pSgBuf,
1885 size_t cbCopy, size_t *pcbSkip)
1886{
1887 size_t cbSkipped = RT_MIN(cbCopy, *pcbSkip);
1888 cbCopy -= cbSkipped;
1889 GCPhys += cbSkipped;
1890 *pcbSkip -= cbSkipped;
1891
1892 while (cbCopy)
1893 {
1894 size_t cbSeg = cbCopy;
1895 void *pvSeg = RTSgBufGetNextSegment(pSgBuf, &cbSeg);
1896
1897 AssertPtr(pvSeg);
1898 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, pvSeg, cbSeg);
1899 GCPhys += cbSeg;
1900 cbCopy -= cbSeg;
1901 }
1902}
1903
1904/**
1905 * Copy from host to guest memory worker.
1906 *
1907 * @copydoc LSILOGICR3MEMCOPYCALLBACK
1908 */
1909static DECLCALLBACK(void) lsilogicR3CopyBufferToGuestWorker(PLSILOGICSCSI pThis, RTGCPHYS GCPhys, PRTSGBUF pSgBuf,
1910 size_t cbCopy, size_t *pcbSkip)
1911{
1912 size_t cbSkipped = RT_MIN(cbCopy, *pcbSkip);
1913 cbCopy -= cbSkipped;
1914 GCPhys += cbSkipped;
1915 *pcbSkip -= cbSkipped;
1916
1917 while (cbCopy)
1918 {
1919 size_t cbSeg = cbCopy;
1920 void *pvSeg = RTSgBufGetNextSegment(pSgBuf, &cbSeg);
1921
1922 AssertPtr(pvSeg);
1923 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhys, pvSeg, cbSeg);
1924 GCPhys += cbSeg;
1925 cbCopy -= cbSeg;
1926 }
1927}
1928
1929/**
1930 * Walks the guest S/G buffer calling the given copy worker for every buffer.
1931 *
1932 * @returns The amout of bytes actually copied.
1933 * @param pThis Pointer to the LsiLogic device state.
1934 * @param pLsiReq LSI request state.
1935 * @param pfnCopyWorker The copy method to apply for each guest buffer.
1936 * @param pSgBuf The host S/G buffer.
1937 * @param cbSkip How many bytes to skip in advance before starting to copy.
1938 * @param cbCopy How many bytes to copy.
1939 */
1940static size_t lsilogicSgBufWalker(PLSILOGICSCSI pThis, PLSILOGICREQ pLsiReq,
1941 PLSILOGICR3MEMCOPYCALLBACK pfnCopyWorker,
1942 PRTSGBUF pSgBuf, size_t cbSkip, size_t cbCopy)
1943{
1944 bool fEndOfList = false;
1945 RTGCPHYS GCPhysSgEntryNext = pLsiReq->GCPhysSgStart;
1946 RTGCPHYS GCPhysSegmentStart = pLsiReq->GCPhysSgStart;
1947 uint32_t cChainOffsetNext = pLsiReq->cChainOffset;
1948 PPDMDEVINS pDevIns = pThis->CTX_SUFF(pDevIns);
1949 size_t cbCopied = 0;
1950
1951 /*
1952 * Add the amount to skip to the host buffer size to avoid a
1953 * few conditionals later on.
1954 */
1955 cbCopy += cbSkip;
1956
1957 /* Go through the list until we reach the end. */
1958 while ( !fEndOfList
1959 && cbCopy)
1960 {
1961 bool fEndOfSegment = false;
1962
1963 while ( !fEndOfSegment
1964 && cbCopy)
1965 {
1966 MptSGEntryUnion SGEntry;
1967
1968 Log(("%s: Reading SG entry from %RGp\n", __FUNCTION__, GCPhysSgEntryNext));
1969
1970 /* Read the entry. */
1971 PDMDevHlpPhysRead(pDevIns, GCPhysSgEntryNext, &SGEntry, sizeof(MptSGEntryUnion));
1972
1973# ifdef LOG_ENABLED
1974 lsilogicDumpSGEntry(&SGEntry);
1975# endif
1976
1977 AssertMsg(SGEntry.Simple32.u2ElementType == MPTSGENTRYTYPE_SIMPLE, ("Invalid SG entry type\n"));
1978
1979 /* Check if this is a zero element and abort. */
1980 if ( !SGEntry.Simple32.u24Length
1981 && SGEntry.Simple32.fEndOfList
1982 && SGEntry.Simple32.fEndOfBuffer)
1983 return cbCopied - RT_MIN(cbSkip, cbCopied);
1984
1985 uint32_t cbCopyThis = SGEntry.Simple32.u24Length;
1986 RTGCPHYS GCPhysAddrDataBuffer = SGEntry.Simple32.u32DataBufferAddressLow;
1987
1988 if (SGEntry.Simple32.f64BitAddress)
1989 {
1990 GCPhysAddrDataBuffer |= ((uint64_t)SGEntry.Simple64.u32DataBufferAddressHigh) << 32;
1991 GCPhysSgEntryNext += sizeof(MptSGEntrySimple64);
1992 }
1993 else
1994 GCPhysSgEntryNext += sizeof(MptSGEntrySimple32);
1995
1996 pfnCopyWorker(pThis, GCPhysAddrDataBuffer, pSgBuf, cbCopyThis, &cbSkip);
1997 cbCopy -= cbCopyThis;
1998 cbCopied += cbCopyThis;
1999
2000 /* Check if we reached the end of the list. */
2001 if (SGEntry.Simple32.fEndOfList)
2002 {
2003 /* We finished. */
2004 fEndOfSegment = true;
2005 fEndOfList = true;
2006 }
2007 else if (SGEntry.Simple32.fLastElement)
2008 fEndOfSegment = true;
2009 } /* while (!fEndOfSegment) */
2010
2011 /* Get next chain element. */
2012 if (cChainOffsetNext)
2013 {
2014 MptSGEntryChain SGEntryChain;
2015
2016 PDMDevHlpPhysRead(pDevIns, GCPhysSegmentStart + cChainOffsetNext, &SGEntryChain, sizeof(MptSGEntryChain));
2017
2018 AssertMsg(SGEntryChain.u2ElementType == MPTSGENTRYTYPE_CHAIN, ("Invalid SG entry type\n"));
2019
2020 /* Set the next address now. */
2021 GCPhysSgEntryNext = SGEntryChain.u32SegmentAddressLow;
2022 if (SGEntryChain.f64BitAddress)
2023 GCPhysSgEntryNext |= ((uint64_t)SGEntryChain.u32SegmentAddressHigh) << 32;
2024
2025 GCPhysSegmentStart = GCPhysSgEntryNext;
2026 cChainOffsetNext = SGEntryChain.u8NextChainOffset * sizeof(uint32_t);
2027 }
2028 } /* while (!fEndOfList) */
2029
2030 return cbCopied - RT_MIN(cbSkip, cbCopied);
2031}
2032
2033/**
2034 * Copies a data buffer into the S/G buffer set up by the guest.
2035 *
2036 * @returns Amount of bytes copied to the guest.
2037 * @param pThis The LsiLogic controller device instance.
2038 * @param pReq Request structure.
2039 * @param pSgBuf The S/G buffer to copy from.
2040 * @param cbSkip How many bytes to skip in advance before starting to copy.
2041 * @param cbCopy How many bytes to copy.
2042 */
2043static size_t lsilogicR3CopySgBufToGuest(PLSILOGICSCSI pThis, PLSILOGICREQ pReq, PRTSGBUF pSgBuf,
2044 size_t cbSkip, size_t cbCopy)
2045{
2046 return lsilogicSgBufWalker(pThis, pReq, lsilogicR3CopyBufferToGuestWorker,
2047 pSgBuf, cbSkip, cbCopy);
2048}
2049
2050/**
2051 * Copies the guest S/G buffer into a host data buffer.
2052 *
2053 * @returns Amount of bytes copied from the guest.
2054 * @param pThis The LsiLogic controller device instance.
2055 * @param pReq Request structure.
2056 * @param pSgBuf The S/G buffer to copy into.
2057 * @param cbSkip How many bytes to skip in advance before starting to copy.
2058 * @param cbCopy How many bytes to copy.
2059 */
2060static size_t lsilogicR3CopySgBufFromGuest(PLSILOGICSCSI pThis, PLSILOGICREQ pReq, PRTSGBUF pSgBuf,
2061 size_t cbSkip, size_t cbCopy)
2062{
2063 return lsilogicSgBufWalker(pThis, pReq, lsilogicR3CopyBufferFromGuestWorker,
2064 pSgBuf, cbSkip, cbCopy);
2065}
2066
2067#if 0 /* unused */
2068/**
2069 * Copy a simple memory buffer to the guest memory buffer.
2070 *
2071 * @returns Amount of bytes copied to the guest.
2072 * @param pThis The LsiLogic controller device instance.
2073 * @param pReq Request structure.
2074 * @param pvSrc The buffer to copy from.
2075 * @param cbSrc How many bytes to copy.
2076 * @param cbSkip How many bytes to skip initially.
2077 */
2078static size_t lsilogicR3CopyBufferToGuest(PLSILOGICSCSI pThis, PLSILOGICREQ pReq, const void *pvSrc,
2079 size_t cbSrc, size_t cbSkip)
2080{
2081 RTSGSEG Seg;
2082 RTSGBUF SgBuf;
2083 Seg.pvSeg = (void *)pvSrc;
2084 Seg.cbSeg = cbSrc;
2085 RTSgBufInit(&SgBuf, &Seg, 1);
2086 return lsilogicR3CopySgBufToGuest(pThis, pReq, &SgBuf, cbSkip, cbSrc);
2087}
2088
2089/**
2090 * Copy a guest memry buffe into simple host memory buffer.
2091 *
2092 * @returns Amount of bytes copied to the guest.
2093 * @param pThis The LsiLogic controller device instance.
2094 * @param pReq Request structure.
2095 * @param pvSrc The buffer to copy from.
2096 * @param cbSrc How many bytes to copy.
2097 * @param cbSkip How many bytes to skip initially.
2098 */
2099static size_t lsilogicR3CopyBufferFromGuest(PLSILOGICSCSI pThis, PLSILOGICREQ pReq, void *pvDst,
2100 size_t cbDst, size_t cbSkip)
2101{
2102 RTSGSEG Seg;
2103 RTSGBUF SgBuf;
2104 Seg.pvSeg = (void *)pvDst;
2105 Seg.cbSeg = cbDst;
2106 RTSgBufInit(&SgBuf, &Seg, 1);
2107 return lsilogicR3CopySgBufFromGuest(pThis, pReq, &SgBuf, cbSkip, cbDst);
2108}
2109#endif
2110
2111# ifdef LOG_ENABLED
2112static void lsilogicR3DumpSCSIIORequest(PMptSCSIIORequest pSCSIIORequest)
2113{
2114 if (LogIsEnabled())
2115 {
2116 Log(("%s: u8TargetID=%d\n", __FUNCTION__, pSCSIIORequest->u8TargetID));
2117 Log(("%s: u8Bus=%d\n", __FUNCTION__, pSCSIIORequest->u8Bus));
2118 Log(("%s: u8ChainOffset=%d\n", __FUNCTION__, pSCSIIORequest->u8ChainOffset));
2119 Log(("%s: u8Function=%d\n", __FUNCTION__, pSCSIIORequest->u8Function));
2120 Log(("%s: u8CDBLength=%d\n", __FUNCTION__, pSCSIIORequest->u8CDBLength));
2121 Log(("%s: u8SenseBufferLength=%d\n", __FUNCTION__, pSCSIIORequest->u8SenseBufferLength));
2122 Log(("%s: u8MessageFlags=%d\n", __FUNCTION__, pSCSIIORequest->u8MessageFlags));
2123 Log(("%s: u32MessageContext=%#x\n", __FUNCTION__, pSCSIIORequest->u32MessageContext));
2124 for (unsigned i = 0; i < RT_ELEMENTS(pSCSIIORequest->au8LUN); i++)
2125 Log(("%s: u8LUN[%d]=%d\n", __FUNCTION__, i, pSCSIIORequest->au8LUN[i]));
2126 Log(("%s: u32Control=%#x\n", __FUNCTION__, pSCSIIORequest->u32Control));
2127 for (unsigned i = 0; i < RT_ELEMENTS(pSCSIIORequest->au8CDB); i++)
2128 Log(("%s: u8CDB[%d]=%d\n", __FUNCTION__, i, pSCSIIORequest->au8CDB[i]));
2129 Log(("%s: u32DataLength=%#x\n", __FUNCTION__, pSCSIIORequest->u32DataLength));
2130 Log(("%s: u32SenseBufferLowAddress=%#x\n", __FUNCTION__, pSCSIIORequest->u32SenseBufferLowAddress));
2131 }
2132}
2133# endif
2134
2135/**
2136 * Handles the completion of th given request.
2137 *
2138 * @returns nothing.
2139 * @param pThis Pointer to the LsiLogic device state.
2140 * @param pReq The request to complete.
2141 * @param rcReq Status code of the request.
2142 */
2143static void lsilogicR3ReqComplete(PLSILOGICSCSI pThis, PLSILOGICREQ pReq, int rcReq)
2144{
2145 PLSILOGICDEVICE pTgtDev = pReq->pTargetDevice;
2146
2147 if (RT_UNLIKELY(pReq->fBIOS))
2148 {
2149 uint8_t u8ScsiSts = pReq->u8ScsiSts;
2150 pTgtDev->pDrvMediaEx->pfnIoReqFree(pTgtDev->pDrvMediaEx, pReq->hIoReq);
2151 int rc = vboxscsiRequestFinished(&pThis->VBoxSCSI, u8ScsiSts);
2152 AssertMsgRC(rc, ("Finishing BIOS SCSI request failed rc=%Rrc\n", rc));
2153 }
2154 else
2155 {
2156 RTGCPHYS GCPhysAddrSenseBuffer;
2157
2158 GCPhysAddrSenseBuffer = pReq->GuestRequest.SCSIIO.u32SenseBufferLowAddress;
2159 GCPhysAddrSenseBuffer |= ((uint64_t)pThis->u32SenseBufferHighAddr << 32);
2160
2161 /* Copy the sense buffer over. */
2162 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhysAddrSenseBuffer, pReq->abSenseBuffer,
2163 RT_UNLIKELY( pReq->GuestRequest.SCSIIO.u8SenseBufferLength
2164 < sizeof(pReq->abSenseBuffer))
2165 ? pReq->GuestRequest.SCSIIO.u8SenseBufferLength
2166 : sizeof(pReq->abSenseBuffer));
2167
2168 if (RT_SUCCESS(rcReq) && RT_LIKELY(pReq->u8ScsiSts == SCSI_STATUS_OK))
2169 {
2170 uint32_t u32MsgCtx = pReq->GuestRequest.SCSIIO.u32MessageContext;
2171
2172 /* Free the request before posting completion. */
2173 pTgtDev->pDrvMediaEx->pfnIoReqFree(pTgtDev->pDrvMediaEx, pReq->hIoReq);
2174 lsilogicR3FinishContextReply(pThis, u32MsgCtx);
2175 }
2176 else
2177 {
2178 MptReplyUnion IOCReply;
2179 RT_ZERO(IOCReply);
2180
2181 /* The SCSI target encountered an error during processing post a reply. */
2182 IOCReply.SCSIIOError.u8TargetID = pReq->GuestRequest.SCSIIO.u8TargetID;
2183 IOCReply.SCSIIOError.u8Bus = pReq->GuestRequest.SCSIIO.u8Bus;
2184 IOCReply.SCSIIOError.u8MessageLength = 8;
2185 IOCReply.SCSIIOError.u8Function = pReq->GuestRequest.SCSIIO.u8Function;
2186 IOCReply.SCSIIOError.u8CDBLength = pReq->GuestRequest.SCSIIO.u8CDBLength;
2187 IOCReply.SCSIIOError.u8SenseBufferLength = pReq->GuestRequest.SCSIIO.u8SenseBufferLength;
2188 IOCReply.SCSIIOError.u8MessageFlags = pReq->GuestRequest.SCSIIO.u8MessageFlags;
2189 IOCReply.SCSIIOError.u32MessageContext = pReq->GuestRequest.SCSIIO.u32MessageContext;
2190 IOCReply.SCSIIOError.u8SCSIStatus = pReq->u8ScsiSts;
2191 IOCReply.SCSIIOError.u8SCSIState = MPT_SCSI_IO_ERROR_SCSI_STATE_AUTOSENSE_VALID;
2192 IOCReply.SCSIIOError.u16IOCStatus = 0;
2193 IOCReply.SCSIIOError.u32IOCLogInfo = 0;
2194 IOCReply.SCSIIOError.u32TransferCount = 0;
2195 IOCReply.SCSIIOError.u32SenseCount = sizeof(pReq->abSenseBuffer);
2196 IOCReply.SCSIIOError.u32ResponseInfo = 0;
2197
2198 /* Free the request before posting completion. */
2199 pTgtDev->pDrvMediaEx->pfnIoReqFree(pTgtDev->pDrvMediaEx, pReq->hIoReq);
2200 lsilogicFinishAddressReply(pThis, &IOCReply, false);
2201 }
2202 }
2203
2204 ASMAtomicDecU32(&pTgtDev->cOutstandingRequests);
2205
2206 if (pTgtDev->cOutstandingRequests == 0 && pThis->fSignalIdle)
2207 PDMDevHlpAsyncNotificationCompleted(pThis->pDevInsR3);
2208}
2209
2210/**
2211 * Processes a SCSI I/O request by setting up the request
2212 * and sending it to the underlying SCSI driver.
2213 * Steps needed to complete request are done in the
2214 * callback called by the driver below upon completion of
2215 * the request.
2216 *
2217 * @returns VBox status code.
2218 * @param pThis Pointer to the LsiLogic device state.
2219 * @param GCPhysMessageFrameAddr Guest physical address where the request is located.
2220 * @param pGuestReq The request read fro th guest memory.
2221 */
2222static int lsilogicR3ProcessSCSIIORequest(PLSILOGICSCSI pThis, RTGCPHYS GCPhysMessageFrameAddr,
2223 PMptRequestUnion pGuestReq)
2224{
2225 MptReplyUnion IOCReply;
2226 int rc = VINF_SUCCESS;
2227
2228# ifdef LOG_ENABLED
2229 lsilogicR3DumpSCSIIORequest(&pGuestReq->SCSIIO);
2230# endif
2231
2232 if (RT_LIKELY( (pGuestReq->SCSIIO.u8TargetID < pThis->cDeviceStates)
2233 && (pGuestReq->SCSIIO.u8Bus == 0)))
2234 {
2235 PLSILOGICDEVICE pTgtDev = &pThis->paDeviceStates[pGuestReq->SCSIIO.u8TargetID];
2236
2237 if (pTgtDev->pDrvBase)
2238 {
2239 /* Allocate and prepare a new request. */
2240 PDMMEDIAEXIOREQ hIoReq;
2241 PLSILOGICREQ pLsiReq = NULL;
2242 rc = pTgtDev->pDrvMediaEx->pfnIoReqAlloc(pTgtDev->pDrvMediaEx, &hIoReq, (void **)&pLsiReq,
2243 pGuestReq->SCSIIO.u32MessageContext,
2244 PDMIMEDIAEX_F_SUSPEND_ON_RECOVERABLE_ERR);
2245 if (RT_SUCCESS(rc))
2246 {
2247 pLsiReq->hIoReq = hIoReq;
2248 pLsiReq->pTargetDevice = pTgtDev;
2249 pLsiReq->GCPhysMessageFrameAddr = GCPhysMessageFrameAddr;
2250 pLsiReq->fBIOS = false;
2251 pLsiReq->GCPhysSgStart = GCPhysMessageFrameAddr + sizeof(MptSCSIIORequest);
2252 pLsiReq->cChainOffset = pGuestReq->SCSIIO.u8ChainOffset;
2253 if (pLsiReq->cChainOffset)
2254 pLsiReq->cChainOffset = pLsiReq->cChainOffset * sizeof(uint32_t) - sizeof(MptSCSIIORequest);
2255 memcpy(&pLsiReq->GuestRequest, pGuestReq, sizeof(MptRequestUnion));
2256 RT_BZERO(&pLsiReq->abSenseBuffer[0], sizeof(pLsiReq->abSenseBuffer));
2257
2258 PDMMEDIAEXIOREQSCSITXDIR enmXferDir = PDMMEDIAEXIOREQSCSITXDIR_UNKNOWN;
2259 uint8_t uDataDirection = MPT_SCSIIO_REQUEST_CONTROL_TXDIR_GET(pLsiReq->GuestRequest.SCSIIO.u32Control);
2260
2261 /*
2262 * Keep the direction to unknown if there is a mismatch between the data length
2263 * and the transfer direction bit.
2264 * The Solaris 9 driver is buggy and sets it to none for INQUIRY requests.
2265 */
2266 if ( uDataDirection == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_NONE
2267 && pLsiReq->GuestRequest.SCSIIO.u32DataLength == 0)
2268 enmXferDir = PDMMEDIAEXIOREQSCSITXDIR_NONE;
2269 else if (uDataDirection == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_WRITE)
2270 enmXferDir = PDMMEDIAEXIOREQSCSITXDIR_TO_DEVICE;
2271 else if (uDataDirection == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_READ)
2272 enmXferDir = PDMMEDIAEXIOREQSCSITXDIR_FROM_DEVICE;
2273
2274 ASMAtomicIncU32(&pTgtDev->cOutstandingRequests);
2275 rc = pTgtDev->pDrvMediaEx->pfnIoReqSendScsiCmd(pTgtDev->pDrvMediaEx, pLsiReq->hIoReq, pLsiReq->GuestRequest.SCSIIO.au8LUN[1],
2276 &pLsiReq->GuestRequest.SCSIIO.au8CDB[0], pLsiReq->GuestRequest.SCSIIO.u8CDBLength,
2277 enmXferDir, pLsiReq->GuestRequest.SCSIIO.u32DataLength,
2278 &pLsiReq->abSenseBuffer[0], sizeof(pLsiReq->abSenseBuffer), &pLsiReq->u8ScsiSts,
2279 30 * RT_MS_1SEC);
2280 if (rc != VINF_PDM_MEDIAEX_IOREQ_IN_PROGRESS)
2281 lsilogicR3ReqComplete(pThis, pLsiReq, rc);
2282
2283 return VINF_SUCCESS;
2284 }
2285 else
2286 IOCReply.SCSIIOError.u16IOCStatus = MPT_SCSI_IO_ERROR_IOCSTATUS_DEVICE_NOT_THERE;
2287 }
2288 else
2289 {
2290 /* Device is not present report SCSI selection timeout. */
2291 IOCReply.SCSIIOError.u16IOCStatus = MPT_SCSI_IO_ERROR_IOCSTATUS_DEVICE_NOT_THERE;
2292 }
2293 }
2294 else
2295 {
2296 /* Report out of bounds target ID or bus. */
2297 if (pGuestReq->SCSIIO.u8Bus != 0)
2298 IOCReply.SCSIIOError.u16IOCStatus = MPT_SCSI_IO_ERROR_IOCSTATUS_INVALID_BUS;
2299 else
2300 IOCReply.SCSIIOError.u16IOCStatus = MPT_SCSI_IO_ERROR_IOCSTATUS_INVALID_TARGETID;
2301 }
2302
2303 static int g_cLogged = 0;
2304
2305 if (g_cLogged++ < MAX_REL_LOG_ERRORS)
2306 {
2307 LogRel(("LsiLogic#%d: %d/%d (Bus/Target) doesn't exist\n", pThis->CTX_SUFF(pDevIns)->iInstance,
2308 pGuestReq->SCSIIO.u8TargetID, pGuestReq->SCSIIO.u8Bus));
2309 /* Log the CDB too */
2310 LogRel(("LsiLogic#%d: Guest issued CDB {%#x",
2311 pThis->CTX_SUFF(pDevIns)->iInstance, pGuestReq->SCSIIO.au8CDB[0]));
2312 for (unsigned i = 1; i < pGuestReq->SCSIIO.u8CDBLength; i++)
2313 LogRel((", %#x", pGuestReq->SCSIIO.au8CDB[i]));
2314 LogRel(("}\n"));
2315 }
2316
2317 /* The rest is equal to both errors. */
2318 IOCReply.SCSIIOError.u8TargetID = pGuestReq->SCSIIO.u8TargetID;
2319 IOCReply.SCSIIOError.u8Bus = pGuestReq->SCSIIO.u8Bus;
2320 IOCReply.SCSIIOError.u8MessageLength = sizeof(MptSCSIIOErrorReply) / 4;
2321 IOCReply.SCSIIOError.u8Function = pGuestReq->SCSIIO.u8Function;
2322 IOCReply.SCSIIOError.u8CDBLength = pGuestReq->SCSIIO.u8CDBLength;
2323 IOCReply.SCSIIOError.u8SenseBufferLength = pGuestReq->SCSIIO.u8SenseBufferLength;
2324 IOCReply.SCSIIOError.u32MessageContext = pGuestReq->SCSIIO.u32MessageContext;
2325 IOCReply.SCSIIOError.u8SCSIStatus = SCSI_STATUS_OK;
2326 IOCReply.SCSIIOError.u8SCSIState = MPT_SCSI_IO_ERROR_SCSI_STATE_TERMINATED;
2327 IOCReply.SCSIIOError.u32IOCLogInfo = 0;
2328 IOCReply.SCSIIOError.u32TransferCount = 0;
2329 IOCReply.SCSIIOError.u32SenseCount = 0;
2330 IOCReply.SCSIIOError.u32ResponseInfo = 0;
2331
2332 lsilogicFinishAddressReply(pThis, &IOCReply, false);
2333
2334 return rc;
2335}
2336
2337
2338/**
2339 * @interface_method_impl{PDMIMEDIAPORT,pfnQueryDeviceLocation}
2340 */
2341static DECLCALLBACK(int) lsilogicR3QueryDeviceLocation(PPDMIMEDIAPORT pInterface, const char **ppcszController,
2342 uint32_t *piInstance, uint32_t *piLUN)
2343{
2344 PLSILOGICDEVICE pTgtDev = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, IMediaPort);
2345 PPDMDEVINS pDevIns = pTgtDev->CTX_SUFF(pLsiLogic)->CTX_SUFF(pDevIns);
2346
2347 AssertPtrReturn(ppcszController, VERR_INVALID_POINTER);
2348 AssertPtrReturn(piInstance, VERR_INVALID_POINTER);
2349 AssertPtrReturn(piLUN, VERR_INVALID_POINTER);
2350
2351 *ppcszController = pDevIns->pReg->szName;
2352 *piInstance = pDevIns->iInstance;
2353 *piLUN = pTgtDev->iLUN;
2354
2355 return VINF_SUCCESS;
2356}
2357
2358
2359/**
2360 * @interface_method_impl{PDMIMEDIAEXPORT,pfnIoReqCopyFromBuf}
2361 */
2362static DECLCALLBACK(int) lsilogicR3IoReqCopyFromBuf(PPDMIMEDIAEXPORT pInterface, PDMMEDIAEXIOREQ hIoReq,
2363 void *pvIoReqAlloc, uint32_t offDst, PRTSGBUF pSgBuf,
2364 size_t cbCopy)
2365{
2366 RT_NOREF1(hIoReq);
2367 PLSILOGICDEVICE pTgtDev = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, IMediaExPort);
2368 PLSILOGICREQ pReq = (PLSILOGICREQ)pvIoReqAlloc;
2369
2370 size_t cbCopied = 0;
2371 if (RT_UNLIKELY(pReq->fBIOS))
2372 cbCopied = vboxscsiCopyToBuf(&pTgtDev->CTX_SUFF(pLsiLogic)->VBoxSCSI, pSgBuf, offDst, cbCopy);
2373 else
2374 cbCopied = lsilogicR3CopySgBufToGuest(pTgtDev->CTX_SUFF(pLsiLogic), pReq, pSgBuf, offDst, cbCopy);
2375 return cbCopied == cbCopy ? VINF_SUCCESS : VERR_PDM_MEDIAEX_IOBUF_OVERFLOW;
2376}
2377
2378/**
2379 * @interface_method_impl{PDMIMEDIAEXPORT,pfnIoReqCopyToBuf}
2380 */
2381static DECLCALLBACK(int) lsilogicR3IoReqCopyToBuf(PPDMIMEDIAEXPORT pInterface, PDMMEDIAEXIOREQ hIoReq,
2382 void *pvIoReqAlloc, uint32_t offSrc, PRTSGBUF pSgBuf,
2383 size_t cbCopy)
2384{
2385 RT_NOREF1(hIoReq);
2386 PLSILOGICDEVICE pTgtDev = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, IMediaExPort);
2387 PLSILOGICREQ pReq = (PLSILOGICREQ)pvIoReqAlloc;
2388
2389 size_t cbCopied = 0;
2390 if (RT_UNLIKELY(pReq->fBIOS))
2391 cbCopied = vboxscsiCopyFromBuf(&pTgtDev->CTX_SUFF(pLsiLogic)->VBoxSCSI, pSgBuf, offSrc, cbCopy);
2392 else
2393 cbCopied = lsilogicR3CopySgBufFromGuest(pTgtDev->CTX_SUFF(pLsiLogic), pReq, pSgBuf, offSrc, cbCopy);
2394 return cbCopied == cbCopy ? VINF_SUCCESS : VERR_PDM_MEDIAEX_IOBUF_UNDERRUN;
2395}
2396
2397/**
2398 * @interface_method_impl{PDMIMEDIAEXPORT,pfnIoReqCompleteNotify}
2399 */
2400static DECLCALLBACK(int) lsilogicR3IoReqCompleteNotify(PPDMIMEDIAEXPORT pInterface, PDMMEDIAEXIOREQ hIoReq,
2401 void *pvIoReqAlloc, int rcReq)
2402{
2403 RT_NOREF(hIoReq);
2404 PLSILOGICDEVICE pTgtDev = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, IMediaExPort);
2405 lsilogicR3ReqComplete(pTgtDev->CTX_SUFF(pLsiLogic), (PLSILOGICREQ)pvIoReqAlloc, rcReq);
2406 return VINF_SUCCESS;
2407}
2408
2409/**
2410 * @interface_method_impl{PDMIMEDIAEXPORT,pfnIoReqStateChanged}
2411 */
2412static DECLCALLBACK(void) lsilogicR3IoReqStateChanged(PPDMIMEDIAEXPORT pInterface, PDMMEDIAEXIOREQ hIoReq,
2413 void *pvIoReqAlloc, PDMMEDIAEXIOREQSTATE enmState)
2414{
2415 RT_NOREF3(hIoReq, pvIoReqAlloc, enmState);
2416 PLSILOGICDEVICE pTgtDev = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, IMediaExPort);
2417
2418 switch (enmState)
2419 {
2420 case PDMMEDIAEXIOREQSTATE_SUSPENDED:
2421 {
2422 /* Make sure the request is not accounted for so the VM can suspend successfully. */
2423 uint32_t cTasksActive = ASMAtomicDecU32(&pTgtDev->cOutstandingRequests);
2424 if (!cTasksActive && pTgtDev->CTX_SUFF(pLsiLogic)->fSignalIdle)
2425 PDMDevHlpAsyncNotificationCompleted(pTgtDev->CTX_SUFF(pLsiLogic)->pDevInsR3);
2426 break;
2427 }
2428 case PDMMEDIAEXIOREQSTATE_ACTIVE:
2429 /* Make sure the request is accounted for so the VM suspends only when the request is complete. */
2430 ASMAtomicIncU32(&pTgtDev->cOutstandingRequests);
2431 break;
2432 default:
2433 AssertMsgFailed(("Invalid request state given %u\n", enmState));
2434 }
2435}
2436
2437/**
2438 * @interface_method_impl{PDMIMEDIAEXPORT,pfnMediumEjected}
2439 */
2440static DECLCALLBACK(void) lsilogicR3MediumEjected(PPDMIMEDIAEXPORT pInterface)
2441{
2442 PLSILOGICDEVICE pTgtDev = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, IMediaExPort);
2443 PLSILOGICSCSI pThis = pTgtDev->CTX_SUFF(pLsiLogic);
2444
2445 if (pThis->pMediaNotify)
2446 {
2447 int rc = VMR3ReqCallNoWait(PDMDevHlpGetVM(pThis->CTX_SUFF(pDevIns)), VMCPUID_ANY,
2448 (PFNRT)pThis->pMediaNotify->pfnEjected, 2,
2449 pThis->pMediaNotify, pTgtDev->iLUN);
2450 AssertRC(rc);
2451 }
2452}
2453
2454
2455/**
2456 * Return the configuration page header and data
2457 * which matches the given page type and number.
2458 *
2459 * @returns VINF_SUCCESS if successful
2460 * VERR_NOT_FOUND if the requested page could be found.
2461 * @param pThis The LsiLogic controller instance data.
2462 * @param pPages The pages supported by the controller.
2463 * @param u8PageNumber Number of the page to get.
2464 * @param ppPageHeader Where to store the pointer to the page header.
2465 * @param ppbPageData Where to store the pointer to the page data.
2466 * @param pcbPage Where to store the size of the page data in bytes on success.
2467 */
2468static int lsilogicR3ConfigurationIOUnitPageGetFromNumber(PLSILOGICSCSI pThis,
2469 PMptConfigurationPagesSupported pPages,
2470 uint8_t u8PageNumber,
2471 PMptConfigurationPageHeader *ppPageHeader,
2472 uint8_t **ppbPageData, size_t *pcbPage)
2473{
2474 RT_NOREF(pThis);
2475 int rc = VINF_SUCCESS;
2476
2477 AssertPtr(ppPageHeader); Assert(ppbPageData);
2478
2479 switch (u8PageNumber)
2480 {
2481 case 0:
2482 *ppPageHeader = &pPages->IOUnitPage0.u.fields.Header;
2483 *ppbPageData = pPages->IOUnitPage0.u.abPageData;
2484 *pcbPage = sizeof(pPages->IOUnitPage0);
2485 break;
2486 case 1:
2487 *ppPageHeader = &pPages->IOUnitPage1.u.fields.Header;
2488 *ppbPageData = pPages->IOUnitPage1.u.abPageData;
2489 *pcbPage = sizeof(pPages->IOUnitPage1);
2490 break;
2491 case 2:
2492 *ppPageHeader = &pPages->IOUnitPage2.u.fields.Header;
2493 *ppbPageData = pPages->IOUnitPage2.u.abPageData;
2494 *pcbPage = sizeof(pPages->IOUnitPage2);
2495 break;
2496 case 3:
2497 *ppPageHeader = &pPages->IOUnitPage3.u.fields.Header;
2498 *ppbPageData = pPages->IOUnitPage3.u.abPageData;
2499 *pcbPage = sizeof(pPages->IOUnitPage3);
2500 break;
2501 case 4:
2502 *ppPageHeader = &pPages->IOUnitPage4.u.fields.Header;
2503 *ppbPageData = pPages->IOUnitPage4.u.abPageData;
2504 *pcbPage = sizeof(pPages->IOUnitPage4);
2505 break;
2506 default:
2507 rc = VERR_NOT_FOUND;
2508 }
2509
2510 return rc;
2511}
2512
2513/**
2514 * Return the configuration page header and data
2515 * which matches the given page type and number.
2516 *
2517 * @returns VINF_SUCCESS if successful
2518 * VERR_NOT_FOUND if the requested page could be found.
2519 * @param pThis The LsiLogic controller instance data.
2520 * @param pPages The pages supported by the controller.
2521 * @param u8PageNumber Number of the page to get.
2522 * @param ppPageHeader Where to store the pointer to the page header.
2523 * @param ppbPageData Where to store the pointer to the page data.
2524 * @param pcbPage Where to store the size of the page data in bytes on success.
2525 */
2526static int lsilogicR3ConfigurationIOCPageGetFromNumber(PLSILOGICSCSI pThis,
2527 PMptConfigurationPagesSupported pPages,
2528 uint8_t u8PageNumber,
2529 PMptConfigurationPageHeader *ppPageHeader,
2530 uint8_t **ppbPageData, size_t *pcbPage)
2531{
2532 RT_NOREF(pThis);
2533 int rc = VINF_SUCCESS;
2534
2535 AssertPtr(ppPageHeader); Assert(ppbPageData);
2536
2537 switch (u8PageNumber)
2538 {
2539 case 0:
2540 *ppPageHeader = &pPages->IOCPage0.u.fields.Header;
2541 *ppbPageData = pPages->IOCPage0.u.abPageData;
2542 *pcbPage = sizeof(pPages->IOCPage0);
2543 break;
2544 case 1:
2545 *ppPageHeader = &pPages->IOCPage1.u.fields.Header;
2546 *ppbPageData = pPages->IOCPage1.u.abPageData;
2547 *pcbPage = sizeof(pPages->IOCPage1);
2548 break;
2549 case 2:
2550 *ppPageHeader = &pPages->IOCPage2.u.fields.Header;
2551 *ppbPageData = pPages->IOCPage2.u.abPageData;
2552 *pcbPage = sizeof(pPages->IOCPage2);
2553 break;
2554 case 3:
2555 *ppPageHeader = &pPages->IOCPage3.u.fields.Header;
2556 *ppbPageData = pPages->IOCPage3.u.abPageData;
2557 *pcbPage = sizeof(pPages->IOCPage3);
2558 break;
2559 case 4:
2560 *ppPageHeader = &pPages->IOCPage4.u.fields.Header;
2561 *ppbPageData = pPages->IOCPage4.u.abPageData;
2562 *pcbPage = sizeof(pPages->IOCPage4);
2563 break;
2564 case 6:
2565 *ppPageHeader = &pPages->IOCPage6.u.fields.Header;
2566 *ppbPageData = pPages->IOCPage6.u.abPageData;
2567 *pcbPage = sizeof(pPages->IOCPage6);
2568 break;
2569 default:
2570 rc = VERR_NOT_FOUND;
2571 }
2572
2573 return rc;
2574}
2575
2576/**
2577 * Return the configuration page header and data
2578 * which matches the given page type and number.
2579 *
2580 * @returns VINF_SUCCESS if successful
2581 * VERR_NOT_FOUND if the requested page could be found.
2582 * @param pThis The LsiLogic controller instance data.
2583 * @param pPages The pages supported by the controller.
2584 * @param u8PageNumber Number of the page to get.
2585 * @param ppPageHeader Where to store the pointer to the page header.
2586 * @param ppbPageData Where to store the pointer to the page data.
2587 * @param pcbPage Where to store the size of the page data in bytes on success.
2588 */
2589static int lsilogicR3ConfigurationManufacturingPageGetFromNumber(PLSILOGICSCSI pThis,
2590 PMptConfigurationPagesSupported pPages,
2591 uint8_t u8PageNumber,
2592 PMptConfigurationPageHeader *ppPageHeader,
2593 uint8_t **ppbPageData, size_t *pcbPage)
2594{
2595 int rc = VINF_SUCCESS;
2596
2597 AssertPtr(ppPageHeader); Assert(ppbPageData);
2598
2599 switch (u8PageNumber)
2600 {
2601 case 0:
2602 *ppPageHeader = &pPages->ManufacturingPage0.u.fields.Header;
2603 *ppbPageData = pPages->ManufacturingPage0.u.abPageData;
2604 *pcbPage = sizeof(pPages->ManufacturingPage0);
2605 break;
2606 case 1:
2607 *ppPageHeader = &pPages->ManufacturingPage1.u.fields.Header;
2608 *ppbPageData = pPages->ManufacturingPage1.u.abPageData;
2609 *pcbPage = sizeof(pPages->ManufacturingPage1);
2610 break;
2611 case 2:
2612 *ppPageHeader = &pPages->ManufacturingPage2.u.fields.Header;
2613 *ppbPageData = pPages->ManufacturingPage2.u.abPageData;
2614 *pcbPage = sizeof(pPages->ManufacturingPage2);
2615 break;
2616 case 3:
2617 *ppPageHeader = &pPages->ManufacturingPage3.u.fields.Header;
2618 *ppbPageData = pPages->ManufacturingPage3.u.abPageData;
2619 *pcbPage = sizeof(pPages->ManufacturingPage3);
2620 break;
2621 case 4:
2622 *ppPageHeader = &pPages->ManufacturingPage4.u.fields.Header;
2623 *ppbPageData = pPages->ManufacturingPage4.u.abPageData;
2624 *pcbPage = sizeof(pPages->ManufacturingPage4);
2625 break;
2626 case 5:
2627 *ppPageHeader = &pPages->ManufacturingPage5.u.fields.Header;
2628 *ppbPageData = pPages->ManufacturingPage5.u.abPageData;
2629 *pcbPage = sizeof(pPages->ManufacturingPage5);
2630 break;
2631 case 6:
2632 *ppPageHeader = &pPages->ManufacturingPage6.u.fields.Header;
2633 *ppbPageData = pPages->ManufacturingPage6.u.abPageData;
2634 *pcbPage = sizeof(pPages->ManufacturingPage6);
2635 break;
2636 case 7:
2637 if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
2638 {
2639 *ppPageHeader = &pPages->u.SasPages.pManufacturingPage7->u.fields.Header;
2640 *ppbPageData = pPages->u.SasPages.pManufacturingPage7->u.abPageData;
2641 *pcbPage = pPages->u.SasPages.cbManufacturingPage7;
2642 }
2643 else
2644 rc = VERR_NOT_FOUND;
2645 break;
2646 case 8:
2647 *ppPageHeader = &pPages->ManufacturingPage8.u.fields.Header;
2648 *ppbPageData = pPages->ManufacturingPage8.u.abPageData;
2649 *pcbPage = sizeof(pPages->ManufacturingPage8);
2650 break;
2651 case 9:
2652 *ppPageHeader = &pPages->ManufacturingPage9.u.fields.Header;
2653 *ppbPageData = pPages->ManufacturingPage9.u.abPageData;
2654 *pcbPage = sizeof(pPages->ManufacturingPage9);
2655 break;
2656 case 10:
2657 *ppPageHeader = &pPages->ManufacturingPage10.u.fields.Header;
2658 *ppbPageData = pPages->ManufacturingPage10.u.abPageData;
2659 *pcbPage = sizeof(pPages->ManufacturingPage10);
2660 break;
2661 default:
2662 rc = VERR_NOT_FOUND;
2663 }
2664
2665 return rc;
2666}
2667
2668/**
2669 * Return the configuration page header and data
2670 * which matches the given page type and number.
2671 *
2672 * @returns VINF_SUCCESS if successful
2673 * VERR_NOT_FOUND if the requested page could be found.
2674 * @param pThis The LsiLogic controller instance data.
2675 * @param pPages The pages supported by the controller.
2676 * @param u8PageNumber Number of the page to get.
2677 * @param ppPageHeader Where to store the pointer to the page header.
2678 * @param ppbPageData Where to store the pointer to the page data.
2679 * @param pcbPage Where to store the size of the page data in bytes on success.
2680 */
2681static int lsilogicR3ConfigurationBiosPageGetFromNumber(PLSILOGICSCSI pThis,
2682 PMptConfigurationPagesSupported pPages,
2683 uint8_t u8PageNumber,
2684 PMptConfigurationPageHeader *ppPageHeader,
2685 uint8_t **ppbPageData, size_t *pcbPage)
2686{
2687 RT_NOREF(pThis);
2688 int rc = VINF_SUCCESS;
2689
2690 AssertPtr(ppPageHeader); Assert(ppbPageData);
2691
2692 switch (u8PageNumber)
2693 {
2694 case 1:
2695 *ppPageHeader = &pPages->BIOSPage1.u.fields.Header;
2696 *ppbPageData = pPages->BIOSPage1.u.abPageData;
2697 *pcbPage = sizeof(pPages->BIOSPage1);
2698 break;
2699 case 2:
2700 *ppPageHeader = &pPages->BIOSPage2.u.fields.Header;
2701 *ppbPageData = pPages->BIOSPage2.u.abPageData;
2702 *pcbPage = sizeof(pPages->BIOSPage2);
2703 break;
2704 case 4:
2705 *ppPageHeader = &pPages->BIOSPage4.u.fields.Header;
2706 *ppbPageData = pPages->BIOSPage4.u.abPageData;
2707 *pcbPage = sizeof(pPages->BIOSPage4);
2708 break;
2709 default:
2710 rc = VERR_NOT_FOUND;
2711 }
2712
2713 return rc;
2714}
2715
2716/**
2717 * Return the configuration page header and data
2718 * which matches the given page type and number.
2719 *
2720 * @returns VINF_SUCCESS if successful
2721 * VERR_NOT_FOUND if the requested page could be found.
2722 * @param pThis The LsiLogic controller instance data.
2723 * @param pPages The pages supported by the controller.
2724 * @param u8Port The port to retrieve the page for.
2725 * @param u8PageNumber Number of the page to get.
2726 * @param ppPageHeader Where to store the pointer to the page header.
2727 * @param ppbPageData Where to store the pointer to the page data.
2728 * @param pcbPage Where to store the size of the page data in bytes on success.
2729 */
2730static int lsilogicR3ConfigurationSCSISPIPortPageGetFromNumber(PLSILOGICSCSI pThis,
2731 PMptConfigurationPagesSupported pPages,
2732 uint8_t u8Port,
2733 uint8_t u8PageNumber,
2734 PMptConfigurationPageHeader *ppPageHeader,
2735 uint8_t **ppbPageData, size_t *pcbPage)
2736{
2737 RT_NOREF(pThis);
2738 int rc = VINF_SUCCESS;
2739 AssertPtr(ppPageHeader); Assert(ppbPageData);
2740
2741
2742 if (u8Port >= RT_ELEMENTS(pPages->u.SpiPages.aPortPages))
2743 return VERR_NOT_FOUND;
2744
2745 switch (u8PageNumber)
2746 {
2747 case 0:
2748 *ppPageHeader = &pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage0.u.fields.Header;
2749 *ppbPageData = pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage0.u.abPageData;
2750 *pcbPage = sizeof(pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage0);
2751 break;
2752 case 1:
2753 *ppPageHeader = &pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage1.u.fields.Header;
2754 *ppbPageData = pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage1.u.abPageData;
2755 *pcbPage = sizeof(pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage1);
2756 break;
2757 case 2:
2758 *ppPageHeader = &pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage2.u.fields.Header;
2759 *ppbPageData = pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage2.u.abPageData;
2760 *pcbPage = sizeof(pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage2);
2761 break;
2762 default:
2763 rc = VERR_NOT_FOUND;
2764 }
2765
2766 return rc;
2767}
2768
2769/**
2770 * Return the configuration page header and data
2771 * which matches the given page type and number.
2772 *
2773 * @returns VINF_SUCCESS if successful
2774 * VERR_NOT_FOUND if the requested page could be found.
2775 * @param pThis The LsiLogic controller instance data.
2776 * @param pPages The pages supported by the controller.
2777 * @param u8Bus The bus the device is on the page should be returned.
2778 * @param u8TargetID The target ID of the device to return the page for.
2779 * @param u8PageNumber Number of the page to get.
2780 * @param ppPageHeader Where to store the pointer to the page header.
2781 * @param ppbPageData Where to store the pointer to the page data.
2782 * @param pcbPage Where to store the size of the page data in bytes on success.
2783 */
2784static int lsilogicR3ConfigurationSCSISPIDevicePageGetFromNumber(PLSILOGICSCSI pThis,
2785 PMptConfigurationPagesSupported pPages,
2786 uint8_t u8Bus,
2787 uint8_t u8TargetID, uint8_t u8PageNumber,
2788 PMptConfigurationPageHeader *ppPageHeader,
2789 uint8_t **ppbPageData, size_t *pcbPage)
2790{
2791 RT_NOREF(pThis);
2792 int rc = VINF_SUCCESS;
2793 AssertPtr(ppPageHeader); Assert(ppbPageData);
2794
2795 if (u8Bus >= RT_ELEMENTS(pPages->u.SpiPages.aBuses))
2796 return VERR_NOT_FOUND;
2797
2798 if (u8TargetID >= RT_ELEMENTS(pPages->u.SpiPages.aBuses[u8Bus].aDevicePages))
2799 return VERR_NOT_FOUND;
2800
2801 switch (u8PageNumber)
2802 {
2803 case 0:
2804 *ppPageHeader = &pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage0.u.fields.Header;
2805 *ppbPageData = pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage0.u.abPageData;
2806 *pcbPage = sizeof(pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage0);
2807 break;
2808 case 1:
2809 *ppPageHeader = &pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage1.u.fields.Header;
2810 *ppbPageData = pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage1.u.abPageData;
2811 *pcbPage = sizeof(pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage1);
2812 break;
2813 case 2:
2814 *ppPageHeader = &pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage2.u.fields.Header;
2815 *ppbPageData = pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage2.u.abPageData;
2816 *pcbPage = sizeof(pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage2);
2817 break;
2818 case 3:
2819 *ppPageHeader = &pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage3.u.fields.Header;
2820 *ppbPageData = pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage3.u.abPageData;
2821 *pcbPage = sizeof(pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage3);
2822 break;
2823 default:
2824 rc = VERR_NOT_FOUND;
2825 }
2826
2827 return rc;
2828}
2829
2830static int lsilogicR3ConfigurationSASIOUnitPageGetFromNumber(PLSILOGICSCSI pThis,
2831 PMptConfigurationPagesSupported pPages,
2832 uint8_t u8PageNumber,
2833 PMptExtendedConfigurationPageHeader *ppPageHeader,
2834 uint8_t **ppbPageData, size_t *pcbPage)
2835{
2836 RT_NOREF(pThis);
2837 int rc = VINF_SUCCESS;
2838
2839 switch (u8PageNumber)
2840 {
2841 case 0:
2842 *ppPageHeader = &pPages->u.SasPages.pSASIOUnitPage0->u.fields.ExtHeader;
2843 *ppbPageData = pPages->u.SasPages.pSASIOUnitPage0->u.abPageData;
2844 *pcbPage = pPages->u.SasPages.cbSASIOUnitPage0;
2845 break;
2846 case 1:
2847 *ppPageHeader = &pPages->u.SasPages.pSASIOUnitPage1->u.fields.ExtHeader;
2848 *ppbPageData = pPages->u.SasPages.pSASIOUnitPage1->u.abPageData;
2849 *pcbPage = pPages->u.SasPages.cbSASIOUnitPage1;
2850 break;
2851 case 2:
2852 *ppPageHeader = &pPages->u.SasPages.SASIOUnitPage2.u.fields.ExtHeader;
2853 *ppbPageData = pPages->u.SasPages.SASIOUnitPage2.u.abPageData;
2854 *pcbPage = sizeof(pPages->u.SasPages.SASIOUnitPage2);
2855 break;
2856 case 3:
2857 *ppPageHeader = &pPages->u.SasPages.SASIOUnitPage3.u.fields.ExtHeader;
2858 *ppbPageData = pPages->u.SasPages.SASIOUnitPage3.u.abPageData;
2859 *pcbPage = sizeof(pPages->u.SasPages.SASIOUnitPage3);
2860 break;
2861 default:
2862 rc = VERR_NOT_FOUND;
2863 }
2864
2865 return rc;
2866}
2867
2868static int lsilogicR3ConfigurationSASPHYPageGetFromNumber(PLSILOGICSCSI pThis,
2869 PMptConfigurationPagesSupported pPages,
2870 uint8_t u8PageNumber,
2871 MptConfigurationPageAddress PageAddress,
2872 PMptExtendedConfigurationPageHeader *ppPageHeader,
2873 uint8_t **ppbPageData, size_t *pcbPage)
2874{
2875 RT_NOREF(pThis);
2876 int rc = VINF_SUCCESS;
2877 uint8_t uAddressForm = MPT_CONFIGURATION_PAGE_ADDRESS_GET_SAS_FORM(PageAddress);
2878 PMptConfigurationPagesSas pPagesSas = &pPages->u.SasPages;
2879 PMptPHY pPHYPages = NULL;
2880
2881 Log(("Address form %d\n", uAddressForm));
2882
2883 if (uAddressForm == 0) /* PHY number */
2884 {
2885 uint8_t u8PhyNumber = PageAddress.SASPHY.Form0.u8PhyNumber;
2886
2887 Log(("PHY number %d\n", u8PhyNumber));
2888
2889 if (u8PhyNumber >= pPagesSas->cPHYs)
2890 return VERR_NOT_FOUND;
2891
2892 pPHYPages = &pPagesSas->paPHYs[u8PhyNumber];
2893 }
2894 else if (uAddressForm == 1) /* Index form */
2895 {
2896 uint16_t u16Index = PageAddress.SASPHY.Form1.u16Index;
2897
2898 Log(("PHY index %d\n", u16Index));
2899
2900 if (u16Index >= pPagesSas->cPHYs)
2901 return VERR_NOT_FOUND;
2902
2903 pPHYPages = &pPagesSas->paPHYs[u16Index];
2904 }
2905 else
2906 rc = VERR_NOT_FOUND; /* Correct? */
2907
2908 if (pPHYPages)
2909 {
2910 switch (u8PageNumber)
2911 {
2912 case 0:
2913 *ppPageHeader = &pPHYPages->SASPHYPage0.u.fields.ExtHeader;
2914 *ppbPageData = pPHYPages->SASPHYPage0.u.abPageData;
2915 *pcbPage = sizeof(pPHYPages->SASPHYPage0);
2916 break;
2917 case 1:
2918 *ppPageHeader = &pPHYPages->SASPHYPage1.u.fields.ExtHeader;
2919 *ppbPageData = pPHYPages->SASPHYPage1.u.abPageData;
2920 *pcbPage = sizeof(pPHYPages->SASPHYPage1);
2921 break;
2922 default:
2923 rc = VERR_NOT_FOUND;
2924 }
2925 }
2926 else
2927 rc = VERR_NOT_FOUND;
2928
2929 return rc;
2930}
2931
2932static int lsilogicR3ConfigurationSASDevicePageGetFromNumber(PLSILOGICSCSI pThis,
2933 PMptConfigurationPagesSupported pPages,
2934 uint8_t u8PageNumber,
2935 MptConfigurationPageAddress PageAddress,
2936 PMptExtendedConfigurationPageHeader *ppPageHeader,
2937 uint8_t **ppbPageData, size_t *pcbPage)
2938{
2939 RT_NOREF(pThis);
2940 int rc = VINF_SUCCESS;
2941 uint8_t uAddressForm = MPT_CONFIGURATION_PAGE_ADDRESS_GET_SAS_FORM(PageAddress);
2942 PMptConfigurationPagesSas pPagesSas = &pPages->u.SasPages;
2943 PMptSASDevice pSASDevice = NULL;
2944
2945 Log(("Address form %d\n", uAddressForm));
2946
2947 if (uAddressForm == 0)
2948 {
2949 uint16_t u16Handle = PageAddress.SASDevice.Form0And2.u16Handle;
2950
2951 Log(("Get next handle %#x\n", u16Handle));
2952
2953 pSASDevice = pPagesSas->pSASDeviceHead;
2954
2955 /* Get the first device? */
2956 if (u16Handle != 0xffff)
2957 {
2958 /* No, search for the right one. */
2959
2960 while ( pSASDevice
2961 && pSASDevice->SASDevicePage0.u.fields.u16DevHandle != u16Handle)
2962 pSASDevice = pSASDevice->pNext;
2963
2964 if (pSASDevice)
2965 pSASDevice = pSASDevice->pNext;
2966 }
2967 }
2968 else if (uAddressForm == 1)
2969 {
2970 uint8_t u8TargetID = PageAddress.SASDevice.Form1.u8TargetID;
2971 uint8_t u8Bus = PageAddress.SASDevice.Form1.u8Bus;
2972
2973 Log(("u8TargetID=%d u8Bus=%d\n", u8TargetID, u8Bus));
2974
2975 pSASDevice = pPagesSas->pSASDeviceHead;
2976
2977 while ( pSASDevice
2978 && ( pSASDevice->SASDevicePage0.u.fields.u8TargetID != u8TargetID
2979 || pSASDevice->SASDevicePage0.u.fields.u8Bus != u8Bus))
2980 pSASDevice = pSASDevice->pNext;
2981 }
2982 else if (uAddressForm == 2)
2983 {
2984 uint16_t u16Handle = PageAddress.SASDevice.Form0And2.u16Handle;
2985
2986 Log(("Handle %#x\n", u16Handle));
2987
2988 pSASDevice = pPagesSas->pSASDeviceHead;
2989
2990 while ( pSASDevice
2991 && pSASDevice->SASDevicePage0.u.fields.u16DevHandle != u16Handle)
2992 pSASDevice = pSASDevice->pNext;
2993 }
2994
2995 if (pSASDevice)
2996 {
2997 switch (u8PageNumber)
2998 {
2999 case 0:
3000 *ppPageHeader = &pSASDevice->SASDevicePage0.u.fields.ExtHeader;
3001 *ppbPageData = pSASDevice->SASDevicePage0.u.abPageData;
3002 *pcbPage = sizeof(pSASDevice->SASDevicePage0);
3003 break;
3004 case 1:
3005 *ppPageHeader = &pSASDevice->SASDevicePage1.u.fields.ExtHeader;
3006 *ppbPageData = pSASDevice->SASDevicePage1.u.abPageData;
3007 *pcbPage = sizeof(pSASDevice->SASDevicePage1);
3008 break;
3009 case 2:
3010 *ppPageHeader = &pSASDevice->SASDevicePage2.u.fields.ExtHeader;
3011 *ppbPageData = pSASDevice->SASDevicePage2.u.abPageData;
3012 *pcbPage = sizeof(pSASDevice->SASDevicePage2);
3013 break;
3014 default:
3015 rc = VERR_NOT_FOUND;
3016 }
3017 }
3018 else
3019 rc = VERR_NOT_FOUND;
3020
3021 return rc;
3022}
3023
3024/**
3025 * Returns the extended configuration page header and data.
3026 * @returns VINF_SUCCESS if successful
3027 * VERR_NOT_FOUND if the requested page could be found.
3028 * @param pThis Pointer to the LsiLogic device state.
3029 * @param pConfigurationReq The configuration request.
3030 * @param ppPageHeader Where to return the pointer to the page header on success.
3031 * @param ppbPageData Where to store the pointer to the page data.
3032 * @param pcbPage Where to store the size of the page in bytes.
3033 */
3034static int lsilogicR3ConfigurationPageGetExtended(PLSILOGICSCSI pThis, PMptConfigurationRequest pConfigurationReq,
3035 PMptExtendedConfigurationPageHeader *ppPageHeader,
3036 uint8_t **ppbPageData, size_t *pcbPage)
3037{
3038 int rc = VINF_SUCCESS;
3039
3040 Log(("Extended page requested:\n"));
3041 Log(("u8ExtPageType=%#x\n", pConfigurationReq->u8ExtPageType));
3042 Log(("u8ExtPageLength=%d\n", pConfigurationReq->u16ExtPageLength));
3043
3044 switch (pConfigurationReq->u8ExtPageType)
3045 {
3046 case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT:
3047 {
3048 rc = lsilogicR3ConfigurationSASIOUnitPageGetFromNumber(pThis,
3049 pThis->pConfigurationPages,
3050 pConfigurationReq->u8PageNumber,
3051 ppPageHeader, ppbPageData, pcbPage);
3052 break;
3053 }
3054 case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASPHYS:
3055 {
3056 rc = lsilogicR3ConfigurationSASPHYPageGetFromNumber(pThis,
3057 pThis->pConfigurationPages,
3058 pConfigurationReq->u8PageNumber,
3059 pConfigurationReq->PageAddress,
3060 ppPageHeader, ppbPageData, pcbPage);
3061 break;
3062 }
3063 case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASDEVICE:
3064 {
3065 rc = lsilogicR3ConfigurationSASDevicePageGetFromNumber(pThis,
3066 pThis->pConfigurationPages,
3067 pConfigurationReq->u8PageNumber,
3068 pConfigurationReq->PageAddress,
3069 ppPageHeader, ppbPageData, pcbPage);
3070 break;
3071 }
3072 case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASEXPANDER: /* No expanders supported */
3073 case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_ENCLOSURE: /* No enclosures supported */
3074 default:
3075 rc = VERR_NOT_FOUND;
3076 }
3077
3078 return rc;
3079}
3080
3081/**
3082 * Processes a Configuration request.
3083 *
3084 * @returns VBox status code.
3085 * @param pThis Pointer to the LsiLogic device state.
3086 * @param pConfigurationReq Pointer to the request structure.
3087 * @param pReply Pointer to the reply message frame
3088 */
3089static int lsilogicR3ProcessConfigurationRequest(PLSILOGICSCSI pThis, PMptConfigurationRequest pConfigurationReq,
3090 PMptConfigurationReply pReply)
3091{
3092 int rc = VINF_SUCCESS;
3093 uint8_t *pbPageData = NULL;
3094 PMptConfigurationPageHeader pPageHeader = NULL;
3095 PMptExtendedConfigurationPageHeader pExtPageHeader = NULL;
3096 uint8_t u8PageType;
3097 uint8_t u8PageAttribute;
3098 size_t cbPage = 0;
3099
3100 LogFlowFunc(("pThis=%#p\n", pThis));
3101
3102 u8PageType = MPT_CONFIGURATION_PAGE_TYPE_GET(pConfigurationReq->u8PageType);
3103 u8PageAttribute = MPT_CONFIGURATION_PAGE_ATTRIBUTE_GET(pConfigurationReq->u8PageType);
3104
3105 Log(("GuestRequest:\n"));
3106 Log(("u8Action=%#x\n", pConfigurationReq->u8Action));
3107 Log(("u8PageType=%#x\n", u8PageType));
3108 Log(("u8PageNumber=%d\n", pConfigurationReq->u8PageNumber));
3109 Log(("u8PageLength=%d\n", pConfigurationReq->u8PageLength));
3110 Log(("u8PageVersion=%d\n", pConfigurationReq->u8PageVersion));
3111
3112 /* Copy common bits from the request into the reply. */
3113 pReply->u8MessageLength = 6; /* 6 32bit D-Words. */
3114 pReply->u8Action = pConfigurationReq->u8Action;
3115 pReply->u8Function = pConfigurationReq->u8Function;
3116 pReply->u32MessageContext = pConfigurationReq->u32MessageContext;
3117
3118 switch (u8PageType)
3119 {
3120 case MPT_CONFIGURATION_PAGE_TYPE_IO_UNIT:
3121 {
3122 /* Get the page data. */
3123 rc = lsilogicR3ConfigurationIOUnitPageGetFromNumber(pThis,
3124 pThis->pConfigurationPages,
3125 pConfigurationReq->u8PageNumber,
3126 &pPageHeader, &pbPageData, &cbPage);
3127 break;
3128 }
3129 case MPT_CONFIGURATION_PAGE_TYPE_IOC:
3130 {
3131 /* Get the page data. */
3132 rc = lsilogicR3ConfigurationIOCPageGetFromNumber(pThis,
3133 pThis->pConfigurationPages,
3134 pConfigurationReq->u8PageNumber,
3135 &pPageHeader, &pbPageData, &cbPage);
3136 break;
3137 }
3138 case MPT_CONFIGURATION_PAGE_TYPE_MANUFACTURING:
3139 {
3140 /* Get the page data. */
3141 rc = lsilogicR3ConfigurationManufacturingPageGetFromNumber(pThis,
3142 pThis->pConfigurationPages,
3143 pConfigurationReq->u8PageNumber,
3144 &pPageHeader, &pbPageData, &cbPage);
3145 break;
3146 }
3147 case MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_PORT:
3148 {
3149 /* Get the page data. */
3150 rc = lsilogicR3ConfigurationSCSISPIPortPageGetFromNumber(pThis,
3151 pThis->pConfigurationPages,
3152 pConfigurationReq->PageAddress.MPIPortNumber.u8PortNumber,
3153 pConfigurationReq->u8PageNumber,
3154 &pPageHeader, &pbPageData, &cbPage);
3155 break;
3156 }
3157 case MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE:
3158 {
3159 /* Get the page data. */
3160 rc = lsilogicR3ConfigurationSCSISPIDevicePageGetFromNumber(pThis,
3161 pThis->pConfigurationPages,
3162 pConfigurationReq->PageAddress.BusAndTargetId.u8Bus,
3163 pConfigurationReq->PageAddress.BusAndTargetId.u8TargetID,
3164 pConfigurationReq->u8PageNumber,
3165 &pPageHeader, &pbPageData, &cbPage);
3166 break;
3167 }
3168 case MPT_CONFIGURATION_PAGE_TYPE_BIOS:
3169 {
3170 rc = lsilogicR3ConfigurationBiosPageGetFromNumber(pThis,
3171 pThis->pConfigurationPages,
3172 pConfigurationReq->u8PageNumber,
3173 &pPageHeader, &pbPageData, &cbPage);
3174 break;
3175 }
3176 case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED:
3177 {
3178 rc = lsilogicR3ConfigurationPageGetExtended(pThis,
3179 pConfigurationReq,
3180 &pExtPageHeader, &pbPageData, &cbPage);
3181 break;
3182 }
3183 default:
3184 rc = VERR_NOT_FOUND;
3185 }
3186
3187 if (rc == VERR_NOT_FOUND)
3188 {
3189 Log(("Page not found\n"));
3190 pReply->u8PageType = pConfigurationReq->u8PageType;
3191 pReply->u8PageNumber = pConfigurationReq->u8PageNumber;
3192 pReply->u8PageLength = pConfigurationReq->u8PageLength;
3193 pReply->u8PageVersion = pConfigurationReq->u8PageVersion;
3194 pReply->u16IOCStatus = MPT_IOCSTATUS_CONFIG_INVALID_PAGE;
3195 return VINF_SUCCESS;
3196 }
3197
3198 if (u8PageType == MPT_CONFIGURATION_PAGE_TYPE_EXTENDED)
3199 {
3200 pReply->u8PageType = pExtPageHeader->u8PageType;
3201 pReply->u8PageNumber = pExtPageHeader->u8PageNumber;
3202 pReply->u8PageVersion = pExtPageHeader->u8PageVersion;
3203 pReply->u8ExtPageType = pExtPageHeader->u8ExtPageType;
3204 pReply->u16ExtPageLength = pExtPageHeader->u16ExtPageLength;
3205
3206 for (int i = 0; i < pExtPageHeader->u16ExtPageLength; i++)
3207 LogFlowFunc(("PageData[%d]=%#x\n", i, ((uint32_t *)pbPageData)[i]));
3208 }
3209 else
3210 {
3211 pReply->u8PageType = pPageHeader->u8PageType;
3212 pReply->u8PageNumber = pPageHeader->u8PageNumber;
3213 pReply->u8PageLength = pPageHeader->u8PageLength;
3214 pReply->u8PageVersion = pPageHeader->u8PageVersion;
3215
3216 for (int i = 0; i < pReply->u8PageLength; i++)
3217 LogFlowFunc(("PageData[%d]=%#x\n", i, ((uint32_t *)pbPageData)[i]));
3218 }
3219
3220 /*
3221 * Don't use the scatter gather handling code as the configuration request always have only one
3222 * simple element.
3223 */
3224 switch (pConfigurationReq->u8Action)
3225 {
3226 case MPT_CONFIGURATION_REQUEST_ACTION_DEFAULT: /* Nothing to do. We are always using the defaults. */
3227 case MPT_CONFIGURATION_REQUEST_ACTION_HEADER:
3228 {
3229 /* Already copied above nothing to do. */
3230 break;
3231 }
3232 case MPT_CONFIGURATION_REQUEST_ACTION_READ_NVRAM:
3233 case MPT_CONFIGURATION_REQUEST_ACTION_READ_CURRENT:
3234 case MPT_CONFIGURATION_REQUEST_ACTION_READ_DEFAULT:
3235 {
3236 uint32_t cbBuffer = pConfigurationReq->SimpleSGElement.u24Length;
3237 if (cbBuffer != 0)
3238 {
3239 RTGCPHYS GCPhysAddrPageBuffer = pConfigurationReq->SimpleSGElement.u32DataBufferAddressLow;
3240 if (pConfigurationReq->SimpleSGElement.f64BitAddress)
3241 GCPhysAddrPageBuffer |= (uint64_t)pConfigurationReq->SimpleSGElement.u32DataBufferAddressHigh << 32;
3242
3243 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhysAddrPageBuffer, pbPageData, RT_MIN(cbBuffer, cbPage));
3244 }
3245 break;
3246 }
3247 case MPT_CONFIGURATION_REQUEST_ACTION_WRITE_CURRENT:
3248 case MPT_CONFIGURATION_REQUEST_ACTION_WRITE_NVRAM:
3249 {
3250 uint32_t cbBuffer = pConfigurationReq->SimpleSGElement.u24Length;
3251 if (cbBuffer != 0)
3252 {
3253 RTGCPHYS GCPhysAddrPageBuffer = pConfigurationReq->SimpleSGElement.u32DataBufferAddressLow;
3254 if (pConfigurationReq->SimpleSGElement.f64BitAddress)
3255 GCPhysAddrPageBuffer |= (uint64_t)pConfigurationReq->SimpleSGElement.u32DataBufferAddressHigh << 32;
3256
3257 LogFlow(("cbBuffer=%u cbPage=%u\n", cbBuffer, cbPage));
3258
3259 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhysAddrPageBuffer, pbPageData,
3260 RT_MIN(cbBuffer, cbPage));
3261 }
3262 break;
3263 }
3264 default:
3265 AssertMsgFailed(("todo\n"));
3266 }
3267
3268 return VINF_SUCCESS;
3269}
3270
3271/**
3272 * Initializes the configuration pages for the SPI SCSI controller.
3273 *
3274 * @returns nothing
3275 * @param pThis Pointer to the LsiLogic device state.
3276 */
3277static void lsilogicR3InitializeConfigurationPagesSpi(PLSILOGICSCSI pThis)
3278{
3279 PMptConfigurationPagesSpi pPages = &pThis->pConfigurationPages->u.SpiPages;
3280
3281 AssertMsg(pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI, ("Controller is not the SPI SCSI one\n"));
3282
3283 LogFlowFunc(("pThis=%#p\n", pThis));
3284
3285 /* Clear everything first. */
3286 memset(pPages, 0, sizeof(MptConfigurationPagesSpi));
3287
3288 for (unsigned i = 0; i < RT_ELEMENTS(pPages->aPortPages); i++)
3289 {
3290 /* SCSI-SPI port page 0. */
3291 pPages->aPortPages[i].SCSISPIPortPage0.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3292 | MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_PORT;
3293 pPages->aPortPages[i].SCSISPIPortPage0.u.fields.Header.u8PageNumber = 0;
3294 pPages->aPortPages[i].SCSISPIPortPage0.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIPort0) / 4;
3295 pPages->aPortPages[i].SCSISPIPortPage0.u.fields.fInformationUnitTransfersCapable = true;
3296 pPages->aPortPages[i].SCSISPIPortPage0.u.fields.fDTCapable = true;
3297 pPages->aPortPages[i].SCSISPIPortPage0.u.fields.fQASCapable = true;
3298 pPages->aPortPages[i].SCSISPIPortPage0.u.fields.u8MinimumSynchronousTransferPeriod = 0;
3299 pPages->aPortPages[i].SCSISPIPortPage0.u.fields.u8MaximumSynchronousOffset = 0xff;
3300 pPages->aPortPages[i].SCSISPIPortPage0.u.fields.fWide = true;
3301 pPages->aPortPages[i].SCSISPIPortPage0.u.fields.fAIPCapable = true;
3302 pPages->aPortPages[i].SCSISPIPortPage0.u.fields.u2SignalingType = 0x3; /* Single Ended. */
3303
3304 /* SCSI-SPI port page 1. */
3305 pPages->aPortPages[i].SCSISPIPortPage1.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE
3306 | MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_PORT;
3307 pPages->aPortPages[i].SCSISPIPortPage1.u.fields.Header.u8PageNumber = 1;
3308 pPages->aPortPages[i].SCSISPIPortPage1.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIPort1) / 4;
3309 pPages->aPortPages[i].SCSISPIPortPage1.u.fields.u8SCSIID = 7;
3310 pPages->aPortPages[i].SCSISPIPortPage1.u.fields.u16PortResponseIDsBitmask = (1 << 7);
3311 pPages->aPortPages[i].SCSISPIPortPage1.u.fields.u32OnBusTimerValue = 0;
3312
3313 /* SCSI-SPI port page 2. */
3314 pPages->aPortPages[i].SCSISPIPortPage2.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE
3315 | MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_PORT;
3316 pPages->aPortPages[i].SCSISPIPortPage2.u.fields.Header.u8PageNumber = 2;
3317 pPages->aPortPages[i].SCSISPIPortPage2.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIPort2) / 4;
3318 pPages->aPortPages[i].SCSISPIPortPage2.u.fields.u4HostSCSIID = 7;
3319 pPages->aPortPages[i].SCSISPIPortPage2.u.fields.u2InitializeHBA = 0x3;
3320 pPages->aPortPages[i].SCSISPIPortPage2.u.fields.fTerminationDisabled = true;
3321 for (unsigned iDevice = 0; iDevice < RT_ELEMENTS(pPages->aPortPages[i].SCSISPIPortPage2.u.fields.aDeviceSettings); iDevice++)
3322 {
3323 pPages->aPortPages[i].SCSISPIPortPage2.u.fields.aDeviceSettings[iDevice].fBootChoice = true;
3324 }
3325 /* Everything else 0 for now. */
3326 }
3327
3328 for (unsigned uBusCurr = 0; uBusCurr < RT_ELEMENTS(pPages->aBuses); uBusCurr++)
3329 {
3330 for (unsigned uDeviceCurr = 0; uDeviceCurr < RT_ELEMENTS(pPages->aBuses[uBusCurr].aDevicePages); uDeviceCurr++)
3331 {
3332 /* SCSI-SPI device page 0. */
3333 pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage0.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3334 | MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE;
3335 pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage0.u.fields.Header.u8PageNumber = 0;
3336 pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage0.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIDevice0) / 4;
3337 /* Everything else 0 for now. */
3338
3339 /* SCSI-SPI device page 1. */
3340 pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage1.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE
3341 | MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE;
3342 pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage1.u.fields.Header.u8PageNumber = 1;
3343 pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage1.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIDevice1) / 4;
3344 /* Everything else 0 for now. */
3345
3346 /* SCSI-SPI device page 2. */
3347 pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage2.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE
3348 | MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE;
3349 pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage2.u.fields.Header.u8PageNumber = 2;
3350 pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage2.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIDevice2) / 4;
3351 /* Everything else 0 for now. */
3352
3353 pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage3.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3354 | MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE;
3355 pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage3.u.fields.Header.u8PageNumber = 3;
3356 pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage3.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIDevice3) / 4;
3357 /* Everything else 0 for now. */
3358 }
3359 }
3360}
3361
3362/**
3363 * Generates a handle.
3364 *
3365 * @returns the handle.
3366 * @param pThis Pointer to the LsiLogic device state.
3367 */
3368DECLINLINE(uint16_t) lsilogicGetHandle(PLSILOGICSCSI pThis)
3369{
3370 uint16_t u16Handle = pThis->u16NextHandle++;
3371 return u16Handle;
3372}
3373
3374/**
3375 * Generates a SAS address (WWID)
3376 *
3377 * @returns nothing.
3378 * @param pSASAddress Pointer to an unitialised SAS address.
3379 * @param iId iId which will go into the address.
3380 *
3381 * @todo Generate better SAS addresses. (Request a block from SUN probably)
3382 */
3383void lsilogicSASAddressGenerate(PSASADDRESS pSASAddress, unsigned iId)
3384{
3385 pSASAddress->u8Address[0] = (0x5 << 5);
3386 pSASAddress->u8Address[1] = 0x01;
3387 pSASAddress->u8Address[2] = 0x02;
3388 pSASAddress->u8Address[3] = 0x03;
3389 pSASAddress->u8Address[4] = 0x04;
3390 pSASAddress->u8Address[5] = 0x05;
3391 pSASAddress->u8Address[6] = 0x06;
3392 pSASAddress->u8Address[7] = iId;
3393}
3394
3395/**
3396 * Initializes the configuration pages for the SAS SCSI controller.
3397 *
3398 * @returns nothing
3399 * @param pThis Pointer to the LsiLogic device state.
3400 */
3401static void lsilogicR3InitializeConfigurationPagesSas(PLSILOGICSCSI pThis)
3402{
3403 PMptConfigurationPagesSas pPages = &pThis->pConfigurationPages->u.SasPages;
3404
3405 AssertMsg(pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS, ("Controller is not the SAS SCSI one\n"));
3406
3407 LogFlowFunc(("pThis=%#p\n", pThis));
3408
3409 /* Manufacturing Page 7 - Connector settings. */
3410 pPages->cbManufacturingPage7 = LSILOGICSCSI_MANUFACTURING7_GET_SIZE(pThis->cPorts);
3411 PMptConfigurationPageManufacturing7 pManufacturingPage7 = (PMptConfigurationPageManufacturing7)RTMemAllocZ(pPages->cbManufacturingPage7);
3412 AssertPtr(pManufacturingPage7);
3413 MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(pManufacturingPage7,
3414 0, 7,
3415 MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3416 /* Set size manually. */
3417 if (pPages->cbManufacturingPage7 / 4 > 255)
3418 pManufacturingPage7->u.fields.Header.u8PageLength = 255;
3419 else
3420 pManufacturingPage7->u.fields.Header.u8PageLength = pPages->cbManufacturingPage7 / 4;
3421 pManufacturingPage7->u.fields.u8NumPhys = pThis->cPorts;
3422 pPages->pManufacturingPage7 = pManufacturingPage7;
3423
3424 /* SAS I/O unit page 0 - Port specific information. */
3425 pPages->cbSASIOUnitPage0 = LSILOGICSCSI_SASIOUNIT0_GET_SIZE(pThis->cPorts);
3426 PMptConfigurationPageSASIOUnit0 pSASPage0 = (PMptConfigurationPageSASIOUnit0)RTMemAllocZ(pPages->cbSASIOUnitPage0);
3427 AssertPtr(pSASPage0);
3428
3429 MPT_CONFIG_EXTENDED_PAGE_HEADER_INIT(pSASPage0, pPages->cbSASIOUnitPage0,
3430 0, MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY,
3431 MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT);
3432 pSASPage0->u.fields.u8NumPhys = pThis->cPorts;
3433 pPages->pSASIOUnitPage0 = pSASPage0;
3434
3435 /* SAS I/O unit page 1 - Port specific settings. */
3436 pPages->cbSASIOUnitPage1 = LSILOGICSCSI_SASIOUNIT1_GET_SIZE(pThis->cPorts);
3437 PMptConfigurationPageSASIOUnit1 pSASPage1 = (PMptConfigurationPageSASIOUnit1)RTMemAllocZ(pPages->cbSASIOUnitPage1);
3438 AssertPtr(pSASPage1);
3439
3440 MPT_CONFIG_EXTENDED_PAGE_HEADER_INIT(pSASPage1, pPages->cbSASIOUnitPage1,
3441 1, MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE,
3442 MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT);
3443 pSASPage1->u.fields.u8NumPhys = pSASPage0->u.fields.u8NumPhys;
3444 pSASPage1->u.fields.u16ControlFlags = 0;
3445 pSASPage1->u.fields.u16AdditionalControlFlags = 0;
3446 pPages->pSASIOUnitPage1 = pSASPage1;
3447
3448 /* SAS I/O unit page 2 - Port specific information. */
3449 pPages->SASIOUnitPage2.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3450 | MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3451 pPages->SASIOUnitPage2.u.fields.ExtHeader.u8PageNumber = 2;
3452 pPages->SASIOUnitPage2.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT;
3453 pPages->SASIOUnitPage2.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASIOUnit2) / 4;
3454
3455 /* SAS I/O unit page 3 - Port specific information. */
3456 pPages->SASIOUnitPage3.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3457 | MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3458 pPages->SASIOUnitPage3.u.fields.ExtHeader.u8PageNumber = 3;
3459 pPages->SASIOUnitPage3.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT;
3460 pPages->SASIOUnitPage3.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASIOUnit3) / 4;
3461
3462 pPages->cPHYs = pThis->cPorts;
3463 pPages->paPHYs = (PMptPHY)RTMemAllocZ(pPages->cPHYs * sizeof(MptPHY));
3464 AssertPtr(pPages->paPHYs);
3465
3466 /* Initialize the PHY configuration */
3467 for (unsigned i = 0; i < pThis->cPorts; i++)
3468 {
3469 PMptPHY pPHYPages = &pPages->paPHYs[i];
3470 uint16_t u16ControllerHandle = lsilogicGetHandle(pThis);
3471
3472 pManufacturingPage7->u.fields.aPHY[i].u8Location = LSILOGICSCSI_MANUFACTURING7_LOCATION_AUTO;
3473
3474 pSASPage0->u.fields.aPHY[i].u8Port = i;
3475 pSASPage0->u.fields.aPHY[i].u8PortFlags = 0;
3476 pSASPage0->u.fields.aPHY[i].u8PhyFlags = 0;
3477 pSASPage0->u.fields.aPHY[i].u8NegotiatedLinkRate = LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_FAILED;
3478 pSASPage0->u.fields.aPHY[i].u32ControllerPhyDeviceInfo = LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_SET(LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_NO);
3479 pSASPage0->u.fields.aPHY[i].u16ControllerDevHandle = u16ControllerHandle;
3480 pSASPage0->u.fields.aPHY[i].u16AttachedDevHandle = 0; /* No device attached. */
3481 pSASPage0->u.fields.aPHY[i].u32DiscoveryStatus = 0; /* No errors */
3482
3483 pSASPage1->u.fields.aPHY[i].u8Port = i;
3484 pSASPage1->u.fields.aPHY[i].u8PortFlags = 0;
3485 pSASPage1->u.fields.aPHY[i].u8PhyFlags = 0;
3486 pSASPage1->u.fields.aPHY[i].u8MaxMinLinkRate = LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MIN_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_15GB)
3487 | LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MAX_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_30GB);
3488 pSASPage1->u.fields.aPHY[i].u32ControllerPhyDeviceInfo = LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_SET(LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_NO);
3489
3490 /* SAS PHY page 0. */
3491 pPHYPages->SASPHYPage0.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3492 | MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3493 pPHYPages->SASPHYPage0.u.fields.ExtHeader.u8PageNumber = 0;
3494 pPHYPages->SASPHYPage0.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASPHYS;
3495 pPHYPages->SASPHYPage0.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASPHY0) / 4;
3496 pPHYPages->SASPHYPage0.u.fields.u8AttachedPhyIdentifier = i;
3497 pPHYPages->SASPHYPage0.u.fields.u32AttachedDeviceInfo = LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_SET(LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_NO);
3498 pPHYPages->SASPHYPage0.u.fields.u8ProgrammedLinkRate = LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MIN_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_15GB)
3499 | LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MAX_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_30GB);
3500 pPHYPages->SASPHYPage0.u.fields.u8HwLinkRate = LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MIN_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_15GB)
3501 | LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MAX_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_30GB);
3502
3503 /* SAS PHY page 1. */
3504 pPHYPages->SASPHYPage1.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3505 | MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3506 pPHYPages->SASPHYPage1.u.fields.ExtHeader.u8PageNumber = 1;
3507 pPHYPages->SASPHYPage1.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASPHYS;
3508 pPHYPages->SASPHYPage1.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASPHY1) / 4;
3509
3510 /* Settings for present devices. */
3511 if (pThis->paDeviceStates[i].pDrvBase)
3512 {
3513 uint16_t u16DeviceHandle = lsilogicGetHandle(pThis);
3514 SASADDRESS SASAddress;
3515 PMptSASDevice pSASDevice = (PMptSASDevice)RTMemAllocZ(sizeof(MptSASDevice));
3516 AssertPtr(pSASDevice);
3517
3518 memset(&SASAddress, 0, sizeof(SASADDRESS));
3519 lsilogicSASAddressGenerate(&SASAddress, i);
3520
3521 pSASPage0->u.fields.aPHY[i].u8NegotiatedLinkRate = LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_SET(LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_30GB);
3522 pSASPage0->u.fields.aPHY[i].u32ControllerPhyDeviceInfo = LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_SET(LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_END)
3523 | LSILOGICSCSI_SASIOUNIT0_DEVICE_SSP_TARGET;
3524 pSASPage0->u.fields.aPHY[i].u16AttachedDevHandle = u16DeviceHandle;
3525 pSASPage1->u.fields.aPHY[i].u32ControllerPhyDeviceInfo = LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_SET(LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_END)
3526 | LSILOGICSCSI_SASIOUNIT0_DEVICE_SSP_TARGET;
3527 pSASPage0->u.fields.aPHY[i].u16ControllerDevHandle = u16DeviceHandle;
3528
3529 pPHYPages->SASPHYPage0.u.fields.u32AttachedDeviceInfo = LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_SET(LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_END);
3530 pPHYPages->SASPHYPage0.u.fields.SASAddress = SASAddress;
3531 pPHYPages->SASPHYPage0.u.fields.u16OwnerDevHandle = u16DeviceHandle;
3532 pPHYPages->SASPHYPage0.u.fields.u16AttachedDevHandle = u16DeviceHandle;
3533
3534 /* SAS device page 0. */
3535 pSASDevice->SASDevicePage0.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3536 | MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3537 pSASDevice->SASDevicePage0.u.fields.ExtHeader.u8PageNumber = 0;
3538 pSASDevice->SASDevicePage0.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASDEVICE;
3539 pSASDevice->SASDevicePage0.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASDevice0) / 4;
3540 pSASDevice->SASDevicePage0.u.fields.SASAddress = SASAddress;
3541 pSASDevice->SASDevicePage0.u.fields.u16ParentDevHandle = u16ControllerHandle;
3542 pSASDevice->SASDevicePage0.u.fields.u8PhyNum = i;
3543 pSASDevice->SASDevicePage0.u.fields.u8AccessStatus = LSILOGICSCSI_SASDEVICE0_STATUS_NO_ERRORS;
3544 pSASDevice->SASDevicePage0.u.fields.u16DevHandle = u16DeviceHandle;
3545 pSASDevice->SASDevicePage0.u.fields.u8TargetID = i;
3546 pSASDevice->SASDevicePage0.u.fields.u8Bus = 0;
3547 pSASDevice->SASDevicePage0.u.fields.u32DeviceInfo = LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_SET(LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_END)
3548 | LSILOGICSCSI_SASIOUNIT0_DEVICE_SSP_TARGET;
3549 pSASDevice->SASDevicePage0.u.fields.u16Flags = LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_PRESENT
3550 | LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_MAPPED_TO_BUS_AND_TARGET_ID
3551 | LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_MAPPING_PERSISTENT;
3552 pSASDevice->SASDevicePage0.u.fields.u8PhysicalPort = i;
3553
3554 /* SAS device page 1. */
3555 pSASDevice->SASDevicePage1.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3556 | MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3557 pSASDevice->SASDevicePage1.u.fields.ExtHeader.u8PageNumber = 1;
3558 pSASDevice->SASDevicePage1.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASDEVICE;
3559 pSASDevice->SASDevicePage1.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASDevice1) / 4;
3560 pSASDevice->SASDevicePage1.u.fields.SASAddress = SASAddress;
3561 pSASDevice->SASDevicePage1.u.fields.u16DevHandle = u16DeviceHandle;
3562 pSASDevice->SASDevicePage1.u.fields.u8TargetID = i;
3563 pSASDevice->SASDevicePage1.u.fields.u8Bus = 0;
3564
3565 /* SAS device page 2. */
3566 pSASDevice->SASDevicePage2.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3567 | MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3568 pSASDevice->SASDevicePage2.u.fields.ExtHeader.u8PageNumber = 2;
3569 pSASDevice->SASDevicePage2.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASDEVICE;
3570 pSASDevice->SASDevicePage2.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASDevice2) / 4;
3571 pSASDevice->SASDevicePage2.u.fields.SASAddress = SASAddress;
3572
3573 /* Link into device list. */
3574 if (!pPages->cDevices)
3575 {
3576 pPages->pSASDeviceHead = pSASDevice;
3577 pPages->pSASDeviceTail = pSASDevice;
3578 pPages->cDevices = 1;
3579 }
3580 else
3581 {
3582 pSASDevice->pPrev = pPages->pSASDeviceTail;
3583 pPages->pSASDeviceTail->pNext = pSASDevice;
3584 pPages->pSASDeviceTail = pSASDevice;
3585 pPages->cDevices++;
3586 }
3587 }
3588 }
3589}
3590
3591/**
3592 * Initializes the configuration pages.
3593 *
3594 * @returns nothing
3595 * @param pThis Pointer to the LsiLogic device state.
3596 */
3597static void lsilogicR3InitializeConfigurationPages(PLSILOGICSCSI pThis)
3598{
3599 /* Initialize the common pages. */
3600 PMptConfigurationPagesSupported pPages = (PMptConfigurationPagesSupported)RTMemAllocZ(sizeof(MptConfigurationPagesSupported));
3601
3602 pThis->pConfigurationPages = pPages;
3603
3604 LogFlowFunc(("pThis=%#p\n", pThis));
3605
3606 /* Clear everything first. */
3607 memset(pPages, 0, sizeof(MptConfigurationPagesSupported));
3608
3609 /* Manufacturing Page 0. */
3610 MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage0,
3611 MptConfigurationPageManufacturing0, 0,
3612 MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3613 strncpy((char *)pPages->ManufacturingPage0.u.fields.abChipName, "VBox MPT Fusion", 16);
3614 strncpy((char *)pPages->ManufacturingPage0.u.fields.abChipRevision, "1.0", 8);
3615 strncpy((char *)pPages->ManufacturingPage0.u.fields.abBoardName, "VBox MPT Fusion", 16);
3616 strncpy((char *)pPages->ManufacturingPage0.u.fields.abBoardAssembly, "SUN", 8);
3617 strncpy((char *)pPages->ManufacturingPage0.u.fields.abBoardTracerNumber, "CAFECAFECAFECAFE", 16);
3618
3619 /* Manufacturing Page 1 - I don't know what this contains so we leave it 0 for now. */
3620 MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage1,
3621 MptConfigurationPageManufacturing1, 1,
3622 MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3623
3624 /* Manufacturing Page 2. */
3625 MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage2,
3626 MptConfigurationPageManufacturing2, 2,
3627 MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3628
3629 if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
3630 {
3631 pPages->ManufacturingPage2.u.fields.u16PCIDeviceID = LSILOGICSCSI_PCI_SPI_DEVICE_ID;
3632 pPages->ManufacturingPage2.u.fields.u8PCIRevisionID = LSILOGICSCSI_PCI_SPI_REVISION_ID;
3633 }
3634 else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
3635 {
3636 pPages->ManufacturingPage2.u.fields.u16PCIDeviceID = LSILOGICSCSI_PCI_SAS_DEVICE_ID;
3637 pPages->ManufacturingPage2.u.fields.u8PCIRevisionID = LSILOGICSCSI_PCI_SAS_REVISION_ID;
3638 }
3639
3640 /* Manufacturing Page 3. */
3641 MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage3,
3642 MptConfigurationPageManufacturing3, 3,
3643 MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3644
3645 if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
3646 {
3647 pPages->ManufacturingPage3.u.fields.u16PCIDeviceID = LSILOGICSCSI_PCI_SPI_DEVICE_ID;
3648 pPages->ManufacturingPage3.u.fields.u8PCIRevisionID = LSILOGICSCSI_PCI_SPI_REVISION_ID;
3649 }
3650 else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
3651 {
3652 pPages->ManufacturingPage3.u.fields.u16PCIDeviceID = LSILOGICSCSI_PCI_SAS_DEVICE_ID;
3653 pPages->ManufacturingPage3.u.fields.u8PCIRevisionID = LSILOGICSCSI_PCI_SAS_REVISION_ID;
3654 }
3655
3656 /* Manufacturing Page 4 - I don't know what this contains so we leave it 0 for now. */
3657 MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage4,
3658 MptConfigurationPageManufacturing4, 4,
3659 MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3660
3661 /* Manufacturing Page 5 - WWID settings. */
3662 MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage5,
3663 MptConfigurationPageManufacturing5, 5,
3664 MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3665
3666 /* Manufacturing Page 6 - Product specific settings. */
3667 MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage6,
3668 MptConfigurationPageManufacturing6, 6,
3669 MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3670
3671 /* Manufacturing Page 8 - Product specific settings. */
3672 MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage8,
3673 MptConfigurationPageManufacturing8, 8,
3674 MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3675
3676 /* Manufacturing Page 9 - Product specific settings. */
3677 MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage9,
3678 MptConfigurationPageManufacturing9, 9,
3679 MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3680
3681 /* Manufacturing Page 10 - Product specific settings. */
3682 MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage10,
3683 MptConfigurationPageManufacturing10, 10,
3684 MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3685
3686 /* I/O Unit page 0. */
3687 MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(&pPages->IOUnitPage0,
3688 MptConfigurationPageIOUnit0, 0,
3689 MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3690 pPages->IOUnitPage0.u.fields.u64UniqueIdentifier = 0xcafe;
3691
3692 /* I/O Unit page 1. */
3693 MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(&pPages->IOUnitPage1,
3694 MptConfigurationPageIOUnit1, 1,
3695 MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3696 pPages->IOUnitPage1.u.fields.fSingleFunction = true;
3697 pPages->IOUnitPage1.u.fields.fAllPathsMapped = false;
3698 pPages->IOUnitPage1.u.fields.fIntegratedRAIDDisabled = true;
3699 pPages->IOUnitPage1.u.fields.f32BitAccessForced = false;
3700
3701 /* I/O Unit page 2. */
3702 MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(&pPages->IOUnitPage2,
3703 MptConfigurationPageIOUnit2, 2,
3704 MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT);
3705 pPages->IOUnitPage2.u.fields.fPauseOnError = false;
3706 pPages->IOUnitPage2.u.fields.fVerboseModeEnabled = false;
3707 pPages->IOUnitPage2.u.fields.fDisableColorVideo = false;
3708 pPages->IOUnitPage2.u.fields.fNotHookInt40h = false;
3709 pPages->IOUnitPage2.u.fields.u32BIOSVersion = 0xcafecafe;
3710 pPages->IOUnitPage2.u.fields.aAdapterOrder[0].fAdapterEnabled = true;
3711 pPages->IOUnitPage2.u.fields.aAdapterOrder[0].fAdapterEmbedded = true;
3712 pPages->IOUnitPage2.u.fields.aAdapterOrder[0].u8PCIBusNumber = 0;
3713 pPages->IOUnitPage2.u.fields.aAdapterOrder[0].u8PCIDevFn = pThis->PciDev.uDevFn;
3714
3715 /* I/O Unit page 3. */
3716 MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(&pPages->IOUnitPage3,
3717 MptConfigurationPageIOUnit3, 3,
3718 MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3719 pPages->IOUnitPage3.u.fields.u8GPIOCount = 0;
3720
3721 /* I/O Unit page 4. */
3722 MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(&pPages->IOUnitPage4,
3723 MptConfigurationPageIOUnit4, 4,
3724 MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3725
3726 /* IOC page 0. */
3727 MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage0,
3728 MptConfigurationPageIOC0, 0,
3729 MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3730 pPages->IOCPage0.u.fields.u32TotalNVStore = 0;
3731 pPages->IOCPage0.u.fields.u32FreeNVStore = 0;
3732
3733 if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
3734 {
3735 pPages->IOCPage0.u.fields.u16VendorId = LSILOGICSCSI_PCI_VENDOR_ID;
3736 pPages->IOCPage0.u.fields.u16DeviceId = LSILOGICSCSI_PCI_SPI_DEVICE_ID;
3737 pPages->IOCPage0.u.fields.u8RevisionId = LSILOGICSCSI_PCI_SPI_REVISION_ID;
3738 pPages->IOCPage0.u.fields.u32ClassCode = LSILOGICSCSI_PCI_SPI_CLASS_CODE;
3739 pPages->IOCPage0.u.fields.u16SubsystemVendorId = LSILOGICSCSI_PCI_SPI_SUBSYSTEM_VENDOR_ID;
3740 pPages->IOCPage0.u.fields.u16SubsystemId = LSILOGICSCSI_PCI_SPI_SUBSYSTEM_ID;
3741 }
3742 else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
3743 {
3744 pPages->IOCPage0.u.fields.u16VendorId = LSILOGICSCSI_PCI_VENDOR_ID;
3745 pPages->IOCPage0.u.fields.u16DeviceId = LSILOGICSCSI_PCI_SAS_DEVICE_ID;
3746 pPages->IOCPage0.u.fields.u8RevisionId = LSILOGICSCSI_PCI_SAS_REVISION_ID;
3747 pPages->IOCPage0.u.fields.u32ClassCode = LSILOGICSCSI_PCI_SAS_CLASS_CODE;
3748 pPages->IOCPage0.u.fields.u16SubsystemVendorId = LSILOGICSCSI_PCI_SAS_SUBSYSTEM_VENDOR_ID;
3749 pPages->IOCPage0.u.fields.u16SubsystemId = LSILOGICSCSI_PCI_SAS_SUBSYSTEM_ID;
3750 }
3751
3752 /* IOC page 1. */
3753 MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage1,
3754 MptConfigurationPageIOC1, 1,
3755 MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3756 pPages->IOCPage1.u.fields.fReplyCoalescingEnabled = false;
3757 pPages->IOCPage1.u.fields.u32CoalescingTimeout = 0;
3758 pPages->IOCPage1.u.fields.u8CoalescingDepth = 0;
3759
3760 /* IOC page 2. */
3761 MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage2,
3762 MptConfigurationPageIOC2, 2,
3763 MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3764 /* Everything else here is 0. */
3765
3766 /* IOC page 3. */
3767 MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage3,
3768 MptConfigurationPageIOC3, 3,
3769 MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3770 /* Everything else here is 0. */
3771
3772 /* IOC page 4. */
3773 MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage4,
3774 MptConfigurationPageIOC4, 4,
3775 MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3776 /* Everything else here is 0. */
3777
3778 /* IOC page 6. */
3779 MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage6,
3780 MptConfigurationPageIOC6, 6,
3781 MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3782 /* Everything else here is 0. */
3783
3784 /* BIOS page 1. */
3785 MPT_CONFIG_PAGE_HEADER_INIT_BIOS(&pPages->BIOSPage1,
3786 MptConfigurationPageBIOS1, 1,
3787 MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3788
3789 /* BIOS page 2. */
3790 MPT_CONFIG_PAGE_HEADER_INIT_BIOS(&pPages->BIOSPage2,
3791 MptConfigurationPageBIOS2, 2,
3792 MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3793
3794 /* BIOS page 4. */
3795 MPT_CONFIG_PAGE_HEADER_INIT_BIOS(&pPages->BIOSPage4,
3796 MptConfigurationPageBIOS4, 4,
3797 MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3798
3799 if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
3800 lsilogicR3InitializeConfigurationPagesSpi(pThis);
3801 else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
3802 lsilogicR3InitializeConfigurationPagesSas(pThis);
3803 else
3804 AssertMsgFailed(("Invalid controller type %d\n", pThis->enmCtrlType));
3805}
3806
3807/**
3808 * @callback_method_impl{FNPDMQUEUEDEV, Transmit queue consumer.}
3809 */
3810static DECLCALLBACK(bool) lsilogicR3NotifyQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
3811{
3812 RT_NOREF(pItem);
3813 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
3814 int rc = VINF_SUCCESS;
3815
3816 LogFlowFunc(("pDevIns=%#p pItem=%#p\n", pDevIns, pItem));
3817
3818 rc = SUPSemEventSignal(pThis->pSupDrvSession, pThis->hEvtProcess);
3819 AssertRC(rc);
3820
3821 return true;
3822}
3823
3824/**
3825 * Sets the emulated controller type from a given string.
3826 *
3827 * @returns VBox status code.
3828 *
3829 * @param pThis Pointer to the LsiLogic device state.
3830 * @param pcszCtrlType The string to use.
3831 */
3832static int lsilogicR3GetCtrlTypeFromString(PLSILOGICSCSI pThis, const char *pcszCtrlType)
3833{
3834 int rc = VERR_INVALID_PARAMETER;
3835
3836 if (!RTStrCmp(pcszCtrlType, LSILOGICSCSI_PCI_SPI_CTRLNAME))
3837 {
3838 pThis->enmCtrlType = LSILOGICCTRLTYPE_SCSI_SPI;
3839 rc = VINF_SUCCESS;
3840 }
3841 else if (!RTStrCmp(pcszCtrlType, LSILOGICSCSI_PCI_SAS_CTRLNAME))
3842 {
3843 pThis->enmCtrlType = LSILOGICCTRLTYPE_SCSI_SAS;
3844 rc = VINF_SUCCESS;
3845 }
3846
3847 return rc;
3848}
3849
3850/**
3851 * @callback_method_impl{FNIOMIOPORTIN, Legacy ISA port.}
3852 */
3853static DECLCALLBACK(int) lsilogicR3IsaIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
3854{
3855 RT_NOREF(pvUser, cb);
3856 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
3857
3858 Assert(cb == 1);
3859
3860 uint8_t iRegister = pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI
3861 ? Port - LSILOGIC_BIOS_IO_PORT
3862 : Port - LSILOGIC_SAS_BIOS_IO_PORT;
3863 int rc = vboxscsiReadRegister(&pThis->VBoxSCSI, iRegister, pu32);
3864
3865 Log2(("%s: pu32=%p:{%.*Rhxs} iRegister=%d rc=%Rrc\n",
3866 __FUNCTION__, pu32, 1, pu32, iRegister, rc));
3867
3868 return rc;
3869}
3870
3871/**
3872 * Prepares a request from the BIOS.
3873 *
3874 * @returns VBox status code.
3875 * @param pThis Pointer to the LsiLogic device state.
3876 */
3877static int lsilogicR3PrepareBiosScsiRequest(PLSILOGICSCSI pThis)
3878{
3879 int rc;
3880 uint32_t uTargetDevice;
3881 uint32_t uLun;
3882 uint8_t *pbCdb;
3883 size_t cbCdb;
3884 size_t cbBuf;
3885
3886 rc = vboxscsiSetupRequest(&pThis->VBoxSCSI, &uLun, &pbCdb, &cbCdb, &cbBuf, &uTargetDevice);
3887 AssertMsgRCReturn(rc, ("Setting up SCSI request failed rc=%Rrc\n", rc), rc);
3888
3889 if ( uTargetDevice < pThis->cDeviceStates
3890 && pThis->paDeviceStates[uTargetDevice].pDrvBase)
3891 {
3892 PLSILOGICDEVICE pTgtDev = &pThis->paDeviceStates[uTargetDevice];
3893 PDMMEDIAEXIOREQ hIoReq;
3894 PLSILOGICREQ pReq;
3895
3896 rc = pTgtDev->pDrvMediaEx->pfnIoReqAlloc(pTgtDev->pDrvMediaEx, &hIoReq, (void **)&pReq,
3897 0, PDMIMEDIAEX_F_SUSPEND_ON_RECOVERABLE_ERR);
3898 AssertMsgRCReturn(rc, ("Getting task from cache failed rc=%Rrc\n", rc), rc);
3899
3900 pReq->fBIOS = true;
3901 pReq->hIoReq = hIoReq;
3902 pReq->pTargetDevice = pTgtDev;
3903
3904 ASMAtomicIncU32(&pTgtDev->cOutstandingRequests);
3905
3906 rc = pTgtDev->pDrvMediaEx->pfnIoReqSendScsiCmd(pTgtDev->pDrvMediaEx, pReq->hIoReq, uLun,
3907 pbCdb, cbCdb, PDMMEDIAEXIOREQSCSITXDIR_UNKNOWN,
3908 cbBuf, NULL, 0, &pReq->u8ScsiSts, 30 * RT_MS_1SEC);
3909 if (rc == VINF_SUCCESS || rc != VINF_PDM_MEDIAEX_IOREQ_IN_PROGRESS)
3910 {
3911 uint8_t u8ScsiSts = pReq->u8ScsiSts;
3912 pTgtDev->pDrvMediaEx->pfnIoReqFree(pTgtDev->pDrvMediaEx, pReq->hIoReq);
3913 rc = vboxscsiRequestFinished(&pThis->VBoxSCSI, u8ScsiSts);
3914 }
3915 else if (rc == VINF_PDM_MEDIAEX_IOREQ_IN_PROGRESS)
3916 rc = VINF_SUCCESS;
3917
3918 return rc;
3919 }
3920
3921 /* Device is not present. */
3922 AssertMsg(pbCdb[0] == SCSI_INQUIRY,
3923 ("Device is not present but command is not inquiry\n"));
3924
3925 SCSIINQUIRYDATA ScsiInquiryData;
3926
3927 memset(&ScsiInquiryData, 0, sizeof(SCSIINQUIRYDATA));
3928 ScsiInquiryData.u5PeripheralDeviceType = SCSI_INQUIRY_DATA_PERIPHERAL_DEVICE_TYPE_UNKNOWN;
3929 ScsiInquiryData.u3PeripheralQualifier = SCSI_INQUIRY_DATA_PERIPHERAL_QUALIFIER_NOT_CONNECTED_NOT_SUPPORTED;
3930
3931 memcpy(pThis->VBoxSCSI.pbBuf, &ScsiInquiryData, 5);
3932
3933 rc = vboxscsiRequestFinished(&pThis->VBoxSCSI, SCSI_STATUS_OK);
3934 AssertMsgRCReturn(rc, ("Finishing BIOS SCSI request failed rc=%Rrc\n", rc), rc);
3935
3936 return rc;
3937}
3938
3939/**
3940 * @callback_method_impl{FNIOMIOPORTOUT, Legacy ISA port.}
3941 */
3942static DECLCALLBACK(int) lsilogicR3IsaIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
3943{
3944 RT_NOREF(pvUser, cb);
3945 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
3946 Log2(("#%d %s: pvUser=%#p cb=%d u32=%#x Port=%#x\n", pDevIns->iInstance, __FUNCTION__, pvUser, cb, u32, Port));
3947
3948 Assert(cb == 1);
3949
3950 /*
3951 * If there is already a request form the BIOS pending ignore this write
3952 * because it should not happen.
3953 */
3954 if (ASMAtomicReadBool(&pThis->fBiosReqPending))
3955 return VINF_SUCCESS;
3956
3957 uint8_t iRegister = pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI
3958 ? Port - LSILOGIC_BIOS_IO_PORT
3959 : Port - LSILOGIC_SAS_BIOS_IO_PORT;
3960 int rc = vboxscsiWriteRegister(&pThis->VBoxSCSI, iRegister, (uint8_t)u32);
3961 if (rc == VERR_MORE_DATA)
3962 {
3963 ASMAtomicXchgBool(&pThis->fBiosReqPending, true);
3964 /* Send a notifier to the PDM queue that there are pending requests. */
3965 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pNotificationQueue));
3966 AssertMsg(pItem, ("Allocating item for queue failed\n"));
3967 PDMQueueInsert(pThis->CTX_SUFF(pNotificationQueue), (PPDMQUEUEITEMCORE)pItem);
3968 }
3969 else if (RT_FAILURE(rc))
3970 AssertMsgFailed(("Writing BIOS register failed %Rrc\n", rc));
3971
3972 return VINF_SUCCESS;
3973}
3974
3975/**
3976 * @callback_method_impl{FNIOMIOPORTOUTSTRING,
3977 * Port I/O Handler for primary port range OUT string operations.}
3978 */
3979static DECLCALLBACK(int) lsilogicR3IsaIOPortWriteStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port,
3980 uint8_t const *pbSrc, uint32_t *pcTransfers, unsigned cb)
3981{
3982 RT_NOREF(pvUser);
3983 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
3984 Log2(("#%d %s: pvUser=%#p cb=%d Port=%#x\n", pDevIns->iInstance, __FUNCTION__, pvUser, cb, Port));
3985
3986 uint8_t iRegister = pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI
3987 ? Port - LSILOGIC_BIOS_IO_PORT
3988 : Port - LSILOGIC_SAS_BIOS_IO_PORT;
3989 int rc = vboxscsiWriteString(pDevIns, &pThis->VBoxSCSI, iRegister, pbSrc, pcTransfers, cb);
3990 if (rc == VERR_MORE_DATA)
3991 {
3992 ASMAtomicXchgBool(&pThis->fBiosReqPending, true);
3993 /* Send a notifier to the PDM queue that there are pending requests. */
3994 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pNotificationQueue));
3995 AssertMsg(pItem, ("Allocating item for queue failed\n"));
3996 PDMQueueInsert(pThis->CTX_SUFF(pNotificationQueue), (PPDMQUEUEITEMCORE)pItem);
3997 }
3998 else if (RT_FAILURE(rc))
3999 AssertMsgFailed(("Writing BIOS register failed %Rrc\n", rc));
4000
4001 return VINF_SUCCESS;
4002}
4003
4004/**
4005 * @callback_method_impl{FNIOMIOPORTINSTRING,
4006 * Port I/O Handler for primary port range IN string operations.}
4007 */
4008static DECLCALLBACK(int) lsilogicR3IsaIOPortReadStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port,
4009 uint8_t *pbDst, uint32_t *pcTransfers, unsigned cb)
4010{
4011 RT_NOREF(pvUser);
4012 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4013 LogFlowFunc(("#%d %s: pvUser=%#p cb=%d Port=%#x\n", pDevIns->iInstance, __FUNCTION__, pvUser, cb, Port));
4014
4015 uint8_t iRegister = pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI
4016 ? Port - LSILOGIC_BIOS_IO_PORT
4017 : Port - LSILOGIC_SAS_BIOS_IO_PORT;
4018 return vboxscsiReadString(pDevIns, &pThis->VBoxSCSI, iRegister, pbDst, pcTransfers, cb);
4019}
4020
4021/**
4022 * @callback_method_impl{FNPCIIOREGIONMAP}
4023 */
4024static DECLCALLBACK(int) lsilogicR3Map(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
4025 RTGCPHYS GCPhysAddress, RTGCPHYS cb,
4026 PCIADDRESSSPACE enmType)
4027{
4028 RT_NOREF(pPciDev);
4029 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4030 int rc = VINF_SUCCESS;
4031 const char *pcszCtrl = pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI
4032 ? "LsiLogic"
4033 : "LsiLogicSas";
4034 const char *pcszDiag = pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI
4035 ? "LsiLogicDiag"
4036 : "LsiLogicSasDiag";
4037
4038 Log2(("%s: registering area at GCPhysAddr=%RGp cb=%RGp\n", __FUNCTION__, GCPhysAddress, cb));
4039
4040 AssertMsg( (enmType == PCI_ADDRESS_SPACE_MEM && cb >= LSILOGIC_PCI_SPACE_MEM_SIZE)
4041 || (enmType == PCI_ADDRESS_SPACE_IO && cb >= LSILOGIC_PCI_SPACE_IO_SIZE),
4042 ("PCI region type and size do not match\n"));
4043
4044 if (enmType == PCI_ADDRESS_SPACE_MEM && iRegion == 1)
4045 {
4046 /*
4047 * Non-4-byte read access to LSILOGIC_REG_REPLY_QUEUE may cause real strange behavior
4048 * because the data is part of a physical guest address. But some drivers use 1-byte
4049 * access to scan for SCSI controllers. So, we simplify our code by telling IOM to
4050 * read DWORDs.
4051 *
4052 * Regarding writes, we couldn't find anything specific in the specs about what should
4053 * happen. So far we've ignored unaligned writes and assumed the missing bytes of
4054 * byte and word access to be zero. We suspect that IOMMMIO_FLAGS_WRITE_ONLY_DWORD
4055 * or IOMMMIO_FLAGS_WRITE_DWORD_ZEROED would be the most appropriate here, but since we
4056 * don't have real hw to test one, the old behavior is kept exactly like it used to be.
4057 */
4058 /** @todo Check out unaligned writes and non-dword writes on real LsiLogic
4059 * hardware. */
4060 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
4061 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_PASSTHRU,
4062 lsilogicMMIOWrite, lsilogicMMIORead, pcszCtrl);
4063 if (RT_FAILURE(rc))
4064 return rc;
4065
4066 if (pThis->fR0Enabled)
4067 {
4068 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
4069 "lsilogicMMIOWrite", "lsilogicMMIORead");
4070 if (RT_FAILURE(rc))
4071 return rc;
4072 }
4073
4074 if (pThis->fGCEnabled)
4075 {
4076 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
4077 "lsilogicMMIOWrite", "lsilogicMMIORead");
4078 if (RT_FAILURE(rc))
4079 return rc;
4080 }
4081
4082 pThis->GCPhysMMIOBase = GCPhysAddress;
4083 }
4084 else if (enmType == PCI_ADDRESS_SPACE_MEM && iRegion == 2)
4085 {
4086 /* We use the assigned size here, because we currently only support page aligned MMIO ranges. */
4087 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
4088 IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,
4089 lsilogicDiagnosticWrite, lsilogicDiagnosticRead, pcszDiag);
4090 if (RT_FAILURE(rc))
4091 return rc;
4092
4093 if (pThis->fR0Enabled)
4094 {
4095 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
4096 "lsilogicDiagnosticWrite", "lsilogicDiagnosticRead");
4097 if (RT_FAILURE(rc))
4098 return rc;
4099 }
4100
4101 if (pThis->fGCEnabled)
4102 {
4103 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
4104 "lsilogicDiagnosticWrite", "lsilogicDiagnosticRead");
4105 if (RT_FAILURE(rc))
4106 return rc;
4107 }
4108 }
4109 else if (enmType == PCI_ADDRESS_SPACE_IO)
4110 {
4111 rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, LSILOGIC_PCI_SPACE_IO_SIZE,
4112 NULL, lsilogicIOPortWrite, lsilogicIOPortRead, NULL, NULL, pcszCtrl);
4113 if (RT_FAILURE(rc))
4114 return rc;
4115
4116 if (pThis->fR0Enabled)
4117 {
4118 rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, LSILOGIC_PCI_SPACE_IO_SIZE,
4119 0, "lsilogicIOPortWrite", "lsilogicIOPortRead", NULL, NULL, pcszCtrl);
4120 if (RT_FAILURE(rc))
4121 return rc;
4122 }
4123
4124 if (pThis->fGCEnabled)
4125 {
4126 rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, LSILOGIC_PCI_SPACE_IO_SIZE,
4127 0, "lsilogicIOPortWrite", "lsilogicIOPortRead", NULL, NULL, pcszCtrl);
4128 if (RT_FAILURE(rc))
4129 return rc;
4130 }
4131
4132 pThis->IOPortBase = (RTIOPORT)GCPhysAddress;
4133 }
4134 else
4135 AssertMsgFailed(("Invalid enmType=%d iRegion=%d\n", enmType, iRegion));
4136
4137 return rc;
4138}
4139
4140/**
4141 * @callback_method_impl{PFNDBGFHANDLERDEV}
4142 */
4143static DECLCALLBACK(void) lsilogicR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4144{
4145 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4146 bool fVerbose = false;
4147
4148 /*
4149 * Parse args.
4150 */
4151 if (pszArgs)
4152 fVerbose = strstr(pszArgs, "verbose") != NULL;
4153
4154 /*
4155 * Show info.
4156 */
4157 pHlp->pfnPrintf(pHlp,
4158 "%s#%d: port=%RTiop mmio=%RGp max-devices=%u GC=%RTbool R0=%RTbool\n",
4159 pDevIns->pReg->szName,
4160 pDevIns->iInstance,
4161 pThis->IOPortBase, pThis->GCPhysMMIOBase,
4162 pThis->cDeviceStates,
4163 pThis->fGCEnabled ? true : false,
4164 pThis->fR0Enabled ? true : false);
4165
4166 /*
4167 * Show general state.
4168 */
4169 pHlp->pfnPrintf(pHlp, "enmState=%u\n", pThis->enmState);
4170 pHlp->pfnPrintf(pHlp, "enmWhoInit=%u\n", pThis->enmWhoInit);
4171 pHlp->pfnPrintf(pHlp, "enmDoorbellState=%d\n", pThis->enmDoorbellState);
4172 pHlp->pfnPrintf(pHlp, "fDiagnosticEnabled=%RTbool\n", pThis->fDiagnosticEnabled);
4173 pHlp->pfnPrintf(pHlp, "fNotificationSent=%RTbool\n", pThis->fNotificationSent);
4174 pHlp->pfnPrintf(pHlp, "fEventNotificationEnabled=%RTbool\n", pThis->fEventNotificationEnabled);
4175 pHlp->pfnPrintf(pHlp, "uInterruptMask=%#x\n", pThis->uInterruptMask);
4176 pHlp->pfnPrintf(pHlp, "uInterruptStatus=%#x\n", pThis->uInterruptStatus);
4177 pHlp->pfnPrintf(pHlp, "u16IOCFaultCode=%#06x\n", pThis->u16IOCFaultCode);
4178 pHlp->pfnPrintf(pHlp, "u32HostMFAHighAddr=%#x\n", pThis->u32HostMFAHighAddr);
4179 pHlp->pfnPrintf(pHlp, "u32SenseBufferHighAddr=%#x\n", pThis->u32SenseBufferHighAddr);
4180 pHlp->pfnPrintf(pHlp, "cMaxDevices=%u\n", pThis->cMaxDevices);
4181 pHlp->pfnPrintf(pHlp, "cMaxBuses=%u\n", pThis->cMaxBuses);
4182 pHlp->pfnPrintf(pHlp, "cbReplyFrame=%u\n", pThis->cbReplyFrame);
4183 pHlp->pfnPrintf(pHlp, "cReplyQueueEntries=%u\n", pThis->cReplyQueueEntries);
4184 pHlp->pfnPrintf(pHlp, "cRequestQueueEntries=%u\n", pThis->cRequestQueueEntries);
4185 pHlp->pfnPrintf(pHlp, "cPorts=%u\n", pThis->cPorts);
4186
4187 /*
4188 * Show queue status.
4189 */
4190 pHlp->pfnPrintf(pHlp, "uReplyFreeQueueNextEntryFreeWrite=%u\n", pThis->uReplyFreeQueueNextEntryFreeWrite);
4191 pHlp->pfnPrintf(pHlp, "uReplyFreeQueueNextAddressRead=%u\n", pThis->uReplyFreeQueueNextAddressRead);
4192 pHlp->pfnPrintf(pHlp, "uReplyPostQueueNextEntryFreeWrite=%u\n", pThis->uReplyPostQueueNextEntryFreeWrite);
4193 pHlp->pfnPrintf(pHlp, "uReplyPostQueueNextAddressRead=%u\n", pThis->uReplyPostQueueNextAddressRead);
4194 pHlp->pfnPrintf(pHlp, "uRequestQueueNextEntryFreeWrite=%u\n", pThis->uRequestQueueNextEntryFreeWrite);
4195 pHlp->pfnPrintf(pHlp, "uRequestQueueNextAddressRead=%u\n", pThis->uRequestQueueNextAddressRead);
4196
4197 /*
4198 * Show queue content if verbose
4199 */
4200 if (fVerbose)
4201 {
4202 for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
4203 pHlp->pfnPrintf(pHlp, "RFQ[%u]=%#x\n", i, pThis->pReplyFreeQueueBaseR3[i]);
4204
4205 pHlp->pfnPrintf(pHlp, "\n");
4206
4207 for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
4208 pHlp->pfnPrintf(pHlp, "RPQ[%u]=%#x\n", i, pThis->pReplyPostQueueBaseR3[i]);
4209
4210 pHlp->pfnPrintf(pHlp, "\n");
4211
4212 for (unsigned i = 0; i < pThis->cRequestQueueEntries; i++)
4213 pHlp->pfnPrintf(pHlp, "ReqQ[%u]=%#x\n", i, pThis->pRequestQueueBaseR3[i]);
4214 }
4215
4216 /*
4217 * Print the device status.
4218 */
4219 for (unsigned i = 0; i < pThis->cDeviceStates; i++)
4220 {
4221 PLSILOGICDEVICE pDevice = &pThis->paDeviceStates[i];
4222
4223 pHlp->pfnPrintf(pHlp, "\n");
4224
4225 pHlp->pfnPrintf(pHlp, "Device[%u]: device-attached=%RTbool cOutstandingRequests=%u\n",
4226 i, pDevice->pDrvBase != NULL, pDevice->cOutstandingRequests);
4227 }
4228}
4229
4230/**
4231 * Allocate the queues.
4232 *
4233 * @returns VBox status code.
4234 *
4235 * @param pThis Pointer to the LsiLogic device state.
4236 */
4237static int lsilogicR3QueuesAlloc(PLSILOGICSCSI pThis)
4238{
4239 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
4240 uint32_t cbQueues;
4241
4242 Assert(!pThis->pReplyFreeQueueBaseR3);
4243
4244 cbQueues = 2*pThis->cReplyQueueEntries * sizeof(uint32_t);
4245 cbQueues += pThis->cRequestQueueEntries * sizeof(uint32_t);
4246 int rc = MMHyperAlloc(pVM, cbQueues, 1, MM_TAG_PDM_DEVICE_USER,
4247 (void **)&pThis->pReplyFreeQueueBaseR3);
4248 if (RT_FAILURE(rc))
4249 return VERR_NO_MEMORY;
4250 pThis->pReplyFreeQueueBaseR0 = MMHyperR3ToR0(pVM, (void *)pThis->pReplyFreeQueueBaseR3);
4251 pThis->pReplyFreeQueueBaseRC = MMHyperR3ToRC(pVM, (void *)pThis->pReplyFreeQueueBaseR3);
4252
4253 pThis->pReplyPostQueueBaseR3 = pThis->pReplyFreeQueueBaseR3 + pThis->cReplyQueueEntries;
4254 pThis->pReplyPostQueueBaseR0 = MMHyperR3ToR0(pVM, (void *)pThis->pReplyPostQueueBaseR3);
4255 pThis->pReplyPostQueueBaseRC = MMHyperR3ToRC(pVM, (void *)pThis->pReplyPostQueueBaseR3);
4256
4257 pThis->pRequestQueueBaseR3 = pThis->pReplyPostQueueBaseR3 + pThis->cReplyQueueEntries;
4258 pThis->pRequestQueueBaseR0 = MMHyperR3ToR0(pVM, (void *)pThis->pRequestQueueBaseR3);
4259 pThis->pRequestQueueBaseRC = MMHyperR3ToRC(pVM, (void *)pThis->pRequestQueueBaseR3);
4260
4261 return VINF_SUCCESS;
4262}
4263
4264/**
4265 * Free the hyper memory used or the queues.
4266 *
4267 * @returns nothing.
4268 *
4269 * @param pThis Pointer to the LsiLogic device state.
4270 */
4271static void lsilogicR3QueuesFree(PLSILOGICSCSI pThis)
4272{
4273 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
4274 int rc = VINF_SUCCESS;
4275
4276 AssertPtr(pThis->pReplyFreeQueueBaseR3);
4277
4278 rc = MMHyperFree(pVM, (void *)pThis->pReplyFreeQueueBaseR3);
4279 AssertRC(rc);
4280
4281 pThis->pReplyFreeQueueBaseR3 = NULL;
4282 pThis->pReplyPostQueueBaseR3 = NULL;
4283 pThis->pRequestQueueBaseR3 = NULL;
4284}
4285
4286
4287/* The worker thread. */
4288static DECLCALLBACK(int) lsilogicR3Worker(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4289{
4290 PLSILOGICSCSI pThis = (PLSILOGICSCSI)pThread->pvUser;
4291 int rc = VINF_SUCCESS;
4292
4293 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
4294 return VINF_SUCCESS;
4295
4296 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4297 {
4298 ASMAtomicWriteBool(&pThis->fWrkThreadSleeping, true);
4299 bool fNotificationSent = ASMAtomicXchgBool(&pThis->fNotificationSent, false);
4300 if (!fNotificationSent)
4301 {
4302 Assert(ASMAtomicReadBool(&pThis->fWrkThreadSleeping));
4303 rc = SUPSemEventWaitNoResume(pThis->pSupDrvSession, pThis->hEvtProcess, RT_INDEFINITE_WAIT);
4304 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
4305 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
4306 break;
4307 LogFlowFunc(("Woken up with rc=%Rrc\n", rc));
4308 ASMAtomicWriteBool(&pThis->fNotificationSent, false);
4309 }
4310
4311 ASMAtomicWriteBool(&pThis->fWrkThreadSleeping, false);
4312
4313 /* Check whether there is a BIOS request pending and process it first. */
4314 if (ASMAtomicReadBool(&pThis->fBiosReqPending))
4315 {
4316 rc = lsilogicR3PrepareBiosScsiRequest(pThis);
4317 AssertRC(rc);
4318 ASMAtomicXchgBool(&pThis->fBiosReqPending, false);
4319 }
4320
4321 /* Only process request which arrived before we received the notification. */
4322 uint32_t uRequestQueueNextEntryWrite = ASMAtomicReadU32(&pThis->uRequestQueueNextEntryFreeWrite);
4323
4324 /* Go through the messages now and process them. */
4325 while ( RT_LIKELY(pThis->enmState == LSILOGICSTATE_OPERATIONAL)
4326 && (pThis->uRequestQueueNextAddressRead != uRequestQueueNextEntryWrite))
4327 {
4328 MptRequestUnion GuestRequest;
4329 uint32_t u32RequestMessageFrameDesc = pThis->CTX_SUFF(pRequestQueueBase)[pThis->uRequestQueueNextAddressRead];
4330 RTGCPHYS GCPhysMessageFrameAddr = LSILOGIC_RTGCPHYS_FROM_U32(pThis->u32HostMFAHighAddr,
4331 (u32RequestMessageFrameDesc & ~0x07));
4332
4333 /* Read the message header from the guest first. */
4334 PDMDevHlpPhysRead(pDevIns, GCPhysMessageFrameAddr, &GuestRequest, sizeof(MptMessageHdr));
4335
4336 /* Determine the size of the request. */
4337 uint32_t cbRequest = 0;
4338 switch (GuestRequest.Header.u8Function)
4339 {
4340 case MPT_MESSAGE_HDR_FUNCTION_SCSI_IO_REQUEST:
4341 cbRequest = sizeof(MptSCSIIORequest);
4342 break;
4343 case MPT_MESSAGE_HDR_FUNCTION_SCSI_TASK_MGMT:
4344 cbRequest = sizeof(MptSCSITaskManagementRequest);
4345 break;
4346 case MPT_MESSAGE_HDR_FUNCTION_IOC_INIT:
4347 cbRequest = sizeof(MptIOCInitRequest);
4348 break;
4349 case MPT_MESSAGE_HDR_FUNCTION_IOC_FACTS:
4350 cbRequest = sizeof(MptIOCFactsRequest);
4351 break;
4352 case MPT_MESSAGE_HDR_FUNCTION_CONFIG:
4353 cbRequest = sizeof(MptConfigurationRequest);
4354 break;
4355 case MPT_MESSAGE_HDR_FUNCTION_PORT_FACTS:
4356 cbRequest = sizeof(MptPortFactsRequest);
4357 break;
4358 case MPT_MESSAGE_HDR_FUNCTION_PORT_ENABLE:
4359 cbRequest = sizeof(MptPortEnableRequest);
4360 break;
4361 case MPT_MESSAGE_HDR_FUNCTION_EVENT_NOTIFICATION:
4362 cbRequest = sizeof(MptEventNotificationRequest);
4363 break;
4364 case MPT_MESSAGE_HDR_FUNCTION_EVENT_ACK:
4365 AssertMsgFailed(("todo\n"));
4366 //cbRequest = sizeof(MptEventAckRequest);
4367 break;
4368 case MPT_MESSAGE_HDR_FUNCTION_FW_DOWNLOAD:
4369 cbRequest = sizeof(MptFWDownloadRequest);
4370 break;
4371 case MPT_MESSAGE_HDR_FUNCTION_FW_UPLOAD:
4372 cbRequest = sizeof(MptFWUploadRequest);
4373 break;
4374 default:
4375 AssertMsgFailed(("Unknown function issued %u\n", GuestRequest.Header.u8Function));
4376 lsilogicSetIOCFaultCode(pThis, LSILOGIC_IOCSTATUS_INVALID_FUNCTION);
4377 }
4378
4379 if (cbRequest != 0)
4380 {
4381 /* Read the complete message frame from guest memory now. */
4382 PDMDevHlpPhysRead(pDevIns, GCPhysMessageFrameAddr, &GuestRequest, cbRequest);
4383
4384 /* Handle SCSI I/O requests now. */
4385 if (GuestRequest.Header.u8Function == MPT_MESSAGE_HDR_FUNCTION_SCSI_IO_REQUEST)
4386 {
4387 rc = lsilogicR3ProcessSCSIIORequest(pThis, GCPhysMessageFrameAddr, &GuestRequest);
4388 AssertRC(rc);
4389 }
4390 else
4391 {
4392 MptReplyUnion Reply;
4393 rc = lsilogicR3ProcessMessageRequest(pThis, &GuestRequest.Header, &Reply);
4394 AssertRC(rc);
4395 }
4396
4397 pThis->uRequestQueueNextAddressRead++;
4398 pThis->uRequestQueueNextAddressRead %= pThis->cRequestQueueEntries;
4399 }
4400 } /* While request frames available. */
4401 } /* While running */
4402
4403 return VINF_SUCCESS;
4404}
4405
4406
4407/**
4408 * Unblock the worker thread so it can respond to a state change.
4409 *
4410 * @returns VBox status code.
4411 * @param pDevIns The pcnet device instance.
4412 * @param pThread The send thread.
4413 */
4414static DECLCALLBACK(int) lsilogicR3WorkerWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4415{
4416 RT_NOREF(pThread);
4417 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4418 return SUPSemEventSignal(pThis->pSupDrvSession, pThis->hEvtProcess);
4419}
4420
4421
4422/**
4423 * Kicks the controller to process pending tasks after the VM was resumed
4424 * or loaded from a saved state.
4425 *
4426 * @returns nothing.
4427 * @param pThis Pointer to the LsiLogic device state.
4428 */
4429static void lsilogicR3Kick(PLSILOGICSCSI pThis)
4430{
4431 if (pThis->fNotificationSent)
4432 {
4433 /* Send a notifier to the PDM queue that there are pending requests. */
4434 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pNotificationQueue));
4435 AssertMsg(pItem, ("Allocating item for queue failed\n"));
4436 PDMQueueInsert(pThis->CTX_SUFF(pNotificationQueue), (PPDMQUEUEITEMCORE)pItem);
4437 }
4438}
4439
4440
4441/*
4442 * Saved state.
4443 */
4444
4445/**
4446 * @callback_method_impl{FNSSMDEVLIVEEXEC}
4447 */
4448static DECLCALLBACK(int) lsilogicR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
4449{
4450 RT_NOREF(uPass);
4451 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4452
4453 SSMR3PutU32(pSSM, pThis->enmCtrlType);
4454 SSMR3PutU32(pSSM, pThis->cDeviceStates);
4455 SSMR3PutU32(pSSM, pThis->cPorts);
4456
4457 /* Save the device config. */
4458 for (unsigned i = 0; i < pThis->cDeviceStates; i++)
4459 SSMR3PutBool(pSSM, pThis->paDeviceStates[i].pDrvBase != NULL);
4460
4461 return VINF_SSM_DONT_CALL_AGAIN;
4462}
4463
4464/**
4465 * @callback_method_impl{FNSSMDEVSAVEEXEC}
4466 */
4467static DECLCALLBACK(int) lsilogicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4468{
4469 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4470
4471 /* Every device first. */
4472 lsilogicR3LiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
4473 for (unsigned i = 0; i < pThis->cDeviceStates; i++)
4474 {
4475 PLSILOGICDEVICE pDevice = &pThis->paDeviceStates[i];
4476
4477 AssertMsg(!pDevice->cOutstandingRequests,
4478 ("There are still outstanding requests on this device\n"));
4479 SSMR3PutU32(pSSM, pDevice->cOutstandingRequests);
4480
4481 /* Query all suspended requests and store them in the request queue. */
4482 if (pDevice->pDrvMediaEx)
4483 {
4484 uint32_t cReqsRedo = pDevice->pDrvMediaEx->pfnIoReqGetSuspendedCount(pDevice->pDrvMediaEx);
4485 if (cReqsRedo)
4486 {
4487 PDMMEDIAEXIOREQ hIoReq;
4488 PLSILOGICREQ pReq;
4489 int rc = pDevice->pDrvMediaEx->pfnIoReqQuerySuspendedStart(pDevice->pDrvMediaEx, &hIoReq,
4490 (void **)&pReq);
4491 AssertRCBreak(rc);
4492
4493 for (;;)
4494 {
4495 if (!pReq->fBIOS)
4496 {
4497 /* Write only the lower 32bit part of the address. */
4498 ASMAtomicWriteU32(&pThis->CTX_SUFF(pRequestQueueBase)[pThis->uRequestQueueNextEntryFreeWrite],
4499 pReq->GCPhysMessageFrameAddr & UINT32_C(0xffffffff));
4500
4501 pThis->uRequestQueueNextEntryFreeWrite++;
4502 pThis->uRequestQueueNextEntryFreeWrite %= pThis->cRequestQueueEntries;
4503 }
4504 else
4505 {
4506 AssertMsg(!pReq->pRedoNext, ("Only one BIOS task can be active!\n"));
4507 vboxscsiSetRequestRedo(&pThis->VBoxSCSI);
4508 }
4509
4510 cReqsRedo--;
4511 if (!cReqsRedo)
4512 break;
4513
4514 rc = pDevice->pDrvMediaEx->pfnIoReqQuerySuspendedNext(pDevice->pDrvMediaEx, hIoReq,
4515 &hIoReq, (void **)&pReq);
4516 AssertRCBreak(rc);
4517 }
4518 }
4519 }
4520 }
4521
4522 /* Now the main device state. */
4523 SSMR3PutU32 (pSSM, pThis->enmState);
4524 SSMR3PutU32 (pSSM, pThis->enmWhoInit);
4525 SSMR3PutU32 (pSSM, pThis->enmDoorbellState);
4526 SSMR3PutBool (pSSM, pThis->fDiagnosticEnabled);
4527 SSMR3PutBool (pSSM, pThis->fNotificationSent);
4528 SSMR3PutBool (pSSM, pThis->fEventNotificationEnabled);
4529 SSMR3PutU32 (pSSM, pThis->uInterruptMask);
4530 SSMR3PutU32 (pSSM, pThis->uInterruptStatus);
4531 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMessage); i++)
4532 SSMR3PutU32 (pSSM, pThis->aMessage[i]);
4533 SSMR3PutU32 (pSSM, pThis->iMessage);
4534 SSMR3PutU32 (pSSM, pThis->cMessage);
4535 SSMR3PutMem (pSSM, &pThis->ReplyBuffer, sizeof(pThis->ReplyBuffer));
4536 SSMR3PutU32 (pSSM, pThis->uNextReplyEntryRead);
4537 SSMR3PutU32 (pSSM, pThis->cReplySize);
4538 SSMR3PutU16 (pSSM, pThis->u16IOCFaultCode);
4539 SSMR3PutU32 (pSSM, pThis->u32HostMFAHighAddr);
4540 SSMR3PutU32 (pSSM, pThis->u32SenseBufferHighAddr);
4541 SSMR3PutU8 (pSSM, pThis->cMaxDevices);
4542 SSMR3PutU8 (pSSM, pThis->cMaxBuses);
4543 SSMR3PutU16 (pSSM, pThis->cbReplyFrame);
4544 SSMR3PutU32 (pSSM, pThis->iDiagnosticAccess);
4545 SSMR3PutU32 (pSSM, pThis->cReplyQueueEntries);
4546 SSMR3PutU32 (pSSM, pThis->cRequestQueueEntries);
4547 SSMR3PutU32 (pSSM, pThis->uReplyFreeQueueNextEntryFreeWrite);
4548 SSMR3PutU32 (pSSM, pThis->uReplyFreeQueueNextAddressRead);
4549 SSMR3PutU32 (pSSM, pThis->uReplyPostQueueNextEntryFreeWrite);
4550 SSMR3PutU32 (pSSM, pThis->uReplyPostQueueNextAddressRead);
4551 SSMR3PutU32 (pSSM, pThis->uRequestQueueNextEntryFreeWrite);
4552 SSMR3PutU32 (pSSM, pThis->uRequestQueueNextAddressRead);
4553
4554 for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
4555 SSMR3PutU32(pSSM, pThis->pReplyFreeQueueBaseR3[i]);
4556 for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
4557 SSMR3PutU32(pSSM, pThis->pReplyPostQueueBaseR3[i]);
4558 for (unsigned i = 0; i < pThis->cRequestQueueEntries; i++)
4559 SSMR3PutU32(pSSM, pThis->pRequestQueueBaseR3[i]);
4560
4561 SSMR3PutU16 (pSSM, pThis->u16NextHandle);
4562
4563 /* Save diagnostic memory register and data regions. */
4564 SSMR3PutU32 (pSSM, pThis->u32DiagMemAddr);
4565 SSMR3PutU32 (pSSM, lsilogicR3MemRegionsCount(pThis));
4566
4567 PLSILOGICMEMREGN pIt;
4568 RTListForEach(&pThis->ListMemRegns, pIt, LSILOGICMEMREGN, NodeList)
4569 {
4570 SSMR3PutU32(pSSM, pIt->u32AddrStart);
4571 SSMR3PutU32(pSSM, pIt->u32AddrEnd);
4572 SSMR3PutMem(pSSM, &pIt->au32Data[0], (pIt->u32AddrEnd - pIt->u32AddrStart + 1) * sizeof(uint32_t));
4573 }
4574
4575 PMptConfigurationPagesSupported pPages = pThis->pConfigurationPages;
4576
4577 SSMR3PutMem (pSSM, &pPages->ManufacturingPage0, sizeof(MptConfigurationPageManufacturing0));
4578 SSMR3PutMem (pSSM, &pPages->ManufacturingPage1, sizeof(MptConfigurationPageManufacturing1));
4579 SSMR3PutMem (pSSM, &pPages->ManufacturingPage2, sizeof(MptConfigurationPageManufacturing2));
4580 SSMR3PutMem (pSSM, &pPages->ManufacturingPage3, sizeof(MptConfigurationPageManufacturing3));
4581 SSMR3PutMem (pSSM, &pPages->ManufacturingPage4, sizeof(MptConfigurationPageManufacturing4));
4582 SSMR3PutMem (pSSM, &pPages->ManufacturingPage5, sizeof(MptConfigurationPageManufacturing5));
4583 SSMR3PutMem (pSSM, &pPages->ManufacturingPage6, sizeof(MptConfigurationPageManufacturing6));
4584 SSMR3PutMem (pSSM, &pPages->ManufacturingPage8, sizeof(MptConfigurationPageManufacturing8));
4585 SSMR3PutMem (pSSM, &pPages->ManufacturingPage9, sizeof(MptConfigurationPageManufacturing9));
4586 SSMR3PutMem (pSSM, &pPages->ManufacturingPage10, sizeof(MptConfigurationPageManufacturing10));
4587 SSMR3PutMem (pSSM, &pPages->IOUnitPage0, sizeof(MptConfigurationPageIOUnit0));
4588 SSMR3PutMem (pSSM, &pPages->IOUnitPage1, sizeof(MptConfigurationPageIOUnit1));
4589 SSMR3PutMem (pSSM, &pPages->IOUnitPage2, sizeof(MptConfigurationPageIOUnit2));
4590 SSMR3PutMem (pSSM, &pPages->IOUnitPage3, sizeof(MptConfigurationPageIOUnit3));
4591 SSMR3PutMem (pSSM, &pPages->IOUnitPage4, sizeof(MptConfigurationPageIOUnit4));
4592 SSMR3PutMem (pSSM, &pPages->IOCPage0, sizeof(MptConfigurationPageIOC0));
4593 SSMR3PutMem (pSSM, &pPages->IOCPage1, sizeof(MptConfigurationPageIOC1));
4594 SSMR3PutMem (pSSM, &pPages->IOCPage2, sizeof(MptConfigurationPageIOC2));
4595 SSMR3PutMem (pSSM, &pPages->IOCPage3, sizeof(MptConfigurationPageIOC3));
4596 SSMR3PutMem (pSSM, &pPages->IOCPage4, sizeof(MptConfigurationPageIOC4));
4597 SSMR3PutMem (pSSM, &pPages->IOCPage6, sizeof(MptConfigurationPageIOC6));
4598 SSMR3PutMem (pSSM, &pPages->BIOSPage1, sizeof(MptConfigurationPageBIOS1));
4599 SSMR3PutMem (pSSM, &pPages->BIOSPage2, sizeof(MptConfigurationPageBIOS2));
4600 SSMR3PutMem (pSSM, &pPages->BIOSPage4, sizeof(MptConfigurationPageBIOS4));
4601
4602 /* Device dependent pages */
4603 if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
4604 {
4605 PMptConfigurationPagesSpi pSpiPages = &pPages->u.SpiPages;
4606
4607 SSMR3PutMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage0, sizeof(MptConfigurationPageSCSISPIPort0));
4608 SSMR3PutMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage1, sizeof(MptConfigurationPageSCSISPIPort1));
4609 SSMR3PutMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage2, sizeof(MptConfigurationPageSCSISPIPort2));
4610
4611 for (unsigned i = 0; i < RT_ELEMENTS(pSpiPages->aBuses[0].aDevicePages); i++)
4612 {
4613 SSMR3PutMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage0, sizeof(MptConfigurationPageSCSISPIDevice0));
4614 SSMR3PutMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage1, sizeof(MptConfigurationPageSCSISPIDevice1));
4615 SSMR3PutMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage2, sizeof(MptConfigurationPageSCSISPIDevice2));
4616 SSMR3PutMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage3, sizeof(MptConfigurationPageSCSISPIDevice3));
4617 }
4618 }
4619 else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
4620 {
4621 PMptConfigurationPagesSas pSasPages = &pPages->u.SasPages;
4622
4623 SSMR3PutU32(pSSM, pSasPages->cbManufacturingPage7);
4624 SSMR3PutU32(pSSM, pSasPages->cbSASIOUnitPage0);
4625 SSMR3PutU32(pSSM, pSasPages->cbSASIOUnitPage1);
4626
4627 SSMR3PutMem(pSSM, pSasPages->pManufacturingPage7, pSasPages->cbManufacturingPage7);
4628 SSMR3PutMem(pSSM, pSasPages->pSASIOUnitPage0, pSasPages->cbSASIOUnitPage0);
4629 SSMR3PutMem(pSSM, pSasPages->pSASIOUnitPage1, pSasPages->cbSASIOUnitPage1);
4630
4631 SSMR3PutMem(pSSM, &pSasPages->SASIOUnitPage2, sizeof(MptConfigurationPageSASIOUnit2));
4632 SSMR3PutMem(pSSM, &pSasPages->SASIOUnitPage3, sizeof(MptConfigurationPageSASIOUnit3));
4633
4634 SSMR3PutU32(pSSM, pSasPages->cPHYs);
4635 for (unsigned i = 0; i < pSasPages->cPHYs; i++)
4636 {
4637 SSMR3PutMem(pSSM, &pSasPages->paPHYs[i].SASPHYPage0, sizeof(MptConfigurationPageSASPHY0));
4638 SSMR3PutMem(pSSM, &pSasPages->paPHYs[i].SASPHYPage1, sizeof(MptConfigurationPageSASPHY1));
4639 }
4640
4641 /* The number of devices first. */
4642 SSMR3PutU32(pSSM, pSasPages->cDevices);
4643
4644 PMptSASDevice pCurr = pSasPages->pSASDeviceHead;
4645
4646 while (pCurr)
4647 {
4648 SSMR3PutMem(pSSM, &pCurr->SASDevicePage0, sizeof(MptConfigurationPageSASDevice0));
4649 SSMR3PutMem(pSSM, &pCurr->SASDevicePage1, sizeof(MptConfigurationPageSASDevice1));
4650 SSMR3PutMem(pSSM, &pCurr->SASDevicePage2, sizeof(MptConfigurationPageSASDevice2));
4651
4652 pCurr = pCurr->pNext;
4653 }
4654 }
4655 else
4656 AssertMsgFailed(("Invalid controller type %d\n", pThis->enmCtrlType));
4657
4658 vboxscsiR3SaveExec(&pThis->VBoxSCSI, pSSM);
4659 return SSMR3PutU32(pSSM, UINT32_MAX);
4660}
4661
4662/**
4663 * @callback_method_impl{FNSSMDEVLOADDONE}
4664 */
4665static DECLCALLBACK(int) lsilogicR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4666{
4667 RT_NOREF(pSSM);
4668 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4669
4670 lsilogicR3Kick(pThis);
4671 return VINF_SUCCESS;
4672}
4673
4674/**
4675 * @callback_method_impl{FNSSMDEVLOADEXEC}
4676 */
4677static DECLCALLBACK(int) lsilogicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4678{
4679 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4680 int rc;
4681
4682 if ( uVersion != LSILOGIC_SAVED_STATE_VERSION
4683 && uVersion != LSILOGIC_SAVED_STATE_VERSION_PRE_DIAG_MEM
4684 && uVersion != LSILOGIC_SAVED_STATE_VERSION_BOOL_DOORBELL
4685 && uVersion != LSILOGIC_SAVED_STATE_VERSION_PRE_SAS
4686 && uVersion != LSILOGIC_SAVED_STATE_VERSION_VBOX_30)
4687 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
4688
4689 /* device config */
4690 if (uVersion > LSILOGIC_SAVED_STATE_VERSION_PRE_SAS)
4691 {
4692 LSILOGICCTRLTYPE enmCtrlType;
4693 uint32_t cDeviceStates, cPorts;
4694
4695 rc = SSMR3GetU32(pSSM, (uint32_t *)&enmCtrlType);
4696 AssertRCReturn(rc, rc);
4697 rc = SSMR3GetU32(pSSM, &cDeviceStates);
4698 AssertRCReturn(rc, rc);
4699 rc = SSMR3GetU32(pSSM, &cPorts);
4700 AssertRCReturn(rc, rc);
4701
4702 if (enmCtrlType != pThis->enmCtrlType)
4703 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Target config mismatch (Controller type): config=%d state=%d"),
4704 pThis->enmCtrlType, enmCtrlType);
4705 if (cDeviceStates != pThis->cDeviceStates)
4706 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Target config mismatch (Device states): config=%u state=%u"),
4707 pThis->cDeviceStates, cDeviceStates);
4708 if (cPorts != pThis->cPorts)
4709 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Target config mismatch (Ports): config=%u state=%u"),
4710 pThis->cPorts, cPorts);
4711 }
4712 if (uVersion > LSILOGIC_SAVED_STATE_VERSION_VBOX_30)
4713 {
4714 for (unsigned i = 0; i < pThis->cDeviceStates; i++)
4715 {
4716 bool fPresent;
4717 rc = SSMR3GetBool(pSSM, &fPresent);
4718 AssertRCReturn(rc, rc);
4719 if (fPresent != (pThis->paDeviceStates[i].pDrvBase != NULL))
4720 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Target %u config mismatch: config=%RTbool state=%RTbool"),
4721 i, pThis->paDeviceStates[i].pDrvBase != NULL, fPresent);
4722 }
4723 }
4724 if (uPass != SSM_PASS_FINAL)
4725 return VINF_SUCCESS;
4726
4727 /* Every device first. */
4728 for (unsigned i = 0; i < pThis->cDeviceStates; i++)
4729 {
4730 PLSILOGICDEVICE pDevice = &pThis->paDeviceStates[i];
4731
4732 AssertMsg(!pDevice->cOutstandingRequests,
4733 ("There are still outstanding requests on this device\n"));
4734 SSMR3GetU32(pSSM, (uint32_t *)&pDevice->cOutstandingRequests);
4735 }
4736 /* Now the main device state. */
4737 SSMR3GetU32 (pSSM, (uint32_t *)&pThis->enmState);
4738 SSMR3GetU32 (pSSM, (uint32_t *)&pThis->enmWhoInit);
4739 if (uVersion <= LSILOGIC_SAVED_STATE_VERSION_BOOL_DOORBELL)
4740 {
4741 bool fDoorbellInProgress = false;
4742
4743 /*
4744 * The doorbell status flag distinguishes only between
4745 * doorbell not in use or a Function handshake is currently in progress.
4746 */
4747 SSMR3GetBool (pSSM, &fDoorbellInProgress);
4748 if (fDoorbellInProgress)
4749 pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_FN_HANDSHAKE;
4750 else
4751 pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_NOT_IN_USE;
4752 }
4753 else
4754 SSMR3GetU32(pSSM, (uint32_t *)&pThis->enmDoorbellState);
4755 SSMR3GetBool (pSSM, &pThis->fDiagnosticEnabled);
4756 SSMR3GetBool (pSSM, &pThis->fNotificationSent);
4757 SSMR3GetBool (pSSM, &pThis->fEventNotificationEnabled);
4758 SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uInterruptMask);
4759 SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uInterruptStatus);
4760 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMessage); i++)
4761 SSMR3GetU32 (pSSM, &pThis->aMessage[i]);
4762 SSMR3GetU32 (pSSM, &pThis->iMessage);
4763 SSMR3GetU32 (pSSM, &pThis->cMessage);
4764 SSMR3GetMem (pSSM, &pThis->ReplyBuffer, sizeof(pThis->ReplyBuffer));
4765 SSMR3GetU32 (pSSM, &pThis->uNextReplyEntryRead);
4766 SSMR3GetU32 (pSSM, &pThis->cReplySize);
4767 SSMR3GetU16 (pSSM, &pThis->u16IOCFaultCode);
4768 SSMR3GetU32 (pSSM, &pThis->u32HostMFAHighAddr);
4769 SSMR3GetU32 (pSSM, &pThis->u32SenseBufferHighAddr);
4770 SSMR3GetU8 (pSSM, &pThis->cMaxDevices);
4771 SSMR3GetU8 (pSSM, &pThis->cMaxBuses);
4772 SSMR3GetU16 (pSSM, &pThis->cbReplyFrame);
4773 SSMR3GetU32 (pSSM, &pThis->iDiagnosticAccess);
4774
4775 uint32_t cReplyQueueEntries, cRequestQueueEntries;
4776 SSMR3GetU32 (pSSM, &cReplyQueueEntries);
4777 SSMR3GetU32 (pSSM, &cRequestQueueEntries);
4778
4779 if ( cReplyQueueEntries != pThis->cReplyQueueEntries
4780 || cRequestQueueEntries != pThis->cRequestQueueEntries)
4781 {
4782 LogFlow(("Reallocating queues cReplyQueueEntries=%u cRequestQueuEntries=%u\n",
4783 cReplyQueueEntries, cRequestQueueEntries));
4784 lsilogicR3QueuesFree(pThis);
4785 pThis->cReplyQueueEntries = cReplyQueueEntries;
4786 pThis->cRequestQueueEntries = cRequestQueueEntries;
4787 rc = lsilogicR3QueuesAlloc(pThis);
4788 if (RT_FAILURE(rc))
4789 return rc;
4790 }
4791
4792 SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uReplyFreeQueueNextEntryFreeWrite);
4793 SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uReplyFreeQueueNextAddressRead);
4794 SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uReplyPostQueueNextEntryFreeWrite);
4795 SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uReplyPostQueueNextAddressRead);
4796 SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uRequestQueueNextEntryFreeWrite);
4797 SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uRequestQueueNextAddressRead);
4798
4799 PMptConfigurationPagesSupported pPages = pThis->pConfigurationPages;
4800
4801 if (uVersion <= LSILOGIC_SAVED_STATE_VERSION_PRE_SAS)
4802 {
4803 PMptConfigurationPagesSpi pSpiPages = &pPages->u.SpiPages;
4804 MptConfigurationPagesSupported_SSM_V2 ConfigPagesV2;
4805
4806 if (pThis->enmCtrlType != LSILOGICCTRLTYPE_SCSI_SPI)
4807 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: Expected SPI SCSI controller"));
4808
4809 SSMR3GetMem(pSSM, &ConfigPagesV2,
4810 sizeof(MptConfigurationPagesSupported_SSM_V2));
4811
4812 pPages->ManufacturingPage0 = ConfigPagesV2.ManufacturingPage0;
4813 pPages->ManufacturingPage1 = ConfigPagesV2.ManufacturingPage1;
4814 pPages->ManufacturingPage2 = ConfigPagesV2.ManufacturingPage2;
4815 pPages->ManufacturingPage3 = ConfigPagesV2.ManufacturingPage3;
4816 pPages->ManufacturingPage4 = ConfigPagesV2.ManufacturingPage4;
4817 pPages->IOUnitPage0 = ConfigPagesV2.IOUnitPage0;
4818 pPages->IOUnitPage1 = ConfigPagesV2.IOUnitPage1;
4819 pPages->IOUnitPage2 = ConfigPagesV2.IOUnitPage2;
4820 pPages->IOUnitPage3 = ConfigPagesV2.IOUnitPage3;
4821 pPages->IOCPage0 = ConfigPagesV2.IOCPage0;
4822 pPages->IOCPage1 = ConfigPagesV2.IOCPage1;
4823 pPages->IOCPage2 = ConfigPagesV2.IOCPage2;
4824 pPages->IOCPage3 = ConfigPagesV2.IOCPage3;
4825 pPages->IOCPage4 = ConfigPagesV2.IOCPage4;
4826 pPages->IOCPage6 = ConfigPagesV2.IOCPage6;
4827
4828 pSpiPages->aPortPages[0].SCSISPIPortPage0 = ConfigPagesV2.aPortPages[0].SCSISPIPortPage0;
4829 pSpiPages->aPortPages[0].SCSISPIPortPage1 = ConfigPagesV2.aPortPages[0].SCSISPIPortPage1;
4830 pSpiPages->aPortPages[0].SCSISPIPortPage2 = ConfigPagesV2.aPortPages[0].SCSISPIPortPage2;
4831
4832 for (unsigned i = 0; i < RT_ELEMENTS(pPages->u.SpiPages.aBuses[0].aDevicePages); i++)
4833 {
4834 pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage0 = ConfigPagesV2.aBuses[0].aDevicePages[i].SCSISPIDevicePage0;
4835 pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage1 = ConfigPagesV2.aBuses[0].aDevicePages[i].SCSISPIDevicePage1;
4836 pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage2 = ConfigPagesV2.aBuses[0].aDevicePages[i].SCSISPIDevicePage2;
4837 pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage3 = ConfigPagesV2.aBuses[0].aDevicePages[i].SCSISPIDevicePage3;
4838 }
4839 }
4840 else
4841 {
4842 /* Queue content */
4843 for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
4844 SSMR3GetU32(pSSM, (uint32_t *)&pThis->pReplyFreeQueueBaseR3[i]);
4845 for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
4846 SSMR3GetU32(pSSM, (uint32_t *)&pThis->pReplyPostQueueBaseR3[i]);
4847 for (unsigned i = 0; i < pThis->cRequestQueueEntries; i++)
4848 SSMR3GetU32(pSSM, (uint32_t *)&pThis->pRequestQueueBaseR3[i]);
4849
4850 SSMR3GetU16(pSSM, &pThis->u16NextHandle);
4851
4852 if (uVersion > LSILOGIC_SAVED_STATE_VERSION_PRE_DIAG_MEM)
4853 {
4854 uint32_t cMemRegions = 0;
4855
4856 /* Save diagnostic memory register and data regions. */
4857 SSMR3GetU32 (pSSM, &pThis->u32DiagMemAddr);
4858 SSMR3GetU32 (pSSM, &cMemRegions);
4859
4860 while (cMemRegions)
4861 {
4862 uint32_t u32AddrStart = 0;
4863 uint32_t u32AddrEnd = 0;
4864 uint32_t cRegion = 0;
4865 PLSILOGICMEMREGN pRegion = NULL;
4866
4867 SSMR3GetU32(pSSM, &u32AddrStart);
4868 SSMR3GetU32(pSSM, &u32AddrEnd);
4869
4870 cRegion = u32AddrEnd - u32AddrStart + 1;
4871 pRegion = (PLSILOGICMEMREGN)RTMemAllocZ(RT_OFFSETOF(LSILOGICMEMREGN, au32Data[cRegion]));
4872 if (pRegion)
4873 {
4874 pRegion->u32AddrStart = u32AddrStart;
4875 pRegion->u32AddrEnd = u32AddrEnd;
4876 SSMR3GetMem(pSSM, &pRegion->au32Data[0], cRegion * sizeof(uint32_t));
4877 lsilogicR3MemRegionInsert(pThis, pRegion);
4878 pThis->cbMemRegns += cRegion * sizeof(uint32_t);
4879 }
4880 else
4881 {
4882 /* Leave a log message but continue. */
4883 LogRel(("LsiLogic: Out of memory while restoring the state, might not work as expected\n"));
4884 SSMR3Skip(pSSM, cRegion * sizeof(uint32_t));
4885 }
4886 cMemRegions--;
4887 }
4888 }
4889
4890 /* Configuration pages */
4891 SSMR3GetMem(pSSM, &pPages->ManufacturingPage0, sizeof(MptConfigurationPageManufacturing0));
4892 SSMR3GetMem(pSSM, &pPages->ManufacturingPage1, sizeof(MptConfigurationPageManufacturing1));
4893 SSMR3GetMem(pSSM, &pPages->ManufacturingPage2, sizeof(MptConfigurationPageManufacturing2));
4894 SSMR3GetMem(pSSM, &pPages->ManufacturingPage3, sizeof(MptConfigurationPageManufacturing3));
4895 SSMR3GetMem(pSSM, &pPages->ManufacturingPage4, sizeof(MptConfigurationPageManufacturing4));
4896 SSMR3GetMem(pSSM, &pPages->ManufacturingPage5, sizeof(MptConfigurationPageManufacturing5));
4897 SSMR3GetMem(pSSM, &pPages->ManufacturingPage6, sizeof(MptConfigurationPageManufacturing6));
4898 SSMR3GetMem(pSSM, &pPages->ManufacturingPage8, sizeof(MptConfigurationPageManufacturing8));
4899 SSMR3GetMem(pSSM, &pPages->ManufacturingPage9, sizeof(MptConfigurationPageManufacturing9));
4900 SSMR3GetMem(pSSM, &pPages->ManufacturingPage10, sizeof(MptConfigurationPageManufacturing10));
4901 SSMR3GetMem(pSSM, &pPages->IOUnitPage0, sizeof(MptConfigurationPageIOUnit0));
4902 SSMR3GetMem(pSSM, &pPages->IOUnitPage1, sizeof(MptConfigurationPageIOUnit1));
4903 SSMR3GetMem(pSSM, &pPages->IOUnitPage2, sizeof(MptConfigurationPageIOUnit2));
4904 SSMR3GetMem(pSSM, &pPages->IOUnitPage3, sizeof(MptConfigurationPageIOUnit3));
4905 SSMR3GetMem(pSSM, &pPages->IOUnitPage4, sizeof(MptConfigurationPageIOUnit4));
4906 SSMR3GetMem(pSSM, &pPages->IOCPage0, sizeof(MptConfigurationPageIOC0));
4907 SSMR3GetMem(pSSM, &pPages->IOCPage1, sizeof(MptConfigurationPageIOC1));
4908 SSMR3GetMem(pSSM, &pPages->IOCPage2, sizeof(MptConfigurationPageIOC2));
4909 SSMR3GetMem(pSSM, &pPages->IOCPage3, sizeof(MptConfigurationPageIOC3));
4910 SSMR3GetMem(pSSM, &pPages->IOCPage4, sizeof(MptConfigurationPageIOC4));
4911 SSMR3GetMem(pSSM, &pPages->IOCPage6, sizeof(MptConfigurationPageIOC6));
4912 SSMR3GetMem(pSSM, &pPages->BIOSPage1, sizeof(MptConfigurationPageBIOS1));
4913 SSMR3GetMem(pSSM, &pPages->BIOSPage2, sizeof(MptConfigurationPageBIOS2));
4914 SSMR3GetMem(pSSM, &pPages->BIOSPage4, sizeof(MptConfigurationPageBIOS4));
4915
4916 /* Device dependent pages */
4917 if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
4918 {
4919 PMptConfigurationPagesSpi pSpiPages = &pPages->u.SpiPages;
4920
4921 SSMR3GetMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage0, sizeof(MptConfigurationPageSCSISPIPort0));
4922 SSMR3GetMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage1, sizeof(MptConfigurationPageSCSISPIPort1));
4923 SSMR3GetMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage2, sizeof(MptConfigurationPageSCSISPIPort2));
4924
4925 for (unsigned i = 0; i < RT_ELEMENTS(pSpiPages->aBuses[0].aDevicePages); i++)
4926 {
4927 SSMR3GetMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage0, sizeof(MptConfigurationPageSCSISPIDevice0));
4928 SSMR3GetMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage1, sizeof(MptConfigurationPageSCSISPIDevice1));
4929 SSMR3GetMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage2, sizeof(MptConfigurationPageSCSISPIDevice2));
4930 SSMR3GetMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage3, sizeof(MptConfigurationPageSCSISPIDevice3));
4931 }
4932 }
4933 else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
4934 {
4935 uint32_t cbPage0, cbPage1, cPHYs, cbManufacturingPage7;
4936 PMptConfigurationPagesSas pSasPages = &pPages->u.SasPages;
4937
4938 SSMR3GetU32(pSSM, &cbManufacturingPage7);
4939 SSMR3GetU32(pSSM, &cbPage0);
4940 SSMR3GetU32(pSSM, &cbPage1);
4941
4942 if ( (cbPage0 != pSasPages->cbSASIOUnitPage0)
4943 || (cbPage1 != pSasPages->cbSASIOUnitPage1)
4944 || (cbManufacturingPage7 != pSasPages->cbManufacturingPage7))
4945 return VERR_SSM_LOAD_CONFIG_MISMATCH;
4946
4947 AssertPtr(pSasPages->pManufacturingPage7);
4948 AssertPtr(pSasPages->pSASIOUnitPage0);
4949 AssertPtr(pSasPages->pSASIOUnitPage1);
4950
4951 SSMR3GetMem(pSSM, pSasPages->pManufacturingPage7, pSasPages->cbManufacturingPage7);
4952 SSMR3GetMem(pSSM, pSasPages->pSASIOUnitPage0, pSasPages->cbSASIOUnitPage0);
4953 SSMR3GetMem(pSSM, pSasPages->pSASIOUnitPage1, pSasPages->cbSASIOUnitPage1);
4954
4955 SSMR3GetMem(pSSM, &pSasPages->SASIOUnitPage2, sizeof(MptConfigurationPageSASIOUnit2));
4956 SSMR3GetMem(pSSM, &pSasPages->SASIOUnitPage3, sizeof(MptConfigurationPageSASIOUnit3));
4957
4958 SSMR3GetU32(pSSM, &cPHYs);
4959 if (cPHYs != pSasPages->cPHYs)
4960 return VERR_SSM_LOAD_CONFIG_MISMATCH;
4961
4962 AssertPtr(pSasPages->paPHYs);
4963 for (unsigned i = 0; i < pSasPages->cPHYs; i++)
4964 {
4965 SSMR3GetMem(pSSM, &pSasPages->paPHYs[i].SASPHYPage0, sizeof(MptConfigurationPageSASPHY0));
4966 SSMR3GetMem(pSSM, &pSasPages->paPHYs[i].SASPHYPage1, sizeof(MptConfigurationPageSASPHY1));
4967 }
4968
4969 /* The number of devices first. */
4970 SSMR3GetU32(pSSM, &pSasPages->cDevices);
4971
4972 PMptSASDevice pCurr = pSasPages->pSASDeviceHead;
4973
4974 for (unsigned i = 0; i < pSasPages->cDevices; i++)
4975 {
4976 SSMR3GetMem(pSSM, &pCurr->SASDevicePage0, sizeof(MptConfigurationPageSASDevice0));
4977 SSMR3GetMem(pSSM, &pCurr->SASDevicePage1, sizeof(MptConfigurationPageSASDevice1));
4978 SSMR3GetMem(pSSM, &pCurr->SASDevicePage2, sizeof(MptConfigurationPageSASDevice2));
4979
4980 pCurr = pCurr->pNext;
4981 }
4982
4983 Assert(!pCurr);
4984 }
4985 else
4986 AssertMsgFailed(("Invalid controller type %d\n", pThis->enmCtrlType));
4987 }
4988
4989 rc = vboxscsiR3LoadExec(&pThis->VBoxSCSI, pSSM);
4990 if (RT_FAILURE(rc))
4991 {
4992 LogRel(("LsiLogic: Failed to restore BIOS state: %Rrc.\n", rc));
4993 return PDMDEV_SET_ERROR(pDevIns, rc,
4994 N_("LsiLogic: Failed to restore BIOS state\n"));
4995 }
4996
4997 uint32_t u32;
4998 rc = SSMR3GetU32(pSSM, &u32);
4999 if (RT_FAILURE(rc))
5000 return rc;
5001 AssertMsgReturn(u32 == UINT32_MAX, ("%#x\n", u32), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5002
5003 return VINF_SUCCESS;
5004}
5005
5006
5007/*
5008 * The device level IBASE and LED interfaces.
5009 */
5010
5011/**
5012 * @interface_method_impl{PDMILEDPORTS,pfnQueryStatusLed, For a SCSI device.}
5013 *
5014 * @remarks Called by the scsi driver, proxying the main calls.
5015 */
5016static DECLCALLBACK(int) lsilogicR3DeviceQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
5017{
5018 PLSILOGICDEVICE pDevice = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, ILed);
5019 if (iLUN == 0)
5020 {
5021 *ppLed = &pDevice->Led;
5022 Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
5023 return VINF_SUCCESS;
5024 }
5025 return VERR_PDM_LUN_NOT_FOUND;
5026}
5027
5028
5029/**
5030 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
5031 */
5032static DECLCALLBACK(void *) lsilogicR3DeviceQueryInterface(PPDMIBASE pInterface, const char *pszIID)
5033{
5034 PLSILOGICDEVICE pDevice = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, IBase);
5035
5036 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevice->IBase);
5037 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIMEDIAPORT, &pDevice->IMediaPort);
5038 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIMEDIAEXPORT, &pDevice->IMediaExPort);
5039 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pDevice->ILed);
5040 return NULL;
5041}
5042
5043
5044/*
5045 * The controller level IBASE and LED interfaces.
5046 */
5047
5048/**
5049 * Gets the pointer to the status LED of a unit.
5050 *
5051 * @returns VBox status code.
5052 * @param pInterface Pointer to the interface structure containing the called function pointer.
5053 * @param iLUN The unit which status LED we desire.
5054 * @param ppLed Where to store the LED pointer.
5055 */
5056static DECLCALLBACK(int) lsilogicR3StatusQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
5057{
5058 PLSILOGICSCSI pThis = RT_FROM_MEMBER(pInterface, LSILOGICSCSI, ILeds);
5059 if (iLUN < pThis->cDeviceStates)
5060 {
5061 *ppLed = &pThis->paDeviceStates[iLUN].Led;
5062 Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
5063 return VINF_SUCCESS;
5064 }
5065 return VERR_PDM_LUN_NOT_FOUND;
5066}
5067
5068/**
5069 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
5070 */
5071static DECLCALLBACK(void *) lsilogicR3StatusQueryInterface(PPDMIBASE pInterface, const char *pszIID)
5072{
5073 PLSILOGICSCSI pThis = RT_FROM_MEMBER(pInterface, LSILOGICSCSI, IBase);
5074 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
5075 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
5076 return NULL;
5077}
5078
5079
5080/*
5081 * The PDM device interface and some helpers.
5082 */
5083
5084/**
5085 * Checks if all asynchronous I/O is finished.
5086 *
5087 * Used by lsilogicR3Reset, lsilogicR3Suspend and lsilogicR3PowerOff.
5088 *
5089 * @returns true if quiesced, false if busy.
5090 * @param pDevIns The device instance.
5091 */
5092static bool lsilogicR3AllAsyncIOIsFinished(PPDMDEVINS pDevIns)
5093{
5094 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5095
5096 for (uint32_t i = 0; i < pThis->cDeviceStates; i++)
5097 {
5098 PLSILOGICDEVICE pThisDevice = &pThis->paDeviceStates[i];
5099 if (pThisDevice->pDrvBase)
5100 {
5101 if (pThisDevice->cOutstandingRequests != 0)
5102 return false;
5103 }
5104 }
5105
5106 return true;
5107}
5108
5109/**
5110 * @callback_method_impl{FNPDMDEVASYNCNOTIFY,
5111 * Callback employed by lsilogicR3Suspend and lsilogicR3PowerOff.}
5112 */
5113static DECLCALLBACK(bool) lsilogicR3IsAsyncSuspendOrPowerOffDone(PPDMDEVINS pDevIns)
5114{
5115 if (!lsilogicR3AllAsyncIOIsFinished(pDevIns))
5116 return false;
5117
5118 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5119 ASMAtomicWriteBool(&pThis->fSignalIdle, false);
5120 return true;
5121}
5122
5123/**
5124 * Common worker for ahciR3Suspend and ahciR3PowerOff.
5125 */
5126static void lsilogicR3SuspendOrPowerOff(PPDMDEVINS pDevIns)
5127{
5128 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5129
5130 ASMAtomicWriteBool(&pThis->fSignalIdle, true);
5131 if (!lsilogicR3AllAsyncIOIsFinished(pDevIns))
5132 PDMDevHlpSetAsyncNotification(pDevIns, lsilogicR3IsAsyncSuspendOrPowerOffDone);
5133 else
5134 {
5135 ASMAtomicWriteBool(&pThis->fSignalIdle, false);
5136
5137 AssertMsg(!pThis->fNotificationSent, ("The PDM Queue should be empty at this point\n"));
5138 }
5139
5140 for (uint32_t i = 0; i < pThis->cDeviceStates; i++)
5141 {
5142 PLSILOGICDEVICE pThisDevice = &pThis->paDeviceStates[i];
5143 if (pThisDevice->pDrvMediaEx)
5144 pThisDevice->pDrvMediaEx->pfnNotifySuspend(pThisDevice->pDrvMediaEx);
5145 }
5146}
5147
5148/**
5149 * @interface_method_impl{PDMDEVREG,pfnSuspend}
5150 */
5151static DECLCALLBACK(void) lsilogicR3Suspend(PPDMDEVINS pDevIns)
5152{
5153 Log(("lsilogicR3Suspend\n"));
5154 lsilogicR3SuspendOrPowerOff(pDevIns);
5155}
5156
5157/**
5158 * @interface_method_impl{PDMDEVREG,pfnResume}
5159 */
5160static DECLCALLBACK(void) lsilogicR3Resume(PPDMDEVINS pDevIns)
5161{
5162 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5163
5164 Log(("lsilogicR3Resume\n"));
5165
5166 lsilogicR3Kick(pThis);
5167}
5168
5169/**
5170 * @interface_method_impl{PDMDEVREG,pfnDetach}
5171 *
5172 * One harddisk at one port has been unplugged.
5173 * The VM is suspended at this point.
5174 */
5175static DECLCALLBACK(void) lsilogicR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
5176{
5177 RT_NOREF(fFlags);
5178 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5179 PLSILOGICDEVICE pDevice = &pThis->paDeviceStates[iLUN];
5180
5181 if (iLUN >= pThis->cDeviceStates)
5182 return;
5183
5184 AssertMsg(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
5185 ("LsiLogic: Device does not support hotplugging\n"));
5186
5187 Log(("%s:\n", __FUNCTION__));
5188
5189 /*
5190 * Zero some important members.
5191 */
5192 pDevice->pDrvBase = NULL;
5193 pDevice->pDrvMedia = NULL;
5194 pDevice->pDrvMediaEx = NULL;
5195}
5196
5197/**
5198 * @interface_method_impl{PDMDEVREG,pfnAttach}
5199 */
5200static DECLCALLBACK(int) lsilogicR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
5201{
5202 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5203 PLSILOGICDEVICE pDevice = &pThis->paDeviceStates[iLUN];
5204 int rc;
5205
5206 if (iLUN >= pThis->cDeviceStates)
5207 return VERR_PDM_LUN_NOT_FOUND;
5208
5209 AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
5210 ("LsiLogic: Device does not support hotplugging\n"),
5211 VERR_INVALID_PARAMETER);
5212
5213 /* the usual paranoia */
5214 AssertRelease(!pDevice->pDrvBase);
5215 AssertRelease(!pDevice->pDrvMedia);
5216 AssertRelease(!pDevice->pDrvMediaEx);
5217 Assert(pDevice->iLUN == iLUN);
5218
5219 /*
5220 * Try attach the block device and get the interfaces,
5221 * required as well as optional.
5222 */
5223 rc = PDMDevHlpDriverAttach(pDevIns, pDevice->iLUN, &pDevice->IBase, &pDevice->pDrvBase, NULL);
5224 if (RT_SUCCESS(rc))
5225 {
5226 /* Query the media interface. */
5227 pDevice->pDrvMedia = PDMIBASE_QUERY_INTERFACE(pDevice->pDrvBase, PDMIMEDIA);
5228 AssertMsgReturn(VALID_PTR(pDevice->pDrvMedia),
5229 ("LsiLogic configuration error: LUN#%d misses the basic media interface!\n", pDevice->iLUN),
5230 VERR_PDM_MISSING_INTERFACE);
5231
5232 /* Get the extended media interface. */
5233 pDevice->pDrvMediaEx = PDMIBASE_QUERY_INTERFACE(pDevice->pDrvBase, PDMIMEDIAEX);
5234 AssertMsgReturn(VALID_PTR(pDevice->pDrvMediaEx),
5235 ("LsiLogic configuration error: LUN#%d misses the extended media interface!\n", pDevice->iLUN),
5236 VERR_PDM_MISSING_INTERFACE);
5237
5238 rc = pDevice->pDrvMediaEx->pfnIoReqAllocSizeSet(pDevice->pDrvMediaEx, sizeof(LSILOGICREQ));
5239 AssertMsgRCReturn(rc, ("LsiLogic configuration error: LUN#%u: Failed to set I/O request size!", pDevice->iLUN),
5240 rc);
5241 }
5242 else
5243 AssertMsgFailed(("Failed to attach LUN#%d. rc=%Rrc\n", pDevice->iLUN, rc));
5244
5245 if (RT_FAILURE(rc))
5246 {
5247 pDevice->pDrvBase = NULL;
5248 pDevice->pDrvMedia = NULL;
5249 pDevice->pDrvMediaEx = NULL;
5250 }
5251 return rc;
5252}
5253
5254/**
5255 * Common reset worker.
5256 *
5257 * @param pDevIns The device instance data.
5258 */
5259static void lsilogicR3ResetCommon(PPDMDEVINS pDevIns)
5260{
5261 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5262 int rc;
5263
5264 rc = lsilogicR3HardReset(pThis);
5265 AssertRC(rc);
5266
5267 vboxscsiInitialize(&pThis->VBoxSCSI);
5268}
5269
5270/**
5271 * @callback_method_impl{FNPDMDEVASYNCNOTIFY,
5272 * Callback employed by lsilogicR3Reset.}
5273 */
5274static DECLCALLBACK(bool) lsilogicR3IsAsyncResetDone(PPDMDEVINS pDevIns)
5275{
5276 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5277
5278 if (!lsilogicR3AllAsyncIOIsFinished(pDevIns))
5279 return false;
5280 ASMAtomicWriteBool(&pThis->fSignalIdle, false);
5281
5282 lsilogicR3ResetCommon(pDevIns);
5283 return true;
5284}
5285
5286/**
5287 * @interface_method_impl{PDMDEVREG,pfnReset}
5288 */
5289static DECLCALLBACK(void) lsilogicR3Reset(PPDMDEVINS pDevIns)
5290{
5291 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5292
5293 ASMAtomicWriteBool(&pThis->fSignalIdle, true);
5294 if (!lsilogicR3AllAsyncIOIsFinished(pDevIns))
5295 PDMDevHlpSetAsyncNotification(pDevIns, lsilogicR3IsAsyncResetDone);
5296 else
5297 {
5298 ASMAtomicWriteBool(&pThis->fSignalIdle, false);
5299 lsilogicR3ResetCommon(pDevIns);
5300 }
5301}
5302
5303/**
5304 * @interface_method_impl{PDMDEVREG,pfnRelocate}
5305 */
5306static DECLCALLBACK(void) lsilogicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
5307{
5308 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5309
5310 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5311 pThis->pNotificationQueueRC = PDMQueueRCPtr(pThis->pNotificationQueueR3);
5312
5313 /* Relocate queues. */
5314 pThis->pReplyFreeQueueBaseRC += offDelta;
5315 pThis->pReplyPostQueueBaseRC += offDelta;
5316 pThis->pRequestQueueBaseRC += offDelta;
5317}
5318
5319/**
5320 * @interface_method_impl{PDMDEVREG,pfnPowerOff}
5321 */
5322static DECLCALLBACK(void) lsilogicR3PowerOff(PPDMDEVINS pDevIns)
5323{
5324 Log(("lsilogicR3PowerOff\n"));
5325 lsilogicR3SuspendOrPowerOff(pDevIns);
5326}
5327
5328/**
5329 * @interface_method_impl{PDMDEVREG,pfnDestruct}
5330 */
5331static DECLCALLBACK(int) lsilogicR3Destruct(PPDMDEVINS pDevIns)
5332{
5333 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5334 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
5335
5336 PDMR3CritSectDelete(&pThis->ReplyFreeQueueCritSect);
5337 PDMR3CritSectDelete(&pThis->ReplyPostQueueCritSect);
5338 PDMR3CritSectDelete(&pThis->RequestQueueCritSect);
5339 PDMR3CritSectDelete(&pThis->ReplyFreeQueueWriteCritSect);
5340
5341 RTMemFree(pThis->paDeviceStates);
5342 pThis->paDeviceStates = NULL;
5343
5344 if (pThis->hEvtProcess != NIL_SUPSEMEVENT)
5345 {
5346 SUPSemEventClose(pThis->pSupDrvSession, pThis->hEvtProcess);
5347 pThis->hEvtProcess = NIL_SUPSEMEVENT;
5348 }
5349
5350 lsilogicR3ConfigurationPagesFree(pThis);
5351 lsilogicR3MemRegionsFree(pThis);
5352
5353 return VINF_SUCCESS;
5354}
5355
5356/**
5357 * @interface_method_impl{PDMDEVREG,pfnConstruct}
5358 */
5359static DECLCALLBACK(int) lsilogicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
5360{
5361 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5362 int rc = VINF_SUCCESS;
5363 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5364
5365 /*
5366 * Initialize enought of the state to make the destructure not trip up.
5367 */
5368 pThis->hEvtProcess = NIL_SUPSEMEVENT;
5369 pThis->fBiosReqPending = false;
5370 RTListInit(&pThis->ListMemRegns);
5371
5372 /*
5373 * Validate and read configuration.
5374 */
5375 rc = CFGMR3AreValuesValid(pCfg, "GCEnabled\0"
5376 "R0Enabled\0"
5377 "ReplyQueueDepth\0"
5378 "RequestQueueDepth\0"
5379 "ControllerType\0"
5380 "NumPorts\0"
5381 "Bootable\0");
5382 if (RT_FAILURE(rc))
5383 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
5384 N_("LsiLogic configuration error: unknown option specified"));
5385 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &pThis->fGCEnabled, true);
5386 if (RT_FAILURE(rc))
5387 return PDMDEV_SET_ERROR(pDevIns, rc,
5388 N_("LsiLogic configuration error: failed to read GCEnabled as boolean"));
5389 Log(("%s: fGCEnabled=%d\n", __FUNCTION__, pThis->fGCEnabled));
5390
5391 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, true);
5392 if (RT_FAILURE(rc))
5393 return PDMDEV_SET_ERROR(pDevIns, rc,
5394 N_("LsiLogic configuration error: failed to read R0Enabled as boolean"));
5395 Log(("%s: fR0Enabled=%d\n", __FUNCTION__, pThis->fR0Enabled));
5396
5397 rc = CFGMR3QueryU32Def(pCfg, "ReplyQueueDepth",
5398 &pThis->cReplyQueueEntries,
5399 LSILOGICSCSI_REPLY_QUEUE_DEPTH_DEFAULT);
5400 if (RT_FAILURE(rc))
5401 return PDMDEV_SET_ERROR(pDevIns, rc,
5402 N_("LsiLogic configuration error: failed to read ReplyQueue as integer"));
5403 Log(("%s: ReplyQueueDepth=%u\n", __FUNCTION__, pThis->cReplyQueueEntries));
5404
5405 rc = CFGMR3QueryU32Def(pCfg, "RequestQueueDepth",
5406 &pThis->cRequestQueueEntries,
5407 LSILOGICSCSI_REQUEST_QUEUE_DEPTH_DEFAULT);
5408 if (RT_FAILURE(rc))
5409 return PDMDEV_SET_ERROR(pDevIns, rc,
5410 N_("LsiLogic configuration error: failed to read RequestQueue as integer"));
5411 Log(("%s: RequestQueueDepth=%u\n", __FUNCTION__, pThis->cRequestQueueEntries));
5412
5413 char *pszCtrlType;
5414 rc = CFGMR3QueryStringAllocDef(pCfg, "ControllerType",
5415 &pszCtrlType, LSILOGICSCSI_PCI_SPI_CTRLNAME);
5416 if (RT_FAILURE(rc))
5417 return PDMDEV_SET_ERROR(pDevIns, rc,
5418 N_("LsiLogic configuration error: failed to read ControllerType as string"));
5419 Log(("%s: ControllerType=%s\n", __FUNCTION__, pszCtrlType));
5420
5421 rc = lsilogicR3GetCtrlTypeFromString(pThis, pszCtrlType);
5422 MMR3HeapFree(pszCtrlType);
5423
5424 char szDevTag[20];
5425 RTStrPrintf(szDevTag, sizeof(szDevTag), "LSILOGIC%s-%u",
5426 pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI ? "SPI" : "SAS",
5427 iInstance);
5428
5429
5430 if (RT_FAILURE(rc))
5431 return PDMDEV_SET_ERROR(pDevIns, rc,
5432 N_("LsiLogic configuration error: failed to determine controller type from string"));
5433
5434 rc = CFGMR3QueryU8(pCfg, "NumPorts",
5435 &pThis->cPorts);
5436 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
5437 {
5438 if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
5439 pThis->cPorts = LSILOGICSCSI_PCI_SPI_PORTS_MAX;
5440 else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
5441 pThis->cPorts = LSILOGICSCSI_PCI_SAS_PORTS_DEFAULT;
5442 else
5443 AssertMsgFailed(("Invalid controller type: %d\n", pThis->enmCtrlType));
5444 }
5445 else if (RT_FAILURE(rc))
5446 return PDMDEV_SET_ERROR(pDevIns, rc,
5447 N_("LsiLogic configuration error: failed to read NumPorts as integer"));
5448
5449 bool fBootable;
5450 rc = CFGMR3QueryBoolDef(pCfg, "Bootable", &fBootable, true);
5451 if (RT_FAILURE(rc))
5452 return PDMDEV_SET_ERROR(pDevIns, rc,
5453 N_("LsiLogic configuration error: failed to read Bootable as boolean"));
5454 Log(("%s: Bootable=%RTbool\n", __FUNCTION__, fBootable));
5455
5456 /* Init static parts. */
5457 PCIDevSetVendorId(&pThis->PciDev, LSILOGICSCSI_PCI_VENDOR_ID); /* LsiLogic */
5458
5459 if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
5460 {
5461 PCIDevSetDeviceId (&pThis->PciDev, LSILOGICSCSI_PCI_SPI_DEVICE_ID); /* LSI53C1030 */
5462 PCIDevSetSubSystemVendorId(&pThis->PciDev, LSILOGICSCSI_PCI_SPI_SUBSYSTEM_VENDOR_ID);
5463 PCIDevSetSubSystemId (&pThis->PciDev, LSILOGICSCSI_PCI_SPI_SUBSYSTEM_ID);
5464 }
5465 else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
5466 {
5467 PCIDevSetDeviceId (&pThis->PciDev, LSILOGICSCSI_PCI_SAS_DEVICE_ID); /* SAS1068 */
5468 PCIDevSetSubSystemVendorId(&pThis->PciDev, LSILOGICSCSI_PCI_SAS_SUBSYSTEM_VENDOR_ID);
5469 PCIDevSetSubSystemId (&pThis->PciDev, LSILOGICSCSI_PCI_SAS_SUBSYSTEM_ID);
5470 }
5471 else
5472 AssertMsgFailed(("Invalid controller type: %d\n", pThis->enmCtrlType));
5473
5474 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* SCSI */
5475 PCIDevSetClassSub (&pThis->PciDev, 0x00); /* SCSI */
5476 PCIDevSetClassBase (&pThis->PciDev, 0x01); /* Mass storage */
5477 PCIDevSetInterruptPin(&pThis->PciDev, 0x01); /* Interrupt pin A */
5478
5479# ifdef VBOX_WITH_MSI_DEVICES
5480 PCIDevSetStatus(&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST);
5481 PCIDevSetCapabilityList(&pThis->PciDev, 0x80);
5482# endif
5483
5484 pThis->pDevInsR3 = pDevIns;
5485 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
5486 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5487 pThis->pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
5488 pThis->IBase.pfnQueryInterface = lsilogicR3StatusQueryInterface;
5489 pThis->ILeds.pfnQueryStatusLed = lsilogicR3StatusQueryStatusLed;
5490
5491 /*
5492 * Create critical sections protecting the reply post and free queues.
5493 * Note! We do our own syncronization, so NOP the default crit sect for the device.
5494 */
5495 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
5496 AssertRCReturn(rc, rc);
5497
5498 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->ReplyFreeQueueCritSect, RT_SRC_POS, "%sRFQ", szDevTag);
5499 if (RT_FAILURE(rc))
5500 return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic: cannot create critical section for reply free queue"));
5501
5502 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->ReplyPostQueueCritSect, RT_SRC_POS, "%sRPQ", szDevTag);
5503 if (RT_FAILURE(rc))
5504 return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic: cannot create critical section for reply post queue"));
5505
5506 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->RequestQueueCritSect, RT_SRC_POS, "%sRQ", szDevTag);
5507 if (RT_FAILURE(rc))
5508 return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic: cannot create critical section for request queue"));
5509
5510 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->ReplyFreeQueueWriteCritSect, RT_SRC_POS, "%sRFQW", szDevTag);
5511 if (RT_FAILURE(rc))
5512 return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic: cannot create critical section for reply free queue write access"));
5513
5514 /*
5515 * Register the PCI device, it's I/O regions.
5516 */
5517 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
5518 if (RT_FAILURE(rc))
5519 return rc;
5520
5521# ifdef VBOX_WITH_MSI_DEVICES
5522 PDMMSIREG MsiReg;
5523 RT_ZERO(MsiReg);
5524 /* use this code for MSI-X support */
5525# if 0
5526 MsiReg.cMsixVectors = 1;
5527 MsiReg.iMsixCapOffset = 0x80;
5528 MsiReg.iMsixNextOffset = 0x00;
5529 MsiReg.iMsixBar = 3;
5530# else
5531 MsiReg.cMsiVectors = 1;
5532 MsiReg.iMsiCapOffset = 0x80;
5533 MsiReg.iMsiNextOffset = 0x00;
5534# endif
5535 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
5536 if (RT_FAILURE (rc))
5537 {
5538 /* That's OK, we can work without MSI */
5539 PCIDevSetCapabilityList(&pThis->PciDev, 0x0);
5540 }
5541# endif
5542
5543 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, LSILOGIC_PCI_SPACE_IO_SIZE, PCI_ADDRESS_SPACE_IO, lsilogicR3Map);
5544 if (RT_FAILURE(rc))
5545 return rc;
5546
5547 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 1, LSILOGIC_PCI_SPACE_MEM_SIZE, PCI_ADDRESS_SPACE_MEM, lsilogicR3Map);
5548 if (RT_FAILURE(rc))
5549 return rc;
5550
5551 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 2, LSILOGIC_PCI_SPACE_MEM_SIZE, PCI_ADDRESS_SPACE_MEM, lsilogicR3Map);
5552 if (RT_FAILURE(rc))
5553 return rc;
5554
5555 /* Initialize task queue. (Need two items to handle SMP guest concurrency.) */
5556 char szTaggedText[64];
5557 RTStrPrintf(szTaggedText, sizeof(szTaggedText), "%s-Task", szDevTag);
5558 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 2, 0,
5559 lsilogicR3NotifyQueueConsumer, true,
5560 szTaggedText,
5561 &pThis->pNotificationQueueR3);
5562 if (RT_FAILURE(rc))
5563 return rc;
5564 pThis->pNotificationQueueR0 = PDMQueueR0Ptr(pThis->pNotificationQueueR3);
5565 pThis->pNotificationQueueRC = PDMQueueRCPtr(pThis->pNotificationQueueR3);
5566
5567 /*
5568 * We need one entry free in the queue.
5569 */
5570 pThis->cReplyQueueEntries++;
5571 pThis->cRequestQueueEntries++;
5572
5573 /*
5574 * Allocate memory for the queues.
5575 */
5576 rc = lsilogicR3QueuesAlloc(pThis);
5577 if (RT_FAILURE(rc))
5578 return rc;
5579
5580 if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
5581 pThis->cDeviceStates = pThis->cPorts * LSILOGICSCSI_PCI_SPI_DEVICES_PER_BUS_MAX;
5582 else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
5583 pThis->cDeviceStates = pThis->cPorts * LSILOGICSCSI_PCI_SAS_DEVICES_PER_PORT_MAX;
5584 else
5585 AssertMsgFailed(("Invalid controller type: %d\n", pThis->enmCtrlType));
5586
5587 /*
5588 * Create event semaphore and worker thread.
5589 */
5590 rc = PDMDevHlpThreadCreate(pDevIns, &pThis->pThreadWrk, pThis, lsilogicR3Worker,
5591 lsilogicR3WorkerWakeUp, 0, RTTHREADTYPE_IO, szDevTag);
5592 if (RT_FAILURE(rc))
5593 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
5594 N_("LsiLogic: Failed to create worker thread %s"), szDevTag);
5595
5596 rc = SUPSemEventCreate(pThis->pSupDrvSession, &pThis->hEvtProcess);
5597 if (RT_FAILURE(rc))
5598 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
5599 N_("LsiLogic: Failed to create SUP event semaphore"));
5600
5601 /*
5602 * Allocate device states.
5603 */
5604 pThis->paDeviceStates = (PLSILOGICDEVICE)RTMemAllocZ(sizeof(LSILOGICDEVICE) * pThis->cDeviceStates);
5605 if (!pThis->paDeviceStates)
5606 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to allocate memory for device states"));
5607
5608 for (unsigned i = 0; i < pThis->cDeviceStates; i++)
5609 {
5610 PLSILOGICDEVICE pDevice = &pThis->paDeviceStates[i];
5611
5612 /* Initialize static parts of the device. */
5613 pDevice->iLUN = i;
5614 pDevice->pLsiLogicR3 = pThis;
5615 pDevice->Led.u32Magic = PDMLED_MAGIC;
5616 pDevice->IBase.pfnQueryInterface = lsilogicR3DeviceQueryInterface;
5617 pDevice->IMediaPort.pfnQueryDeviceLocation = lsilogicR3QueryDeviceLocation;
5618 pDevice->IMediaExPort.pfnIoReqCompleteNotify = lsilogicR3IoReqCompleteNotify;
5619 pDevice->IMediaExPort.pfnIoReqCopyFromBuf = lsilogicR3IoReqCopyFromBuf;
5620 pDevice->IMediaExPort.pfnIoReqCopyToBuf = lsilogicR3IoReqCopyToBuf;
5621 pDevice->IMediaExPort.pfnIoReqQueryBuf = NULL;
5622 pDevice->IMediaExPort.pfnIoReqQueryDiscardRanges = NULL;
5623 pDevice->IMediaExPort.pfnIoReqStateChanged = lsilogicR3IoReqStateChanged;
5624 pDevice->IMediaExPort.pfnMediumEjected = lsilogicR3MediumEjected;
5625 pDevice->ILed.pfnQueryStatusLed = lsilogicR3DeviceQueryStatusLed;
5626
5627 char *pszName;
5628 if (RTStrAPrintf(&pszName, "Device%u", i) <= 0)
5629 AssertLogRelFailedReturn(VERR_NO_MEMORY);
5630
5631 /* Attach SCSI driver. */
5632 rc = PDMDevHlpDriverAttach(pDevIns, pDevice->iLUN, &pDevice->IBase, &pDevice->pDrvBase, pszName);
5633 if (RT_SUCCESS(rc))
5634 {
5635 /* Query the media interface. */
5636 pDevice->pDrvMedia = PDMIBASE_QUERY_INTERFACE(pDevice->pDrvBase, PDMIMEDIA);
5637 AssertMsgReturn(VALID_PTR(pDevice->pDrvMedia),
5638 ("LsiLogic configuration error: LUN#%d misses the basic media interface!\n", pDevice->iLUN),
5639 VERR_PDM_MISSING_INTERFACE);
5640
5641 /* Get the extended media interface. */
5642 pDevice->pDrvMediaEx = PDMIBASE_QUERY_INTERFACE(pDevice->pDrvBase, PDMIMEDIAEX);
5643 AssertMsgReturn(VALID_PTR(pDevice->pDrvMediaEx),
5644 ("LsiLogic configuration error: LUN#%d misses the extended media interface!\n", pDevice->iLUN),
5645 VERR_PDM_MISSING_INTERFACE);
5646
5647 rc = pDevice->pDrvMediaEx->pfnIoReqAllocSizeSet(pDevice->pDrvMediaEx, sizeof(LSILOGICREQ));
5648 if (RT_FAILURE(rc))
5649 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
5650 N_("LsiLogic configuration error: LUN#%u: Failed to set I/O request size!"),
5651 pDevice->iLUN);
5652 }
5653 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5654 {
5655 pDevice->pDrvBase = NULL;
5656 rc = VINF_SUCCESS;
5657 Log(("LsiLogic: no driver attached to device %s\n", pszName));
5658 }
5659 else
5660 {
5661 AssertLogRelMsgFailed(("LsiLogic: Failed to attach %s\n", pszName));
5662 return rc;
5663 }
5664 }
5665
5666 /*
5667 * Attach status driver (optional).
5668 */
5669 PPDMIBASE pBase;
5670 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThis->IBase, &pBase, "Status Port");
5671 if (RT_SUCCESS(rc))
5672 {
5673 pThis->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
5674 pThis->pMediaNotify = PDMIBASE_QUERY_INTERFACE(pBase, PDMIMEDIANOTIFY);
5675 }
5676 else if (rc != VERR_PDM_NO_ATTACHED_DRIVER)
5677 {
5678 AssertMsgFailed(("Failed to attach to status driver. rc=%Rrc\n", rc));
5679 return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic cannot attach to status driver"));
5680 }
5681
5682 /* Initialize the SCSI emulation for the BIOS. */
5683 rc = vboxscsiInitialize(&pThis->VBoxSCSI);
5684 AssertRC(rc);
5685
5686 /*
5687 * Register I/O port space in ISA region for BIOS access
5688 * if the controller is marked as bootable.
5689 */
5690 if (fBootable)
5691 {
5692 if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
5693 rc = PDMDevHlpIOPortRegister(pDevIns, LSILOGIC_BIOS_IO_PORT, 4, NULL,
5694 lsilogicR3IsaIOPortWrite, lsilogicR3IsaIOPortRead,
5695 lsilogicR3IsaIOPortWriteStr, lsilogicR3IsaIOPortReadStr,
5696 "LsiLogic BIOS");
5697 else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
5698 rc = PDMDevHlpIOPortRegister(pDevIns, LSILOGIC_SAS_BIOS_IO_PORT, 4, NULL,
5699 lsilogicR3IsaIOPortWrite, lsilogicR3IsaIOPortRead,
5700 lsilogicR3IsaIOPortWriteStr, lsilogicR3IsaIOPortReadStr,
5701 "LsiLogic SAS BIOS");
5702 else
5703 AssertMsgFailed(("Invalid controller type %d\n", pThis->enmCtrlType));
5704
5705 if (RT_FAILURE(rc))
5706 return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic cannot register legacy I/O handlers"));
5707 }
5708
5709 /* Register save state handlers. */
5710 rc = PDMDevHlpSSMRegisterEx(pDevIns, LSILOGIC_SAVED_STATE_VERSION, sizeof(*pThis), NULL,
5711 NULL, lsilogicR3LiveExec, NULL,
5712 NULL, lsilogicR3SaveExec, NULL,
5713 NULL, lsilogicR3LoadExec, lsilogicR3LoadDone);
5714 if (RT_FAILURE(rc))
5715 return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic cannot register save state handlers"));
5716
5717 pThis->enmWhoInit = LSILOGICWHOINIT_SYSTEM_BIOS;
5718
5719 /*
5720 * Register the info item.
5721 */
5722 char szTmp[128];
5723 RTStrPrintf(szTmp, sizeof(szTmp), "%s%u", pDevIns->pReg->szName, pDevIns->iInstance);
5724 PDMDevHlpDBGFInfoRegister(pDevIns, szTmp,
5725 pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI
5726 ? "LsiLogic SPI info."
5727 : "LsiLogic SAS info.", lsilogicR3Info);
5728
5729 /* Perform hard reset. */
5730 rc = lsilogicR3HardReset(pThis);
5731 AssertRC(rc);
5732
5733 return rc;
5734}
5735
5736/**
5737 * The device registration structure - SPI SCSI controller.
5738 */
5739const PDMDEVREG g_DeviceLsiLogicSCSI =
5740{
5741 /* u32Version */
5742 PDM_DEVREG_VERSION,
5743 /* szName */
5744 "lsilogicscsi",
5745 /* szRCMod */
5746 "VBoxDDRC.rc",
5747 /* szR0Mod */
5748 "VBoxDDR0.r0",
5749 /* pszDescription */
5750 "LSI Logic 53c1030 SCSI controller.\n",
5751 /* fFlags */
5752 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0 |
5753 PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION | PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION,
5754 /* fClass */
5755 PDM_DEVREG_CLASS_STORAGE,
5756 /* cMaxInstances */
5757 ~0U,
5758 /* cbInstance */
5759 sizeof(LSILOGICSCSI),
5760 /* pfnConstruct */
5761 lsilogicR3Construct,
5762 /* pfnDestruct */
5763 lsilogicR3Destruct,
5764 /* pfnRelocate */
5765 lsilogicR3Relocate,
5766 /* pfnMemSetup */
5767 NULL,
5768 /* pfnPowerOn */
5769 NULL,
5770 /* pfnReset */
5771 lsilogicR3Reset,
5772 /* pfnSuspend */
5773 lsilogicR3Suspend,
5774 /* pfnResume */
5775 lsilogicR3Resume,
5776 /* pfnAttach */
5777 lsilogicR3Attach,
5778 /* pfnDetach */
5779 lsilogicR3Detach,
5780 /* pfnQueryInterface. */
5781 NULL,
5782 /* pfnInitComplete */
5783 NULL,
5784 /* pfnPowerOff */
5785 lsilogicR3PowerOff,
5786 /* pfnSoftReset */
5787 NULL,
5788 /* u32VersionEnd */
5789 PDM_DEVREG_VERSION
5790};
5791
5792/**
5793 * The device registration structure - SAS controller.
5794 */
5795const PDMDEVREG g_DeviceLsiLogicSAS =
5796{
5797 /* u32Version */
5798 PDM_DEVREG_VERSION,
5799 /* szName */
5800 "lsilogicsas",
5801 /* szRCMod */
5802 "VBoxDDRC.rc",
5803 /* szR0Mod */
5804 "VBoxDDR0.r0",
5805 /* pszDescription */
5806 "LSI Logic SAS1068 controller.\n",
5807 /* fFlags */
5808 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0 |
5809 PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION | PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION |
5810 PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION,
5811 /* fClass */
5812 PDM_DEVREG_CLASS_STORAGE,
5813 /* cMaxInstances */
5814 ~0U,
5815 /* cbInstance */
5816 sizeof(LSILOGICSCSI),
5817 /* pfnConstruct */
5818 lsilogicR3Construct,
5819 /* pfnDestruct */
5820 lsilogicR3Destruct,
5821 /* pfnRelocate */
5822 lsilogicR3Relocate,
5823 /* pfnMemSetup */
5824 NULL,
5825 /* pfnPowerOn */
5826 NULL,
5827 /* pfnReset */
5828 lsilogicR3Reset,
5829 /* pfnSuspend */
5830 lsilogicR3Suspend,
5831 /* pfnResume */
5832 lsilogicR3Resume,
5833 /* pfnAttach */
5834 lsilogicR3Attach,
5835 /* pfnDetach */
5836 lsilogicR3Detach,
5837 /* pfnQueryInterface. */
5838 NULL,
5839 /* pfnInitComplete */
5840 NULL,
5841 /* pfnPowerOff */
5842 lsilogicR3PowerOff,
5843 /* pfnSoftReset */
5844 NULL,
5845 /* u32VersionEnd */
5846 PDM_DEVREG_VERSION
5847};
5848
5849#endif /* IN_RING3 */
5850#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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