VirtualBox

source: vbox/trunk/src/VBox/Devices/Storage/DevLsiLogicSCSI.cpp@ 64008

Last change on this file since 64008 was 63690, checked in by vboxsync, 8 years ago

PCI,Devices: Changed range size in FNPCIIOREGIONMAP from uint32_t to RTGCPHYS.

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  • Property svn:keywords set to Author Date Id Revision
File size: 238.7 KB
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1/* $Id: DevLsiLogicSCSI.cpp 63690 2016-09-02 12:15:07Z vboxsync $ */
2/** @file
3 * DevLsiLogicSCSI - LsiLogic LSI53c1030 SCSI controller.
4 */
5
6/*
7 * Copyright (C) 2006-2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_LSILOGICSCSI
23#include <VBox/vmm/pdmdev.h>
24#include <VBox/vmm/pdmstorageifs.h>
25#include <VBox/vmm/pdmqueue.h>
26#include <VBox/vmm/pdmthread.h>
27#include <VBox/vmm/pdmcritsect.h>
28#include <VBox/scsi.h>
29#include <VBox/sup.h>
30#include <iprt/assert.h>
31#include <iprt/asm.h>
32#include <iprt/string.h>
33#include <iprt/list.h>
34#ifdef IN_RING3
35# include <iprt/memcache.h>
36# include <iprt/mem.h>
37# include <iprt/param.h>
38# include <iprt/uuid.h>
39# include <iprt/time.h>
40#endif
41
42#include "DevLsiLogicSCSI.h"
43#include "VBoxSCSI.h"
44
45#include "VBoxDD.h"
46
47
48/*********************************************************************************************************************************
49* Defined Constants And Macros *
50*********************************************************************************************************************************/
51/** The current saved state version. */
52#define LSILOGIC_SAVED_STATE_VERSION 5
53/** The saved state version used by VirtualBox before the diagnostic
54 * memory access was implemented. */
55#define LSILOGIC_SAVED_STATE_VERSION_PRE_DIAG_MEM 4
56/** The saved state version used by VirtualBox before the doorbell status flag
57 * was changed from bool to a 32bit enum. */
58#define LSILOGIC_SAVED_STATE_VERSION_BOOL_DOORBELL 3
59/** The saved state version used by VirtualBox before SAS support was added. */
60#define LSILOGIC_SAVED_STATE_VERSION_PRE_SAS 2
61/** The saved state version used by VirtualBox 3.0 and earlier. It does not
62 * include the device config part. */
63#define LSILOGIC_SAVED_STATE_VERSION_VBOX_30 1
64
65/** Maximum number of entries in the release log. */
66#define MAX_REL_LOG_ERRORS 1024
67
68#define LSILOGIC_RTGCPHYS_FROM_U32(Hi, Lo) ( (RTGCPHYS)RT_MAKE_U64(Lo, Hi) )
69
70/** Upper number a buffer is freed if it was too big before. */
71#define LSILOGIC_MAX_ALLOC_TOO_MUCH 20
72
73/** Maximum size of the memory regions (prevents teh guest from DOSing the host by
74 * allocating loadds of memory). */
75#define LSILOGIC_MEMORY_REGIONS_MAX (_1M)
76
77
78/*********************************************************************************************************************************
79* Structures and Typedefs *
80*********************************************************************************************************************************/
81
82/**
83 * I/O buffer copy worker.
84 *
85 * @returns nothing.
86 * @param pDevIns Device instance data.
87 * @param GCPhysIoBuf Guest physical address of the I/O buffer.
88 * @param pvBuf R3 buffer pointer.
89 * @param cbCopy How much to copy.
90 */
91typedef DECLCALLBACK(void) FNLSILOGICIOBUFCOPY(PPDMDEVINS pDevIns, RTGCPHYS GCPhysIoBuf,
92 void *pvBuf, size_t cbCopy);
93/** Pointer to a I/O buffer copy worker. */
94typedef FNLSILOGICIOBUFCOPY *PFNLSILOGICIOBUFCOPY;
95
96/**
97 * Reply data.
98 */
99typedef struct LSILOGICSCSIREPLY
100{
101 /** Lower 32 bits of the reply address in memory. */
102 uint32_t u32HostMFALowAddress;
103 /** Full address of the reply in guest memory. */
104 RTGCPHYS GCPhysReplyAddress;
105 /** Size of the reply. */
106 uint32_t cbReply;
107 /** Different views to the reply depending on the request type. */
108 MptReplyUnion Reply;
109} LSILOGICSCSIREPLY;
110/** Pointer to reply data. */
111typedef LSILOGICSCSIREPLY *PLSILOGICSCSIREPLY;
112
113/**
114 * Memory region of the IOC.
115 */
116typedef struct LSILOGICMEMREGN
117{
118 /** List node. */
119 RTLISTNODE NodeList;
120 /** 32bit address the region starts to describe. */
121 uint32_t u32AddrStart;
122 /** 32bit address the region ends (inclusive). */
123 uint32_t u32AddrEnd;
124 /** Data for this region - variable. */
125 uint32_t au32Data[1];
126} LSILOGICMEMREGN;
127/** Pointer to a memory region. */
128typedef LSILOGICMEMREGN *PLSILOGICMEMREGN;
129
130/**
131 * State of a device attached to the buslogic host adapter.
132 *
133 * @implements PDMIBASE
134 * @implements PDMISCSIPORT
135 * @implements PDMILEDPORTS
136 */
137typedef struct LSILOGICDEVICE
138{
139 /** Pointer to the owning lsilogic device instance. - R3 pointer */
140 R3PTRTYPE(struct LSILOGICSCSI *) pLsiLogicR3;
141
142 /** LUN of the device. */
143 uint32_t iLUN;
144 /** Number of outstanding tasks on the port. */
145 volatile uint32_t cOutstandingRequests;
146
147#if HC_ARCH_BITS == 64
148 uint32_t Alignment0;
149#endif
150
151 /** Our base interface. */
152 PDMIBASE IBase;
153 /** SCSI port interface. */
154 PDMISCSIPORT ISCSIPort;
155 /** Led interface. */
156 PDMILEDPORTS ILed;
157 /** Pointer to the attached driver's base interface. */
158 R3PTRTYPE(PPDMIBASE) pDrvBase;
159 /** Pointer to the underlying SCSI connector interface. */
160 R3PTRTYPE(PPDMISCSICONNECTOR) pDrvSCSIConnector;
161 /** The status LED state for this device. */
162 PDMLED Led;
163
164} LSILOGICDEVICE;
165/** Pointer to a device state. */
166typedef LSILOGICDEVICE *PLSILOGICDEVICE;
167
168/** Pointer to a task state. */
169typedef struct LSILOGICREQ *PLSILOGICREQ;
170
171/**
172 * Device instance data for the emulated SCSI controller.
173 */
174typedef struct LSILOGICSCSI
175{
176 /** PCI device structure. */
177 PCIDEVICE PciDev;
178 /** Pointer to the device instance. - R3 ptr. */
179 PPDMDEVINSR3 pDevInsR3;
180 /** Pointer to the device instance. - R0 ptr. */
181 PPDMDEVINSR0 pDevInsR0;
182 /** Pointer to the device instance. - RC ptr. */
183 PPDMDEVINSRC pDevInsRC;
184
185 /** Flag whether the GC part of the device is enabled. */
186 bool fGCEnabled;
187 /** Flag whether the R0 part of the device is enabled. */
188 bool fR0Enabled;
189
190 /** The state the controller is currently in. */
191 LSILOGICSTATE enmState;
192 /** Who needs to init the driver to get into operational state. */
193 LSILOGICWHOINIT enmWhoInit;
194 /** Flag whether we are in doorbell function. */
195 LSILOGICDOORBELLSTATE enmDoorbellState;
196 /** Flag whether diagnostic access is enabled. */
197 bool fDiagnosticEnabled;
198 /** Flag whether a notification was send to R3. */
199 bool fNotificationSent;
200 /** Flag whether the guest enabled event notification from the IOC. */
201 bool fEventNotificationEnabled;
202 /** Flag whether the diagnostic address and RW registers are enabled. */
203 bool fDiagRegsEnabled;
204
205 /** Queue to send tasks to R3. - R3 ptr */
206 R3PTRTYPE(PPDMQUEUE) pNotificationQueueR3;
207 /** Queue to send tasks to R3. - R0 ptr */
208 R0PTRTYPE(PPDMQUEUE) pNotificationQueueR0;
209 /** Queue to send tasks to R3. - RC ptr */
210 RCPTRTYPE(PPDMQUEUE) pNotificationQueueRC;
211
212 /** Number of device states allocated. */
213 uint32_t cDeviceStates;
214
215 /** States for attached devices. */
216 R3PTRTYPE(PLSILOGICDEVICE) paDeviceStates;
217#if HC_ARCH_BITS == 32
218 RTR3PTR R3PtrPadding0;
219#endif
220
221 /** Interrupt mask. */
222 volatile uint32_t uInterruptMask;
223 /** Interrupt status register. */
224 volatile uint32_t uInterruptStatus;
225
226 /** Buffer for messages which are passed through the doorbell using the
227 * handshake method. */
228 uint32_t aMessage[sizeof(MptConfigurationRequest)]; /** @todo r=bird: Looks like 4 tims the required size? Please explain in comment if this correct... */
229 /** Actual position in the buffer. */
230 uint32_t iMessage;
231 /** Size of the message which is given in the doorbell message in dwords. */
232 uint32_t cMessage;
233
234 /** Reply buffer.
235 * @note 60 bytes */
236 MptReplyUnion ReplyBuffer;
237 /** Next entry to read. */
238 uint32_t uNextReplyEntryRead;
239 /** Size of the reply in the buffer in 16bit words. */
240 uint32_t cReplySize;
241
242 /** The fault code of the I/O controller if we are in the fault state. */
243 uint16_t u16IOCFaultCode;
244
245 /** I/O port address the device is mapped to. */
246 RTIOPORT IOPortBase;
247 /** MMIO address the device is mapped to. */
248 RTGCPHYS GCPhysMMIOBase;
249
250 /** Upper 32 bits of the message frame address to locate requests in guest memory. */
251 uint32_t u32HostMFAHighAddr;
252 /** Upper 32 bits of the sense buffer address. */
253 uint32_t u32SenseBufferHighAddr;
254 /** Maximum number of devices the driver reported he can handle. */
255 uint8_t cMaxDevices;
256 /** Maximum number of buses the driver reported he can handle. */
257 uint8_t cMaxBuses;
258 /** Current size of reply message frames in the guest. */
259 uint16_t cbReplyFrame;
260
261 /** Next key to write in the sequence to get access
262 * to diagnostic memory. */
263 uint32_t iDiagnosticAccess;
264
265 /** Number entries allocated for the reply queue. */
266 uint32_t cReplyQueueEntries;
267 /** Number entries allocated for the outstanding request queue. */
268 uint32_t cRequestQueueEntries;
269
270
271 /** Critical section protecting the reply post queue. */
272 PDMCRITSECT ReplyPostQueueCritSect;
273 /** Critical section protecting the reply free queue. */
274 PDMCRITSECT ReplyFreeQueueCritSect;
275
276 /** Pointer to the start of the reply free queue - R3. */
277 R3PTRTYPE(volatile uint32_t *) pReplyFreeQueueBaseR3;
278 /** Pointer to the start of the reply post queue - R3. */
279 R3PTRTYPE(volatile uint32_t *) pReplyPostQueueBaseR3;
280 /** Pointer to the start of the request queue - R3. */
281 R3PTRTYPE(volatile uint32_t *) pRequestQueueBaseR3;
282
283 /** Pointer to the start of the reply queue - R0. */
284 R0PTRTYPE(volatile uint32_t *) pReplyFreeQueueBaseR0;
285 /** Pointer to the start of the reply queue - R0. */
286 R0PTRTYPE(volatile uint32_t *) pReplyPostQueueBaseR0;
287 /** Pointer to the start of the request queue - R0. */
288 R0PTRTYPE(volatile uint32_t *) pRequestQueueBaseR0;
289
290 /** Pointer to the start of the reply queue - RC. */
291 RCPTRTYPE(volatile uint32_t *) pReplyFreeQueueBaseRC;
292 /** Pointer to the start of the reply queue - RC. */
293 RCPTRTYPE(volatile uint32_t *) pReplyPostQueueBaseRC;
294 /** Pointer to the start of the request queue - RC. */
295 RCPTRTYPE(volatile uint32_t *) pRequestQueueBaseRC;
296 /** End these RC pointers on a 64-bit boundrary. */
297 RTRCPTR RCPtrPadding1;
298
299 /** Next free entry in the reply queue the guest can write a address to. */
300 volatile uint32_t uReplyFreeQueueNextEntryFreeWrite;
301 /** Next valid entry the controller can read a valid address for reply frames from. */
302 volatile uint32_t uReplyFreeQueueNextAddressRead;
303
304 /** Next free entry in the reply queue the guest can write a address to. */
305 volatile uint32_t uReplyPostQueueNextEntryFreeWrite;
306 /** Next valid entry the controller can read a valid address for reply frames from. */
307 volatile uint32_t uReplyPostQueueNextAddressRead;
308
309 /** Next free entry the guest can write a address to a request frame to. */
310 volatile uint32_t uRequestQueueNextEntryFreeWrite;
311 /** Next valid entry the controller can read a valid address for request frames from. */
312 volatile uint32_t uRequestQueueNextAddressRead;
313
314 /** Emulated controller type */
315 LSILOGICCTRLTYPE enmCtrlType;
316 /** Handle counter */
317 uint16_t u16NextHandle;
318
319 /** Number of ports this controller has. */
320 uint8_t cPorts;
321
322 /** BIOS emulation. */
323 VBOXSCSI VBoxSCSI;
324
325 /** Cache for allocated tasks. */
326 R3PTRTYPE(RTMEMCACHE) hTaskCache;
327 /** Status LUN: The base interface. */
328 PDMIBASE IBase;
329 /** Status LUN: Leds interface. */
330 PDMILEDPORTS ILeds;
331 /** Status LUN: Partner of ILeds. */
332 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
333 /** Pointer to the configuration page area. */
334 R3PTRTYPE(PMptConfigurationPagesSupported) pConfigurationPages;
335
336 /** Indicates that PDMDevHlpAsyncNotificationCompleted should be called when
337 * a port is entering the idle state. */
338 bool volatile fSignalIdle;
339 /** Flag whether we have tasks which need to be processed again- */
340 bool volatile fRedo;
341 /** Flag whether the worker thread is sleeping. */
342 volatile bool fWrkThreadSleeping;
343 /** Flag whether a request from the BIOS is pending which the
344 * worker thread needs to process. */
345 volatile bool fBiosReqPending;
346#if HC_ARCH_BITS == 64
347 /** Alignment padding. */
348 bool afPadding2[4];
349#endif
350 /** List of tasks which can be redone. */
351 R3PTRTYPE(volatile PLSILOGICREQ) pTasksRedoHead;
352
353 /** Current address to read from or write to in the diagnostic memory region. */
354 uint32_t u32DiagMemAddr;
355 /** Current size of the memory regions. */
356 uint32_t cbMemRegns;
357
358#if HC_ARCH_BITS ==32
359 uint32_t u32Padding3;
360#endif
361
362 union
363 {
364 /** List of memory regions - PLSILOGICMEMREGN. */
365 RTLISTANCHOR ListMemRegns;
366 uint8_t u8Padding[2 * sizeof(RTUINTPTR)];
367 };
368
369 /** The support driver session handle. */
370 R3R0PTRTYPE(PSUPDRVSESSION) pSupDrvSession;
371 /** Worker thread. */
372 R3PTRTYPE(PPDMTHREAD) pThreadWrk;
373 /** The event semaphore the processing thread waits on. */
374 SUPSEMEVENT hEvtProcess;
375
376} LSILOGISCSI;
377/** Pointer to the device instance data of the LsiLogic emulation. */
378typedef LSILOGICSCSI *PLSILOGICSCSI;
379
380/**
381 * Task state object which holds all necessary data while
382 * processing the request from the guest.
383 */
384typedef struct LSILOGICREQ
385{
386 /** Next in the redo list. */
387 PLSILOGICREQ pRedoNext;
388 /** Target device. */
389 PLSILOGICDEVICE pTargetDevice;
390 /** The message request from the guest. */
391 MptRequestUnion GuestRequest;
392 /** Reply message if the request produces one. */
393 MptReplyUnion IOCReply;
394 /** SCSI request structure for the SCSI driver. */
395 PDMSCSIREQUEST PDMScsiRequest;
396 /** Address of the message request frame in guests memory.
397 * Used to read the S/G entries in the second step. */
398 RTGCPHYS GCPhysMessageFrameAddr;
399 /** Physical start address of the S/G list. */
400 RTGCPHYS GCPhysSgStart;
401 /** Chain offset */
402 uint32_t cChainOffset;
403 /** Segment describing the I/O buffer. */
404 RTSGSEG SegIoBuf;
405 /** Additional memory allocation for this task. */
406 void *pvAlloc;
407 /** Siize of the allocation. */
408 size_t cbAlloc;
409 /** Number of times we had too much memory allocated for the request. */
410 unsigned cAllocTooMuch;
411 /** Pointer to the sense buffer. */
412 uint8_t abSenseBuffer[18];
413 /** Flag whether the request was issued from the BIOS. */
414 bool fBIOS;
415} LSILOGICREQ;
416
417
418#ifndef VBOX_DEVICE_STRUCT_TESTCASE
419
420
421/*********************************************************************************************************************************
422* Internal Functions *
423*********************************************************************************************************************************/
424RT_C_DECLS_BEGIN
425#ifdef IN_RING3
426static void lsilogicR3InitializeConfigurationPages(PLSILOGICSCSI pThis);
427static void lsilogicR3ConfigurationPagesFree(PLSILOGICSCSI pThis);
428static int lsilogicR3ProcessConfigurationRequest(PLSILOGICSCSI pThis, PMptConfigurationRequest pConfigurationReq,
429 PMptConfigurationReply pReply);
430#endif
431RT_C_DECLS_END
432
433
434/*********************************************************************************************************************************
435* Global Variables *
436*********************************************************************************************************************************/
437/** Key sequence the guest has to write to enable access
438 * to diagnostic memory. */
439static const uint8_t g_lsilogicDiagnosticAccess[] = {0x04, 0x0b, 0x02, 0x07, 0x0d};
440
441/**
442 * Updates the status of the interrupt pin of the device.
443 *
444 * @returns nothing.
445 * @param pThis Pointer to the LsiLogic device state.
446 */
447static void lsilogicUpdateInterrupt(PLSILOGICSCSI pThis)
448{
449 uint32_t uIntSts;
450
451 LogFlowFunc(("Updating interrupts\n"));
452
453 /* Mask out doorbell status so that it does not affect interrupt updating. */
454 uIntSts = (ASMAtomicReadU32(&pThis->uInterruptStatus) & ~LSILOGIC_REG_HOST_INTR_STATUS_DOORBELL_STS);
455 /* Check maskable interrupts. */
456 uIntSts &= ~(ASMAtomicReadU32(&pThis->uInterruptMask) & ~LSILOGIC_REG_HOST_INTR_MASK_IRQ_ROUTING);
457
458 if (uIntSts)
459 {
460 LogFlowFunc(("Setting interrupt\n"));
461 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, 1);
462 }
463 else
464 {
465 LogFlowFunc(("Clearing interrupt\n"));
466 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, 0);
467 }
468}
469
470/**
471 * Sets a given interrupt status bit in the status register and
472 * updates the interrupt status.
473 *
474 * @returns nothing.
475 * @param pThis Pointer to the LsiLogic device state.
476 * @param uStatus The status bit to set.
477 */
478DECLINLINE(void) lsilogicSetInterrupt(PLSILOGICSCSI pThis, uint32_t uStatus)
479{
480 ASMAtomicOrU32(&pThis->uInterruptStatus, uStatus);
481 lsilogicUpdateInterrupt(pThis);
482}
483
484/**
485 * Clears a given interrupt status bit in the status register and
486 * updates the interrupt status.
487 *
488 * @returns nothing.
489 * @param pThis Pointer to the LsiLogic device state.
490 * @param uStatus The status bit to set.
491 */
492DECLINLINE(void) lsilogicClearInterrupt(PLSILOGICSCSI pThis, uint32_t uStatus)
493{
494 ASMAtomicAndU32(&pThis->uInterruptStatus, ~uStatus);
495 lsilogicUpdateInterrupt(pThis);
496}
497
498
499#ifdef IN_RING3
500/**
501 * Sets the I/O controller into fault state and sets the fault code.
502 *
503 * @returns nothing
504 * @param pThis Pointer to the LsiLogic device state.
505 * @param uIOCFaultCode Fault code to set.
506 */
507DECLINLINE(void) lsilogicSetIOCFaultCode(PLSILOGICSCSI pThis, uint16_t uIOCFaultCode)
508{
509 if (pThis->enmState != LSILOGICSTATE_FAULT)
510 {
511 LogFunc(("Setting I/O controller into FAULT state: uIOCFaultCode=%u\n", uIOCFaultCode));
512 pThis->enmState = LSILOGICSTATE_FAULT;
513 pThis->u16IOCFaultCode = uIOCFaultCode;
514 }
515 else
516 LogFunc(("We are already in FAULT state\n"));
517}
518#endif /* IN_RING3 */
519
520
521/**
522 * Returns the number of frames in the reply free queue.
523 *
524 * @returns Number of frames in the reply free queue.
525 * @param pThis Pointer to the LsiLogic device state.
526 */
527DECLINLINE(uint32_t) lsilogicReplyFreeQueueGetFrameCount(PLSILOGICSCSI pThis)
528{
529 uint32_t cReplyFrames = 0;
530
531 if (pThis->uReplyFreeQueueNextAddressRead <= pThis->uReplyFreeQueueNextEntryFreeWrite)
532 cReplyFrames = pThis->uReplyFreeQueueNextEntryFreeWrite - pThis->uReplyFreeQueueNextAddressRead;
533 else
534 cReplyFrames = pThis->cReplyQueueEntries - pThis->uReplyFreeQueueNextAddressRead + pThis->uReplyFreeQueueNextEntryFreeWrite;
535
536 return cReplyFrames;
537}
538
539#ifdef IN_RING3
540
541/**
542 * Returns the number of free entries in the reply post queue.
543 *
544 * @returns Number of frames in the reply free queue.
545 * @param pThis Pointer to the LsiLogic device state.
546 */
547DECLINLINE(uint32_t) lsilogicReplyPostQueueGetFrameCount(PLSILOGICSCSI pThis)
548{
549 uint32_t cReplyFrames = 0;
550
551 if (pThis->uReplyPostQueueNextAddressRead <= pThis->uReplyPostQueueNextEntryFreeWrite)
552 cReplyFrames = pThis->cReplyQueueEntries - pThis->uReplyPostQueueNextEntryFreeWrite + pThis->uReplyPostQueueNextAddressRead;
553 else
554 cReplyFrames = pThis->uReplyPostQueueNextEntryFreeWrite - pThis->uReplyPostQueueNextAddressRead;
555
556 return cReplyFrames;
557}
558
559
560/**
561 * Performs a hard reset on the controller.
562 *
563 * @returns VBox status code.
564 * @param pThis Pointer to the LsiLogic device state.
565 */
566static int lsilogicR3HardReset(PLSILOGICSCSI pThis)
567{
568 pThis->enmState = LSILOGICSTATE_RESET;
569 pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_NOT_IN_USE;
570
571 /* The interrupts are masked out. */
572 pThis->uInterruptMask |= LSILOGIC_REG_HOST_INTR_MASK_DOORBELL
573 | LSILOGIC_REG_HOST_INTR_MASK_REPLY;
574 /* Reset interrupt states. */
575 pThis->uInterruptStatus = 0;
576 lsilogicUpdateInterrupt(pThis);
577
578 /* Reset the queues. */
579 pThis->uReplyFreeQueueNextEntryFreeWrite = 0;
580 pThis->uReplyFreeQueueNextAddressRead = 0;
581 pThis->uReplyPostQueueNextEntryFreeWrite = 0;
582 pThis->uReplyPostQueueNextAddressRead = 0;
583 pThis->uRequestQueueNextEntryFreeWrite = 0;
584 pThis->uRequestQueueNextAddressRead = 0;
585
586 /* Disable diagnostic access. */
587 pThis->iDiagnosticAccess = 0;
588 pThis->fDiagnosticEnabled = false;
589 pThis->fDiagRegsEnabled = false;
590
591 /* Set default values. */
592 pThis->cMaxDevices = pThis->cDeviceStates;
593 pThis->cMaxBuses = 1;
594 pThis->cbReplyFrame = 128; /** @todo Figure out where it is needed. */
595 pThis->u16NextHandle = 1;
596 pThis->u32DiagMemAddr = 0;
597
598 lsilogicR3ConfigurationPagesFree(pThis);
599 lsilogicR3InitializeConfigurationPages(pThis);
600
601 /* Mark that we finished performing the reset. */
602 pThis->enmState = LSILOGICSTATE_READY;
603 return VINF_SUCCESS;
604}
605
606/**
607 * Frees the configuration pages if allocated.
608 *
609 * @returns nothing.
610 * @param pThis The LsiLogic controller instance
611 */
612static void lsilogicR3ConfigurationPagesFree(PLSILOGICSCSI pThis)
613{
614
615 if (pThis->pConfigurationPages)
616 {
617 /* Destroy device list if we emulate a SAS controller. */
618 if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
619 {
620 PMptConfigurationPagesSas pSasPages = &pThis->pConfigurationPages->u.SasPages;
621 PMptSASDevice pSASDeviceCurr = pSasPages->pSASDeviceHead;
622
623 while (pSASDeviceCurr)
624 {
625 PMptSASDevice pFree = pSASDeviceCurr;
626
627 pSASDeviceCurr = pSASDeviceCurr->pNext;
628 RTMemFree(pFree);
629 }
630 if (pSasPages->paPHYs)
631 RTMemFree(pSasPages->paPHYs);
632 if (pSasPages->pManufacturingPage7)
633 RTMemFree(pSasPages->pManufacturingPage7);
634 if (pSasPages->pSASIOUnitPage0)
635 RTMemFree(pSasPages->pSASIOUnitPage0);
636 if (pSasPages->pSASIOUnitPage1)
637 RTMemFree(pSasPages->pSASIOUnitPage1);
638 }
639
640 RTMemFree(pThis->pConfigurationPages);
641 }
642}
643
644/**
645 * Finishes a context reply.
646 *
647 * @returns nothing
648 * @param pThis Pointer to the LsiLogic device state.
649 * @param u32MessageContext The message context ID to post.
650 */
651static void lsilogicR3FinishContextReply(PLSILOGICSCSI pThis, uint32_t u32MessageContext)
652{
653 int rc;
654
655 LogFlowFunc(("pThis=%#p u32MessageContext=%#x\n", pThis, u32MessageContext));
656
657 AssertMsg(pThis->enmDoorbellState == LSILOGICDOORBELLSTATE_NOT_IN_USE, ("We are in a doorbell function\n"));
658
659 /* Write message context ID into reply post queue. */
660 rc = PDMCritSectEnter(&pThis->ReplyPostQueueCritSect, VINF_SUCCESS);
661 AssertRC(rc);
662
663 /* Check for a entry in the queue. */
664 if (!lsilogicReplyPostQueueGetFrameCount(pThis))
665 {
666 /* Set error code. */
667 lsilogicSetIOCFaultCode(pThis, LSILOGIC_IOCSTATUS_INSUFFICIENT_RESOURCES);
668 PDMCritSectLeave(&pThis->ReplyPostQueueCritSect);
669 return;
670 }
671
672 /* We have a context reply. */
673 ASMAtomicWriteU32(&pThis->CTX_SUFF(pReplyPostQueueBase)[pThis->uReplyPostQueueNextEntryFreeWrite], u32MessageContext);
674 ASMAtomicIncU32(&pThis->uReplyPostQueueNextEntryFreeWrite);
675 pThis->uReplyPostQueueNextEntryFreeWrite %= pThis->cReplyQueueEntries;
676
677 /* Set interrupt. */
678 lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_REPLY_INTR);
679
680 PDMCritSectLeave(&pThis->ReplyPostQueueCritSect);
681}
682
683
684/**
685 * Takes necessary steps to finish a reply frame.
686 *
687 * @returns nothing
688 * @param pThis Pointer to the LsiLogic device state.
689 * @param pReply Pointer to the reply message.
690 * @param fForceReplyFifo Flag whether the use of the reply post fifo is forced.
691 */
692static void lsilogicFinishAddressReply(PLSILOGICSCSI pThis, PMptReplyUnion pReply, bool fForceReplyFifo)
693{
694 /*
695 * If we are in a doorbell function we set the reply size now and
696 * set the system doorbell status interrupt to notify the guest that
697 * we are ready to send the reply.
698 */
699 if (pThis->enmDoorbellState != LSILOGICDOORBELLSTATE_NOT_IN_USE && !fForceReplyFifo)
700 {
701 /* Set size of the reply in 16bit words. The size in the reply is in 32bit dwords. */
702 pThis->cReplySize = pReply->Header.u8MessageLength * 2;
703 Log(("%s: cReplySize=%u\n", __FUNCTION__, pThis->cReplySize));
704 pThis->uNextReplyEntryRead = 0;
705 lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
706 }
707 else
708 {
709 /*
710 * The reply queues are only used if the request was fetched from the request queue.
711 * Requests from the request queue are always transferred to R3. So it is not possible
712 * that this case happens in R0 or GC.
713 */
714# ifdef IN_RING3
715 int rc;
716 /* Grab a free reply message from the queue. */
717 rc = PDMCritSectEnter(&pThis->ReplyFreeQueueCritSect, VINF_SUCCESS);
718 AssertRC(rc);
719
720 /* Check for a free reply frame. */
721 if (!lsilogicReplyFreeQueueGetFrameCount(pThis))
722 {
723 /* Set error code. */
724 lsilogicSetIOCFaultCode(pThis, LSILOGIC_IOCSTATUS_INSUFFICIENT_RESOURCES);
725 PDMCritSectLeave(&pThis->ReplyFreeQueueCritSect);
726 return;
727 }
728
729 uint32_t u32ReplyFrameAddressLow = pThis->CTX_SUFF(pReplyFreeQueueBase)[pThis->uReplyFreeQueueNextAddressRead];
730
731 pThis->uReplyFreeQueueNextAddressRead++;
732 pThis->uReplyFreeQueueNextAddressRead %= pThis->cReplyQueueEntries;
733
734 PDMCritSectLeave(&pThis->ReplyFreeQueueCritSect);
735
736 /* Build 64bit physical address. */
737 RTGCPHYS GCPhysReplyMessage = LSILOGIC_RTGCPHYS_FROM_U32(pThis->u32HostMFAHighAddr, u32ReplyFrameAddressLow);
738 size_t cbReplyCopied = (pThis->cbReplyFrame < sizeof(MptReplyUnion)) ? pThis->cbReplyFrame : sizeof(MptReplyUnion);
739
740 /* Write reply to guest memory. */
741 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhysReplyMessage, pReply, cbReplyCopied);
742
743 /* Write low 32bits of reply frame into post reply queue. */
744 rc = PDMCritSectEnter(&pThis->ReplyPostQueueCritSect, VINF_SUCCESS);
745 AssertRC(rc);
746
747 /* Check for a entry in the queue. */
748 if (!lsilogicReplyPostQueueGetFrameCount(pThis))
749 {
750 /* Set error code. */
751 lsilogicSetIOCFaultCode(pThis, LSILOGIC_IOCSTATUS_INSUFFICIENT_RESOURCES);
752 PDMCritSectLeave(&pThis->ReplyPostQueueCritSect);
753 return;
754 }
755
756 /* We have a address reply. Set the 31th bit to indicate that. */
757 ASMAtomicWriteU32(&pThis->CTX_SUFF(pReplyPostQueueBase)[pThis->uReplyPostQueueNextEntryFreeWrite],
758 RT_BIT(31) | (u32ReplyFrameAddressLow >> 1));
759 ASMAtomicIncU32(&pThis->uReplyPostQueueNextEntryFreeWrite);
760 pThis->uReplyPostQueueNextEntryFreeWrite %= pThis->cReplyQueueEntries;
761
762 if (fForceReplyFifo)
763 {
764 pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_NOT_IN_USE;
765 lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
766 }
767
768 /* Set interrupt. */
769 lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_REPLY_INTR);
770
771 PDMCritSectLeave(&pThis->ReplyPostQueueCritSect);
772# else
773 AssertMsgFailed(("This is not allowed to happen.\n"));
774# endif
775 }
776}
777
778
779/**
780 * Tries to find a memory region which covers the given address.
781 *
782 * @returns Pointer to memory region or NULL if not found.
783 * @param pThis Pointer to the LsiLogic device state.
784 * @param u32Addr The 32bit address to search for.
785 */
786static PLSILOGICMEMREGN lsilogicR3MemRegionFindByAddr(PLSILOGICSCSI pThis, uint32_t u32Addr)
787{
788 PLSILOGICMEMREGN pIt;
789 PLSILOGICMEMREGN pRegion = NULL;
790
791 RTListForEach(&pThis->ListMemRegns, pIt, LSILOGICMEMREGN, NodeList)
792 {
793 if ( u32Addr >= pIt->u32AddrStart
794 && u32Addr <= pIt->u32AddrEnd)
795 {
796 pRegion = pIt;
797 break;
798 }
799 }
800
801 return pRegion;
802}
803
804/**
805 * Frees all allocated memory regions.
806 *
807 * @returns nothing.
808 * @param pThis Pointer to the LsiLogic device state.
809 */
810static void lsilogicR3MemRegionsFree(PLSILOGICSCSI pThis)
811{
812 PLSILOGICMEMREGN pIt;
813 PLSILOGICMEMREGN pItNext;
814
815 RTListForEachSafe(&pThis->ListMemRegns, pIt, pItNext, LSILOGICMEMREGN, NodeList)
816 {
817 RTListNodeRemove(&pIt->NodeList);
818 RTMemFree(pIt);
819 }
820 pThis->cbMemRegns = 0;
821}
822
823/**
824 * Inserts a given memory region into the list.
825 *
826 * @returns nothing.
827 * @param pThis Pointer to the LsiLogic device state.
828 * @param pRegion The region to insert.
829 */
830static void lsilogicR3MemRegionInsert(PLSILOGICSCSI pThis, PLSILOGICMEMREGN pRegion)
831{
832 PLSILOGICMEMREGN pIt;
833 bool fInserted = false;
834
835 /* Insert at the right position. */
836 RTListForEach(&pThis->ListMemRegns, pIt, LSILOGICMEMREGN, NodeList)
837 {
838 if (pRegion->u32AddrEnd < pIt->u32AddrStart)
839 {
840 RTListNodeInsertBefore(&pIt->NodeList, &pRegion->NodeList);
841 fInserted = true;
842 break;
843 }
844 }
845 if (!fInserted)
846 RTListAppend(&pThis->ListMemRegns, &pRegion->NodeList);
847}
848
849/**
850 * Count number of memory regions.
851 *
852 * @returns Number of memory regions.
853 * @param pThis Pointer to the LsiLogic device state.
854 */
855static uint32_t lsilogicR3MemRegionsCount(PLSILOGICSCSI pThis)
856{
857 uint32_t cRegions = 0;
858 PLSILOGICMEMREGN pIt;
859
860 RTListForEach(&pThis->ListMemRegns, pIt, LSILOGICMEMREGN, NodeList)
861 {
862 cRegions++;
863 }
864
865 return cRegions;
866}
867
868/**
869 * Handles a write to the diagnostic data register.
870 *
871 * @returns nothing.
872 * @param pThis Pointer to the LsiLogic device state.
873 * @param u32Data Data to write.
874 */
875static void lsilogicR3DiagRegDataWrite(PLSILOGICSCSI pThis, uint32_t u32Data)
876{
877 PLSILOGICMEMREGN pRegion = lsilogicR3MemRegionFindByAddr(pThis, pThis->u32DiagMemAddr);
878
879 if (pRegion)
880 {
881 uint32_t offRegion = pThis->u32DiagMemAddr - pRegion->u32AddrStart;
882
883 AssertMsg( offRegion % 4 == 0
884 && pThis->u32DiagMemAddr <= pRegion->u32AddrEnd,
885 ("Region offset not on a word boundary or crosses memory region\n"));
886
887 offRegion /= 4;
888 pRegion->au32Data[offRegion] = u32Data;
889 }
890 else
891 {
892 PLSILOGICMEMREGN pIt;
893
894 pRegion = NULL;
895
896 /* Create new region, first check whether we can extend another region. */
897 RTListForEach(&pThis->ListMemRegns, pIt, LSILOGICMEMREGN, NodeList)
898 {
899 if (pThis->u32DiagMemAddr == pIt->u32AddrEnd + sizeof(uint32_t))
900 {
901 pRegion = pIt;
902 break;
903 }
904 }
905
906 if (pRegion)
907 {
908 /* Reallocate. */
909 RTListNodeRemove(&pRegion->NodeList);
910
911 uint32_t cRegionSizeOld = (pRegion->u32AddrEnd - pRegion->u32AddrStart) / 4 + 1;
912 uint32_t cRegionSizeNew = cRegionSizeOld + 512;
913
914 if (pThis->cbMemRegns + 512 * sizeof(uint32_t) < LSILOGIC_MEMORY_REGIONS_MAX)
915 {
916 PLSILOGICMEMREGN pRegionNew = (PLSILOGICMEMREGN)RTMemRealloc(pRegion, RT_OFFSETOF(LSILOGICMEMREGN, au32Data[cRegionSizeNew]));
917
918 if (pRegionNew)
919 {
920 pRegion = pRegionNew;
921 memset(&pRegion->au32Data[cRegionSizeOld], 0, 512 * sizeof(uint32_t));
922 pRegion->au32Data[cRegionSizeOld] = u32Data;
923 pRegion->u32AddrEnd = pRegion->u32AddrStart + (cRegionSizeNew - 1) * sizeof(uint32_t);
924 pThis->cbMemRegns += 512 * sizeof(uint32_t);
925 }
926 /* else: Silently fail, there is nothing we can do here and the guest might work nevertheless. */
927
928 lsilogicR3MemRegionInsert(pThis, pRegion);
929 }
930 }
931 else
932 {
933 if (pThis->cbMemRegns + 512 * sizeof(uint32_t) < LSILOGIC_MEMORY_REGIONS_MAX)
934 {
935 /* Create completely new. */
936 pRegion = (PLSILOGICMEMREGN)RTMemAllocZ(RT_OFFSETOF(LSILOGICMEMREGN, au32Data[512]));
937 if (pRegion)
938 {
939 pRegion->u32AddrStart = pThis->u32DiagMemAddr;
940 pRegion->u32AddrEnd = pRegion->u32AddrStart + (512 - 1) * sizeof(uint32_t);
941 pRegion->au32Data[0] = u32Data;
942 pThis->cbMemRegns += 512 * sizeof(uint32_t);
943
944 lsilogicR3MemRegionInsert(pThis, pRegion);
945 }
946 /* else: Silently fail, there is nothing we can do here and the guest might work nevertheless. */
947 }
948 }
949
950 }
951
952 /* Memory access is always 32bit big. */
953 pThis->u32DiagMemAddr += sizeof(uint32_t);
954}
955
956/**
957 * Handles a read from the diagnostic data register.
958 *
959 * @returns nothing.
960 * @param pThis Pointer to the LsiLogic device state.
961 * @param pu32Data Where to store the data.
962 */
963static void lsilogicR3DiagRegDataRead(PLSILOGICSCSI pThis, uint32_t *pu32Data)
964{
965 PLSILOGICMEMREGN pRegion = lsilogicR3MemRegionFindByAddr(pThis, pThis->u32DiagMemAddr);
966
967 if (pRegion)
968 {
969 uint32_t offRegion = pThis->u32DiagMemAddr - pRegion->u32AddrStart;
970
971 AssertMsg( offRegion % 4 == 0
972 && pThis->u32DiagMemAddr <= pRegion->u32AddrEnd,
973 ("Region offset not on a word boundary or crosses memory region\n"));
974
975 offRegion /= 4;
976 *pu32Data = pRegion->au32Data[offRegion];
977 }
978 else /* No region, default value 0. */
979 *pu32Data = 0;
980
981 /* Memory access is always 32bit big. */
982 pThis->u32DiagMemAddr += sizeof(uint32_t);
983}
984
985/**
986 * Handles a write to the diagnostic memory address register.
987 *
988 * @returns nothing.
989 * @param pThis Pointer to the LsiLogic device state.
990 * @param u32Addr Address to write.
991 */
992static void lsilogicR3DiagRegAddressWrite(PLSILOGICSCSI pThis, uint32_t u32Addr)
993{
994 pThis->u32DiagMemAddr = u32Addr & ~UINT32_C(0x3); /* 32bit alignment. */
995}
996
997/**
998 * Handles a read from the diagnostic memory address register.
999 *
1000 * @returns nothing.
1001 * @param pThis Pointer to the LsiLogic device state.
1002 * @param pu32Addr Where to store the current address.
1003 */
1004static void lsilogicR3DiagRegAddressRead(PLSILOGICSCSI pThis, uint32_t *pu32Addr)
1005{
1006 *pu32Addr = pThis->u32DiagMemAddr;
1007}
1008
1009/**
1010 * Processes a given Request from the guest
1011 *
1012 * @returns VBox status code.
1013 * @param pThis Pointer to the LsiLogic device state.
1014 * @param pMessageHdr Pointer to the message header of the request.
1015 * @param pReply Pointer to the reply.
1016 */
1017static int lsilogicR3ProcessMessageRequest(PLSILOGICSCSI pThis, PMptMessageHdr pMessageHdr, PMptReplyUnion pReply)
1018{
1019 int rc = VINF_SUCCESS;
1020 bool fForceReplyPostFifo = false;
1021
1022# ifdef LOG_ENABLED
1023 if (pMessageHdr->u8Function < RT_ELEMENTS(g_apszMPTFunctionNames))
1024 Log(("Message request function: %s\n", g_apszMPTFunctionNames[pMessageHdr->u8Function]));
1025 else
1026 Log(("Message request function: <unknown>\n"));
1027# endif
1028
1029 memset(pReply, 0, sizeof(MptReplyUnion));
1030
1031 switch (pMessageHdr->u8Function)
1032 {
1033 case MPT_MESSAGE_HDR_FUNCTION_SCSI_TASK_MGMT:
1034 {
1035 PMptSCSITaskManagementRequest pTaskMgmtReq = (PMptSCSITaskManagementRequest)pMessageHdr;
1036
1037 LogFlow(("u8TaskType=%u\n", pTaskMgmtReq->u8TaskType));
1038 LogFlow(("u32TaskMessageContext=%#x\n", pTaskMgmtReq->u32TaskMessageContext));
1039
1040 pReply->SCSITaskManagement.u8MessageLength = 6; /* 6 32bit dwords. */
1041 pReply->SCSITaskManagement.u8TaskType = pTaskMgmtReq->u8TaskType;
1042 pReply->SCSITaskManagement.u32TerminationCount = 0;
1043 fForceReplyPostFifo = true;
1044 break;
1045 }
1046 case MPT_MESSAGE_HDR_FUNCTION_IOC_INIT:
1047 {
1048 /*
1049 * This request sets the I/O controller to the
1050 * operational state.
1051 */
1052 PMptIOCInitRequest pIOCInitReq = (PMptIOCInitRequest)pMessageHdr;
1053
1054 /* Update configuration values. */
1055 pThis->enmWhoInit = (LSILOGICWHOINIT)pIOCInitReq->u8WhoInit;
1056 pThis->cbReplyFrame = pIOCInitReq->u16ReplyFrameSize;
1057 pThis->cMaxBuses = pIOCInitReq->u8MaxBuses;
1058 pThis->cMaxDevices = pIOCInitReq->u8MaxDevices;
1059 pThis->u32HostMFAHighAddr = pIOCInitReq->u32HostMfaHighAddr;
1060 pThis->u32SenseBufferHighAddr = pIOCInitReq->u32SenseBufferHighAddr;
1061
1062 if (pThis->enmState == LSILOGICSTATE_READY)
1063 {
1064 pThis->enmState = LSILOGICSTATE_OPERATIONAL;
1065 }
1066
1067 /* Return reply. */
1068 pReply->IOCInit.u8MessageLength = 5;
1069 pReply->IOCInit.u8WhoInit = pThis->enmWhoInit;
1070 pReply->IOCInit.u8MaxDevices = pThis->cMaxDevices;
1071 pReply->IOCInit.u8MaxBuses = pThis->cMaxBuses;
1072 break;
1073 }
1074 case MPT_MESSAGE_HDR_FUNCTION_IOC_FACTS:
1075 {
1076 pReply->IOCFacts.u8MessageLength = 15; /* 15 32bit dwords. */
1077
1078 if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
1079 {
1080 pReply->IOCFacts.u16MessageVersion = 0x0102; /* Version from the specification. */
1081 pReply->IOCFacts.u8NumberOfPorts = pThis->cPorts;
1082 }
1083 else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
1084 {
1085 pReply->IOCFacts.u16MessageVersion = 0x0105; /* Version from the specification. */
1086 pReply->IOCFacts.u8NumberOfPorts = pThis->cPorts;
1087 }
1088 else
1089 AssertMsgFailed(("Invalid controller type %d\n", pThis->enmCtrlType));
1090
1091 pReply->IOCFacts.u8IOCNumber = 0; /* PCI function number. */
1092 pReply->IOCFacts.u16IOCExceptions = 0;
1093 pReply->IOCFacts.u8MaxChainDepth = LSILOGICSCSI_MAXIMUM_CHAIN_DEPTH;
1094 pReply->IOCFacts.u8WhoInit = pThis->enmWhoInit;
1095 pReply->IOCFacts.u8BlockSize = 12; /* Block size in 32bit dwords. This is the largest request we can get (SCSI I/O). */
1096 pReply->IOCFacts.u8Flags = 0; /* Bit 0 is set if the guest must upload the FW prior to using the controller. Obviously not needed here. */
1097 pReply->IOCFacts.u16ReplyQueueDepth = pThis->cReplyQueueEntries - 1; /* One entry is always free. */
1098 pReply->IOCFacts.u16RequestFrameSize = 128; /** @todo Figure out where it is needed. */
1099 pReply->IOCFacts.u32CurrentHostMFAHighAddr = pThis->u32HostMFAHighAddr;
1100 pReply->IOCFacts.u16GlobalCredits = pThis->cRequestQueueEntries - 1; /* One entry is always free. */
1101
1102 pReply->IOCFacts.u8EventState = 0; /* Event notifications not enabled. */
1103 pReply->IOCFacts.u32CurrentSenseBufferHighAddr = pThis->u32SenseBufferHighAddr;
1104 pReply->IOCFacts.u16CurReplyFrameSize = pThis->cbReplyFrame;
1105 pReply->IOCFacts.u8MaxDevices = pThis->cMaxDevices;
1106 pReply->IOCFacts.u8MaxBuses = pThis->cMaxBuses;
1107
1108 /* Check for a valid firmware image in the IOC memory which was downlaoded by tzhe guest earlier. */
1109 PLSILOGICMEMREGN pRegion = lsilogicR3MemRegionFindByAddr(pThis, LSILOGIC_FWIMGHDR_LOAD_ADDRESS);
1110
1111 if (pRegion)
1112 {
1113 uint32_t offImgHdr = (LSILOGIC_FWIMGHDR_LOAD_ADDRESS - pRegion->u32AddrStart) / 4;
1114 PFwImageHdr pFwImgHdr = (PFwImageHdr)&pRegion->au32Data[offImgHdr];
1115
1116 /* Check for the signature. */
1117 /** @todo Checksum validation. */
1118 if ( pFwImgHdr->u32Signature1 == LSILOGIC_FWIMGHDR_SIGNATURE1
1119 && pFwImgHdr->u32Signature2 == LSILOGIC_FWIMGHDR_SIGNATURE2
1120 && pFwImgHdr->u32Signature3 == LSILOGIC_FWIMGHDR_SIGNATURE3)
1121 {
1122 LogFlowFunc(("IOC Facts: Found valid firmware image header in memory, using version (%#x), size (%d) and product ID (%#x) from there\n",
1123 pFwImgHdr->u32FwVersion, pFwImgHdr->u32ImageSize, pFwImgHdr->u16ProductId));
1124
1125 pReply->IOCFacts.u16ProductID = pFwImgHdr->u16ProductId;
1126 pReply->IOCFacts.u32FwImageSize = pFwImgHdr->u32ImageSize;
1127 pReply->IOCFacts.u32FWVersion = pFwImgHdr->u32FwVersion;
1128 }
1129 }
1130 else
1131 {
1132 pReply->IOCFacts.u16ProductID = 0xcafe; /* Our own product ID :) */
1133 pReply->IOCFacts.u32FwImageSize = 0; /* No image needed. */
1134 pReply->IOCFacts.u32FWVersion = 0;
1135 }
1136 break;
1137 }
1138 case MPT_MESSAGE_HDR_FUNCTION_PORT_FACTS:
1139 {
1140 PMptPortFactsRequest pPortFactsReq = (PMptPortFactsRequest)pMessageHdr;
1141
1142 pReply->PortFacts.u8MessageLength = 10;
1143 pReply->PortFacts.u8PortNumber = pPortFactsReq->u8PortNumber;
1144
1145 if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
1146 {
1147 /* This controller only supports one bus with bus number 0. */
1148 if (pPortFactsReq->u8PortNumber >= pThis->cPorts)
1149 {
1150 pReply->PortFacts.u8PortType = 0; /* Not existant. */
1151 }
1152 else
1153 {
1154 pReply->PortFacts.u8PortType = 0x01; /* SCSI Port. */
1155 pReply->PortFacts.u16MaxDevices = LSILOGICSCSI_PCI_SPI_DEVICES_PER_BUS_MAX;
1156 pReply->PortFacts.u16ProtocolFlags = RT_BIT(3) | RT_BIT(0); /* SCSI initiator and LUN supported. */
1157 pReply->PortFacts.u16PortSCSIID = 7; /* Default */
1158 pReply->PortFacts.u16MaxPersistentIDs = 0;
1159 pReply->PortFacts.u16MaxPostedCmdBuffers = 0; /* Only applies for target mode which we dont support. */
1160 pReply->PortFacts.u16MaxLANBuckets = 0; /* Only for the LAN controller. */
1161 }
1162 }
1163 else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
1164 {
1165 if (pPortFactsReq->u8PortNumber >= pThis->cPorts)
1166 {
1167 pReply->PortFacts.u8PortType = 0; /* Not existant. */
1168 }
1169 else
1170 {
1171 pReply->PortFacts.u8PortType = 0x30; /* SAS Port. */
1172 pReply->PortFacts.u16MaxDevices = pThis->cPorts;
1173 pReply->PortFacts.u16ProtocolFlags = RT_BIT(3) | RT_BIT(0); /* SCSI initiator and LUN supported. */
1174 pReply->PortFacts.u16PortSCSIID = pThis->cPorts;
1175 pReply->PortFacts.u16MaxPersistentIDs = 0;
1176 pReply->PortFacts.u16MaxPostedCmdBuffers = 0; /* Only applies for target mode which we dont support. */
1177 pReply->PortFacts.u16MaxLANBuckets = 0; /* Only for the LAN controller. */
1178 }
1179 }
1180 else
1181 AssertMsgFailed(("Invalid controller type %d\n", pThis->enmCtrlType));
1182 break;
1183 }
1184 case MPT_MESSAGE_HDR_FUNCTION_PORT_ENABLE:
1185 {
1186 /*
1187 * The port enable request notifies the IOC to make the port available and perform
1188 * appropriate discovery on the associated link.
1189 */
1190 PMptPortEnableRequest pPortEnableReq = (PMptPortEnableRequest)pMessageHdr;
1191
1192 pReply->PortEnable.u8MessageLength = 5;
1193 pReply->PortEnable.u8PortNumber = pPortEnableReq->u8PortNumber;
1194 break;
1195 }
1196 case MPT_MESSAGE_HDR_FUNCTION_EVENT_NOTIFICATION:
1197 {
1198 PMptEventNotificationRequest pEventNotificationReq = (PMptEventNotificationRequest)pMessageHdr;
1199
1200 if (pEventNotificationReq->u8Switch)
1201 pThis->fEventNotificationEnabled = true;
1202 else
1203 pThis->fEventNotificationEnabled = false;
1204
1205 pReply->EventNotification.u16EventDataLength = 1; /* 1 32bit D-Word. */
1206 pReply->EventNotification.u8MessageLength = 8;
1207 pReply->EventNotification.u8MessageFlags = (1 << 7);
1208 pReply->EventNotification.u8AckRequired = 0;
1209 pReply->EventNotification.u32Event = MPT_EVENT_EVENT_CHANGE;
1210 pReply->EventNotification.u32EventContext = 0;
1211 pReply->EventNotification.u32EventData = pThis->fEventNotificationEnabled ? 1 : 0;
1212
1213 break;
1214 }
1215 case MPT_MESSAGE_HDR_FUNCTION_EVENT_ACK:
1216 {
1217 AssertMsgFailed(("todo"));
1218 break;
1219 }
1220 case MPT_MESSAGE_HDR_FUNCTION_CONFIG:
1221 {
1222 PMptConfigurationRequest pConfigurationReq = (PMptConfigurationRequest)pMessageHdr;
1223
1224 rc = lsilogicR3ProcessConfigurationRequest(pThis, pConfigurationReq, &pReply->Configuration);
1225 AssertRC(rc);
1226 break;
1227 }
1228 case MPT_MESSAGE_HDR_FUNCTION_FW_UPLOAD:
1229 {
1230 PMptFWUploadRequest pFWUploadReq = (PMptFWUploadRequest)pMessageHdr;
1231
1232 pReply->FWUpload.u8ImageType = pFWUploadReq->u8ImageType;
1233 pReply->FWUpload.u8MessageLength = 6;
1234 pReply->FWUpload.u32ActualImageSize = 0;
1235 break;
1236 }
1237 case MPT_MESSAGE_HDR_FUNCTION_FW_DOWNLOAD:
1238 {
1239 //PMptFWDownloadRequest pFWDownloadReq = (PMptFWDownloadRequest)pMessageHdr;
1240
1241 pReply->FWDownload.u8MessageLength = 5;
1242 LogFlowFunc(("FW Download request issued\n"));
1243 break;
1244 }
1245 case MPT_MESSAGE_HDR_FUNCTION_SCSI_IO_REQUEST: /* Should be handled already. */
1246 default:
1247 AssertMsgFailed(("Invalid request function %#x\n", pMessageHdr->u8Function));
1248 }
1249
1250 /* Copy common bits from request message frame to reply. */
1251 pReply->Header.u8Function = pMessageHdr->u8Function;
1252 pReply->Header.u32MessageContext = pMessageHdr->u32MessageContext;
1253
1254 lsilogicFinishAddressReply(pThis, pReply, fForceReplyPostFifo);
1255 return rc;
1256}
1257
1258#endif /* IN_RING3 */
1259
1260/**
1261 * Writes a value to a register at a given offset.
1262 *
1263 * @returns VBox status code.
1264 * @param pThis Pointer to the LsiLogic device state.
1265 * @param offReg Offset of the register to write.
1266 * @param u32 The value being written.
1267 */
1268static int lsilogicRegisterWrite(PLSILOGICSCSI pThis, uint32_t offReg, uint32_t u32)
1269{
1270 LogFlowFunc(("pThis=%#p offReg=%#x u32=%#x\n", pThis, offReg, u32));
1271 switch (offReg)
1272 {
1273 case LSILOGIC_REG_REPLY_QUEUE:
1274 {
1275 /* Add the entry to the reply free queue. */
1276 ASMAtomicWriteU32(&pThis->CTX_SUFF(pReplyFreeQueueBase)[pThis->uReplyFreeQueueNextEntryFreeWrite], u32);
1277 pThis->uReplyFreeQueueNextEntryFreeWrite++;
1278 pThis->uReplyFreeQueueNextEntryFreeWrite %= pThis->cReplyQueueEntries;
1279 break;
1280 }
1281 case LSILOGIC_REG_REQUEST_QUEUE:
1282 {
1283 uint32_t uNextWrite = ASMAtomicReadU32(&pThis->uRequestQueueNextEntryFreeWrite);
1284
1285 ASMAtomicWriteU32(&pThis->CTX_SUFF(pRequestQueueBase)[uNextWrite], u32);
1286
1287 /*
1288 * Don't update the value in place. It can happen that we get preempted
1289 * after the increment but before the modulo.
1290 * Another EMT will read the wrong value when processing the queues
1291 * and hang in an endless loop creating thousands of requests.
1292 */
1293 uNextWrite++;
1294 uNextWrite %= pThis->cRequestQueueEntries;
1295 ASMAtomicWriteU32(&pThis->uRequestQueueNextEntryFreeWrite, uNextWrite);
1296
1297 /* Send notification to R3 if there is not one sent already. Do this
1298 * only if the worker thread is not sleeping or might go sleeping. */
1299 if (!ASMAtomicXchgBool(&pThis->fNotificationSent, true))
1300 {
1301 if (ASMAtomicReadBool(&pThis->fWrkThreadSleeping))
1302 {
1303#ifdef IN_RC
1304 PPDMQUEUEITEMCORE pNotificationItem = PDMQueueAlloc(pThis->CTX_SUFF(pNotificationQueue));
1305 AssertPtr(pNotificationItem);
1306 PDMQueueInsert(pThis->CTX_SUFF(pNotificationQueue), pNotificationItem);
1307#else
1308 LogFlowFunc(("Signal event semaphore\n"));
1309 int rc = SUPSemEventSignal(pThis->pSupDrvSession, pThis->hEvtProcess);
1310 AssertRC(rc);
1311#endif
1312 }
1313 }
1314 break;
1315 }
1316 case LSILOGIC_REG_DOORBELL:
1317 {
1318 /*
1319 * When the guest writes to this register a real device would set the
1320 * doorbell status bit in the interrupt status register to indicate that the IOP
1321 * has still to process the message.
1322 * The guest needs to wait with posting new messages here until the bit is cleared.
1323 * Because the guest is not continuing execution while we are here we can skip this.
1324 */
1325 if (pThis->enmDoorbellState == LSILOGICDOORBELLSTATE_NOT_IN_USE)
1326 {
1327 uint32_t uFunction = LSILOGIC_REG_DOORBELL_GET_FUNCTION(u32);
1328
1329 switch (uFunction)
1330 {
1331 case LSILOGIC_DOORBELL_FUNCTION_IO_UNIT_RESET:
1332 case LSILOGIC_DOORBELL_FUNCTION_IOC_MSG_UNIT_RESET:
1333 {
1334 /*
1335 * The I/O unit reset does much more on real hardware like
1336 * reloading the firmware, nothing we need to do here,
1337 * so this is like the IOC message unit reset.
1338 */
1339 pThis->enmState = LSILOGICSTATE_RESET;
1340
1341 /* Reset interrupt status. */
1342 pThis->uInterruptStatus = 0;
1343 lsilogicUpdateInterrupt(pThis);
1344
1345 /* Reset the queues. */
1346 pThis->uReplyFreeQueueNextEntryFreeWrite = 0;
1347 pThis->uReplyFreeQueueNextAddressRead = 0;
1348 pThis->uReplyPostQueueNextEntryFreeWrite = 0;
1349 pThis->uReplyPostQueueNextAddressRead = 0;
1350 pThis->uRequestQueueNextEntryFreeWrite = 0;
1351 pThis->uRequestQueueNextAddressRead = 0;
1352
1353 /* Only the IOC message unit reset transisionts to the ready state. */
1354 if (uFunction == LSILOGIC_DOORBELL_FUNCTION_IOC_MSG_UNIT_RESET)
1355 pThis->enmState = LSILOGICSTATE_READY;
1356 break;
1357 }
1358 case LSILOGIC_DOORBELL_FUNCTION_HANDSHAKE:
1359 {
1360 pThis->cMessage = LSILOGIC_REG_DOORBELL_GET_SIZE(u32);
1361 pThis->iMessage = 0;
1362 AssertMsg(pThis->cMessage <= RT_ELEMENTS(pThis->aMessage),
1363 ("Message doesn't fit into the buffer, cMessage=%u", pThis->cMessage));
1364 pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_FN_HANDSHAKE;
1365 /* Update the interrupt status to notify the guest that a doorbell function was started. */
1366 lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1367 break;
1368 }
1369 case LSILOGIC_DOORBELL_FUNCTION_REPLY_FRAME_REMOVAL:
1370 {
1371 pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_RFR_FRAME_COUNT_LOW;
1372 /* Update the interrupt status to notify the guest that a doorbell function was started. */
1373 lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1374 break;
1375 }
1376 default:
1377 AssertMsgFailed(("Unknown function %u to perform\n", uFunction));
1378 }
1379 }
1380 else if (pThis->enmDoorbellState == LSILOGICDOORBELLSTATE_FN_HANDSHAKE)
1381 {
1382 /*
1383 * We are already performing a doorbell function.
1384 * Get the remaining parameters.
1385 */
1386 AssertMsg(pThis->iMessage < RT_ELEMENTS(pThis->aMessage), ("Message is too big to fit into the buffer\n"));
1387 /*
1388 * If the last byte of the message is written, force a switch to R3 because some requests might force
1389 * a reply through the FIFO which cannot be handled in GC or R0.
1390 */
1391#ifndef IN_RING3
1392 if (pThis->iMessage == pThis->cMessage - 1)
1393 return VINF_IOM_R3_MMIO_WRITE;
1394#endif
1395 pThis->aMessage[pThis->iMessage++] = u32;
1396#ifdef IN_RING3
1397 if (pThis->iMessage == pThis->cMessage)
1398 {
1399 int rc = lsilogicR3ProcessMessageRequest(pThis, (PMptMessageHdr)pThis->aMessage, &pThis->ReplyBuffer);
1400 AssertRC(rc);
1401 }
1402#endif
1403 }
1404 break;
1405 }
1406 case LSILOGIC_REG_HOST_INTR_STATUS:
1407 {
1408 /*
1409 * Clear the bits the guest wants except the system doorbell interrupt and the IO controller
1410 * status bit.
1411 * The former bit is always cleared no matter what the guest writes to the register and
1412 * the latter one is read only.
1413 */
1414 ASMAtomicAndU32(&pThis->uInterruptStatus, ~LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1415
1416 /*
1417 * Check if there is still a doorbell function in progress. Set the
1418 * system doorbell interrupt bit again if it is.
1419 * We do not use lsilogicSetInterrupt here because the interrupt status
1420 * is updated afterwards anyway.
1421 */
1422 if ( (pThis->enmDoorbellState == LSILOGICDOORBELLSTATE_FN_HANDSHAKE)
1423 && (pThis->cMessage == pThis->iMessage))
1424 {
1425 if (pThis->uNextReplyEntryRead == pThis->cReplySize)
1426 {
1427 /* Reply finished. Reset doorbell in progress status. */
1428 Log(("%s: Doorbell function finished\n", __FUNCTION__));
1429 pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_NOT_IN_USE;
1430 }
1431 ASMAtomicOrU32(&pThis->uInterruptStatus, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1432 }
1433 else if ( pThis->enmDoorbellState != LSILOGICDOORBELLSTATE_NOT_IN_USE
1434 && pThis->enmDoorbellState != LSILOGICDOORBELLSTATE_FN_HANDSHAKE)
1435 {
1436 /* Reply frame removal, check whether the reply free queue is empty. */
1437 if ( pThis->uReplyFreeQueueNextAddressRead == pThis->uReplyFreeQueueNextEntryFreeWrite
1438 && pThis->enmDoorbellState == LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_LOW)
1439 pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_NOT_IN_USE;
1440 ASMAtomicOrU32(&pThis->uInterruptStatus, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1441 }
1442
1443 lsilogicUpdateInterrupt(pThis);
1444 break;
1445 }
1446 case LSILOGIC_REG_HOST_INTR_MASK:
1447 {
1448 ASMAtomicWriteU32(&pThis->uInterruptMask, u32 & LSILOGIC_REG_HOST_INTR_MASK_W_MASK);
1449 lsilogicUpdateInterrupt(pThis);
1450 break;
1451 }
1452 case LSILOGIC_REG_WRITE_SEQUENCE:
1453 {
1454 if (pThis->fDiagnosticEnabled)
1455 {
1456 /* Any value will cause a reset and disabling access. */
1457 pThis->fDiagnosticEnabled = false;
1458 pThis->iDiagnosticAccess = 0;
1459 pThis->fDiagRegsEnabled = false;
1460 }
1461 else if ((u32 & 0xf) == g_lsilogicDiagnosticAccess[pThis->iDiagnosticAccess])
1462 {
1463 pThis->iDiagnosticAccess++;
1464 if (pThis->iDiagnosticAccess == RT_ELEMENTS(g_lsilogicDiagnosticAccess))
1465 {
1466 /*
1467 * Key sequence successfully written. Enable access to diagnostic
1468 * memory and register.
1469 */
1470 pThis->fDiagnosticEnabled = true;
1471 }
1472 }
1473 else
1474 {
1475 /* Wrong value written - reset to beginning. */
1476 pThis->iDiagnosticAccess = 0;
1477 }
1478 break;
1479 }
1480 case LSILOGIC_REG_HOST_DIAGNOSTIC:
1481 {
1482 if (pThis->fDiagnosticEnabled)
1483 {
1484#ifndef IN_RING3
1485 return VINF_IOM_R3_MMIO_WRITE;
1486#else
1487 if (u32 & LSILOGIC_REG_HOST_DIAGNOSTIC_RESET_ADAPTER)
1488 lsilogicR3HardReset(pThis);
1489 else if (u32 & LSILOGIC_REG_HOST_DIAGNOSTIC_DIAG_RW_ENABLE)
1490 pThis->fDiagRegsEnabled = true;
1491#endif
1492 }
1493 break;
1494 }
1495 case LSILOGIC_REG_DIAG_RW_DATA:
1496 {
1497 if (pThis->fDiagRegsEnabled)
1498 {
1499#ifndef IN_RING3
1500 return VINF_IOM_R3_MMIO_WRITE;
1501#else
1502 lsilogicR3DiagRegDataWrite(pThis, u32);
1503#endif
1504 }
1505 break;
1506 }
1507 case LSILOGIC_REG_DIAG_RW_ADDRESS:
1508 {
1509 if (pThis->fDiagRegsEnabled)
1510 {
1511#ifndef IN_RING3
1512 return VINF_IOM_R3_MMIO_WRITE;
1513#else
1514 lsilogicR3DiagRegAddressWrite(pThis, u32);
1515#endif
1516 }
1517 break;
1518 }
1519 default: /* Ignore. */
1520 {
1521 break;
1522 }
1523 }
1524 return VINF_SUCCESS;
1525}
1526
1527/**
1528 * Reads the content of a register at a given offset.
1529 *
1530 * @returns VBox status code.
1531 * @param pThis Pointer to the LsiLogic device state.
1532 * @param offReg Offset of the register to read.
1533 * @param pu32 Where to store the content of the register.
1534 */
1535static int lsilogicRegisterRead(PLSILOGICSCSI pThis, uint32_t offReg, uint32_t *pu32)
1536{
1537 int rc = VINF_SUCCESS;
1538 uint32_t u32 = 0;
1539 Assert(!(offReg & 3));
1540
1541 /* Align to a 4 byte offset. */
1542 switch (offReg)
1543 {
1544 case LSILOGIC_REG_REPLY_QUEUE:
1545 {
1546 rc = PDMCritSectEnter(&pThis->ReplyPostQueueCritSect, VINF_IOM_R3_MMIO_READ);
1547 if (rc != VINF_SUCCESS)
1548 break;
1549
1550 uint32_t idxReplyPostQueueWrite = ASMAtomicUoReadU32(&pThis->uReplyPostQueueNextEntryFreeWrite);
1551 uint32_t idxReplyPostQueueRead = ASMAtomicUoReadU32(&pThis->uReplyPostQueueNextAddressRead);
1552
1553 if (idxReplyPostQueueWrite != idxReplyPostQueueRead)
1554 {
1555 u32 = pThis->CTX_SUFF(pReplyPostQueueBase)[idxReplyPostQueueRead];
1556 idxReplyPostQueueRead++;
1557 idxReplyPostQueueRead %= pThis->cReplyQueueEntries;
1558 ASMAtomicWriteU32(&pThis->uReplyPostQueueNextAddressRead, idxReplyPostQueueRead);
1559 }
1560 else
1561 {
1562 /* The reply post queue is empty. Reset interrupt. */
1563 u32 = UINT32_C(0xffffffff);
1564 lsilogicClearInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_REPLY_INTR);
1565 }
1566 PDMCritSectLeave(&pThis->ReplyPostQueueCritSect);
1567
1568 Log(("%s: Returning address %#x\n", __FUNCTION__, u32));
1569 break;
1570 }
1571 case LSILOGIC_REG_DOORBELL:
1572 {
1573 u32 = LSILOGIC_REG_DOORBELL_SET_STATE(pThis->enmState);
1574 u32 |= LSILOGIC_REG_DOORBELL_SET_USED(pThis->enmDoorbellState);
1575 u32 |= LSILOGIC_REG_DOORBELL_SET_WHOINIT(pThis->enmWhoInit);
1576 /*
1577 * If there is a doorbell function in progress we pass the return value
1578 * instead of the status code. We transfer 16bit of the reply
1579 * during one read.
1580 */
1581 switch (pThis->enmDoorbellState)
1582 {
1583 case LSILOGICDOORBELLSTATE_NOT_IN_USE:
1584 /* We return the status code of the I/O controller. */
1585 u32 |= pThis->u16IOCFaultCode;
1586 break;
1587 case LSILOGICDOORBELLSTATE_FN_HANDSHAKE:
1588 /* Return next 16bit value. */
1589 u32 |= pThis->ReplyBuffer.au16Reply[pThis->uNextReplyEntryRead++];
1590 lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1591 break;
1592 case LSILOGICDOORBELLSTATE_RFR_FRAME_COUNT_LOW:
1593 {
1594 uint32_t cReplyFrames = lsilogicReplyFreeQueueGetFrameCount(pThis);
1595
1596 u32 |= cReplyFrames & UINT32_C(0xffff);
1597 pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_RFR_FRAME_COUNT_HIGH;
1598 lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1599 break;
1600 }
1601 case LSILOGICDOORBELLSTATE_RFR_FRAME_COUNT_HIGH:
1602 {
1603 uint32_t cReplyFrames = lsilogicReplyFreeQueueGetFrameCount(pThis);
1604
1605 u32 |= cReplyFrames >> 16;
1606 pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_LOW;
1607 lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1608 break;
1609 }
1610 case LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_LOW:
1611 if (pThis->uReplyFreeQueueNextEntryFreeWrite != pThis->uReplyFreeQueueNextAddressRead)
1612 {
1613 u32 |= pThis->CTX_SUFF(pReplyFreeQueueBase)[pThis->uReplyFreeQueueNextAddressRead] & UINT32_C(0xffff);
1614 pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_HIGH;
1615 lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1616 }
1617 break;
1618 case LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_HIGH:
1619 u32 |= pThis->CTX_SUFF(pReplyFreeQueueBase)[pThis->uReplyFreeQueueNextAddressRead] >> 16;
1620 pThis->uReplyFreeQueueNextAddressRead++;
1621 pThis->uReplyFreeQueueNextAddressRead %= pThis->cReplyQueueEntries;
1622 pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_LOW;
1623 lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1624 break;
1625 default:
1626 AssertMsgFailed(("Invalid doorbell state %d\n", pThis->enmDoorbellState));
1627 }
1628
1629 break;
1630 }
1631 case LSILOGIC_REG_HOST_INTR_STATUS:
1632 {
1633 u32 = ASMAtomicReadU32(&pThis->uInterruptStatus);
1634 break;
1635 }
1636 case LSILOGIC_REG_HOST_INTR_MASK:
1637 {
1638 u32 = ASMAtomicReadU32(&pThis->uInterruptMask);
1639 break;
1640 }
1641 case LSILOGIC_REG_HOST_DIAGNOSTIC:
1642 {
1643 if (pThis->fDiagnosticEnabled)
1644 u32 |= LSILOGIC_REG_HOST_DIAGNOSTIC_DRWE;
1645 if (pThis->fDiagRegsEnabled)
1646 u32 |= LSILOGIC_REG_HOST_DIAGNOSTIC_DIAG_RW_ENABLE;
1647 break;
1648 }
1649 case LSILOGIC_REG_DIAG_RW_DATA:
1650 {
1651 if (pThis->fDiagRegsEnabled)
1652 {
1653#ifndef IN_RING3
1654 return VINF_IOM_R3_MMIO_READ;
1655#else
1656 lsilogicR3DiagRegDataRead(pThis, &u32);
1657#endif
1658 }
1659 }
1660 case LSILOGIC_REG_DIAG_RW_ADDRESS:
1661 {
1662 if (pThis->fDiagRegsEnabled)
1663 {
1664#ifndef IN_RING3
1665 return VINF_IOM_R3_MMIO_READ;
1666#else
1667 lsilogicR3DiagRegAddressRead(pThis, &u32);
1668#endif
1669 }
1670 }
1671 case LSILOGIC_REG_TEST_BASE_ADDRESS: /* The spec doesn't say anything about these registers, so we just ignore them */
1672 default: /* Ignore. */
1673 {
1674 /** @todo LSILOGIC_REG_DIAG_* should return all F's when accessed by MMIO. We
1675 * return 0. Likely to apply to undefined offsets as well. */
1676 break;
1677 }
1678 }
1679
1680 *pu32 = u32;
1681 LogFlowFunc(("pThis=%#p offReg=%#x u32=%#x\n", pThis, offReg, u32));
1682 return rc;
1683}
1684
1685/**
1686 * @callback_method_impl{FNIOMIOPORTOUT}
1687 */
1688PDMBOTHCBDECL(int) lsilogicIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1689{
1690 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
1691 uint32_t offReg = Port - pThis->IOPortBase;
1692 int rc;
1693 RT_NOREF2(pvUser, cb);
1694
1695 if (!(offReg & 3))
1696 {
1697 rc = lsilogicRegisterWrite(pThis, offReg, u32);
1698 if (rc == VINF_IOM_R3_MMIO_WRITE)
1699 rc = VINF_IOM_R3_IOPORT_WRITE;
1700 }
1701 else
1702 {
1703 Log(("lsilogicIOPortWrite: Ignoring misaligned write - offReg=%#x u32=%#x cb=%#x\n", offReg, u32, cb));
1704 rc = VINF_SUCCESS;
1705 }
1706
1707 return rc;
1708}
1709
1710/**
1711 * @callback_method_impl{FNIOMIOPORTIN}
1712 */
1713PDMBOTHCBDECL(int) lsilogicIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1714{
1715 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
1716 uint32_t offReg = Port - pThis->IOPortBase;
1717 RT_NOREF_PV(pvUser);
1718 RT_NOREF_PV(cb);
1719
1720 int rc = lsilogicRegisterRead(pThis, offReg & ~(uint32_t)3, pu32);
1721 if (rc == VINF_IOM_R3_MMIO_READ)
1722 rc = VINF_IOM_R3_IOPORT_READ;
1723
1724 return rc;
1725}
1726
1727/**
1728 * @callback_method_impl{FNIOMMMIOWRITE}
1729 */
1730PDMBOTHCBDECL(int) lsilogicMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
1731{
1732 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
1733 uint32_t offReg = GCPhysAddr - pThis->GCPhysMMIOBase;
1734 uint32_t u32;
1735 int rc;
1736 RT_NOREF_PV(pvUser);
1737
1738 /* See comments in lsilogicR3Map regarding size and alignment. */
1739 if (cb == 4)
1740 u32 = *(uint32_t const *)pv;
1741 else
1742 {
1743 if (cb > 4)
1744 u32 = *(uint32_t const *)pv;
1745 else if (cb >= 2)
1746 u32 = *(uint16_t const *)pv;
1747 else
1748 u32 = *(uint8_t const *)pv;
1749 Log(("lsilogicMMIOWrite: Non-DWORD write access - offReg=%#x u32=%#x cb=%#x\n", offReg, u32, cb));
1750 }
1751
1752 if (!(offReg & 3))
1753 rc = lsilogicRegisterWrite(pThis, offReg, u32);
1754 else
1755 {
1756 Log(("lsilogicIOPortWrite: Ignoring misaligned write - offReg=%#x u32=%#x cb=%#x\n", offReg, u32, cb));
1757 rc = VINF_SUCCESS;
1758 }
1759 return rc;
1760}
1761
1762/**
1763 * @callback_method_impl{FNIOMMMIOREAD}
1764 */
1765PDMBOTHCBDECL(int) lsilogicMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1766{
1767 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
1768 uint32_t offReg = GCPhysAddr - pThis->GCPhysMMIOBase;
1769 Assert(!(offReg & 3)); Assert(cb == 4);
1770 RT_NOREF2(pvUser, cb);
1771
1772 return lsilogicRegisterRead(pThis, offReg, (uint32_t *)pv);
1773}
1774
1775PDMBOTHCBDECL(int) lsilogicDiagnosticWrite(PPDMDEVINS pDevIns, void *pvUser,
1776 RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
1777{
1778#ifdef LOG_ENABLED
1779 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
1780 LogFlowFunc(("pThis=%#p GCPhysAddr=%RGp pv=%#p{%.*Rhxs} cb=%u\n", pThis, GCPhysAddr, pv, cb, pv, cb));
1781#endif
1782
1783 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pvUser); RT_NOREF_PV(GCPhysAddr); RT_NOREF_PV(pv); RT_NOREF_PV(cb);
1784 return VINF_SUCCESS;
1785}
1786
1787PDMBOTHCBDECL(int) lsilogicDiagnosticRead(PPDMDEVINS pDevIns, void *pvUser,
1788 RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1789{
1790#ifdef LOG_ENABLED
1791 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
1792 LogFlowFunc(("pThis=%#p GCPhysAddr=%RGp pv=%#p{%.*Rhxs} cb=%u\n", pThis, GCPhysAddr, pv, cb, pv, cb));
1793#endif
1794
1795 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pvUser); RT_NOREF_PV(GCPhysAddr); RT_NOREF_PV(pv); RT_NOREF_PV(cb);
1796 return VINF_SUCCESS;
1797}
1798
1799#ifdef IN_RING3
1800
1801# ifdef LOG_ENABLED
1802/**
1803 * Dump an SG entry.
1804 *
1805 * @returns nothing.
1806 * @param pSGEntry Pointer to the SG entry to dump
1807 */
1808static void lsilogicDumpSGEntry(PMptSGEntryUnion pSGEntry)
1809{
1810 if (LogIsEnabled())
1811 {
1812 switch (pSGEntry->Simple32.u2ElementType)
1813 {
1814 case MPTSGENTRYTYPE_SIMPLE:
1815 {
1816 Log(("%s: Dumping info for SIMPLE SG entry:\n", __FUNCTION__));
1817 Log(("%s: u24Length=%u\n", __FUNCTION__, pSGEntry->Simple32.u24Length));
1818 Log(("%s: fEndOfList=%d\n", __FUNCTION__, pSGEntry->Simple32.fEndOfList));
1819 Log(("%s: f64BitAddress=%d\n", __FUNCTION__, pSGEntry->Simple32.f64BitAddress));
1820 Log(("%s: fBufferContainsData=%d\n", __FUNCTION__, pSGEntry->Simple32.fBufferContainsData));
1821 Log(("%s: fLocalAddress=%d\n", __FUNCTION__, pSGEntry->Simple32.fLocalAddress));
1822 Log(("%s: fEndOfBuffer=%d\n", __FUNCTION__, pSGEntry->Simple32.fEndOfBuffer));
1823 Log(("%s: fLastElement=%d\n", __FUNCTION__, pSGEntry->Simple32.fLastElement));
1824 Log(("%s: u32DataBufferAddressLow=%u\n", __FUNCTION__, pSGEntry->Simple32.u32DataBufferAddressLow));
1825 if (pSGEntry->Simple32.f64BitAddress)
1826 {
1827 Log(("%s: u32DataBufferAddressHigh=%u\n", __FUNCTION__, pSGEntry->Simple64.u32DataBufferAddressHigh));
1828 Log(("%s: GCDataBufferAddress=%RGp\n", __FUNCTION__,
1829 ((uint64_t)pSGEntry->Simple64.u32DataBufferAddressHigh << 32)
1830 | pSGEntry->Simple64.u32DataBufferAddressLow));
1831 }
1832 else
1833 Log(("%s: GCDataBufferAddress=%RGp\n", __FUNCTION__, pSGEntry->Simple32.u32DataBufferAddressLow));
1834
1835 break;
1836 }
1837 case MPTSGENTRYTYPE_CHAIN:
1838 {
1839 Log(("%s: Dumping info for CHAIN SG entry:\n", __FUNCTION__));
1840 Log(("%s: u16Length=%u\n", __FUNCTION__, pSGEntry->Chain.u16Length));
1841 Log(("%s: u8NExtChainOffset=%d\n", __FUNCTION__, pSGEntry->Chain.u8NextChainOffset));
1842 Log(("%s: f64BitAddress=%d\n", __FUNCTION__, pSGEntry->Chain.f64BitAddress));
1843 Log(("%s: fLocalAddress=%d\n", __FUNCTION__, pSGEntry->Chain.fLocalAddress));
1844 Log(("%s: u32SegmentAddressLow=%u\n", __FUNCTION__, pSGEntry->Chain.u32SegmentAddressLow));
1845 Log(("%s: u32SegmentAddressHigh=%u\n", __FUNCTION__, pSGEntry->Chain.u32SegmentAddressHigh));
1846 if (pSGEntry->Chain.f64BitAddress)
1847 Log(("%s: GCSegmentAddress=%RGp\n", __FUNCTION__,
1848 ((uint64_t)pSGEntry->Chain.u32SegmentAddressHigh << 32) | pSGEntry->Chain.u32SegmentAddressLow));
1849 else
1850 Log(("%s: GCSegmentAddress=%RGp\n", __FUNCTION__, pSGEntry->Chain.u32SegmentAddressLow));
1851 break;
1852 }
1853 }
1854 }
1855}
1856# endif /* LOG_ENABLED */
1857
1858/**
1859 * Walks the guest S/G buffer calling the given copy worker for every buffer.
1860 *
1861 * @returns nothing.
1862 * @param pDevIns Device instance data.
1863 * @param pLsiReq LSI request state.
1864 * @param cbCopy How much bytes to copy.
1865 * @param pfnIoBufCopy Copy worker to call.
1866 */
1867static void lsilogicSgBufWalker(PPDMDEVINS pDevIns, PLSILOGICREQ pLsiReq, size_t cbCopy,
1868 PFNLSILOGICIOBUFCOPY pfnIoBufCopy)
1869{
1870 bool fEndOfList = false;
1871 RTGCPHYS GCPhysSgEntryNext = pLsiReq->GCPhysSgStart;
1872 RTGCPHYS GCPhysSegmentStart = pLsiReq->GCPhysSgStart;
1873 uint32_t cChainOffsetNext = pLsiReq->cChainOffset;
1874 uint8_t *pbBuf = (uint8_t *)pLsiReq->SegIoBuf.pvSeg;
1875
1876 /* Go through the list until we reach the end. */
1877 while ( !fEndOfList
1878 && cbCopy)
1879 {
1880 bool fEndOfSegment = false;
1881
1882 while ( !fEndOfSegment
1883 && cbCopy)
1884 {
1885 MptSGEntryUnion SGEntry;
1886
1887 Log(("%s: Reading SG entry from %RGp\n", __FUNCTION__, GCPhysSgEntryNext));
1888
1889 /* Read the entry. */
1890 PDMDevHlpPhysRead(pDevIns, GCPhysSgEntryNext, &SGEntry, sizeof(MptSGEntryUnion));
1891
1892# ifdef LOG_ENABLED
1893 lsilogicDumpSGEntry(&SGEntry);
1894# endif
1895
1896 AssertMsg(SGEntry.Simple32.u2ElementType == MPTSGENTRYTYPE_SIMPLE, ("Invalid SG entry type\n"));
1897
1898 /* Check if this is a zero element and abort. */
1899 if ( !SGEntry.Simple32.u24Length
1900 && SGEntry.Simple32.fEndOfList
1901 && SGEntry.Simple32.fEndOfBuffer)
1902 return;
1903
1904 uint32_t cbCopyThis = SGEntry.Simple32.u24Length;
1905 RTGCPHYS GCPhysAddrDataBuffer = SGEntry.Simple32.u32DataBufferAddressLow;
1906
1907 if (SGEntry.Simple32.f64BitAddress)
1908 {
1909 GCPhysAddrDataBuffer |= ((uint64_t)SGEntry.Simple64.u32DataBufferAddressHigh) << 32;
1910 GCPhysSgEntryNext += sizeof(MptSGEntrySimple64);
1911 }
1912 else
1913 GCPhysSgEntryNext += sizeof(MptSGEntrySimple32);
1914
1915
1916 pfnIoBufCopy(pDevIns, GCPhysAddrDataBuffer, pbBuf, cbCopyThis);
1917 pbBuf += cbCopyThis;
1918 cbCopy -= cbCopyThis;
1919
1920 /* Check if we reached the end of the list. */
1921 if (SGEntry.Simple32.fEndOfList)
1922 {
1923 /* We finished. */
1924 fEndOfSegment = true;
1925 fEndOfList = true;
1926 }
1927 else if (SGEntry.Simple32.fLastElement)
1928 fEndOfSegment = true;
1929 } /* while (!fEndOfSegment) */
1930
1931 /* Get next chain element. */
1932 if (cChainOffsetNext)
1933 {
1934 MptSGEntryChain SGEntryChain;
1935
1936 PDMDevHlpPhysRead(pDevIns, GCPhysSegmentStart + cChainOffsetNext, &SGEntryChain, sizeof(MptSGEntryChain));
1937
1938 AssertMsg(SGEntryChain.u2ElementType == MPTSGENTRYTYPE_CHAIN, ("Invalid SG entry type\n"));
1939
1940 /* Set the next address now. */
1941 GCPhysSgEntryNext = SGEntryChain.u32SegmentAddressLow;
1942 if (SGEntryChain.f64BitAddress)
1943 GCPhysSgEntryNext |= ((uint64_t)SGEntryChain.u32SegmentAddressHigh) << 32;
1944
1945 GCPhysSegmentStart = GCPhysSgEntryNext;
1946 cChainOffsetNext = SGEntryChain.u8NextChainOffset * sizeof(uint32_t);
1947 }
1948 } /* while (!fEndOfList) */
1949}
1950
1951static DECLCALLBACK(void) lsilogicCopyFromGuest(PPDMDEVINS pDevIns, RTGCPHYS GCPhysIoBuf,
1952 void *pvBuf, size_t cbCopy)
1953{
1954 PDMDevHlpPhysRead(pDevIns, GCPhysIoBuf, pvBuf, cbCopy);
1955}
1956
1957static DECLCALLBACK(void) lsilogicCopyToGuest(PPDMDEVINS pDevIns, RTGCPHYS GCPhysIoBuf,
1958 void *pvBuf, size_t cbCopy)
1959{
1960 PDMDevHlpPCIPhysWrite(pDevIns, GCPhysIoBuf, pvBuf, cbCopy);
1961}
1962
1963/**
1964 * Copy from a guest S/G buffer to the I/O buffer.
1965 *
1966 * @returns nothing.
1967 * @param pDevIns Device instance data.
1968 * @param pLsiReq Request data.
1969 * @param cbCopy How much to copy over.
1970 */
1971DECLINLINE(void) lsilogicCopyFromSgBuf(PPDMDEVINS pDevIns, PLSILOGICREQ pLsiReq, size_t cbCopy)
1972{
1973 lsilogicSgBufWalker(pDevIns, pLsiReq, cbCopy, lsilogicCopyFromGuest);
1974}
1975
1976/**
1977 * Copy from an I/O buffer to the guest S/G buffer.
1978 *
1979 * @returns nothing.
1980 * @param pDevIns Device instance data.
1981 * @param pLsiReq Request data.
1982 * @param cbCopy How much to copy over.
1983 */
1984DECLINLINE(void) lsilogicCopyToSgBuf(PPDMDEVINS pDevIns, PLSILOGICREQ pLsiReq, size_t cbCopy)
1985{
1986 lsilogicSgBufWalker(pDevIns, pLsiReq, cbCopy, lsilogicCopyToGuest);
1987}
1988
1989/**
1990 * Allocates memory for the given request using already allocated memory if possible.
1991 *
1992 * @returns Pointer to the memory or NULL on failure
1993 * @param pLsiReq The request to allocate memory for.
1994 * @param cb The amount of memory to allocate.
1995 */
1996static void *lsilogicReqMemAlloc(PLSILOGICREQ pLsiReq, size_t cb)
1997{
1998 if (pLsiReq->cbAlloc > cb)
1999 pLsiReq->cAllocTooMuch++;
2000 else if (pLsiReq->cbAlloc < cb)
2001 {
2002 if (pLsiReq->cbAlloc)
2003 RTMemPageFree(pLsiReq->pvAlloc, pLsiReq->cbAlloc);
2004
2005 pLsiReq->cbAlloc = RT_ALIGN_Z(cb, _4K);
2006 pLsiReq->pvAlloc = RTMemPageAlloc(pLsiReq->cbAlloc);
2007 pLsiReq->cAllocTooMuch = 0;
2008 if (RT_UNLIKELY(!pLsiReq->pvAlloc))
2009 pLsiReq->cbAlloc = 0;
2010 }
2011
2012 return pLsiReq->pvAlloc;
2013}
2014
2015/**
2016 * Frees memory allocated for the given request.
2017 *
2018 * @returns nothing.
2019 * @param pLsiReq The request.
2020 */
2021static void lsilogicReqMemFree(PLSILOGICREQ pLsiReq)
2022{
2023 if (pLsiReq->cAllocTooMuch >= LSILOGIC_MAX_ALLOC_TOO_MUCH)
2024 {
2025 RTMemPageFree(pLsiReq->pvAlloc, pLsiReq->cbAlloc);
2026 pLsiReq->cbAlloc = 0;
2027 pLsiReq->cAllocTooMuch = 0;
2028 }
2029}
2030
2031/**
2032 * Allocate I/O memory and copies the guest buffer for writes.
2033 *
2034 * @returns VBox status code.
2035 * @param pDevIns The device instance.
2036 * @param pLsiReq The request state.
2037 * @param cbTransfer Amount of bytes to allocate.
2038 */
2039static int lsilogicIoBufAllocate(PPDMDEVINS pDevIns, PLSILOGICREQ pLsiReq,
2040 size_t cbTransfer)
2041{
2042 uint8_t uTxDir = MPT_SCSIIO_REQUEST_CONTROL_TXDIR_GET(pLsiReq->GuestRequest.SCSIIO.u32Control);
2043
2044 AssertMsg( uTxDir == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_WRITE
2045 || uTxDir == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_READ
2046 || uTxDir == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_NONE,
2047 ("Allocating I/O memory for a non I/O request is not allowed\n"));
2048
2049 pLsiReq->SegIoBuf.pvSeg = lsilogicReqMemAlloc(pLsiReq, cbTransfer);
2050 if (!pLsiReq->SegIoBuf.pvSeg)
2051 return VERR_NO_MEMORY;
2052
2053 pLsiReq->SegIoBuf.cbSeg = cbTransfer;
2054 if ( uTxDir == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_WRITE
2055 || uTxDir == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_NONE)
2056 lsilogicCopyFromSgBuf(pDevIns, pLsiReq, cbTransfer);
2057
2058 return VINF_SUCCESS;
2059}
2060
2061/**
2062 * Frees the I/O memory of the given request and updates the guest buffer if necessary.
2063 *
2064 * @returns nothing.
2065 * @param pDevIns The device instance.
2066 * @param pLsiReq The request state.
2067 * @param fCopyToGuest Flag whether to update the guest buffer if necessary.
2068 * Nothing is copied if false even if the request was a read.
2069 */
2070static void lsilogicIoBufFree(PPDMDEVINS pDevIns, PLSILOGICREQ pLsiReq,
2071 bool fCopyToGuest)
2072{
2073 uint8_t uTxDir = MPT_SCSIIO_REQUEST_CONTROL_TXDIR_GET(pLsiReq->GuestRequest.SCSIIO.u32Control);
2074
2075 AssertMsg( uTxDir == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_WRITE
2076 || uTxDir == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_READ
2077 || uTxDir == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_NONE,
2078 ("Allocating I/O memory for a non I/O request is not allowed\n"));
2079
2080 if ( ( uTxDir == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_READ
2081 || uTxDir == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_NONE)
2082 && fCopyToGuest)
2083 lsilogicCopyToSgBuf(pDevIns, pLsiReq, pLsiReq->SegIoBuf.cbSeg);
2084
2085 lsilogicReqMemFree(pLsiReq);
2086 pLsiReq->SegIoBuf.pvSeg = NULL;
2087 pLsiReq->SegIoBuf.cbSeg = 0;
2088}
2089
2090# ifdef LOG_ENABLED
2091static void lsilogicR3DumpSCSIIORequest(PMptSCSIIORequest pSCSIIORequest)
2092{
2093 if (LogIsEnabled())
2094 {
2095 Log(("%s: u8TargetID=%d\n", __FUNCTION__, pSCSIIORequest->u8TargetID));
2096 Log(("%s: u8Bus=%d\n", __FUNCTION__, pSCSIIORequest->u8Bus));
2097 Log(("%s: u8ChainOffset=%d\n", __FUNCTION__, pSCSIIORequest->u8ChainOffset));
2098 Log(("%s: u8Function=%d\n", __FUNCTION__, pSCSIIORequest->u8Function));
2099 Log(("%s: u8CDBLength=%d\n", __FUNCTION__, pSCSIIORequest->u8CDBLength));
2100 Log(("%s: u8SenseBufferLength=%d\n", __FUNCTION__, pSCSIIORequest->u8SenseBufferLength));
2101 Log(("%s: u8MessageFlags=%d\n", __FUNCTION__, pSCSIIORequest->u8MessageFlags));
2102 Log(("%s: u32MessageContext=%#x\n", __FUNCTION__, pSCSIIORequest->u32MessageContext));
2103 for (unsigned i = 0; i < RT_ELEMENTS(pSCSIIORequest->au8LUN); i++)
2104 Log(("%s: u8LUN[%d]=%d\n", __FUNCTION__, i, pSCSIIORequest->au8LUN[i]));
2105 Log(("%s: u32Control=%#x\n", __FUNCTION__, pSCSIIORequest->u32Control));
2106 for (unsigned i = 0; i < RT_ELEMENTS(pSCSIIORequest->au8CDB); i++)
2107 Log(("%s: u8CDB[%d]=%d\n", __FUNCTION__, i, pSCSIIORequest->au8CDB[i]));
2108 Log(("%s: u32DataLength=%#x\n", __FUNCTION__, pSCSIIORequest->u32DataLength));
2109 Log(("%s: u32SenseBufferLowAddress=%#x\n", __FUNCTION__, pSCSIIORequest->u32SenseBufferLowAddress));
2110 }
2111}
2112# endif
2113
2114static void lsilogicR3WarningDiskFull(PPDMDEVINS pDevIns)
2115{
2116 int rc;
2117 LogRel(("LsiLogic#%d: Host disk full\n", pDevIns->iInstance));
2118 rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND | VMSETRTERR_FLAGS_NO_WAIT, "DevLsiLogic_DISKFULL",
2119 N_("Host system reported disk full. VM execution is suspended. You can resume after freeing some space"));
2120 AssertRC(rc);
2121}
2122
2123static void lsilogicR3WarningFileTooBig(PPDMDEVINS pDevIns)
2124{
2125 int rc;
2126 LogRel(("LsiLogic#%d: File too big\n", pDevIns->iInstance));
2127 rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND | VMSETRTERR_FLAGS_NO_WAIT, "DevLsiLogic_FILETOOBIG",
2128 N_("Host system reported that the file size limit of the host file system has been exceeded. VM execution is suspended. You need to move your virtual hard disk to a filesystem which allows bigger files"));
2129 AssertRC(rc);
2130}
2131
2132static void lsilogicR3WarningISCSI(PPDMDEVINS pDevIns)
2133{
2134 int rc;
2135 LogRel(("LsiLogic#%d: iSCSI target unavailable\n", pDevIns->iInstance));
2136 rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND | VMSETRTERR_FLAGS_NO_WAIT, "DevLsiLogic_ISCSIDOWN",
2137 N_("The iSCSI target has stopped responding. VM execution is suspended. You can resume when it is available again"));
2138 AssertRC(rc);
2139}
2140
2141static void lsilogicR3WarningUnknown(PPDMDEVINS pDevIns, int rc)
2142{
2143 int rc2;
2144 LogRel(("LsiLogic#%d: Unknown but recoverable error has occurred (rc=%Rrc)\n", pDevIns->iInstance, rc));
2145 rc2 = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND | VMSETRTERR_FLAGS_NO_WAIT, "DevLsiLogic_UNKNOWN",
2146 N_("An unknown but recoverable I/O error has occurred (rc=%Rrc). VM execution is suspended. You can resume when the error is fixed"), rc);
2147 AssertRC(rc2);
2148}
2149
2150static void lsilogicR3RedoSetWarning(PLSILOGICSCSI pThis, int rc)
2151{
2152 if (rc == VERR_DISK_FULL)
2153 lsilogicR3WarningDiskFull(pThis->CTX_SUFF(pDevIns));
2154 else if (rc == VERR_FILE_TOO_BIG)
2155 lsilogicR3WarningFileTooBig(pThis->CTX_SUFF(pDevIns));
2156 else if (rc == VERR_BROKEN_PIPE || rc == VERR_NET_CONNECTION_REFUSED)
2157 {
2158 /* iSCSI connection abort (first error) or failure to reestablish
2159 * connection (second error). Pause VM. On resume we'll retry. */
2160 lsilogicR3WarningISCSI(pThis->CTX_SUFF(pDevIns));
2161 }
2162 else if (rc != VERR_VD_DEK_MISSING)
2163 lsilogicR3WarningUnknown(pThis->CTX_SUFF(pDevIns), rc);
2164}
2165
2166/**
2167 * Processes a SCSI I/O request by setting up the request
2168 * and sending it to the underlying SCSI driver.
2169 * Steps needed to complete request are done in the
2170 * callback called by the driver below upon completion of
2171 * the request.
2172 *
2173 * @returns VBox status code.
2174 * @param pThis Pointer to the LsiLogic device state.
2175 * @param pLsiReq Pointer to the task state data.
2176 */
2177static int lsilogicR3ProcessSCSIIORequest(PLSILOGICSCSI pThis, PLSILOGICREQ pLsiReq)
2178{
2179 int rc = VINF_SUCCESS;
2180
2181# ifdef LOG_ENABLED
2182 lsilogicR3DumpSCSIIORequest(&pLsiReq->GuestRequest.SCSIIO);
2183# endif
2184
2185 pLsiReq->fBIOS = false;
2186 pLsiReq->GCPhysSgStart = pLsiReq->GCPhysMessageFrameAddr + sizeof(MptSCSIIORequest);
2187 pLsiReq->cChainOffset = pLsiReq->GuestRequest.SCSIIO.u8ChainOffset;
2188 if (pLsiReq->cChainOffset)
2189 pLsiReq->cChainOffset = pLsiReq->cChainOffset * sizeof(uint32_t) - sizeof(MptSCSIIORequest);
2190
2191 if (RT_LIKELY( (pLsiReq->GuestRequest.SCSIIO.u8TargetID < pThis->cDeviceStates)
2192 && (pLsiReq->GuestRequest.SCSIIO.u8Bus == 0)))
2193 {
2194 PLSILOGICDEVICE pTargetDevice;
2195 pTargetDevice = &pThis->paDeviceStates[pLsiReq->GuestRequest.SCSIIO.u8TargetID];
2196
2197 if (pTargetDevice->pDrvBase)
2198 {
2199
2200 if (pLsiReq->GuestRequest.SCSIIO.u32DataLength)
2201 {
2202
2203 rc = lsilogicIoBufAllocate(pThis->CTX_SUFF(pDevIns), pLsiReq,
2204 pLsiReq->GuestRequest.SCSIIO.u32DataLength);
2205 AssertRC(rc); /** @todo Insufficient resources error. */
2206 }
2207
2208 /* Setup the SCSI request. */
2209 pLsiReq->pTargetDevice = pTargetDevice;
2210 pLsiReq->PDMScsiRequest.uLogicalUnit = pLsiReq->GuestRequest.SCSIIO.au8LUN[1];
2211
2212 uint8_t uDataDirection = MPT_SCSIIO_REQUEST_CONTROL_TXDIR_GET(pLsiReq->GuestRequest.SCSIIO.u32Control);
2213
2214 if (uDataDirection == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_NONE)
2215 pLsiReq->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_NONE;
2216 else if (uDataDirection == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_WRITE)
2217 pLsiReq->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_TO_DEVICE;
2218 else if (uDataDirection == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_READ)
2219 pLsiReq->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_FROM_DEVICE;
2220
2221 pLsiReq->PDMScsiRequest.cbCDB = pLsiReq->GuestRequest.SCSIIO.u8CDBLength;
2222 pLsiReq->PDMScsiRequest.pbCDB = pLsiReq->GuestRequest.SCSIIO.au8CDB;
2223 pLsiReq->PDMScsiRequest.cbScatterGather = pLsiReq->GuestRequest.SCSIIO.u32DataLength;
2224 if (pLsiReq->PDMScsiRequest.cbScatterGather)
2225 {
2226 pLsiReq->PDMScsiRequest.cScatterGatherEntries = 1;
2227 pLsiReq->PDMScsiRequest.paScatterGatherHead = &pLsiReq->SegIoBuf;
2228 }
2229 else
2230 {
2231 pLsiReq->PDMScsiRequest.cScatterGatherEntries = 0;
2232 pLsiReq->PDMScsiRequest.paScatterGatherHead = NULL;
2233 }
2234 pLsiReq->PDMScsiRequest.cbSenseBuffer = sizeof(pLsiReq->abSenseBuffer);
2235 memset(pLsiReq->abSenseBuffer, 0, pLsiReq->PDMScsiRequest.cbSenseBuffer);
2236 pLsiReq->PDMScsiRequest.pbSenseBuffer = pLsiReq->abSenseBuffer;
2237 pLsiReq->PDMScsiRequest.pvUser = pLsiReq;
2238
2239 ASMAtomicIncU32(&pTargetDevice->cOutstandingRequests);
2240 rc = pTargetDevice->pDrvSCSIConnector->pfnSCSIRequestSend(pTargetDevice->pDrvSCSIConnector, &pLsiReq->PDMScsiRequest);
2241 AssertMsgRC(rc, ("Sending request to SCSI layer failed rc=%Rrc\n", rc));
2242 return VINF_SUCCESS;
2243 }
2244 else
2245 {
2246 /* Device is not present report SCSI selection timeout. */
2247 pLsiReq->IOCReply.SCSIIOError.u16IOCStatus = MPT_SCSI_IO_ERROR_IOCSTATUS_DEVICE_NOT_THERE;
2248 }
2249 }
2250 else
2251 {
2252 /* Report out of bounds target ID or bus. */
2253 if (pLsiReq->GuestRequest.SCSIIO.u8Bus != 0)
2254 pLsiReq->IOCReply.SCSIIOError.u16IOCStatus = MPT_SCSI_IO_ERROR_IOCSTATUS_INVALID_BUS;
2255 else
2256 pLsiReq->IOCReply.SCSIIOError.u16IOCStatus = MPT_SCSI_IO_ERROR_IOCSTATUS_INVALID_TARGETID;
2257 }
2258
2259 static int g_cLogged = 0;
2260
2261 if (g_cLogged++ < MAX_REL_LOG_ERRORS)
2262 {
2263 LogRel(("LsiLogic#%d: %d/%d (Bus/Target) doesn't exist\n", pThis->CTX_SUFF(pDevIns)->iInstance,
2264 pLsiReq->GuestRequest.SCSIIO.u8TargetID, pLsiReq->GuestRequest.SCSIIO.u8Bus));
2265 /* Log the CDB too */
2266 LogRel(("LsiLogic#%d: Guest issued CDB {%#x",
2267 pThis->CTX_SUFF(pDevIns)->iInstance, pLsiReq->GuestRequest.SCSIIO.au8CDB[0]));
2268 for (unsigned i = 1; i < pLsiReq->GuestRequest.SCSIIO.u8CDBLength; i++)
2269 LogRel((", %#x", pLsiReq->GuestRequest.SCSIIO.au8CDB[i]));
2270 LogRel(("}\n"));
2271 }
2272
2273 /* The rest is equal to both errors. */
2274 pLsiReq->IOCReply.SCSIIOError.u8TargetID = pLsiReq->GuestRequest.SCSIIO.u8TargetID;
2275 pLsiReq->IOCReply.SCSIIOError.u8Bus = pLsiReq->GuestRequest.SCSIIO.u8Bus;
2276 pLsiReq->IOCReply.SCSIIOError.u8MessageLength = sizeof(MptSCSIIOErrorReply) / 4;
2277 pLsiReq->IOCReply.SCSIIOError.u8Function = pLsiReq->GuestRequest.SCSIIO.u8Function;
2278 pLsiReq->IOCReply.SCSIIOError.u8CDBLength = pLsiReq->GuestRequest.SCSIIO.u8CDBLength;
2279 pLsiReq->IOCReply.SCSIIOError.u8SenseBufferLength = pLsiReq->GuestRequest.SCSIIO.u8SenseBufferLength;
2280 pLsiReq->IOCReply.SCSIIOError.u32MessageContext = pLsiReq->GuestRequest.SCSIIO.u32MessageContext;
2281 pLsiReq->IOCReply.SCSIIOError.u8SCSIStatus = SCSI_STATUS_OK;
2282 pLsiReq->IOCReply.SCSIIOError.u8SCSIState = MPT_SCSI_IO_ERROR_SCSI_STATE_TERMINATED;
2283 pLsiReq->IOCReply.SCSIIOError.u32IOCLogInfo = 0;
2284 pLsiReq->IOCReply.SCSIIOError.u32TransferCount = 0;
2285 pLsiReq->IOCReply.SCSIIOError.u32SenseCount = 0;
2286 pLsiReq->IOCReply.SCSIIOError.u32ResponseInfo = 0;
2287
2288 lsilogicFinishAddressReply(pThis, &pLsiReq->IOCReply, false);
2289 RTMemCacheFree(pThis->hTaskCache, pLsiReq);
2290
2291 return rc;
2292}
2293
2294
2295/**
2296 * @interface_method_impl{PDMISCSIPORT,pfnSCSIRequestCompleted}
2297 */
2298static DECLCALLBACK(int) lsilogicR3DeviceSCSIRequestCompleted(PPDMISCSIPORT pInterface, PPDMSCSIREQUEST pSCSIRequest,
2299 int rcCompletion, bool fRedo, int rcReq)
2300{
2301 RT_NOREF(pInterface);
2302 PLSILOGICREQ pLsiReq = (PLSILOGICREQ)pSCSIRequest->pvUser;
2303 PLSILOGICDEVICE pLsiLogicDevice = pLsiReq->pTargetDevice;
2304 PLSILOGICSCSI pThis = pLsiLogicDevice->CTX_SUFF(pLsiLogic);
2305
2306 /* If the task failed but it is possible to redo it again after a suspend
2307 * add it to the list. */
2308 if (fRedo)
2309 {
2310 if (!pLsiReq->fBIOS && pLsiReq->PDMScsiRequest.cbScatterGather)
2311 lsilogicIoBufFree(pThis->CTX_SUFF(pDevIns), pLsiReq, false /* fCopyToGuest */);
2312
2313 /* Add to the list. */
2314 do
2315 {
2316 pLsiReq->pRedoNext = ASMAtomicReadPtrT(&pThis->pTasksRedoHead, PLSILOGICREQ);
2317 } while (!ASMAtomicCmpXchgPtr(&pThis->pTasksRedoHead, pLsiReq, pLsiReq->pRedoNext));
2318
2319 /* Suspend the VM if not done already. */
2320 if (!ASMAtomicXchgBool(&pThis->fRedo, true))
2321 lsilogicR3RedoSetWarning(pThis, rcReq);
2322 }
2323 else
2324 {
2325 if (RT_UNLIKELY(pLsiReq->fBIOS))
2326 {
2327 int rc = vboxscsiRequestFinished(&pThis->VBoxSCSI, pSCSIRequest, rcCompletion);
2328 AssertMsgRC(rc, ("Finishing BIOS SCSI request failed rc=%Rrc\n", rc));
2329 }
2330 else
2331 {
2332 RTGCPHYS GCPhysAddrSenseBuffer;
2333
2334 GCPhysAddrSenseBuffer = pLsiReq->GuestRequest.SCSIIO.u32SenseBufferLowAddress;
2335 GCPhysAddrSenseBuffer |= ((uint64_t)pThis->u32SenseBufferHighAddr << 32);
2336
2337 /* Copy the sense buffer over. */
2338 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhysAddrSenseBuffer, pLsiReq->abSenseBuffer,
2339 RT_UNLIKELY( pLsiReq->GuestRequest.SCSIIO.u8SenseBufferLength
2340 < pLsiReq->PDMScsiRequest.cbSenseBuffer)
2341 ? pLsiReq->GuestRequest.SCSIIO.u8SenseBufferLength
2342 : pLsiReq->PDMScsiRequest.cbSenseBuffer);
2343
2344 if (pLsiReq->PDMScsiRequest.cbScatterGather)
2345 lsilogicIoBufFree(pThis->CTX_SUFF(pDevIns), pLsiReq, true /* fCopyToGuest */);
2346
2347
2348 if (RT_LIKELY(rcCompletion == SCSI_STATUS_OK))
2349 lsilogicR3FinishContextReply(pThis, pLsiReq->GuestRequest.SCSIIO.u32MessageContext);
2350 else
2351 {
2352 /* The SCSI target encountered an error during processing post a reply. */
2353 memset(&pLsiReq->IOCReply, 0, sizeof(MptReplyUnion));
2354 pLsiReq->IOCReply.SCSIIOError.u8TargetID = pLsiReq->GuestRequest.SCSIIO.u8TargetID;
2355 pLsiReq->IOCReply.SCSIIOError.u8Bus = pLsiReq->GuestRequest.SCSIIO.u8Bus;
2356 pLsiReq->IOCReply.SCSIIOError.u8MessageLength = 8;
2357 pLsiReq->IOCReply.SCSIIOError.u8Function = pLsiReq->GuestRequest.SCSIIO.u8Function;
2358 pLsiReq->IOCReply.SCSIIOError.u8CDBLength = pLsiReq->GuestRequest.SCSIIO.u8CDBLength;
2359 pLsiReq->IOCReply.SCSIIOError.u8SenseBufferLength = pLsiReq->GuestRequest.SCSIIO.u8SenseBufferLength;
2360 pLsiReq->IOCReply.SCSIIOError.u8MessageFlags = pLsiReq->GuestRequest.SCSIIO.u8MessageFlags;
2361 pLsiReq->IOCReply.SCSIIOError.u32MessageContext = pLsiReq->GuestRequest.SCSIIO.u32MessageContext;
2362 pLsiReq->IOCReply.SCSIIOError.u8SCSIStatus = rcCompletion;
2363 pLsiReq->IOCReply.SCSIIOError.u8SCSIState = MPT_SCSI_IO_ERROR_SCSI_STATE_AUTOSENSE_VALID;
2364 pLsiReq->IOCReply.SCSIIOError.u16IOCStatus = 0;
2365 pLsiReq->IOCReply.SCSIIOError.u32IOCLogInfo = 0;
2366 pLsiReq->IOCReply.SCSIIOError.u32TransferCount = 0;
2367 pLsiReq->IOCReply.SCSIIOError.u32SenseCount = sizeof(pLsiReq->abSenseBuffer);
2368 pLsiReq->IOCReply.SCSIIOError.u32ResponseInfo = 0;
2369
2370 lsilogicFinishAddressReply(pThis, &pLsiReq->IOCReply, false);
2371 }
2372 }
2373
2374 RTMemCacheFree(pThis->hTaskCache, pLsiReq);
2375 }
2376
2377 ASMAtomicDecU32(&pLsiLogicDevice->cOutstandingRequests);
2378
2379 if (pLsiLogicDevice->cOutstandingRequests == 0 && pThis->fSignalIdle)
2380 PDMDevHlpAsyncNotificationCompleted(pThis->pDevInsR3);
2381
2382 return VINF_SUCCESS;
2383}
2384
2385/**
2386 * @interface_method_impl{PDMISCSIPORT,pfnQueryDeviceLocation}
2387 */
2388static DECLCALLBACK(int) lsilogicR3QueryDeviceLocation(PPDMISCSIPORT pInterface, const char **ppcszController,
2389 uint32_t *piInstance, uint32_t *piLUN)
2390{
2391 PLSILOGICDEVICE pLsiLogicDevice = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, ISCSIPort);
2392 PPDMDEVINS pDevIns = pLsiLogicDevice->CTX_SUFF(pLsiLogic)->CTX_SUFF(pDevIns);
2393
2394 AssertPtrReturn(ppcszController, VERR_INVALID_POINTER);
2395 AssertPtrReturn(piInstance, VERR_INVALID_POINTER);
2396 AssertPtrReturn(piLUN, VERR_INVALID_POINTER);
2397
2398 *ppcszController = pDevIns->pReg->szName;
2399 *piInstance = pDevIns->iInstance;
2400 *piLUN = pLsiLogicDevice->iLUN;
2401
2402 return VINF_SUCCESS;
2403}
2404
2405/**
2406 * Return the configuration page header and data
2407 * which matches the given page type and number.
2408 *
2409 * @returns VINF_SUCCESS if successful
2410 * VERR_NOT_FOUND if the requested page could be found.
2411 * @param u8PageNumber Number of the page to get.
2412 * @param ppPageHeader Where to store the pointer to the page header.
2413 * @param ppbPageData Where to store the pointer to the page data.
2414 */
2415static int lsilogicR3ConfigurationIOUnitPageGetFromNumber(PLSILOGICSCSI pThis,
2416 PMptConfigurationPagesSupported pPages,
2417 uint8_t u8PageNumber,
2418 PMptConfigurationPageHeader *ppPageHeader,
2419 uint8_t **ppbPageData, size_t *pcbPage)
2420{
2421 RT_NOREF(pThis);
2422 int rc = VINF_SUCCESS;
2423
2424 AssertPtr(ppPageHeader); Assert(ppbPageData);
2425
2426 switch (u8PageNumber)
2427 {
2428 case 0:
2429 *ppPageHeader = &pPages->IOUnitPage0.u.fields.Header;
2430 *ppbPageData = pPages->IOUnitPage0.u.abPageData;
2431 *pcbPage = sizeof(pPages->IOUnitPage0);
2432 break;
2433 case 1:
2434 *ppPageHeader = &pPages->IOUnitPage1.u.fields.Header;
2435 *ppbPageData = pPages->IOUnitPage1.u.abPageData;
2436 *pcbPage = sizeof(pPages->IOUnitPage1);
2437 break;
2438 case 2:
2439 *ppPageHeader = &pPages->IOUnitPage2.u.fields.Header;
2440 *ppbPageData = pPages->IOUnitPage2.u.abPageData;
2441 *pcbPage = sizeof(pPages->IOUnitPage2);
2442 break;
2443 case 3:
2444 *ppPageHeader = &pPages->IOUnitPage3.u.fields.Header;
2445 *ppbPageData = pPages->IOUnitPage3.u.abPageData;
2446 *pcbPage = sizeof(pPages->IOUnitPage3);
2447 break;
2448 case 4:
2449 *ppPageHeader = &pPages->IOUnitPage4.u.fields.Header;
2450 *ppbPageData = pPages->IOUnitPage4.u.abPageData;
2451 *pcbPage = sizeof(pPages->IOUnitPage4);
2452 break;
2453 default:
2454 rc = VERR_NOT_FOUND;
2455 }
2456
2457 return rc;
2458}
2459
2460/**
2461 * Return the configuration page header and data
2462 * which matches the given page type and number.
2463 *
2464 * @returns VINF_SUCCESS if successful
2465 * VERR_NOT_FOUND if the requested page could be found.
2466 * @param u8PageNumber Number of the page to get.
2467 * @param ppPageHeader Where to store the pointer to the page header.
2468 * @param ppbPageData Where to store the pointer to the page data.
2469 */
2470static int lsilogicR3ConfigurationIOCPageGetFromNumber(PLSILOGICSCSI pThis,
2471 PMptConfigurationPagesSupported pPages,
2472 uint8_t u8PageNumber,
2473 PMptConfigurationPageHeader *ppPageHeader,
2474 uint8_t **ppbPageData, size_t *pcbPage)
2475{
2476 RT_NOREF(pThis);
2477 int rc = VINF_SUCCESS;
2478
2479 AssertPtr(ppPageHeader); Assert(ppbPageData);
2480
2481 switch (u8PageNumber)
2482 {
2483 case 0:
2484 *ppPageHeader = &pPages->IOCPage0.u.fields.Header;
2485 *ppbPageData = pPages->IOCPage0.u.abPageData;
2486 *pcbPage = sizeof(pPages->IOCPage0);
2487 break;
2488 case 1:
2489 *ppPageHeader = &pPages->IOCPage1.u.fields.Header;
2490 *ppbPageData = pPages->IOCPage1.u.abPageData;
2491 *pcbPage = sizeof(pPages->IOCPage1);
2492 break;
2493 case 2:
2494 *ppPageHeader = &pPages->IOCPage2.u.fields.Header;
2495 *ppbPageData = pPages->IOCPage2.u.abPageData;
2496 *pcbPage = sizeof(pPages->IOCPage2);
2497 break;
2498 case 3:
2499 *ppPageHeader = &pPages->IOCPage3.u.fields.Header;
2500 *ppbPageData = pPages->IOCPage3.u.abPageData;
2501 *pcbPage = sizeof(pPages->IOCPage3);
2502 break;
2503 case 4:
2504 *ppPageHeader = &pPages->IOCPage4.u.fields.Header;
2505 *ppbPageData = pPages->IOCPage4.u.abPageData;
2506 *pcbPage = sizeof(pPages->IOCPage4);
2507 break;
2508 case 6:
2509 *ppPageHeader = &pPages->IOCPage6.u.fields.Header;
2510 *ppbPageData = pPages->IOCPage6.u.abPageData;
2511 *pcbPage = sizeof(pPages->IOCPage6);
2512 break;
2513 default:
2514 rc = VERR_NOT_FOUND;
2515 }
2516
2517 return rc;
2518}
2519
2520/**
2521 * Return the configuration page header and data
2522 * which matches the given page type and number.
2523 *
2524 * @returns VINF_SUCCESS if successful
2525 * VERR_NOT_FOUND if the requested page could be found.
2526 * @param u8PageNumber Number of the page to get.
2527 * @param ppPageHeader Where to store the pointer to the page header.
2528 * @param ppbPageData Where to store the pointer to the page data.
2529 */
2530static int lsilogicR3ConfigurationManufacturingPageGetFromNumber(PLSILOGICSCSI pThis,
2531 PMptConfigurationPagesSupported pPages,
2532 uint8_t u8PageNumber,
2533 PMptConfigurationPageHeader *ppPageHeader,
2534 uint8_t **ppbPageData, size_t *pcbPage)
2535{
2536 int rc = VINF_SUCCESS;
2537
2538 AssertPtr(ppPageHeader); Assert(ppbPageData);
2539
2540 switch (u8PageNumber)
2541 {
2542 case 0:
2543 *ppPageHeader = &pPages->ManufacturingPage0.u.fields.Header;
2544 *ppbPageData = pPages->ManufacturingPage0.u.abPageData;
2545 *pcbPage = sizeof(pPages->ManufacturingPage0);
2546 break;
2547 case 1:
2548 *ppPageHeader = &pPages->ManufacturingPage1.u.fields.Header;
2549 *ppbPageData = pPages->ManufacturingPage1.u.abPageData;
2550 *pcbPage = sizeof(pPages->ManufacturingPage1);
2551 break;
2552 case 2:
2553 *ppPageHeader = &pPages->ManufacturingPage2.u.fields.Header;
2554 *ppbPageData = pPages->ManufacturingPage2.u.abPageData;
2555 *pcbPage = sizeof(pPages->ManufacturingPage2);
2556 break;
2557 case 3:
2558 *ppPageHeader = &pPages->ManufacturingPage3.u.fields.Header;
2559 *ppbPageData = pPages->ManufacturingPage3.u.abPageData;
2560 *pcbPage = sizeof(pPages->ManufacturingPage3);
2561 break;
2562 case 4:
2563 *ppPageHeader = &pPages->ManufacturingPage4.u.fields.Header;
2564 *ppbPageData = pPages->ManufacturingPage4.u.abPageData;
2565 *pcbPage = sizeof(pPages->ManufacturingPage4);
2566 break;
2567 case 5:
2568 *ppPageHeader = &pPages->ManufacturingPage5.u.fields.Header;
2569 *ppbPageData = pPages->ManufacturingPage5.u.abPageData;
2570 *pcbPage = sizeof(pPages->ManufacturingPage5);
2571 break;
2572 case 6:
2573 *ppPageHeader = &pPages->ManufacturingPage6.u.fields.Header;
2574 *ppbPageData = pPages->ManufacturingPage6.u.abPageData;
2575 *pcbPage = sizeof(pPages->ManufacturingPage6);
2576 break;
2577 case 7:
2578 if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
2579 {
2580 *ppPageHeader = &pPages->u.SasPages.pManufacturingPage7->u.fields.Header;
2581 *ppbPageData = pPages->u.SasPages.pManufacturingPage7->u.abPageData;
2582 *pcbPage = pPages->u.SasPages.cbManufacturingPage7;
2583 }
2584 else
2585 rc = VERR_NOT_FOUND;
2586 break;
2587 case 8:
2588 *ppPageHeader = &pPages->ManufacturingPage8.u.fields.Header;
2589 *ppbPageData = pPages->ManufacturingPage8.u.abPageData;
2590 *pcbPage = sizeof(pPages->ManufacturingPage8);
2591 break;
2592 case 9:
2593 *ppPageHeader = &pPages->ManufacturingPage9.u.fields.Header;
2594 *ppbPageData = pPages->ManufacturingPage9.u.abPageData;
2595 *pcbPage = sizeof(pPages->ManufacturingPage9);
2596 break;
2597 case 10:
2598 *ppPageHeader = &pPages->ManufacturingPage10.u.fields.Header;
2599 *ppbPageData = pPages->ManufacturingPage10.u.abPageData;
2600 *pcbPage = sizeof(pPages->ManufacturingPage10);
2601 break;
2602 default:
2603 rc = VERR_NOT_FOUND;
2604 }
2605
2606 return rc;
2607}
2608
2609/**
2610 * Return the configuration page header and data
2611 * which matches the given page type and number.
2612 *
2613 * @returns VINF_SUCCESS if successful
2614 * VERR_NOT_FOUND if the requested page could be found.
2615 * @param u8PageNumber Number of the page to get.
2616 * @param ppPageHeader Where to store the pointer to the page header.
2617 * @param ppbPageData Where to store the pointer to the page data.
2618 */
2619static int lsilogicR3ConfigurationBiosPageGetFromNumber(PLSILOGICSCSI pThis,
2620 PMptConfigurationPagesSupported pPages,
2621 uint8_t u8PageNumber,
2622 PMptConfigurationPageHeader *ppPageHeader,
2623 uint8_t **ppbPageData, size_t *pcbPage)
2624{
2625 RT_NOREF(pThis);
2626 int rc = VINF_SUCCESS;
2627
2628 AssertPtr(ppPageHeader); Assert(ppbPageData);
2629
2630 switch (u8PageNumber)
2631 {
2632 case 1:
2633 *ppPageHeader = &pPages->BIOSPage1.u.fields.Header;
2634 *ppbPageData = pPages->BIOSPage1.u.abPageData;
2635 *pcbPage = sizeof(pPages->BIOSPage1);
2636 break;
2637 case 2:
2638 *ppPageHeader = &pPages->BIOSPage2.u.fields.Header;
2639 *ppbPageData = pPages->BIOSPage2.u.abPageData;
2640 *pcbPage = sizeof(pPages->BIOSPage2);
2641 break;
2642 case 4:
2643 *ppPageHeader = &pPages->BIOSPage4.u.fields.Header;
2644 *ppbPageData = pPages->BIOSPage4.u.abPageData;
2645 *pcbPage = sizeof(pPages->BIOSPage4);
2646 break;
2647 default:
2648 rc = VERR_NOT_FOUND;
2649 }
2650
2651 return rc;
2652}
2653
2654/**
2655 * Return the configuration page header and data
2656 * which matches the given page type and number.
2657 *
2658 * @returns VINF_SUCCESS if successful
2659 * VERR_NOT_FOUND if the requested page could be found.
2660 * @param u8PageNumber Number of the page to get.
2661 * @param ppPageHeader Where to store the pointer to the page header.
2662 * @param ppbPageData Where to store the pointer to the page data.
2663 */
2664static int lsilogicR3ConfigurationSCSISPIPortPageGetFromNumber(PLSILOGICSCSI pThis,
2665 PMptConfigurationPagesSupported pPages,
2666 uint8_t u8Port,
2667 uint8_t u8PageNumber,
2668 PMptConfigurationPageHeader *ppPageHeader,
2669 uint8_t **ppbPageData, size_t *pcbPage)
2670{
2671 RT_NOREF(pThis);
2672 int rc = VINF_SUCCESS;
2673 AssertPtr(ppPageHeader); Assert(ppbPageData);
2674
2675
2676 if (u8Port >= RT_ELEMENTS(pPages->u.SpiPages.aPortPages))
2677 return VERR_NOT_FOUND;
2678
2679 switch (u8PageNumber)
2680 {
2681 case 0:
2682 *ppPageHeader = &pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage0.u.fields.Header;
2683 *ppbPageData = pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage0.u.abPageData;
2684 *pcbPage = sizeof(pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage0);
2685 break;
2686 case 1:
2687 *ppPageHeader = &pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage1.u.fields.Header;
2688 *ppbPageData = pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage1.u.abPageData;
2689 *pcbPage = sizeof(pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage1);
2690 break;
2691 case 2:
2692 *ppPageHeader = &pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage2.u.fields.Header;
2693 *ppbPageData = pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage2.u.abPageData;
2694 *pcbPage = sizeof(pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage2);
2695 break;
2696 default:
2697 rc = VERR_NOT_FOUND;
2698 }
2699
2700 return rc;
2701}
2702
2703/**
2704 * Return the configuration page header and data
2705 * which matches the given page type and number.
2706 *
2707 * @returns VINF_SUCCESS if successful
2708 * VERR_NOT_FOUND if the requested page could be found.
2709 * @param u8PageNumber Number of the page to get.
2710 * @param ppPageHeader Where to store the pointer to the page header.
2711 * @param ppbPageData Where to store the pointer to the page data.
2712 */
2713static int lsilogicR3ConfigurationSCSISPIDevicePageGetFromNumber(PLSILOGICSCSI pThis,
2714 PMptConfigurationPagesSupported pPages,
2715 uint8_t u8Bus,
2716 uint8_t u8TargetID, uint8_t u8PageNumber,
2717 PMptConfigurationPageHeader *ppPageHeader,
2718 uint8_t **ppbPageData, size_t *pcbPage)
2719{
2720 RT_NOREF(pThis);
2721 int rc = VINF_SUCCESS;
2722 AssertPtr(ppPageHeader); Assert(ppbPageData);
2723
2724 if (u8Bus >= RT_ELEMENTS(pPages->u.SpiPages.aBuses))
2725 return VERR_NOT_FOUND;
2726
2727 if (u8TargetID >= RT_ELEMENTS(pPages->u.SpiPages.aBuses[u8Bus].aDevicePages))
2728 return VERR_NOT_FOUND;
2729
2730 switch (u8PageNumber)
2731 {
2732 case 0:
2733 *ppPageHeader = &pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage0.u.fields.Header;
2734 *ppbPageData = pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage0.u.abPageData;
2735 *pcbPage = sizeof(pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage0);
2736 break;
2737 case 1:
2738 *ppPageHeader = &pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage1.u.fields.Header;
2739 *ppbPageData = pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage1.u.abPageData;
2740 *pcbPage = sizeof(pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage1);
2741 break;
2742 case 2:
2743 *ppPageHeader = &pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage2.u.fields.Header;
2744 *ppbPageData = pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage2.u.abPageData;
2745 *pcbPage = sizeof(pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage2);
2746 break;
2747 case 3:
2748 *ppPageHeader = &pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage3.u.fields.Header;
2749 *ppbPageData = pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage3.u.abPageData;
2750 *pcbPage = sizeof(pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage3);
2751 break;
2752 default:
2753 rc = VERR_NOT_FOUND;
2754 }
2755
2756 return rc;
2757}
2758
2759static int lsilogicR3ConfigurationSASIOUnitPageGetFromNumber(PLSILOGICSCSI pThis,
2760 PMptConfigurationPagesSupported pPages,
2761 uint8_t u8PageNumber,
2762 PMptExtendedConfigurationPageHeader *ppPageHeader,
2763 uint8_t **ppbPageData, size_t *pcbPage)
2764{
2765 RT_NOREF(pThis);
2766 int rc = VINF_SUCCESS;
2767
2768 switch (u8PageNumber)
2769 {
2770 case 0:
2771 *ppPageHeader = &pPages->u.SasPages.pSASIOUnitPage0->u.fields.ExtHeader;
2772 *ppbPageData = pPages->u.SasPages.pSASIOUnitPage0->u.abPageData;
2773 *pcbPage = pPages->u.SasPages.cbSASIOUnitPage0;
2774 break;
2775 case 1:
2776 *ppPageHeader = &pPages->u.SasPages.pSASIOUnitPage1->u.fields.ExtHeader;
2777 *ppbPageData = pPages->u.SasPages.pSASIOUnitPage1->u.abPageData;
2778 *pcbPage = pPages->u.SasPages.cbSASIOUnitPage1;
2779 break;
2780 case 2:
2781 *ppPageHeader = &pPages->u.SasPages.SASIOUnitPage2.u.fields.ExtHeader;
2782 *ppbPageData = pPages->u.SasPages.SASIOUnitPage2.u.abPageData;
2783 *pcbPage = sizeof(pPages->u.SasPages.SASIOUnitPage2);
2784 break;
2785 case 3:
2786 *ppPageHeader = &pPages->u.SasPages.SASIOUnitPage3.u.fields.ExtHeader;
2787 *ppbPageData = pPages->u.SasPages.SASIOUnitPage3.u.abPageData;
2788 *pcbPage = sizeof(pPages->u.SasPages.SASIOUnitPage3);
2789 break;
2790 default:
2791 rc = VERR_NOT_FOUND;
2792 }
2793
2794 return rc;
2795}
2796
2797static int lsilogicR3ConfigurationSASPHYPageGetFromNumber(PLSILOGICSCSI pThis,
2798 PMptConfigurationPagesSupported pPages,
2799 uint8_t u8PageNumber,
2800 MptConfigurationPageAddress PageAddress,
2801 PMptExtendedConfigurationPageHeader *ppPageHeader,
2802 uint8_t **ppbPageData, size_t *pcbPage)
2803{
2804 RT_NOREF(pThis);
2805 int rc = VINF_SUCCESS;
2806 uint8_t uAddressForm = MPT_CONFIGURATION_PAGE_ADDRESS_GET_SAS_FORM(PageAddress);
2807 PMptConfigurationPagesSas pPagesSas = &pPages->u.SasPages;
2808 PMptPHY pPHYPages = NULL;
2809
2810 Log(("Address form %d\n", uAddressForm));
2811
2812 if (uAddressForm == 0) /* PHY number */
2813 {
2814 uint8_t u8PhyNumber = PageAddress.SASPHY.Form0.u8PhyNumber;
2815
2816 Log(("PHY number %d\n", u8PhyNumber));
2817
2818 if (u8PhyNumber >= pPagesSas->cPHYs)
2819 return VERR_NOT_FOUND;
2820
2821 pPHYPages = &pPagesSas->paPHYs[u8PhyNumber];
2822 }
2823 else if (uAddressForm == 1) /* Index form */
2824 {
2825 uint16_t u16Index = PageAddress.SASPHY.Form1.u16Index;
2826
2827 Log(("PHY index %d\n", u16Index));
2828
2829 if (u16Index >= pPagesSas->cPHYs)
2830 return VERR_NOT_FOUND;
2831
2832 pPHYPages = &pPagesSas->paPHYs[u16Index];
2833 }
2834 else
2835 rc = VERR_NOT_FOUND; /* Correct? */
2836
2837 if (pPHYPages)
2838 {
2839 switch (u8PageNumber)
2840 {
2841 case 0:
2842 *ppPageHeader = &pPHYPages->SASPHYPage0.u.fields.ExtHeader;
2843 *ppbPageData = pPHYPages->SASPHYPage0.u.abPageData;
2844 *pcbPage = sizeof(pPHYPages->SASPHYPage0);
2845 break;
2846 case 1:
2847 *ppPageHeader = &pPHYPages->SASPHYPage1.u.fields.ExtHeader;
2848 *ppbPageData = pPHYPages->SASPHYPage1.u.abPageData;
2849 *pcbPage = sizeof(pPHYPages->SASPHYPage1);
2850 break;
2851 default:
2852 rc = VERR_NOT_FOUND;
2853 }
2854 }
2855 else
2856 rc = VERR_NOT_FOUND;
2857
2858 return rc;
2859}
2860
2861static int lsilogicR3ConfigurationSASDevicePageGetFromNumber(PLSILOGICSCSI pThis,
2862 PMptConfigurationPagesSupported pPages,
2863 uint8_t u8PageNumber,
2864 MptConfigurationPageAddress PageAddress,
2865 PMptExtendedConfigurationPageHeader *ppPageHeader,
2866 uint8_t **ppbPageData, size_t *pcbPage)
2867{
2868 RT_NOREF(pThis);
2869 int rc = VINF_SUCCESS;
2870 uint8_t uAddressForm = MPT_CONFIGURATION_PAGE_ADDRESS_GET_SAS_FORM(PageAddress);
2871 PMptConfigurationPagesSas pPagesSas = &pPages->u.SasPages;
2872 PMptSASDevice pSASDevice = NULL;
2873
2874 Log(("Address form %d\n", uAddressForm));
2875
2876 if (uAddressForm == 0)
2877 {
2878 uint16_t u16Handle = PageAddress.SASDevice.Form0And2.u16Handle;
2879
2880 Log(("Get next handle %#x\n", u16Handle));
2881
2882 pSASDevice = pPagesSas->pSASDeviceHead;
2883
2884 /* Get the first device? */
2885 if (u16Handle != 0xffff)
2886 {
2887 /* No, search for the right one. */
2888
2889 while ( pSASDevice
2890 && pSASDevice->SASDevicePage0.u.fields.u16DevHandle != u16Handle)
2891 pSASDevice = pSASDevice->pNext;
2892
2893 if (pSASDevice)
2894 pSASDevice = pSASDevice->pNext;
2895 }
2896 }
2897 else if (uAddressForm == 1)
2898 {
2899 uint8_t u8TargetID = PageAddress.SASDevice.Form1.u8TargetID;
2900 uint8_t u8Bus = PageAddress.SASDevice.Form1.u8Bus;
2901
2902 Log(("u8TargetID=%d u8Bus=%d\n", u8TargetID, u8Bus));
2903
2904 pSASDevice = pPagesSas->pSASDeviceHead;
2905
2906 while ( pSASDevice
2907 && ( pSASDevice->SASDevicePage0.u.fields.u8TargetID != u8TargetID
2908 || pSASDevice->SASDevicePage0.u.fields.u8Bus != u8Bus))
2909 pSASDevice = pSASDevice->pNext;
2910 }
2911 else if (uAddressForm == 2)
2912 {
2913 uint16_t u16Handle = PageAddress.SASDevice.Form0And2.u16Handle;
2914
2915 Log(("Handle %#x\n", u16Handle));
2916
2917 pSASDevice = pPagesSas->pSASDeviceHead;
2918
2919 while ( pSASDevice
2920 && pSASDevice->SASDevicePage0.u.fields.u16DevHandle != u16Handle)
2921 pSASDevice = pSASDevice->pNext;
2922 }
2923
2924 if (pSASDevice)
2925 {
2926 switch (u8PageNumber)
2927 {
2928 case 0:
2929 *ppPageHeader = &pSASDevice->SASDevicePage0.u.fields.ExtHeader;
2930 *ppbPageData = pSASDevice->SASDevicePage0.u.abPageData;
2931 *pcbPage = sizeof(pSASDevice->SASDevicePage0);
2932 break;
2933 case 1:
2934 *ppPageHeader = &pSASDevice->SASDevicePage1.u.fields.ExtHeader;
2935 *ppbPageData = pSASDevice->SASDevicePage1.u.abPageData;
2936 *pcbPage = sizeof(pSASDevice->SASDevicePage1);
2937 break;
2938 case 2:
2939 *ppPageHeader = &pSASDevice->SASDevicePage2.u.fields.ExtHeader;
2940 *ppbPageData = pSASDevice->SASDevicePage2.u.abPageData;
2941 *pcbPage = sizeof(pSASDevice->SASDevicePage2);
2942 break;
2943 default:
2944 rc = VERR_NOT_FOUND;
2945 }
2946 }
2947 else
2948 rc = VERR_NOT_FOUND;
2949
2950 return rc;
2951}
2952
2953/**
2954 * Returns the extended configuration page header and data.
2955 * @returns VINF_SUCCESS if successful
2956 * VERR_NOT_FOUND if the requested page could be found.
2957 * @param pThis Pointer to the LsiLogic device state.
2958 * @param pConfigurationReq The configuration request.
2959 * @param u8PageNumber Number of the page to get.
2960 * @param ppPageHeader Where to store the pointer to the page header.
2961 * @param ppbPageData Where to store the pointer to the page data.
2962 */
2963static int lsilogicR3ConfigurationPageGetExtended(PLSILOGICSCSI pThis, PMptConfigurationRequest pConfigurationReq,
2964 PMptExtendedConfigurationPageHeader *ppPageHeader,
2965 uint8_t **ppbPageData, size_t *pcbPage)
2966{
2967 int rc = VINF_SUCCESS;
2968
2969 Log(("Extended page requested:\n"));
2970 Log(("u8ExtPageType=%#x\n", pConfigurationReq->u8ExtPageType));
2971 Log(("u8ExtPageLength=%d\n", pConfigurationReq->u16ExtPageLength));
2972
2973 switch (pConfigurationReq->u8ExtPageType)
2974 {
2975 case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT:
2976 {
2977 rc = lsilogicR3ConfigurationSASIOUnitPageGetFromNumber(pThis,
2978 pThis->pConfigurationPages,
2979 pConfigurationReq->u8PageNumber,
2980 ppPageHeader, ppbPageData, pcbPage);
2981 break;
2982 }
2983 case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASPHYS:
2984 {
2985 rc = lsilogicR3ConfigurationSASPHYPageGetFromNumber(pThis,
2986 pThis->pConfigurationPages,
2987 pConfigurationReq->u8PageNumber,
2988 pConfigurationReq->PageAddress,
2989 ppPageHeader, ppbPageData, pcbPage);
2990 break;
2991 }
2992 case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASDEVICE:
2993 {
2994 rc = lsilogicR3ConfigurationSASDevicePageGetFromNumber(pThis,
2995 pThis->pConfigurationPages,
2996 pConfigurationReq->u8PageNumber,
2997 pConfigurationReq->PageAddress,
2998 ppPageHeader, ppbPageData, pcbPage);
2999 break;
3000 }
3001 case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASEXPANDER: /* No expanders supported */
3002 case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_ENCLOSURE: /* No enclosures supported */
3003 default:
3004 rc = VERR_NOT_FOUND;
3005 }
3006
3007 return rc;
3008}
3009
3010/**
3011 * Processes a Configuration request.
3012 *
3013 * @returns VBox status code.
3014 * @param pThis Pointer to the LsiLogic device state.
3015 * @param pConfigurationReq Pointer to the request structure.
3016 * @param pReply Pointer to the reply message frame
3017 */
3018static int lsilogicR3ProcessConfigurationRequest(PLSILOGICSCSI pThis, PMptConfigurationRequest pConfigurationReq,
3019 PMptConfigurationReply pReply)
3020{
3021 int rc = VINF_SUCCESS;
3022 uint8_t *pbPageData = NULL;
3023 PMptConfigurationPageHeader pPageHeader = NULL;
3024 PMptExtendedConfigurationPageHeader pExtPageHeader = NULL;
3025 uint8_t u8PageType;
3026 uint8_t u8PageAttribute;
3027 size_t cbPage = 0;
3028
3029 LogFlowFunc(("pThis=%#p\n", pThis));
3030
3031 u8PageType = MPT_CONFIGURATION_PAGE_TYPE_GET(pConfigurationReq->u8PageType);
3032 u8PageAttribute = MPT_CONFIGURATION_PAGE_ATTRIBUTE_GET(pConfigurationReq->u8PageType);
3033
3034 Log(("GuestRequest:\n"));
3035 Log(("u8Action=%#x\n", pConfigurationReq->u8Action));
3036 Log(("u8PageType=%#x\n", u8PageType));
3037 Log(("u8PageNumber=%d\n", pConfigurationReq->u8PageNumber));
3038 Log(("u8PageLength=%d\n", pConfigurationReq->u8PageLength));
3039 Log(("u8PageVersion=%d\n", pConfigurationReq->u8PageVersion));
3040
3041 /* Copy common bits from the request into the reply. */
3042 pReply->u8MessageLength = 6; /* 6 32bit D-Words. */
3043 pReply->u8Action = pConfigurationReq->u8Action;
3044 pReply->u8Function = pConfigurationReq->u8Function;
3045 pReply->u32MessageContext = pConfigurationReq->u32MessageContext;
3046
3047 switch (u8PageType)
3048 {
3049 case MPT_CONFIGURATION_PAGE_TYPE_IO_UNIT:
3050 {
3051 /* Get the page data. */
3052 rc = lsilogicR3ConfigurationIOUnitPageGetFromNumber(pThis,
3053 pThis->pConfigurationPages,
3054 pConfigurationReq->u8PageNumber,
3055 &pPageHeader, &pbPageData, &cbPage);
3056 break;
3057 }
3058 case MPT_CONFIGURATION_PAGE_TYPE_IOC:
3059 {
3060 /* Get the page data. */
3061 rc = lsilogicR3ConfigurationIOCPageGetFromNumber(pThis,
3062 pThis->pConfigurationPages,
3063 pConfigurationReq->u8PageNumber,
3064 &pPageHeader, &pbPageData, &cbPage);
3065 break;
3066 }
3067 case MPT_CONFIGURATION_PAGE_TYPE_MANUFACTURING:
3068 {
3069 /* Get the page data. */
3070 rc = lsilogicR3ConfigurationManufacturingPageGetFromNumber(pThis,
3071 pThis->pConfigurationPages,
3072 pConfigurationReq->u8PageNumber,
3073 &pPageHeader, &pbPageData, &cbPage);
3074 break;
3075 }
3076 case MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_PORT:
3077 {
3078 /* Get the page data. */
3079 rc = lsilogicR3ConfigurationSCSISPIPortPageGetFromNumber(pThis,
3080 pThis->pConfigurationPages,
3081 pConfigurationReq->PageAddress.MPIPortNumber.u8PortNumber,
3082 pConfigurationReq->u8PageNumber,
3083 &pPageHeader, &pbPageData, &cbPage);
3084 break;
3085 }
3086 case MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE:
3087 {
3088 /* Get the page data. */
3089 rc = lsilogicR3ConfigurationSCSISPIDevicePageGetFromNumber(pThis,
3090 pThis->pConfigurationPages,
3091 pConfigurationReq->PageAddress.BusAndTargetId.u8Bus,
3092 pConfigurationReq->PageAddress.BusAndTargetId.u8TargetID,
3093 pConfigurationReq->u8PageNumber,
3094 &pPageHeader, &pbPageData, &cbPage);
3095 break;
3096 }
3097 case MPT_CONFIGURATION_PAGE_TYPE_BIOS:
3098 {
3099 rc = lsilogicR3ConfigurationBiosPageGetFromNumber(pThis,
3100 pThis->pConfigurationPages,
3101 pConfigurationReq->u8PageNumber,
3102 &pPageHeader, &pbPageData, &cbPage);
3103 break;
3104 }
3105 case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED:
3106 {
3107 rc = lsilogicR3ConfigurationPageGetExtended(pThis,
3108 pConfigurationReq,
3109 &pExtPageHeader, &pbPageData, &cbPage);
3110 break;
3111 }
3112 default:
3113 rc = VERR_NOT_FOUND;
3114 }
3115
3116 if (rc == VERR_NOT_FOUND)
3117 {
3118 Log(("Page not found\n"));
3119 pReply->u8PageType = pConfigurationReq->u8PageType;
3120 pReply->u8PageNumber = pConfigurationReq->u8PageNumber;
3121 pReply->u8PageLength = pConfigurationReq->u8PageLength;
3122 pReply->u8PageVersion = pConfigurationReq->u8PageVersion;
3123 pReply->u16IOCStatus = MPT_IOCSTATUS_CONFIG_INVALID_PAGE;
3124 return VINF_SUCCESS;
3125 }
3126
3127 if (u8PageType == MPT_CONFIGURATION_PAGE_TYPE_EXTENDED)
3128 {
3129 pReply->u8PageType = pExtPageHeader->u8PageType;
3130 pReply->u8PageNumber = pExtPageHeader->u8PageNumber;
3131 pReply->u8PageVersion = pExtPageHeader->u8PageVersion;
3132 pReply->u8ExtPageType = pExtPageHeader->u8ExtPageType;
3133 pReply->u16ExtPageLength = pExtPageHeader->u16ExtPageLength;
3134
3135 for (int i = 0; i < pExtPageHeader->u16ExtPageLength; i++)
3136 LogFlowFunc(("PageData[%d]=%#x\n", i, ((uint32_t *)pbPageData)[i]));
3137 }
3138 else
3139 {
3140 pReply->u8PageType = pPageHeader->u8PageType;
3141 pReply->u8PageNumber = pPageHeader->u8PageNumber;
3142 pReply->u8PageLength = pPageHeader->u8PageLength;
3143 pReply->u8PageVersion = pPageHeader->u8PageVersion;
3144
3145 for (int i = 0; i < pReply->u8PageLength; i++)
3146 LogFlowFunc(("PageData[%d]=%#x\n", i, ((uint32_t *)pbPageData)[i]));
3147 }
3148
3149 /*
3150 * Don't use the scatter gather handling code as the configuration request always have only one
3151 * simple element.
3152 */
3153 switch (pConfigurationReq->u8Action)
3154 {
3155 case MPT_CONFIGURATION_REQUEST_ACTION_DEFAULT: /* Nothing to do. We are always using the defaults. */
3156 case MPT_CONFIGURATION_REQUEST_ACTION_HEADER:
3157 {
3158 /* Already copied above nothing to do. */
3159 break;
3160 }
3161 case MPT_CONFIGURATION_REQUEST_ACTION_READ_NVRAM:
3162 case MPT_CONFIGURATION_REQUEST_ACTION_READ_CURRENT:
3163 case MPT_CONFIGURATION_REQUEST_ACTION_READ_DEFAULT:
3164 {
3165 uint32_t cbBuffer = pConfigurationReq->SimpleSGElement.u24Length;
3166 if (cbBuffer != 0)
3167 {
3168 RTGCPHYS GCPhysAddrPageBuffer = pConfigurationReq->SimpleSGElement.u32DataBufferAddressLow;
3169 if (pConfigurationReq->SimpleSGElement.f64BitAddress)
3170 GCPhysAddrPageBuffer |= (uint64_t)pConfigurationReq->SimpleSGElement.u32DataBufferAddressHigh << 32;
3171
3172 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhysAddrPageBuffer, pbPageData, RT_MIN(cbBuffer, cbPage));
3173 }
3174 break;
3175 }
3176 case MPT_CONFIGURATION_REQUEST_ACTION_WRITE_CURRENT:
3177 case MPT_CONFIGURATION_REQUEST_ACTION_WRITE_NVRAM:
3178 {
3179 uint32_t cbBuffer = pConfigurationReq->SimpleSGElement.u24Length;
3180 if (cbBuffer != 0)
3181 {
3182 RTGCPHYS GCPhysAddrPageBuffer = pConfigurationReq->SimpleSGElement.u32DataBufferAddressLow;
3183 if (pConfigurationReq->SimpleSGElement.f64BitAddress)
3184 GCPhysAddrPageBuffer |= (uint64_t)pConfigurationReq->SimpleSGElement.u32DataBufferAddressHigh << 32;
3185
3186 LogFlow(("cbBuffer=%u cbPage=%u\n", cbBuffer, cbPage));
3187
3188 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhysAddrPageBuffer, pbPageData,
3189 RT_MIN(cbBuffer, cbPage));
3190 }
3191 break;
3192 }
3193 default:
3194 AssertMsgFailed(("todo\n"));
3195 }
3196
3197 return VINF_SUCCESS;
3198}
3199
3200/**
3201 * Initializes the configuration pages for the SPI SCSI controller.
3202 *
3203 * @returns nothing
3204 * @param pThis Pointer to the LsiLogic device state.
3205 */
3206static void lsilogicR3InitializeConfigurationPagesSpi(PLSILOGICSCSI pThis)
3207{
3208 PMptConfigurationPagesSpi pPages = &pThis->pConfigurationPages->u.SpiPages;
3209
3210 AssertMsg(pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI, ("Controller is not the SPI SCSI one\n"));
3211
3212 LogFlowFunc(("pThis=%#p\n", pThis));
3213
3214 /* Clear everything first. */
3215 memset(pPages, 0, sizeof(MptConfigurationPagesSpi));
3216
3217 for (unsigned i = 0; i < RT_ELEMENTS(pPages->aPortPages); i++)
3218 {
3219 /* SCSI-SPI port page 0. */
3220 pPages->aPortPages[i].SCSISPIPortPage0.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3221 | MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_PORT;
3222 pPages->aPortPages[i].SCSISPIPortPage0.u.fields.Header.u8PageNumber = 0;
3223 pPages->aPortPages[i].SCSISPIPortPage0.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIPort0) / 4;
3224 pPages->aPortPages[i].SCSISPIPortPage0.u.fields.fInformationUnitTransfersCapable = true;
3225 pPages->aPortPages[i].SCSISPIPortPage0.u.fields.fDTCapable = true;
3226 pPages->aPortPages[i].SCSISPIPortPage0.u.fields.fQASCapable = true;
3227 pPages->aPortPages[i].SCSISPIPortPage0.u.fields.u8MinimumSynchronousTransferPeriod = 0;
3228 pPages->aPortPages[i].SCSISPIPortPage0.u.fields.u8MaximumSynchronousOffset = 0xff;
3229 pPages->aPortPages[i].SCSISPIPortPage0.u.fields.fWide = true;
3230 pPages->aPortPages[i].SCSISPIPortPage0.u.fields.fAIPCapable = true;
3231 pPages->aPortPages[i].SCSISPIPortPage0.u.fields.u2SignalingType = 0x3; /* Single Ended. */
3232
3233 /* SCSI-SPI port page 1. */
3234 pPages->aPortPages[i].SCSISPIPortPage1.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE
3235 | MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_PORT;
3236 pPages->aPortPages[i].SCSISPIPortPage1.u.fields.Header.u8PageNumber = 1;
3237 pPages->aPortPages[i].SCSISPIPortPage1.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIPort1) / 4;
3238 pPages->aPortPages[i].SCSISPIPortPage1.u.fields.u8SCSIID = 7;
3239 pPages->aPortPages[i].SCSISPIPortPage1.u.fields.u16PortResponseIDsBitmask = (1 << 7);
3240 pPages->aPortPages[i].SCSISPIPortPage1.u.fields.u32OnBusTimerValue = 0;
3241
3242 /* SCSI-SPI port page 2. */
3243 pPages->aPortPages[i].SCSISPIPortPage2.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE
3244 | MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_PORT;
3245 pPages->aPortPages[i].SCSISPIPortPage2.u.fields.Header.u8PageNumber = 2;
3246 pPages->aPortPages[i].SCSISPIPortPage2.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIPort2) / 4;
3247 pPages->aPortPages[i].SCSISPIPortPage2.u.fields.u4HostSCSIID = 7;
3248 pPages->aPortPages[i].SCSISPIPortPage2.u.fields.u2InitializeHBA = 0x3;
3249 pPages->aPortPages[i].SCSISPIPortPage2.u.fields.fTerminationDisabled = true;
3250 for (unsigned iDevice = 0; iDevice < RT_ELEMENTS(pPages->aPortPages[i].SCSISPIPortPage2.u.fields.aDeviceSettings); iDevice++)
3251 {
3252 pPages->aPortPages[i].SCSISPIPortPage2.u.fields.aDeviceSettings[iDevice].fBootChoice = true;
3253 }
3254 /* Everything else 0 for now. */
3255 }
3256
3257 for (unsigned uBusCurr = 0; uBusCurr < RT_ELEMENTS(pPages->aBuses); uBusCurr++)
3258 {
3259 for (unsigned uDeviceCurr = 0; uDeviceCurr < RT_ELEMENTS(pPages->aBuses[uBusCurr].aDevicePages); uDeviceCurr++)
3260 {
3261 /* SCSI-SPI device page 0. */
3262 pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage0.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3263 | MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE;
3264 pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage0.u.fields.Header.u8PageNumber = 0;
3265 pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage0.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIDevice0) / 4;
3266 /* Everything else 0 for now. */
3267
3268 /* SCSI-SPI device page 1. */
3269 pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage1.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE
3270 | MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE;
3271 pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage1.u.fields.Header.u8PageNumber = 1;
3272 pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage1.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIDevice1) / 4;
3273 /* Everything else 0 for now. */
3274
3275 /* SCSI-SPI device page 2. */
3276 pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage2.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE
3277 | MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE;
3278 pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage2.u.fields.Header.u8PageNumber = 2;
3279 pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage2.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIDevice2) / 4;
3280 /* Everything else 0 for now. */
3281
3282 pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage3.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3283 | MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE;
3284 pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage3.u.fields.Header.u8PageNumber = 3;
3285 pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage3.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIDevice3) / 4;
3286 /* Everything else 0 for now. */
3287 }
3288 }
3289}
3290
3291/**
3292 * Generates a handle.
3293 *
3294 * @returns the handle.
3295 * @param pThis Pointer to the LsiLogic device state.
3296 */
3297DECLINLINE(uint16_t) lsilogicGetHandle(PLSILOGICSCSI pThis)
3298{
3299 uint16_t u16Handle = pThis->u16NextHandle++;
3300 return u16Handle;
3301}
3302
3303/**
3304 * Generates a SAS address (WWID)
3305 *
3306 * @returns nothing.
3307 * @param pSASAddress Pointer to an unitialised SAS address.
3308 * @param iId iId which will go into the address.
3309 *
3310 * @todo Generate better SAS addresses. (Request a block from SUN probably)
3311 */
3312void lsilogicSASAddressGenerate(PSASADDRESS pSASAddress, unsigned iId)
3313{
3314 pSASAddress->u8Address[0] = (0x5 << 5);
3315 pSASAddress->u8Address[1] = 0x01;
3316 pSASAddress->u8Address[2] = 0x02;
3317 pSASAddress->u8Address[3] = 0x03;
3318 pSASAddress->u8Address[4] = 0x04;
3319 pSASAddress->u8Address[5] = 0x05;
3320 pSASAddress->u8Address[6] = 0x06;
3321 pSASAddress->u8Address[7] = iId;
3322}
3323
3324/**
3325 * Initializes the configuration pages for the SAS SCSI controller.
3326 *
3327 * @returns nothing
3328 * @param pThis Pointer to the LsiLogic device state.
3329 */
3330static void lsilogicR3InitializeConfigurationPagesSas(PLSILOGICSCSI pThis)
3331{
3332 PMptConfigurationPagesSas pPages = &pThis->pConfigurationPages->u.SasPages;
3333
3334 AssertMsg(pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS, ("Controller is not the SAS SCSI one\n"));
3335
3336 LogFlowFunc(("pThis=%#p\n", pThis));
3337
3338 /* Manufacturing Page 7 - Connector settings. */
3339 pPages->cbManufacturingPage7 = LSILOGICSCSI_MANUFACTURING7_GET_SIZE(pThis->cPorts);
3340 PMptConfigurationPageManufacturing7 pManufacturingPage7 = (PMptConfigurationPageManufacturing7)RTMemAllocZ(pPages->cbManufacturingPage7);
3341 AssertPtr(pManufacturingPage7);
3342 MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(pManufacturingPage7,
3343 0, 7,
3344 MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3345 /* Set size manually. */
3346 if (pPages->cbManufacturingPage7 / 4 > 255)
3347 pManufacturingPage7->u.fields.Header.u8PageLength = 255;
3348 else
3349 pManufacturingPage7->u.fields.Header.u8PageLength = pPages->cbManufacturingPage7 / 4;
3350 pManufacturingPage7->u.fields.u8NumPhys = pThis->cPorts;
3351 pPages->pManufacturingPage7 = pManufacturingPage7;
3352
3353 /* SAS I/O unit page 0 - Port specific information. */
3354 pPages->cbSASIOUnitPage0 = LSILOGICSCSI_SASIOUNIT0_GET_SIZE(pThis->cPorts);
3355 PMptConfigurationPageSASIOUnit0 pSASPage0 = (PMptConfigurationPageSASIOUnit0)RTMemAllocZ(pPages->cbSASIOUnitPage0);
3356 AssertPtr(pSASPage0);
3357
3358 MPT_CONFIG_EXTENDED_PAGE_HEADER_INIT(pSASPage0, pPages->cbSASIOUnitPage0,
3359 0, MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY,
3360 MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT);
3361 pSASPage0->u.fields.u8NumPhys = pThis->cPorts;
3362 pPages->pSASIOUnitPage0 = pSASPage0;
3363
3364 /* SAS I/O unit page 1 - Port specific settings. */
3365 pPages->cbSASIOUnitPage1 = LSILOGICSCSI_SASIOUNIT1_GET_SIZE(pThis->cPorts);
3366 PMptConfigurationPageSASIOUnit1 pSASPage1 = (PMptConfigurationPageSASIOUnit1)RTMemAllocZ(pPages->cbSASIOUnitPage1);
3367 AssertPtr(pSASPage1);
3368
3369 MPT_CONFIG_EXTENDED_PAGE_HEADER_INIT(pSASPage1, pPages->cbSASIOUnitPage1,
3370 1, MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE,
3371 MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT);
3372 pSASPage1->u.fields.u8NumPhys = pSASPage0->u.fields.u8NumPhys;
3373 pSASPage1->u.fields.u16ControlFlags = 0;
3374 pSASPage1->u.fields.u16AdditionalControlFlags = 0;
3375 pPages->pSASIOUnitPage1 = pSASPage1;
3376
3377 /* SAS I/O unit page 2 - Port specific information. */
3378 pPages->SASIOUnitPage2.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3379 | MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3380 pPages->SASIOUnitPage2.u.fields.ExtHeader.u8PageNumber = 2;
3381 pPages->SASIOUnitPage2.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT;
3382 pPages->SASIOUnitPage2.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASIOUnit2) / 4;
3383
3384 /* SAS I/O unit page 3 - Port specific information. */
3385 pPages->SASIOUnitPage3.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3386 | MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3387 pPages->SASIOUnitPage3.u.fields.ExtHeader.u8PageNumber = 3;
3388 pPages->SASIOUnitPage3.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT;
3389 pPages->SASIOUnitPage3.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASIOUnit3) / 4;
3390
3391 pPages->cPHYs = pThis->cPorts;
3392 pPages->paPHYs = (PMptPHY)RTMemAllocZ(pPages->cPHYs * sizeof(MptPHY));
3393 AssertPtr(pPages->paPHYs);
3394
3395 /* Initialize the PHY configuration */
3396 for (unsigned i = 0; i < pThis->cPorts; i++)
3397 {
3398 PMptPHY pPHYPages = &pPages->paPHYs[i];
3399 uint16_t u16ControllerHandle = lsilogicGetHandle(pThis);
3400
3401 pManufacturingPage7->u.fields.aPHY[i].u8Location = LSILOGICSCSI_MANUFACTURING7_LOCATION_AUTO;
3402
3403 pSASPage0->u.fields.aPHY[i].u8Port = i;
3404 pSASPage0->u.fields.aPHY[i].u8PortFlags = 0;
3405 pSASPage0->u.fields.aPHY[i].u8PhyFlags = 0;
3406 pSASPage0->u.fields.aPHY[i].u8NegotiatedLinkRate = LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_FAILED;
3407 pSASPage0->u.fields.aPHY[i].u32ControllerPhyDeviceInfo = LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_SET(LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_NO);
3408 pSASPage0->u.fields.aPHY[i].u16ControllerDevHandle = u16ControllerHandle;
3409 pSASPage0->u.fields.aPHY[i].u16AttachedDevHandle = 0; /* No device attached. */
3410 pSASPage0->u.fields.aPHY[i].u32DiscoveryStatus = 0; /* No errors */
3411
3412 pSASPage1->u.fields.aPHY[i].u8Port = i;
3413 pSASPage1->u.fields.aPHY[i].u8PortFlags = 0;
3414 pSASPage1->u.fields.aPHY[i].u8PhyFlags = 0;
3415 pSASPage1->u.fields.aPHY[i].u8MaxMinLinkRate = LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MIN_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_15GB)
3416 | LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MAX_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_30GB);
3417 pSASPage1->u.fields.aPHY[i].u32ControllerPhyDeviceInfo = LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_SET(LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_NO);
3418
3419 /* SAS PHY page 0. */
3420 pPHYPages->SASPHYPage0.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3421 | MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3422 pPHYPages->SASPHYPage0.u.fields.ExtHeader.u8PageNumber = 0;
3423 pPHYPages->SASPHYPage0.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASPHYS;
3424 pPHYPages->SASPHYPage0.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASPHY0) / 4;
3425 pPHYPages->SASPHYPage0.u.fields.u8AttachedPhyIdentifier = i;
3426 pPHYPages->SASPHYPage0.u.fields.u32AttachedDeviceInfo = LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_SET(LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_NO);
3427 pPHYPages->SASPHYPage0.u.fields.u8ProgrammedLinkRate = LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MIN_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_15GB)
3428 | LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MAX_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_30GB);
3429 pPHYPages->SASPHYPage0.u.fields.u8HwLinkRate = LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MIN_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_15GB)
3430 | LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MAX_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_30GB);
3431
3432 /* SAS PHY page 1. */
3433 pPHYPages->SASPHYPage1.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3434 | MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3435 pPHYPages->SASPHYPage1.u.fields.ExtHeader.u8PageNumber = 1;
3436 pPHYPages->SASPHYPage1.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASPHYS;
3437 pPHYPages->SASPHYPage1.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASPHY1) / 4;
3438
3439 /* Settings for present devices. */
3440 if (pThis->paDeviceStates[i].pDrvBase)
3441 {
3442 uint16_t u16DeviceHandle = lsilogicGetHandle(pThis);
3443 SASADDRESS SASAddress;
3444 PMptSASDevice pSASDevice = (PMptSASDevice)RTMemAllocZ(sizeof(MptSASDevice));
3445 AssertPtr(pSASDevice);
3446
3447 memset(&SASAddress, 0, sizeof(SASADDRESS));
3448 lsilogicSASAddressGenerate(&SASAddress, i);
3449
3450 pSASPage0->u.fields.aPHY[i].u8NegotiatedLinkRate = LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_SET(LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_30GB);
3451 pSASPage0->u.fields.aPHY[i].u32ControllerPhyDeviceInfo = LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_SET(LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_END)
3452 | LSILOGICSCSI_SASIOUNIT0_DEVICE_SSP_TARGET;
3453 pSASPage0->u.fields.aPHY[i].u16AttachedDevHandle = u16DeviceHandle;
3454 pSASPage1->u.fields.aPHY[i].u32ControllerPhyDeviceInfo = LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_SET(LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_END)
3455 | LSILOGICSCSI_SASIOUNIT0_DEVICE_SSP_TARGET;
3456 pSASPage0->u.fields.aPHY[i].u16ControllerDevHandle = u16DeviceHandle;
3457
3458 pPHYPages->SASPHYPage0.u.fields.u32AttachedDeviceInfo = LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_SET(LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_END);
3459 pPHYPages->SASPHYPage0.u.fields.SASAddress = SASAddress;
3460 pPHYPages->SASPHYPage0.u.fields.u16OwnerDevHandle = u16DeviceHandle;
3461 pPHYPages->SASPHYPage0.u.fields.u16AttachedDevHandle = u16DeviceHandle;
3462
3463 /* SAS device page 0. */
3464 pSASDevice->SASDevicePage0.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3465 | MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3466 pSASDevice->SASDevicePage0.u.fields.ExtHeader.u8PageNumber = 0;
3467 pSASDevice->SASDevicePage0.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASDEVICE;
3468 pSASDevice->SASDevicePage0.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASDevice0) / 4;
3469 pSASDevice->SASDevicePage0.u.fields.SASAddress = SASAddress;
3470 pSASDevice->SASDevicePage0.u.fields.u16ParentDevHandle = u16ControllerHandle;
3471 pSASDevice->SASDevicePage0.u.fields.u8PhyNum = i;
3472 pSASDevice->SASDevicePage0.u.fields.u8AccessStatus = LSILOGICSCSI_SASDEVICE0_STATUS_NO_ERRORS;
3473 pSASDevice->SASDevicePage0.u.fields.u16DevHandle = u16DeviceHandle;
3474 pSASDevice->SASDevicePage0.u.fields.u8TargetID = i;
3475 pSASDevice->SASDevicePage0.u.fields.u8Bus = 0;
3476 pSASDevice->SASDevicePage0.u.fields.u32DeviceInfo = LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_SET(LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_END)
3477 | LSILOGICSCSI_SASIOUNIT0_DEVICE_SSP_TARGET;
3478 pSASDevice->SASDevicePage0.u.fields.u16Flags = LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_PRESENT
3479 | LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_MAPPED_TO_BUS_AND_TARGET_ID
3480 | LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_MAPPING_PERSISTENT;
3481 pSASDevice->SASDevicePage0.u.fields.u8PhysicalPort = i;
3482
3483 /* SAS device page 1. */
3484 pSASDevice->SASDevicePage1.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3485 | MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3486 pSASDevice->SASDevicePage1.u.fields.ExtHeader.u8PageNumber = 1;
3487 pSASDevice->SASDevicePage1.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASDEVICE;
3488 pSASDevice->SASDevicePage1.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASDevice1) / 4;
3489 pSASDevice->SASDevicePage1.u.fields.SASAddress = SASAddress;
3490 pSASDevice->SASDevicePage1.u.fields.u16DevHandle = u16DeviceHandle;
3491 pSASDevice->SASDevicePage1.u.fields.u8TargetID = i;
3492 pSASDevice->SASDevicePage1.u.fields.u8Bus = 0;
3493
3494 /* SAS device page 2. */
3495 pSASDevice->SASDevicePage2.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3496 | MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3497 pSASDevice->SASDevicePage2.u.fields.ExtHeader.u8PageNumber = 2;
3498 pSASDevice->SASDevicePage2.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASDEVICE;
3499 pSASDevice->SASDevicePage2.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASDevice2) / 4;
3500 pSASDevice->SASDevicePage2.u.fields.SASAddress = SASAddress;
3501
3502 /* Link into device list. */
3503 if (!pPages->cDevices)
3504 {
3505 pPages->pSASDeviceHead = pSASDevice;
3506 pPages->pSASDeviceTail = pSASDevice;
3507 pPages->cDevices = 1;
3508 }
3509 else
3510 {
3511 pSASDevice->pPrev = pPages->pSASDeviceTail;
3512 pPages->pSASDeviceTail->pNext = pSASDevice;
3513 pPages->pSASDeviceTail = pSASDevice;
3514 pPages->cDevices++;
3515 }
3516 }
3517 }
3518}
3519
3520/**
3521 * Initializes the configuration pages.
3522 *
3523 * @returns nothing
3524 * @param pThis Pointer to the LsiLogic device state.
3525 */
3526static void lsilogicR3InitializeConfigurationPages(PLSILOGICSCSI pThis)
3527{
3528 /* Initialize the common pages. */
3529 PMptConfigurationPagesSupported pPages = (PMptConfigurationPagesSupported)RTMemAllocZ(sizeof(MptConfigurationPagesSupported));
3530
3531 pThis->pConfigurationPages = pPages;
3532
3533 LogFlowFunc(("pThis=%#p\n", pThis));
3534
3535 /* Clear everything first. */
3536 memset(pPages, 0, sizeof(MptConfigurationPagesSupported));
3537
3538 /* Manufacturing Page 0. */
3539 MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage0,
3540 MptConfigurationPageManufacturing0, 0,
3541 MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3542 strncpy((char *)pPages->ManufacturingPage0.u.fields.abChipName, "VBox MPT Fusion", 16);
3543 strncpy((char *)pPages->ManufacturingPage0.u.fields.abChipRevision, "1.0", 8);
3544 strncpy((char *)pPages->ManufacturingPage0.u.fields.abBoardName, "VBox MPT Fusion", 16);
3545 strncpy((char *)pPages->ManufacturingPage0.u.fields.abBoardAssembly, "SUN", 8);
3546 strncpy((char *)pPages->ManufacturingPage0.u.fields.abBoardTracerNumber, "CAFECAFECAFECAFE", 16);
3547
3548 /* Manufacturing Page 1 - I don't know what this contains so we leave it 0 for now. */
3549 MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage1,
3550 MptConfigurationPageManufacturing1, 1,
3551 MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3552
3553 /* Manufacturing Page 2. */
3554 MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage2,
3555 MptConfigurationPageManufacturing2, 2,
3556 MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3557
3558 if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
3559 {
3560 pPages->ManufacturingPage2.u.fields.u16PCIDeviceID = LSILOGICSCSI_PCI_SPI_DEVICE_ID;
3561 pPages->ManufacturingPage2.u.fields.u8PCIRevisionID = LSILOGICSCSI_PCI_SPI_REVISION_ID;
3562 }
3563 else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
3564 {
3565 pPages->ManufacturingPage2.u.fields.u16PCIDeviceID = LSILOGICSCSI_PCI_SAS_DEVICE_ID;
3566 pPages->ManufacturingPage2.u.fields.u8PCIRevisionID = LSILOGICSCSI_PCI_SAS_REVISION_ID;
3567 }
3568
3569 /* Manufacturing Page 3. */
3570 MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage3,
3571 MptConfigurationPageManufacturing3, 3,
3572 MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3573
3574 if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
3575 {
3576 pPages->ManufacturingPage3.u.fields.u16PCIDeviceID = LSILOGICSCSI_PCI_SPI_DEVICE_ID;
3577 pPages->ManufacturingPage3.u.fields.u8PCIRevisionID = LSILOGICSCSI_PCI_SPI_REVISION_ID;
3578 }
3579 else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
3580 {
3581 pPages->ManufacturingPage3.u.fields.u16PCIDeviceID = LSILOGICSCSI_PCI_SAS_DEVICE_ID;
3582 pPages->ManufacturingPage3.u.fields.u8PCIRevisionID = LSILOGICSCSI_PCI_SAS_REVISION_ID;
3583 }
3584
3585 /* Manufacturing Page 4 - I don't know what this contains so we leave it 0 for now. */
3586 MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage4,
3587 MptConfigurationPageManufacturing4, 4,
3588 MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3589
3590 /* Manufacturing Page 5 - WWID settings. */
3591 MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage5,
3592 MptConfigurationPageManufacturing5, 5,
3593 MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3594
3595 /* Manufacturing Page 6 - Product specific settings. */
3596 MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage6,
3597 MptConfigurationPageManufacturing6, 6,
3598 MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3599
3600 /* Manufacturing Page 8 - Product specific settings. */
3601 MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage8,
3602 MptConfigurationPageManufacturing8, 8,
3603 MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3604
3605 /* Manufacturing Page 9 - Product specific settings. */
3606 MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage9,
3607 MptConfigurationPageManufacturing9, 9,
3608 MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3609
3610 /* Manufacturing Page 10 - Product specific settings. */
3611 MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage10,
3612 MptConfigurationPageManufacturing10, 10,
3613 MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3614
3615 /* I/O Unit page 0. */
3616 MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(&pPages->IOUnitPage0,
3617 MptConfigurationPageIOUnit0, 0,
3618 MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3619 pPages->IOUnitPage0.u.fields.u64UniqueIdentifier = 0xcafe;
3620
3621 /* I/O Unit page 1. */
3622 MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(&pPages->IOUnitPage1,
3623 MptConfigurationPageIOUnit1, 1,
3624 MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3625 pPages->IOUnitPage1.u.fields.fSingleFunction = true;
3626 pPages->IOUnitPage1.u.fields.fAllPathsMapped = false;
3627 pPages->IOUnitPage1.u.fields.fIntegratedRAIDDisabled = true;
3628 pPages->IOUnitPage1.u.fields.f32BitAccessForced = false;
3629
3630 /* I/O Unit page 2. */
3631 MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(&pPages->IOUnitPage2,
3632 MptConfigurationPageIOUnit2, 2,
3633 MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT);
3634 pPages->IOUnitPage2.u.fields.fPauseOnError = false;
3635 pPages->IOUnitPage2.u.fields.fVerboseModeEnabled = false;
3636 pPages->IOUnitPage2.u.fields.fDisableColorVideo = false;
3637 pPages->IOUnitPage2.u.fields.fNotHookInt40h = false;
3638 pPages->IOUnitPage2.u.fields.u32BIOSVersion = 0xcafecafe;
3639 pPages->IOUnitPage2.u.fields.aAdapterOrder[0].fAdapterEnabled = true;
3640 pPages->IOUnitPage2.u.fields.aAdapterOrder[0].fAdapterEmbedded = true;
3641 pPages->IOUnitPage2.u.fields.aAdapterOrder[0].u8PCIBusNumber = 0;
3642 pPages->IOUnitPage2.u.fields.aAdapterOrder[0].u8PCIDevFn = pThis->PciDev.devfn;
3643
3644 /* I/O Unit page 3. */
3645 MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(&pPages->IOUnitPage3,
3646 MptConfigurationPageIOUnit3, 3,
3647 MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3648 pPages->IOUnitPage3.u.fields.u8GPIOCount = 0;
3649
3650 /* I/O Unit page 4. */
3651 MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(&pPages->IOUnitPage4,
3652 MptConfigurationPageIOUnit4, 4,
3653 MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3654
3655 /* IOC page 0. */
3656 MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage0,
3657 MptConfigurationPageIOC0, 0,
3658 MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3659 pPages->IOCPage0.u.fields.u32TotalNVStore = 0;
3660 pPages->IOCPage0.u.fields.u32FreeNVStore = 0;
3661
3662 if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
3663 {
3664 pPages->IOCPage0.u.fields.u16VendorId = LSILOGICSCSI_PCI_VENDOR_ID;
3665 pPages->IOCPage0.u.fields.u16DeviceId = LSILOGICSCSI_PCI_SPI_DEVICE_ID;
3666 pPages->IOCPage0.u.fields.u8RevisionId = LSILOGICSCSI_PCI_SPI_REVISION_ID;
3667 pPages->IOCPage0.u.fields.u32ClassCode = LSILOGICSCSI_PCI_SPI_CLASS_CODE;
3668 pPages->IOCPage0.u.fields.u16SubsystemVendorId = LSILOGICSCSI_PCI_SPI_SUBSYSTEM_VENDOR_ID;
3669 pPages->IOCPage0.u.fields.u16SubsystemId = LSILOGICSCSI_PCI_SPI_SUBSYSTEM_ID;
3670 }
3671 else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
3672 {
3673 pPages->IOCPage0.u.fields.u16VendorId = LSILOGICSCSI_PCI_VENDOR_ID;
3674 pPages->IOCPage0.u.fields.u16DeviceId = LSILOGICSCSI_PCI_SAS_DEVICE_ID;
3675 pPages->IOCPage0.u.fields.u8RevisionId = LSILOGICSCSI_PCI_SAS_REVISION_ID;
3676 pPages->IOCPage0.u.fields.u32ClassCode = LSILOGICSCSI_PCI_SAS_CLASS_CODE;
3677 pPages->IOCPage0.u.fields.u16SubsystemVendorId = LSILOGICSCSI_PCI_SAS_SUBSYSTEM_VENDOR_ID;
3678 pPages->IOCPage0.u.fields.u16SubsystemId = LSILOGICSCSI_PCI_SAS_SUBSYSTEM_ID;
3679 }
3680
3681 /* IOC page 1. */
3682 MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage1,
3683 MptConfigurationPageIOC1, 1,
3684 MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3685 pPages->IOCPage1.u.fields.fReplyCoalescingEnabled = false;
3686 pPages->IOCPage1.u.fields.u32CoalescingTimeout = 0;
3687 pPages->IOCPage1.u.fields.u8CoalescingDepth = 0;
3688
3689 /* IOC page 2. */
3690 MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage2,
3691 MptConfigurationPageIOC2, 2,
3692 MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3693 /* Everything else here is 0. */
3694
3695 /* IOC page 3. */
3696 MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage3,
3697 MptConfigurationPageIOC3, 3,
3698 MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3699 /* Everything else here is 0. */
3700
3701 /* IOC page 4. */
3702 MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage4,
3703 MptConfigurationPageIOC4, 4,
3704 MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3705 /* Everything else here is 0. */
3706
3707 /* IOC page 6. */
3708 MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage6,
3709 MptConfigurationPageIOC6, 6,
3710 MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3711 /* Everything else here is 0. */
3712
3713 /* BIOS page 1. */
3714 MPT_CONFIG_PAGE_HEADER_INIT_BIOS(&pPages->BIOSPage1,
3715 MptConfigurationPageBIOS1, 1,
3716 MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3717
3718 /* BIOS page 2. */
3719 MPT_CONFIG_PAGE_HEADER_INIT_BIOS(&pPages->BIOSPage2,
3720 MptConfigurationPageBIOS2, 2,
3721 MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3722
3723 /* BIOS page 4. */
3724 MPT_CONFIG_PAGE_HEADER_INIT_BIOS(&pPages->BIOSPage4,
3725 MptConfigurationPageBIOS4, 4,
3726 MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3727
3728 if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
3729 lsilogicR3InitializeConfigurationPagesSpi(pThis);
3730 else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
3731 lsilogicR3InitializeConfigurationPagesSas(pThis);
3732 else
3733 AssertMsgFailed(("Invalid controller type %d\n", pThis->enmCtrlType));
3734}
3735
3736/**
3737 * @callback_method_impl{FNPDMQUEUEDEV, Transmit queue consumer.}
3738 */
3739static DECLCALLBACK(bool) lsilogicR3NotifyQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
3740{
3741 RT_NOREF(pItem);
3742 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
3743 int rc = VINF_SUCCESS;
3744
3745 LogFlowFunc(("pDevIns=%#p pItem=%#p\n", pDevIns, pItem));
3746
3747 rc = SUPSemEventSignal(pThis->pSupDrvSession, pThis->hEvtProcess);
3748 AssertRC(rc);
3749
3750 return true;
3751}
3752
3753/**
3754 * Sets the emulated controller type from a given string.
3755 *
3756 * @returns VBox status code.
3757 *
3758 * @param pThis Pointer to the LsiLogic device state.
3759 * @param pcszCtrlType The string to use.
3760 */
3761static int lsilogicR3GetCtrlTypeFromString(PLSILOGICSCSI pThis, const char *pcszCtrlType)
3762{
3763 int rc = VERR_INVALID_PARAMETER;
3764
3765 if (!RTStrCmp(pcszCtrlType, LSILOGICSCSI_PCI_SPI_CTRLNAME))
3766 {
3767 pThis->enmCtrlType = LSILOGICCTRLTYPE_SCSI_SPI;
3768 rc = VINF_SUCCESS;
3769 }
3770 else if (!RTStrCmp(pcszCtrlType, LSILOGICSCSI_PCI_SAS_CTRLNAME))
3771 {
3772 pThis->enmCtrlType = LSILOGICCTRLTYPE_SCSI_SAS;
3773 rc = VINF_SUCCESS;
3774 }
3775
3776 return rc;
3777}
3778
3779/**
3780 * @callback_method_impl{FNIOMIOPORTIN, Legacy ISA port.}
3781 */
3782static DECLCALLBACK(int) lsilogicR3IsaIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
3783{
3784 RT_NOREF(pvUser, cb);
3785 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
3786
3787 Assert(cb == 1);
3788
3789 uint8_t iRegister = pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI
3790 ? Port - LSILOGIC_BIOS_IO_PORT
3791 : Port - LSILOGIC_SAS_BIOS_IO_PORT;
3792 int rc = vboxscsiReadRegister(&pThis->VBoxSCSI, iRegister, pu32);
3793
3794 Log2(("%s: pu32=%p:{%.*Rhxs} iRegister=%d rc=%Rrc\n",
3795 __FUNCTION__, pu32, 1, pu32, iRegister, rc));
3796
3797 return rc;
3798}
3799
3800/**
3801 * Prepares a request from the BIOS.
3802 *
3803 * @returns VBox status code.
3804 * @param pThis Pointer to the LsiLogic device state.
3805 */
3806static int lsilogicR3PrepareBiosScsiRequest(PLSILOGICSCSI pThis)
3807{
3808 int rc;
3809 PLSILOGICREQ pLsiReq;
3810 uint32_t uTargetDevice;
3811
3812 rc = RTMemCacheAllocEx(pThis->hTaskCache, (void **)&pLsiReq);
3813 AssertMsgRCReturn(rc, ("Getting task from cache failed rc=%Rrc\n", rc), rc);
3814
3815 pLsiReq->fBIOS = true;
3816
3817 rc = vboxscsiSetupRequest(&pThis->VBoxSCSI, &pLsiReq->PDMScsiRequest, &uTargetDevice);
3818 AssertMsgRCReturn(rc, ("Setting up SCSI request failed rc=%Rrc\n", rc), rc);
3819
3820 pLsiReq->PDMScsiRequest.pvUser = pLsiReq;
3821
3822 if (uTargetDevice < pThis->cDeviceStates)
3823 {
3824 pLsiReq->pTargetDevice = &pThis->paDeviceStates[uTargetDevice];
3825
3826 if (pLsiReq->pTargetDevice->pDrvBase)
3827 {
3828 ASMAtomicIncU32(&pLsiReq->pTargetDevice->cOutstandingRequests);
3829
3830 rc = pLsiReq->pTargetDevice->pDrvSCSIConnector->pfnSCSIRequestSend(pLsiReq->pTargetDevice->pDrvSCSIConnector,
3831 &pLsiReq->PDMScsiRequest);
3832 AssertMsgRCReturn(rc, ("Sending request to SCSI layer failed rc=%Rrc\n", rc), rc);
3833 return VINF_SUCCESS;
3834 }
3835 }
3836
3837 /* Device is not present. */
3838 AssertMsg(pLsiReq->PDMScsiRequest.pbCDB[0] == SCSI_INQUIRY,
3839 ("Device is not present but command is not inquiry\n"));
3840
3841 SCSIINQUIRYDATA ScsiInquiryData;
3842
3843 memset(&ScsiInquiryData, 0, sizeof(SCSIINQUIRYDATA));
3844 ScsiInquiryData.u5PeripheralDeviceType = SCSI_INQUIRY_DATA_PERIPHERAL_DEVICE_TYPE_UNKNOWN;
3845 ScsiInquiryData.u3PeripheralQualifier = SCSI_INQUIRY_DATA_PERIPHERAL_QUALIFIER_NOT_CONNECTED_NOT_SUPPORTED;
3846
3847 memcpy(pThis->VBoxSCSI.pbBuf, &ScsiInquiryData, 5);
3848
3849 rc = vboxscsiRequestFinished(&pThis->VBoxSCSI, &pLsiReq->PDMScsiRequest, SCSI_STATUS_OK);
3850 AssertMsgRCReturn(rc, ("Finishing BIOS SCSI request failed rc=%Rrc\n", rc), rc);
3851
3852 RTMemCacheFree(pThis->hTaskCache, pLsiReq);
3853 return rc;
3854}
3855
3856/**
3857 * @callback_method_impl{FNIOMIOPORTOUT, Legacy ISA port.}
3858 */
3859static DECLCALLBACK(int) lsilogicR3IsaIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
3860{
3861 RT_NOREF(pvUser, cb);
3862 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
3863 Log2(("#%d %s: pvUser=%#p cb=%d u32=%#x Port=%#x\n", pDevIns->iInstance, __FUNCTION__, pvUser, cb, u32, Port));
3864
3865 Assert(cb == 1);
3866
3867 /*
3868 * If there is already a request form the BIOS pending ignore this write
3869 * because it should not happen.
3870 */
3871 if (ASMAtomicReadBool(&pThis->fBiosReqPending))
3872 return VINF_SUCCESS;
3873
3874 uint8_t iRegister = pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI
3875 ? Port - LSILOGIC_BIOS_IO_PORT
3876 : Port - LSILOGIC_SAS_BIOS_IO_PORT;
3877 int rc = vboxscsiWriteRegister(&pThis->VBoxSCSI, iRegister, (uint8_t)u32);
3878 if (rc == VERR_MORE_DATA)
3879 {
3880 ASMAtomicXchgBool(&pThis->fBiosReqPending, true);
3881 /* Send a notifier to the PDM queue that there are pending requests. */
3882 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pNotificationQueue));
3883 AssertMsg(pItem, ("Allocating item for queue failed\n"));
3884 PDMQueueInsert(pThis->CTX_SUFF(pNotificationQueue), (PPDMQUEUEITEMCORE)pItem);
3885 }
3886 else if (RT_FAILURE(rc))
3887 AssertMsgFailed(("Writing BIOS register failed %Rrc\n", rc));
3888
3889 return VINF_SUCCESS;
3890}
3891
3892/**
3893 * @callback_method_impl{FNIOMIOPORTOUTSTRING,
3894 * Port I/O Handler for primary port range OUT string operations.}
3895 */
3896static DECLCALLBACK(int) lsilogicR3IsaIOPortWriteStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port,
3897 uint8_t const *pbSrc, uint32_t *pcTransfers, unsigned cb)
3898{
3899 RT_NOREF(pvUser);
3900 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
3901 Log2(("#%d %s: pvUser=%#p cb=%d Port=%#x\n", pDevIns->iInstance, __FUNCTION__, pvUser, cb, Port));
3902
3903 uint8_t iRegister = pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI
3904 ? Port - LSILOGIC_BIOS_IO_PORT
3905 : Port - LSILOGIC_SAS_BIOS_IO_PORT;
3906 int rc = vboxscsiWriteString(pDevIns, &pThis->VBoxSCSI, iRegister, pbSrc, pcTransfers, cb);
3907 if (rc == VERR_MORE_DATA)
3908 {
3909 ASMAtomicXchgBool(&pThis->fBiosReqPending, true);
3910 /* Send a notifier to the PDM queue that there are pending requests. */
3911 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pNotificationQueue));
3912 AssertMsg(pItem, ("Allocating item for queue failed\n"));
3913 PDMQueueInsert(pThis->CTX_SUFF(pNotificationQueue), (PPDMQUEUEITEMCORE)pItem);
3914 }
3915 else if (RT_FAILURE(rc))
3916 AssertMsgFailed(("Writing BIOS register failed %Rrc\n", rc));
3917
3918 return VINF_SUCCESS;
3919}
3920
3921/**
3922 * @callback_method_impl{FNIOMIOPORTINSTRING,
3923 * Port I/O Handler for primary port range IN string operations.}
3924 */
3925static DECLCALLBACK(int) lsilogicR3IsaIOPortReadStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port,
3926 uint8_t *pbDst, uint32_t *pcTransfers, unsigned cb)
3927{
3928 RT_NOREF(pvUser);
3929 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
3930 LogFlowFunc(("#%d %s: pvUser=%#p cb=%d Port=%#x\n", pDevIns->iInstance, __FUNCTION__, pvUser, cb, Port));
3931
3932 uint8_t iRegister = pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI
3933 ? Port - LSILOGIC_BIOS_IO_PORT
3934 : Port - LSILOGIC_SAS_BIOS_IO_PORT;
3935 return vboxscsiReadString(pDevIns, &pThis->VBoxSCSI, iRegister, pbDst, pcTransfers, cb);
3936}
3937
3938/**
3939 * @callback_method_impl{FNPCIIOREGIONMAP}
3940 */
3941static DECLCALLBACK(int) lsilogicR3Map(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion,
3942 RTGCPHYS GCPhysAddress, RTGCPHYS cb,
3943 PCIADDRESSSPACE enmType)
3944{
3945 PPDMDEVINS pDevIns = pPciDev->pDevIns;
3946 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
3947 int rc = VINF_SUCCESS;
3948 const char *pcszCtrl = pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI
3949 ? "LsiLogic"
3950 : "LsiLogicSas";
3951 const char *pcszDiag = pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI
3952 ? "LsiLogicDiag"
3953 : "LsiLogicSasDiag";
3954
3955 Log2(("%s: registering area at GCPhysAddr=%RGp cb=%RGp\n", __FUNCTION__, GCPhysAddress, cb));
3956
3957 AssertMsg( (enmType == PCI_ADDRESS_SPACE_MEM && cb >= LSILOGIC_PCI_SPACE_MEM_SIZE)
3958 || (enmType == PCI_ADDRESS_SPACE_IO && cb >= LSILOGIC_PCI_SPACE_IO_SIZE),
3959 ("PCI region type and size do not match\n"));
3960
3961 if (enmType == PCI_ADDRESS_SPACE_MEM && iRegion == 1)
3962 {
3963 /*
3964 * Non-4-byte read access to LSILOGIC_REG_REPLY_QUEUE may cause real strange behavior
3965 * because the data is part of a physical guest address. But some drivers use 1-byte
3966 * access to scan for SCSI controllers. So, we simplify our code by telling IOM to
3967 * read DWORDs.
3968 *
3969 * Regarding writes, we couldn't find anything specific in the specs about what should
3970 * happen. So far we've ignored unaligned writes and assumed the missing bytes of
3971 * byte and word access to be zero. We suspect that IOMMMIO_FLAGS_WRITE_ONLY_DWORD
3972 * or IOMMMIO_FLAGS_WRITE_DWORD_ZEROED would be the most appropriate here, but since we
3973 * don't have real hw to test one, the old behavior is kept exactly like it used to be.
3974 */
3975 /** @todo Check out unaligned writes and non-dword writes on real LsiLogic
3976 * hardware. */
3977 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
3978 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_PASSTHRU,
3979 lsilogicMMIOWrite, lsilogicMMIORead, pcszCtrl);
3980 if (RT_FAILURE(rc))
3981 return rc;
3982
3983 if (pThis->fR0Enabled)
3984 {
3985 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
3986 "lsilogicMMIOWrite", "lsilogicMMIORead");
3987 if (RT_FAILURE(rc))
3988 return rc;
3989 }
3990
3991 if (pThis->fGCEnabled)
3992 {
3993 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
3994 "lsilogicMMIOWrite", "lsilogicMMIORead");
3995 if (RT_FAILURE(rc))
3996 return rc;
3997 }
3998
3999 pThis->GCPhysMMIOBase = GCPhysAddress;
4000 }
4001 else if (enmType == PCI_ADDRESS_SPACE_MEM && iRegion == 2)
4002 {
4003 /* We use the assigned size here, because we currently only support page aligned MMIO ranges. */
4004 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
4005 IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,
4006 lsilogicDiagnosticWrite, lsilogicDiagnosticRead, pcszDiag);
4007 if (RT_FAILURE(rc))
4008 return rc;
4009
4010 if (pThis->fR0Enabled)
4011 {
4012 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
4013 "lsilogicDiagnosticWrite", "lsilogicDiagnosticRead");
4014 if (RT_FAILURE(rc))
4015 return rc;
4016 }
4017
4018 if (pThis->fGCEnabled)
4019 {
4020 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
4021 "lsilogicDiagnosticWrite", "lsilogicDiagnosticRead");
4022 if (RT_FAILURE(rc))
4023 return rc;
4024 }
4025 }
4026 else if (enmType == PCI_ADDRESS_SPACE_IO)
4027 {
4028 rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, LSILOGIC_PCI_SPACE_IO_SIZE,
4029 NULL, lsilogicIOPortWrite, lsilogicIOPortRead, NULL, NULL, pcszCtrl);
4030 if (RT_FAILURE(rc))
4031 return rc;
4032
4033 if (pThis->fR0Enabled)
4034 {
4035 rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, LSILOGIC_PCI_SPACE_IO_SIZE,
4036 0, "lsilogicIOPortWrite", "lsilogicIOPortRead", NULL, NULL, pcszCtrl);
4037 if (RT_FAILURE(rc))
4038 return rc;
4039 }
4040
4041 if (pThis->fGCEnabled)
4042 {
4043 rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, LSILOGIC_PCI_SPACE_IO_SIZE,
4044 0, "lsilogicIOPortWrite", "lsilogicIOPortRead", NULL, NULL, pcszCtrl);
4045 if (RT_FAILURE(rc))
4046 return rc;
4047 }
4048
4049 pThis->IOPortBase = (RTIOPORT)GCPhysAddress;
4050 }
4051 else
4052 AssertMsgFailed(("Invalid enmType=%d iRegion=%d\n", enmType, iRegion));
4053
4054 return rc;
4055}
4056
4057/**
4058 * @callback_method_impl{PFNDBGFHANDLERDEV}
4059 */
4060static DECLCALLBACK(void) lsilogicR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4061{
4062 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4063 bool fVerbose = false;
4064
4065 /*
4066 * Parse args.
4067 */
4068 if (pszArgs)
4069 fVerbose = strstr(pszArgs, "verbose") != NULL;
4070
4071 /*
4072 * Show info.
4073 */
4074 pHlp->pfnPrintf(pHlp,
4075 "%s#%d: port=%RTiop mmio=%RGp max-devices=%u GC=%RTbool R0=%RTbool\n",
4076 pDevIns->pReg->szName,
4077 pDevIns->iInstance,
4078 pThis->IOPortBase, pThis->GCPhysMMIOBase,
4079 pThis->cDeviceStates,
4080 pThis->fGCEnabled ? true : false,
4081 pThis->fR0Enabled ? true : false);
4082
4083 /*
4084 * Show general state.
4085 */
4086 pHlp->pfnPrintf(pHlp, "enmState=%u\n", pThis->enmState);
4087 pHlp->pfnPrintf(pHlp, "enmWhoInit=%u\n", pThis->enmWhoInit);
4088 pHlp->pfnPrintf(pHlp, "enmDoorbellState=%d\n", pThis->enmDoorbellState);
4089 pHlp->pfnPrintf(pHlp, "fDiagnosticEnabled=%RTbool\n", pThis->fDiagnosticEnabled);
4090 pHlp->pfnPrintf(pHlp, "fNotificationSent=%RTbool\n", pThis->fNotificationSent);
4091 pHlp->pfnPrintf(pHlp, "fEventNotificationEnabled=%RTbool\n", pThis->fEventNotificationEnabled);
4092 pHlp->pfnPrintf(pHlp, "uInterruptMask=%#x\n", pThis->uInterruptMask);
4093 pHlp->pfnPrintf(pHlp, "uInterruptStatus=%#x\n", pThis->uInterruptStatus);
4094 pHlp->pfnPrintf(pHlp, "u16IOCFaultCode=%#06x\n", pThis->u16IOCFaultCode);
4095 pHlp->pfnPrintf(pHlp, "u32HostMFAHighAddr=%#x\n", pThis->u32HostMFAHighAddr);
4096 pHlp->pfnPrintf(pHlp, "u32SenseBufferHighAddr=%#x\n", pThis->u32SenseBufferHighAddr);
4097 pHlp->pfnPrintf(pHlp, "cMaxDevices=%u\n", pThis->cMaxDevices);
4098 pHlp->pfnPrintf(pHlp, "cMaxBuses=%u\n", pThis->cMaxBuses);
4099 pHlp->pfnPrintf(pHlp, "cbReplyFrame=%u\n", pThis->cbReplyFrame);
4100 pHlp->pfnPrintf(pHlp, "cReplyQueueEntries=%u\n", pThis->cReplyQueueEntries);
4101 pHlp->pfnPrintf(pHlp, "cRequestQueueEntries=%u\n", pThis->cRequestQueueEntries);
4102 pHlp->pfnPrintf(pHlp, "cPorts=%u\n", pThis->cPorts);
4103
4104 /*
4105 * Show queue status.
4106 */
4107 pHlp->pfnPrintf(pHlp, "uReplyFreeQueueNextEntryFreeWrite=%u\n", pThis->uReplyFreeQueueNextEntryFreeWrite);
4108 pHlp->pfnPrintf(pHlp, "uReplyFreeQueueNextAddressRead=%u\n", pThis->uReplyFreeQueueNextAddressRead);
4109 pHlp->pfnPrintf(pHlp, "uReplyPostQueueNextEntryFreeWrite=%u\n", pThis->uReplyPostQueueNextEntryFreeWrite);
4110 pHlp->pfnPrintf(pHlp, "uReplyPostQueueNextAddressRead=%u\n", pThis->uReplyPostQueueNextAddressRead);
4111 pHlp->pfnPrintf(pHlp, "uRequestQueueNextEntryFreeWrite=%u\n", pThis->uRequestQueueNextEntryFreeWrite);
4112 pHlp->pfnPrintf(pHlp, "uRequestQueueNextAddressRead=%u\n", pThis->uRequestQueueNextAddressRead);
4113
4114 /*
4115 * Show queue content if verbose
4116 */
4117 if (fVerbose)
4118 {
4119 for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
4120 pHlp->pfnPrintf(pHlp, "RFQ[%u]=%#x\n", i, pThis->pReplyFreeQueueBaseR3[i]);
4121
4122 pHlp->pfnPrintf(pHlp, "\n");
4123
4124 for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
4125 pHlp->pfnPrintf(pHlp, "RPQ[%u]=%#x\n", i, pThis->pReplyPostQueueBaseR3[i]);
4126
4127 pHlp->pfnPrintf(pHlp, "\n");
4128
4129 for (unsigned i = 0; i < pThis->cRequestQueueEntries; i++)
4130 pHlp->pfnPrintf(pHlp, "ReqQ[%u]=%#x\n", i, pThis->pRequestQueueBaseR3[i]);
4131 }
4132
4133 /*
4134 * Print the device status.
4135 */
4136 for (unsigned i = 0; i < pThis->cDeviceStates; i++)
4137 {
4138 PLSILOGICDEVICE pDevice = &pThis->paDeviceStates[i];
4139
4140 pHlp->pfnPrintf(pHlp, "\n");
4141
4142 pHlp->pfnPrintf(pHlp, "Device[%u]: device-attached=%RTbool cOutstandingRequests=%u\n",
4143 i, pDevice->pDrvBase != NULL, pDevice->cOutstandingRequests);
4144 }
4145}
4146
4147/**
4148 * Allocate the queues.
4149 *
4150 * @returns VBox status code.
4151 *
4152 * @param pThis Pointer to the LsiLogic device state.
4153 */
4154static int lsilogicR3QueuesAlloc(PLSILOGICSCSI pThis)
4155{
4156 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
4157 uint32_t cbQueues;
4158
4159 Assert(!pThis->pReplyFreeQueueBaseR3);
4160
4161 cbQueues = 2*pThis->cReplyQueueEntries * sizeof(uint32_t);
4162 cbQueues += pThis->cRequestQueueEntries * sizeof(uint32_t);
4163 int rc = MMHyperAlloc(pVM, cbQueues, 1, MM_TAG_PDM_DEVICE_USER,
4164 (void **)&pThis->pReplyFreeQueueBaseR3);
4165 if (RT_FAILURE(rc))
4166 return VERR_NO_MEMORY;
4167 pThis->pReplyFreeQueueBaseR0 = MMHyperR3ToR0(pVM, (void *)pThis->pReplyFreeQueueBaseR3);
4168 pThis->pReplyFreeQueueBaseRC = MMHyperR3ToRC(pVM, (void *)pThis->pReplyFreeQueueBaseR3);
4169
4170 pThis->pReplyPostQueueBaseR3 = pThis->pReplyFreeQueueBaseR3 + pThis->cReplyQueueEntries;
4171 pThis->pReplyPostQueueBaseR0 = MMHyperR3ToR0(pVM, (void *)pThis->pReplyPostQueueBaseR3);
4172 pThis->pReplyPostQueueBaseRC = MMHyperR3ToRC(pVM, (void *)pThis->pReplyPostQueueBaseR3);
4173
4174 pThis->pRequestQueueBaseR3 = pThis->pReplyPostQueueBaseR3 + pThis->cReplyQueueEntries;
4175 pThis->pRequestQueueBaseR0 = MMHyperR3ToR0(pVM, (void *)pThis->pRequestQueueBaseR3);
4176 pThis->pRequestQueueBaseRC = MMHyperR3ToRC(pVM, (void *)pThis->pRequestQueueBaseR3);
4177
4178 return VINF_SUCCESS;
4179}
4180
4181/**
4182 * Free the hyper memory used or the queues.
4183 *
4184 * @returns nothing.
4185 *
4186 * @param pThis Pointer to the LsiLogic device state.
4187 */
4188static void lsilogicR3QueuesFree(PLSILOGICSCSI pThis)
4189{
4190 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
4191 int rc = VINF_SUCCESS;
4192
4193 AssertPtr(pThis->pReplyFreeQueueBaseR3);
4194
4195 rc = MMHyperFree(pVM, (void *)pThis->pReplyFreeQueueBaseR3);
4196 AssertRC(rc);
4197
4198 pThis->pReplyFreeQueueBaseR3 = NULL;
4199 pThis->pReplyPostQueueBaseR3 = NULL;
4200 pThis->pRequestQueueBaseR3 = NULL;
4201}
4202
4203
4204/* The worker thread. */
4205static DECLCALLBACK(int) lsilogicR3Worker(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4206{
4207 PLSILOGICSCSI pThis = (PLSILOGICSCSI)pThread->pvUser;
4208 int rc = VINF_SUCCESS;
4209
4210 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
4211 return VINF_SUCCESS;
4212
4213 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4214 {
4215 ASMAtomicWriteBool(&pThis->fWrkThreadSleeping, true);
4216 bool fNotificationSent = ASMAtomicXchgBool(&pThis->fNotificationSent, false);
4217 if (!fNotificationSent)
4218 {
4219 Assert(ASMAtomicReadBool(&pThis->fWrkThreadSleeping));
4220 rc = SUPSemEventWaitNoResume(pThis->pSupDrvSession, pThis->hEvtProcess, RT_INDEFINITE_WAIT);
4221 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
4222 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
4223 break;
4224 LogFlowFunc(("Woken up with rc=%Rrc\n", rc));
4225 ASMAtomicWriteBool(&pThis->fNotificationSent, false);
4226 }
4227
4228 ASMAtomicWriteBool(&pThis->fWrkThreadSleeping, false);
4229
4230 /* Check whether there is a BIOS request pending and process it first. */
4231 if (ASMAtomicReadBool(&pThis->fBiosReqPending))
4232 {
4233 rc = lsilogicR3PrepareBiosScsiRequest(pThis);
4234 AssertRC(rc);
4235 ASMAtomicXchgBool(&pThis->fBiosReqPending, false);
4236 }
4237
4238 /* Only process request which arrived before we received the notification. */
4239 uint32_t uRequestQueueNextEntryWrite = ASMAtomicReadU32(&pThis->uRequestQueueNextEntryFreeWrite);
4240
4241 /* Go through the messages now and process them. */
4242 while ( RT_LIKELY(pThis->enmState == LSILOGICSTATE_OPERATIONAL)
4243 && (pThis->uRequestQueueNextAddressRead != uRequestQueueNextEntryWrite))
4244 {
4245 uint32_t u32RequestMessageFrameDesc = pThis->CTX_SUFF(pRequestQueueBase)[pThis->uRequestQueueNextAddressRead];
4246 RTGCPHYS GCPhysMessageFrameAddr = LSILOGIC_RTGCPHYS_FROM_U32(pThis->u32HostMFAHighAddr,
4247 (u32RequestMessageFrameDesc & ~0x07));
4248
4249 PLSILOGICREQ pLsiReq;
4250
4251 /* Get new task state. */
4252 rc = RTMemCacheAllocEx(pThis->hTaskCache, (void **)&pLsiReq);
4253 AssertRC(rc);
4254
4255 pLsiReq->GCPhysMessageFrameAddr = GCPhysMessageFrameAddr;
4256
4257 /* Read the message header from the guest first. */
4258 PDMDevHlpPhysRead(pDevIns, GCPhysMessageFrameAddr, &pLsiReq->GuestRequest, sizeof(MptMessageHdr));
4259
4260 /* Determine the size of the request. */
4261 uint32_t cbRequest = 0;
4262
4263 switch (pLsiReq->GuestRequest.Header.u8Function)
4264 {
4265 case MPT_MESSAGE_HDR_FUNCTION_SCSI_IO_REQUEST:
4266 cbRequest = sizeof(MptSCSIIORequest);
4267 break;
4268 case MPT_MESSAGE_HDR_FUNCTION_SCSI_TASK_MGMT:
4269 cbRequest = sizeof(MptSCSITaskManagementRequest);
4270 break;
4271 case MPT_MESSAGE_HDR_FUNCTION_IOC_INIT:
4272 cbRequest = sizeof(MptIOCInitRequest);
4273 break;
4274 case MPT_MESSAGE_HDR_FUNCTION_IOC_FACTS:
4275 cbRequest = sizeof(MptIOCFactsRequest);
4276 break;
4277 case MPT_MESSAGE_HDR_FUNCTION_CONFIG:
4278 cbRequest = sizeof(MptConfigurationRequest);
4279 break;
4280 case MPT_MESSAGE_HDR_FUNCTION_PORT_FACTS:
4281 cbRequest = sizeof(MptPortFactsRequest);
4282 break;
4283 case MPT_MESSAGE_HDR_FUNCTION_PORT_ENABLE:
4284 cbRequest = sizeof(MptPortEnableRequest);
4285 break;
4286 case MPT_MESSAGE_HDR_FUNCTION_EVENT_NOTIFICATION:
4287 cbRequest = sizeof(MptEventNotificationRequest);
4288 break;
4289 case MPT_MESSAGE_HDR_FUNCTION_EVENT_ACK:
4290 AssertMsgFailed(("todo\n"));
4291 //cbRequest = sizeof(MptEventAckRequest);
4292 break;
4293 case MPT_MESSAGE_HDR_FUNCTION_FW_DOWNLOAD:
4294 cbRequest = sizeof(MptFWDownloadRequest);
4295 break;
4296 case MPT_MESSAGE_HDR_FUNCTION_FW_UPLOAD:
4297 cbRequest = sizeof(MptFWUploadRequest);
4298 break;
4299 default:
4300 AssertMsgFailed(("Unknown function issued %u\n", pLsiReq->GuestRequest.Header.u8Function));
4301 lsilogicSetIOCFaultCode(pThis, LSILOGIC_IOCSTATUS_INVALID_FUNCTION);
4302 }
4303
4304 if (cbRequest != 0)
4305 {
4306 /* Read the complete message frame from guest memory now. */
4307 PDMDevHlpPhysRead(pDevIns, GCPhysMessageFrameAddr, &pLsiReq->GuestRequest, cbRequest);
4308
4309 /* Handle SCSI I/O requests now. */
4310 if (pLsiReq->GuestRequest.Header.u8Function == MPT_MESSAGE_HDR_FUNCTION_SCSI_IO_REQUEST)
4311 {
4312 rc = lsilogicR3ProcessSCSIIORequest(pThis, pLsiReq);
4313 AssertRC(rc);
4314 }
4315 else
4316 {
4317 MptReplyUnion Reply;
4318 rc = lsilogicR3ProcessMessageRequest(pThis, &pLsiReq->GuestRequest.Header, &Reply);
4319 AssertRC(rc);
4320 RTMemCacheFree(pThis->hTaskCache, pLsiReq);
4321 }
4322
4323 pThis->uRequestQueueNextAddressRead++;
4324 pThis->uRequestQueueNextAddressRead %= pThis->cRequestQueueEntries;
4325 }
4326 } /* While request frames available. */
4327 } /* While running */
4328
4329 return VINF_SUCCESS;
4330}
4331
4332
4333/**
4334 * Unblock the worker thread so it can respond to a state change.
4335 *
4336 * @returns VBox status code.
4337 * @param pDevIns The pcnet device instance.
4338 * @param pThread The send thread.
4339 */
4340static DECLCALLBACK(int) lsilogicR3WorkerWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4341{
4342 RT_NOREF(pThread);
4343 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4344 return SUPSemEventSignal(pThis->pSupDrvSession, pThis->hEvtProcess);
4345}
4346
4347
4348/**
4349 * Kicks the controller to process pending tasks after the VM was resumed
4350 * or loaded from a saved state.
4351 *
4352 * @returns nothing.
4353 * @param pThis Pointer to the LsiLogic device state.
4354 */
4355static void lsilogicR3Kick(PLSILOGICSCSI pThis)
4356{
4357 if ( pThis->VBoxSCSI.fBusy
4358 && !pThis->fBiosReqPending)
4359 pThis->fBiosReqPending = true;
4360
4361 if (pThis->fNotificationSent)
4362 {
4363 /* Send a notifier to the PDM queue that there are pending requests. */
4364 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pNotificationQueue));
4365 AssertMsg(pItem, ("Allocating item for queue failed\n"));
4366 PDMQueueInsert(pThis->CTX_SUFF(pNotificationQueue), (PPDMQUEUEITEMCORE)pItem);
4367 }
4368}
4369
4370
4371/*
4372 * Saved state.
4373 */
4374
4375/**
4376 * @callback_method_impl{FNSSMDEVLIVEEXEC}
4377 */
4378static DECLCALLBACK(int) lsilogicR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
4379{
4380 RT_NOREF(uPass);
4381 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4382
4383 SSMR3PutU32(pSSM, pThis->enmCtrlType);
4384 SSMR3PutU32(pSSM, pThis->cDeviceStates);
4385 SSMR3PutU32(pSSM, pThis->cPorts);
4386
4387 /* Save the device config. */
4388 for (unsigned i = 0; i < pThis->cDeviceStates; i++)
4389 SSMR3PutBool(pSSM, pThis->paDeviceStates[i].pDrvBase != NULL);
4390
4391 return VINF_SSM_DONT_CALL_AGAIN;
4392}
4393
4394/**
4395 * @callback_method_impl{FNSSMDEVSAVEEXEC}
4396 */
4397static DECLCALLBACK(int) lsilogicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4398{
4399 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4400
4401 /* Every device first. */
4402 lsilogicR3LiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
4403 for (unsigned i = 0; i < pThis->cDeviceStates; i++)
4404 {
4405 PLSILOGICDEVICE pDevice = &pThis->paDeviceStates[i];
4406
4407 AssertMsg(!pDevice->cOutstandingRequests,
4408 ("There are still outstanding requests on this device\n"));
4409 SSMR3PutU32(pSSM, pDevice->cOutstandingRequests);
4410 }
4411 /* Now the main device state. */
4412 SSMR3PutU32 (pSSM, pThis->enmState);
4413 SSMR3PutU32 (pSSM, pThis->enmWhoInit);
4414 SSMR3PutU32 (pSSM, pThis->enmDoorbellState);
4415 SSMR3PutBool (pSSM, pThis->fDiagnosticEnabled);
4416 SSMR3PutBool (pSSM, pThis->fNotificationSent);
4417 SSMR3PutBool (pSSM, pThis->fEventNotificationEnabled);
4418 SSMR3PutU32 (pSSM, pThis->uInterruptMask);
4419 SSMR3PutU32 (pSSM, pThis->uInterruptStatus);
4420 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMessage); i++)
4421 SSMR3PutU32 (pSSM, pThis->aMessage[i]);
4422 SSMR3PutU32 (pSSM, pThis->iMessage);
4423 SSMR3PutU32 (pSSM, pThis->cMessage);
4424 SSMR3PutMem (pSSM, &pThis->ReplyBuffer, sizeof(pThis->ReplyBuffer));
4425 SSMR3PutU32 (pSSM, pThis->uNextReplyEntryRead);
4426 SSMR3PutU32 (pSSM, pThis->cReplySize);
4427 SSMR3PutU16 (pSSM, pThis->u16IOCFaultCode);
4428 SSMR3PutU32 (pSSM, pThis->u32HostMFAHighAddr);
4429 SSMR3PutU32 (pSSM, pThis->u32SenseBufferHighAddr);
4430 SSMR3PutU8 (pSSM, pThis->cMaxDevices);
4431 SSMR3PutU8 (pSSM, pThis->cMaxBuses);
4432 SSMR3PutU16 (pSSM, pThis->cbReplyFrame);
4433 SSMR3PutU32 (pSSM, pThis->iDiagnosticAccess);
4434 SSMR3PutU32 (pSSM, pThis->cReplyQueueEntries);
4435 SSMR3PutU32 (pSSM, pThis->cRequestQueueEntries);
4436 SSMR3PutU32 (pSSM, pThis->uReplyFreeQueueNextEntryFreeWrite);
4437 SSMR3PutU32 (pSSM, pThis->uReplyFreeQueueNextAddressRead);
4438 SSMR3PutU32 (pSSM, pThis->uReplyPostQueueNextEntryFreeWrite);
4439 SSMR3PutU32 (pSSM, pThis->uReplyPostQueueNextAddressRead);
4440 SSMR3PutU32 (pSSM, pThis->uRequestQueueNextEntryFreeWrite);
4441 SSMR3PutU32 (pSSM, pThis->uRequestQueueNextAddressRead);
4442
4443 for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
4444 SSMR3PutU32(pSSM, pThis->pReplyFreeQueueBaseR3[i]);
4445 for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
4446 SSMR3PutU32(pSSM, pThis->pReplyPostQueueBaseR3[i]);
4447 for (unsigned i = 0; i < pThis->cRequestQueueEntries; i++)
4448 SSMR3PutU32(pSSM, pThis->pRequestQueueBaseR3[i]);
4449
4450 SSMR3PutU16 (pSSM, pThis->u16NextHandle);
4451
4452 /* Save diagnostic memory register and data regions. */
4453 SSMR3PutU32 (pSSM, pThis->u32DiagMemAddr);
4454 SSMR3PutU32 (pSSM, lsilogicR3MemRegionsCount(pThis));
4455
4456 PLSILOGICMEMREGN pIt = NULL;
4457 RTListForEach(&pThis->ListMemRegns, pIt, LSILOGICMEMREGN, NodeList)
4458 {
4459 SSMR3PutU32(pSSM, pIt->u32AddrStart);
4460 SSMR3PutU32(pSSM, pIt->u32AddrEnd);
4461 SSMR3PutMem(pSSM, &pIt->au32Data[0], (pIt->u32AddrEnd - pIt->u32AddrStart + 1) * sizeof(uint32_t));
4462 }
4463
4464 PMptConfigurationPagesSupported pPages = pThis->pConfigurationPages;
4465
4466 SSMR3PutMem (pSSM, &pPages->ManufacturingPage0, sizeof(MptConfigurationPageManufacturing0));
4467 SSMR3PutMem (pSSM, &pPages->ManufacturingPage1, sizeof(MptConfigurationPageManufacturing1));
4468 SSMR3PutMem (pSSM, &pPages->ManufacturingPage2, sizeof(MptConfigurationPageManufacturing2));
4469 SSMR3PutMem (pSSM, &pPages->ManufacturingPage3, sizeof(MptConfigurationPageManufacturing3));
4470 SSMR3PutMem (pSSM, &pPages->ManufacturingPage4, sizeof(MptConfigurationPageManufacturing4));
4471 SSMR3PutMem (pSSM, &pPages->ManufacturingPage5, sizeof(MptConfigurationPageManufacturing5));
4472 SSMR3PutMem (pSSM, &pPages->ManufacturingPage6, sizeof(MptConfigurationPageManufacturing6));
4473 SSMR3PutMem (pSSM, &pPages->ManufacturingPage8, sizeof(MptConfigurationPageManufacturing8));
4474 SSMR3PutMem (pSSM, &pPages->ManufacturingPage9, sizeof(MptConfigurationPageManufacturing9));
4475 SSMR3PutMem (pSSM, &pPages->ManufacturingPage10, sizeof(MptConfigurationPageManufacturing10));
4476 SSMR3PutMem (pSSM, &pPages->IOUnitPage0, sizeof(MptConfigurationPageIOUnit0));
4477 SSMR3PutMem (pSSM, &pPages->IOUnitPage1, sizeof(MptConfigurationPageIOUnit1));
4478 SSMR3PutMem (pSSM, &pPages->IOUnitPage2, sizeof(MptConfigurationPageIOUnit2));
4479 SSMR3PutMem (pSSM, &pPages->IOUnitPage3, sizeof(MptConfigurationPageIOUnit3));
4480 SSMR3PutMem (pSSM, &pPages->IOUnitPage4, sizeof(MptConfigurationPageIOUnit4));
4481 SSMR3PutMem (pSSM, &pPages->IOCPage0, sizeof(MptConfigurationPageIOC0));
4482 SSMR3PutMem (pSSM, &pPages->IOCPage1, sizeof(MptConfigurationPageIOC1));
4483 SSMR3PutMem (pSSM, &pPages->IOCPage2, sizeof(MptConfigurationPageIOC2));
4484 SSMR3PutMem (pSSM, &pPages->IOCPage3, sizeof(MptConfigurationPageIOC3));
4485 SSMR3PutMem (pSSM, &pPages->IOCPage4, sizeof(MptConfigurationPageIOC4));
4486 SSMR3PutMem (pSSM, &pPages->IOCPage6, sizeof(MptConfigurationPageIOC6));
4487 SSMR3PutMem (pSSM, &pPages->BIOSPage1, sizeof(MptConfigurationPageBIOS1));
4488 SSMR3PutMem (pSSM, &pPages->BIOSPage2, sizeof(MptConfigurationPageBIOS2));
4489 SSMR3PutMem (pSSM, &pPages->BIOSPage4, sizeof(MptConfigurationPageBIOS4));
4490
4491 /* Device dependent pages */
4492 if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
4493 {
4494 PMptConfigurationPagesSpi pSpiPages = &pPages->u.SpiPages;
4495
4496 SSMR3PutMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage0, sizeof(MptConfigurationPageSCSISPIPort0));
4497 SSMR3PutMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage1, sizeof(MptConfigurationPageSCSISPIPort1));
4498 SSMR3PutMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage2, sizeof(MptConfigurationPageSCSISPIPort2));
4499
4500 for (unsigned i = 0; i < RT_ELEMENTS(pSpiPages->aBuses[0].aDevicePages); i++)
4501 {
4502 SSMR3PutMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage0, sizeof(MptConfigurationPageSCSISPIDevice0));
4503 SSMR3PutMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage1, sizeof(MptConfigurationPageSCSISPIDevice1));
4504 SSMR3PutMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage2, sizeof(MptConfigurationPageSCSISPIDevice2));
4505 SSMR3PutMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage3, sizeof(MptConfigurationPageSCSISPIDevice3));
4506 }
4507 }
4508 else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
4509 {
4510 PMptConfigurationPagesSas pSasPages = &pPages->u.SasPages;
4511
4512 SSMR3PutU32(pSSM, pSasPages->cbManufacturingPage7);
4513 SSMR3PutU32(pSSM, pSasPages->cbSASIOUnitPage0);
4514 SSMR3PutU32(pSSM, pSasPages->cbSASIOUnitPage1);
4515
4516 SSMR3PutMem(pSSM, pSasPages->pManufacturingPage7, pSasPages->cbManufacturingPage7);
4517 SSMR3PutMem(pSSM, pSasPages->pSASIOUnitPage0, pSasPages->cbSASIOUnitPage0);
4518 SSMR3PutMem(pSSM, pSasPages->pSASIOUnitPage1, pSasPages->cbSASIOUnitPage1);
4519
4520 SSMR3PutMem(pSSM, &pSasPages->SASIOUnitPage2, sizeof(MptConfigurationPageSASIOUnit2));
4521 SSMR3PutMem(pSSM, &pSasPages->SASIOUnitPage3, sizeof(MptConfigurationPageSASIOUnit3));
4522
4523 SSMR3PutU32(pSSM, pSasPages->cPHYs);
4524 for (unsigned i = 0; i < pSasPages->cPHYs; i++)
4525 {
4526 SSMR3PutMem(pSSM, &pSasPages->paPHYs[i].SASPHYPage0, sizeof(MptConfigurationPageSASPHY0));
4527 SSMR3PutMem(pSSM, &pSasPages->paPHYs[i].SASPHYPage1, sizeof(MptConfigurationPageSASPHY1));
4528 }
4529
4530 /* The number of devices first. */
4531 SSMR3PutU32(pSSM, pSasPages->cDevices);
4532
4533 PMptSASDevice pCurr = pSasPages->pSASDeviceHead;
4534
4535 while (pCurr)
4536 {
4537 SSMR3PutMem(pSSM, &pCurr->SASDevicePage0, sizeof(MptConfigurationPageSASDevice0));
4538 SSMR3PutMem(pSSM, &pCurr->SASDevicePage1, sizeof(MptConfigurationPageSASDevice1));
4539 SSMR3PutMem(pSSM, &pCurr->SASDevicePage2, sizeof(MptConfigurationPageSASDevice2));
4540
4541 pCurr = pCurr->pNext;
4542 }
4543 }
4544 else
4545 AssertMsgFailed(("Invalid controller type %d\n", pThis->enmCtrlType));
4546
4547 vboxscsiR3SaveExec(&pThis->VBoxSCSI, pSSM);
4548 return SSMR3PutU32(pSSM, UINT32_MAX);
4549}
4550
4551/**
4552 * @callback_method_impl{FNSSMDEVLOADDONE}
4553 */
4554static DECLCALLBACK(int) lsilogicR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4555{
4556 RT_NOREF(pSSM);
4557 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4558
4559 lsilogicR3Kick(pThis);
4560 return VINF_SUCCESS;
4561}
4562
4563/**
4564 * @callback_method_impl{FNSSMDEVLOADEXEC}
4565 */
4566static DECLCALLBACK(int) lsilogicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4567{
4568 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4569 int rc;
4570
4571 if ( uVersion != LSILOGIC_SAVED_STATE_VERSION
4572 && uVersion != LSILOGIC_SAVED_STATE_VERSION_PRE_DIAG_MEM
4573 && uVersion != LSILOGIC_SAVED_STATE_VERSION_BOOL_DOORBELL
4574 && uVersion != LSILOGIC_SAVED_STATE_VERSION_PRE_SAS
4575 && uVersion != LSILOGIC_SAVED_STATE_VERSION_VBOX_30)
4576 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
4577
4578 /* device config */
4579 if (uVersion > LSILOGIC_SAVED_STATE_VERSION_PRE_SAS)
4580 {
4581 LSILOGICCTRLTYPE enmCtrlType;
4582 uint32_t cDeviceStates, cPorts;
4583
4584 rc = SSMR3GetU32(pSSM, (uint32_t *)&enmCtrlType);
4585 AssertRCReturn(rc, rc);
4586 rc = SSMR3GetU32(pSSM, &cDeviceStates);
4587 AssertRCReturn(rc, rc);
4588 rc = SSMR3GetU32(pSSM, &cPorts);
4589 AssertRCReturn(rc, rc);
4590
4591 if (enmCtrlType != pThis->enmCtrlType)
4592 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Target config mismatch (Controller type): config=%d state=%d"),
4593 pThis->enmCtrlType, enmCtrlType);
4594 if (cDeviceStates != pThis->cDeviceStates)
4595 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Target config mismatch (Device states): config=%u state=%u"),
4596 pThis->cDeviceStates, cDeviceStates);
4597 if (cPorts != pThis->cPorts)
4598 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Target config mismatch (Ports): config=%u state=%u"),
4599 pThis->cPorts, cPorts);
4600 }
4601 if (uVersion > LSILOGIC_SAVED_STATE_VERSION_VBOX_30)
4602 {
4603 for (unsigned i = 0; i < pThis->cDeviceStates; i++)
4604 {
4605 bool fPresent;
4606 rc = SSMR3GetBool(pSSM, &fPresent);
4607 AssertRCReturn(rc, rc);
4608 if (fPresent != (pThis->paDeviceStates[i].pDrvBase != NULL))
4609 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Target %u config mismatch: config=%RTbool state=%RTbool"),
4610 i, pThis->paDeviceStates[i].pDrvBase != NULL, fPresent);
4611 }
4612 }
4613 if (uPass != SSM_PASS_FINAL)
4614 return VINF_SUCCESS;
4615
4616 /* Every device first. */
4617 for (unsigned i = 0; i < pThis->cDeviceStates; i++)
4618 {
4619 PLSILOGICDEVICE pDevice = &pThis->paDeviceStates[i];
4620
4621 AssertMsg(!pDevice->cOutstandingRequests,
4622 ("There are still outstanding requests on this device\n"));
4623 SSMR3GetU32(pSSM, (uint32_t *)&pDevice->cOutstandingRequests);
4624 }
4625 /* Now the main device state. */
4626 SSMR3GetU32 (pSSM, (uint32_t *)&pThis->enmState);
4627 SSMR3GetU32 (pSSM, (uint32_t *)&pThis->enmWhoInit);
4628 if (uVersion <= LSILOGIC_SAVED_STATE_VERSION_BOOL_DOORBELL)
4629 {
4630 bool fDoorbellInProgress = false;
4631
4632 /*
4633 * The doorbell status flag distinguishes only between
4634 * doorbell not in use or a Function handshake is currently in progress.
4635 */
4636 SSMR3GetBool (pSSM, &fDoorbellInProgress);
4637 if (fDoorbellInProgress)
4638 pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_FN_HANDSHAKE;
4639 else
4640 pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_NOT_IN_USE;
4641 }
4642 else
4643 SSMR3GetU32(pSSM, (uint32_t *)&pThis->enmDoorbellState);
4644 SSMR3GetBool (pSSM, &pThis->fDiagnosticEnabled);
4645 SSMR3GetBool (pSSM, &pThis->fNotificationSent);
4646 SSMR3GetBool (pSSM, &pThis->fEventNotificationEnabled);
4647 SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uInterruptMask);
4648 SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uInterruptStatus);
4649 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMessage); i++)
4650 SSMR3GetU32 (pSSM, &pThis->aMessage[i]);
4651 SSMR3GetU32 (pSSM, &pThis->iMessage);
4652 SSMR3GetU32 (pSSM, &pThis->cMessage);
4653 SSMR3GetMem (pSSM, &pThis->ReplyBuffer, sizeof(pThis->ReplyBuffer));
4654 SSMR3GetU32 (pSSM, &pThis->uNextReplyEntryRead);
4655 SSMR3GetU32 (pSSM, &pThis->cReplySize);
4656 SSMR3GetU16 (pSSM, &pThis->u16IOCFaultCode);
4657 SSMR3GetU32 (pSSM, &pThis->u32HostMFAHighAddr);
4658 SSMR3GetU32 (pSSM, &pThis->u32SenseBufferHighAddr);
4659 SSMR3GetU8 (pSSM, &pThis->cMaxDevices);
4660 SSMR3GetU8 (pSSM, &pThis->cMaxBuses);
4661 SSMR3GetU16 (pSSM, &pThis->cbReplyFrame);
4662 SSMR3GetU32 (pSSM, &pThis->iDiagnosticAccess);
4663
4664 uint32_t cReplyQueueEntries, cRequestQueueEntries;
4665 SSMR3GetU32 (pSSM, &cReplyQueueEntries);
4666 SSMR3GetU32 (pSSM, &cRequestQueueEntries);
4667
4668 if ( cReplyQueueEntries != pThis->cReplyQueueEntries
4669 || cRequestQueueEntries != pThis->cRequestQueueEntries)
4670 {
4671 LogFlow(("Reallocating queues cReplyQueueEntries=%u cRequestQueuEntries=%u\n",
4672 cReplyQueueEntries, cRequestQueueEntries));
4673 lsilogicR3QueuesFree(pThis);
4674 pThis->cReplyQueueEntries = cReplyQueueEntries;
4675 pThis->cRequestQueueEntries = cRequestQueueEntries;
4676 rc = lsilogicR3QueuesAlloc(pThis);
4677 if (RT_FAILURE(rc))
4678 return rc;
4679 }
4680
4681 SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uReplyFreeQueueNextEntryFreeWrite);
4682 SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uReplyFreeQueueNextAddressRead);
4683 SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uReplyPostQueueNextEntryFreeWrite);
4684 SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uReplyPostQueueNextAddressRead);
4685 SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uRequestQueueNextEntryFreeWrite);
4686 SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uRequestQueueNextAddressRead);
4687
4688 PMptConfigurationPagesSupported pPages = pThis->pConfigurationPages;
4689
4690 if (uVersion <= LSILOGIC_SAVED_STATE_VERSION_PRE_SAS)
4691 {
4692 PMptConfigurationPagesSpi pSpiPages = &pPages->u.SpiPages;
4693 MptConfigurationPagesSupported_SSM_V2 ConfigPagesV2;
4694
4695 if (pThis->enmCtrlType != LSILOGICCTRLTYPE_SCSI_SPI)
4696 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: Expected SPI SCSI controller"));
4697
4698 SSMR3GetMem(pSSM, &ConfigPagesV2,
4699 sizeof(MptConfigurationPagesSupported_SSM_V2));
4700
4701 pPages->ManufacturingPage0 = ConfigPagesV2.ManufacturingPage0;
4702 pPages->ManufacturingPage1 = ConfigPagesV2.ManufacturingPage1;
4703 pPages->ManufacturingPage2 = ConfigPagesV2.ManufacturingPage2;
4704 pPages->ManufacturingPage3 = ConfigPagesV2.ManufacturingPage3;
4705 pPages->ManufacturingPage4 = ConfigPagesV2.ManufacturingPage4;
4706 pPages->IOUnitPage0 = ConfigPagesV2.IOUnitPage0;
4707 pPages->IOUnitPage1 = ConfigPagesV2.IOUnitPage1;
4708 pPages->IOUnitPage2 = ConfigPagesV2.IOUnitPage2;
4709 pPages->IOUnitPage3 = ConfigPagesV2.IOUnitPage3;
4710 pPages->IOCPage0 = ConfigPagesV2.IOCPage0;
4711 pPages->IOCPage1 = ConfigPagesV2.IOCPage1;
4712 pPages->IOCPage2 = ConfigPagesV2.IOCPage2;
4713 pPages->IOCPage3 = ConfigPagesV2.IOCPage3;
4714 pPages->IOCPage4 = ConfigPagesV2.IOCPage4;
4715 pPages->IOCPage6 = ConfigPagesV2.IOCPage6;
4716
4717 pSpiPages->aPortPages[0].SCSISPIPortPage0 = ConfigPagesV2.aPortPages[0].SCSISPIPortPage0;
4718 pSpiPages->aPortPages[0].SCSISPIPortPage1 = ConfigPagesV2.aPortPages[0].SCSISPIPortPage1;
4719 pSpiPages->aPortPages[0].SCSISPIPortPage2 = ConfigPagesV2.aPortPages[0].SCSISPIPortPage2;
4720
4721 for (unsigned i = 0; i < RT_ELEMENTS(pPages->u.SpiPages.aBuses[0].aDevicePages); i++)
4722 {
4723 pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage0 = ConfigPagesV2.aBuses[0].aDevicePages[i].SCSISPIDevicePage0;
4724 pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage1 = ConfigPagesV2.aBuses[0].aDevicePages[i].SCSISPIDevicePage1;
4725 pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage2 = ConfigPagesV2.aBuses[0].aDevicePages[i].SCSISPIDevicePage2;
4726 pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage3 = ConfigPagesV2.aBuses[0].aDevicePages[i].SCSISPIDevicePage3;
4727 }
4728 }
4729 else
4730 {
4731 /* Queue content */
4732 for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
4733 SSMR3GetU32(pSSM, (uint32_t *)&pThis->pReplyFreeQueueBaseR3[i]);
4734 for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
4735 SSMR3GetU32(pSSM, (uint32_t *)&pThis->pReplyPostQueueBaseR3[i]);
4736 for (unsigned i = 0; i < pThis->cRequestQueueEntries; i++)
4737 SSMR3GetU32(pSSM, (uint32_t *)&pThis->pRequestQueueBaseR3[i]);
4738
4739 SSMR3GetU16(pSSM, &pThis->u16NextHandle);
4740
4741 if (uVersion > LSILOGIC_SAVED_STATE_VERSION_PRE_DIAG_MEM)
4742 {
4743 uint32_t cMemRegions = 0;
4744
4745 /* Save diagnostic memory register and data regions. */
4746 SSMR3GetU32 (pSSM, &pThis->u32DiagMemAddr);
4747 SSMR3GetU32 (pSSM, &cMemRegions);
4748
4749 while (cMemRegions)
4750 {
4751 uint32_t u32AddrStart = 0;
4752 uint32_t u32AddrEnd = 0;
4753 uint32_t cRegion = 0;
4754 PLSILOGICMEMREGN pRegion = NULL;
4755
4756 SSMR3GetU32(pSSM, &u32AddrStart);
4757 SSMR3GetU32(pSSM, &u32AddrEnd);
4758
4759 cRegion = u32AddrEnd - u32AddrStart + 1;
4760 pRegion = (PLSILOGICMEMREGN)RTMemAllocZ(RT_OFFSETOF(LSILOGICMEMREGN, au32Data[cRegion]));
4761 if (pRegion)
4762 {
4763 pRegion->u32AddrStart = u32AddrStart;
4764 pRegion->u32AddrEnd = u32AddrEnd;
4765 SSMR3GetMem(pSSM, &pRegion->au32Data[0], cRegion * sizeof(uint32_t));
4766 lsilogicR3MemRegionInsert(pThis, pRegion);
4767 pThis->cbMemRegns += cRegion * sizeof(uint32_t);
4768 }
4769 else
4770 {
4771 /* Leave a log message but continue. */
4772 LogRel(("LsiLogic: Out of memory while restoring the state, might not work as expected\n"));
4773 SSMR3Skip(pSSM, cRegion * sizeof(uint32_t));
4774 }
4775 cMemRegions--;
4776 }
4777 }
4778
4779 /* Configuration pages */
4780 SSMR3GetMem(pSSM, &pPages->ManufacturingPage0, sizeof(MptConfigurationPageManufacturing0));
4781 SSMR3GetMem(pSSM, &pPages->ManufacturingPage1, sizeof(MptConfigurationPageManufacturing1));
4782 SSMR3GetMem(pSSM, &pPages->ManufacturingPage2, sizeof(MptConfigurationPageManufacturing2));
4783 SSMR3GetMem(pSSM, &pPages->ManufacturingPage3, sizeof(MptConfigurationPageManufacturing3));
4784 SSMR3GetMem(pSSM, &pPages->ManufacturingPage4, sizeof(MptConfigurationPageManufacturing4));
4785 SSMR3GetMem(pSSM, &pPages->ManufacturingPage5, sizeof(MptConfigurationPageManufacturing5));
4786 SSMR3GetMem(pSSM, &pPages->ManufacturingPage6, sizeof(MptConfigurationPageManufacturing6));
4787 SSMR3GetMem(pSSM, &pPages->ManufacturingPage8, sizeof(MptConfigurationPageManufacturing8));
4788 SSMR3GetMem(pSSM, &pPages->ManufacturingPage9, sizeof(MptConfigurationPageManufacturing9));
4789 SSMR3GetMem(pSSM, &pPages->ManufacturingPage10, sizeof(MptConfigurationPageManufacturing10));
4790 SSMR3GetMem(pSSM, &pPages->IOUnitPage0, sizeof(MptConfigurationPageIOUnit0));
4791 SSMR3GetMem(pSSM, &pPages->IOUnitPage1, sizeof(MptConfigurationPageIOUnit1));
4792 SSMR3GetMem(pSSM, &pPages->IOUnitPage2, sizeof(MptConfigurationPageIOUnit2));
4793 SSMR3GetMem(pSSM, &pPages->IOUnitPage3, sizeof(MptConfigurationPageIOUnit3));
4794 SSMR3GetMem(pSSM, &pPages->IOUnitPage4, sizeof(MptConfigurationPageIOUnit4));
4795 SSMR3GetMem(pSSM, &pPages->IOCPage0, sizeof(MptConfigurationPageIOC0));
4796 SSMR3GetMem(pSSM, &pPages->IOCPage1, sizeof(MptConfigurationPageIOC1));
4797 SSMR3GetMem(pSSM, &pPages->IOCPage2, sizeof(MptConfigurationPageIOC2));
4798 SSMR3GetMem(pSSM, &pPages->IOCPage3, sizeof(MptConfigurationPageIOC3));
4799 SSMR3GetMem(pSSM, &pPages->IOCPage4, sizeof(MptConfigurationPageIOC4));
4800 SSMR3GetMem(pSSM, &pPages->IOCPage6, sizeof(MptConfigurationPageIOC6));
4801 SSMR3GetMem(pSSM, &pPages->BIOSPage1, sizeof(MptConfigurationPageBIOS1));
4802 SSMR3GetMem(pSSM, &pPages->BIOSPage2, sizeof(MptConfigurationPageBIOS2));
4803 SSMR3GetMem(pSSM, &pPages->BIOSPage4, sizeof(MptConfigurationPageBIOS4));
4804
4805 /* Device dependent pages */
4806 if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
4807 {
4808 PMptConfigurationPagesSpi pSpiPages = &pPages->u.SpiPages;
4809
4810 SSMR3GetMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage0, sizeof(MptConfigurationPageSCSISPIPort0));
4811 SSMR3GetMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage1, sizeof(MptConfigurationPageSCSISPIPort1));
4812 SSMR3GetMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage2, sizeof(MptConfigurationPageSCSISPIPort2));
4813
4814 for (unsigned i = 0; i < RT_ELEMENTS(pSpiPages->aBuses[0].aDevicePages); i++)
4815 {
4816 SSMR3GetMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage0, sizeof(MptConfigurationPageSCSISPIDevice0));
4817 SSMR3GetMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage1, sizeof(MptConfigurationPageSCSISPIDevice1));
4818 SSMR3GetMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage2, sizeof(MptConfigurationPageSCSISPIDevice2));
4819 SSMR3GetMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage3, sizeof(MptConfigurationPageSCSISPIDevice3));
4820 }
4821 }
4822 else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
4823 {
4824 uint32_t cbPage0, cbPage1, cPHYs, cbManufacturingPage7;
4825 PMptConfigurationPagesSas pSasPages = &pPages->u.SasPages;
4826
4827 SSMR3GetU32(pSSM, &cbManufacturingPage7);
4828 SSMR3GetU32(pSSM, &cbPage0);
4829 SSMR3GetU32(pSSM, &cbPage1);
4830
4831 if ( (cbPage0 != pSasPages->cbSASIOUnitPage0)
4832 || (cbPage1 != pSasPages->cbSASIOUnitPage1)
4833 || (cbManufacturingPage7 != pSasPages->cbManufacturingPage7))
4834 return VERR_SSM_LOAD_CONFIG_MISMATCH;
4835
4836 AssertPtr(pSasPages->pManufacturingPage7);
4837 AssertPtr(pSasPages->pSASIOUnitPage0);
4838 AssertPtr(pSasPages->pSASIOUnitPage1);
4839
4840 SSMR3GetMem(pSSM, pSasPages->pManufacturingPage7, pSasPages->cbManufacturingPage7);
4841 SSMR3GetMem(pSSM, pSasPages->pSASIOUnitPage0, pSasPages->cbSASIOUnitPage0);
4842 SSMR3GetMem(pSSM, pSasPages->pSASIOUnitPage1, pSasPages->cbSASIOUnitPage1);
4843
4844 SSMR3GetMem(pSSM, &pSasPages->SASIOUnitPage2, sizeof(MptConfigurationPageSASIOUnit2));
4845 SSMR3GetMem(pSSM, &pSasPages->SASIOUnitPage3, sizeof(MptConfigurationPageSASIOUnit3));
4846
4847 SSMR3GetU32(pSSM, &cPHYs);
4848 if (cPHYs != pSasPages->cPHYs)
4849 return VERR_SSM_LOAD_CONFIG_MISMATCH;
4850
4851 AssertPtr(pSasPages->paPHYs);
4852 for (unsigned i = 0; i < pSasPages->cPHYs; i++)
4853 {
4854 SSMR3GetMem(pSSM, &pSasPages->paPHYs[i].SASPHYPage0, sizeof(MptConfigurationPageSASPHY0));
4855 SSMR3GetMem(pSSM, &pSasPages->paPHYs[i].SASPHYPage1, sizeof(MptConfigurationPageSASPHY1));
4856 }
4857
4858 /* The number of devices first. */
4859 SSMR3GetU32(pSSM, &pSasPages->cDevices);
4860
4861 PMptSASDevice pCurr = pSasPages->pSASDeviceHead;
4862
4863 for (unsigned i = 0; i < pSasPages->cDevices; i++)
4864 {
4865 SSMR3GetMem(pSSM, &pCurr->SASDevicePage0, sizeof(MptConfigurationPageSASDevice0));
4866 SSMR3GetMem(pSSM, &pCurr->SASDevicePage1, sizeof(MptConfigurationPageSASDevice1));
4867 SSMR3GetMem(pSSM, &pCurr->SASDevicePage2, sizeof(MptConfigurationPageSASDevice2));
4868
4869 pCurr = pCurr->pNext;
4870 }
4871
4872 Assert(!pCurr);
4873 }
4874 else
4875 AssertMsgFailed(("Invalid controller type %d\n", pThis->enmCtrlType));
4876 }
4877
4878 rc = vboxscsiR3LoadExec(&pThis->VBoxSCSI, pSSM);
4879 if (RT_FAILURE(rc))
4880 {
4881 LogRel(("LsiLogic: Failed to restore BIOS state: %Rrc.\n", rc));
4882 return PDMDEV_SET_ERROR(pDevIns, rc,
4883 N_("LsiLogic: Failed to restore BIOS state\n"));
4884 }
4885
4886 uint32_t u32;
4887 rc = SSMR3GetU32(pSSM, &u32);
4888 if (RT_FAILURE(rc))
4889 return rc;
4890 AssertMsgReturn(u32 == UINT32_MAX, ("%#x\n", u32), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
4891
4892 return VINF_SUCCESS;
4893}
4894
4895
4896/*
4897 * The device level IBASE and LED interfaces.
4898 */
4899
4900/**
4901 * @interface_method_impl{PDMILEDPORTS,pfnQueryInterface, For a SCSI device.}
4902 *
4903 * @remarks Called by the scsi driver, proxying the main calls.
4904 */
4905static DECLCALLBACK(int) lsilogicR3DeviceQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
4906{
4907 PLSILOGICDEVICE pDevice = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, ILed);
4908 if (iLUN == 0)
4909 {
4910 *ppLed = &pDevice->Led;
4911 Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
4912 return VINF_SUCCESS;
4913 }
4914 return VERR_PDM_LUN_NOT_FOUND;
4915}
4916
4917
4918/**
4919 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
4920 */
4921static DECLCALLBACK(void *) lsilogicR3DeviceQueryInterface(PPDMIBASE pInterface, const char *pszIID)
4922{
4923 PLSILOGICDEVICE pDevice = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, IBase);
4924
4925 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevice->IBase);
4926 PDMIBASE_RETURN_INTERFACE(pszIID, PDMISCSIPORT, &pDevice->ISCSIPort);
4927 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pDevice->ILed);
4928 return NULL;
4929}
4930
4931
4932/*
4933 * The controller level IBASE and LED interfaces.
4934 */
4935
4936/**
4937 * Gets the pointer to the status LED of a unit.
4938 *
4939 * @returns VBox status code.
4940 * @param pInterface Pointer to the interface structure containing the called function pointer.
4941 * @param iLUN The unit which status LED we desire.
4942 * @param ppLed Where to store the LED pointer.
4943 */
4944static DECLCALLBACK(int) lsilogicR3StatusQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
4945{
4946 PLSILOGICSCSI pThis = RT_FROM_MEMBER(pInterface, LSILOGICSCSI, ILeds);
4947 if (iLUN < pThis->cDeviceStates)
4948 {
4949 *ppLed = &pThis->paDeviceStates[iLUN].Led;
4950 Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
4951 return VINF_SUCCESS;
4952 }
4953 return VERR_PDM_LUN_NOT_FOUND;
4954}
4955
4956/**
4957 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
4958 */
4959static DECLCALLBACK(void *) lsilogicR3StatusQueryInterface(PPDMIBASE pInterface, const char *pszIID)
4960{
4961 PLSILOGICSCSI pThis = RT_FROM_MEMBER(pInterface, LSILOGICSCSI, IBase);
4962 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
4963 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
4964 return NULL;
4965}
4966
4967
4968/*
4969 * The PDM device interface and some helpers.
4970 */
4971
4972/**
4973 * Checks if all asynchronous I/O is finished.
4974 *
4975 * Used by lsilogicR3Reset, lsilogicR3Suspend and lsilogicR3PowerOff.
4976 *
4977 * @returns true if quiesced, false if busy.
4978 * @param pDevIns The device instance.
4979 */
4980static bool lsilogicR3AllAsyncIOIsFinished(PPDMDEVINS pDevIns)
4981{
4982 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4983
4984 for (uint32_t i = 0; i < pThis->cDeviceStates; i++)
4985 {
4986 PLSILOGICDEVICE pThisDevice = &pThis->paDeviceStates[i];
4987 if (pThisDevice->pDrvBase)
4988 {
4989 if (pThisDevice->cOutstandingRequests != 0)
4990 return false;
4991 }
4992 }
4993
4994 return true;
4995}
4996
4997/**
4998 * @callback_method_impl{FNPDMDEVASYNCNOTIFY,
4999 * Callback employed by lsilogicR3Suspend and lsilogicR3PowerOff.}
5000 */
5001static DECLCALLBACK(bool) lsilogicR3IsAsyncSuspendOrPowerOffDone(PPDMDEVINS pDevIns)
5002{
5003 if (!lsilogicR3AllAsyncIOIsFinished(pDevIns))
5004 return false;
5005
5006 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5007 ASMAtomicWriteBool(&pThis->fSignalIdle, false);
5008 return true;
5009}
5010
5011/**
5012 * Common worker for ahciR3Suspend and ahciR3PowerOff.
5013 */
5014static void lsilogicR3SuspendOrPowerOff(PPDMDEVINS pDevIns)
5015{
5016 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5017
5018 ASMAtomicWriteBool(&pThis->fSignalIdle, true);
5019 if (!lsilogicR3AllAsyncIOIsFinished(pDevIns))
5020 PDMDevHlpSetAsyncNotification(pDevIns, lsilogicR3IsAsyncSuspendOrPowerOffDone);
5021 else
5022 {
5023 ASMAtomicWriteBool(&pThis->fSignalIdle, false);
5024
5025 AssertMsg(!pThis->fNotificationSent, ("The PDM Queue should be empty at this point\n"));
5026
5027 if (pThis->fRedo)
5028 {
5029 /*
5030 * We have tasks which we need to redo. Put the message frame addresses
5031 * into the request queue (we save the requests).
5032 * Guest execution is suspended at this point so there is no race between us and
5033 * lsilogicRegisterWrite.
5034 */
5035 PLSILOGICREQ pLsiReq = pThis->pTasksRedoHead;
5036
5037 pThis->pTasksRedoHead = NULL;
5038
5039 while (pLsiReq)
5040 {
5041 PLSILOGICREQ pFree;
5042
5043 if (!pLsiReq->fBIOS)
5044 {
5045 /* Write only the lower 32bit part of the address. */
5046 ASMAtomicWriteU32(&pThis->CTX_SUFF(pRequestQueueBase)[pThis->uRequestQueueNextEntryFreeWrite],
5047 pLsiReq->GCPhysMessageFrameAddr & UINT32_C(0xffffffff));
5048
5049 pThis->uRequestQueueNextEntryFreeWrite++;
5050 pThis->uRequestQueueNextEntryFreeWrite %= pThis->cRequestQueueEntries;
5051 }
5052 else
5053 {
5054 AssertMsg(!pLsiReq->pRedoNext, ("Only one BIOS task can be active!\n"));
5055 vboxscsiSetRequestRedo(&pThis->VBoxSCSI, &pLsiReq->PDMScsiRequest);
5056 }
5057
5058 pThis->fNotificationSent = true;
5059
5060 pFree = pLsiReq;
5061 pLsiReq = pLsiReq->pRedoNext;
5062
5063 RTMemCacheFree(pThis->hTaskCache, pFree);
5064 }
5065 pThis->fRedo = false;
5066 }
5067 }
5068}
5069
5070/**
5071 * @interface_method_impl{PDMDEVREG,pfnSuspend}
5072 */
5073static DECLCALLBACK(void) lsilogicR3Suspend(PPDMDEVINS pDevIns)
5074{
5075 Log(("lsilogicR3Suspend\n"));
5076 lsilogicR3SuspendOrPowerOff(pDevIns);
5077}
5078
5079/**
5080 * @interface_method_impl{PDMDEVREG,pfnResume}
5081 */
5082static DECLCALLBACK(void) lsilogicR3Resume(PPDMDEVINS pDevIns)
5083{
5084 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5085
5086 Log(("lsilogicR3Resume\n"));
5087
5088 lsilogicR3Kick(pThis);
5089}
5090
5091/**
5092 * @interface_method_impl{PDMDEVREG,pfnDetach}
5093 *
5094 * One harddisk at one port has been unplugged.
5095 * The VM is suspended at this point.
5096 */
5097static DECLCALLBACK(void) lsilogicR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
5098{
5099 RT_NOREF(fFlags);
5100 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5101 PLSILOGICDEVICE pDevice = &pThis->paDeviceStates[iLUN];
5102
5103 if (iLUN >= pThis->cDeviceStates)
5104 return;
5105
5106 AssertMsg(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
5107 ("LsiLogic: Device does not support hotplugging\n"));
5108
5109 Log(("%s:\n", __FUNCTION__));
5110
5111 /*
5112 * Zero some important members.
5113 */
5114 pDevice->pDrvBase = NULL;
5115 pDevice->pDrvSCSIConnector = NULL;
5116}
5117
5118/**
5119 * @interface_method_impl{PDMDEVREG,pfnAttach}
5120 */
5121static DECLCALLBACK(int) lsilogicR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
5122{
5123 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5124 PLSILOGICDEVICE pDevice = &pThis->paDeviceStates[iLUN];
5125 int rc;
5126
5127 if (iLUN >= pThis->cDeviceStates)
5128 return VERR_PDM_LUN_NOT_FOUND;
5129
5130 AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
5131 ("LsiLogic: Device does not support hotplugging\n"),
5132 VERR_INVALID_PARAMETER);
5133
5134 /* the usual paranoia */
5135 AssertRelease(!pDevice->pDrvBase);
5136 AssertRelease(!pDevice->pDrvSCSIConnector);
5137 Assert(pDevice->iLUN == iLUN);
5138
5139 /*
5140 * Try attach the block device and get the interfaces,
5141 * required as well as optional.
5142 */
5143 rc = PDMDevHlpDriverAttach(pDevIns, pDevice->iLUN, &pDevice->IBase, &pDevice->pDrvBase, NULL);
5144 if (RT_SUCCESS(rc))
5145 {
5146 /* Get SCSI connector interface. */
5147 pDevice->pDrvSCSIConnector = PDMIBASE_QUERY_INTERFACE(pDevice->pDrvBase, PDMISCSICONNECTOR);
5148 AssertMsgReturn(pDevice->pDrvSCSIConnector, ("Missing SCSI interface below\n"), VERR_PDM_MISSING_INTERFACE);
5149 }
5150 else
5151 AssertMsgFailed(("Failed to attach LUN#%d. rc=%Rrc\n", pDevice->iLUN, rc));
5152
5153 if (RT_FAILURE(rc))
5154 {
5155 pDevice->pDrvBase = NULL;
5156 pDevice->pDrvSCSIConnector = NULL;
5157 }
5158 return rc;
5159}
5160
5161/**
5162 * Common reset worker.
5163 *
5164 * @param pDevIns The device instance data.
5165 */
5166static void lsilogicR3ResetCommon(PPDMDEVINS pDevIns)
5167{
5168 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5169 int rc;
5170
5171 rc = lsilogicR3HardReset(pThis);
5172 AssertRC(rc);
5173
5174 vboxscsiInitialize(&pThis->VBoxSCSI);
5175}
5176
5177/**
5178 * @callback_method_impl{FNPDMDEVASYNCNOTIFY,
5179 * Callback employed by lsilogicR3Reset.}
5180 */
5181static DECLCALLBACK(bool) lsilogicR3IsAsyncResetDone(PPDMDEVINS pDevIns)
5182{
5183 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5184
5185 if (!lsilogicR3AllAsyncIOIsFinished(pDevIns))
5186 return false;
5187 ASMAtomicWriteBool(&pThis->fSignalIdle, false);
5188
5189 lsilogicR3ResetCommon(pDevIns);
5190 return true;
5191}
5192
5193/**
5194 * @interface_method_impl{PDMDEVREG,pfnReset}
5195 */
5196static DECLCALLBACK(void) lsilogicR3Reset(PPDMDEVINS pDevIns)
5197{
5198 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5199
5200 ASMAtomicWriteBool(&pThis->fSignalIdle, true);
5201 if (!lsilogicR3AllAsyncIOIsFinished(pDevIns))
5202 PDMDevHlpSetAsyncNotification(pDevIns, lsilogicR3IsAsyncResetDone);
5203 else
5204 {
5205 ASMAtomicWriteBool(&pThis->fSignalIdle, false);
5206 lsilogicR3ResetCommon(pDevIns);
5207 }
5208}
5209
5210/**
5211 * @interface_method_impl{PDMDEVREG,pfnRelocate}
5212 */
5213static DECLCALLBACK(void) lsilogicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
5214{
5215 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5216
5217 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5218 pThis->pNotificationQueueRC = PDMQueueRCPtr(pThis->pNotificationQueueR3);
5219
5220 /* Relocate queues. */
5221 pThis->pReplyFreeQueueBaseRC += offDelta;
5222 pThis->pReplyPostQueueBaseRC += offDelta;
5223 pThis->pRequestQueueBaseRC += offDelta;
5224}
5225
5226/**
5227 * @interface_method_impl{PDMDEVREG,pfnPowerOff}
5228 */
5229static DECLCALLBACK(void) lsilogicR3PowerOff(PPDMDEVINS pDevIns)
5230{
5231 Log(("lsilogicR3PowerOff\n"));
5232 lsilogicR3SuspendOrPowerOff(pDevIns);
5233}
5234
5235/**
5236 * @interface_method_impl{PDMDEVREG,pfnDestruct}
5237 */
5238static DECLCALLBACK(int) lsilogicR3Destruct(PPDMDEVINS pDevIns)
5239{
5240 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5241 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
5242
5243 PDMR3CritSectDelete(&pThis->ReplyFreeQueueCritSect);
5244 PDMR3CritSectDelete(&pThis->ReplyPostQueueCritSect);
5245
5246 RTMemFree(pThis->paDeviceStates);
5247 pThis->paDeviceStates = NULL;
5248
5249 /* Destroy task cache. */
5250 if (pThis->hTaskCache != NIL_RTMEMCACHE)
5251 {
5252 int rc = RTMemCacheDestroy(pThis->hTaskCache); AssertRC(rc);
5253 pThis->hTaskCache = NIL_RTMEMCACHE;
5254 }
5255
5256 if (pThis->hEvtProcess != NIL_SUPSEMEVENT)
5257 {
5258 SUPSemEventClose(pThis->pSupDrvSession, pThis->hEvtProcess);
5259 pThis->hEvtProcess = NIL_SUPSEMEVENT;
5260 }
5261
5262 lsilogicR3ConfigurationPagesFree(pThis);
5263 lsilogicR3MemRegionsFree(pThis);
5264
5265 return VINF_SUCCESS;
5266}
5267
5268/**
5269 * @interface_method_impl{PDMDEVREG,pfnConstruct}
5270 */
5271static DECLCALLBACK(int) lsilogicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
5272{
5273 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5274 int rc = VINF_SUCCESS;
5275 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5276
5277 /*
5278 * Initialize enought of the state to make the destructure not trip up.
5279 */
5280 pThis->hTaskCache = NIL_RTMEMCACHE;
5281 pThis->hEvtProcess = NIL_SUPSEMEVENT;
5282 pThis->fBiosReqPending = false;
5283 RTListInit(&pThis->ListMemRegns);
5284
5285 /*
5286 * Validate and read configuration.
5287 */
5288 rc = CFGMR3AreValuesValid(pCfg, "GCEnabled\0"
5289 "R0Enabled\0"
5290 "ReplyQueueDepth\0"
5291 "RequestQueueDepth\0"
5292 "ControllerType\0"
5293 "NumPorts\0"
5294 "Bootable\0");
5295 if (RT_FAILURE(rc))
5296 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
5297 N_("LsiLogic configuration error: unknown option specified"));
5298 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &pThis->fGCEnabled, true);
5299 if (RT_FAILURE(rc))
5300 return PDMDEV_SET_ERROR(pDevIns, rc,
5301 N_("LsiLogic configuration error: failed to read GCEnabled as boolean"));
5302 Log(("%s: fGCEnabled=%d\n", __FUNCTION__, pThis->fGCEnabled));
5303
5304 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, true);
5305 if (RT_FAILURE(rc))
5306 return PDMDEV_SET_ERROR(pDevIns, rc,
5307 N_("LsiLogic configuration error: failed to read R0Enabled as boolean"));
5308 Log(("%s: fR0Enabled=%d\n", __FUNCTION__, pThis->fR0Enabled));
5309
5310 rc = CFGMR3QueryU32Def(pCfg, "ReplyQueueDepth",
5311 &pThis->cReplyQueueEntries,
5312 LSILOGICSCSI_REPLY_QUEUE_DEPTH_DEFAULT);
5313 if (RT_FAILURE(rc))
5314 return PDMDEV_SET_ERROR(pDevIns, rc,
5315 N_("LsiLogic configuration error: failed to read ReplyQueue as integer"));
5316 Log(("%s: ReplyQueueDepth=%u\n", __FUNCTION__, pThis->cReplyQueueEntries));
5317
5318 rc = CFGMR3QueryU32Def(pCfg, "RequestQueueDepth",
5319 &pThis->cRequestQueueEntries,
5320 LSILOGICSCSI_REQUEST_QUEUE_DEPTH_DEFAULT);
5321 if (RT_FAILURE(rc))
5322 return PDMDEV_SET_ERROR(pDevIns, rc,
5323 N_("LsiLogic configuration error: failed to read RequestQueue as integer"));
5324 Log(("%s: RequestQueueDepth=%u\n", __FUNCTION__, pThis->cRequestQueueEntries));
5325
5326 char *pszCtrlType;
5327 rc = CFGMR3QueryStringAllocDef(pCfg, "ControllerType",
5328 &pszCtrlType, LSILOGICSCSI_PCI_SPI_CTRLNAME);
5329 if (RT_FAILURE(rc))
5330 return PDMDEV_SET_ERROR(pDevIns, rc,
5331 N_("LsiLogic configuration error: failed to read ControllerType as string"));
5332 Log(("%s: ControllerType=%s\n", __FUNCTION__, pszCtrlType));
5333
5334 rc = lsilogicR3GetCtrlTypeFromString(pThis, pszCtrlType);
5335 MMR3HeapFree(pszCtrlType);
5336
5337 char szDevTag[20];
5338 RTStrPrintf(szDevTag, sizeof(szDevTag), "LSILOGIC%s-%u",
5339 pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI ? "SPI" : "SAS",
5340 iInstance);
5341
5342
5343 if (RT_FAILURE(rc))
5344 return PDMDEV_SET_ERROR(pDevIns, rc,
5345 N_("LsiLogic configuration error: failed to determine controller type from string"));
5346
5347 rc = CFGMR3QueryU8(pCfg, "NumPorts",
5348 &pThis->cPorts);
5349 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
5350 {
5351 if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
5352 pThis->cPorts = LSILOGICSCSI_PCI_SPI_PORTS_MAX;
5353 else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
5354 pThis->cPorts = LSILOGICSCSI_PCI_SAS_PORTS_DEFAULT;
5355 else
5356 AssertMsgFailed(("Invalid controller type: %d\n", pThis->enmCtrlType));
5357 }
5358 else if (RT_FAILURE(rc))
5359 return PDMDEV_SET_ERROR(pDevIns, rc,
5360 N_("LsiLogic configuration error: failed to read NumPorts as integer"));
5361
5362 bool fBootable;
5363 rc = CFGMR3QueryBoolDef(pCfg, "Bootable", &fBootable, true);
5364 if (RT_FAILURE(rc))
5365 return PDMDEV_SET_ERROR(pDevIns, rc,
5366 N_("LsiLogic configuration error: failed to read Bootable as boolean"));
5367 Log(("%s: Bootable=%RTbool\n", __FUNCTION__, fBootable));
5368
5369 /* Init static parts. */
5370 PCIDevSetVendorId(&pThis->PciDev, LSILOGICSCSI_PCI_VENDOR_ID); /* LsiLogic */
5371
5372 if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
5373 {
5374 PCIDevSetDeviceId (&pThis->PciDev, LSILOGICSCSI_PCI_SPI_DEVICE_ID); /* LSI53C1030 */
5375 PCIDevSetSubSystemVendorId(&pThis->PciDev, LSILOGICSCSI_PCI_SPI_SUBSYSTEM_VENDOR_ID);
5376 PCIDevSetSubSystemId (&pThis->PciDev, LSILOGICSCSI_PCI_SPI_SUBSYSTEM_ID);
5377 }
5378 else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
5379 {
5380 PCIDevSetDeviceId (&pThis->PciDev, LSILOGICSCSI_PCI_SAS_DEVICE_ID); /* SAS1068 */
5381 PCIDevSetSubSystemVendorId(&pThis->PciDev, LSILOGICSCSI_PCI_SAS_SUBSYSTEM_VENDOR_ID);
5382 PCIDevSetSubSystemId (&pThis->PciDev, LSILOGICSCSI_PCI_SAS_SUBSYSTEM_ID);
5383 }
5384 else
5385 AssertMsgFailed(("Invalid controller type: %d\n", pThis->enmCtrlType));
5386
5387 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* SCSI */
5388 PCIDevSetClassSub (&pThis->PciDev, 0x00); /* SCSI */
5389 PCIDevSetClassBase (&pThis->PciDev, 0x01); /* Mass storage */
5390 PCIDevSetInterruptPin(&pThis->PciDev, 0x01); /* Interrupt pin A */
5391
5392# ifdef VBOX_WITH_MSI_DEVICES
5393 PCIDevSetStatus(&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST);
5394 PCIDevSetCapabilityList(&pThis->PciDev, 0x80);
5395# endif
5396
5397 pThis->pDevInsR3 = pDevIns;
5398 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
5399 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5400 pThis->pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
5401 pThis->IBase.pfnQueryInterface = lsilogicR3StatusQueryInterface;
5402 pThis->ILeds.pfnQueryStatusLed = lsilogicR3StatusQueryStatusLed;
5403
5404 /*
5405 * Create critical sections protecting the reply post and free queues.
5406 * Note! We do our own syncronization, so NOP the default crit sect for the device.
5407 */
5408 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
5409 AssertRCReturn(rc, rc);
5410
5411 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->ReplyFreeQueueCritSect, RT_SRC_POS, "%sRFQ", szDevTag);
5412 if (RT_FAILURE(rc))
5413 return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic: cannot create critical section for reply free queue"));
5414
5415 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->ReplyPostQueueCritSect, RT_SRC_POS, "%sRPQ", szDevTag);
5416 if (RT_FAILURE(rc))
5417 return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic: cannot create critical section for reply post queue"));
5418
5419 /*
5420 * Register the PCI device, it's I/O regions.
5421 */
5422 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
5423 if (RT_FAILURE(rc))
5424 return rc;
5425
5426# ifdef VBOX_WITH_MSI_DEVICES
5427 PDMMSIREG MsiReg;
5428 RT_ZERO(MsiReg);
5429 /* use this code for MSI-X support */
5430# if 0
5431 MsiReg.cMsixVectors = 1;
5432 MsiReg.iMsixCapOffset = 0x80;
5433 MsiReg.iMsixNextOffset = 0x00;
5434 MsiReg.iMsixBar = 3;
5435# else
5436 MsiReg.cMsiVectors = 1;
5437 MsiReg.iMsiCapOffset = 0x80;
5438 MsiReg.iMsiNextOffset = 0x00;
5439# endif
5440 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
5441 if (RT_FAILURE (rc))
5442 {
5443 /* That's OK, we can work without MSI */
5444 PCIDevSetCapabilityList(&pThis->PciDev, 0x0);
5445 }
5446# endif
5447
5448 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, LSILOGIC_PCI_SPACE_IO_SIZE, PCI_ADDRESS_SPACE_IO, lsilogicR3Map);
5449 if (RT_FAILURE(rc))
5450 return rc;
5451
5452 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 1, LSILOGIC_PCI_SPACE_MEM_SIZE, PCI_ADDRESS_SPACE_MEM, lsilogicR3Map);
5453 if (RT_FAILURE(rc))
5454 return rc;
5455
5456 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 2, LSILOGIC_PCI_SPACE_MEM_SIZE, PCI_ADDRESS_SPACE_MEM, lsilogicR3Map);
5457 if (RT_FAILURE(rc))
5458 return rc;
5459
5460 /* Initialize task queue. (Need two items to handle SMP guest concurrency.) */
5461 char szTaggedText[64];
5462 RTStrPrintf(szTaggedText, sizeof(szTaggedText), "%s-Task", szDevTag);
5463 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 2, 0,
5464 lsilogicR3NotifyQueueConsumer, true,
5465 szTaggedText,
5466 &pThis->pNotificationQueueR3);
5467 if (RT_FAILURE(rc))
5468 return rc;
5469 pThis->pNotificationQueueR0 = PDMQueueR0Ptr(pThis->pNotificationQueueR3);
5470 pThis->pNotificationQueueRC = PDMQueueRCPtr(pThis->pNotificationQueueR3);
5471
5472 /*
5473 * We need one entry free in the queue.
5474 */
5475 pThis->cReplyQueueEntries++;
5476 pThis->cRequestQueueEntries++;
5477
5478 /*
5479 * Allocate memory for the queues.
5480 */
5481 rc = lsilogicR3QueuesAlloc(pThis);
5482 if (RT_FAILURE(rc))
5483 return rc;
5484
5485 /*
5486 * Allocate task cache.
5487 */
5488 rc = RTMemCacheCreate(&pThis->hTaskCache, sizeof(LSILOGICREQ), 0, UINT32_MAX,
5489 NULL, NULL, NULL, 0);
5490 if (RT_FAILURE(rc))
5491 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Cannot create task cache"));
5492
5493 if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
5494 pThis->cDeviceStates = pThis->cPorts * LSILOGICSCSI_PCI_SPI_DEVICES_PER_BUS_MAX;
5495 else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
5496 pThis->cDeviceStates = pThis->cPorts * LSILOGICSCSI_PCI_SAS_DEVICES_PER_PORT_MAX;
5497 else
5498 AssertMsgFailed(("Invalid controller type: %d\n", pThis->enmCtrlType));
5499
5500 /*
5501 * Create event semaphore and worker thread.
5502 */
5503 rc = PDMDevHlpThreadCreate(pDevIns, &pThis->pThreadWrk, pThis, lsilogicR3Worker,
5504 lsilogicR3WorkerWakeUp, 0, RTTHREADTYPE_IO, szDevTag);
5505 if (RT_FAILURE(rc))
5506 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
5507 N_("LsiLogic: Failed to create worker thread %s"), szDevTag);
5508
5509 rc = SUPSemEventCreate(pThis->pSupDrvSession, &pThis->hEvtProcess);
5510 if (RT_FAILURE(rc))
5511 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
5512 N_("LsiLogic: Failed to create SUP event semaphore"));
5513
5514 /*
5515 * Allocate device states.
5516 */
5517 pThis->paDeviceStates = (PLSILOGICDEVICE)RTMemAllocZ(sizeof(LSILOGICDEVICE) * pThis->cDeviceStates);
5518 if (!pThis->paDeviceStates)
5519 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to allocate memory for device states"));
5520
5521 for (unsigned i = 0; i < pThis->cDeviceStates; i++)
5522 {
5523 char szName[24];
5524 PLSILOGICDEVICE pDevice = &pThis->paDeviceStates[i];
5525
5526 /* Initialize static parts of the device. */
5527 pDevice->iLUN = i;
5528 pDevice->pLsiLogicR3 = pThis;
5529 pDevice->Led.u32Magic = PDMLED_MAGIC;
5530 pDevice->IBase.pfnQueryInterface = lsilogicR3DeviceQueryInterface;
5531 pDevice->ISCSIPort.pfnSCSIRequestCompleted = lsilogicR3DeviceSCSIRequestCompleted;
5532 pDevice->ISCSIPort.pfnQueryDeviceLocation = lsilogicR3QueryDeviceLocation;
5533 pDevice->ILed.pfnQueryStatusLed = lsilogicR3DeviceQueryStatusLed;
5534
5535 RTStrPrintf(szName, sizeof(szName), "Device%u", i);
5536
5537 /* Attach SCSI driver. */
5538 rc = PDMDevHlpDriverAttach(pDevIns, pDevice->iLUN, &pDevice->IBase, &pDevice->pDrvBase, szName);
5539 if (RT_SUCCESS(rc))
5540 {
5541 /* Get SCSI connector interface. */
5542 pDevice->pDrvSCSIConnector = PDMIBASE_QUERY_INTERFACE(pDevice->pDrvBase, PDMISCSICONNECTOR);
5543 AssertMsgReturn(pDevice->pDrvSCSIConnector, ("Missing SCSI interface below\n"), VERR_PDM_MISSING_INTERFACE);
5544 }
5545 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5546 {
5547 pDevice->pDrvBase = NULL;
5548 rc = VINF_SUCCESS;
5549 Log(("LsiLogic: no driver attached to device %s\n", szName));
5550 }
5551 else
5552 {
5553 AssertLogRelMsgFailed(("LsiLogic: Failed to attach %s\n", szName));
5554 return rc;
5555 }
5556 }
5557
5558 /*
5559 * Attach status driver (optional).
5560 */
5561 PPDMIBASE pBase;
5562 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThis->IBase, &pBase, "Status Port");
5563 if (RT_SUCCESS(rc))
5564 pThis->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
5565 else if (rc != VERR_PDM_NO_ATTACHED_DRIVER)
5566 {
5567 AssertMsgFailed(("Failed to attach to status driver. rc=%Rrc\n", rc));
5568 return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic cannot attach to status driver"));
5569 }
5570
5571 /* Initialize the SCSI emulation for the BIOS. */
5572 rc = vboxscsiInitialize(&pThis->VBoxSCSI);
5573 AssertRC(rc);
5574
5575 /*
5576 * Register I/O port space in ISA region for BIOS access
5577 * if the controller is marked as bootable.
5578 */
5579 if (fBootable)
5580 {
5581 if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
5582 rc = PDMDevHlpIOPortRegister(pDevIns, LSILOGIC_BIOS_IO_PORT, 4, NULL,
5583 lsilogicR3IsaIOPortWrite, lsilogicR3IsaIOPortRead,
5584 lsilogicR3IsaIOPortWriteStr, lsilogicR3IsaIOPortReadStr,
5585 "LsiLogic BIOS");
5586 else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
5587 rc = PDMDevHlpIOPortRegister(pDevIns, LSILOGIC_SAS_BIOS_IO_PORT, 4, NULL,
5588 lsilogicR3IsaIOPortWrite, lsilogicR3IsaIOPortRead,
5589 lsilogicR3IsaIOPortWriteStr, lsilogicR3IsaIOPortReadStr,
5590 "LsiLogic SAS BIOS");
5591 else
5592 AssertMsgFailed(("Invalid controller type %d\n", pThis->enmCtrlType));
5593
5594 if (RT_FAILURE(rc))
5595 return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic cannot register legacy I/O handlers"));
5596 }
5597
5598 /* Register save state handlers. */
5599 rc = PDMDevHlpSSMRegisterEx(pDevIns, LSILOGIC_SAVED_STATE_VERSION, sizeof(*pThis), NULL,
5600 NULL, lsilogicR3LiveExec, NULL,
5601 NULL, lsilogicR3SaveExec, NULL,
5602 NULL, lsilogicR3LoadExec, lsilogicR3LoadDone);
5603 if (RT_FAILURE(rc))
5604 return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic cannot register save state handlers"));
5605
5606 pThis->enmWhoInit = LSILOGICWHOINIT_SYSTEM_BIOS;
5607
5608 /*
5609 * Register the info item.
5610 */
5611 char szTmp[128];
5612 RTStrPrintf(szTmp, sizeof(szTmp), "%s%u", pDevIns->pReg->szName, pDevIns->iInstance);
5613 PDMDevHlpDBGFInfoRegister(pDevIns, szTmp,
5614 pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI
5615 ? "LsiLogic SPI info."
5616 : "LsiLogic SAS info.", lsilogicR3Info);
5617
5618 /* Perform hard reset. */
5619 rc = lsilogicR3HardReset(pThis);
5620 AssertRC(rc);
5621
5622 return rc;
5623}
5624
5625/**
5626 * The device registration structure - SPI SCSI controller.
5627 */
5628const PDMDEVREG g_DeviceLsiLogicSCSI =
5629{
5630 /* u32Version */
5631 PDM_DEVREG_VERSION,
5632 /* szName */
5633 "lsilogicscsi",
5634 /* szRCMod */
5635 "VBoxDDRC.rc",
5636 /* szR0Mod */
5637 "VBoxDDR0.r0",
5638 /* pszDescription */
5639 "LSI Logic 53c1030 SCSI controller.\n",
5640 /* fFlags */
5641 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0 |
5642 PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION | PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION,
5643 /* fClass */
5644 PDM_DEVREG_CLASS_STORAGE,
5645 /* cMaxInstances */
5646 ~0U,
5647 /* cbInstance */
5648 sizeof(LSILOGICSCSI),
5649 /* pfnConstruct */
5650 lsilogicR3Construct,
5651 /* pfnDestruct */
5652 lsilogicR3Destruct,
5653 /* pfnRelocate */
5654 lsilogicR3Relocate,
5655 /* pfnMemSetup */
5656 NULL,
5657 /* pfnPowerOn */
5658 NULL,
5659 /* pfnReset */
5660 lsilogicR3Reset,
5661 /* pfnSuspend */
5662 lsilogicR3Suspend,
5663 /* pfnResume */
5664 lsilogicR3Resume,
5665 /* pfnAttach */
5666 lsilogicR3Attach,
5667 /* pfnDetach */
5668 lsilogicR3Detach,
5669 /* pfnQueryInterface. */
5670 NULL,
5671 /* pfnInitComplete */
5672 NULL,
5673 /* pfnPowerOff */
5674 lsilogicR3PowerOff,
5675 /* pfnSoftReset */
5676 NULL,
5677 /* u32VersionEnd */
5678 PDM_DEVREG_VERSION
5679};
5680
5681/**
5682 * The device registration structure - SAS controller.
5683 */
5684const PDMDEVREG g_DeviceLsiLogicSAS =
5685{
5686 /* u32Version */
5687 PDM_DEVREG_VERSION,
5688 /* szName */
5689 "lsilogicsas",
5690 /* szRCMod */
5691 "VBoxDDRC.rc",
5692 /* szR0Mod */
5693 "VBoxDDR0.r0",
5694 /* pszDescription */
5695 "LSI Logic SAS1068 controller.\n",
5696 /* fFlags */
5697 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0 |
5698 PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION | PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION |
5699 PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION,
5700 /* fClass */
5701 PDM_DEVREG_CLASS_STORAGE,
5702 /* cMaxInstances */
5703 ~0U,
5704 /* cbInstance */
5705 sizeof(LSILOGICSCSI),
5706 /* pfnConstruct */
5707 lsilogicR3Construct,
5708 /* pfnDestruct */
5709 lsilogicR3Destruct,
5710 /* pfnRelocate */
5711 lsilogicR3Relocate,
5712 /* pfnMemSetup */
5713 NULL,
5714 /* pfnPowerOn */
5715 NULL,
5716 /* pfnReset */
5717 lsilogicR3Reset,
5718 /* pfnSuspend */
5719 lsilogicR3Suspend,
5720 /* pfnResume */
5721 lsilogicR3Resume,
5722 /* pfnAttach */
5723 lsilogicR3Attach,
5724 /* pfnDetach */
5725 lsilogicR3Detach,
5726 /* pfnQueryInterface. */
5727 NULL,
5728 /* pfnInitComplete */
5729 NULL,
5730 /* pfnPowerOff */
5731 lsilogicR3PowerOff,
5732 /* pfnSoftReset */
5733 NULL,
5734 /* u32VersionEnd */
5735 PDM_DEVREG_VERSION
5736};
5737
5738#endif /* IN_RING3 */
5739#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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