DevLsiLogicSCSI.cpp@ 64362

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1	/* $Id: DevLsiLogicSCSI.cpp 64274 2016-10-14 10:33:43Z vboxsync $ */
2	/** @file
3	* DevLsiLogicSCSI - LsiLogic LSI53c1030 SCSI controller.
4	*/
5
6	/*
7	* Copyright (C) 2006-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_LSILOGICSCSI
23	#include <VBox/vmm/pdmdev.h>
24	#include <VBox/vmm/pdmstorageifs.h>
25	#include <VBox/vmm/pdmqueue.h>
26	#include <VBox/vmm/pdmthread.h>
27	#include <VBox/vmm/pdmcritsect.h>
28	#include <VBox/scsi.h>
29	#include <VBox/sup.h>
30	#include <iprt/assert.h>
31	#include <iprt/asm.h>
32	#include <iprt/string.h>
33	#include <iprt/list.h>
34	#ifdef IN_RING3
35	# include <iprt/memcache.h>
36	# include <iprt/mem.h>
37	# include <iprt/param.h>
38	# include <iprt/uuid.h>
39	# include <iprt/time.h>
40	#endif
41
42	#include "DevLsiLogicSCSI.h"
43	#include "VBoxSCSI.h"
44
45	#include "VBoxDD.h"
46
47
48	/*********************************************************************************************************************************
49	* Defined Constants And Macros *
50	*********************************************************************************************************************************/
51	/** The current saved state version. */
52	#define LSILOGIC_SAVED_STATE_VERSION 5
53	/** The saved state version used by VirtualBox before the diagnostic
54	* memory access was implemented. */
55	#define LSILOGIC_SAVED_STATE_VERSION_PRE_DIAG_MEM 4
56	/** The saved state version used by VirtualBox before the doorbell status flag
57	* was changed from bool to a 32bit enum. */
58	#define LSILOGIC_SAVED_STATE_VERSION_BOOL_DOORBELL 3
59	/** The saved state version used by VirtualBox before SAS support was added. */
60	#define LSILOGIC_SAVED_STATE_VERSION_PRE_SAS 2
61	/** The saved state version used by VirtualBox 3.0 and earlier. It does not
62	* include the device config part. */
63	#define LSILOGIC_SAVED_STATE_VERSION_VBOX_30 1
64
65	/** Maximum number of entries in the release log. */
66	#define MAX_REL_LOG_ERRORS 1024
67
68	#define LSILOGIC_RTGCPHYS_FROM_U32(Hi, Lo) ( (RTGCPHYS)RT_MAKE_U64(Lo, Hi) )
69
70	/** Upper number a buffer is freed if it was too big before. */
71	#define LSILOGIC_MAX_ALLOC_TOO_MUCH 20
72
73	/** Maximum size of the memory regions (prevents teh guest from DOSing the host by
74	* allocating loadds of memory). */
75	#define LSILOGIC_MEMORY_REGIONS_MAX (_1M)
76
77
78	/*********************************************************************************************************************************
79	* Structures and Typedefs *
80	*********************************************************************************************************************************/
81
82	/** Pointer to the device instance data of the LsiLogic emulation. */
83	typedef struct LSILOGICSCSI *PLSILOGICSCSI;
84
85	#ifdef IN_RING3
86	/**
87	* Memory buffer callback.
88	*
89	* @returns nothing.
90	* @param pThis The LsiLogic controller instance.
91	* @param GCPhys The guest physical address of the memory buffer.
92	* @param pSgBuf The pointer to the host R3 S/G buffer.
93	* @param cbCopy How many bytes to copy between the two buffers.
94	* @param pcbSkip Initially contains the amount of bytes to skip
95	* starting from the guest physical address before
96	* accessing the S/G buffer and start copying data.
97	* On return this contains the remaining amount if
98	* cbCopy < *pcbSkip or 0 otherwise.
99	*/
100	typedef DECLCALLBACK(void) LSILOGICR3MEMCOPYCALLBACK(PLSILOGICSCSI pThis, RTGCPHYS GCPhys, PRTSGBUF pSgBuf, size_t cbCopy,
101	size_t *pcbSkip);
102	/** Pointer to a memory copy buffer callback. */
103	typedef LSILOGICR3MEMCOPYCALLBACK *PLSILOGICR3MEMCOPYCALLBACK;
104	#endif
105
106	/**
107	* Reply data.
108	*/
109	typedef struct LSILOGICSCSIREPLY
110	{
111	/** Lower 32 bits of the reply address in memory. */
112	uint32_t u32HostMFALowAddress;
113	/** Full address of the reply in guest memory. */
114	RTGCPHYS GCPhysReplyAddress;
115	/** Size of the reply. */
116	uint32_t cbReply;
117	/** Different views to the reply depending on the request type. */
118	MptReplyUnion Reply;
119	} LSILOGICSCSIREPLY;
120	/** Pointer to reply data. */
121	typedef LSILOGICSCSIREPLY *PLSILOGICSCSIREPLY;
122
123	/**
124	* Memory region of the IOC.
125	*/
126	typedef struct LSILOGICMEMREGN
127	{
128	/** List node. */
129	RTLISTNODE NodeList;
130	/** 32bit address the region starts to describe. */
131	uint32_t u32AddrStart;
132	/** 32bit address the region ends (inclusive). */
133	uint32_t u32AddrEnd;
134	/** Data for this region - variable. */
135	uint32_t au32Data[1];
136	} LSILOGICMEMREGN;
137	/** Pointer to a memory region. */
138	typedef LSILOGICMEMREGN *PLSILOGICMEMREGN;
139
140	/**
141	* State of a device attached to the buslogic host adapter.
142	*
143	* @implements PDMIBASE
144	* @implements PDMISCSIPORT
145	* @implements PDMILEDPORTS
146	*/
147	typedef struct LSILOGICDEVICE
148	{
149	/** Pointer to the owning lsilogic device instance. - R3 pointer */
150	R3PTRTYPE(PLSILOGICSCSI) pLsiLogicR3;
151
152	/** LUN of the device. */
153	uint32_t iLUN;
154	/** Number of outstanding tasks on the port. */
155	volatile uint32_t cOutstandingRequests;
156
157	#if HC_ARCH_BITS == 64
158	uint32_t Alignment0;
159	#endif
160
161	/** Our base interface. */
162	PDMIBASE IBase;
163	/** Media port interface. */
164	PDMIMEDIAPORT IMediaPort;
165	/** Extended media port interface. */
166	PDMIMEDIAEXPORT IMediaExPort;
167	/** Led interface. */
168	PDMILEDPORTS ILed;
169	/** Pointer to the attached driver's base interface. */
170	R3PTRTYPE(PPDMIBASE) pDrvBase;
171	/** Pointer to the attached driver's media interface. */
172	R3PTRTYPE(PPDMIMEDIA) pDrvMedia;
173	/** Pointer to the attached driver's extended media interface. */
174	R3PTRTYPE(PPDMIMEDIAEX) pDrvMediaEx;
175	/** The status LED state for this device. */
176	PDMLED Led;
177
178	} LSILOGICDEVICE;
179	/** Pointer to a device state. */
180	typedef LSILOGICDEVICE *PLSILOGICDEVICE;
181
182	/** Pointer to a task state. */
183	typedef struct LSILOGICREQ *PLSILOGICREQ;
184
185	/**
186	* Device instance data for the emulated SCSI controller.
187	*/
188	typedef struct LSILOGICSCSI
189	{
190	/** PCI device structure. */
191	PCIDEVICE PciDev;
192	/** Pointer to the device instance. - R3 ptr. */
193	PPDMDEVINSR3 pDevInsR3;
194	/** Pointer to the device instance. - R0 ptr. */
195	PPDMDEVINSR0 pDevInsR0;
196	/** Pointer to the device instance. - RC ptr. */
197	PPDMDEVINSRC pDevInsRC;
198
199	/** Flag whether the GC part of the device is enabled. */
200	bool fGCEnabled;
201	/** Flag whether the R0 part of the device is enabled. */
202	bool fR0Enabled;
203
204	/** The state the controller is currently in. */
205	LSILOGICSTATE enmState;
206	/** Who needs to init the driver to get into operational state. */
207	LSILOGICWHOINIT enmWhoInit;
208	/** Flag whether we are in doorbell function. */
209	LSILOGICDOORBELLSTATE enmDoorbellState;
210	/** Flag whether diagnostic access is enabled. */
211	bool fDiagnosticEnabled;
212	/** Flag whether a notification was send to R3. */
213	bool fNotificationSent;
214	/** Flag whether the guest enabled event notification from the IOC. */
215	bool fEventNotificationEnabled;
216	/** Flag whether the diagnostic address and RW registers are enabled. */
217	bool fDiagRegsEnabled;
218
219	/** Queue to send tasks to R3. - R3 ptr */
220	R3PTRTYPE(PPDMQUEUE) pNotificationQueueR3;
221	/** Queue to send tasks to R3. - R0 ptr */
222	R0PTRTYPE(PPDMQUEUE) pNotificationQueueR0;
223	/** Queue to send tasks to R3. - RC ptr */
224	RCPTRTYPE(PPDMQUEUE) pNotificationQueueRC;
225
226	/** Number of device states allocated. */
227	uint32_t cDeviceStates;
228
229	/** States for attached devices. */
230	R3PTRTYPE(PLSILOGICDEVICE) paDeviceStates;
231	#if HC_ARCH_BITS == 32
232	RTR3PTR R3PtrPadding0;
233	#endif
234
235	/** Interrupt mask. */
236	volatile uint32_t uInterruptMask;
237	/** Interrupt status register. */
238	volatile uint32_t uInterruptStatus;
239
240	/** Buffer for messages which are passed through the doorbell using the
241	* handshake method. */
242	uint32_t aMessage[sizeof(MptConfigurationRequest)]; /** @todo r=bird: Looks like 4 tims the required size? Please explain in comment if this correct... */
243	/** Actual position in the buffer. */
244	uint32_t iMessage;
245	/** Size of the message which is given in the doorbell message in dwords. */
246	uint32_t cMessage;
247
248	/** Reply buffer.
249	* @note 60 bytes */
250	MptReplyUnion ReplyBuffer;
251	/** Next entry to read. */
252	uint32_t uNextReplyEntryRead;
253	/** Size of the reply in the buffer in 16bit words. */
254	uint32_t cReplySize;
255
256	/** The fault code of the I/O controller if we are in the fault state. */
257	uint16_t u16IOCFaultCode;
258
259	/** I/O port address the device is mapped to. */
260	RTIOPORT IOPortBase;
261	/** MMIO address the device is mapped to. */
262	RTGCPHYS GCPhysMMIOBase;
263
264	/** Upper 32 bits of the message frame address to locate requests in guest memory. */
265	uint32_t u32HostMFAHighAddr;
266	/** Upper 32 bits of the sense buffer address. */
267	uint32_t u32SenseBufferHighAddr;
268	/** Maximum number of devices the driver reported he can handle. */
269	uint8_t cMaxDevices;
270	/** Maximum number of buses the driver reported he can handle. */
271	uint8_t cMaxBuses;
272	/** Current size of reply message frames in the guest. */
273	uint16_t cbReplyFrame;
274
275	/** Next key to write in the sequence to get access
276	* to diagnostic memory. */
277	uint32_t iDiagnosticAccess;
278
279	/** Number entries allocated for the reply queue. */
280	uint32_t cReplyQueueEntries;
281	/** Number entries allocated for the outstanding request queue. */
282	uint32_t cRequestQueueEntries;
283
284
285	/** Critical section protecting the reply post queue. */
286	PDMCRITSECT ReplyPostQueueCritSect;
287	/** Critical section protecting the reply free queue. */
288	PDMCRITSECT ReplyFreeQueueCritSect;
289
290	/** Pointer to the start of the reply free queue - R3. */
291	R3PTRTYPE(volatile uint32_t *) pReplyFreeQueueBaseR3;
292	/** Pointer to the start of the reply post queue - R3. */
293	R3PTRTYPE(volatile uint32_t *) pReplyPostQueueBaseR3;
294	/** Pointer to the start of the request queue - R3. */
295	R3PTRTYPE(volatile uint32_t *) pRequestQueueBaseR3;
296
297	/** Pointer to the start of the reply queue - R0. */
298	R0PTRTYPE(volatile uint32_t *) pReplyFreeQueueBaseR0;
299	/** Pointer to the start of the reply queue - R0. */
300	R0PTRTYPE(volatile uint32_t *) pReplyPostQueueBaseR0;
301	/** Pointer to the start of the request queue - R0. */
302	R0PTRTYPE(volatile uint32_t *) pRequestQueueBaseR0;
303
304	/** Pointer to the start of the reply queue - RC. */
305	RCPTRTYPE(volatile uint32_t *) pReplyFreeQueueBaseRC;
306	/** Pointer to the start of the reply queue - RC. */
307	RCPTRTYPE(volatile uint32_t *) pReplyPostQueueBaseRC;
308	/** Pointer to the start of the request queue - RC. */
309	RCPTRTYPE(volatile uint32_t *) pRequestQueueBaseRC;
310	/** End these RC pointers on a 64-bit boundrary. */
311	RTRCPTR RCPtrPadding1;
312
313	/** Next free entry in the reply queue the guest can write a address to. */
314	volatile uint32_t uReplyFreeQueueNextEntryFreeWrite;
315	/** Next valid entry the controller can read a valid address for reply frames from. */
316	volatile uint32_t uReplyFreeQueueNextAddressRead;
317
318	/** Next free entry in the reply queue the guest can write a address to. */
319	volatile uint32_t uReplyPostQueueNextEntryFreeWrite;
320	/** Next valid entry the controller can read a valid address for reply frames from. */
321	volatile uint32_t uReplyPostQueueNextAddressRead;
322
323	/** Next free entry the guest can write a address to a request frame to. */
324	volatile uint32_t uRequestQueueNextEntryFreeWrite;
325	/** Next valid entry the controller can read a valid address for request frames from. */
326	volatile uint32_t uRequestQueueNextAddressRead;
327
328	/** Emulated controller type */
329	LSILOGICCTRLTYPE enmCtrlType;
330	/** Handle counter */
331	uint16_t u16NextHandle;
332
333	/** Number of ports this controller has. */
334	uint8_t cPorts;
335
336	/** BIOS emulation. */
337	VBOXSCSI VBoxSCSI;
338
339	/** Status LUN: The base interface. */
340	PDMIBASE IBase;
341	/** Status LUN: Leds interface. */
342	PDMILEDPORTS ILeds;
343	/** Status LUN: Partner of ILeds. */
344	R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
345	/** Pointer to the configuration page area. */
346	R3PTRTYPE(PMptConfigurationPagesSupported) pConfigurationPages;
347
348	/** Indicates that PDMDevHlpAsyncNotificationCompleted should be called when
349	* a port is entering the idle state. */
350	bool volatile fSignalIdle;
351	/** Flag whether we have tasks which need to be processed again- */
352	bool volatile fRedo;
353	/** Flag whether the worker thread is sleeping. */
354	volatile bool fWrkThreadSleeping;
355	/** Flag whether a request from the BIOS is pending which the
356	* worker thread needs to process. */
357	volatile bool fBiosReqPending;
358	#if HC_ARCH_BITS == 64
359	/** Alignment padding. */
360	bool afPadding2[4];
361	#endif
362	/** List of tasks which can be redone. */
363	R3PTRTYPE(volatile PLSILOGICREQ) pTasksRedoHead;
364
365	/** Current address to read from or write to in the diagnostic memory region. */
366	uint32_t u32DiagMemAddr;
367	/** Current size of the memory regions. */
368	uint32_t cbMemRegns;
369
370	#if HC_ARCH_BITS ==32
371	uint32_t u32Padding3;
372	#endif
373
374	union
375	{
376	/** List of memory regions - PLSILOGICMEMREGN. */
377	RTLISTANCHOR ListMemRegns;
378	uint8_t u8Padding[2 * sizeof(RTUINTPTR)];
379	};
380
381	/** The support driver session handle. */
382	R3R0PTRTYPE(PSUPDRVSESSION) pSupDrvSession;
383	/** Worker thread. */
384	R3PTRTYPE(PPDMTHREAD) pThreadWrk;
385	/** The event semaphore the processing thread waits on. */
386	SUPSEMEVENT hEvtProcess;
387
388	} LSILOGISCSI;
389
390	/**
391	* Task state object which holds all necessary data while
392	* processing the request from the guest.
393	*/
394	typedef struct LSILOGICREQ
395	{
396	/** I/O request handle. */
397	PDMMEDIAEXIOREQ hIoReq;
398	/** Next in the redo list. */
399	PLSILOGICREQ pRedoNext;
400	/** Target device. */
401	PLSILOGICDEVICE pTargetDevice;
402	/** The message request from the guest. */
403	MptRequestUnion GuestRequest;
404	/** Address of the message request frame in guests memory.
405	* Used to read the S/G entries in the second step. */
406	RTGCPHYS GCPhysMessageFrameAddr;
407	/** Physical start address of the S/G list. */
408	RTGCPHYS GCPhysSgStart;
409	/** Chain offset */
410	uint32_t cChainOffset;
411	/** Pointer to the sense buffer. */
412	uint8_t abSenseBuffer[18];
413	/** Flag whether the request was issued from the BIOS. */
414	bool fBIOS;
415	/** SCSI status code. */
416	uint8_t u8ScsiSts;
417	} LSILOGICREQ;
418
419
420	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
421
422
423	/*********************************************************************************************************************************
424	* Internal Functions *
425	*********************************************************************************************************************************/
426	RT_C_DECLS_BEGIN
427	#ifdef IN_RING3
428	static void lsilogicR3InitializeConfigurationPages(PLSILOGICSCSI pThis);
429	static void lsilogicR3ConfigurationPagesFree(PLSILOGICSCSI pThis);
430	static int lsilogicR3ProcessConfigurationRequest(PLSILOGICSCSI pThis, PMptConfigurationRequest pConfigurationReq,
431	PMptConfigurationReply pReply);
432	#endif
433	RT_C_DECLS_END
434
435
436	/*********************************************************************************************************************************
437	* Global Variables *
438	*********************************************************************************************************************************/
439	/** Key sequence the guest has to write to enable access
440	* to diagnostic memory. */
441	static const uint8_t g_lsilogicDiagnosticAccess[] = {0x04, 0x0b, 0x02, 0x07, 0x0d};
442
443	/**
444	* Updates the status of the interrupt pin of the device.
445	*
446	* @returns nothing.
447	* @param pThis Pointer to the LsiLogic device state.
448	*/
449	static void lsilogicUpdateInterrupt(PLSILOGICSCSI pThis)
450	{
451	uint32_t uIntSts;
452
453	LogFlowFunc(("Updating interrupts\n"));
454
455	/* Mask out doorbell status so that it does not affect interrupt updating. */
456	uIntSts = (ASMAtomicReadU32(&pThis->uInterruptStatus) & ~LSILOGIC_REG_HOST_INTR_STATUS_DOORBELL_STS);
457	/* Check maskable interrupts. */
458	uIntSts &= ~(ASMAtomicReadU32(&pThis->uInterruptMask) & ~LSILOGIC_REG_HOST_INTR_MASK_IRQ_ROUTING);
459
460	if (uIntSts)
461	{
462	LogFlowFunc(("Setting interrupt\n"));
463	PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, 1);
464	}
465	else
466	{
467	LogFlowFunc(("Clearing interrupt\n"));
468	PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, 0);
469	}
470	}
471
472	/**
473	* Sets a given interrupt status bit in the status register and
474	* updates the interrupt status.
475	*
476	* @returns nothing.
477	* @param pThis Pointer to the LsiLogic device state.
478	* @param uStatus The status bit to set.
479	*/
480	DECLINLINE(void) lsilogicSetInterrupt(PLSILOGICSCSI pThis, uint32_t uStatus)
481	{
482	ASMAtomicOrU32(&pThis->uInterruptStatus, uStatus);
483	lsilogicUpdateInterrupt(pThis);
484	}
485
486	/**
487	* Clears a given interrupt status bit in the status register and
488	* updates the interrupt status.
489	*
490	* @returns nothing.
491	* @param pThis Pointer to the LsiLogic device state.
492	* @param uStatus The status bit to set.
493	*/
494	DECLINLINE(void) lsilogicClearInterrupt(PLSILOGICSCSI pThis, uint32_t uStatus)
495	{
496	ASMAtomicAndU32(&pThis->uInterruptStatus, ~uStatus);
497	lsilogicUpdateInterrupt(pThis);
498	}
499
500
501	#ifdef IN_RING3
502	/**
503	* Sets the I/O controller into fault state and sets the fault code.
504	*
505	* @returns nothing
506	* @param pThis Pointer to the LsiLogic device state.
507	* @param uIOCFaultCode Fault code to set.
508	*/
509	DECLINLINE(void) lsilogicSetIOCFaultCode(PLSILOGICSCSI pThis, uint16_t uIOCFaultCode)
510	{
511	if (pThis->enmState != LSILOGICSTATE_FAULT)
512	{
513	LogFunc(("Setting I/O controller into FAULT state: uIOCFaultCode=%u\n", uIOCFaultCode));
514	pThis->enmState = LSILOGICSTATE_FAULT;
515	pThis->u16IOCFaultCode = uIOCFaultCode;
516	}
517	else
518	LogFunc(("We are already in FAULT state\n"));
519	}
520	#endif /* IN_RING3 */
521
522
523	/**
524	* Returns the number of frames in the reply free queue.
525	*
526	* @returns Number of frames in the reply free queue.
527	* @param pThis Pointer to the LsiLogic device state.
528	*/
529	DECLINLINE(uint32_t) lsilogicReplyFreeQueueGetFrameCount(PLSILOGICSCSI pThis)
530	{
531	uint32_t cReplyFrames = 0;
532
533	if (pThis->uReplyFreeQueueNextAddressRead <= pThis->uReplyFreeQueueNextEntryFreeWrite)
534	cReplyFrames = pThis->uReplyFreeQueueNextEntryFreeWrite - pThis->uReplyFreeQueueNextAddressRead;
535	else
536	cReplyFrames = pThis->cReplyQueueEntries - pThis->uReplyFreeQueueNextAddressRead + pThis->uReplyFreeQueueNextEntryFreeWrite;
537
538	return cReplyFrames;
539	}
540
541	#ifdef IN_RING3
542
543	/**
544	* Returns the number of free entries in the reply post queue.
545	*
546	* @returns Number of frames in the reply free queue.
547	* @param pThis Pointer to the LsiLogic device state.
548	*/
549	DECLINLINE(uint32_t) lsilogicReplyPostQueueGetFrameCount(PLSILOGICSCSI pThis)
550	{
551	uint32_t cReplyFrames = 0;
552
553	if (pThis->uReplyPostQueueNextAddressRead <= pThis->uReplyPostQueueNextEntryFreeWrite)
554	cReplyFrames = pThis->cReplyQueueEntries - pThis->uReplyPostQueueNextEntryFreeWrite + pThis->uReplyPostQueueNextAddressRead;
555	else
556	cReplyFrames = pThis->uReplyPostQueueNextEntryFreeWrite - pThis->uReplyPostQueueNextAddressRead;
557
558	return cReplyFrames;
559	}
560
561
562	/**
563	* Performs a hard reset on the controller.
564	*
565	* @returns VBox status code.
566	* @param pThis Pointer to the LsiLogic device state.
567	*/
568	static int lsilogicR3HardReset(PLSILOGICSCSI pThis)
569	{
570	pThis->enmState = LSILOGICSTATE_RESET;
571	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_NOT_IN_USE;
572
573	/* The interrupts are masked out. */
574	pThis->uInterruptMask \|= LSILOGIC_REG_HOST_INTR_MASK_DOORBELL
575	\| LSILOGIC_REG_HOST_INTR_MASK_REPLY;
576	/* Reset interrupt states. */
577	pThis->uInterruptStatus = 0;
578	lsilogicUpdateInterrupt(pThis);
579
580	/* Reset the queues. */
581	pThis->uReplyFreeQueueNextEntryFreeWrite = 0;
582	pThis->uReplyFreeQueueNextAddressRead = 0;
583	pThis->uReplyPostQueueNextEntryFreeWrite = 0;
584	pThis->uReplyPostQueueNextAddressRead = 0;
585	pThis->uRequestQueueNextEntryFreeWrite = 0;
586	pThis->uRequestQueueNextAddressRead = 0;
587
588	/* Disable diagnostic access. */
589	pThis->iDiagnosticAccess = 0;
590	pThis->fDiagnosticEnabled = false;
591	pThis->fDiagRegsEnabled = false;
592
593	/* Set default values. */
594	pThis->cMaxDevices = pThis->cDeviceStates;
595	pThis->cMaxBuses = 1;
596	pThis->cbReplyFrame = 128; /** @todo Figure out where it is needed. */
597	pThis->u16NextHandle = 1;
598	pThis->u32DiagMemAddr = 0;
599
600	lsilogicR3ConfigurationPagesFree(pThis);
601	lsilogicR3InitializeConfigurationPages(pThis);
602
603	/* Mark that we finished performing the reset. */
604	pThis->enmState = LSILOGICSTATE_READY;
605	return VINF_SUCCESS;
606	}
607
608	/**
609	* Frees the configuration pages if allocated.
610	*
611	* @returns nothing.
612	* @param pThis The LsiLogic controller instance
613	*/
614	static void lsilogicR3ConfigurationPagesFree(PLSILOGICSCSI pThis)
615	{
616
617	if (pThis->pConfigurationPages)
618	{
619	/* Destroy device list if we emulate a SAS controller. */
620	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
621	{
622	PMptConfigurationPagesSas pSasPages = &pThis->pConfigurationPages->u.SasPages;
623	PMptSASDevice pSASDeviceCurr = pSasPages->pSASDeviceHead;
624
625	while (pSASDeviceCurr)
626	{
627	PMptSASDevice pFree = pSASDeviceCurr;
628
629	pSASDeviceCurr = pSASDeviceCurr->pNext;
630	RTMemFree(pFree);
631	}
632	if (pSasPages->paPHYs)
633	RTMemFree(pSasPages->paPHYs);
634	if (pSasPages->pManufacturingPage7)
635	RTMemFree(pSasPages->pManufacturingPage7);
636	if (pSasPages->pSASIOUnitPage0)
637	RTMemFree(pSasPages->pSASIOUnitPage0);
638	if (pSasPages->pSASIOUnitPage1)
639	RTMemFree(pSasPages->pSASIOUnitPage1);
640	}
641
642	RTMemFree(pThis->pConfigurationPages);
643	}
644	}
645
646	/**
647	* Finishes a context reply.
648	*
649	* @returns nothing
650	* @param pThis Pointer to the LsiLogic device state.
651	* @param u32MessageContext The message context ID to post.
652	*/
653	static void lsilogicR3FinishContextReply(PLSILOGICSCSI pThis, uint32_t u32MessageContext)
654	{
655	int rc;
656
657	LogFlowFunc(("pThis=%#p u32MessageContext=%#x\n", pThis, u32MessageContext));
658
659	AssertMsg(pThis->enmDoorbellState == LSILOGICDOORBELLSTATE_NOT_IN_USE, ("We are in a doorbell function\n"));
660
661	/* Write message context ID into reply post queue. */
662	rc = PDMCritSectEnter(&pThis->ReplyPostQueueCritSect, VINF_SUCCESS);
663	AssertRC(rc);
664
665	/* Check for a entry in the queue. */
666	if (!lsilogicReplyPostQueueGetFrameCount(pThis))
667	{
668	/* Set error code. */
669	lsilogicSetIOCFaultCode(pThis, LSILOGIC_IOCSTATUS_INSUFFICIENT_RESOURCES);
670	PDMCritSectLeave(&pThis->ReplyPostQueueCritSect);
671	return;
672	}
673
674	/* We have a context reply. */
675	ASMAtomicWriteU32(&pThis->CTX_SUFF(pReplyPostQueueBase)[pThis->uReplyPostQueueNextEntryFreeWrite], u32MessageContext);
676	ASMAtomicIncU32(&pThis->uReplyPostQueueNextEntryFreeWrite);
677	pThis->uReplyPostQueueNextEntryFreeWrite %= pThis->cReplyQueueEntries;
678
679	/* Set interrupt. */
680	lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_REPLY_INTR);
681
682	PDMCritSectLeave(&pThis->ReplyPostQueueCritSect);
683	}
684
685
686	/**
687	* Takes necessary steps to finish a reply frame.
688	*
689	* @returns nothing
690	* @param pThis Pointer to the LsiLogic device state.
691	* @param pReply Pointer to the reply message.
692	* @param fForceReplyFifo Flag whether the use of the reply post fifo is forced.
693	*/
694	static void lsilogicFinishAddressReply(PLSILOGICSCSI pThis, PMptReplyUnion pReply, bool fForceReplyFifo)
695	{
696	/*
697	* If we are in a doorbell function we set the reply size now and
698	* set the system doorbell status interrupt to notify the guest that
699	* we are ready to send the reply.
700	*/
701	if (pThis->enmDoorbellState != LSILOGICDOORBELLSTATE_NOT_IN_USE && !fForceReplyFifo)
702	{
703	/* Set size of the reply in 16bit words. The size in the reply is in 32bit dwords. */
704	pThis->cReplySize = pReply->Header.u8MessageLength * 2;
705	Log(("%s: cReplySize=%u\n", __FUNCTION__, pThis->cReplySize));
706	pThis->uNextReplyEntryRead = 0;
707	lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
708	}
709	else
710	{
711	/*
712	* The reply queues are only used if the request was fetched from the request queue.
713	* Requests from the request queue are always transferred to R3. So it is not possible
714	* that this case happens in R0 or GC.
715	*/
716	# ifdef IN_RING3
717	int rc;
718	/* Grab a free reply message from the queue. */
719	rc = PDMCritSectEnter(&pThis->ReplyFreeQueueCritSect, VINF_SUCCESS);
720	AssertRC(rc);
721
722	/* Check for a free reply frame. */
723	if (!lsilogicReplyFreeQueueGetFrameCount(pThis))
724	{
725	/* Set error code. */
726	lsilogicSetIOCFaultCode(pThis, LSILOGIC_IOCSTATUS_INSUFFICIENT_RESOURCES);
727	PDMCritSectLeave(&pThis->ReplyFreeQueueCritSect);
728	return;
729	}
730
731	uint32_t u32ReplyFrameAddressLow = pThis->CTX_SUFF(pReplyFreeQueueBase)[pThis->uReplyFreeQueueNextAddressRead];
732
733	pThis->uReplyFreeQueueNextAddressRead++;
734	pThis->uReplyFreeQueueNextAddressRead %= pThis->cReplyQueueEntries;
735
736	PDMCritSectLeave(&pThis->ReplyFreeQueueCritSect);
737
738	/* Build 64bit physical address. */
739	RTGCPHYS GCPhysReplyMessage = LSILOGIC_RTGCPHYS_FROM_U32(pThis->u32HostMFAHighAddr, u32ReplyFrameAddressLow);
740	size_t cbReplyCopied = (pThis->cbReplyFrame < sizeof(MptReplyUnion)) ? pThis->cbReplyFrame : sizeof(MptReplyUnion);
741
742	/* Write reply to guest memory. */
743	PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhysReplyMessage, pReply, cbReplyCopied);
744
745	/* Write low 32bits of reply frame into post reply queue. */
746	rc = PDMCritSectEnter(&pThis->ReplyPostQueueCritSect, VINF_SUCCESS);
747	AssertRC(rc);
748
749	/* Check for a entry in the queue. */
750	if (!lsilogicReplyPostQueueGetFrameCount(pThis))
751	{
752	/* Set error code. */
753	lsilogicSetIOCFaultCode(pThis, LSILOGIC_IOCSTATUS_INSUFFICIENT_RESOURCES);
754	PDMCritSectLeave(&pThis->ReplyPostQueueCritSect);
755	return;
756	}
757
758	/* We have a address reply. Set the 31th bit to indicate that. */
759	ASMAtomicWriteU32(&pThis->CTX_SUFF(pReplyPostQueueBase)[pThis->uReplyPostQueueNextEntryFreeWrite],
760	RT_BIT(31) \| (u32ReplyFrameAddressLow >> 1));
761	ASMAtomicIncU32(&pThis->uReplyPostQueueNextEntryFreeWrite);
762	pThis->uReplyPostQueueNextEntryFreeWrite %= pThis->cReplyQueueEntries;
763
764	if (fForceReplyFifo)
765	{
766	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_NOT_IN_USE;
767	lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
768	}
769
770	/* Set interrupt. */
771	lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_REPLY_INTR);
772
773	PDMCritSectLeave(&pThis->ReplyPostQueueCritSect);
774	# else
775	AssertMsgFailed(("This is not allowed to happen.\n"));
776	# endif
777	}
778	}
779
780
781	/**
782	* Tries to find a memory region which covers the given address.
783	*
784	* @returns Pointer to memory region or NULL if not found.
785	* @param pThis Pointer to the LsiLogic device state.
786	* @param u32Addr The 32bit address to search for.
787	*/
788	static PLSILOGICMEMREGN lsilogicR3MemRegionFindByAddr(PLSILOGICSCSI pThis, uint32_t u32Addr)
789	{
790	PLSILOGICMEMREGN pIt;
791	PLSILOGICMEMREGN pRegion = NULL;
792
793	RTListForEach(&pThis->ListMemRegns, pIt, LSILOGICMEMREGN, NodeList)
794	{
795	if ( u32Addr >= pIt->u32AddrStart
796	&& u32Addr <= pIt->u32AddrEnd)
797	{
798	pRegion = pIt;
799	break;
800	}
801	}
802
803	return pRegion;
804	}
805
806	/**
807	* Frees all allocated memory regions.
808	*
809	* @returns nothing.
810	* @param pThis Pointer to the LsiLogic device state.
811	*/
812	static void lsilogicR3MemRegionsFree(PLSILOGICSCSI pThis)
813	{
814	PLSILOGICMEMREGN pIt;
815	PLSILOGICMEMREGN pItNext;
816
817	RTListForEachSafe(&pThis->ListMemRegns, pIt, pItNext, LSILOGICMEMREGN, NodeList)
818	{
819	RTListNodeRemove(&pIt->NodeList);
820	RTMemFree(pIt);
821	}
822	pThis->cbMemRegns = 0;
823	}
824
825	/**
826	* Inserts a given memory region into the list.
827	*
828	* @returns nothing.
829	* @param pThis Pointer to the LsiLogic device state.
830	* @param pRegion The region to insert.
831	*/
832	static void lsilogicR3MemRegionInsert(PLSILOGICSCSI pThis, PLSILOGICMEMREGN pRegion)
833	{
834	PLSILOGICMEMREGN pIt;
835	bool fInserted = false;
836
837	/* Insert at the right position. */
838	RTListForEach(&pThis->ListMemRegns, pIt, LSILOGICMEMREGN, NodeList)
839	{
840	if (pRegion->u32AddrEnd < pIt->u32AddrStart)
841	{
842	RTListNodeInsertBefore(&pIt->NodeList, &pRegion->NodeList);
843	fInserted = true;
844	break;
845	}
846	}
847	if (!fInserted)
848	RTListAppend(&pThis->ListMemRegns, &pRegion->NodeList);
849	}
850
851	/**
852	* Count number of memory regions.
853	*
854	* @returns Number of memory regions.
855	* @param pThis Pointer to the LsiLogic device state.
856	*/
857	static uint32_t lsilogicR3MemRegionsCount(PLSILOGICSCSI pThis)
858	{
859	uint32_t cRegions = 0;
860	PLSILOGICMEMREGN pIt;
861
862	RTListForEach(&pThis->ListMemRegns, pIt, LSILOGICMEMREGN, NodeList)
863	{
864	cRegions++;
865	}
866
867	return cRegions;
868	}
869
870	/**
871	* Handles a write to the diagnostic data register.
872	*
873	* @returns nothing.
874	* @param pThis Pointer to the LsiLogic device state.
875	* @param u32Data Data to write.
876	*/
877	static void lsilogicR3DiagRegDataWrite(PLSILOGICSCSI pThis, uint32_t u32Data)
878	{
879	PLSILOGICMEMREGN pRegion = lsilogicR3MemRegionFindByAddr(pThis, pThis->u32DiagMemAddr);
880
881	if (pRegion)
882	{
883	uint32_t offRegion = pThis->u32DiagMemAddr - pRegion->u32AddrStart;
884
885	AssertMsg( offRegion % 4 == 0
886	&& pThis->u32DiagMemAddr <= pRegion->u32AddrEnd,
887	("Region offset not on a word boundary or crosses memory region\n"));
888
889	offRegion /= 4;
890	pRegion->au32Data[offRegion] = u32Data;
891	}
892	else
893	{
894	PLSILOGICMEMREGN pIt;
895
896	pRegion = NULL;
897
898	/* Create new region, first check whether we can extend another region. */
899	RTListForEach(&pThis->ListMemRegns, pIt, LSILOGICMEMREGN, NodeList)
900	{
901	if (pThis->u32DiagMemAddr == pIt->u32AddrEnd + sizeof(uint32_t))
902	{
903	pRegion = pIt;
904	break;
905	}
906	}
907
908	if (pRegion)
909	{
910	/* Reallocate. */
911	RTListNodeRemove(&pRegion->NodeList);
912
913	uint32_t cRegionSizeOld = (pRegion->u32AddrEnd - pRegion->u32AddrStart) / 4 + 1;
914	uint32_t cRegionSizeNew = cRegionSizeOld + 512;
915
916	if (pThis->cbMemRegns + 512 * sizeof(uint32_t) < LSILOGIC_MEMORY_REGIONS_MAX)
917	{
918	PLSILOGICMEMREGN pRegionNew = (PLSILOGICMEMREGN)RTMemRealloc(pRegion, RT_OFFSETOF(LSILOGICMEMREGN, au32Data[cRegionSizeNew]));
919
920	if (pRegionNew)
921	{
922	pRegion = pRegionNew;
923	memset(&pRegion->au32Data[cRegionSizeOld], 0, 512 * sizeof(uint32_t));
924	pRegion->au32Data[cRegionSizeOld] = u32Data;
925	pRegion->u32AddrEnd = pRegion->u32AddrStart + (cRegionSizeNew - 1) * sizeof(uint32_t);
926	pThis->cbMemRegns += 512 * sizeof(uint32_t);
927	}
928	/* else: Silently fail, there is nothing we can do here and the guest might work nevertheless. */
929
930	lsilogicR3MemRegionInsert(pThis, pRegion);
931	}
932	}
933	else
934	{
935	if (pThis->cbMemRegns + 512 * sizeof(uint32_t) < LSILOGIC_MEMORY_REGIONS_MAX)
936	{
937	/* Create completely new. */
938	pRegion = (PLSILOGICMEMREGN)RTMemAllocZ(RT_OFFSETOF(LSILOGICMEMREGN, au32Data[512]));
939	if (pRegion)
940	{
941	pRegion->u32AddrStart = pThis->u32DiagMemAddr;
942	pRegion->u32AddrEnd = pRegion->u32AddrStart + (512 - 1) * sizeof(uint32_t);
943	pRegion->au32Data[0] = u32Data;
944	pThis->cbMemRegns += 512 * sizeof(uint32_t);
945
946	lsilogicR3MemRegionInsert(pThis, pRegion);
947	}
948	/* else: Silently fail, there is nothing we can do here and the guest might work nevertheless. */
949	}
950	}
951
952	}
953
954	/* Memory access is always 32bit big. */
955	pThis->u32DiagMemAddr += sizeof(uint32_t);
956	}
957
958	/**
959	* Handles a read from the diagnostic data register.
960	*
961	* @returns nothing.
962	* @param pThis Pointer to the LsiLogic device state.
963	* @param pu32Data Where to store the data.
964	*/
965	static void lsilogicR3DiagRegDataRead(PLSILOGICSCSI pThis, uint32_t *pu32Data)
966	{
967	PLSILOGICMEMREGN pRegion = lsilogicR3MemRegionFindByAddr(pThis, pThis->u32DiagMemAddr);
968
969	if (pRegion)
970	{
971	uint32_t offRegion = pThis->u32DiagMemAddr - pRegion->u32AddrStart;
972
973	AssertMsg( offRegion % 4 == 0
974	&& pThis->u32DiagMemAddr <= pRegion->u32AddrEnd,
975	("Region offset not on a word boundary or crosses memory region\n"));
976
977	offRegion /= 4;
978	*pu32Data = pRegion->au32Data[offRegion];
979	}
980	else /* No region, default value 0. */
981	*pu32Data = 0;
982
983	/* Memory access is always 32bit big. */
984	pThis->u32DiagMemAddr += sizeof(uint32_t);
985	}
986
987	/**
988	* Handles a write to the diagnostic memory address register.
989	*
990	* @returns nothing.
991	* @param pThis Pointer to the LsiLogic device state.
992	* @param u32Addr Address to write.
993	*/
994	static void lsilogicR3DiagRegAddressWrite(PLSILOGICSCSI pThis, uint32_t u32Addr)
995	{
996	pThis->u32DiagMemAddr = u32Addr & ~UINT32_C(0x3); /* 32bit alignment. */
997	}
998
999	/**
1000	* Handles a read from the diagnostic memory address register.
1001	*
1002	* @returns nothing.
1003	* @param pThis Pointer to the LsiLogic device state.
1004	* @param pu32Addr Where to store the current address.
1005	*/
1006	static void lsilogicR3DiagRegAddressRead(PLSILOGICSCSI pThis, uint32_t *pu32Addr)
1007	{
1008	*pu32Addr = pThis->u32DiagMemAddr;
1009	}
1010
1011	/**
1012	* Processes a given Request from the guest
1013	*
1014	* @returns VBox status code.
1015	* @param pThis Pointer to the LsiLogic device state.
1016	* @param pMessageHdr Pointer to the message header of the request.
1017	* @param pReply Pointer to the reply.
1018	*/
1019	static int lsilogicR3ProcessMessageRequest(PLSILOGICSCSI pThis, PMptMessageHdr pMessageHdr, PMptReplyUnion pReply)
1020	{
1021	int rc = VINF_SUCCESS;
1022	bool fForceReplyPostFifo = false;
1023
1024	# ifdef LOG_ENABLED
1025	if (pMessageHdr->u8Function < RT_ELEMENTS(g_apszMPTFunctionNames))
1026	Log(("Message request function: %s\n", g_apszMPTFunctionNames[pMessageHdr->u8Function]));
1027	else
1028	Log(("Message request function: <unknown>\n"));
1029	# endif
1030
1031	memset(pReply, 0, sizeof(MptReplyUnion));
1032
1033	switch (pMessageHdr->u8Function)
1034	{
1035	case MPT_MESSAGE_HDR_FUNCTION_SCSI_TASK_MGMT:
1036	{
1037	PMptSCSITaskManagementRequest pTaskMgmtReq = (PMptSCSITaskManagementRequest)pMessageHdr;
1038
1039	LogFlow(("u8TaskType=%u\n", pTaskMgmtReq->u8TaskType));
1040	LogFlow(("u32TaskMessageContext=%#x\n", pTaskMgmtReq->u32TaskMessageContext));
1041
1042	pReply->SCSITaskManagement.u8MessageLength = 6; /* 6 32bit dwords. */
1043	pReply->SCSITaskManagement.u8TaskType = pTaskMgmtReq->u8TaskType;
1044	pReply->SCSITaskManagement.u32TerminationCount = 0;
1045	fForceReplyPostFifo = true;
1046	break;
1047	}
1048	case MPT_MESSAGE_HDR_FUNCTION_IOC_INIT:
1049	{
1050	/*
1051	* This request sets the I/O controller to the
1052	* operational state.
1053	*/
1054	PMptIOCInitRequest pIOCInitReq = (PMptIOCInitRequest)pMessageHdr;
1055
1056	/* Update configuration values. */
1057	pThis->enmWhoInit = (LSILOGICWHOINIT)pIOCInitReq->u8WhoInit;
1058	pThis->cbReplyFrame = pIOCInitReq->u16ReplyFrameSize;
1059	pThis->cMaxBuses = pIOCInitReq->u8MaxBuses;
1060	pThis->cMaxDevices = pIOCInitReq->u8MaxDevices;
1061	pThis->u32HostMFAHighAddr = pIOCInitReq->u32HostMfaHighAddr;
1062	pThis->u32SenseBufferHighAddr = pIOCInitReq->u32SenseBufferHighAddr;
1063
1064	if (pThis->enmState == LSILOGICSTATE_READY)
1065	{
1066	pThis->enmState = LSILOGICSTATE_OPERATIONAL;
1067	}
1068
1069	/* Return reply. */
1070	pReply->IOCInit.u8MessageLength = 5;
1071	pReply->IOCInit.u8WhoInit = pThis->enmWhoInit;
1072	pReply->IOCInit.u8MaxDevices = pThis->cMaxDevices;
1073	pReply->IOCInit.u8MaxBuses = pThis->cMaxBuses;
1074	break;
1075	}
1076	case MPT_MESSAGE_HDR_FUNCTION_IOC_FACTS:
1077	{
1078	pReply->IOCFacts.u8MessageLength = 15; /* 15 32bit dwords. */
1079
1080	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
1081	{
1082	pReply->IOCFacts.u16MessageVersion = 0x0102; /* Version from the specification. */
1083	pReply->IOCFacts.u8NumberOfPorts = pThis->cPorts;
1084	}
1085	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
1086	{
1087	pReply->IOCFacts.u16MessageVersion = 0x0105; /* Version from the specification. */
1088	pReply->IOCFacts.u8NumberOfPorts = pThis->cPorts;
1089	}
1090	else
1091	AssertMsgFailed(("Invalid controller type %d\n", pThis->enmCtrlType));
1092
1093	pReply->IOCFacts.u8IOCNumber = 0; /* PCI function number. */
1094	pReply->IOCFacts.u16IOCExceptions = 0;
1095	pReply->IOCFacts.u8MaxChainDepth = LSILOGICSCSI_MAXIMUM_CHAIN_DEPTH;
1096	pReply->IOCFacts.u8WhoInit = pThis->enmWhoInit;
1097	pReply->IOCFacts.u8BlockSize = 12; /* Block size in 32bit dwords. This is the largest request we can get (SCSI I/O). */
1098	pReply->IOCFacts.u8Flags = 0; /* Bit 0 is set if the guest must upload the FW prior to using the controller. Obviously not needed here. */
1099	pReply->IOCFacts.u16ReplyQueueDepth = pThis->cReplyQueueEntries - 1; /* One entry is always free. */
1100	pReply->IOCFacts.u16RequestFrameSize = 128; /** @todo Figure out where it is needed. */
1101	pReply->IOCFacts.u32CurrentHostMFAHighAddr = pThis->u32HostMFAHighAddr;
1102	pReply->IOCFacts.u16GlobalCredits = pThis->cRequestQueueEntries - 1; /* One entry is always free. */
1103
1104	pReply->IOCFacts.u8EventState = 0; /* Event notifications not enabled. */
1105	pReply->IOCFacts.u32CurrentSenseBufferHighAddr = pThis->u32SenseBufferHighAddr;
1106	pReply->IOCFacts.u16CurReplyFrameSize = pThis->cbReplyFrame;
1107	pReply->IOCFacts.u8MaxDevices = pThis->cMaxDevices;
1108	pReply->IOCFacts.u8MaxBuses = pThis->cMaxBuses;
1109
1110	/* Check for a valid firmware image in the IOC memory which was downlaoded by tzhe guest earlier. */
1111	PLSILOGICMEMREGN pRegion = lsilogicR3MemRegionFindByAddr(pThis, LSILOGIC_FWIMGHDR_LOAD_ADDRESS);
1112
1113	if (pRegion)
1114	{
1115	uint32_t offImgHdr = (LSILOGIC_FWIMGHDR_LOAD_ADDRESS - pRegion->u32AddrStart) / 4;
1116	PFwImageHdr pFwImgHdr = (PFwImageHdr)&pRegion->au32Data[offImgHdr];
1117
1118	/* Check for the signature. */
1119	/** @todo Checksum validation. */
1120	if ( pFwImgHdr->u32Signature1 == LSILOGIC_FWIMGHDR_SIGNATURE1
1121	&& pFwImgHdr->u32Signature2 == LSILOGIC_FWIMGHDR_SIGNATURE2
1122	&& pFwImgHdr->u32Signature3 == LSILOGIC_FWIMGHDR_SIGNATURE3)
1123	{
1124	LogFlowFunc(("IOC Facts: Found valid firmware image header in memory, using version (%#x), size (%d) and product ID (%#x) from there\n",
1125	pFwImgHdr->u32FwVersion, pFwImgHdr->u32ImageSize, pFwImgHdr->u16ProductId));
1126
1127	pReply->IOCFacts.u16ProductID = pFwImgHdr->u16ProductId;
1128	pReply->IOCFacts.u32FwImageSize = pFwImgHdr->u32ImageSize;
1129	pReply->IOCFacts.u32FWVersion = pFwImgHdr->u32FwVersion;
1130	}
1131	}
1132	else
1133	{
1134	pReply->IOCFacts.u16ProductID = 0xcafe; /* Our own product ID :) */
1135	pReply->IOCFacts.u32FwImageSize = 0; /* No image needed. */
1136	pReply->IOCFacts.u32FWVersion = 0;
1137	}
1138	break;
1139	}
1140	case MPT_MESSAGE_HDR_FUNCTION_PORT_FACTS:
1141	{
1142	PMptPortFactsRequest pPortFactsReq = (PMptPortFactsRequest)pMessageHdr;
1143
1144	pReply->PortFacts.u8MessageLength = 10;
1145	pReply->PortFacts.u8PortNumber = pPortFactsReq->u8PortNumber;
1146
1147	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
1148	{
1149	/* This controller only supports one bus with bus number 0. */
1150	if (pPortFactsReq->u8PortNumber >= pThis->cPorts)
1151	{
1152	pReply->PortFacts.u8PortType = 0; /* Not existant. */
1153	}
1154	else
1155	{
1156	pReply->PortFacts.u8PortType = 0x01; /* SCSI Port. */
1157	pReply->PortFacts.u16MaxDevices = LSILOGICSCSI_PCI_SPI_DEVICES_PER_BUS_MAX;
1158	pReply->PortFacts.u16ProtocolFlags = RT_BIT(3) \| RT_BIT(0); /* SCSI initiator and LUN supported. */
1159	pReply->PortFacts.u16PortSCSIID = 7; /* Default */
1160	pReply->PortFacts.u16MaxPersistentIDs = 0;
1161	pReply->PortFacts.u16MaxPostedCmdBuffers = 0; /* Only applies for target mode which we dont support. */
1162	pReply->PortFacts.u16MaxLANBuckets = 0; /* Only for the LAN controller. */
1163	}
1164	}
1165	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
1166	{
1167	if (pPortFactsReq->u8PortNumber >= pThis->cPorts)
1168	{
1169	pReply->PortFacts.u8PortType = 0; /* Not existant. */
1170	}
1171	else
1172	{
1173	pReply->PortFacts.u8PortType = 0x30; /* SAS Port. */
1174	pReply->PortFacts.u16MaxDevices = pThis->cPorts;
1175	pReply->PortFacts.u16ProtocolFlags = RT_BIT(3) \| RT_BIT(0); /* SCSI initiator and LUN supported. */
1176	pReply->PortFacts.u16PortSCSIID = pThis->cPorts;
1177	pReply->PortFacts.u16MaxPersistentIDs = 0;
1178	pReply->PortFacts.u16MaxPostedCmdBuffers = 0; /* Only applies for target mode which we dont support. */
1179	pReply->PortFacts.u16MaxLANBuckets = 0; /* Only for the LAN controller. */
1180	}
1181	}
1182	else
1183	AssertMsgFailed(("Invalid controller type %d\n", pThis->enmCtrlType));
1184	break;
1185	}
1186	case MPT_MESSAGE_HDR_FUNCTION_PORT_ENABLE:
1187	{
1188	/*
1189	* The port enable request notifies the IOC to make the port available and perform
1190	* appropriate discovery on the associated link.
1191	*/
1192	PMptPortEnableRequest pPortEnableReq = (PMptPortEnableRequest)pMessageHdr;
1193
1194	pReply->PortEnable.u8MessageLength = 5;
1195	pReply->PortEnable.u8PortNumber = pPortEnableReq->u8PortNumber;
1196	break;
1197	}
1198	case MPT_MESSAGE_HDR_FUNCTION_EVENT_NOTIFICATION:
1199	{
1200	PMptEventNotificationRequest pEventNotificationReq = (PMptEventNotificationRequest)pMessageHdr;
1201
1202	if (pEventNotificationReq->u8Switch)
1203	pThis->fEventNotificationEnabled = true;
1204	else
1205	pThis->fEventNotificationEnabled = false;
1206
1207	pReply->EventNotification.u16EventDataLength = 1; /* 1 32bit D-Word. */
1208	pReply->EventNotification.u8MessageLength = 8;
1209	pReply->EventNotification.u8MessageFlags = (1 << 7);
1210	pReply->EventNotification.u8AckRequired = 0;
1211	pReply->EventNotification.u32Event = MPT_EVENT_EVENT_CHANGE;
1212	pReply->EventNotification.u32EventContext = 0;
1213	pReply->EventNotification.u32EventData = pThis->fEventNotificationEnabled ? 1 : 0;
1214
1215	break;
1216	}
1217	case MPT_MESSAGE_HDR_FUNCTION_EVENT_ACK:
1218	{
1219	AssertMsgFailed(("todo"));
1220	break;
1221	}
1222	case MPT_MESSAGE_HDR_FUNCTION_CONFIG:
1223	{
1224	PMptConfigurationRequest pConfigurationReq = (PMptConfigurationRequest)pMessageHdr;
1225
1226	rc = lsilogicR3ProcessConfigurationRequest(pThis, pConfigurationReq, &pReply->Configuration);
1227	AssertRC(rc);
1228	break;
1229	}
1230	case MPT_MESSAGE_HDR_FUNCTION_FW_UPLOAD:
1231	{
1232	PMptFWUploadRequest pFWUploadReq = (PMptFWUploadRequest)pMessageHdr;
1233
1234	pReply->FWUpload.u8ImageType = pFWUploadReq->u8ImageType;
1235	pReply->FWUpload.u8MessageLength = 6;
1236	pReply->FWUpload.u32ActualImageSize = 0;
1237	break;
1238	}
1239	case MPT_MESSAGE_HDR_FUNCTION_FW_DOWNLOAD:
1240	{
1241	//PMptFWDownloadRequest pFWDownloadReq = (PMptFWDownloadRequest)pMessageHdr;
1242
1243	pReply->FWDownload.u8MessageLength = 5;
1244	LogFlowFunc(("FW Download request issued\n"));
1245	break;
1246	}
1247	case MPT_MESSAGE_HDR_FUNCTION_SCSI_IO_REQUEST: /* Should be handled already. */
1248	default:
1249	AssertMsgFailed(("Invalid request function %#x\n", pMessageHdr->u8Function));
1250	}
1251
1252	/* Copy common bits from request message frame to reply. */
1253	pReply->Header.u8Function = pMessageHdr->u8Function;
1254	pReply->Header.u32MessageContext = pMessageHdr->u32MessageContext;
1255
1256	lsilogicFinishAddressReply(pThis, pReply, fForceReplyPostFifo);
1257	return rc;
1258	}
1259
1260	#endif /* IN_RING3 */
1261
1262	/**
1263	* Writes a value to a register at a given offset.
1264	*
1265	* @returns VBox status code.
1266	* @param pThis Pointer to the LsiLogic device state.
1267	* @param offReg Offset of the register to write.
1268	* @param u32 The value being written.
1269	*/
1270	static int lsilogicRegisterWrite(PLSILOGICSCSI pThis, uint32_t offReg, uint32_t u32)
1271	{
1272	LogFlowFunc(("pThis=%#p offReg=%#x u32=%#x\n", pThis, offReg, u32));
1273	switch (offReg)
1274	{
1275	case LSILOGIC_REG_REPLY_QUEUE:
1276	{
1277	/* Add the entry to the reply free queue. */
1278	ASMAtomicWriteU32(&pThis->CTX_SUFF(pReplyFreeQueueBase)[pThis->uReplyFreeQueueNextEntryFreeWrite], u32);
1279	pThis->uReplyFreeQueueNextEntryFreeWrite++;
1280	pThis->uReplyFreeQueueNextEntryFreeWrite %= pThis->cReplyQueueEntries;
1281	break;
1282	}
1283	case LSILOGIC_REG_REQUEST_QUEUE:
1284	{
1285	uint32_t uNextWrite = ASMAtomicReadU32(&pThis->uRequestQueueNextEntryFreeWrite);
1286
1287	ASMAtomicWriteU32(&pThis->CTX_SUFF(pRequestQueueBase)[uNextWrite], u32);
1288
1289	/*
1290	* Don't update the value in place. It can happen that we get preempted
1291	* after the increment but before the modulo.
1292	* Another EMT will read the wrong value when processing the queues
1293	* and hang in an endless loop creating thousands of requests.
1294	*/
1295	uNextWrite++;
1296	uNextWrite %= pThis->cRequestQueueEntries;
1297	ASMAtomicWriteU32(&pThis->uRequestQueueNextEntryFreeWrite, uNextWrite);
1298
1299	/* Send notification to R3 if there is not one sent already. Do this
1300	* only if the worker thread is not sleeping or might go sleeping. */
1301	if (!ASMAtomicXchgBool(&pThis->fNotificationSent, true))
1302	{
1303	if (ASMAtomicReadBool(&pThis->fWrkThreadSleeping))
1304	{
1305	#ifdef IN_RC
1306	PPDMQUEUEITEMCORE pNotificationItem = PDMQueueAlloc(pThis->CTX_SUFF(pNotificationQueue));
1307	AssertPtr(pNotificationItem);
1308	PDMQueueInsert(pThis->CTX_SUFF(pNotificationQueue), pNotificationItem);
1309	#else
1310	LogFlowFunc(("Signal event semaphore\n"));
1311	int rc = SUPSemEventSignal(pThis->pSupDrvSession, pThis->hEvtProcess);
1312	AssertRC(rc);
1313	#endif
1314	}
1315	}
1316	break;
1317	}
1318	case LSILOGIC_REG_DOORBELL:
1319	{
1320	/*
1321	* When the guest writes to this register a real device would set the
1322	* doorbell status bit in the interrupt status register to indicate that the IOP
1323	* has still to process the message.
1324	* The guest needs to wait with posting new messages here until the bit is cleared.
1325	* Because the guest is not continuing execution while we are here we can skip this.
1326	*/
1327	if (pThis->enmDoorbellState == LSILOGICDOORBELLSTATE_NOT_IN_USE)
1328	{
1329	uint32_t uFunction = LSILOGIC_REG_DOORBELL_GET_FUNCTION(u32);
1330
1331	switch (uFunction)
1332	{
1333	case LSILOGIC_DOORBELL_FUNCTION_IO_UNIT_RESET:
1334	case LSILOGIC_DOORBELL_FUNCTION_IOC_MSG_UNIT_RESET:
1335	{
1336	/*
1337	* The I/O unit reset does much more on real hardware like
1338	* reloading the firmware, nothing we need to do here,
1339	* so this is like the IOC message unit reset.
1340	*/
1341	pThis->enmState = LSILOGICSTATE_RESET;
1342
1343	/* Reset interrupt status. */
1344	pThis->uInterruptStatus = 0;
1345	lsilogicUpdateInterrupt(pThis);
1346
1347	/* Reset the queues. */
1348	pThis->uReplyFreeQueueNextEntryFreeWrite = 0;
1349	pThis->uReplyFreeQueueNextAddressRead = 0;
1350	pThis->uReplyPostQueueNextEntryFreeWrite = 0;
1351	pThis->uReplyPostQueueNextAddressRead = 0;
1352	pThis->uRequestQueueNextEntryFreeWrite = 0;
1353	pThis->uRequestQueueNextAddressRead = 0;
1354
1355	/* Only the IOC message unit reset transisionts to the ready state. */
1356	if (uFunction == LSILOGIC_DOORBELL_FUNCTION_IOC_MSG_UNIT_RESET)
1357	pThis->enmState = LSILOGICSTATE_READY;
1358	break;
1359	}
1360	case LSILOGIC_DOORBELL_FUNCTION_HANDSHAKE:
1361	{
1362	pThis->cMessage = LSILOGIC_REG_DOORBELL_GET_SIZE(u32);
1363	pThis->iMessage = 0;
1364	AssertMsg(pThis->cMessage <= RT_ELEMENTS(pThis->aMessage),
1365	("Message doesn't fit into the buffer, cMessage=%u", pThis->cMessage));
1366	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_FN_HANDSHAKE;
1367	/* Update the interrupt status to notify the guest that a doorbell function was started. */
1368	lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1369	break;
1370	}
1371	case LSILOGIC_DOORBELL_FUNCTION_REPLY_FRAME_REMOVAL:
1372	{
1373	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_RFR_FRAME_COUNT_LOW;
1374	/* Update the interrupt status to notify the guest that a doorbell function was started. */
1375	lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1376	break;
1377	}
1378	default:
1379	AssertMsgFailed(("Unknown function %u to perform\n", uFunction));
1380	}
1381	}
1382	else if (pThis->enmDoorbellState == LSILOGICDOORBELLSTATE_FN_HANDSHAKE)
1383	{
1384	/*
1385	* We are already performing a doorbell function.
1386	* Get the remaining parameters.
1387	*/
1388	AssertMsg(pThis->iMessage < RT_ELEMENTS(pThis->aMessage), ("Message is too big to fit into the buffer\n"));
1389	/*
1390	* If the last byte of the message is written, force a switch to R3 because some requests might force
1391	* a reply through the FIFO which cannot be handled in GC or R0.
1392	*/
1393	#ifndef IN_RING3
1394	if (pThis->iMessage == pThis->cMessage - 1)
1395	return VINF_IOM_R3_MMIO_WRITE;
1396	#endif
1397	pThis->aMessage[pThis->iMessage++] = u32;
1398	#ifdef IN_RING3
1399	if (pThis->iMessage == pThis->cMessage)
1400	{
1401	int rc = lsilogicR3ProcessMessageRequest(pThis, (PMptMessageHdr)pThis->aMessage, &pThis->ReplyBuffer);
1402	AssertRC(rc);
1403	}
1404	#endif
1405	}
1406	break;
1407	}
1408	case LSILOGIC_REG_HOST_INTR_STATUS:
1409	{
1410	/*
1411	* Clear the bits the guest wants except the system doorbell interrupt and the IO controller
1412	* status bit.
1413	* The former bit is always cleared no matter what the guest writes to the register and
1414	* the latter one is read only.
1415	*/
1416	ASMAtomicAndU32(&pThis->uInterruptStatus, ~LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1417
1418	/*
1419	* Check if there is still a doorbell function in progress. Set the
1420	* system doorbell interrupt bit again if it is.
1421	* We do not use lsilogicSetInterrupt here because the interrupt status
1422	* is updated afterwards anyway.
1423	*/
1424	if ( (pThis->enmDoorbellState == LSILOGICDOORBELLSTATE_FN_HANDSHAKE)
1425	&& (pThis->cMessage == pThis->iMessage))
1426	{
1427	if (pThis->uNextReplyEntryRead == pThis->cReplySize)
1428	{
1429	/* Reply finished. Reset doorbell in progress status. */
1430	Log(("%s: Doorbell function finished\n", __FUNCTION__));
1431	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_NOT_IN_USE;
1432	}
1433	ASMAtomicOrU32(&pThis->uInterruptStatus, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1434	}
1435	else if ( pThis->enmDoorbellState != LSILOGICDOORBELLSTATE_NOT_IN_USE
1436	&& pThis->enmDoorbellState != LSILOGICDOORBELLSTATE_FN_HANDSHAKE)
1437	{
1438	/* Reply frame removal, check whether the reply free queue is empty. */
1439	if ( pThis->uReplyFreeQueueNextAddressRead == pThis->uReplyFreeQueueNextEntryFreeWrite
1440	&& pThis->enmDoorbellState == LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_LOW)
1441	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_NOT_IN_USE;
1442	ASMAtomicOrU32(&pThis->uInterruptStatus, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1443	}
1444
1445	lsilogicUpdateInterrupt(pThis);
1446	break;
1447	}
1448	case LSILOGIC_REG_HOST_INTR_MASK:
1449	{
1450	ASMAtomicWriteU32(&pThis->uInterruptMask, u32 & LSILOGIC_REG_HOST_INTR_MASK_W_MASK);
1451	lsilogicUpdateInterrupt(pThis);
1452	break;
1453	}
1454	case LSILOGIC_REG_WRITE_SEQUENCE:
1455	{
1456	if (pThis->fDiagnosticEnabled)
1457	{
1458	/* Any value will cause a reset and disabling access. */
1459	pThis->fDiagnosticEnabled = false;
1460	pThis->iDiagnosticAccess = 0;
1461	pThis->fDiagRegsEnabled = false;
1462	}
1463	else if ((u32 & 0xf) == g_lsilogicDiagnosticAccess[pThis->iDiagnosticAccess])
1464	{
1465	pThis->iDiagnosticAccess++;
1466	if (pThis->iDiagnosticAccess == RT_ELEMENTS(g_lsilogicDiagnosticAccess))
1467	{
1468	/*
1469	* Key sequence successfully written. Enable access to diagnostic
1470	* memory and register.
1471	*/
1472	pThis->fDiagnosticEnabled = true;
1473	}
1474	}
1475	else
1476	{
1477	/* Wrong value written - reset to beginning. */
1478	pThis->iDiagnosticAccess = 0;
1479	}
1480	break;
1481	}
1482	case LSILOGIC_REG_HOST_DIAGNOSTIC:
1483	{
1484	if (pThis->fDiagnosticEnabled)
1485	{
1486	#ifndef IN_RING3
1487	return VINF_IOM_R3_MMIO_WRITE;
1488	#else
1489	if (u32 & LSILOGIC_REG_HOST_DIAGNOSTIC_RESET_ADAPTER)
1490	lsilogicR3HardReset(pThis);
1491	else if (u32 & LSILOGIC_REG_HOST_DIAGNOSTIC_DIAG_RW_ENABLE)
1492	pThis->fDiagRegsEnabled = true;
1493	#endif
1494	}
1495	break;
1496	}
1497	case LSILOGIC_REG_DIAG_RW_DATA:
1498	{
1499	if (pThis->fDiagRegsEnabled)
1500	{
1501	#ifndef IN_RING3
1502	return VINF_IOM_R3_MMIO_WRITE;
1503	#else
1504	lsilogicR3DiagRegDataWrite(pThis, u32);
1505	#endif
1506	}
1507	break;
1508	}
1509	case LSILOGIC_REG_DIAG_RW_ADDRESS:
1510	{
1511	if (pThis->fDiagRegsEnabled)
1512	{
1513	#ifndef IN_RING3
1514	return VINF_IOM_R3_MMIO_WRITE;
1515	#else
1516	lsilogicR3DiagRegAddressWrite(pThis, u32);
1517	#endif
1518	}
1519	break;
1520	}
1521	default: /* Ignore. */
1522	{
1523	break;
1524	}
1525	}
1526	return VINF_SUCCESS;
1527	}
1528
1529	/**
1530	* Reads the content of a register at a given offset.
1531	*
1532	* @returns VBox status code.
1533	* @param pThis Pointer to the LsiLogic device state.
1534	* @param offReg Offset of the register to read.
1535	* @param pu32 Where to store the content of the register.
1536	*/
1537	static int lsilogicRegisterRead(PLSILOGICSCSI pThis, uint32_t offReg, uint32_t *pu32)
1538	{
1539	int rc = VINF_SUCCESS;
1540	uint32_t u32 = 0;
1541	Assert(!(offReg & 3));
1542
1543	/* Align to a 4 byte offset. */
1544	switch (offReg)
1545	{
1546	case LSILOGIC_REG_REPLY_QUEUE:
1547	{
1548	rc = PDMCritSectEnter(&pThis->ReplyPostQueueCritSect, VINF_IOM_R3_MMIO_READ);
1549	if (rc != VINF_SUCCESS)
1550	break;
1551
1552	uint32_t idxReplyPostQueueWrite = ASMAtomicUoReadU32(&pThis->uReplyPostQueueNextEntryFreeWrite);
1553	uint32_t idxReplyPostQueueRead = ASMAtomicUoReadU32(&pThis->uReplyPostQueueNextAddressRead);
1554
1555	if (idxReplyPostQueueWrite != idxReplyPostQueueRead)
1556	{
1557	u32 = pThis->CTX_SUFF(pReplyPostQueueBase)[idxReplyPostQueueRead];
1558	idxReplyPostQueueRead++;
1559	idxReplyPostQueueRead %= pThis->cReplyQueueEntries;
1560	ASMAtomicWriteU32(&pThis->uReplyPostQueueNextAddressRead, idxReplyPostQueueRead);
1561	}
1562	else
1563	{
1564	/* The reply post queue is empty. Reset interrupt. */
1565	u32 = UINT32_C(0xffffffff);
1566	lsilogicClearInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_REPLY_INTR);
1567	}
1568	PDMCritSectLeave(&pThis->ReplyPostQueueCritSect);
1569
1570	Log(("%s: Returning address %#x\n", __FUNCTION__, u32));
1571	break;
1572	}
1573	case LSILOGIC_REG_DOORBELL:
1574	{
1575	u32 = LSILOGIC_REG_DOORBELL_SET_STATE(pThis->enmState);
1576	u32 \|= LSILOGIC_REG_DOORBELL_SET_USED(pThis->enmDoorbellState);
1577	u32 \|= LSILOGIC_REG_DOORBELL_SET_WHOINIT(pThis->enmWhoInit);
1578	/*
1579	* If there is a doorbell function in progress we pass the return value
1580	* instead of the status code. We transfer 16bit of the reply
1581	* during one read.
1582	*/
1583	switch (pThis->enmDoorbellState)
1584	{
1585	case LSILOGICDOORBELLSTATE_NOT_IN_USE:
1586	/* We return the status code of the I/O controller. */
1587	u32 \|= pThis->u16IOCFaultCode;
1588	break;
1589	case LSILOGICDOORBELLSTATE_FN_HANDSHAKE:
1590	/* Return next 16bit value. */
1591	u32 \|= pThis->ReplyBuffer.au16Reply[pThis->uNextReplyEntryRead++];
1592	lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1593	break;
1594	case LSILOGICDOORBELLSTATE_RFR_FRAME_COUNT_LOW:
1595	{
1596	uint32_t cReplyFrames = lsilogicReplyFreeQueueGetFrameCount(pThis);
1597
1598	u32 \|= cReplyFrames & UINT32_C(0xffff);
1599	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_RFR_FRAME_COUNT_HIGH;
1600	lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1601	break;
1602	}
1603	case LSILOGICDOORBELLSTATE_RFR_FRAME_COUNT_HIGH:
1604	{
1605	uint32_t cReplyFrames = lsilogicReplyFreeQueueGetFrameCount(pThis);
1606
1607	u32 \|= cReplyFrames >> 16;
1608	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_LOW;
1609	lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1610	break;
1611	}
1612	case LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_LOW:
1613	if (pThis->uReplyFreeQueueNextEntryFreeWrite != pThis->uReplyFreeQueueNextAddressRead)
1614	{
1615	u32 \|= pThis->CTX_SUFF(pReplyFreeQueueBase)[pThis->uReplyFreeQueueNextAddressRead] & UINT32_C(0xffff);
1616	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_HIGH;
1617	lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1618	}
1619	break;
1620	case LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_HIGH:
1621	u32 \|= pThis->CTX_SUFF(pReplyFreeQueueBase)[pThis->uReplyFreeQueueNextAddressRead] >> 16;
1622	pThis->uReplyFreeQueueNextAddressRead++;
1623	pThis->uReplyFreeQueueNextAddressRead %= pThis->cReplyQueueEntries;
1624	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_LOW;
1625	lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1626	break;
1627	default:
1628	AssertMsgFailed(("Invalid doorbell state %d\n", pThis->enmDoorbellState));
1629	}
1630
1631	break;
1632	}
1633	case LSILOGIC_REG_HOST_INTR_STATUS:
1634	{
1635	u32 = ASMAtomicReadU32(&pThis->uInterruptStatus);
1636	break;
1637	}
1638	case LSILOGIC_REG_HOST_INTR_MASK:
1639	{
1640	u32 = ASMAtomicReadU32(&pThis->uInterruptMask);
1641	break;
1642	}
1643	case LSILOGIC_REG_HOST_DIAGNOSTIC:
1644	{
1645	if (pThis->fDiagnosticEnabled)
1646	u32 \|= LSILOGIC_REG_HOST_DIAGNOSTIC_DRWE;
1647	if (pThis->fDiagRegsEnabled)
1648	u32 \|= LSILOGIC_REG_HOST_DIAGNOSTIC_DIAG_RW_ENABLE;
1649	break;
1650	}
1651	case LSILOGIC_REG_DIAG_RW_DATA:
1652	{
1653	if (pThis->fDiagRegsEnabled)
1654	{
1655	#ifndef IN_RING3
1656	return VINF_IOM_R3_MMIO_READ;
1657	#else
1658	lsilogicR3DiagRegDataRead(pThis, &u32);
1659	#endif
1660	}
1661	}
1662	case LSILOGIC_REG_DIAG_RW_ADDRESS:
1663	{
1664	if (pThis->fDiagRegsEnabled)
1665	{
1666	#ifndef IN_RING3
1667	return VINF_IOM_R3_MMIO_READ;
1668	#else
1669	lsilogicR3DiagRegAddressRead(pThis, &u32);
1670	#endif
1671	}
1672	}
1673	case LSILOGIC_REG_TEST_BASE_ADDRESS: /* The spec doesn't say anything about these registers, so we just ignore them */
1674	default: /* Ignore. */
1675	{
1676	/** @todo LSILOGIC_REG_DIAG_* should return all F's when accessed by MMIO. We
1677	* return 0. Likely to apply to undefined offsets as well. */
1678	break;
1679	}
1680	}
1681
1682	*pu32 = u32;
1683	LogFlowFunc(("pThis=%#p offReg=%#x u32=%#x\n", pThis, offReg, u32));
1684	return rc;
1685	}
1686
1687	/**
1688	* @callback_method_impl{FNIOMIOPORTOUT}
1689	*/
1690	PDMBOTHCBDECL(int) lsilogicIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
1691	{
1692	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
1693	uint32_t offReg = uPort - pThis->IOPortBase;
1694	int rc;
1695	RT_NOREF2(pvUser, cb);
1696
1697	if (!(offReg & 3))
1698	{
1699	rc = lsilogicRegisterWrite(pThis, offReg, u32);
1700	if (rc == VINF_IOM_R3_MMIO_WRITE)
1701	rc = VINF_IOM_R3_IOPORT_WRITE;
1702	}
1703	else
1704	{
1705	Log(("lsilogicIOPortWrite: Ignoring misaligned write - offReg=%#x u32=%#x cb=%#x\n", offReg, u32, cb));
1706	rc = VINF_SUCCESS;
1707	}
1708
1709	return rc;
1710	}
1711
1712	/**
1713	* @callback_method_impl{FNIOMIOPORTIN}
1714	*/
1715	PDMBOTHCBDECL(int) lsilogicIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32, unsigned cb)
1716	{
1717	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
1718	uint32_t offReg = uPort - pThis->IOPortBase;
1719	RT_NOREF_PV(pvUser);
1720	RT_NOREF_PV(cb);
1721
1722	int rc = lsilogicRegisterRead(pThis, offReg & ~(uint32_t)3, pu32);
1723	if (rc == VINF_IOM_R3_MMIO_READ)
1724	rc = VINF_IOM_R3_IOPORT_READ;
1725
1726	return rc;
1727	}
1728
1729	/**
1730	* @callback_method_impl{FNIOMMMIOWRITE}
1731	*/
1732	PDMBOTHCBDECL(int) lsilogicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
1733	{
1734	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
1735	uint32_t offReg = GCPhysAddr - pThis->GCPhysMMIOBase;
1736	uint32_t u32;
1737	int rc;
1738	RT_NOREF_PV(pvUser);
1739
1740	/* See comments in lsilogicR3Map regarding size and alignment. */
1741	if (cb == 4)
1742	u32 = (uint32_t const )pv;
1743	else
1744	{
1745	if (cb > 4)
1746	u32 = (uint32_t const )pv;
1747	else if (cb >= 2)
1748	u32 = (uint16_t const )pv;
1749	else
1750	u32 = (uint8_t const )pv;
1751	Log(("lsilogicMMIOWrite: Non-DWORD write access - offReg=%#x u32=%#x cb=%#x\n", offReg, u32, cb));
1752	}
1753
1754	if (!(offReg & 3))
1755	rc = lsilogicRegisterWrite(pThis, offReg, u32);
1756	else
1757	{
1758	Log(("lsilogicIOPortWrite: Ignoring misaligned write - offReg=%#x u32=%#x cb=%#x\n", offReg, u32, cb));
1759	rc = VINF_SUCCESS;
1760	}
1761	return rc;
1762	}
1763
1764	/**
1765	* @callback_method_impl{FNIOMMMIOREAD}
1766	*/
1767	PDMBOTHCBDECL(int) lsilogicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
1768	{
1769	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
1770	uint32_t offReg = GCPhysAddr - pThis->GCPhysMMIOBase;
1771	Assert(!(offReg & 3)); Assert(cb == 4);
1772	RT_NOREF2(pvUser, cb);
1773
1774	return lsilogicRegisterRead(pThis, offReg, (uint32_t *)pv);
1775	}
1776
1777	PDMBOTHCBDECL(int) lsilogicDiagnosticWrite(PPDMDEVINS pDevIns, void *pvUser,
1778	RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
1779	{
1780	#ifdef LOG_ENABLED
1781	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
1782	LogFlowFunc(("pThis=%#p GCPhysAddr=%RGp pv=%#p{%.*Rhxs} cb=%u\n", pThis, GCPhysAddr, pv, cb, pv, cb));
1783	#endif
1784
1785	RT_NOREF_PV(pDevIns); RT_NOREF_PV(pvUser); RT_NOREF_PV(GCPhysAddr); RT_NOREF_PV(pv); RT_NOREF_PV(cb);
1786	return VINF_SUCCESS;
1787	}
1788
1789	PDMBOTHCBDECL(int) lsilogicDiagnosticRead(PPDMDEVINS pDevIns, void *pvUser,
1790	RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1791	{
1792	#ifdef LOG_ENABLED
1793	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
1794	LogFlowFunc(("pThis=%#p GCPhysAddr=%RGp pv=%#p{%.*Rhxs} cb=%u\n", pThis, GCPhysAddr, pv, cb, pv, cb));
1795	#endif
1796
1797	RT_NOREF_PV(pDevIns); RT_NOREF_PV(pvUser); RT_NOREF_PV(GCPhysAddr); RT_NOREF_PV(pv); RT_NOREF_PV(cb);
1798	return VINF_SUCCESS;
1799	}
1800
1801	#ifdef IN_RING3
1802
1803	# ifdef LOG_ENABLED
1804	/**
1805	* Dump an SG entry.
1806	*
1807	* @returns nothing.
1808	* @param pSGEntry Pointer to the SG entry to dump
1809	*/
1810	static void lsilogicDumpSGEntry(PMptSGEntryUnion pSGEntry)
1811	{
1812	if (LogIsEnabled())
1813	{
1814	switch (pSGEntry->Simple32.u2ElementType)
1815	{
1816	case MPTSGENTRYTYPE_SIMPLE:
1817	{
1818	Log(("%s: Dumping info for SIMPLE SG entry:\n", __FUNCTION__));
1819	Log(("%s: u24Length=%u\n", __FUNCTION__, pSGEntry->Simple32.u24Length));
1820	Log(("%s: fEndOfList=%d\n", __FUNCTION__, pSGEntry->Simple32.fEndOfList));
1821	Log(("%s: f64BitAddress=%d\n", __FUNCTION__, pSGEntry->Simple32.f64BitAddress));
1822	Log(("%s: fBufferContainsData=%d\n", __FUNCTION__, pSGEntry->Simple32.fBufferContainsData));
1823	Log(("%s: fLocalAddress=%d\n", __FUNCTION__, pSGEntry->Simple32.fLocalAddress));
1824	Log(("%s: fEndOfBuffer=%d\n", __FUNCTION__, pSGEntry->Simple32.fEndOfBuffer));
1825	Log(("%s: fLastElement=%d\n", __FUNCTION__, pSGEntry->Simple32.fLastElement));
1826	Log(("%s: u32DataBufferAddressLow=%u\n", __FUNCTION__, pSGEntry->Simple32.u32DataBufferAddressLow));
1827	if (pSGEntry->Simple32.f64BitAddress)
1828	{
1829	Log(("%s: u32DataBufferAddressHigh=%u\n", __FUNCTION__, pSGEntry->Simple64.u32DataBufferAddressHigh));
1830	Log(("%s: GCDataBufferAddress=%RGp\n", __FUNCTION__,
1831	((uint64_t)pSGEntry->Simple64.u32DataBufferAddressHigh << 32)
1832	\| pSGEntry->Simple64.u32DataBufferAddressLow));
1833	}
1834	else
1835	Log(("%s: GCDataBufferAddress=%RGp\n", __FUNCTION__, pSGEntry->Simple32.u32DataBufferAddressLow));
1836
1837	break;
1838	}
1839	case MPTSGENTRYTYPE_CHAIN:
1840	{
1841	Log(("%s: Dumping info for CHAIN SG entry:\n", __FUNCTION__));
1842	Log(("%s: u16Length=%u\n", __FUNCTION__, pSGEntry->Chain.u16Length));
1843	Log(("%s: u8NExtChainOffset=%d\n", __FUNCTION__, pSGEntry->Chain.u8NextChainOffset));
1844	Log(("%s: f64BitAddress=%d\n", __FUNCTION__, pSGEntry->Chain.f64BitAddress));
1845	Log(("%s: fLocalAddress=%d\n", __FUNCTION__, pSGEntry->Chain.fLocalAddress));
1846	Log(("%s: u32SegmentAddressLow=%u\n", __FUNCTION__, pSGEntry->Chain.u32SegmentAddressLow));
1847	Log(("%s: u32SegmentAddressHigh=%u\n", __FUNCTION__, pSGEntry->Chain.u32SegmentAddressHigh));
1848	if (pSGEntry->Chain.f64BitAddress)
1849	Log(("%s: GCSegmentAddress=%RGp\n", __FUNCTION__,
1850	((uint64_t)pSGEntry->Chain.u32SegmentAddressHigh << 32) \| pSGEntry->Chain.u32SegmentAddressLow));
1851	else
1852	Log(("%s: GCSegmentAddress=%RGp\n", __FUNCTION__, pSGEntry->Chain.u32SegmentAddressLow));
1853	break;
1854	}
1855	}
1856	}
1857	}
1858	# endif /* LOG_ENABLED */
1859
1860	/**
1861	* Copy from guest to host memory worker.
1862	*
1863	* @copydoc{LSILOGICR3MEMCOPYCALLBACK}
1864	*/
1865	static DECLCALLBACK(void) lsilogicR3CopyBufferFromGuestWorker(PLSILOGICSCSI pThis, RTGCPHYS GCPhys, PRTSGBUF pSgBuf,
1866	size_t cbCopy, size_t *pcbSkip)
1867	{
1868	size_t cbSkipped = RT_MIN(cbCopy, *pcbSkip);
1869	cbCopy -= cbSkipped;
1870	GCPhys += cbSkipped;
1871	*pcbSkip -= cbSkipped;
1872
1873	while (cbCopy)
1874	{
1875	size_t cbSeg = cbCopy;
1876	void *pvSeg = RTSgBufGetNextSegment(pSgBuf, &cbSeg);
1877
1878	AssertPtr(pvSeg);
1879	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, pvSeg, cbSeg);
1880	GCPhys += cbSeg;
1881	cbCopy -= cbSeg;
1882	}
1883	}
1884
1885	/**
1886	* Copy from host to guest memory worker.
1887	*
1888	* @copydoc{LSILOGICR3MEMCOPYCALLBACK}
1889	*/
1890	static DECLCALLBACK(void) lsilogicR3CopyBufferToGuestWorker(PLSILOGICSCSI pThis, RTGCPHYS GCPhys, PRTSGBUF pSgBuf,
1891	size_t cbCopy, size_t *pcbSkip)
1892	{
1893	size_t cbSkipped = RT_MIN(cbCopy, *pcbSkip);
1894	cbCopy -= cbSkipped;
1895	GCPhys += cbSkipped;
1896	*pcbSkip -= cbSkipped;
1897
1898	while (cbCopy)
1899	{
1900	size_t cbSeg = cbCopy;
1901	void *pvSeg = RTSgBufGetNextSegment(pSgBuf, &cbSeg);
1902
1903	AssertPtr(pvSeg);
1904	PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhys, pvSeg, cbSeg);
1905	GCPhys += cbSeg;
1906	cbCopy -= cbSeg;
1907	}
1908	}
1909
1910	/**
1911	* Walks the guest S/G buffer calling the given copy worker for every buffer.
1912	*
1913	* @returns The amout of bytes actually copied.
1914	* @param pThis Pointer to the LsiLogic device state.
1915	* @param pLsiReq LSI request state.
1916	* @param pfnCopyWorker The copy method to apply for each guest buffer.
1917	* @param pSgBuf The host S/G buffer.
1918	* @param cbSkip How many bytes to skip in advance before starting to copy.
1919	* @param cbCopy How many bytes to copy.
1920	*/
1921	static size_t lsilogicSgBufWalker(PLSILOGICSCSI pThis, PLSILOGICREQ pLsiReq,
1922	PLSILOGICR3MEMCOPYCALLBACK pfnCopyWorker,
1923	PRTSGBUF pSgBuf, size_t cbSkip, size_t cbCopy)
1924	{
1925	bool fEndOfList = false;
1926	RTGCPHYS GCPhysSgEntryNext = pLsiReq->GCPhysSgStart;
1927	RTGCPHYS GCPhysSegmentStart = pLsiReq->GCPhysSgStart;
1928	uint32_t cChainOffsetNext = pLsiReq->cChainOffset;
1929	PPDMDEVINS pDevIns = pThis->CTX_SUFF(pDevIns);
1930	size_t cbCopied = 0;
1931
1932	/*
1933	* Add the amount to skip to the host buffer size to avoid a
1934	* few conditionals later on.
1935	*/
1936	cbCopy += cbSkip;
1937
1938	/* Go through the list until we reach the end. */
1939	while ( !fEndOfList
1940	&& cbCopy)
1941	{
1942	bool fEndOfSegment = false;
1943
1944	while ( !fEndOfSegment
1945	&& cbCopy)
1946	{
1947	MptSGEntryUnion SGEntry;
1948
1949	Log(("%s: Reading SG entry from %RGp\n", __FUNCTION__, GCPhysSgEntryNext));
1950
1951	/* Read the entry. */
1952	PDMDevHlpPhysRead(pDevIns, GCPhysSgEntryNext, &SGEntry, sizeof(MptSGEntryUnion));
1953
1954	# ifdef LOG_ENABLED
1955	lsilogicDumpSGEntry(&SGEntry);
1956	# endif
1957
1958	AssertMsg(SGEntry.Simple32.u2ElementType == MPTSGENTRYTYPE_SIMPLE, ("Invalid SG entry type\n"));
1959
1960	/* Check if this is a zero element and abort. */
1961	if ( !SGEntry.Simple32.u24Length
1962	&& SGEntry.Simple32.fEndOfList
1963	&& SGEntry.Simple32.fEndOfBuffer)
1964	return cbCopied - RT_MIN(cbSkip, cbCopied);
1965
1966	uint32_t cbCopyThis = SGEntry.Simple32.u24Length;
1967	RTGCPHYS GCPhysAddrDataBuffer = SGEntry.Simple32.u32DataBufferAddressLow;
1968
1969	if (SGEntry.Simple32.f64BitAddress)
1970	{
1971	GCPhysAddrDataBuffer \|= ((uint64_t)SGEntry.Simple64.u32DataBufferAddressHigh) << 32;
1972	GCPhysSgEntryNext += sizeof(MptSGEntrySimple64);
1973	}
1974	else
1975	GCPhysSgEntryNext += sizeof(MptSGEntrySimple32);
1976
1977	pfnCopyWorker(pThis, GCPhysAddrDataBuffer, pSgBuf, cbCopyThis, &cbSkip);
1978	cbCopy -= cbCopyThis;
1979	cbCopied += cbCopyThis;
1980
1981	/* Check if we reached the end of the list. */
1982	if (SGEntry.Simple32.fEndOfList)
1983	{
1984	/* We finished. */
1985	fEndOfSegment = true;
1986	fEndOfList = true;
1987	}
1988	else if (SGEntry.Simple32.fLastElement)
1989	fEndOfSegment = true;
1990	} /* while (!fEndOfSegment) */
1991
1992	/* Get next chain element. */
1993	if (cChainOffsetNext)
1994	{
1995	MptSGEntryChain SGEntryChain;
1996
1997	PDMDevHlpPhysRead(pDevIns, GCPhysSegmentStart + cChainOffsetNext, &SGEntryChain, sizeof(MptSGEntryChain));
1998
1999	AssertMsg(SGEntryChain.u2ElementType == MPTSGENTRYTYPE_CHAIN, ("Invalid SG entry type\n"));
2000
2001	/* Set the next address now. */
2002	GCPhysSgEntryNext = SGEntryChain.u32SegmentAddressLow;
2003	if (SGEntryChain.f64BitAddress)
2004	GCPhysSgEntryNext \|= ((uint64_t)SGEntryChain.u32SegmentAddressHigh) << 32;
2005
2006	GCPhysSegmentStart = GCPhysSgEntryNext;
2007	cChainOffsetNext = SGEntryChain.u8NextChainOffset * sizeof(uint32_t);
2008	}
2009	} /* while (!fEndOfList) */
2010
2011	return cbCopied - RT_MIN(cbSkip, cbCopied);
2012	}
2013
2014	/**
2015	* Copies a data buffer into the S/G buffer set up by the guest.
2016	*
2017	* @returns Amount of bytes copied to the guest.
2018	* @param pThis The LsiLogic controller device instance.
2019	* @param pReq Request structure.
2020	* @param pSgBuf The S/G buffer to copy from.
2021	* @param cbSkip How many bytes to skip in advance before starting to copy.
2022	* @param cbCopy How many bytes to copy.
2023	*/
2024	static size_t lsilogicR3CopySgBufToGuest(PLSILOGICSCSI pThis, PLSILOGICREQ pReq, PRTSGBUF pSgBuf,
2025	size_t cbSkip, size_t cbCopy)
2026	{
2027	return lsilogicSgBufWalker(pThis, pReq, lsilogicR3CopyBufferToGuestWorker,
2028	pSgBuf, cbSkip, cbCopy);
2029	}
2030
2031	/**
2032	* Copies the guest S/G buffer into a host data buffer.
2033	*
2034	* @returns Amount of bytes copied from the guest.
2035	* @param pThis The LsiLogic controller device instance.
2036	* @param pReq Request structure.
2037	* @param pSgBuf The S/G buffer to copy into.
2038	* @param cbSkip How many bytes to skip in advance before starting to copy.
2039	* @param cbCopy How many bytes to copy.
2040	*/
2041	static size_t lsilogicR3CopySgBufFromGuest(PLSILOGICSCSI pThis, PLSILOGICREQ pReq, PRTSGBUF pSgBuf,
2042	size_t cbSkip, size_t cbCopy)
2043	{
2044	return lsilogicSgBufWalker(pThis, pReq, lsilogicR3CopyBufferFromGuestWorker,
2045	pSgBuf, cbSkip, cbCopy);
2046	}
2047
2048	#if 0 /* unused */
2049	/**
2050	* Copy a simple memory buffer to the guest memory buffer.
2051	*
2052	* @returns Amount of bytes copied to the guest.
2053	* @param pThis The LsiLogic controller device instance.
2054	* @param pReq Request structure.
2055	* @param pvSrc The buffer to copy from.
2056	* @param cbSrc How many bytes to copy.
2057	* @param cbSkip How many bytes to skip initially.
2058	*/
2059	static size_t lsilogicR3CopyBufferToGuest(PLSILOGICSCSI pThis, PLSILOGICREQ pReq, const void *pvSrc,
2060	size_t cbSrc, size_t cbSkip)
2061	{
2062	RTSGSEG Seg;
2063	RTSGBUF SgBuf;
2064	Seg.pvSeg = (void *)pvSrc;
2065	Seg.cbSeg = cbSrc;
2066	RTSgBufInit(&SgBuf, &Seg, 1);
2067	return lsilogicR3CopySgBufToGuest(pThis, pReq, &SgBuf, cbSkip, cbSrc);
2068	}
2069
2070	/**
2071	* Copy a guest memry buffe into simple host memory buffer.
2072	*
2073	* @returns Amount of bytes copied to the guest.
2074	* @param pThis The LsiLogic controller device instance.
2075	* @param pReq Request structure.
2076	* @param pvSrc The buffer to copy from.
2077	* @param cbSrc How many bytes to copy.
2078	* @param cbSkip How many bytes to skip initially.
2079	*/
2080	static size_t lsilogicR3CopyBufferFromGuest(PLSILOGICSCSI pThis, PLSILOGICREQ pReq, void *pvDst,
2081	size_t cbDst, size_t cbSkip)
2082	{
2083	RTSGSEG Seg;
2084	RTSGBUF SgBuf;
2085	Seg.pvSeg = (void *)pvDst;
2086	Seg.cbSeg = cbDst;
2087	RTSgBufInit(&SgBuf, &Seg, 1);
2088	return lsilogicR3CopySgBufFromGuest(pThis, pReq, &SgBuf, cbSkip, cbDst);
2089	}
2090	#endif
2091
2092	# ifdef LOG_ENABLED
2093	static void lsilogicR3DumpSCSIIORequest(PMptSCSIIORequest pSCSIIORequest)
2094	{
2095	if (LogIsEnabled())
2096	{
2097	Log(("%s: u8TargetID=%d\n", __FUNCTION__, pSCSIIORequest->u8TargetID));
2098	Log(("%s: u8Bus=%d\n", __FUNCTION__, pSCSIIORequest->u8Bus));
2099	Log(("%s: u8ChainOffset=%d\n", __FUNCTION__, pSCSIIORequest->u8ChainOffset));
2100	Log(("%s: u8Function=%d\n", __FUNCTION__, pSCSIIORequest->u8Function));
2101	Log(("%s: u8CDBLength=%d\n", __FUNCTION__, pSCSIIORequest->u8CDBLength));
2102	Log(("%s: u8SenseBufferLength=%d\n", __FUNCTION__, pSCSIIORequest->u8SenseBufferLength));
2103	Log(("%s: u8MessageFlags=%d\n", __FUNCTION__, pSCSIIORequest->u8MessageFlags));
2104	Log(("%s: u32MessageContext=%#x\n", __FUNCTION__, pSCSIIORequest->u32MessageContext));
2105	for (unsigned i = 0; i < RT_ELEMENTS(pSCSIIORequest->au8LUN); i++)
2106	Log(("%s: u8LUN[%d]=%d\n", __FUNCTION__, i, pSCSIIORequest->au8LUN[i]));
2107	Log(("%s: u32Control=%#x\n", __FUNCTION__, pSCSIIORequest->u32Control));
2108	for (unsigned i = 0; i < RT_ELEMENTS(pSCSIIORequest->au8CDB); i++)
2109	Log(("%s: u8CDB[%d]=%d\n", __FUNCTION__, i, pSCSIIORequest->au8CDB[i]));
2110	Log(("%s: u32DataLength=%#x\n", __FUNCTION__, pSCSIIORequest->u32DataLength));
2111	Log(("%s: u32SenseBufferLowAddress=%#x\n", __FUNCTION__, pSCSIIORequest->u32SenseBufferLowAddress));
2112	}
2113	}
2114	# endif
2115
2116	/**
2117	* Handles the completion of th given request.
2118	*
2119	* @returns nothing.
2120	* @param pThis Pointer to the LsiLogic device state.
2121	* @param pReq The request to complete.
2122	* @param rcReq Status code of the request.
2123	*/
2124	static void lsilogicR3ReqComplete(PLSILOGICSCSI pThis, PLSILOGICREQ pReq, int rcReq)
2125	{
2126	PLSILOGICDEVICE pTgtDev = pReq->pTargetDevice;
2127
2128	if (RT_UNLIKELY(pReq->fBIOS))
2129	{
2130	pTgtDev->pDrvMediaEx->pfnIoReqFree(pTgtDev->pDrvMediaEx, pReq->hIoReq);
2131	int rc = vboxscsiRequestFinished(&pThis->VBoxSCSI, rcReq);
2132	AssertMsgRC(rc, ("Finishing BIOS SCSI request failed rc=%Rrc\n", rc));
2133	}
2134	else
2135	{
2136	RTGCPHYS GCPhysAddrSenseBuffer;
2137
2138	GCPhysAddrSenseBuffer = pReq->GuestRequest.SCSIIO.u32SenseBufferLowAddress;
2139	GCPhysAddrSenseBuffer \|= ((uint64_t)pThis->u32SenseBufferHighAddr << 32);
2140
2141	/* Copy the sense buffer over. */
2142	PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhysAddrSenseBuffer, pReq->abSenseBuffer,
2143	RT_UNLIKELY( pReq->GuestRequest.SCSIIO.u8SenseBufferLength
2144	< sizeof(pReq->abSenseBuffer))
2145	? pReq->GuestRequest.SCSIIO.u8SenseBufferLength
2146	: sizeof(pReq->abSenseBuffer));
2147
2148	if (RT_SUCCESS(rcReq) && RT_LIKELY(pReq->u8ScsiSts == SCSI_STATUS_OK))
2149	{
2150	uint32_t u32MsgCtx = pReq->GuestRequest.SCSIIO.u32MessageContext;
2151
2152	/* Free the request before posting completion. */
2153	pTgtDev->pDrvMediaEx->pfnIoReqFree(pTgtDev->pDrvMediaEx, pReq->hIoReq);
2154	lsilogicR3FinishContextReply(pThis, u32MsgCtx);
2155	}
2156	else
2157	{
2158	MptReplyUnion IOCReply;
2159	RT_ZERO(IOCReply);
2160
2161	/* The SCSI target encountered an error during processing post a reply. */
2162	IOCReply.SCSIIOError.u8TargetID = pReq->GuestRequest.SCSIIO.u8TargetID;
2163	IOCReply.SCSIIOError.u8Bus = pReq->GuestRequest.SCSIIO.u8Bus;
2164	IOCReply.SCSIIOError.u8MessageLength = 8;
2165	IOCReply.SCSIIOError.u8Function = pReq->GuestRequest.SCSIIO.u8Function;
2166	IOCReply.SCSIIOError.u8CDBLength = pReq->GuestRequest.SCSIIO.u8CDBLength;
2167	IOCReply.SCSIIOError.u8SenseBufferLength = pReq->GuestRequest.SCSIIO.u8SenseBufferLength;
2168	IOCReply.SCSIIOError.u8MessageFlags = pReq->GuestRequest.SCSIIO.u8MessageFlags;
2169	IOCReply.SCSIIOError.u32MessageContext = pReq->GuestRequest.SCSIIO.u32MessageContext;
2170	IOCReply.SCSIIOError.u8SCSIStatus = pReq->u8ScsiSts;
2171	IOCReply.SCSIIOError.u8SCSIState = MPT_SCSI_IO_ERROR_SCSI_STATE_AUTOSENSE_VALID;
2172	IOCReply.SCSIIOError.u16IOCStatus = 0;
2173	IOCReply.SCSIIOError.u32IOCLogInfo = 0;
2174	IOCReply.SCSIIOError.u32TransferCount = 0;
2175	IOCReply.SCSIIOError.u32SenseCount = sizeof(pReq->abSenseBuffer);
2176	IOCReply.SCSIIOError.u32ResponseInfo = 0;
2177
2178	/* Free the request before posting completion. */
2179	pTgtDev->pDrvMediaEx->pfnIoReqFree(pTgtDev->pDrvMediaEx, pReq->hIoReq);
2180	lsilogicFinishAddressReply(pThis, &IOCReply, false);
2181	}
2182	}
2183
2184	ASMAtomicDecU32(&pTgtDev->cOutstandingRequests);
2185
2186	if (pTgtDev->cOutstandingRequests == 0 && pThis->fSignalIdle)
2187	PDMDevHlpAsyncNotificationCompleted(pThis->pDevInsR3);
2188	}
2189
2190	/**
2191	* Processes a SCSI I/O request by setting up the request
2192	* and sending it to the underlying SCSI driver.
2193	* Steps needed to complete request are done in the
2194	* callback called by the driver below upon completion of
2195	* the request.
2196	*
2197	* @returns VBox status code.
2198	* @param pThis Pointer to the LsiLogic device state.
2199	* @param GCPhysMessageFrameAddr Guest physical address where the request is located.
2200	* @param pGuestReq The request read fro th guest memory.
2201	*/
2202	static int lsilogicR3ProcessSCSIIORequest(PLSILOGICSCSI pThis, RTGCPHYS GCPhysMessageFrameAddr,
2203	PMptRequestUnion pGuestReq)
2204	{
2205	MptReplyUnion IOCReply;
2206	int rc = VINF_SUCCESS;
2207
2208	# ifdef LOG_ENABLED
2209	lsilogicR3DumpSCSIIORequest(&pGuestReq->SCSIIO);
2210	# endif
2211
2212	if (RT_LIKELY( (pGuestReq->SCSIIO.u8TargetID < pThis->cDeviceStates)
2213	&& (pGuestReq->SCSIIO.u8Bus == 0)))
2214	{
2215	PLSILOGICDEVICE pTgtDev = &pThis->paDeviceStates[pGuestReq->SCSIIO.u8TargetID];
2216
2217	if (pTgtDev->pDrvBase)
2218	{
2219	/* Allocate and prepare a new request. */
2220	PDMMEDIAEXIOREQ hIoReq;
2221	PLSILOGICREQ pLsiReq = NULL;
2222	rc = pTgtDev->pDrvMediaEx->pfnIoReqAlloc(pTgtDev->pDrvMediaEx, &hIoReq, (void **)&pLsiReq,
2223	pGuestReq->SCSIIO.u32MessageContext,
2224	PDMIMEDIAEX_F_SUSPEND_ON_RECOVERABLE_ERR);
2225	if (RT_SUCCESS(rc))
2226	{
2227	pLsiReq->hIoReq = hIoReq;
2228	pLsiReq->pTargetDevice = pTgtDev;
2229	pLsiReq->GCPhysMessageFrameAddr = GCPhysMessageFrameAddr;
2230	pLsiReq->fBIOS = false;
2231	pLsiReq->GCPhysSgStart = GCPhysMessageFrameAddr + sizeof(MptSCSIIORequest);
2232	pLsiReq->cChainOffset = pGuestReq->SCSIIO.u8ChainOffset;
2233	if (pLsiReq->cChainOffset)
2234	pLsiReq->cChainOffset = pLsiReq->cChainOffset * sizeof(uint32_t) - sizeof(MptSCSIIORequest);
2235	memcpy(&pLsiReq->GuestRequest, pGuestReq, sizeof(MptRequestUnion));
2236	RT_BZERO(&pLsiReq->abSenseBuffer[0], sizeof(pLsiReq->abSenseBuffer));
2237
2238	PDMMEDIAEXIOREQSCSITXDIR enmXferDir = PDMMEDIAEXIOREQSCSITXDIR_UNKNOWN;
2239	uint8_t uDataDirection = MPT_SCSIIO_REQUEST_CONTROL_TXDIR_GET(pLsiReq->GuestRequest.SCSIIO.u32Control);
2240
2241	if (uDataDirection == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_NONE)
2242	enmXferDir = PDMMEDIAEXIOREQSCSITXDIR_NONE;
2243	else if (uDataDirection == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_WRITE)
2244	enmXferDir = PDMMEDIAEXIOREQSCSITXDIR_TO_DEVICE;
2245	else if (uDataDirection == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_READ)
2246	enmXferDir = PDMMEDIAEXIOREQSCSITXDIR_FROM_DEVICE;
2247
2248	ASMAtomicIncU32(&pTgtDev->cOutstandingRequests);
2249	rc = pTgtDev->pDrvMediaEx->pfnIoReqSendScsiCmd(pTgtDev->pDrvMediaEx, pLsiReq->hIoReq, pLsiReq->GuestRequest.SCSIIO.au8LUN[1],
2250	&pLsiReq->GuestRequest.SCSIIO.au8CDB[0], pLsiReq->GuestRequest.SCSIIO.u8CDBLength,
2251	enmXferDir, pLsiReq->GuestRequest.SCSIIO.u32DataLength,
2252	&pLsiReq->abSenseBuffer[0], sizeof(pLsiReq->abSenseBuffer), &pLsiReq->u8ScsiSts,
2253	30 * RT_MS_1SEC);
2254	if (rc != VINF_PDM_MEDIAEX_IOREQ_IN_PROGRESS)
2255	lsilogicR3ReqComplete(pThis, pLsiReq, rc);
2256
2257	return VINF_SUCCESS;
2258	}
2259	else
2260	IOCReply.SCSIIOError.u16IOCStatus = MPT_SCSI_IO_ERROR_IOCSTATUS_DEVICE_NOT_THERE;
2261	}
2262	else
2263	{
2264	/* Device is not present report SCSI selection timeout. */
2265	IOCReply.SCSIIOError.u16IOCStatus = MPT_SCSI_IO_ERROR_IOCSTATUS_DEVICE_NOT_THERE;
2266	}
2267	}
2268	else
2269	{
2270	/* Report out of bounds target ID or bus. */
2271	if (pGuestReq->SCSIIO.u8Bus != 0)
2272	IOCReply.SCSIIOError.u16IOCStatus = MPT_SCSI_IO_ERROR_IOCSTATUS_INVALID_BUS;
2273	else
2274	IOCReply.SCSIIOError.u16IOCStatus = MPT_SCSI_IO_ERROR_IOCSTATUS_INVALID_TARGETID;
2275	}
2276
2277	static int g_cLogged = 0;
2278
2279	if (g_cLogged++ < MAX_REL_LOG_ERRORS)
2280	{
2281	LogRel(("LsiLogic#%d: %d/%d (Bus/Target) doesn't exist\n", pThis->CTX_SUFF(pDevIns)->iInstance,
2282	pGuestReq->SCSIIO.u8TargetID, pGuestReq->SCSIIO.u8Bus));
2283	/* Log the CDB too */
2284	LogRel(("LsiLogic#%d: Guest issued CDB {%#x",
2285	pThis->CTX_SUFF(pDevIns)->iInstance, pGuestReq->SCSIIO.au8CDB[0]));
2286	for (unsigned i = 1; i < pGuestReq->SCSIIO.u8CDBLength; i++)
2287	LogRel((", %#x", pGuestReq->SCSIIO.au8CDB[i]));
2288	LogRel(("}\n"));
2289	}
2290
2291	/* The rest is equal to both errors. */
2292	IOCReply.SCSIIOError.u8TargetID = pGuestReq->SCSIIO.u8TargetID;
2293	IOCReply.SCSIIOError.u8Bus = pGuestReq->SCSIIO.u8Bus;
2294	IOCReply.SCSIIOError.u8MessageLength = sizeof(MptSCSIIOErrorReply) / 4;
2295	IOCReply.SCSIIOError.u8Function = pGuestReq->SCSIIO.u8Function;
2296	IOCReply.SCSIIOError.u8CDBLength = pGuestReq->SCSIIO.u8CDBLength;
2297	IOCReply.SCSIIOError.u8SenseBufferLength = pGuestReq->SCSIIO.u8SenseBufferLength;
2298	IOCReply.SCSIIOError.u32MessageContext = pGuestReq->SCSIIO.u32MessageContext;
2299	IOCReply.SCSIIOError.u8SCSIStatus = SCSI_STATUS_OK;
2300	IOCReply.SCSIIOError.u8SCSIState = MPT_SCSI_IO_ERROR_SCSI_STATE_TERMINATED;
2301	IOCReply.SCSIIOError.u32IOCLogInfo = 0;
2302	IOCReply.SCSIIOError.u32TransferCount = 0;
2303	IOCReply.SCSIIOError.u32SenseCount = 0;
2304	IOCReply.SCSIIOError.u32ResponseInfo = 0;
2305
2306	lsilogicFinishAddressReply(pThis, &IOCReply, false);
2307
2308	return rc;
2309	}
2310
2311
2312	/**
2313	* @interface_method_impl{PDMIMEDIAPORT,pfnQueryDeviceLocation}
2314	*/
2315	static DECLCALLBACK(int) lsilogicR3QueryDeviceLocation(PPDMIMEDIAPORT pInterface, const char **ppcszController,
2316	uint32_t piInstance, uint32_t piLUN)
2317	{
2318	PLSILOGICDEVICE pTgtDev = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, IMediaPort);
2319	PPDMDEVINS pDevIns = pTgtDev->CTX_SUFF(pLsiLogic)->CTX_SUFF(pDevIns);
2320
2321	AssertPtrReturn(ppcszController, VERR_INVALID_POINTER);
2322	AssertPtrReturn(piInstance, VERR_INVALID_POINTER);
2323	AssertPtrReturn(piLUN, VERR_INVALID_POINTER);
2324
2325	*ppcszController = pDevIns->pReg->szName;
2326	*piInstance = pDevIns->iInstance;
2327	*piLUN = pTgtDev->iLUN;
2328
2329	return VINF_SUCCESS;
2330	}
2331
2332
2333	/**
2334	* @interface_method_impl{PDMIMEDIAEXPORT,pfnIoReqCopyFromBuf}
2335	*/
2336	static DECLCALLBACK(int) lsilogicR3IoReqCopyFromBuf(PPDMIMEDIAEXPORT pInterface, PDMMEDIAEXIOREQ hIoReq,
2337	void *pvIoReqAlloc, uint32_t offDst, PRTSGBUF pSgBuf,
2338	size_t cbCopy)
2339	{
2340	RT_NOREF1(hIoReq);
2341	PLSILOGICDEVICE pTgtDev = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, IMediaExPort);
2342	PLSILOGICREQ pReq = (PLSILOGICREQ)pvIoReqAlloc;
2343
2344	size_t cbCopied = 0;
2345	if (RT_UNLIKELY(pReq->fBIOS))
2346	cbCopied = vboxscsiCopyToBuf(&pTgtDev->CTX_SUFF(pLsiLogic)->VBoxSCSI, pSgBuf, offDst, cbCopy);
2347	else
2348	cbCopied = lsilogicR3CopySgBufToGuest(pTgtDev->CTX_SUFF(pLsiLogic), pReq, pSgBuf, offDst, cbCopy);
2349	return cbCopied == cbCopy ? VINF_SUCCESS : VERR_PDM_MEDIAEX_IOBUF_OVERFLOW;
2350	}
2351
2352	/**
2353	* @interface_method_impl{PDMIMEDIAEXPORT,pfnIoReqCopyToBuf}
2354	*/
2355	static DECLCALLBACK(int) lsilogicR3IoReqCopyToBuf(PPDMIMEDIAEXPORT pInterface, PDMMEDIAEXIOREQ hIoReq,
2356	void *pvIoReqAlloc, uint32_t offSrc, PRTSGBUF pSgBuf,
2357	size_t cbCopy)
2358	{
2359	RT_NOREF1(hIoReq);
2360	PLSILOGICDEVICE pTgtDev = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, IMediaExPort);
2361	PLSILOGICREQ pReq = (PLSILOGICREQ)pvIoReqAlloc;
2362
2363	size_t cbCopied = 0;
2364	if (RT_UNLIKELY(pReq->fBIOS))
2365	cbCopied = vboxscsiCopyFromBuf(&pTgtDev->CTX_SUFF(pLsiLogic)->VBoxSCSI, pSgBuf, offSrc, cbCopy);
2366	else
2367	cbCopied = lsilogicR3CopySgBufFromGuest(pTgtDev->CTX_SUFF(pLsiLogic), pReq, pSgBuf, offSrc, cbCopy);
2368	return cbCopied == cbCopy ? VINF_SUCCESS : VERR_PDM_MEDIAEX_IOBUF_UNDERRUN;
2369	}
2370
2371	/**
2372	* @interface_method_impl{PDMIMEDIAEXPORT,pfnIoReqCompleteNotify}
2373	*/
2374	static DECLCALLBACK(int) lsilogicR3IoReqCompleteNotify(PPDMIMEDIAEXPORT pInterface, PDMMEDIAEXIOREQ hIoReq,
2375	void *pvIoReqAlloc, int rcReq)
2376	{
2377	RT_NOREF(hIoReq);
2378	PLSILOGICDEVICE pTgtDev = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, IMediaExPort);
2379	lsilogicR3ReqComplete(pTgtDev->CTX_SUFF(pLsiLogic), (PLSILOGICREQ)pvIoReqAlloc, rcReq);
2380	return VINF_SUCCESS;
2381	}
2382
2383	/**
2384	* @interface_method_impl{PDMIMEDIAEXPORT,pfnIoReqStateChanged}
2385	*/
2386	static DECLCALLBACK(void) lsilogicR3IoReqStateChanged(PPDMIMEDIAEXPORT pInterface, PDMMEDIAEXIOREQ hIoReq,
2387	void *pvIoReqAlloc, PDMMEDIAEXIOREQSTATE enmState)
2388	{
2389	RT_NOREF3(hIoReq, pvIoReqAlloc, enmState);
2390	PLSILOGICDEVICE pTgtDev = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, IMediaExPort);
2391
2392	switch (enmState)
2393	{
2394	case PDMMEDIAEXIOREQSTATE_SUSPENDED:
2395	{
2396	/* Make sure the request is not accounted for so the VM can suspend successfully. */
2397	uint32_t cTasksActive = ASMAtomicDecU32(&pTgtDev->cOutstandingRequests);
2398	if (!cTasksActive && pTgtDev->CTX_SUFF(pLsiLogic)->fSignalIdle)
2399	PDMDevHlpAsyncNotificationCompleted(pTgtDev->CTX_SUFF(pLsiLogic)->pDevInsR3);
2400	break;
2401	}
2402	case PDMMEDIAEXIOREQSTATE_ACTIVE:
2403	/* Make sure the request is accounted for so the VM suspends only when the request is complete. */
2404	ASMAtomicIncU32(&pTgtDev->cOutstandingRequests);
2405	break;
2406	default:
2407	AssertMsgFailed(("Invalid request state given %u\n", enmState));
2408	}
2409	}
2410
2411	/**
2412	* @interface_method_impl{PDMIMEDIAEXPORT,pfnMediumEjected}
2413	*/
2414	static DECLCALLBACK(void) lsilogicR3MediumEjected(PPDMIMEDIAEXPORT pInterface)
2415	{
2416	PLSILOGICDEVICE pTgtDev = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, IMediaExPort);
2417	PLSILOGICSCSI pThis = pTgtDev->CTX_SUFF(pLsiLogic);
2418
2419	RT_NOREF(pThis); /** @todo */
2420	}
2421
2422
2423	/**
2424	* Return the configuration page header and data
2425	* which matches the given page type and number.
2426	*
2427	* @returns VINF_SUCCESS if successful
2428	* VERR_NOT_FOUND if the requested page could be found.
2429	* @param pThis The LsiLogic controller instance data.
2430	* @param pPages The pages supported by the controller.
2431	* @param u8PageNumber Number of the page to get.
2432	* @param ppPageHeader Where to store the pointer to the page header.
2433	* @param ppbPageData Where to store the pointer to the page data.
2434	* @param pcbPage Where to store the size of the page data in bytes on success.
2435	*/
2436	static int lsilogicR3ConfigurationIOUnitPageGetFromNumber(PLSILOGICSCSI pThis,
2437	PMptConfigurationPagesSupported pPages,
2438	uint8_t u8PageNumber,
2439	PMptConfigurationPageHeader *ppPageHeader,
2440	uint8_t *ppbPageData, size_t pcbPage)
2441	{
2442	RT_NOREF(pThis);
2443	int rc = VINF_SUCCESS;
2444
2445	AssertPtr(ppPageHeader); Assert(ppbPageData);
2446
2447	switch (u8PageNumber)
2448	{
2449	case 0:
2450	*ppPageHeader = &pPages->IOUnitPage0.u.fields.Header;
2451	*ppbPageData = pPages->IOUnitPage0.u.abPageData;
2452	*pcbPage = sizeof(pPages->IOUnitPage0);
2453	break;
2454	case 1:
2455	*ppPageHeader = &pPages->IOUnitPage1.u.fields.Header;
2456	*ppbPageData = pPages->IOUnitPage1.u.abPageData;
2457	*pcbPage = sizeof(pPages->IOUnitPage1);
2458	break;
2459	case 2:
2460	*ppPageHeader = &pPages->IOUnitPage2.u.fields.Header;
2461	*ppbPageData = pPages->IOUnitPage2.u.abPageData;
2462	*pcbPage = sizeof(pPages->IOUnitPage2);
2463	break;
2464	case 3:
2465	*ppPageHeader = &pPages->IOUnitPage3.u.fields.Header;
2466	*ppbPageData = pPages->IOUnitPage3.u.abPageData;
2467	*pcbPage = sizeof(pPages->IOUnitPage3);
2468	break;
2469	case 4:
2470	*ppPageHeader = &pPages->IOUnitPage4.u.fields.Header;
2471	*ppbPageData = pPages->IOUnitPage4.u.abPageData;
2472	*pcbPage = sizeof(pPages->IOUnitPage4);
2473	break;
2474	default:
2475	rc = VERR_NOT_FOUND;
2476	}
2477
2478	return rc;
2479	}
2480
2481	/**
2482	* Return the configuration page header and data
2483	* which matches the given page type and number.
2484	*
2485	* @returns VINF_SUCCESS if successful
2486	* VERR_NOT_FOUND if the requested page could be found.
2487	* @param pThis The LsiLogic controller instance data.
2488	* @param pPages The pages supported by the controller.
2489	* @param u8PageNumber Number of the page to get.
2490	* @param ppPageHeader Where to store the pointer to the page header.
2491	* @param ppbPageData Where to store the pointer to the page data.
2492	* @param pcbPage Where to store the size of the page data in bytes on success.
2493	*/
2494	static int lsilogicR3ConfigurationIOCPageGetFromNumber(PLSILOGICSCSI pThis,
2495	PMptConfigurationPagesSupported pPages,
2496	uint8_t u8PageNumber,
2497	PMptConfigurationPageHeader *ppPageHeader,
2498	uint8_t *ppbPageData, size_t pcbPage)
2499	{
2500	RT_NOREF(pThis);
2501	int rc = VINF_SUCCESS;
2502
2503	AssertPtr(ppPageHeader); Assert(ppbPageData);
2504
2505	switch (u8PageNumber)
2506	{
2507	case 0:
2508	*ppPageHeader = &pPages->IOCPage0.u.fields.Header;
2509	*ppbPageData = pPages->IOCPage0.u.abPageData;
2510	*pcbPage = sizeof(pPages->IOCPage0);
2511	break;
2512	case 1:
2513	*ppPageHeader = &pPages->IOCPage1.u.fields.Header;
2514	*ppbPageData = pPages->IOCPage1.u.abPageData;
2515	*pcbPage = sizeof(pPages->IOCPage1);
2516	break;
2517	case 2:
2518	*ppPageHeader = &pPages->IOCPage2.u.fields.Header;
2519	*ppbPageData = pPages->IOCPage2.u.abPageData;
2520	*pcbPage = sizeof(pPages->IOCPage2);
2521	break;
2522	case 3:
2523	*ppPageHeader = &pPages->IOCPage3.u.fields.Header;
2524	*ppbPageData = pPages->IOCPage3.u.abPageData;
2525	*pcbPage = sizeof(pPages->IOCPage3);
2526	break;
2527	case 4:
2528	*ppPageHeader = &pPages->IOCPage4.u.fields.Header;
2529	*ppbPageData = pPages->IOCPage4.u.abPageData;
2530	*pcbPage = sizeof(pPages->IOCPage4);
2531	break;
2532	case 6:
2533	*ppPageHeader = &pPages->IOCPage6.u.fields.Header;
2534	*ppbPageData = pPages->IOCPage6.u.abPageData;
2535	*pcbPage = sizeof(pPages->IOCPage6);
2536	break;
2537	default:
2538	rc = VERR_NOT_FOUND;
2539	}
2540
2541	return rc;
2542	}
2543
2544	/**
2545	* Return the configuration page header and data
2546	* which matches the given page type and number.
2547	*
2548	* @returns VINF_SUCCESS if successful
2549	* VERR_NOT_FOUND if the requested page could be found.
2550	* @param pThis The LsiLogic controller instance data.
2551	* @param pPages The pages supported by the controller.
2552	* @param u8PageNumber Number of the page to get.
2553	* @param ppPageHeader Where to store the pointer to the page header.
2554	* @param ppbPageData Where to store the pointer to the page data.
2555	* @param pcbPage Where to store the size of the page data in bytes on success.
2556	*/
2557	static int lsilogicR3ConfigurationManufacturingPageGetFromNumber(PLSILOGICSCSI pThis,
2558	PMptConfigurationPagesSupported pPages,
2559	uint8_t u8PageNumber,
2560	PMptConfigurationPageHeader *ppPageHeader,
2561	uint8_t *ppbPageData, size_t pcbPage)
2562	{
2563	int rc = VINF_SUCCESS;
2564
2565	AssertPtr(ppPageHeader); Assert(ppbPageData);
2566
2567	switch (u8PageNumber)
2568	{
2569	case 0:
2570	*ppPageHeader = &pPages->ManufacturingPage0.u.fields.Header;
2571	*ppbPageData = pPages->ManufacturingPage0.u.abPageData;
2572	*pcbPage = sizeof(pPages->ManufacturingPage0);
2573	break;
2574	case 1:
2575	*ppPageHeader = &pPages->ManufacturingPage1.u.fields.Header;
2576	*ppbPageData = pPages->ManufacturingPage1.u.abPageData;
2577	*pcbPage = sizeof(pPages->ManufacturingPage1);
2578	break;
2579	case 2:
2580	*ppPageHeader = &pPages->ManufacturingPage2.u.fields.Header;
2581	*ppbPageData = pPages->ManufacturingPage2.u.abPageData;
2582	*pcbPage = sizeof(pPages->ManufacturingPage2);
2583	break;
2584	case 3:
2585	*ppPageHeader = &pPages->ManufacturingPage3.u.fields.Header;
2586	*ppbPageData = pPages->ManufacturingPage3.u.abPageData;
2587	*pcbPage = sizeof(pPages->ManufacturingPage3);
2588	break;
2589	case 4:
2590	*ppPageHeader = &pPages->ManufacturingPage4.u.fields.Header;
2591	*ppbPageData = pPages->ManufacturingPage4.u.abPageData;
2592	*pcbPage = sizeof(pPages->ManufacturingPage4);
2593	break;
2594	case 5:
2595	*ppPageHeader = &pPages->ManufacturingPage5.u.fields.Header;
2596	*ppbPageData = pPages->ManufacturingPage5.u.abPageData;
2597	*pcbPage = sizeof(pPages->ManufacturingPage5);
2598	break;
2599	case 6:
2600	*ppPageHeader = &pPages->ManufacturingPage6.u.fields.Header;
2601	*ppbPageData = pPages->ManufacturingPage6.u.abPageData;
2602	*pcbPage = sizeof(pPages->ManufacturingPage6);
2603	break;
2604	case 7:
2605	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
2606	{
2607	*ppPageHeader = &pPages->u.SasPages.pManufacturingPage7->u.fields.Header;
2608	*ppbPageData = pPages->u.SasPages.pManufacturingPage7->u.abPageData;
2609	*pcbPage = pPages->u.SasPages.cbManufacturingPage7;
2610	}
2611	else
2612	rc = VERR_NOT_FOUND;
2613	break;
2614	case 8:
2615	*ppPageHeader = &pPages->ManufacturingPage8.u.fields.Header;
2616	*ppbPageData = pPages->ManufacturingPage8.u.abPageData;
2617	*pcbPage = sizeof(pPages->ManufacturingPage8);
2618	break;
2619	case 9:
2620	*ppPageHeader = &pPages->ManufacturingPage9.u.fields.Header;
2621	*ppbPageData = pPages->ManufacturingPage9.u.abPageData;
2622	*pcbPage = sizeof(pPages->ManufacturingPage9);
2623	break;
2624	case 10:
2625	*ppPageHeader = &pPages->ManufacturingPage10.u.fields.Header;
2626	*ppbPageData = pPages->ManufacturingPage10.u.abPageData;
2627	*pcbPage = sizeof(pPages->ManufacturingPage10);
2628	break;
2629	default:
2630	rc = VERR_NOT_FOUND;
2631	}
2632
2633	return rc;
2634	}
2635
2636	/**
2637	* Return the configuration page header and data
2638	* which matches the given page type and number.
2639	*
2640	* @returns VINF_SUCCESS if successful
2641	* VERR_NOT_FOUND if the requested page could be found.
2642	* @param pThis The LsiLogic controller instance data.
2643	* @param pPages The pages supported by the controller.
2644	* @param u8PageNumber Number of the page to get.
2645	* @param ppPageHeader Where to store the pointer to the page header.
2646	* @param ppbPageData Where to store the pointer to the page data.
2647	* @param pcbPage Where to store the size of the page data in bytes on success.
2648	*/
2649	static int lsilogicR3ConfigurationBiosPageGetFromNumber(PLSILOGICSCSI pThis,
2650	PMptConfigurationPagesSupported pPages,
2651	uint8_t u8PageNumber,
2652	PMptConfigurationPageHeader *ppPageHeader,
2653	uint8_t *ppbPageData, size_t pcbPage)
2654	{
2655	RT_NOREF(pThis);
2656	int rc = VINF_SUCCESS;
2657
2658	AssertPtr(ppPageHeader); Assert(ppbPageData);
2659
2660	switch (u8PageNumber)
2661	{
2662	case 1:
2663	*ppPageHeader = &pPages->BIOSPage1.u.fields.Header;
2664	*ppbPageData = pPages->BIOSPage1.u.abPageData;
2665	*pcbPage = sizeof(pPages->BIOSPage1);
2666	break;
2667	case 2:
2668	*ppPageHeader = &pPages->BIOSPage2.u.fields.Header;
2669	*ppbPageData = pPages->BIOSPage2.u.abPageData;
2670	*pcbPage = sizeof(pPages->BIOSPage2);
2671	break;
2672	case 4:
2673	*ppPageHeader = &pPages->BIOSPage4.u.fields.Header;
2674	*ppbPageData = pPages->BIOSPage4.u.abPageData;
2675	*pcbPage = sizeof(pPages->BIOSPage4);
2676	break;
2677	default:
2678	rc = VERR_NOT_FOUND;
2679	}
2680
2681	return rc;
2682	}
2683
2684	/**
2685	* Return the configuration page header and data
2686	* which matches the given page type and number.
2687	*
2688	* @returns VINF_SUCCESS if successful
2689	* VERR_NOT_FOUND if the requested page could be found.
2690	* @param pThis The LsiLogic controller instance data.
2691	* @param pPages The pages supported by the controller.
2692	* @param u8Port The port to retrieve the page for.
2693	* @param u8PageNumber Number of the page to get.
2694	* @param ppPageHeader Where to store the pointer to the page header.
2695	* @param ppbPageData Where to store the pointer to the page data.
2696	* @param pcbPage Where to store the size of the page data in bytes on success.
2697	*/
2698	static int lsilogicR3ConfigurationSCSISPIPortPageGetFromNumber(PLSILOGICSCSI pThis,
2699	PMptConfigurationPagesSupported pPages,
2700	uint8_t u8Port,
2701	uint8_t u8PageNumber,
2702	PMptConfigurationPageHeader *ppPageHeader,
2703	uint8_t *ppbPageData, size_t pcbPage)
2704	{
2705	RT_NOREF(pThis);
2706	int rc = VINF_SUCCESS;
2707	AssertPtr(ppPageHeader); Assert(ppbPageData);
2708
2709
2710	if (u8Port >= RT_ELEMENTS(pPages->u.SpiPages.aPortPages))
2711	return VERR_NOT_FOUND;
2712
2713	switch (u8PageNumber)
2714	{
2715	case 0:
2716	*ppPageHeader = &pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage0.u.fields.Header;
2717	*ppbPageData = pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage0.u.abPageData;
2718	*pcbPage = sizeof(pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage0);
2719	break;
2720	case 1:
2721	*ppPageHeader = &pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage1.u.fields.Header;
2722	*ppbPageData = pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage1.u.abPageData;
2723	*pcbPage = sizeof(pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage1);
2724	break;
2725	case 2:
2726	*ppPageHeader = &pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage2.u.fields.Header;
2727	*ppbPageData = pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage2.u.abPageData;
2728	*pcbPage = sizeof(pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage2);
2729	break;
2730	default:
2731	rc = VERR_NOT_FOUND;
2732	}
2733
2734	return rc;
2735	}
2736
2737	/**
2738	* Return the configuration page header and data
2739	* which matches the given page type and number.
2740	*
2741	* @returns VINF_SUCCESS if successful
2742	* VERR_NOT_FOUND if the requested page could be found.
2743	* @param pThis The LsiLogic controller instance data.
2744	* @param pPages The pages supported by the controller.
2745	* @param u8Bus The bus the device is on the page should be returned.
2746	* @param u8TargetID The target ID of the device to return the page for.
2747	* @param u8PageNumber Number of the page to get.
2748	* @param ppPageHeader Where to store the pointer to the page header.
2749	* @param ppbPageData Where to store the pointer to the page data.
2750	* @param pcbPage Where to store the size of the page data in bytes on success.
2751	*/
2752	static int lsilogicR3ConfigurationSCSISPIDevicePageGetFromNumber(PLSILOGICSCSI pThis,
2753	PMptConfigurationPagesSupported pPages,
2754	uint8_t u8Bus,
2755	uint8_t u8TargetID, uint8_t u8PageNumber,
2756	PMptConfigurationPageHeader *ppPageHeader,
2757	uint8_t *ppbPageData, size_t pcbPage)
2758	{
2759	RT_NOREF(pThis);
2760	int rc = VINF_SUCCESS;
2761	AssertPtr(ppPageHeader); Assert(ppbPageData);
2762
2763	if (u8Bus >= RT_ELEMENTS(pPages->u.SpiPages.aBuses))
2764	return VERR_NOT_FOUND;
2765
2766	if (u8TargetID >= RT_ELEMENTS(pPages->u.SpiPages.aBuses[u8Bus].aDevicePages))
2767	return VERR_NOT_FOUND;
2768
2769	switch (u8PageNumber)
2770	{
2771	case 0:
2772	*ppPageHeader = &pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage0.u.fields.Header;
2773	*ppbPageData = pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage0.u.abPageData;
2774	*pcbPage = sizeof(pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage0);
2775	break;
2776	case 1:
2777	*ppPageHeader = &pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage1.u.fields.Header;
2778	*ppbPageData = pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage1.u.abPageData;
2779	*pcbPage = sizeof(pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage1);
2780	break;
2781	case 2:
2782	*ppPageHeader = &pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage2.u.fields.Header;
2783	*ppbPageData = pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage2.u.abPageData;
2784	*pcbPage = sizeof(pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage2);
2785	break;
2786	case 3:
2787	*ppPageHeader = &pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage3.u.fields.Header;
2788	*ppbPageData = pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage3.u.abPageData;
2789	*pcbPage = sizeof(pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage3);
2790	break;
2791	default:
2792	rc = VERR_NOT_FOUND;
2793	}
2794
2795	return rc;
2796	}
2797
2798	static int lsilogicR3ConfigurationSASIOUnitPageGetFromNumber(PLSILOGICSCSI pThis,
2799	PMptConfigurationPagesSupported pPages,
2800	uint8_t u8PageNumber,
2801	PMptExtendedConfigurationPageHeader *ppPageHeader,
2802	uint8_t *ppbPageData, size_t pcbPage)
2803	{
2804	RT_NOREF(pThis);
2805	int rc = VINF_SUCCESS;
2806
2807	switch (u8PageNumber)
2808	{
2809	case 0:
2810	*ppPageHeader = &pPages->u.SasPages.pSASIOUnitPage0->u.fields.ExtHeader;
2811	*ppbPageData = pPages->u.SasPages.pSASIOUnitPage0->u.abPageData;
2812	*pcbPage = pPages->u.SasPages.cbSASIOUnitPage0;
2813	break;
2814	case 1:
2815	*ppPageHeader = &pPages->u.SasPages.pSASIOUnitPage1->u.fields.ExtHeader;
2816	*ppbPageData = pPages->u.SasPages.pSASIOUnitPage1->u.abPageData;
2817	*pcbPage = pPages->u.SasPages.cbSASIOUnitPage1;
2818	break;
2819	case 2:
2820	*ppPageHeader = &pPages->u.SasPages.SASIOUnitPage2.u.fields.ExtHeader;
2821	*ppbPageData = pPages->u.SasPages.SASIOUnitPage2.u.abPageData;
2822	*pcbPage = sizeof(pPages->u.SasPages.SASIOUnitPage2);
2823	break;
2824	case 3:
2825	*ppPageHeader = &pPages->u.SasPages.SASIOUnitPage3.u.fields.ExtHeader;
2826	*ppbPageData = pPages->u.SasPages.SASIOUnitPage3.u.abPageData;
2827	*pcbPage = sizeof(pPages->u.SasPages.SASIOUnitPage3);
2828	break;
2829	default:
2830	rc = VERR_NOT_FOUND;
2831	}
2832
2833	return rc;
2834	}
2835
2836	static int lsilogicR3ConfigurationSASPHYPageGetFromNumber(PLSILOGICSCSI pThis,
2837	PMptConfigurationPagesSupported pPages,
2838	uint8_t u8PageNumber,
2839	MptConfigurationPageAddress PageAddress,
2840	PMptExtendedConfigurationPageHeader *ppPageHeader,
2841	uint8_t *ppbPageData, size_t pcbPage)
2842	{
2843	RT_NOREF(pThis);
2844	int rc = VINF_SUCCESS;
2845	uint8_t uAddressForm = MPT_CONFIGURATION_PAGE_ADDRESS_GET_SAS_FORM(PageAddress);
2846	PMptConfigurationPagesSas pPagesSas = &pPages->u.SasPages;
2847	PMptPHY pPHYPages = NULL;
2848
2849	Log(("Address form %d\n", uAddressForm));
2850
2851	if (uAddressForm == 0) /* PHY number */
2852	{
2853	uint8_t u8PhyNumber = PageAddress.SASPHY.Form0.u8PhyNumber;
2854
2855	Log(("PHY number %d\n", u8PhyNumber));
2856
2857	if (u8PhyNumber >= pPagesSas->cPHYs)
2858	return VERR_NOT_FOUND;
2859
2860	pPHYPages = &pPagesSas->paPHYs[u8PhyNumber];
2861	}
2862	else if (uAddressForm == 1) /* Index form */
2863	{
2864	uint16_t u16Index = PageAddress.SASPHY.Form1.u16Index;
2865
2866	Log(("PHY index %d\n", u16Index));
2867
2868	if (u16Index >= pPagesSas->cPHYs)
2869	return VERR_NOT_FOUND;
2870
2871	pPHYPages = &pPagesSas->paPHYs[u16Index];
2872	}
2873	else
2874	rc = VERR_NOT_FOUND; /* Correct? */
2875
2876	if (pPHYPages)
2877	{
2878	switch (u8PageNumber)
2879	{
2880	case 0:
2881	*ppPageHeader = &pPHYPages->SASPHYPage0.u.fields.ExtHeader;
2882	*ppbPageData = pPHYPages->SASPHYPage0.u.abPageData;
2883	*pcbPage = sizeof(pPHYPages->SASPHYPage0);
2884	break;
2885	case 1:
2886	*ppPageHeader = &pPHYPages->SASPHYPage1.u.fields.ExtHeader;
2887	*ppbPageData = pPHYPages->SASPHYPage1.u.abPageData;
2888	*pcbPage = sizeof(pPHYPages->SASPHYPage1);
2889	break;
2890	default:
2891	rc = VERR_NOT_FOUND;
2892	}
2893	}
2894	else
2895	rc = VERR_NOT_FOUND;
2896
2897	return rc;
2898	}
2899
2900	static int lsilogicR3ConfigurationSASDevicePageGetFromNumber(PLSILOGICSCSI pThis,
2901	PMptConfigurationPagesSupported pPages,
2902	uint8_t u8PageNumber,
2903	MptConfigurationPageAddress PageAddress,
2904	PMptExtendedConfigurationPageHeader *ppPageHeader,
2905	uint8_t *ppbPageData, size_t pcbPage)
2906	{
2907	RT_NOREF(pThis);
2908	int rc = VINF_SUCCESS;
2909	uint8_t uAddressForm = MPT_CONFIGURATION_PAGE_ADDRESS_GET_SAS_FORM(PageAddress);
2910	PMptConfigurationPagesSas pPagesSas = &pPages->u.SasPages;
2911	PMptSASDevice pSASDevice = NULL;
2912
2913	Log(("Address form %d\n", uAddressForm));
2914
2915	if (uAddressForm == 0)
2916	{
2917	uint16_t u16Handle = PageAddress.SASDevice.Form0And2.u16Handle;
2918
2919	Log(("Get next handle %#x\n", u16Handle));
2920
2921	pSASDevice = pPagesSas->pSASDeviceHead;
2922
2923	/* Get the first device? */
2924	if (u16Handle != 0xffff)
2925	{
2926	/* No, search for the right one. */
2927
2928	while ( pSASDevice
2929	&& pSASDevice->SASDevicePage0.u.fields.u16DevHandle != u16Handle)
2930	pSASDevice = pSASDevice->pNext;
2931
2932	if (pSASDevice)
2933	pSASDevice = pSASDevice->pNext;
2934	}
2935	}
2936	else if (uAddressForm == 1)
2937	{
2938	uint8_t u8TargetID = PageAddress.SASDevice.Form1.u8TargetID;
2939	uint8_t u8Bus = PageAddress.SASDevice.Form1.u8Bus;
2940
2941	Log(("u8TargetID=%d u8Bus=%d\n", u8TargetID, u8Bus));
2942
2943	pSASDevice = pPagesSas->pSASDeviceHead;
2944
2945	while ( pSASDevice
2946	&& ( pSASDevice->SASDevicePage0.u.fields.u8TargetID != u8TargetID
2947	\|\| pSASDevice->SASDevicePage0.u.fields.u8Bus != u8Bus))
2948	pSASDevice = pSASDevice->pNext;
2949	}
2950	else if (uAddressForm == 2)
2951	{
2952	uint16_t u16Handle = PageAddress.SASDevice.Form0And2.u16Handle;
2953
2954	Log(("Handle %#x\n", u16Handle));
2955
2956	pSASDevice = pPagesSas->pSASDeviceHead;
2957
2958	while ( pSASDevice
2959	&& pSASDevice->SASDevicePage0.u.fields.u16DevHandle != u16Handle)
2960	pSASDevice = pSASDevice->pNext;
2961	}
2962
2963	if (pSASDevice)
2964	{
2965	switch (u8PageNumber)
2966	{
2967	case 0:
2968	*ppPageHeader = &pSASDevice->SASDevicePage0.u.fields.ExtHeader;
2969	*ppbPageData = pSASDevice->SASDevicePage0.u.abPageData;
2970	*pcbPage = sizeof(pSASDevice->SASDevicePage0);
2971	break;
2972	case 1:
2973	*ppPageHeader = &pSASDevice->SASDevicePage1.u.fields.ExtHeader;
2974	*ppbPageData = pSASDevice->SASDevicePage1.u.abPageData;
2975	*pcbPage = sizeof(pSASDevice->SASDevicePage1);
2976	break;
2977	case 2:
2978	*ppPageHeader = &pSASDevice->SASDevicePage2.u.fields.ExtHeader;
2979	*ppbPageData = pSASDevice->SASDevicePage2.u.abPageData;
2980	*pcbPage = sizeof(pSASDevice->SASDevicePage2);
2981	break;
2982	default:
2983	rc = VERR_NOT_FOUND;
2984	}
2985	}
2986	else
2987	rc = VERR_NOT_FOUND;
2988
2989	return rc;
2990	}
2991
2992	/**
2993	* Returns the extended configuration page header and data.
2994	* @returns VINF_SUCCESS if successful
2995	* VERR_NOT_FOUND if the requested page could be found.
2996	* @param pThis Pointer to the LsiLogic device state.
2997	* @param pConfigurationReq The configuration request.
2998	* @param ppPageHeader Where to return the pointer to the page header on success.
2999	* @param ppbPageData Where to store the pointer to the page data.
3000	* @param pcbPage Where to store the size of the page in bytes.
3001	*/
3002	static int lsilogicR3ConfigurationPageGetExtended(PLSILOGICSCSI pThis, PMptConfigurationRequest pConfigurationReq,
3003	PMptExtendedConfigurationPageHeader *ppPageHeader,
3004	uint8_t *ppbPageData, size_t pcbPage)
3005	{
3006	int rc = VINF_SUCCESS;
3007
3008	Log(("Extended page requested:\n"));
3009	Log(("u8ExtPageType=%#x\n", pConfigurationReq->u8ExtPageType));
3010	Log(("u8ExtPageLength=%d\n", pConfigurationReq->u16ExtPageLength));
3011
3012	switch (pConfigurationReq->u8ExtPageType)
3013	{
3014	case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT:
3015	{
3016	rc = lsilogicR3ConfigurationSASIOUnitPageGetFromNumber(pThis,
3017	pThis->pConfigurationPages,
3018	pConfigurationReq->u8PageNumber,
3019	ppPageHeader, ppbPageData, pcbPage);
3020	break;
3021	}
3022	case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASPHYS:
3023	{
3024	rc = lsilogicR3ConfigurationSASPHYPageGetFromNumber(pThis,
3025	pThis->pConfigurationPages,
3026	pConfigurationReq->u8PageNumber,
3027	pConfigurationReq->PageAddress,
3028	ppPageHeader, ppbPageData, pcbPage);
3029	break;
3030	}
3031	case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASDEVICE:
3032	{
3033	rc = lsilogicR3ConfigurationSASDevicePageGetFromNumber(pThis,
3034	pThis->pConfigurationPages,
3035	pConfigurationReq->u8PageNumber,
3036	pConfigurationReq->PageAddress,
3037	ppPageHeader, ppbPageData, pcbPage);
3038	break;
3039	}
3040	case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASEXPANDER: /* No expanders supported */
3041	case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_ENCLOSURE: /* No enclosures supported */
3042	default:
3043	rc = VERR_NOT_FOUND;
3044	}
3045
3046	return rc;
3047	}
3048
3049	/**
3050	* Processes a Configuration request.
3051	*
3052	* @returns VBox status code.
3053	* @param pThis Pointer to the LsiLogic device state.
3054	* @param pConfigurationReq Pointer to the request structure.
3055	* @param pReply Pointer to the reply message frame
3056	*/
3057	static int lsilogicR3ProcessConfigurationRequest(PLSILOGICSCSI pThis, PMptConfigurationRequest pConfigurationReq,
3058	PMptConfigurationReply pReply)
3059	{
3060	int rc = VINF_SUCCESS;
3061	uint8_t *pbPageData = NULL;
3062	PMptConfigurationPageHeader pPageHeader = NULL;
3063	PMptExtendedConfigurationPageHeader pExtPageHeader = NULL;
3064	uint8_t u8PageType;
3065	uint8_t u8PageAttribute;
3066	size_t cbPage = 0;
3067
3068	LogFlowFunc(("pThis=%#p\n", pThis));
3069
3070	u8PageType = MPT_CONFIGURATION_PAGE_TYPE_GET(pConfigurationReq->u8PageType);
3071	u8PageAttribute = MPT_CONFIGURATION_PAGE_ATTRIBUTE_GET(pConfigurationReq->u8PageType);
3072
3073	Log(("GuestRequest:\n"));
3074	Log(("u8Action=%#x\n", pConfigurationReq->u8Action));
3075	Log(("u8PageType=%#x\n", u8PageType));
3076	Log(("u8PageNumber=%d\n", pConfigurationReq->u8PageNumber));
3077	Log(("u8PageLength=%d\n", pConfigurationReq->u8PageLength));
3078	Log(("u8PageVersion=%d\n", pConfigurationReq->u8PageVersion));
3079
3080	/* Copy common bits from the request into the reply. */
3081	pReply->u8MessageLength = 6; /* 6 32bit D-Words. */
3082	pReply->u8Action = pConfigurationReq->u8Action;
3083	pReply->u8Function = pConfigurationReq->u8Function;
3084	pReply->u32MessageContext = pConfigurationReq->u32MessageContext;
3085
3086	switch (u8PageType)
3087	{
3088	case MPT_CONFIGURATION_PAGE_TYPE_IO_UNIT:
3089	{
3090	/* Get the page data. */
3091	rc = lsilogicR3ConfigurationIOUnitPageGetFromNumber(pThis,
3092	pThis->pConfigurationPages,
3093	pConfigurationReq->u8PageNumber,
3094	&pPageHeader, &pbPageData, &cbPage);
3095	break;
3096	}
3097	case MPT_CONFIGURATION_PAGE_TYPE_IOC:
3098	{
3099	/* Get the page data. */
3100	rc = lsilogicR3ConfigurationIOCPageGetFromNumber(pThis,
3101	pThis->pConfigurationPages,
3102	pConfigurationReq->u8PageNumber,
3103	&pPageHeader, &pbPageData, &cbPage);
3104	break;
3105	}
3106	case MPT_CONFIGURATION_PAGE_TYPE_MANUFACTURING:
3107	{
3108	/* Get the page data. */
3109	rc = lsilogicR3ConfigurationManufacturingPageGetFromNumber(pThis,
3110	pThis->pConfigurationPages,
3111	pConfigurationReq->u8PageNumber,
3112	&pPageHeader, &pbPageData, &cbPage);
3113	break;
3114	}
3115	case MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_PORT:
3116	{
3117	/* Get the page data. */
3118	rc = lsilogicR3ConfigurationSCSISPIPortPageGetFromNumber(pThis,
3119	pThis->pConfigurationPages,
3120	pConfigurationReq->PageAddress.MPIPortNumber.u8PortNumber,
3121	pConfigurationReq->u8PageNumber,
3122	&pPageHeader, &pbPageData, &cbPage);
3123	break;
3124	}
3125	case MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE:
3126	{
3127	/* Get the page data. */
3128	rc = lsilogicR3ConfigurationSCSISPIDevicePageGetFromNumber(pThis,
3129	pThis->pConfigurationPages,
3130	pConfigurationReq->PageAddress.BusAndTargetId.u8Bus,
3131	pConfigurationReq->PageAddress.BusAndTargetId.u8TargetID,
3132	pConfigurationReq->u8PageNumber,
3133	&pPageHeader, &pbPageData, &cbPage);
3134	break;
3135	}
3136	case MPT_CONFIGURATION_PAGE_TYPE_BIOS:
3137	{
3138	rc = lsilogicR3ConfigurationBiosPageGetFromNumber(pThis,
3139	pThis->pConfigurationPages,
3140	pConfigurationReq->u8PageNumber,
3141	&pPageHeader, &pbPageData, &cbPage);
3142	break;
3143	}
3144	case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED:
3145	{
3146	rc = lsilogicR3ConfigurationPageGetExtended(pThis,
3147	pConfigurationReq,
3148	&pExtPageHeader, &pbPageData, &cbPage);
3149	break;
3150	}
3151	default:
3152	rc = VERR_NOT_FOUND;
3153	}
3154
3155	if (rc == VERR_NOT_FOUND)
3156	{
3157	Log(("Page not found\n"));
3158	pReply->u8PageType = pConfigurationReq->u8PageType;
3159	pReply->u8PageNumber = pConfigurationReq->u8PageNumber;
3160	pReply->u8PageLength = pConfigurationReq->u8PageLength;
3161	pReply->u8PageVersion = pConfigurationReq->u8PageVersion;
3162	pReply->u16IOCStatus = MPT_IOCSTATUS_CONFIG_INVALID_PAGE;
3163	return VINF_SUCCESS;
3164	}
3165
3166	if (u8PageType == MPT_CONFIGURATION_PAGE_TYPE_EXTENDED)
3167	{
3168	pReply->u8PageType = pExtPageHeader->u8PageType;
3169	pReply->u8PageNumber = pExtPageHeader->u8PageNumber;
3170	pReply->u8PageVersion = pExtPageHeader->u8PageVersion;
3171	pReply->u8ExtPageType = pExtPageHeader->u8ExtPageType;
3172	pReply->u16ExtPageLength = pExtPageHeader->u16ExtPageLength;
3173
3174	for (int i = 0; i < pExtPageHeader->u16ExtPageLength; i++)
3175	LogFlowFunc(("PageData[%d]=%#x\n", i, ((uint32_t *)pbPageData)[i]));
3176	}
3177	else
3178	{
3179	pReply->u8PageType = pPageHeader->u8PageType;
3180	pReply->u8PageNumber = pPageHeader->u8PageNumber;
3181	pReply->u8PageLength = pPageHeader->u8PageLength;
3182	pReply->u8PageVersion = pPageHeader->u8PageVersion;
3183
3184	for (int i = 0; i < pReply->u8PageLength; i++)
3185	LogFlowFunc(("PageData[%d]=%#x\n", i, ((uint32_t *)pbPageData)[i]));
3186	}
3187
3188	/*
3189	* Don't use the scatter gather handling code as the configuration request always have only one
3190	* simple element.
3191	*/
3192	switch (pConfigurationReq->u8Action)
3193	{
3194	case MPT_CONFIGURATION_REQUEST_ACTION_DEFAULT: /* Nothing to do. We are always using the defaults. */
3195	case MPT_CONFIGURATION_REQUEST_ACTION_HEADER:
3196	{
3197	/* Already copied above nothing to do. */
3198	break;
3199	}
3200	case MPT_CONFIGURATION_REQUEST_ACTION_READ_NVRAM:
3201	case MPT_CONFIGURATION_REQUEST_ACTION_READ_CURRENT:
3202	case MPT_CONFIGURATION_REQUEST_ACTION_READ_DEFAULT:
3203	{
3204	uint32_t cbBuffer = pConfigurationReq->SimpleSGElement.u24Length;
3205	if (cbBuffer != 0)
3206	{
3207	RTGCPHYS GCPhysAddrPageBuffer = pConfigurationReq->SimpleSGElement.u32DataBufferAddressLow;
3208	if (pConfigurationReq->SimpleSGElement.f64BitAddress)
3209	GCPhysAddrPageBuffer \|= (uint64_t)pConfigurationReq->SimpleSGElement.u32DataBufferAddressHigh << 32;
3210
3211	PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhysAddrPageBuffer, pbPageData, RT_MIN(cbBuffer, cbPage));
3212	}
3213	break;
3214	}
3215	case MPT_CONFIGURATION_REQUEST_ACTION_WRITE_CURRENT:
3216	case MPT_CONFIGURATION_REQUEST_ACTION_WRITE_NVRAM:
3217	{
3218	uint32_t cbBuffer = pConfigurationReq->SimpleSGElement.u24Length;
3219	if (cbBuffer != 0)
3220	{
3221	RTGCPHYS GCPhysAddrPageBuffer = pConfigurationReq->SimpleSGElement.u32DataBufferAddressLow;
3222	if (pConfigurationReq->SimpleSGElement.f64BitAddress)
3223	GCPhysAddrPageBuffer \|= (uint64_t)pConfigurationReq->SimpleSGElement.u32DataBufferAddressHigh << 32;
3224
3225	LogFlow(("cbBuffer=%u cbPage=%u\n", cbBuffer, cbPage));
3226
3227	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhysAddrPageBuffer, pbPageData,
3228	RT_MIN(cbBuffer, cbPage));
3229	}
3230	break;
3231	}
3232	default:
3233	AssertMsgFailed(("todo\n"));
3234	}
3235
3236	return VINF_SUCCESS;
3237	}
3238
3239	/**
3240	* Initializes the configuration pages for the SPI SCSI controller.
3241	*
3242	* @returns nothing
3243	* @param pThis Pointer to the LsiLogic device state.
3244	*/
3245	static void lsilogicR3InitializeConfigurationPagesSpi(PLSILOGICSCSI pThis)
3246	{
3247	PMptConfigurationPagesSpi pPages = &pThis->pConfigurationPages->u.SpiPages;
3248
3249	AssertMsg(pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI, ("Controller is not the SPI SCSI one\n"));
3250
3251	LogFlowFunc(("pThis=%#p\n", pThis));
3252
3253	/* Clear everything first. */
3254	memset(pPages, 0, sizeof(MptConfigurationPagesSpi));
3255
3256	for (unsigned i = 0; i < RT_ELEMENTS(pPages->aPortPages); i++)
3257	{
3258	/* SCSI-SPI port page 0. */
3259	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3260	\| MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_PORT;
3261	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.Header.u8PageNumber = 0;
3262	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIPort0) / 4;
3263	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.fInformationUnitTransfersCapable = true;
3264	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.fDTCapable = true;
3265	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.fQASCapable = true;
3266	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.u8MinimumSynchronousTransferPeriod = 0;
3267	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.u8MaximumSynchronousOffset = 0xff;
3268	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.fWide = true;
3269	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.fAIPCapable = true;
3270	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.u2SignalingType = 0x3; /* Single Ended. */
3271
3272	/* SCSI-SPI port page 1. */
3273	pPages->aPortPages[i].SCSISPIPortPage1.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE
3274	\| MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_PORT;
3275	pPages->aPortPages[i].SCSISPIPortPage1.u.fields.Header.u8PageNumber = 1;
3276	pPages->aPortPages[i].SCSISPIPortPage1.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIPort1) / 4;
3277	pPages->aPortPages[i].SCSISPIPortPage1.u.fields.u8SCSIID = 7;
3278	pPages->aPortPages[i].SCSISPIPortPage1.u.fields.u16PortResponseIDsBitmask = (1 << 7);
3279	pPages->aPortPages[i].SCSISPIPortPage1.u.fields.u32OnBusTimerValue = 0;
3280
3281	/* SCSI-SPI port page 2. */
3282	pPages->aPortPages[i].SCSISPIPortPage2.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE
3283	\| MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_PORT;
3284	pPages->aPortPages[i].SCSISPIPortPage2.u.fields.Header.u8PageNumber = 2;
3285	pPages->aPortPages[i].SCSISPIPortPage2.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIPort2) / 4;
3286	pPages->aPortPages[i].SCSISPIPortPage2.u.fields.u4HostSCSIID = 7;
3287	pPages->aPortPages[i].SCSISPIPortPage2.u.fields.u2InitializeHBA = 0x3;
3288	pPages->aPortPages[i].SCSISPIPortPage2.u.fields.fTerminationDisabled = true;
3289	for (unsigned iDevice = 0; iDevice < RT_ELEMENTS(pPages->aPortPages[i].SCSISPIPortPage2.u.fields.aDeviceSettings); iDevice++)
3290	{
3291	pPages->aPortPages[i].SCSISPIPortPage2.u.fields.aDeviceSettings[iDevice].fBootChoice = true;
3292	}
3293	/* Everything else 0 for now. */
3294	}
3295
3296	for (unsigned uBusCurr = 0; uBusCurr < RT_ELEMENTS(pPages->aBuses); uBusCurr++)
3297	{
3298	for (unsigned uDeviceCurr = 0; uDeviceCurr < RT_ELEMENTS(pPages->aBuses[uBusCurr].aDevicePages); uDeviceCurr++)
3299	{
3300	/* SCSI-SPI device page 0. */
3301	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage0.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3302	\| MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE;
3303	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage0.u.fields.Header.u8PageNumber = 0;
3304	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage0.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIDevice0) / 4;
3305	/* Everything else 0 for now. */
3306
3307	/* SCSI-SPI device page 1. */
3308	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage1.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE
3309	\| MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE;
3310	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage1.u.fields.Header.u8PageNumber = 1;
3311	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage1.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIDevice1) / 4;
3312	/* Everything else 0 for now. */
3313
3314	/* SCSI-SPI device page 2. */
3315	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage2.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE
3316	\| MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE;
3317	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage2.u.fields.Header.u8PageNumber = 2;
3318	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage2.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIDevice2) / 4;
3319	/* Everything else 0 for now. */
3320
3321	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage3.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3322	\| MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE;
3323	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage3.u.fields.Header.u8PageNumber = 3;
3324	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage3.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIDevice3) / 4;
3325	/* Everything else 0 for now. */
3326	}
3327	}
3328	}
3329
3330	/**
3331	* Generates a handle.
3332	*
3333	* @returns the handle.
3334	* @param pThis Pointer to the LsiLogic device state.
3335	*/
3336	DECLINLINE(uint16_t) lsilogicGetHandle(PLSILOGICSCSI pThis)
3337	{
3338	uint16_t u16Handle = pThis->u16NextHandle++;
3339	return u16Handle;
3340	}
3341
3342	/**
3343	* Generates a SAS address (WWID)
3344	*
3345	* @returns nothing.
3346	* @param pSASAddress Pointer to an unitialised SAS address.
3347	* @param iId iId which will go into the address.
3348	*
3349	* @todo Generate better SAS addresses. (Request a block from SUN probably)
3350	*/
3351	void lsilogicSASAddressGenerate(PSASADDRESS pSASAddress, unsigned iId)
3352	{
3353	pSASAddress->u8Address[0] = (0x5 << 5);
3354	pSASAddress->u8Address[1] = 0x01;
3355	pSASAddress->u8Address[2] = 0x02;
3356	pSASAddress->u8Address[3] = 0x03;
3357	pSASAddress->u8Address[4] = 0x04;
3358	pSASAddress->u8Address[5] = 0x05;
3359	pSASAddress->u8Address[6] = 0x06;
3360	pSASAddress->u8Address[7] = iId;
3361	}
3362
3363	/**
3364	* Initializes the configuration pages for the SAS SCSI controller.
3365	*
3366	* @returns nothing
3367	* @param pThis Pointer to the LsiLogic device state.
3368	*/
3369	static void lsilogicR3InitializeConfigurationPagesSas(PLSILOGICSCSI pThis)
3370	{
3371	PMptConfigurationPagesSas pPages = &pThis->pConfigurationPages->u.SasPages;
3372
3373	AssertMsg(pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS, ("Controller is not the SAS SCSI one\n"));
3374
3375	LogFlowFunc(("pThis=%#p\n", pThis));
3376
3377	/* Manufacturing Page 7 - Connector settings. */
3378	pPages->cbManufacturingPage7 = LSILOGICSCSI_MANUFACTURING7_GET_SIZE(pThis->cPorts);
3379	PMptConfigurationPageManufacturing7 pManufacturingPage7 = (PMptConfigurationPageManufacturing7)RTMemAllocZ(pPages->cbManufacturingPage7);
3380	AssertPtr(pManufacturingPage7);
3381	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(pManufacturingPage7,
3382	0, 7,
3383	MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3384	/* Set size manually. */
3385	if (pPages->cbManufacturingPage7 / 4 > 255)
3386	pManufacturingPage7->u.fields.Header.u8PageLength = 255;
3387	else
3388	pManufacturingPage7->u.fields.Header.u8PageLength = pPages->cbManufacturingPage7 / 4;
3389	pManufacturingPage7->u.fields.u8NumPhys = pThis->cPorts;
3390	pPages->pManufacturingPage7 = pManufacturingPage7;
3391
3392	/* SAS I/O unit page 0 - Port specific information. */
3393	pPages->cbSASIOUnitPage0 = LSILOGICSCSI_SASIOUNIT0_GET_SIZE(pThis->cPorts);
3394	PMptConfigurationPageSASIOUnit0 pSASPage0 = (PMptConfigurationPageSASIOUnit0)RTMemAllocZ(pPages->cbSASIOUnitPage0);
3395	AssertPtr(pSASPage0);
3396
3397	MPT_CONFIG_EXTENDED_PAGE_HEADER_INIT(pSASPage0, pPages->cbSASIOUnitPage0,
3398	0, MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY,
3399	MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT);
3400	pSASPage0->u.fields.u8NumPhys = pThis->cPorts;
3401	pPages->pSASIOUnitPage0 = pSASPage0;
3402
3403	/* SAS I/O unit page 1 - Port specific settings. */
3404	pPages->cbSASIOUnitPage1 = LSILOGICSCSI_SASIOUNIT1_GET_SIZE(pThis->cPorts);
3405	PMptConfigurationPageSASIOUnit1 pSASPage1 = (PMptConfigurationPageSASIOUnit1)RTMemAllocZ(pPages->cbSASIOUnitPage1);
3406	AssertPtr(pSASPage1);
3407
3408	MPT_CONFIG_EXTENDED_PAGE_HEADER_INIT(pSASPage1, pPages->cbSASIOUnitPage1,
3409	1, MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE,
3410	MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT);
3411	pSASPage1->u.fields.u8NumPhys = pSASPage0->u.fields.u8NumPhys;
3412	pSASPage1->u.fields.u16ControlFlags = 0;
3413	pSASPage1->u.fields.u16AdditionalControlFlags = 0;
3414	pPages->pSASIOUnitPage1 = pSASPage1;
3415
3416	/* SAS I/O unit page 2 - Port specific information. */
3417	pPages->SASIOUnitPage2.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3418	\| MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3419	pPages->SASIOUnitPage2.u.fields.ExtHeader.u8PageNumber = 2;
3420	pPages->SASIOUnitPage2.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT;
3421	pPages->SASIOUnitPage2.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASIOUnit2) / 4;
3422
3423	/* SAS I/O unit page 3 - Port specific information. */
3424	pPages->SASIOUnitPage3.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3425	\| MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3426	pPages->SASIOUnitPage3.u.fields.ExtHeader.u8PageNumber = 3;
3427	pPages->SASIOUnitPage3.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT;
3428	pPages->SASIOUnitPage3.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASIOUnit3) / 4;
3429
3430	pPages->cPHYs = pThis->cPorts;
3431	pPages->paPHYs = (PMptPHY)RTMemAllocZ(pPages->cPHYs * sizeof(MptPHY));
3432	AssertPtr(pPages->paPHYs);
3433
3434	/* Initialize the PHY configuration */
3435	for (unsigned i = 0; i < pThis->cPorts; i++)
3436	{
3437	PMptPHY pPHYPages = &pPages->paPHYs[i];
3438	uint16_t u16ControllerHandle = lsilogicGetHandle(pThis);
3439
3440	pManufacturingPage7->u.fields.aPHY[i].u8Location = LSILOGICSCSI_MANUFACTURING7_LOCATION_AUTO;
3441
3442	pSASPage0->u.fields.aPHY[i].u8Port = i;
3443	pSASPage0->u.fields.aPHY[i].u8PortFlags = 0;
3444	pSASPage0->u.fields.aPHY[i].u8PhyFlags = 0;
3445	pSASPage0->u.fields.aPHY[i].u8NegotiatedLinkRate = LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_FAILED;
3446	pSASPage0->u.fields.aPHY[i].u32ControllerPhyDeviceInfo = LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_SET(LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_NO);
3447	pSASPage0->u.fields.aPHY[i].u16ControllerDevHandle = u16ControllerHandle;
3448	pSASPage0->u.fields.aPHY[i].u16AttachedDevHandle = 0; /* No device attached. */
3449	pSASPage0->u.fields.aPHY[i].u32DiscoveryStatus = 0; /* No errors */
3450
3451	pSASPage1->u.fields.aPHY[i].u8Port = i;
3452	pSASPage1->u.fields.aPHY[i].u8PortFlags = 0;
3453	pSASPage1->u.fields.aPHY[i].u8PhyFlags = 0;
3454	pSASPage1->u.fields.aPHY[i].u8MaxMinLinkRate = LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MIN_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_15GB)
3455	\| LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MAX_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_30GB);
3456	pSASPage1->u.fields.aPHY[i].u32ControllerPhyDeviceInfo = LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_SET(LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_NO);
3457
3458	/* SAS PHY page 0. */
3459	pPHYPages->SASPHYPage0.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3460	\| MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3461	pPHYPages->SASPHYPage0.u.fields.ExtHeader.u8PageNumber = 0;
3462	pPHYPages->SASPHYPage0.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASPHYS;
3463	pPHYPages->SASPHYPage0.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASPHY0) / 4;
3464	pPHYPages->SASPHYPage0.u.fields.u8AttachedPhyIdentifier = i;
3465	pPHYPages->SASPHYPage0.u.fields.u32AttachedDeviceInfo = LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_SET(LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_NO);
3466	pPHYPages->SASPHYPage0.u.fields.u8ProgrammedLinkRate = LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MIN_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_15GB)
3467	\| LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MAX_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_30GB);
3468	pPHYPages->SASPHYPage0.u.fields.u8HwLinkRate = LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MIN_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_15GB)
3469	\| LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MAX_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_30GB);
3470
3471	/* SAS PHY page 1. */
3472	pPHYPages->SASPHYPage1.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3473	\| MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3474	pPHYPages->SASPHYPage1.u.fields.ExtHeader.u8PageNumber = 1;
3475	pPHYPages->SASPHYPage1.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASPHYS;
3476	pPHYPages->SASPHYPage1.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASPHY1) / 4;
3477
3478	/* Settings for present devices. */
3479	if (pThis->paDeviceStates[i].pDrvBase)
3480	{
3481	uint16_t u16DeviceHandle = lsilogicGetHandle(pThis);
3482	SASADDRESS SASAddress;
3483	PMptSASDevice pSASDevice = (PMptSASDevice)RTMemAllocZ(sizeof(MptSASDevice));
3484	AssertPtr(pSASDevice);
3485
3486	memset(&SASAddress, 0, sizeof(SASADDRESS));
3487	lsilogicSASAddressGenerate(&SASAddress, i);
3488
3489	pSASPage0->u.fields.aPHY[i].u8NegotiatedLinkRate = LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_SET(LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_30GB);
3490	pSASPage0->u.fields.aPHY[i].u32ControllerPhyDeviceInfo = LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_SET(LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_END)
3491	\| LSILOGICSCSI_SASIOUNIT0_DEVICE_SSP_TARGET;
3492	pSASPage0->u.fields.aPHY[i].u16AttachedDevHandle = u16DeviceHandle;
3493	pSASPage1->u.fields.aPHY[i].u32ControllerPhyDeviceInfo = LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_SET(LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_END)
3494	\| LSILOGICSCSI_SASIOUNIT0_DEVICE_SSP_TARGET;
3495	pSASPage0->u.fields.aPHY[i].u16ControllerDevHandle = u16DeviceHandle;
3496
3497	pPHYPages->SASPHYPage0.u.fields.u32AttachedDeviceInfo = LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_SET(LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_END);
3498	pPHYPages->SASPHYPage0.u.fields.SASAddress = SASAddress;
3499	pPHYPages->SASPHYPage0.u.fields.u16OwnerDevHandle = u16DeviceHandle;
3500	pPHYPages->SASPHYPage0.u.fields.u16AttachedDevHandle = u16DeviceHandle;
3501
3502	/* SAS device page 0. */
3503	pSASDevice->SASDevicePage0.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3504	\| MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3505	pSASDevice->SASDevicePage0.u.fields.ExtHeader.u8PageNumber = 0;
3506	pSASDevice->SASDevicePage0.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASDEVICE;
3507	pSASDevice->SASDevicePage0.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASDevice0) / 4;
3508	pSASDevice->SASDevicePage0.u.fields.SASAddress = SASAddress;
3509	pSASDevice->SASDevicePage0.u.fields.u16ParentDevHandle = u16ControllerHandle;
3510	pSASDevice->SASDevicePage0.u.fields.u8PhyNum = i;
3511	pSASDevice->SASDevicePage0.u.fields.u8AccessStatus = LSILOGICSCSI_SASDEVICE0_STATUS_NO_ERRORS;
3512	pSASDevice->SASDevicePage0.u.fields.u16DevHandle = u16DeviceHandle;
3513	pSASDevice->SASDevicePage0.u.fields.u8TargetID = i;
3514	pSASDevice->SASDevicePage0.u.fields.u8Bus = 0;
3515	pSASDevice->SASDevicePage0.u.fields.u32DeviceInfo = LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_SET(LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_END)
3516	\| LSILOGICSCSI_SASIOUNIT0_DEVICE_SSP_TARGET;
3517	pSASDevice->SASDevicePage0.u.fields.u16Flags = LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_PRESENT
3518	\| LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_MAPPED_TO_BUS_AND_TARGET_ID
3519	\| LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_MAPPING_PERSISTENT;
3520	pSASDevice->SASDevicePage0.u.fields.u8PhysicalPort = i;
3521
3522	/* SAS device page 1. */
3523	pSASDevice->SASDevicePage1.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3524	\| MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3525	pSASDevice->SASDevicePage1.u.fields.ExtHeader.u8PageNumber = 1;
3526	pSASDevice->SASDevicePage1.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASDEVICE;
3527	pSASDevice->SASDevicePage1.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASDevice1) / 4;
3528	pSASDevice->SASDevicePage1.u.fields.SASAddress = SASAddress;
3529	pSASDevice->SASDevicePage1.u.fields.u16DevHandle = u16DeviceHandle;
3530	pSASDevice->SASDevicePage1.u.fields.u8TargetID = i;
3531	pSASDevice->SASDevicePage1.u.fields.u8Bus = 0;
3532
3533	/* SAS device page 2. */
3534	pSASDevice->SASDevicePage2.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3535	\| MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3536	pSASDevice->SASDevicePage2.u.fields.ExtHeader.u8PageNumber = 2;
3537	pSASDevice->SASDevicePage2.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASDEVICE;
3538	pSASDevice->SASDevicePage2.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASDevice2) / 4;
3539	pSASDevice->SASDevicePage2.u.fields.SASAddress = SASAddress;
3540
3541	/* Link into device list. */
3542	if (!pPages->cDevices)
3543	{
3544	pPages->pSASDeviceHead = pSASDevice;
3545	pPages->pSASDeviceTail = pSASDevice;
3546	pPages->cDevices = 1;
3547	}
3548	else
3549	{
3550	pSASDevice->pPrev = pPages->pSASDeviceTail;
3551	pPages->pSASDeviceTail->pNext = pSASDevice;
3552	pPages->pSASDeviceTail = pSASDevice;
3553	pPages->cDevices++;
3554	}
3555	}
3556	}
3557	}
3558
3559	/**
3560	* Initializes the configuration pages.
3561	*
3562	* @returns nothing
3563	* @param pThis Pointer to the LsiLogic device state.
3564	*/
3565	static void lsilogicR3InitializeConfigurationPages(PLSILOGICSCSI pThis)
3566	{
3567	/* Initialize the common pages. */
3568	PMptConfigurationPagesSupported pPages = (PMptConfigurationPagesSupported)RTMemAllocZ(sizeof(MptConfigurationPagesSupported));
3569
3570	pThis->pConfigurationPages = pPages;
3571
3572	LogFlowFunc(("pThis=%#p\n", pThis));
3573
3574	/* Clear everything first. */
3575	memset(pPages, 0, sizeof(MptConfigurationPagesSupported));
3576
3577	/* Manufacturing Page 0. */
3578	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage0,
3579	MptConfigurationPageManufacturing0, 0,
3580	MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3581	strncpy((char *)pPages->ManufacturingPage0.u.fields.abChipName, "VBox MPT Fusion", 16);
3582	strncpy((char *)pPages->ManufacturingPage0.u.fields.abChipRevision, "1.0", 8);
3583	strncpy((char *)pPages->ManufacturingPage0.u.fields.abBoardName, "VBox MPT Fusion", 16);
3584	strncpy((char *)pPages->ManufacturingPage0.u.fields.abBoardAssembly, "SUN", 8);
3585	strncpy((char *)pPages->ManufacturingPage0.u.fields.abBoardTracerNumber, "CAFECAFECAFECAFE", 16);
3586
3587	/* Manufacturing Page 1 - I don't know what this contains so we leave it 0 for now. */
3588	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage1,
3589	MptConfigurationPageManufacturing1, 1,
3590	MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3591
3592	/* Manufacturing Page 2. */
3593	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage2,
3594	MptConfigurationPageManufacturing2, 2,
3595	MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3596
3597	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
3598	{
3599	pPages->ManufacturingPage2.u.fields.u16PCIDeviceID = LSILOGICSCSI_PCI_SPI_DEVICE_ID;
3600	pPages->ManufacturingPage2.u.fields.u8PCIRevisionID = LSILOGICSCSI_PCI_SPI_REVISION_ID;
3601	}
3602	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
3603	{
3604	pPages->ManufacturingPage2.u.fields.u16PCIDeviceID = LSILOGICSCSI_PCI_SAS_DEVICE_ID;
3605	pPages->ManufacturingPage2.u.fields.u8PCIRevisionID = LSILOGICSCSI_PCI_SAS_REVISION_ID;
3606	}
3607
3608	/* Manufacturing Page 3. */
3609	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage3,
3610	MptConfigurationPageManufacturing3, 3,
3611	MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3612
3613	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
3614	{
3615	pPages->ManufacturingPage3.u.fields.u16PCIDeviceID = LSILOGICSCSI_PCI_SPI_DEVICE_ID;
3616	pPages->ManufacturingPage3.u.fields.u8PCIRevisionID = LSILOGICSCSI_PCI_SPI_REVISION_ID;
3617	}
3618	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
3619	{
3620	pPages->ManufacturingPage3.u.fields.u16PCIDeviceID = LSILOGICSCSI_PCI_SAS_DEVICE_ID;
3621	pPages->ManufacturingPage3.u.fields.u8PCIRevisionID = LSILOGICSCSI_PCI_SAS_REVISION_ID;
3622	}
3623
3624	/* Manufacturing Page 4 - I don't know what this contains so we leave it 0 for now. */
3625	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage4,
3626	MptConfigurationPageManufacturing4, 4,
3627	MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3628
3629	/* Manufacturing Page 5 - WWID settings. */
3630	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage5,
3631	MptConfigurationPageManufacturing5, 5,
3632	MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3633
3634	/* Manufacturing Page 6 - Product specific settings. */
3635	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage6,
3636	MptConfigurationPageManufacturing6, 6,
3637	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3638
3639	/* Manufacturing Page 8 - Product specific settings. */
3640	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage8,
3641	MptConfigurationPageManufacturing8, 8,
3642	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3643
3644	/* Manufacturing Page 9 - Product specific settings. */
3645	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage9,
3646	MptConfigurationPageManufacturing9, 9,
3647	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3648
3649	/* Manufacturing Page 10 - Product specific settings. */
3650	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage10,
3651	MptConfigurationPageManufacturing10, 10,
3652	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3653
3654	/* I/O Unit page 0. */
3655	MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(&pPages->IOUnitPage0,
3656	MptConfigurationPageIOUnit0, 0,
3657	MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3658	pPages->IOUnitPage0.u.fields.u64UniqueIdentifier = 0xcafe;
3659
3660	/* I/O Unit page 1. */
3661	MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(&pPages->IOUnitPage1,
3662	MptConfigurationPageIOUnit1, 1,
3663	MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3664	pPages->IOUnitPage1.u.fields.fSingleFunction = true;
3665	pPages->IOUnitPage1.u.fields.fAllPathsMapped = false;
3666	pPages->IOUnitPage1.u.fields.fIntegratedRAIDDisabled = true;
3667	pPages->IOUnitPage1.u.fields.f32BitAccessForced = false;
3668
3669	/* I/O Unit page 2. */
3670	MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(&pPages->IOUnitPage2,
3671	MptConfigurationPageIOUnit2, 2,
3672	MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT);
3673	pPages->IOUnitPage2.u.fields.fPauseOnError = false;
3674	pPages->IOUnitPage2.u.fields.fVerboseModeEnabled = false;
3675	pPages->IOUnitPage2.u.fields.fDisableColorVideo = false;
3676	pPages->IOUnitPage2.u.fields.fNotHookInt40h = false;
3677	pPages->IOUnitPage2.u.fields.u32BIOSVersion = 0xcafecafe;
3678	pPages->IOUnitPage2.u.fields.aAdapterOrder[0].fAdapterEnabled = true;
3679	pPages->IOUnitPage2.u.fields.aAdapterOrder[0].fAdapterEmbedded = true;
3680	pPages->IOUnitPage2.u.fields.aAdapterOrder[0].u8PCIBusNumber = 0;
3681	pPages->IOUnitPage2.u.fields.aAdapterOrder[0].u8PCIDevFn = pThis->PciDev.devfn;
3682
3683	/* I/O Unit page 3. */
3684	MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(&pPages->IOUnitPage3,
3685	MptConfigurationPageIOUnit3, 3,
3686	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3687	pPages->IOUnitPage3.u.fields.u8GPIOCount = 0;
3688
3689	/* I/O Unit page 4. */
3690	MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(&pPages->IOUnitPage4,
3691	MptConfigurationPageIOUnit4, 4,
3692	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3693
3694	/* IOC page 0. */
3695	MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage0,
3696	MptConfigurationPageIOC0, 0,
3697	MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3698	pPages->IOCPage0.u.fields.u32TotalNVStore = 0;
3699	pPages->IOCPage0.u.fields.u32FreeNVStore = 0;
3700
3701	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
3702	{
3703	pPages->IOCPage0.u.fields.u16VendorId = LSILOGICSCSI_PCI_VENDOR_ID;
3704	pPages->IOCPage0.u.fields.u16DeviceId = LSILOGICSCSI_PCI_SPI_DEVICE_ID;
3705	pPages->IOCPage0.u.fields.u8RevisionId = LSILOGICSCSI_PCI_SPI_REVISION_ID;
3706	pPages->IOCPage0.u.fields.u32ClassCode = LSILOGICSCSI_PCI_SPI_CLASS_CODE;
3707	pPages->IOCPage0.u.fields.u16SubsystemVendorId = LSILOGICSCSI_PCI_SPI_SUBSYSTEM_VENDOR_ID;
3708	pPages->IOCPage0.u.fields.u16SubsystemId = LSILOGICSCSI_PCI_SPI_SUBSYSTEM_ID;
3709	}
3710	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
3711	{
3712	pPages->IOCPage0.u.fields.u16VendorId = LSILOGICSCSI_PCI_VENDOR_ID;
3713	pPages->IOCPage0.u.fields.u16DeviceId = LSILOGICSCSI_PCI_SAS_DEVICE_ID;
3714	pPages->IOCPage0.u.fields.u8RevisionId = LSILOGICSCSI_PCI_SAS_REVISION_ID;
3715	pPages->IOCPage0.u.fields.u32ClassCode = LSILOGICSCSI_PCI_SAS_CLASS_CODE;
3716	pPages->IOCPage0.u.fields.u16SubsystemVendorId = LSILOGICSCSI_PCI_SAS_SUBSYSTEM_VENDOR_ID;
3717	pPages->IOCPage0.u.fields.u16SubsystemId = LSILOGICSCSI_PCI_SAS_SUBSYSTEM_ID;
3718	}
3719
3720	/* IOC page 1. */
3721	MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage1,
3722	MptConfigurationPageIOC1, 1,
3723	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3724	pPages->IOCPage1.u.fields.fReplyCoalescingEnabled = false;
3725	pPages->IOCPage1.u.fields.u32CoalescingTimeout = 0;
3726	pPages->IOCPage1.u.fields.u8CoalescingDepth = 0;
3727
3728	/* IOC page 2. */
3729	MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage2,
3730	MptConfigurationPageIOC2, 2,
3731	MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3732	/* Everything else here is 0. */
3733
3734	/* IOC page 3. */
3735	MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage3,
3736	MptConfigurationPageIOC3, 3,
3737	MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3738	/* Everything else here is 0. */
3739
3740	/* IOC page 4. */
3741	MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage4,
3742	MptConfigurationPageIOC4, 4,
3743	MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3744	/* Everything else here is 0. */
3745
3746	/* IOC page 6. */
3747	MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage6,
3748	MptConfigurationPageIOC6, 6,
3749	MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3750	/* Everything else here is 0. */
3751
3752	/* BIOS page 1. */
3753	MPT_CONFIG_PAGE_HEADER_INIT_BIOS(&pPages->BIOSPage1,
3754	MptConfigurationPageBIOS1, 1,
3755	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3756
3757	/* BIOS page 2. */
3758	MPT_CONFIG_PAGE_HEADER_INIT_BIOS(&pPages->BIOSPage2,
3759	MptConfigurationPageBIOS2, 2,
3760	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3761
3762	/* BIOS page 4. */
3763	MPT_CONFIG_PAGE_HEADER_INIT_BIOS(&pPages->BIOSPage4,
3764	MptConfigurationPageBIOS4, 4,
3765	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3766
3767	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
3768	lsilogicR3InitializeConfigurationPagesSpi(pThis);
3769	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
3770	lsilogicR3InitializeConfigurationPagesSas(pThis);
3771	else
3772	AssertMsgFailed(("Invalid controller type %d\n", pThis->enmCtrlType));
3773	}
3774
3775	/**
3776	* @callback_method_impl{FNPDMQUEUEDEV, Transmit queue consumer.}
3777	*/
3778	static DECLCALLBACK(bool) lsilogicR3NotifyQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
3779	{
3780	RT_NOREF(pItem);
3781	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
3782	int rc = VINF_SUCCESS;
3783
3784	LogFlowFunc(("pDevIns=%#p pItem=%#p\n", pDevIns, pItem));
3785
3786	rc = SUPSemEventSignal(pThis->pSupDrvSession, pThis->hEvtProcess);
3787	AssertRC(rc);
3788
3789	return true;
3790	}
3791
3792	/**
3793	* Sets the emulated controller type from a given string.
3794	*
3795	* @returns VBox status code.
3796	*
3797	* @param pThis Pointer to the LsiLogic device state.
3798	* @param pcszCtrlType The string to use.
3799	*/
3800	static int lsilogicR3GetCtrlTypeFromString(PLSILOGICSCSI pThis, const char *pcszCtrlType)
3801	{
3802	int rc = VERR_INVALID_PARAMETER;
3803
3804	if (!RTStrCmp(pcszCtrlType, LSILOGICSCSI_PCI_SPI_CTRLNAME))
3805	{
3806	pThis->enmCtrlType = LSILOGICCTRLTYPE_SCSI_SPI;
3807	rc = VINF_SUCCESS;
3808	}
3809	else if (!RTStrCmp(pcszCtrlType, LSILOGICSCSI_PCI_SAS_CTRLNAME))
3810	{
3811	pThis->enmCtrlType = LSILOGICCTRLTYPE_SCSI_SAS;
3812	rc = VINF_SUCCESS;
3813	}
3814
3815	return rc;
3816	}
3817
3818	/**
3819	* @callback_method_impl{FNIOMIOPORTIN, Legacy ISA port.}
3820	*/
3821	static DECLCALLBACK(int) lsilogicR3IsaIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
3822	{
3823	RT_NOREF(pvUser, cb);
3824	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
3825
3826	Assert(cb == 1);
3827
3828	uint8_t iRegister = pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI
3829	? Port - LSILOGIC_BIOS_IO_PORT
3830	: Port - LSILOGIC_SAS_BIOS_IO_PORT;
3831	int rc = vboxscsiReadRegister(&pThis->VBoxSCSI, iRegister, pu32);
3832
3833	Log2(("%s: pu32=%p:{%.*Rhxs} iRegister=%d rc=%Rrc\n",
3834	__FUNCTION__, pu32, 1, pu32, iRegister, rc));
3835
3836	return rc;
3837	}
3838
3839	/**
3840	* Prepares a request from the BIOS.
3841	*
3842	* @returns VBox status code.
3843	* @param pThis Pointer to the LsiLogic device state.
3844	*/
3845	static int lsilogicR3PrepareBiosScsiRequest(PLSILOGICSCSI pThis)
3846	{
3847	int rc;
3848	uint32_t uTargetDevice;
3849	uint32_t uLun;
3850	uint8_t *pbCdb;
3851	size_t cbCdb;
3852	size_t cbBuf;
3853
3854	rc = vboxscsiSetupRequest(&pThis->VBoxSCSI, &uLun, &pbCdb, &cbCdb, &cbBuf, &uTargetDevice);
3855	AssertMsgRCReturn(rc, ("Setting up SCSI request failed rc=%Rrc\n", rc), rc);
3856
3857	if ( uTargetDevice < pThis->cDeviceStates
3858	&& pThis->paDeviceStates[uTargetDevice].pDrvBase)
3859	{
3860	PLSILOGICDEVICE pTgtDev = &pThis->paDeviceStates[uTargetDevice];
3861	PDMMEDIAEXIOREQ hIoReq;
3862	PLSILOGICREQ pReq;
3863
3864	rc = pTgtDev->pDrvMediaEx->pfnIoReqAlloc(pTgtDev->pDrvMediaEx, &hIoReq, (void **)&pReq,
3865	0, PDMIMEDIAEX_F_SUSPEND_ON_RECOVERABLE_ERR);
3866	AssertMsgRCReturn(rc, ("Getting task from cache failed rc=%Rrc\n", rc), rc);
3867
3868	pReq->fBIOS = true;
3869	pReq->hIoReq = hIoReq;
3870	pReq->pTargetDevice = pTgtDev;
3871
3872	ASMAtomicIncU32(&pTgtDev->cOutstandingRequests);
3873
3874	rc = pTgtDev->pDrvMediaEx->pfnIoReqSendScsiCmd(pTgtDev->pDrvMediaEx, pReq->hIoReq, uLun,
3875	pbCdb, cbCdb, PDMMEDIAEXIOREQSCSITXDIR_UNKNOWN,
3876	cbBuf, NULL, 0, &pReq->u8ScsiSts, 30 * RT_MS_1SEC);
3877	if (rc == VINF_SUCCESS \|\| rc != VINF_PDM_MEDIAEX_IOREQ_IN_PROGRESS)
3878	{
3879	uint8_t u8ScsiSts = pReq->u8ScsiSts;
3880	pTgtDev->pDrvMediaEx->pfnIoReqFree(pTgtDev->pDrvMediaEx, pReq->hIoReq);
3881	rc = vboxscsiRequestFinished(&pThis->VBoxSCSI, u8ScsiSts);
3882	}
3883	else if (rc == VINF_PDM_MEDIAEX_IOREQ_IN_PROGRESS)
3884	rc = VINF_SUCCESS;
3885
3886	return rc;
3887	}
3888
3889	/* Device is not present. */
3890	AssertMsg(pbCdb[0] == SCSI_INQUIRY,
3891	("Device is not present but command is not inquiry\n"));
3892
3893	SCSIINQUIRYDATA ScsiInquiryData;
3894
3895	memset(&ScsiInquiryData, 0, sizeof(SCSIINQUIRYDATA));
3896	ScsiInquiryData.u5PeripheralDeviceType = SCSI_INQUIRY_DATA_PERIPHERAL_DEVICE_TYPE_UNKNOWN;
3897	ScsiInquiryData.u3PeripheralQualifier = SCSI_INQUIRY_DATA_PERIPHERAL_QUALIFIER_NOT_CONNECTED_NOT_SUPPORTED;
3898
3899	memcpy(pThis->VBoxSCSI.pbBuf, &ScsiInquiryData, 5);
3900
3901	rc = vboxscsiRequestFinished(&pThis->VBoxSCSI, SCSI_STATUS_OK);
3902	AssertMsgRCReturn(rc, ("Finishing BIOS SCSI request failed rc=%Rrc\n", rc), rc);
3903
3904	return rc;
3905	}
3906
3907	/**
3908	* @callback_method_impl{FNIOMIOPORTOUT, Legacy ISA port.}
3909	*/
3910	static DECLCALLBACK(int) lsilogicR3IsaIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
3911	{
3912	RT_NOREF(pvUser, cb);
3913	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
3914	Log2(("#%d %s: pvUser=%#p cb=%d u32=%#x Port=%#x\n", pDevIns->iInstance, __FUNCTION__, pvUser, cb, u32, Port));
3915
3916	Assert(cb == 1);
3917
3918	/*
3919	* If there is already a request form the BIOS pending ignore this write
3920	* because it should not happen.
3921	*/
3922	if (ASMAtomicReadBool(&pThis->fBiosReqPending))
3923	return VINF_SUCCESS;
3924
3925	uint8_t iRegister = pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI
3926	? Port - LSILOGIC_BIOS_IO_PORT
3927	: Port - LSILOGIC_SAS_BIOS_IO_PORT;
3928	int rc = vboxscsiWriteRegister(&pThis->VBoxSCSI, iRegister, (uint8_t)u32);
3929	if (rc == VERR_MORE_DATA)
3930	{
3931	ASMAtomicXchgBool(&pThis->fBiosReqPending, true);
3932	/* Send a notifier to the PDM queue that there are pending requests. */
3933	PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pNotificationQueue));
3934	AssertMsg(pItem, ("Allocating item for queue failed\n"));
3935	PDMQueueInsert(pThis->CTX_SUFF(pNotificationQueue), (PPDMQUEUEITEMCORE)pItem);
3936	}
3937	else if (RT_FAILURE(rc))
3938	AssertMsgFailed(("Writing BIOS register failed %Rrc\n", rc));
3939
3940	return VINF_SUCCESS;
3941	}
3942
3943	/**
3944	* @callback_method_impl{FNIOMIOPORTOUTSTRING,
3945	* Port I/O Handler for primary port range OUT string operations.}
3946	*/
3947	static DECLCALLBACK(int) lsilogicR3IsaIOPortWriteStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port,
3948	uint8_t const pbSrc, uint32_t pcTransfers, unsigned cb)
3949	{
3950	RT_NOREF(pvUser);
3951	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
3952	Log2(("#%d %s: pvUser=%#p cb=%d Port=%#x\n", pDevIns->iInstance, __FUNCTION__, pvUser, cb, Port));
3953
3954	uint8_t iRegister = pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI
3955	? Port - LSILOGIC_BIOS_IO_PORT
3956	: Port - LSILOGIC_SAS_BIOS_IO_PORT;
3957	int rc = vboxscsiWriteString(pDevIns, &pThis->VBoxSCSI, iRegister, pbSrc, pcTransfers, cb);
3958	if (rc == VERR_MORE_DATA)
3959	{
3960	ASMAtomicXchgBool(&pThis->fBiosReqPending, true);
3961	/* Send a notifier to the PDM queue that there are pending requests. */
3962	PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pNotificationQueue));
3963	AssertMsg(pItem, ("Allocating item for queue failed\n"));
3964	PDMQueueInsert(pThis->CTX_SUFF(pNotificationQueue), (PPDMQUEUEITEMCORE)pItem);
3965	}
3966	else if (RT_FAILURE(rc))
3967	AssertMsgFailed(("Writing BIOS register failed %Rrc\n", rc));
3968
3969	return VINF_SUCCESS;
3970	}
3971
3972	/**
3973	* @callback_method_impl{FNIOMIOPORTINSTRING,
3974	* Port I/O Handler for primary port range IN string operations.}
3975	*/
3976	static DECLCALLBACK(int) lsilogicR3IsaIOPortReadStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port,
3977	uint8_t pbDst, uint32_t pcTransfers, unsigned cb)
3978	{
3979	RT_NOREF(pvUser);
3980	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
3981	LogFlowFunc(("#%d %s: pvUser=%#p cb=%d Port=%#x\n", pDevIns->iInstance, __FUNCTION__, pvUser, cb, Port));
3982
3983	uint8_t iRegister = pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI
3984	? Port - LSILOGIC_BIOS_IO_PORT
3985	: Port - LSILOGIC_SAS_BIOS_IO_PORT;
3986	return vboxscsiReadString(pDevIns, &pThis->VBoxSCSI, iRegister, pbDst, pcTransfers, cb);
3987	}
3988
3989	/**
3990	* @callback_method_impl{FNPCIIOREGIONMAP}
3991	*/
3992	static DECLCALLBACK(int) lsilogicR3Map(PPCIDEVICE pPciDev, /unsigned/ int iRegion,
3993	RTGCPHYS GCPhysAddress, RTGCPHYS cb,
3994	PCIADDRESSSPACE enmType)
3995	{
3996	PPDMDEVINS pDevIns = pPciDev->pDevIns;
3997	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
3998	int rc = VINF_SUCCESS;
3999	const char *pcszCtrl = pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI
4000	? "LsiLogic"
4001	: "LsiLogicSas";
4002	const char *pcszDiag = pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI
4003	? "LsiLogicDiag"
4004	: "LsiLogicSasDiag";
4005
4006	Log2(("%s: registering area at GCPhysAddr=%RGp cb=%RGp\n", __FUNCTION__, GCPhysAddress, cb));
4007
4008	AssertMsg( (enmType == PCI_ADDRESS_SPACE_MEM && cb >= LSILOGIC_PCI_SPACE_MEM_SIZE)
4009	\|\| (enmType == PCI_ADDRESS_SPACE_IO && cb >= LSILOGIC_PCI_SPACE_IO_SIZE),
4010	("PCI region type and size do not match\n"));
4011
4012	if (enmType == PCI_ADDRESS_SPACE_MEM && iRegion == 1)
4013	{
4014	/*
4015	* Non-4-byte read access to LSILOGIC_REG_REPLY_QUEUE may cause real strange behavior
4016	* because the data is part of a physical guest address. But some drivers use 1-byte
4017	* access to scan for SCSI controllers. So, we simplify our code by telling IOM to
4018	* read DWORDs.
4019	*
4020	* Regarding writes, we couldn't find anything specific in the specs about what should
4021	* happen. So far we've ignored unaligned writes and assumed the missing bytes of
4022	* byte and word access to be zero. We suspect that IOMMMIO_FLAGS_WRITE_ONLY_DWORD
4023	* or IOMMMIO_FLAGS_WRITE_DWORD_ZEROED would be the most appropriate here, but since we
4024	* don't have real hw to test one, the old behavior is kept exactly like it used to be.
4025	*/
4026	/** @todo Check out unaligned writes and non-dword writes on real LsiLogic
4027	* hardware. */
4028	rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /pvUser/,
4029	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
4030	lsilogicMMIOWrite, lsilogicMMIORead, pcszCtrl);
4031	if (RT_FAILURE(rc))
4032	return rc;
4033
4034	if (pThis->fR0Enabled)
4035	{
4036	rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /pvUser/,
4037	"lsilogicMMIOWrite", "lsilogicMMIORead");
4038	if (RT_FAILURE(rc))
4039	return rc;
4040	}
4041
4042	if (pThis->fGCEnabled)
4043	{
4044	rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /pvUser/,
4045	"lsilogicMMIOWrite", "lsilogicMMIORead");
4046	if (RT_FAILURE(rc))
4047	return rc;
4048	}
4049
4050	pThis->GCPhysMMIOBase = GCPhysAddress;
4051	}
4052	else if (enmType == PCI_ADDRESS_SPACE_MEM && iRegion == 2)
4053	{
4054	/* We use the assigned size here, because we currently only support page aligned MMIO ranges. */
4055	rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /pvUser/,
4056	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
4057	lsilogicDiagnosticWrite, lsilogicDiagnosticRead, pcszDiag);
4058	if (RT_FAILURE(rc))
4059	return rc;
4060
4061	if (pThis->fR0Enabled)
4062	{
4063	rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /pvUser/,
4064	"lsilogicDiagnosticWrite", "lsilogicDiagnosticRead");
4065	if (RT_FAILURE(rc))
4066	return rc;
4067	}
4068
4069	if (pThis->fGCEnabled)
4070	{
4071	rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /pvUser/,
4072	"lsilogicDiagnosticWrite", "lsilogicDiagnosticRead");
4073	if (RT_FAILURE(rc))
4074	return rc;
4075	}
4076	}
4077	else if (enmType == PCI_ADDRESS_SPACE_IO)
4078	{
4079	rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, LSILOGIC_PCI_SPACE_IO_SIZE,
4080	NULL, lsilogicIOPortWrite, lsilogicIOPortRead, NULL, NULL, pcszCtrl);
4081	if (RT_FAILURE(rc))
4082	return rc;
4083
4084	if (pThis->fR0Enabled)
4085	{
4086	rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, LSILOGIC_PCI_SPACE_IO_SIZE,
4087	0, "lsilogicIOPortWrite", "lsilogicIOPortRead", NULL, NULL, pcszCtrl);
4088	if (RT_FAILURE(rc))
4089	return rc;
4090	}
4091
4092	if (pThis->fGCEnabled)
4093	{
4094	rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, LSILOGIC_PCI_SPACE_IO_SIZE,
4095	0, "lsilogicIOPortWrite", "lsilogicIOPortRead", NULL, NULL, pcszCtrl);
4096	if (RT_FAILURE(rc))
4097	return rc;
4098	}
4099
4100	pThis->IOPortBase = (RTIOPORT)GCPhysAddress;
4101	}
4102	else
4103	AssertMsgFailed(("Invalid enmType=%d iRegion=%d\n", enmType, iRegion));
4104
4105	return rc;
4106	}
4107
4108	/**
4109	* @callback_method_impl{PFNDBGFHANDLERDEV}
4110	*/
4111	static DECLCALLBACK(void) lsilogicR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4112	{
4113	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4114	bool fVerbose = false;
4115
4116	/*
4117	* Parse args.
4118	*/
4119	if (pszArgs)
4120	fVerbose = strstr(pszArgs, "verbose") != NULL;
4121
4122	/*
4123	* Show info.
4124	*/
4125	pHlp->pfnPrintf(pHlp,
4126	"%s#%d: port=%RTiop mmio=%RGp max-devices=%u GC=%RTbool R0=%RTbool\n",
4127	pDevIns->pReg->szName,
4128	pDevIns->iInstance,
4129	pThis->IOPortBase, pThis->GCPhysMMIOBase,
4130	pThis->cDeviceStates,
4131	pThis->fGCEnabled ? true : false,
4132	pThis->fR0Enabled ? true : false);
4133
4134	/*
4135	* Show general state.
4136	*/
4137	pHlp->pfnPrintf(pHlp, "enmState=%u\n", pThis->enmState);
4138	pHlp->pfnPrintf(pHlp, "enmWhoInit=%u\n", pThis->enmWhoInit);
4139	pHlp->pfnPrintf(pHlp, "enmDoorbellState=%d\n", pThis->enmDoorbellState);
4140	pHlp->pfnPrintf(pHlp, "fDiagnosticEnabled=%RTbool\n", pThis->fDiagnosticEnabled);
4141	pHlp->pfnPrintf(pHlp, "fNotificationSent=%RTbool\n", pThis->fNotificationSent);
4142	pHlp->pfnPrintf(pHlp, "fEventNotificationEnabled=%RTbool\n", pThis->fEventNotificationEnabled);
4143	pHlp->pfnPrintf(pHlp, "uInterruptMask=%#x\n", pThis->uInterruptMask);
4144	pHlp->pfnPrintf(pHlp, "uInterruptStatus=%#x\n", pThis->uInterruptStatus);
4145	pHlp->pfnPrintf(pHlp, "u16IOCFaultCode=%#06x\n", pThis->u16IOCFaultCode);
4146	pHlp->pfnPrintf(pHlp, "u32HostMFAHighAddr=%#x\n", pThis->u32HostMFAHighAddr);
4147	pHlp->pfnPrintf(pHlp, "u32SenseBufferHighAddr=%#x\n", pThis->u32SenseBufferHighAddr);
4148	pHlp->pfnPrintf(pHlp, "cMaxDevices=%u\n", pThis->cMaxDevices);
4149	pHlp->pfnPrintf(pHlp, "cMaxBuses=%u\n", pThis->cMaxBuses);
4150	pHlp->pfnPrintf(pHlp, "cbReplyFrame=%u\n", pThis->cbReplyFrame);
4151	pHlp->pfnPrintf(pHlp, "cReplyQueueEntries=%u\n", pThis->cReplyQueueEntries);
4152	pHlp->pfnPrintf(pHlp, "cRequestQueueEntries=%u\n", pThis->cRequestQueueEntries);
4153	pHlp->pfnPrintf(pHlp, "cPorts=%u\n", pThis->cPorts);
4154
4155	/*
4156	* Show queue status.
4157	*/
4158	pHlp->pfnPrintf(pHlp, "uReplyFreeQueueNextEntryFreeWrite=%u\n", pThis->uReplyFreeQueueNextEntryFreeWrite);
4159	pHlp->pfnPrintf(pHlp, "uReplyFreeQueueNextAddressRead=%u\n", pThis->uReplyFreeQueueNextAddressRead);
4160	pHlp->pfnPrintf(pHlp, "uReplyPostQueueNextEntryFreeWrite=%u\n", pThis->uReplyPostQueueNextEntryFreeWrite);
4161	pHlp->pfnPrintf(pHlp, "uReplyPostQueueNextAddressRead=%u\n", pThis->uReplyPostQueueNextAddressRead);
4162	pHlp->pfnPrintf(pHlp, "uRequestQueueNextEntryFreeWrite=%u\n", pThis->uRequestQueueNextEntryFreeWrite);
4163	pHlp->pfnPrintf(pHlp, "uRequestQueueNextAddressRead=%u\n", pThis->uRequestQueueNextAddressRead);
4164
4165	/*
4166	* Show queue content if verbose
4167	*/
4168	if (fVerbose)
4169	{
4170	for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
4171	pHlp->pfnPrintf(pHlp, "RFQ[%u]=%#x\n", i, pThis->pReplyFreeQueueBaseR3[i]);
4172
4173	pHlp->pfnPrintf(pHlp, "\n");
4174
4175	for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
4176	pHlp->pfnPrintf(pHlp, "RPQ[%u]=%#x\n", i, pThis->pReplyPostQueueBaseR3[i]);
4177
4178	pHlp->pfnPrintf(pHlp, "\n");
4179
4180	for (unsigned i = 0; i < pThis->cRequestQueueEntries; i++)
4181	pHlp->pfnPrintf(pHlp, "ReqQ[%u]=%#x\n", i, pThis->pRequestQueueBaseR3[i]);
4182	}
4183
4184	/*
4185	* Print the device status.
4186	*/
4187	for (unsigned i = 0; i < pThis->cDeviceStates; i++)
4188	{
4189	PLSILOGICDEVICE pDevice = &pThis->paDeviceStates[i];
4190
4191	pHlp->pfnPrintf(pHlp, "\n");
4192
4193	pHlp->pfnPrintf(pHlp, "Device[%u]: device-attached=%RTbool cOutstandingRequests=%u\n",
4194	i, pDevice->pDrvBase != NULL, pDevice->cOutstandingRequests);
4195	}
4196	}
4197
4198	/**
4199	* Allocate the queues.
4200	*
4201	* @returns VBox status code.
4202	*
4203	* @param pThis Pointer to the LsiLogic device state.
4204	*/
4205	static int lsilogicR3QueuesAlloc(PLSILOGICSCSI pThis)
4206	{
4207	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
4208	uint32_t cbQueues;
4209
4210	Assert(!pThis->pReplyFreeQueueBaseR3);
4211
4212	cbQueues = 2pThis->cReplyQueueEntries sizeof(uint32_t);
4213	cbQueues += pThis->cRequestQueueEntries * sizeof(uint32_t);
4214	int rc = MMHyperAlloc(pVM, cbQueues, 1, MM_TAG_PDM_DEVICE_USER,
4215	(void **)&pThis->pReplyFreeQueueBaseR3);
4216	if (RT_FAILURE(rc))
4217	return VERR_NO_MEMORY;
4218	pThis->pReplyFreeQueueBaseR0 = MMHyperR3ToR0(pVM, (void *)pThis->pReplyFreeQueueBaseR3);
4219	pThis->pReplyFreeQueueBaseRC = MMHyperR3ToRC(pVM, (void *)pThis->pReplyFreeQueueBaseR3);
4220
4221	pThis->pReplyPostQueueBaseR3 = pThis->pReplyFreeQueueBaseR3 + pThis->cReplyQueueEntries;
4222	pThis->pReplyPostQueueBaseR0 = MMHyperR3ToR0(pVM, (void *)pThis->pReplyPostQueueBaseR3);
4223	pThis->pReplyPostQueueBaseRC = MMHyperR3ToRC(pVM, (void *)pThis->pReplyPostQueueBaseR3);
4224
4225	pThis->pRequestQueueBaseR3 = pThis->pReplyPostQueueBaseR3 + pThis->cReplyQueueEntries;
4226	pThis->pRequestQueueBaseR0 = MMHyperR3ToR0(pVM, (void *)pThis->pRequestQueueBaseR3);
4227	pThis->pRequestQueueBaseRC = MMHyperR3ToRC(pVM, (void *)pThis->pRequestQueueBaseR3);
4228
4229	return VINF_SUCCESS;
4230	}
4231
4232	/**
4233	* Free the hyper memory used or the queues.
4234	*
4235	* @returns nothing.
4236	*
4237	* @param pThis Pointer to the LsiLogic device state.
4238	*/
4239	static void lsilogicR3QueuesFree(PLSILOGICSCSI pThis)
4240	{
4241	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
4242	int rc = VINF_SUCCESS;
4243
4244	AssertPtr(pThis->pReplyFreeQueueBaseR3);
4245
4246	rc = MMHyperFree(pVM, (void *)pThis->pReplyFreeQueueBaseR3);
4247	AssertRC(rc);
4248
4249	pThis->pReplyFreeQueueBaseR3 = NULL;
4250	pThis->pReplyPostQueueBaseR3 = NULL;
4251	pThis->pRequestQueueBaseR3 = NULL;
4252	}
4253
4254
4255	/* The worker thread. */
4256	static DECLCALLBACK(int) lsilogicR3Worker(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4257	{
4258	PLSILOGICSCSI pThis = (PLSILOGICSCSI)pThread->pvUser;
4259	int rc = VINF_SUCCESS;
4260
4261	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
4262	return VINF_SUCCESS;
4263
4264	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4265	{
4266	ASMAtomicWriteBool(&pThis->fWrkThreadSleeping, true);
4267	bool fNotificationSent = ASMAtomicXchgBool(&pThis->fNotificationSent, false);
4268	if (!fNotificationSent)
4269	{
4270	Assert(ASMAtomicReadBool(&pThis->fWrkThreadSleeping));
4271	rc = SUPSemEventWaitNoResume(pThis->pSupDrvSession, pThis->hEvtProcess, RT_INDEFINITE_WAIT);
4272	AssertLogRelMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
4273	if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
4274	break;
4275	LogFlowFunc(("Woken up with rc=%Rrc\n", rc));
4276	ASMAtomicWriteBool(&pThis->fNotificationSent, false);
4277	}
4278
4279	ASMAtomicWriteBool(&pThis->fWrkThreadSleeping, false);
4280
4281	/* Check whether there is a BIOS request pending and process it first. */
4282	if (ASMAtomicReadBool(&pThis->fBiosReqPending))
4283	{
4284	rc = lsilogicR3PrepareBiosScsiRequest(pThis);
4285	AssertRC(rc);
4286	ASMAtomicXchgBool(&pThis->fBiosReqPending, false);
4287	}
4288
4289	/* Only process request which arrived before we received the notification. */
4290	uint32_t uRequestQueueNextEntryWrite = ASMAtomicReadU32(&pThis->uRequestQueueNextEntryFreeWrite);
4291
4292	/* Go through the messages now and process them. */
4293	while ( RT_LIKELY(pThis->enmState == LSILOGICSTATE_OPERATIONAL)
4294	&& (pThis->uRequestQueueNextAddressRead != uRequestQueueNextEntryWrite))
4295	{
4296	MptRequestUnion GuestRequest;
4297	uint32_t u32RequestMessageFrameDesc = pThis->CTX_SUFF(pRequestQueueBase)[pThis->uRequestQueueNextAddressRead];
4298	RTGCPHYS GCPhysMessageFrameAddr = LSILOGIC_RTGCPHYS_FROM_U32(pThis->u32HostMFAHighAddr,
4299	(u32RequestMessageFrameDesc & ~0x07));
4300
4301	/* Read the message header from the guest first. */
4302	PDMDevHlpPhysRead(pDevIns, GCPhysMessageFrameAddr, &GuestRequest, sizeof(MptMessageHdr));
4303
4304	/* Determine the size of the request. */
4305	uint32_t cbRequest = 0;
4306	switch (GuestRequest.Header.u8Function)
4307	{
4308	case MPT_MESSAGE_HDR_FUNCTION_SCSI_IO_REQUEST:
4309	cbRequest = sizeof(MptSCSIIORequest);
4310	break;
4311	case MPT_MESSAGE_HDR_FUNCTION_SCSI_TASK_MGMT:
4312	cbRequest = sizeof(MptSCSITaskManagementRequest);
4313	break;
4314	case MPT_MESSAGE_HDR_FUNCTION_IOC_INIT:
4315	cbRequest = sizeof(MptIOCInitRequest);
4316	break;
4317	case MPT_MESSAGE_HDR_FUNCTION_IOC_FACTS:
4318	cbRequest = sizeof(MptIOCFactsRequest);
4319	break;
4320	case MPT_MESSAGE_HDR_FUNCTION_CONFIG:
4321	cbRequest = sizeof(MptConfigurationRequest);
4322	break;
4323	case MPT_MESSAGE_HDR_FUNCTION_PORT_FACTS:
4324	cbRequest = sizeof(MptPortFactsRequest);
4325	break;
4326	case MPT_MESSAGE_HDR_FUNCTION_PORT_ENABLE:
4327	cbRequest = sizeof(MptPortEnableRequest);
4328	break;
4329	case MPT_MESSAGE_HDR_FUNCTION_EVENT_NOTIFICATION:
4330	cbRequest = sizeof(MptEventNotificationRequest);
4331	break;
4332	case MPT_MESSAGE_HDR_FUNCTION_EVENT_ACK:
4333	AssertMsgFailed(("todo\n"));
4334	//cbRequest = sizeof(MptEventAckRequest);
4335	break;
4336	case MPT_MESSAGE_HDR_FUNCTION_FW_DOWNLOAD:
4337	cbRequest = sizeof(MptFWDownloadRequest);
4338	break;
4339	case MPT_MESSAGE_HDR_FUNCTION_FW_UPLOAD:
4340	cbRequest = sizeof(MptFWUploadRequest);
4341	break;
4342	default:
4343	AssertMsgFailed(("Unknown function issued %u\n", GuestRequest.Header.u8Function));
4344	lsilogicSetIOCFaultCode(pThis, LSILOGIC_IOCSTATUS_INVALID_FUNCTION);
4345	}
4346
4347	if (cbRequest != 0)
4348	{
4349	/* Read the complete message frame from guest memory now. */
4350	PDMDevHlpPhysRead(pDevIns, GCPhysMessageFrameAddr, &GuestRequest, cbRequest);
4351
4352	/* Handle SCSI I/O requests now. */
4353	if (GuestRequest.Header.u8Function == MPT_MESSAGE_HDR_FUNCTION_SCSI_IO_REQUEST)
4354	{
4355	rc = lsilogicR3ProcessSCSIIORequest(pThis, GCPhysMessageFrameAddr, &GuestRequest);
4356	AssertRC(rc);
4357	}
4358	else
4359	{
4360	MptReplyUnion Reply;
4361	rc = lsilogicR3ProcessMessageRequest(pThis, &GuestRequest.Header, &Reply);
4362	AssertRC(rc);
4363	}
4364
4365	pThis->uRequestQueueNextAddressRead++;
4366	pThis->uRequestQueueNextAddressRead %= pThis->cRequestQueueEntries;
4367	}
4368	} /* While request frames available. */
4369	} /* While running */
4370
4371	return VINF_SUCCESS;
4372	}
4373
4374
4375	/**
4376	* Unblock the worker thread so it can respond to a state change.
4377	*
4378	* @returns VBox status code.
4379	* @param pDevIns The pcnet device instance.
4380	* @param pThread The send thread.
4381	*/
4382	static DECLCALLBACK(int) lsilogicR3WorkerWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4383	{
4384	RT_NOREF(pThread);
4385	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4386	return SUPSemEventSignal(pThis->pSupDrvSession, pThis->hEvtProcess);
4387	}
4388
4389
4390	/**
4391	* Kicks the controller to process pending tasks after the VM was resumed
4392	* or loaded from a saved state.
4393	*
4394	* @returns nothing.
4395	* @param pThis Pointer to the LsiLogic device state.
4396	*/
4397	static void lsilogicR3Kick(PLSILOGICSCSI pThis)
4398	{
4399	if (pThis->fNotificationSent)
4400	{
4401	/* Send a notifier to the PDM queue that there are pending requests. */
4402	PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pNotificationQueue));
4403	AssertMsg(pItem, ("Allocating item for queue failed\n"));
4404	PDMQueueInsert(pThis->CTX_SUFF(pNotificationQueue), (PPDMQUEUEITEMCORE)pItem);
4405	}
4406	}
4407
4408
4409	/*
4410	* Saved state.
4411	*/
4412
4413	/**
4414	* @callback_method_impl{FNSSMDEVLIVEEXEC}
4415	*/
4416	static DECLCALLBACK(int) lsilogicR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
4417	{
4418	RT_NOREF(uPass);
4419	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4420
4421	SSMR3PutU32(pSSM, pThis->enmCtrlType);
4422	SSMR3PutU32(pSSM, pThis->cDeviceStates);
4423	SSMR3PutU32(pSSM, pThis->cPorts);
4424
4425	/* Save the device config. */
4426	for (unsigned i = 0; i < pThis->cDeviceStates; i++)
4427	SSMR3PutBool(pSSM, pThis->paDeviceStates[i].pDrvBase != NULL);
4428
4429	return VINF_SSM_DONT_CALL_AGAIN;
4430	}
4431
4432	/**
4433	* @callback_method_impl{FNSSMDEVSAVEEXEC}
4434	*/
4435	static DECLCALLBACK(int) lsilogicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4436	{
4437	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4438
4439	/* Every device first. */
4440	lsilogicR3LiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
4441	for (unsigned i = 0; i < pThis->cDeviceStates; i++)
4442	{
4443	PLSILOGICDEVICE pDevice = &pThis->paDeviceStates[i];
4444
4445	AssertMsg(!pDevice->cOutstandingRequests,
4446	("There are still outstanding requests on this device\n"));
4447	SSMR3PutU32(pSSM, pDevice->cOutstandingRequests);
4448
4449	/* Query all suspended requests and store them in the request queue. */
4450	if (pDevice->pDrvMediaEx)
4451	{
4452	uint32_t cReqsRedo = pDevice->pDrvMediaEx->pfnIoReqGetSuspendedCount(pDevice->pDrvMediaEx);
4453	if (cReqsRedo)
4454	{
4455	PDMMEDIAEXIOREQ hIoReq;
4456	PLSILOGICREQ pReq;
4457	int rc = pDevice->pDrvMediaEx->pfnIoReqQuerySuspendedStart(pDevice->pDrvMediaEx, &hIoReq,
4458	(void **)&pReq);
4459	AssertRCBreak(rc);
4460
4461	for (;;)
4462	{
4463	if (!pReq->fBIOS)
4464	{
4465	/* Write only the lower 32bit part of the address. */
4466	ASMAtomicWriteU32(&pThis->CTX_SUFF(pRequestQueueBase)[pThis->uRequestQueueNextEntryFreeWrite],
4467	pReq->GCPhysMessageFrameAddr & UINT32_C(0xffffffff));
4468
4469	pThis->uRequestQueueNextEntryFreeWrite++;
4470	pThis->uRequestQueueNextEntryFreeWrite %= pThis->cRequestQueueEntries;
4471	}
4472	else
4473	{
4474	AssertMsg(!pReq->pRedoNext, ("Only one BIOS task can be active!\n"));
4475	vboxscsiSetRequestRedo(&pThis->VBoxSCSI);
4476	}
4477
4478	cReqsRedo--;
4479	if (!cReqsRedo)
4480	break;
4481
4482	rc = pDevice->pDrvMediaEx->pfnIoReqQuerySuspendedNext(pDevice->pDrvMediaEx, hIoReq,
4483	&hIoReq, (void **)&pReq);
4484	AssertRCBreak(rc);
4485	}
4486	}
4487	}
4488	}
4489
4490	/* Now the main device state. */
4491	SSMR3PutU32 (pSSM, pThis->enmState);
4492	SSMR3PutU32 (pSSM, pThis->enmWhoInit);
4493	SSMR3PutU32 (pSSM, pThis->enmDoorbellState);
4494	SSMR3PutBool (pSSM, pThis->fDiagnosticEnabled);
4495	SSMR3PutBool (pSSM, pThis->fNotificationSent);
4496	SSMR3PutBool (pSSM, pThis->fEventNotificationEnabled);
4497	SSMR3PutU32 (pSSM, pThis->uInterruptMask);
4498	SSMR3PutU32 (pSSM, pThis->uInterruptStatus);
4499	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMessage); i++)
4500	SSMR3PutU32 (pSSM, pThis->aMessage[i]);
4501	SSMR3PutU32 (pSSM, pThis->iMessage);
4502	SSMR3PutU32 (pSSM, pThis->cMessage);
4503	SSMR3PutMem (pSSM, &pThis->ReplyBuffer, sizeof(pThis->ReplyBuffer));
4504	SSMR3PutU32 (pSSM, pThis->uNextReplyEntryRead);
4505	SSMR3PutU32 (pSSM, pThis->cReplySize);
4506	SSMR3PutU16 (pSSM, pThis->u16IOCFaultCode);
4507	SSMR3PutU32 (pSSM, pThis->u32HostMFAHighAddr);
4508	SSMR3PutU32 (pSSM, pThis->u32SenseBufferHighAddr);
4509	SSMR3PutU8 (pSSM, pThis->cMaxDevices);
4510	SSMR3PutU8 (pSSM, pThis->cMaxBuses);
4511	SSMR3PutU16 (pSSM, pThis->cbReplyFrame);
4512	SSMR3PutU32 (pSSM, pThis->iDiagnosticAccess);
4513	SSMR3PutU32 (pSSM, pThis->cReplyQueueEntries);
4514	SSMR3PutU32 (pSSM, pThis->cRequestQueueEntries);
4515	SSMR3PutU32 (pSSM, pThis->uReplyFreeQueueNextEntryFreeWrite);
4516	SSMR3PutU32 (pSSM, pThis->uReplyFreeQueueNextAddressRead);
4517	SSMR3PutU32 (pSSM, pThis->uReplyPostQueueNextEntryFreeWrite);
4518	SSMR3PutU32 (pSSM, pThis->uReplyPostQueueNextAddressRead);
4519	SSMR3PutU32 (pSSM, pThis->uRequestQueueNextEntryFreeWrite);
4520	SSMR3PutU32 (pSSM, pThis->uRequestQueueNextAddressRead);
4521
4522	for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
4523	SSMR3PutU32(pSSM, pThis->pReplyFreeQueueBaseR3[i]);
4524	for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
4525	SSMR3PutU32(pSSM, pThis->pReplyPostQueueBaseR3[i]);
4526	for (unsigned i = 0; i < pThis->cRequestQueueEntries; i++)
4527	SSMR3PutU32(pSSM, pThis->pRequestQueueBaseR3[i]);
4528
4529	SSMR3PutU16 (pSSM, pThis->u16NextHandle);
4530
4531	/* Save diagnostic memory register and data regions. */
4532	SSMR3PutU32 (pSSM, pThis->u32DiagMemAddr);
4533	SSMR3PutU32 (pSSM, lsilogicR3MemRegionsCount(pThis));
4534
4535	PLSILOGICMEMREGN pIt = NULL;
4536	RTListForEach(&pThis->ListMemRegns, pIt, LSILOGICMEMREGN, NodeList)
4537	{
4538	SSMR3PutU32(pSSM, pIt->u32AddrStart);
4539	SSMR3PutU32(pSSM, pIt->u32AddrEnd);
4540	SSMR3PutMem(pSSM, &pIt->au32Data[0], (pIt->u32AddrEnd - pIt->u32AddrStart + 1) * sizeof(uint32_t));
4541	}
4542
4543	PMptConfigurationPagesSupported pPages = pThis->pConfigurationPages;
4544
4545	SSMR3PutMem (pSSM, &pPages->ManufacturingPage0, sizeof(MptConfigurationPageManufacturing0));
4546	SSMR3PutMem (pSSM, &pPages->ManufacturingPage1, sizeof(MptConfigurationPageManufacturing1));
4547	SSMR3PutMem (pSSM, &pPages->ManufacturingPage2, sizeof(MptConfigurationPageManufacturing2));
4548	SSMR3PutMem (pSSM, &pPages->ManufacturingPage3, sizeof(MptConfigurationPageManufacturing3));
4549	SSMR3PutMem (pSSM, &pPages->ManufacturingPage4, sizeof(MptConfigurationPageManufacturing4));
4550	SSMR3PutMem (pSSM, &pPages->ManufacturingPage5, sizeof(MptConfigurationPageManufacturing5));
4551	SSMR3PutMem (pSSM, &pPages->ManufacturingPage6, sizeof(MptConfigurationPageManufacturing6));
4552	SSMR3PutMem (pSSM, &pPages->ManufacturingPage8, sizeof(MptConfigurationPageManufacturing8));
4553	SSMR3PutMem (pSSM, &pPages->ManufacturingPage9, sizeof(MptConfigurationPageManufacturing9));
4554	SSMR3PutMem (pSSM, &pPages->ManufacturingPage10, sizeof(MptConfigurationPageManufacturing10));
4555	SSMR3PutMem (pSSM, &pPages->IOUnitPage0, sizeof(MptConfigurationPageIOUnit0));
4556	SSMR3PutMem (pSSM, &pPages->IOUnitPage1, sizeof(MptConfigurationPageIOUnit1));
4557	SSMR3PutMem (pSSM, &pPages->IOUnitPage2, sizeof(MptConfigurationPageIOUnit2));
4558	SSMR3PutMem (pSSM, &pPages->IOUnitPage3, sizeof(MptConfigurationPageIOUnit3));
4559	SSMR3PutMem (pSSM, &pPages->IOUnitPage4, sizeof(MptConfigurationPageIOUnit4));
4560	SSMR3PutMem (pSSM, &pPages->IOCPage0, sizeof(MptConfigurationPageIOC0));
4561	SSMR3PutMem (pSSM, &pPages->IOCPage1, sizeof(MptConfigurationPageIOC1));
4562	SSMR3PutMem (pSSM, &pPages->IOCPage2, sizeof(MptConfigurationPageIOC2));
4563	SSMR3PutMem (pSSM, &pPages->IOCPage3, sizeof(MptConfigurationPageIOC3));
4564	SSMR3PutMem (pSSM, &pPages->IOCPage4, sizeof(MptConfigurationPageIOC4));
4565	SSMR3PutMem (pSSM, &pPages->IOCPage6, sizeof(MptConfigurationPageIOC6));
4566	SSMR3PutMem (pSSM, &pPages->BIOSPage1, sizeof(MptConfigurationPageBIOS1));
4567	SSMR3PutMem (pSSM, &pPages->BIOSPage2, sizeof(MptConfigurationPageBIOS2));
4568	SSMR3PutMem (pSSM, &pPages->BIOSPage4, sizeof(MptConfigurationPageBIOS4));
4569
4570	/* Device dependent pages */
4571	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
4572	{
4573	PMptConfigurationPagesSpi pSpiPages = &pPages->u.SpiPages;
4574
4575	SSMR3PutMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage0, sizeof(MptConfigurationPageSCSISPIPort0));
4576	SSMR3PutMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage1, sizeof(MptConfigurationPageSCSISPIPort1));
4577	SSMR3PutMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage2, sizeof(MptConfigurationPageSCSISPIPort2));
4578
4579	for (unsigned i = 0; i < RT_ELEMENTS(pSpiPages->aBuses[0].aDevicePages); i++)
4580	{
4581	SSMR3PutMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage0, sizeof(MptConfigurationPageSCSISPIDevice0));
4582	SSMR3PutMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage1, sizeof(MptConfigurationPageSCSISPIDevice1));
4583	SSMR3PutMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage2, sizeof(MptConfigurationPageSCSISPIDevice2));
4584	SSMR3PutMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage3, sizeof(MptConfigurationPageSCSISPIDevice3));
4585	}
4586	}
4587	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
4588	{
4589	PMptConfigurationPagesSas pSasPages = &pPages->u.SasPages;
4590
4591	SSMR3PutU32(pSSM, pSasPages->cbManufacturingPage7);
4592	SSMR3PutU32(pSSM, pSasPages->cbSASIOUnitPage0);
4593	SSMR3PutU32(pSSM, pSasPages->cbSASIOUnitPage1);
4594
4595	SSMR3PutMem(pSSM, pSasPages->pManufacturingPage7, pSasPages->cbManufacturingPage7);
4596	SSMR3PutMem(pSSM, pSasPages->pSASIOUnitPage0, pSasPages->cbSASIOUnitPage0);
4597	SSMR3PutMem(pSSM, pSasPages->pSASIOUnitPage1, pSasPages->cbSASIOUnitPage1);
4598
4599	SSMR3PutMem(pSSM, &pSasPages->SASIOUnitPage2, sizeof(MptConfigurationPageSASIOUnit2));
4600	SSMR3PutMem(pSSM, &pSasPages->SASIOUnitPage3, sizeof(MptConfigurationPageSASIOUnit3));
4601
4602	SSMR3PutU32(pSSM, pSasPages->cPHYs);
4603	for (unsigned i = 0; i < pSasPages->cPHYs; i++)
4604	{
4605	SSMR3PutMem(pSSM, &pSasPages->paPHYs[i].SASPHYPage0, sizeof(MptConfigurationPageSASPHY0));
4606	SSMR3PutMem(pSSM, &pSasPages->paPHYs[i].SASPHYPage1, sizeof(MptConfigurationPageSASPHY1));
4607	}
4608
4609	/* The number of devices first. */
4610	SSMR3PutU32(pSSM, pSasPages->cDevices);
4611
4612	PMptSASDevice pCurr = pSasPages->pSASDeviceHead;
4613
4614	while (pCurr)
4615	{
4616	SSMR3PutMem(pSSM, &pCurr->SASDevicePage0, sizeof(MptConfigurationPageSASDevice0));
4617	SSMR3PutMem(pSSM, &pCurr->SASDevicePage1, sizeof(MptConfigurationPageSASDevice1));
4618	SSMR3PutMem(pSSM, &pCurr->SASDevicePage2, sizeof(MptConfigurationPageSASDevice2));
4619
4620	pCurr = pCurr->pNext;
4621	}
4622	}
4623	else
4624	AssertMsgFailed(("Invalid controller type %d\n", pThis->enmCtrlType));
4625
4626	vboxscsiR3SaveExec(&pThis->VBoxSCSI, pSSM);
4627	return SSMR3PutU32(pSSM, UINT32_MAX);
4628	}
4629
4630	/**
4631	* @callback_method_impl{FNSSMDEVLOADDONE}
4632	*/
4633	static DECLCALLBACK(int) lsilogicR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4634	{
4635	RT_NOREF(pSSM);
4636	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4637
4638	lsilogicR3Kick(pThis);
4639	return VINF_SUCCESS;
4640	}
4641
4642	/**
4643	* @callback_method_impl{FNSSMDEVLOADEXEC}
4644	*/
4645	static DECLCALLBACK(int) lsilogicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4646	{
4647	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4648	int rc;
4649
4650	if ( uVersion != LSILOGIC_SAVED_STATE_VERSION
4651	&& uVersion != LSILOGIC_SAVED_STATE_VERSION_PRE_DIAG_MEM
4652	&& uVersion != LSILOGIC_SAVED_STATE_VERSION_BOOL_DOORBELL
4653	&& uVersion != LSILOGIC_SAVED_STATE_VERSION_PRE_SAS
4654	&& uVersion != LSILOGIC_SAVED_STATE_VERSION_VBOX_30)
4655	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
4656
4657	/* device config */
4658	if (uVersion > LSILOGIC_SAVED_STATE_VERSION_PRE_SAS)
4659	{
4660	LSILOGICCTRLTYPE enmCtrlType;
4661	uint32_t cDeviceStates, cPorts;
4662
4663	rc = SSMR3GetU32(pSSM, (uint32_t *)&enmCtrlType);
4664	AssertRCReturn(rc, rc);
4665	rc = SSMR3GetU32(pSSM, &cDeviceStates);
4666	AssertRCReturn(rc, rc);
4667	rc = SSMR3GetU32(pSSM, &cPorts);
4668	AssertRCReturn(rc, rc);
4669
4670	if (enmCtrlType != pThis->enmCtrlType)
4671	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Target config mismatch (Controller type): config=%d state=%d"),
4672	pThis->enmCtrlType, enmCtrlType);
4673	if (cDeviceStates != pThis->cDeviceStates)
4674	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Target config mismatch (Device states): config=%u state=%u"),
4675	pThis->cDeviceStates, cDeviceStates);
4676	if (cPorts != pThis->cPorts)
4677	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Target config mismatch (Ports): config=%u state=%u"),
4678	pThis->cPorts, cPorts);
4679	}
4680	if (uVersion > LSILOGIC_SAVED_STATE_VERSION_VBOX_30)
4681	{
4682	for (unsigned i = 0; i < pThis->cDeviceStates; i++)
4683	{
4684	bool fPresent;
4685	rc = SSMR3GetBool(pSSM, &fPresent);
4686	AssertRCReturn(rc, rc);
4687	if (fPresent != (pThis->paDeviceStates[i].pDrvBase != NULL))
4688	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Target %u config mismatch: config=%RTbool state=%RTbool"),
4689	i, pThis->paDeviceStates[i].pDrvBase != NULL, fPresent);
4690	}
4691	}
4692	if (uPass != SSM_PASS_FINAL)
4693	return VINF_SUCCESS;
4694
4695	/* Every device first. */
4696	for (unsigned i = 0; i < pThis->cDeviceStates; i++)
4697	{
4698	PLSILOGICDEVICE pDevice = &pThis->paDeviceStates[i];
4699
4700	AssertMsg(!pDevice->cOutstandingRequests,
4701	("There are still outstanding requests on this device\n"));
4702	SSMR3GetU32(pSSM, (uint32_t *)&pDevice->cOutstandingRequests);
4703	}
4704	/* Now the main device state. */
4705	SSMR3GetU32 (pSSM, (uint32_t *)&pThis->enmState);
4706	SSMR3GetU32 (pSSM, (uint32_t *)&pThis->enmWhoInit);
4707	if (uVersion <= LSILOGIC_SAVED_STATE_VERSION_BOOL_DOORBELL)
4708	{
4709	bool fDoorbellInProgress = false;
4710
4711	/*
4712	* The doorbell status flag distinguishes only between
4713	* doorbell not in use or a Function handshake is currently in progress.
4714	*/
4715	SSMR3GetBool (pSSM, &fDoorbellInProgress);
4716	if (fDoorbellInProgress)
4717	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_FN_HANDSHAKE;
4718	else
4719	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_NOT_IN_USE;
4720	}
4721	else
4722	SSMR3GetU32(pSSM, (uint32_t *)&pThis->enmDoorbellState);
4723	SSMR3GetBool (pSSM, &pThis->fDiagnosticEnabled);
4724	SSMR3GetBool (pSSM, &pThis->fNotificationSent);
4725	SSMR3GetBool (pSSM, &pThis->fEventNotificationEnabled);
4726	SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uInterruptMask);
4727	SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uInterruptStatus);
4728	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMessage); i++)
4729	SSMR3GetU32 (pSSM, &pThis->aMessage[i]);
4730	SSMR3GetU32 (pSSM, &pThis->iMessage);
4731	SSMR3GetU32 (pSSM, &pThis->cMessage);
4732	SSMR3GetMem (pSSM, &pThis->ReplyBuffer, sizeof(pThis->ReplyBuffer));
4733	SSMR3GetU32 (pSSM, &pThis->uNextReplyEntryRead);
4734	SSMR3GetU32 (pSSM, &pThis->cReplySize);
4735	SSMR3GetU16 (pSSM, &pThis->u16IOCFaultCode);
4736	SSMR3GetU32 (pSSM, &pThis->u32HostMFAHighAddr);
4737	SSMR3GetU32 (pSSM, &pThis->u32SenseBufferHighAddr);
4738	SSMR3GetU8 (pSSM, &pThis->cMaxDevices);
4739	SSMR3GetU8 (pSSM, &pThis->cMaxBuses);
4740	SSMR3GetU16 (pSSM, &pThis->cbReplyFrame);
4741	SSMR3GetU32 (pSSM, &pThis->iDiagnosticAccess);
4742
4743	uint32_t cReplyQueueEntries, cRequestQueueEntries;
4744	SSMR3GetU32 (pSSM, &cReplyQueueEntries);
4745	SSMR3GetU32 (pSSM, &cRequestQueueEntries);
4746
4747	if ( cReplyQueueEntries != pThis->cReplyQueueEntries
4748	\|\| cRequestQueueEntries != pThis->cRequestQueueEntries)
4749	{
4750	LogFlow(("Reallocating queues cReplyQueueEntries=%u cRequestQueuEntries=%u\n",
4751	cReplyQueueEntries, cRequestQueueEntries));
4752	lsilogicR3QueuesFree(pThis);
4753	pThis->cReplyQueueEntries = cReplyQueueEntries;
4754	pThis->cRequestQueueEntries = cRequestQueueEntries;
4755	rc = lsilogicR3QueuesAlloc(pThis);
4756	if (RT_FAILURE(rc))
4757	return rc;
4758	}
4759
4760	SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uReplyFreeQueueNextEntryFreeWrite);
4761	SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uReplyFreeQueueNextAddressRead);
4762	SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uReplyPostQueueNextEntryFreeWrite);
4763	SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uReplyPostQueueNextAddressRead);
4764	SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uRequestQueueNextEntryFreeWrite);
4765	SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uRequestQueueNextAddressRead);
4766
4767	PMptConfigurationPagesSupported pPages = pThis->pConfigurationPages;
4768
4769	if (uVersion <= LSILOGIC_SAVED_STATE_VERSION_PRE_SAS)
4770	{
4771	PMptConfigurationPagesSpi pSpiPages = &pPages->u.SpiPages;
4772	MptConfigurationPagesSupported_SSM_V2 ConfigPagesV2;
4773
4774	if (pThis->enmCtrlType != LSILOGICCTRLTYPE_SCSI_SPI)
4775	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: Expected SPI SCSI controller"));
4776
4777	SSMR3GetMem(pSSM, &ConfigPagesV2,
4778	sizeof(MptConfigurationPagesSupported_SSM_V2));
4779
4780	pPages->ManufacturingPage0 = ConfigPagesV2.ManufacturingPage0;
4781	pPages->ManufacturingPage1 = ConfigPagesV2.ManufacturingPage1;
4782	pPages->ManufacturingPage2 = ConfigPagesV2.ManufacturingPage2;
4783	pPages->ManufacturingPage3 = ConfigPagesV2.ManufacturingPage3;
4784	pPages->ManufacturingPage4 = ConfigPagesV2.ManufacturingPage4;
4785	pPages->IOUnitPage0 = ConfigPagesV2.IOUnitPage0;
4786	pPages->IOUnitPage1 = ConfigPagesV2.IOUnitPage1;
4787	pPages->IOUnitPage2 = ConfigPagesV2.IOUnitPage2;
4788	pPages->IOUnitPage3 = ConfigPagesV2.IOUnitPage3;
4789	pPages->IOCPage0 = ConfigPagesV2.IOCPage0;
4790	pPages->IOCPage1 = ConfigPagesV2.IOCPage1;
4791	pPages->IOCPage2 = ConfigPagesV2.IOCPage2;
4792	pPages->IOCPage3 = ConfigPagesV2.IOCPage3;
4793	pPages->IOCPage4 = ConfigPagesV2.IOCPage4;
4794	pPages->IOCPage6 = ConfigPagesV2.IOCPage6;
4795
4796	pSpiPages->aPortPages[0].SCSISPIPortPage0 = ConfigPagesV2.aPortPages[0].SCSISPIPortPage0;
4797	pSpiPages->aPortPages[0].SCSISPIPortPage1 = ConfigPagesV2.aPortPages[0].SCSISPIPortPage1;
4798	pSpiPages->aPortPages[0].SCSISPIPortPage2 = ConfigPagesV2.aPortPages[0].SCSISPIPortPage2;
4799
4800	for (unsigned i = 0; i < RT_ELEMENTS(pPages->u.SpiPages.aBuses[0].aDevicePages); i++)
4801	{
4802	pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage0 = ConfigPagesV2.aBuses[0].aDevicePages[i].SCSISPIDevicePage0;
4803	pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage1 = ConfigPagesV2.aBuses[0].aDevicePages[i].SCSISPIDevicePage1;
4804	pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage2 = ConfigPagesV2.aBuses[0].aDevicePages[i].SCSISPIDevicePage2;
4805	pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage3 = ConfigPagesV2.aBuses[0].aDevicePages[i].SCSISPIDevicePage3;
4806	}
4807	}
4808	else
4809	{
4810	/* Queue content */
4811	for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
4812	SSMR3GetU32(pSSM, (uint32_t *)&pThis->pReplyFreeQueueBaseR3[i]);
4813	for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
4814	SSMR3GetU32(pSSM, (uint32_t *)&pThis->pReplyPostQueueBaseR3[i]);
4815	for (unsigned i = 0; i < pThis->cRequestQueueEntries; i++)
4816	SSMR3GetU32(pSSM, (uint32_t *)&pThis->pRequestQueueBaseR3[i]);
4817
4818	SSMR3GetU16(pSSM, &pThis->u16NextHandle);
4819
4820	if (uVersion > LSILOGIC_SAVED_STATE_VERSION_PRE_DIAG_MEM)
4821	{
4822	uint32_t cMemRegions = 0;
4823
4824	/* Save diagnostic memory register and data regions. */
4825	SSMR3GetU32 (pSSM, &pThis->u32DiagMemAddr);
4826	SSMR3GetU32 (pSSM, &cMemRegions);
4827
4828	while (cMemRegions)
4829	{
4830	uint32_t u32AddrStart = 0;
4831	uint32_t u32AddrEnd = 0;
4832	uint32_t cRegion = 0;
4833	PLSILOGICMEMREGN pRegion = NULL;
4834
4835	SSMR3GetU32(pSSM, &u32AddrStart);
4836	SSMR3GetU32(pSSM, &u32AddrEnd);
4837
4838	cRegion = u32AddrEnd - u32AddrStart + 1;
4839	pRegion = (PLSILOGICMEMREGN)RTMemAllocZ(RT_OFFSETOF(LSILOGICMEMREGN, au32Data[cRegion]));
4840	if (pRegion)
4841	{
4842	pRegion->u32AddrStart = u32AddrStart;
4843	pRegion->u32AddrEnd = u32AddrEnd;
4844	SSMR3GetMem(pSSM, &pRegion->au32Data[0], cRegion * sizeof(uint32_t));
4845	lsilogicR3MemRegionInsert(pThis, pRegion);
4846	pThis->cbMemRegns += cRegion * sizeof(uint32_t);
4847	}
4848	else
4849	{
4850	/* Leave a log message but continue. */
4851	LogRel(("LsiLogic: Out of memory while restoring the state, might not work as expected\n"));
4852	SSMR3Skip(pSSM, cRegion * sizeof(uint32_t));
4853	}
4854	cMemRegions--;
4855	}
4856	}
4857
4858	/* Configuration pages */
4859	SSMR3GetMem(pSSM, &pPages->ManufacturingPage0, sizeof(MptConfigurationPageManufacturing0));
4860	SSMR3GetMem(pSSM, &pPages->ManufacturingPage1, sizeof(MptConfigurationPageManufacturing1));
4861	SSMR3GetMem(pSSM, &pPages->ManufacturingPage2, sizeof(MptConfigurationPageManufacturing2));
4862	SSMR3GetMem(pSSM, &pPages->ManufacturingPage3, sizeof(MptConfigurationPageManufacturing3));
4863	SSMR3GetMem(pSSM, &pPages->ManufacturingPage4, sizeof(MptConfigurationPageManufacturing4));
4864	SSMR3GetMem(pSSM, &pPages->ManufacturingPage5, sizeof(MptConfigurationPageManufacturing5));
4865	SSMR3GetMem(pSSM, &pPages->ManufacturingPage6, sizeof(MptConfigurationPageManufacturing6));
4866	SSMR3GetMem(pSSM, &pPages->ManufacturingPage8, sizeof(MptConfigurationPageManufacturing8));
4867	SSMR3GetMem(pSSM, &pPages->ManufacturingPage9, sizeof(MptConfigurationPageManufacturing9));
4868	SSMR3GetMem(pSSM, &pPages->ManufacturingPage10, sizeof(MptConfigurationPageManufacturing10));
4869	SSMR3GetMem(pSSM, &pPages->IOUnitPage0, sizeof(MptConfigurationPageIOUnit0));
4870	SSMR3GetMem(pSSM, &pPages->IOUnitPage1, sizeof(MptConfigurationPageIOUnit1));
4871	SSMR3GetMem(pSSM, &pPages->IOUnitPage2, sizeof(MptConfigurationPageIOUnit2));
4872	SSMR3GetMem(pSSM, &pPages->IOUnitPage3, sizeof(MptConfigurationPageIOUnit3));
4873	SSMR3GetMem(pSSM, &pPages->IOUnitPage4, sizeof(MptConfigurationPageIOUnit4));
4874	SSMR3GetMem(pSSM, &pPages->IOCPage0, sizeof(MptConfigurationPageIOC0));
4875	SSMR3GetMem(pSSM, &pPages->IOCPage1, sizeof(MptConfigurationPageIOC1));
4876	SSMR3GetMem(pSSM, &pPages->IOCPage2, sizeof(MptConfigurationPageIOC2));
4877	SSMR3GetMem(pSSM, &pPages->IOCPage3, sizeof(MptConfigurationPageIOC3));
4878	SSMR3GetMem(pSSM, &pPages->IOCPage4, sizeof(MptConfigurationPageIOC4));
4879	SSMR3GetMem(pSSM, &pPages->IOCPage6, sizeof(MptConfigurationPageIOC6));
4880	SSMR3GetMem(pSSM, &pPages->BIOSPage1, sizeof(MptConfigurationPageBIOS1));
4881	SSMR3GetMem(pSSM, &pPages->BIOSPage2, sizeof(MptConfigurationPageBIOS2));
4882	SSMR3GetMem(pSSM, &pPages->BIOSPage4, sizeof(MptConfigurationPageBIOS4));
4883
4884	/* Device dependent pages */
4885	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
4886	{
4887	PMptConfigurationPagesSpi pSpiPages = &pPages->u.SpiPages;
4888
4889	SSMR3GetMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage0, sizeof(MptConfigurationPageSCSISPIPort0));
4890	SSMR3GetMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage1, sizeof(MptConfigurationPageSCSISPIPort1));
4891	SSMR3GetMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage2, sizeof(MptConfigurationPageSCSISPIPort2));
4892
4893	for (unsigned i = 0; i < RT_ELEMENTS(pSpiPages->aBuses[0].aDevicePages); i++)
4894	{
4895	SSMR3GetMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage0, sizeof(MptConfigurationPageSCSISPIDevice0));
4896	SSMR3GetMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage1, sizeof(MptConfigurationPageSCSISPIDevice1));
4897	SSMR3GetMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage2, sizeof(MptConfigurationPageSCSISPIDevice2));
4898	SSMR3GetMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage3, sizeof(MptConfigurationPageSCSISPIDevice3));
4899	}
4900	}
4901	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
4902	{
4903	uint32_t cbPage0, cbPage1, cPHYs, cbManufacturingPage7;
4904	PMptConfigurationPagesSas pSasPages = &pPages->u.SasPages;
4905
4906	SSMR3GetU32(pSSM, &cbManufacturingPage7);
4907	SSMR3GetU32(pSSM, &cbPage0);
4908	SSMR3GetU32(pSSM, &cbPage1);
4909
4910	if ( (cbPage0 != pSasPages->cbSASIOUnitPage0)
4911	\|\| (cbPage1 != pSasPages->cbSASIOUnitPage1)
4912	\|\| (cbManufacturingPage7 != pSasPages->cbManufacturingPage7))
4913	return VERR_SSM_LOAD_CONFIG_MISMATCH;
4914
4915	AssertPtr(pSasPages->pManufacturingPage7);
4916	AssertPtr(pSasPages->pSASIOUnitPage0);
4917	AssertPtr(pSasPages->pSASIOUnitPage1);
4918
4919	SSMR3GetMem(pSSM, pSasPages->pManufacturingPage7, pSasPages->cbManufacturingPage7);
4920	SSMR3GetMem(pSSM, pSasPages->pSASIOUnitPage0, pSasPages->cbSASIOUnitPage0);
4921	SSMR3GetMem(pSSM, pSasPages->pSASIOUnitPage1, pSasPages->cbSASIOUnitPage1);
4922
4923	SSMR3GetMem(pSSM, &pSasPages->SASIOUnitPage2, sizeof(MptConfigurationPageSASIOUnit2));
4924	SSMR3GetMem(pSSM, &pSasPages->SASIOUnitPage3, sizeof(MptConfigurationPageSASIOUnit3));
4925
4926	SSMR3GetU32(pSSM, &cPHYs);
4927	if (cPHYs != pSasPages->cPHYs)
4928	return VERR_SSM_LOAD_CONFIG_MISMATCH;
4929
4930	AssertPtr(pSasPages->paPHYs);
4931	for (unsigned i = 0; i < pSasPages->cPHYs; i++)
4932	{
4933	SSMR3GetMem(pSSM, &pSasPages->paPHYs[i].SASPHYPage0, sizeof(MptConfigurationPageSASPHY0));
4934	SSMR3GetMem(pSSM, &pSasPages->paPHYs[i].SASPHYPage1, sizeof(MptConfigurationPageSASPHY1));
4935	}
4936
4937	/* The number of devices first. */
4938	SSMR3GetU32(pSSM, &pSasPages->cDevices);
4939
4940	PMptSASDevice pCurr = pSasPages->pSASDeviceHead;
4941
4942	for (unsigned i = 0; i < pSasPages->cDevices; i++)
4943	{
4944	SSMR3GetMem(pSSM, &pCurr->SASDevicePage0, sizeof(MptConfigurationPageSASDevice0));
4945	SSMR3GetMem(pSSM, &pCurr->SASDevicePage1, sizeof(MptConfigurationPageSASDevice1));
4946	SSMR3GetMem(pSSM, &pCurr->SASDevicePage2, sizeof(MptConfigurationPageSASDevice2));
4947
4948	pCurr = pCurr->pNext;
4949	}
4950
4951	Assert(!pCurr);
4952	}
4953	else
4954	AssertMsgFailed(("Invalid controller type %d\n", pThis->enmCtrlType));
4955	}
4956
4957	rc = vboxscsiR3LoadExec(&pThis->VBoxSCSI, pSSM);
4958	if (RT_FAILURE(rc))
4959	{
4960	LogRel(("LsiLogic: Failed to restore BIOS state: %Rrc.\n", rc));
4961	return PDMDEV_SET_ERROR(pDevIns, rc,
4962	N_("LsiLogic: Failed to restore BIOS state\n"));
4963	}
4964
4965	uint32_t u32;
4966	rc = SSMR3GetU32(pSSM, &u32);
4967	if (RT_FAILURE(rc))
4968	return rc;
4969	AssertMsgReturn(u32 == UINT32_MAX, ("%#x\n", u32), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
4970
4971	return VINF_SUCCESS;
4972	}
4973
4974
4975	/*
4976	* The device level IBASE and LED interfaces.
4977	*/
4978
4979	/**
4980	* @interface_method_impl{PDMILEDPORTS,pfnQueryStatusLed, For a SCSI device.}
4981	*
4982	* @remarks Called by the scsi driver, proxying the main calls.
4983	*/
4984	static DECLCALLBACK(int) lsilogicR3DeviceQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
4985	{
4986	PLSILOGICDEVICE pDevice = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, ILed);
4987	if (iLUN == 0)
4988	{
4989	*ppLed = &pDevice->Led;
4990	Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
4991	return VINF_SUCCESS;
4992	}
4993	return VERR_PDM_LUN_NOT_FOUND;
4994	}
4995
4996
4997	/**
4998	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
4999	*/
5000	static DECLCALLBACK(void ) lsilogicR3DeviceQueryInterface(PPDMIBASE pInterface, const char pszIID)
5001	{
5002	PLSILOGICDEVICE pDevice = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, IBase);
5003
5004	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevice->IBase);
5005	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIMEDIAPORT, &pDevice->IMediaPort);
5006	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIMEDIAEXPORT, &pDevice->IMediaExPort);
5007	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pDevice->ILed);
5008	return NULL;
5009	}
5010
5011
5012	/*
5013	* The controller level IBASE and LED interfaces.
5014	*/
5015
5016	/**
5017	* Gets the pointer to the status LED of a unit.
5018	*
5019	* @returns VBox status code.
5020	* @param pInterface Pointer to the interface structure containing the called function pointer.
5021	* @param iLUN The unit which status LED we desire.
5022	* @param ppLed Where to store the LED pointer.
5023	*/
5024	static DECLCALLBACK(int) lsilogicR3StatusQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
5025	{
5026	PLSILOGICSCSI pThis = RT_FROM_MEMBER(pInterface, LSILOGICSCSI, ILeds);
5027	if (iLUN < pThis->cDeviceStates)
5028	{
5029	*ppLed = &pThis->paDeviceStates[iLUN].Led;
5030	Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
5031	return VINF_SUCCESS;
5032	}
5033	return VERR_PDM_LUN_NOT_FOUND;
5034	}
5035
5036	/**
5037	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
5038	*/
5039	static DECLCALLBACK(void ) lsilogicR3StatusQueryInterface(PPDMIBASE pInterface, const char pszIID)
5040	{
5041	PLSILOGICSCSI pThis = RT_FROM_MEMBER(pInterface, LSILOGICSCSI, IBase);
5042	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
5043	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
5044	return NULL;
5045	}
5046
5047
5048	/*
5049	* The PDM device interface and some helpers.
5050	*/
5051
5052	/**
5053	* Checks if all asynchronous I/O is finished.
5054	*
5055	* Used by lsilogicR3Reset, lsilogicR3Suspend and lsilogicR3PowerOff.
5056	*
5057	* @returns true if quiesced, false if busy.
5058	* @param pDevIns The device instance.
5059	*/
5060	static bool lsilogicR3AllAsyncIOIsFinished(PPDMDEVINS pDevIns)
5061	{
5062	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5063
5064	for (uint32_t i = 0; i < pThis->cDeviceStates; i++)
5065	{
5066	PLSILOGICDEVICE pThisDevice = &pThis->paDeviceStates[i];
5067	if (pThisDevice->pDrvBase)
5068	{
5069	if (pThisDevice->cOutstandingRequests != 0)
5070	return false;
5071	}
5072	}
5073
5074	return true;
5075	}
5076
5077	/**
5078	* @callback_method_impl{FNPDMDEVASYNCNOTIFY,
5079	* Callback employed by lsilogicR3Suspend and lsilogicR3PowerOff.}
5080	*/
5081	static DECLCALLBACK(bool) lsilogicR3IsAsyncSuspendOrPowerOffDone(PPDMDEVINS pDevIns)
5082	{
5083	if (!lsilogicR3AllAsyncIOIsFinished(pDevIns))
5084	return false;
5085
5086	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5087	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
5088	return true;
5089	}
5090
5091	/**
5092	* Common worker for ahciR3Suspend and ahciR3PowerOff.
5093	*/
5094	static void lsilogicR3SuspendOrPowerOff(PPDMDEVINS pDevIns)
5095	{
5096	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5097
5098	ASMAtomicWriteBool(&pThis->fSignalIdle, true);
5099	if (!lsilogicR3AllAsyncIOIsFinished(pDevIns))
5100	PDMDevHlpSetAsyncNotification(pDevIns, lsilogicR3IsAsyncSuspendOrPowerOffDone);
5101	else
5102	{
5103	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
5104
5105	AssertMsg(!pThis->fNotificationSent, ("The PDM Queue should be empty at this point\n"));
5106	}
5107	}
5108
5109	/**
5110	* @interface_method_impl{PDMDEVREG,pfnSuspend}
5111	*/
5112	static DECLCALLBACK(void) lsilogicR3Suspend(PPDMDEVINS pDevIns)
5113	{
5114	Log(("lsilogicR3Suspend\n"));
5115	lsilogicR3SuspendOrPowerOff(pDevIns);
5116	}
5117
5118	/**
5119	* @interface_method_impl{PDMDEVREG,pfnResume}
5120	*/
5121	static DECLCALLBACK(void) lsilogicR3Resume(PPDMDEVINS pDevIns)
5122	{
5123	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5124
5125	Log(("lsilogicR3Resume\n"));
5126
5127	lsilogicR3Kick(pThis);
5128	}
5129
5130	/**
5131	* @interface_method_impl{PDMDEVREG,pfnDetach}
5132	*
5133	* One harddisk at one port has been unplugged.
5134	* The VM is suspended at this point.
5135	*/
5136	static DECLCALLBACK(void) lsilogicR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
5137	{
5138	RT_NOREF(fFlags);
5139	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5140	PLSILOGICDEVICE pDevice = &pThis->paDeviceStates[iLUN];
5141
5142	if (iLUN >= pThis->cDeviceStates)
5143	return;
5144
5145	AssertMsg(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
5146	("LsiLogic: Device does not support hotplugging\n"));
5147
5148	Log(("%s:\n", __FUNCTION__));
5149
5150	/*
5151	* Zero some important members.
5152	*/
5153	pDevice->pDrvBase = NULL;
5154	pDevice->pDrvMedia = NULL;
5155	pDevice->pDrvMediaEx = NULL;
5156	}
5157
5158	/**
5159	* @interface_method_impl{PDMDEVREG,pfnAttach}
5160	*/
5161	static DECLCALLBACK(int) lsilogicR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
5162	{
5163	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5164	PLSILOGICDEVICE pDevice = &pThis->paDeviceStates[iLUN];
5165	int rc;
5166
5167	if (iLUN >= pThis->cDeviceStates)
5168	return VERR_PDM_LUN_NOT_FOUND;
5169
5170	AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
5171	("LsiLogic: Device does not support hotplugging\n"),
5172	VERR_INVALID_PARAMETER);
5173
5174	/* the usual paranoia */
5175	AssertRelease(!pDevice->pDrvBase);
5176	AssertRelease(!pDevice->pDrvMedia);
5177	AssertRelease(!pDevice->pDrvMediaEx);
5178	Assert(pDevice->iLUN == iLUN);
5179
5180	/*
5181	* Try attach the block device and get the interfaces,
5182	* required as well as optional.
5183	*/
5184	rc = PDMDevHlpDriverAttach(pDevIns, pDevice->iLUN, &pDevice->IBase, &pDevice->pDrvBase, NULL);
5185	if (RT_SUCCESS(rc))
5186	{
5187	/* Query the media interface. */
5188	pDevice->pDrvMedia = PDMIBASE_QUERY_INTERFACE(pDevice->pDrvBase, PDMIMEDIA);
5189	AssertMsgReturn(VALID_PTR(pDevice->pDrvMedia),
5190	("LsiLogic configuration error: LUN#%d misses the basic media interface!\n", pDevice->iLUN),
5191	VERR_PDM_MISSING_INTERFACE);
5192
5193	/* Get the extended media interface. */
5194	pDevice->pDrvMediaEx = PDMIBASE_QUERY_INTERFACE(pDevice->pDrvBase, PDMIMEDIAEX);
5195	AssertMsgReturn(VALID_PTR(pDevice->pDrvMediaEx),
5196	("LsiLogic configuration error: LUN#%d misses the extended media interface!\n", pDevice->iLUN),
5197	VERR_PDM_MISSING_INTERFACE);
5198
5199	rc = pDevice->pDrvMediaEx->pfnIoReqAllocSizeSet(pDevice->pDrvMediaEx, sizeof(LSILOGICREQ));
5200	AssertMsgRCReturn(rc, ("LsiLogic configuration error: LUN#%u: Failed to set I/O request size!", pDevice->iLUN),
5201	rc);
5202	}
5203	else
5204	AssertMsgFailed(("Failed to attach LUN#%d. rc=%Rrc\n", pDevice->iLUN, rc));
5205
5206	if (RT_FAILURE(rc))
5207	{
5208	pDevice->pDrvBase = NULL;
5209	pDevice->pDrvMedia = NULL;
5210	pDevice->pDrvMediaEx = NULL;
5211	}
5212	return rc;
5213	}
5214
5215	/**
5216	* Common reset worker.
5217	*
5218	* @param pDevIns The device instance data.
5219	*/
5220	static void lsilogicR3ResetCommon(PPDMDEVINS pDevIns)
5221	{
5222	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5223	int rc;
5224
5225	rc = lsilogicR3HardReset(pThis);
5226	AssertRC(rc);
5227
5228	vboxscsiInitialize(&pThis->VBoxSCSI);
5229	}
5230
5231	/**
5232	* @callback_method_impl{FNPDMDEVASYNCNOTIFY,
5233	* Callback employed by lsilogicR3Reset.}
5234	*/
5235	static DECLCALLBACK(bool) lsilogicR3IsAsyncResetDone(PPDMDEVINS pDevIns)
5236	{
5237	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5238
5239	if (!lsilogicR3AllAsyncIOIsFinished(pDevIns))
5240	return false;
5241	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
5242
5243	lsilogicR3ResetCommon(pDevIns);
5244	return true;
5245	}
5246
5247	/**
5248	* @interface_method_impl{PDMDEVREG,pfnReset}
5249	*/
5250	static DECLCALLBACK(void) lsilogicR3Reset(PPDMDEVINS pDevIns)
5251	{
5252	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5253
5254	ASMAtomicWriteBool(&pThis->fSignalIdle, true);
5255	if (!lsilogicR3AllAsyncIOIsFinished(pDevIns))
5256	PDMDevHlpSetAsyncNotification(pDevIns, lsilogicR3IsAsyncResetDone);
5257	else
5258	{
5259	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
5260	lsilogicR3ResetCommon(pDevIns);
5261	}
5262	}
5263
5264	/**
5265	* @interface_method_impl{PDMDEVREG,pfnRelocate}
5266	*/
5267	static DECLCALLBACK(void) lsilogicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
5268	{
5269	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5270
5271	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5272	pThis->pNotificationQueueRC = PDMQueueRCPtr(pThis->pNotificationQueueR3);
5273
5274	/* Relocate queues. */
5275	pThis->pReplyFreeQueueBaseRC += offDelta;
5276	pThis->pReplyPostQueueBaseRC += offDelta;
5277	pThis->pRequestQueueBaseRC += offDelta;
5278	}
5279
5280	/**
5281	* @interface_method_impl{PDMDEVREG,pfnPowerOff}
5282	*/
5283	static DECLCALLBACK(void) lsilogicR3PowerOff(PPDMDEVINS pDevIns)
5284	{
5285	Log(("lsilogicR3PowerOff\n"));
5286	lsilogicR3SuspendOrPowerOff(pDevIns);
5287	}
5288
5289	/**
5290	* @interface_method_impl{PDMDEVREG,pfnDestruct}
5291	*/
5292	static DECLCALLBACK(int) lsilogicR3Destruct(PPDMDEVINS pDevIns)
5293	{
5294	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5295	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
5296
5297	PDMR3CritSectDelete(&pThis->ReplyFreeQueueCritSect);
5298	PDMR3CritSectDelete(&pThis->ReplyPostQueueCritSect);
5299
5300	RTMemFree(pThis->paDeviceStates);
5301	pThis->paDeviceStates = NULL;
5302
5303	if (pThis->hEvtProcess != NIL_SUPSEMEVENT)
5304	{
5305	SUPSemEventClose(pThis->pSupDrvSession, pThis->hEvtProcess);
5306	pThis->hEvtProcess = NIL_SUPSEMEVENT;
5307	}
5308
5309	lsilogicR3ConfigurationPagesFree(pThis);
5310	lsilogicR3MemRegionsFree(pThis);
5311
5312	return VINF_SUCCESS;
5313	}
5314
5315	/**
5316	* @interface_method_impl{PDMDEVREG,pfnConstruct}
5317	*/
5318	static DECLCALLBACK(int) lsilogicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
5319	{
5320	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5321	int rc = VINF_SUCCESS;
5322	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5323
5324	/*
5325	* Initialize enought of the state to make the destructure not trip up.
5326	*/
5327	pThis->hEvtProcess = NIL_SUPSEMEVENT;
5328	pThis->fBiosReqPending = false;
5329	RTListInit(&pThis->ListMemRegns);
5330
5331	/*
5332	* Validate and read configuration.
5333	*/
5334	rc = CFGMR3AreValuesValid(pCfg, "GCEnabled\0"
5335	"R0Enabled\0"
5336	"ReplyQueueDepth\0"
5337	"RequestQueueDepth\0"
5338	"ControllerType\0"
5339	"NumPorts\0"
5340	"Bootable\0");
5341	if (RT_FAILURE(rc))
5342	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
5343	N_("LsiLogic configuration error: unknown option specified"));
5344	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &pThis->fGCEnabled, true);
5345	if (RT_FAILURE(rc))
5346	return PDMDEV_SET_ERROR(pDevIns, rc,
5347	N_("LsiLogic configuration error: failed to read GCEnabled as boolean"));
5348	Log(("%s: fGCEnabled=%d\n", __FUNCTION__, pThis->fGCEnabled));
5349
5350	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, true);
5351	if (RT_FAILURE(rc))
5352	return PDMDEV_SET_ERROR(pDevIns, rc,
5353	N_("LsiLogic configuration error: failed to read R0Enabled as boolean"));
5354	Log(("%s: fR0Enabled=%d\n", __FUNCTION__, pThis->fR0Enabled));
5355
5356	rc = CFGMR3QueryU32Def(pCfg, "ReplyQueueDepth",
5357	&pThis->cReplyQueueEntries,
5358	LSILOGICSCSI_REPLY_QUEUE_DEPTH_DEFAULT);
5359	if (RT_FAILURE(rc))
5360	return PDMDEV_SET_ERROR(pDevIns, rc,
5361	N_("LsiLogic configuration error: failed to read ReplyQueue as integer"));
5362	Log(("%s: ReplyQueueDepth=%u\n", __FUNCTION__, pThis->cReplyQueueEntries));
5363
5364	rc = CFGMR3QueryU32Def(pCfg, "RequestQueueDepth",
5365	&pThis->cRequestQueueEntries,
5366	LSILOGICSCSI_REQUEST_QUEUE_DEPTH_DEFAULT);
5367	if (RT_FAILURE(rc))
5368	return PDMDEV_SET_ERROR(pDevIns, rc,
5369	N_("LsiLogic configuration error: failed to read RequestQueue as integer"));
5370	Log(("%s: RequestQueueDepth=%u\n", __FUNCTION__, pThis->cRequestQueueEntries));
5371
5372	char *pszCtrlType;
5373	rc = CFGMR3QueryStringAllocDef(pCfg, "ControllerType",
5374	&pszCtrlType, LSILOGICSCSI_PCI_SPI_CTRLNAME);
5375	if (RT_FAILURE(rc))
5376	return PDMDEV_SET_ERROR(pDevIns, rc,
5377	N_("LsiLogic configuration error: failed to read ControllerType as string"));
5378	Log(("%s: ControllerType=%s\n", __FUNCTION__, pszCtrlType));
5379
5380	rc = lsilogicR3GetCtrlTypeFromString(pThis, pszCtrlType);
5381	MMR3HeapFree(pszCtrlType);
5382
5383	char szDevTag[20];
5384	RTStrPrintf(szDevTag, sizeof(szDevTag), "LSILOGIC%s-%u",
5385	pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI ? "SPI" : "SAS",
5386	iInstance);
5387
5388
5389	if (RT_FAILURE(rc))
5390	return PDMDEV_SET_ERROR(pDevIns, rc,
5391	N_("LsiLogic configuration error: failed to determine controller type from string"));
5392
5393	rc = CFGMR3QueryU8(pCfg, "NumPorts",
5394	&pThis->cPorts);
5395	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
5396	{
5397	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
5398	pThis->cPorts = LSILOGICSCSI_PCI_SPI_PORTS_MAX;
5399	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
5400	pThis->cPorts = LSILOGICSCSI_PCI_SAS_PORTS_DEFAULT;
5401	else
5402	AssertMsgFailed(("Invalid controller type: %d\n", pThis->enmCtrlType));
5403	}
5404	else if (RT_FAILURE(rc))
5405	return PDMDEV_SET_ERROR(pDevIns, rc,
5406	N_("LsiLogic configuration error: failed to read NumPorts as integer"));
5407
5408	bool fBootable;
5409	rc = CFGMR3QueryBoolDef(pCfg, "Bootable", &fBootable, true);
5410	if (RT_FAILURE(rc))
5411	return PDMDEV_SET_ERROR(pDevIns, rc,
5412	N_("LsiLogic configuration error: failed to read Bootable as boolean"));
5413	Log(("%s: Bootable=%RTbool\n", __FUNCTION__, fBootable));
5414
5415	/* Init static parts. */
5416	PCIDevSetVendorId(&pThis->PciDev, LSILOGICSCSI_PCI_VENDOR_ID); /* LsiLogic */
5417
5418	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
5419	{
5420	PCIDevSetDeviceId (&pThis->PciDev, LSILOGICSCSI_PCI_SPI_DEVICE_ID); /* LSI53C1030 */
5421	PCIDevSetSubSystemVendorId(&pThis->PciDev, LSILOGICSCSI_PCI_SPI_SUBSYSTEM_VENDOR_ID);
5422	PCIDevSetSubSystemId (&pThis->PciDev, LSILOGICSCSI_PCI_SPI_SUBSYSTEM_ID);
5423	}
5424	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
5425	{
5426	PCIDevSetDeviceId (&pThis->PciDev, LSILOGICSCSI_PCI_SAS_DEVICE_ID); /* SAS1068 */
5427	PCIDevSetSubSystemVendorId(&pThis->PciDev, LSILOGICSCSI_PCI_SAS_SUBSYSTEM_VENDOR_ID);
5428	PCIDevSetSubSystemId (&pThis->PciDev, LSILOGICSCSI_PCI_SAS_SUBSYSTEM_ID);
5429	}
5430	else
5431	AssertMsgFailed(("Invalid controller type: %d\n", pThis->enmCtrlType));
5432
5433	PCIDevSetClassProg (&pThis->PciDev, 0x00); /* SCSI */
5434	PCIDevSetClassSub (&pThis->PciDev, 0x00); /* SCSI */
5435	PCIDevSetClassBase (&pThis->PciDev, 0x01); /* Mass storage */
5436	PCIDevSetInterruptPin(&pThis->PciDev, 0x01); /* Interrupt pin A */
5437
5438	# ifdef VBOX_WITH_MSI_DEVICES
5439	PCIDevSetStatus(&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST);
5440	PCIDevSetCapabilityList(&pThis->PciDev, 0x80);
5441	# endif
5442
5443	pThis->pDevInsR3 = pDevIns;
5444	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
5445	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5446	pThis->pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
5447	pThis->IBase.pfnQueryInterface = lsilogicR3StatusQueryInterface;
5448	pThis->ILeds.pfnQueryStatusLed = lsilogicR3StatusQueryStatusLed;
5449
5450	/*
5451	* Create critical sections protecting the reply post and free queues.
5452	* Note! We do our own syncronization, so NOP the default crit sect for the device.
5453	*/
5454	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
5455	AssertRCReturn(rc, rc);
5456
5457	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->ReplyFreeQueueCritSect, RT_SRC_POS, "%sRFQ", szDevTag);
5458	if (RT_FAILURE(rc))
5459	return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic: cannot create critical section for reply free queue"));
5460
5461	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->ReplyPostQueueCritSect, RT_SRC_POS, "%sRPQ", szDevTag);
5462	if (RT_FAILURE(rc))
5463	return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic: cannot create critical section for reply post queue"));
5464
5465	/*
5466	* Register the PCI device, it's I/O regions.
5467	*/
5468	rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
5469	if (RT_FAILURE(rc))
5470	return rc;
5471
5472	# ifdef VBOX_WITH_MSI_DEVICES
5473	PDMMSIREG MsiReg;
5474	RT_ZERO(MsiReg);
5475	/* use this code for MSI-X support */
5476	# if 0
5477	MsiReg.cMsixVectors = 1;
5478	MsiReg.iMsixCapOffset = 0x80;
5479	MsiReg.iMsixNextOffset = 0x00;
5480	MsiReg.iMsixBar = 3;
5481	# else
5482	MsiReg.cMsiVectors = 1;
5483	MsiReg.iMsiCapOffset = 0x80;
5484	MsiReg.iMsiNextOffset = 0x00;
5485	# endif
5486	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
5487	if (RT_FAILURE (rc))
5488	{
5489	/* That's OK, we can work without MSI */
5490	PCIDevSetCapabilityList(&pThis->PciDev, 0x0);
5491	}
5492	# endif
5493
5494	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, LSILOGIC_PCI_SPACE_IO_SIZE, PCI_ADDRESS_SPACE_IO, lsilogicR3Map);
5495	if (RT_FAILURE(rc))
5496	return rc;
5497
5498	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 1, LSILOGIC_PCI_SPACE_MEM_SIZE, PCI_ADDRESS_SPACE_MEM, lsilogicR3Map);
5499	if (RT_FAILURE(rc))
5500	return rc;
5501
5502	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 2, LSILOGIC_PCI_SPACE_MEM_SIZE, PCI_ADDRESS_SPACE_MEM, lsilogicR3Map);
5503	if (RT_FAILURE(rc))
5504	return rc;
5505
5506	/* Initialize task queue. (Need two items to handle SMP guest concurrency.) */
5507	char szTaggedText[64];
5508	RTStrPrintf(szTaggedText, sizeof(szTaggedText), "%s-Task", szDevTag);
5509	rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 2, 0,
5510	lsilogicR3NotifyQueueConsumer, true,
5511	szTaggedText,
5512	&pThis->pNotificationQueueR3);
5513	if (RT_FAILURE(rc))
5514	return rc;
5515	pThis->pNotificationQueueR0 = PDMQueueR0Ptr(pThis->pNotificationQueueR3);
5516	pThis->pNotificationQueueRC = PDMQueueRCPtr(pThis->pNotificationQueueR3);
5517
5518	/*
5519	* We need one entry free in the queue.
5520	*/
5521	pThis->cReplyQueueEntries++;
5522	pThis->cRequestQueueEntries++;
5523
5524	/*
5525	* Allocate memory for the queues.
5526	*/
5527	rc = lsilogicR3QueuesAlloc(pThis);
5528	if (RT_FAILURE(rc))
5529	return rc;
5530
5531	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
5532	pThis->cDeviceStates = pThis->cPorts * LSILOGICSCSI_PCI_SPI_DEVICES_PER_BUS_MAX;
5533	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
5534	pThis->cDeviceStates = pThis->cPorts * LSILOGICSCSI_PCI_SAS_DEVICES_PER_PORT_MAX;
5535	else
5536	AssertMsgFailed(("Invalid controller type: %d\n", pThis->enmCtrlType));
5537
5538	/*
5539	* Create event semaphore and worker thread.
5540	*/
5541	rc = PDMDevHlpThreadCreate(pDevIns, &pThis->pThreadWrk, pThis, lsilogicR3Worker,
5542	lsilogicR3WorkerWakeUp, 0, RTTHREADTYPE_IO, szDevTag);
5543	if (RT_FAILURE(rc))
5544	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
5545	N_("LsiLogic: Failed to create worker thread %s"), szDevTag);
5546
5547	rc = SUPSemEventCreate(pThis->pSupDrvSession, &pThis->hEvtProcess);
5548	if (RT_FAILURE(rc))
5549	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
5550	N_("LsiLogic: Failed to create SUP event semaphore"));
5551
5552	/*
5553	* Allocate device states.
5554	*/
5555	pThis->paDeviceStates = (PLSILOGICDEVICE)RTMemAllocZ(sizeof(LSILOGICDEVICE) * pThis->cDeviceStates);
5556	if (!pThis->paDeviceStates)
5557	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to allocate memory for device states"));
5558
5559	for (unsigned i = 0; i < pThis->cDeviceStates; i++)
5560	{
5561	char szName[24];
5562	PLSILOGICDEVICE pDevice = &pThis->paDeviceStates[i];
5563
5564	/* Initialize static parts of the device. */
5565	pDevice->iLUN = i;
5566	pDevice->pLsiLogicR3 = pThis;
5567	pDevice->Led.u32Magic = PDMLED_MAGIC;
5568	pDevice->IBase.pfnQueryInterface = lsilogicR3DeviceQueryInterface;
5569	pDevice->IMediaPort.pfnQueryDeviceLocation = lsilogicR3QueryDeviceLocation;
5570	pDevice->IMediaExPort.pfnIoReqCompleteNotify = lsilogicR3IoReqCompleteNotify;
5571	pDevice->IMediaExPort.pfnIoReqCopyFromBuf = lsilogicR3IoReqCopyFromBuf;
5572	pDevice->IMediaExPort.pfnIoReqCopyToBuf = lsilogicR3IoReqCopyToBuf;
5573	pDevice->IMediaExPort.pfnIoReqQueryDiscardRanges = NULL;
5574	pDevice->IMediaExPort.pfnIoReqStateChanged = lsilogicR3IoReqStateChanged;
5575	pDevice->IMediaExPort.pfnMediumEjected = lsilogicR3MediumEjected;
5576	pDevice->ILed.pfnQueryStatusLed = lsilogicR3DeviceQueryStatusLed;
5577
5578	RTStrPrintf(szName, sizeof(szName), "Device%u", i);
5579
5580	/* Attach SCSI driver. */
5581	rc = PDMDevHlpDriverAttach(pDevIns, pDevice->iLUN, &pDevice->IBase, &pDevice->pDrvBase, szName);
5582	if (RT_SUCCESS(rc))
5583	{
5584	/* Query the media interface. */
5585	pDevice->pDrvMedia = PDMIBASE_QUERY_INTERFACE(pDevice->pDrvBase, PDMIMEDIA);
5586	AssertMsgReturn(VALID_PTR(pDevice->pDrvMedia),
5587	("LsiLogic configuration error: LUN#%d misses the basic media interface!\n", pDevice->iLUN),
5588	VERR_PDM_MISSING_INTERFACE);
5589
5590	/* Get the extended media interface. */
5591	pDevice->pDrvMediaEx = PDMIBASE_QUERY_INTERFACE(pDevice->pDrvBase, PDMIMEDIAEX);
5592	AssertMsgReturn(VALID_PTR(pDevice->pDrvMediaEx),
5593	("LsiLogic configuration error: LUN#%d misses the extended media interface!\n", pDevice->iLUN),
5594	VERR_PDM_MISSING_INTERFACE);
5595
5596	rc = pDevice->pDrvMediaEx->pfnIoReqAllocSizeSet(pDevice->pDrvMediaEx, sizeof(LSILOGICREQ));
5597	if (RT_FAILURE(rc))
5598	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
5599	N_("LsiLogic configuration error: LUN#%u: Failed to set I/O request size!"),
5600	pDevice->iLUN);
5601	}
5602	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5603	{
5604	pDevice->pDrvBase = NULL;
5605	rc = VINF_SUCCESS;
5606	Log(("LsiLogic: no driver attached to device %s\n", szName));
5607	}
5608	else
5609	{
5610	AssertLogRelMsgFailed(("LsiLogic: Failed to attach %s\n", szName));
5611	return rc;
5612	}
5613	}
5614
5615	/*
5616	* Attach status driver (optional).
5617	*/
5618	PPDMIBASE pBase;
5619	rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThis->IBase, &pBase, "Status Port");
5620	if (RT_SUCCESS(rc))
5621	pThis->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
5622	else if (rc != VERR_PDM_NO_ATTACHED_DRIVER)
5623	{
5624	AssertMsgFailed(("Failed to attach to status driver. rc=%Rrc\n", rc));
5625	return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic cannot attach to status driver"));
5626	}
5627
5628	/* Initialize the SCSI emulation for the BIOS. */
5629	rc = vboxscsiInitialize(&pThis->VBoxSCSI);
5630	AssertRC(rc);
5631
5632	/*
5633	* Register I/O port space in ISA region for BIOS access
5634	* if the controller is marked as bootable.
5635	*/
5636	if (fBootable)
5637	{
5638	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
5639	rc = PDMDevHlpIOPortRegister(pDevIns, LSILOGIC_BIOS_IO_PORT, 4, NULL,
5640	lsilogicR3IsaIOPortWrite, lsilogicR3IsaIOPortRead,
5641	lsilogicR3IsaIOPortWriteStr, lsilogicR3IsaIOPortReadStr,
5642	"LsiLogic BIOS");
5643	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
5644	rc = PDMDevHlpIOPortRegister(pDevIns, LSILOGIC_SAS_BIOS_IO_PORT, 4, NULL,
5645	lsilogicR3IsaIOPortWrite, lsilogicR3IsaIOPortRead,
5646	lsilogicR3IsaIOPortWriteStr, lsilogicR3IsaIOPortReadStr,
5647	"LsiLogic SAS BIOS");
5648	else
5649	AssertMsgFailed(("Invalid controller type %d\n", pThis->enmCtrlType));
5650
5651	if (RT_FAILURE(rc))
5652	return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic cannot register legacy I/O handlers"));
5653	}
5654
5655	/* Register save state handlers. */
5656	rc = PDMDevHlpSSMRegisterEx(pDevIns, LSILOGIC_SAVED_STATE_VERSION, sizeof(*pThis), NULL,
5657	NULL, lsilogicR3LiveExec, NULL,
5658	NULL, lsilogicR3SaveExec, NULL,
5659	NULL, lsilogicR3LoadExec, lsilogicR3LoadDone);
5660	if (RT_FAILURE(rc))
5661	return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic cannot register save state handlers"));
5662
5663	pThis->enmWhoInit = LSILOGICWHOINIT_SYSTEM_BIOS;
5664
5665	/*
5666	* Register the info item.
5667	*/
5668	char szTmp[128];
5669	RTStrPrintf(szTmp, sizeof(szTmp), "%s%u", pDevIns->pReg->szName, pDevIns->iInstance);
5670	PDMDevHlpDBGFInfoRegister(pDevIns, szTmp,
5671	pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI
5672	? "LsiLogic SPI info."
5673	: "LsiLogic SAS info.", lsilogicR3Info);
5674
5675	/* Perform hard reset. */
5676	rc = lsilogicR3HardReset(pThis);
5677	AssertRC(rc);
5678
5679	return rc;
5680	}
5681
5682	/**
5683	* The device registration structure - SPI SCSI controller.
5684	*/
5685	const PDMDEVREG g_DeviceLsiLogicSCSI =
5686	{
5687	/* u32Version */
5688	PDM_DEVREG_VERSION,
5689	/* szName */
5690	"lsilogicscsi",
5691	/* szRCMod */
5692	"VBoxDDRC.rc",
5693	/* szR0Mod */
5694	"VBoxDDR0.r0",
5695	/* pszDescription */
5696	"LSI Logic 53c1030 SCSI controller.\n",
5697	/* fFlags */
5698	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0 \|
5699	PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION \| PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION,
5700	/* fClass */
5701	PDM_DEVREG_CLASS_STORAGE,
5702	/* cMaxInstances */
5703	~0U,
5704	/* cbInstance */
5705	sizeof(LSILOGICSCSI),
5706	/* pfnConstruct */
5707	lsilogicR3Construct,
5708	/* pfnDestruct */
5709	lsilogicR3Destruct,
5710	/* pfnRelocate */
5711	lsilogicR3Relocate,
5712	/* pfnMemSetup */
5713	NULL,
5714	/* pfnPowerOn */
5715	NULL,
5716	/* pfnReset */
5717	lsilogicR3Reset,
5718	/* pfnSuspend */
5719	lsilogicR3Suspend,
5720	/* pfnResume */
5721	lsilogicR3Resume,
5722	/* pfnAttach */
5723	lsilogicR3Attach,
5724	/* pfnDetach */
5725	lsilogicR3Detach,
5726	/* pfnQueryInterface. */
5727	NULL,
5728	/* pfnInitComplete */
5729	NULL,
5730	/* pfnPowerOff */
5731	lsilogicR3PowerOff,
5732	/* pfnSoftReset */
5733	NULL,
5734	/* u32VersionEnd */
5735	PDM_DEVREG_VERSION
5736	};
5737
5738	/**
5739	* The device registration structure - SAS controller.
5740	*/
5741	const PDMDEVREG g_DeviceLsiLogicSAS =
5742	{
5743	/* u32Version */
5744	PDM_DEVREG_VERSION,
5745	/* szName */
5746	"lsilogicsas",
5747	/* szRCMod */
5748	"VBoxDDRC.rc",
5749	/* szR0Mod */
5750	"VBoxDDR0.r0",
5751	/* pszDescription */
5752	"LSI Logic SAS1068 controller.\n",
5753	/* fFlags */
5754	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0 \|
5755	PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION \| PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION \|
5756	PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION,
5757	/* fClass */
5758	PDM_DEVREG_CLASS_STORAGE,
5759	/* cMaxInstances */
5760	~0U,
5761	/* cbInstance */
5762	sizeof(LSILOGICSCSI),
5763	/* pfnConstruct */
5764	lsilogicR3Construct,
5765	/* pfnDestruct */
5766	lsilogicR3Destruct,
5767	/* pfnRelocate */
5768	lsilogicR3Relocate,
5769	/* pfnMemSetup */
5770	NULL,
5771	/* pfnPowerOn */
5772	NULL,
5773	/* pfnReset */
5774	lsilogicR3Reset,
5775	/* pfnSuspend */
5776	lsilogicR3Suspend,
5777	/* pfnResume */
5778	lsilogicR3Resume,
5779	/* pfnAttach */
5780	lsilogicR3Attach,
5781	/* pfnDetach */
5782	lsilogicR3Detach,
5783	/* pfnQueryInterface. */
5784	NULL,
5785	/* pfnInitComplete */
5786	NULL,
5787	/* pfnPowerOff */
5788	lsilogicR3PowerOff,
5789	/* pfnSoftReset */
5790	NULL,
5791	/* u32VersionEnd */
5792	PDM_DEVREG_VERSION
5793	};
5794
5795	#endif /* IN_RING3 */
5796	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Storage/DevLsiLogicSCSI.cpp@ 64362

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