DevLsiLogicSCSI.cpp@ 90330

Last change on this file since 90330 was 89196, checked in by vboxsync, 4 years ago
Devices/Storage/DevLsiLogicSCSI,Devices/testcase: Get rid of the VBoxSCSI interface now that we have proper drivers in the BIOS, bugref:4841 [doxygen fix]
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1	/* $Id: DevLsiLogicSCSI.cpp 89196 2021-05-20 09:34:30Z vboxsync $ */
2	/** @file
3	* DevLsiLogicSCSI - LsiLogic LSI53c1030 SCSI controller.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_LSILOGICSCSI
23	#include <VBox/vmm/pdmdev.h>
24	#include <VBox/vmm/pdmstorageifs.h>
25	#include <VBox/vmm/pdmqueue.h>
26	#include <VBox/vmm/pdmthread.h>
27	#include <VBox/vmm/pdmcritsect.h>
28	#include <VBox/AssertGuest.h>
29	#include <VBox/scsi.h>
30	#include <VBox/sup.h>
31	#include <iprt/assert.h>
32	#include <iprt/asm.h>
33	#include <iprt/string.h>
34	#include <iprt/list.h>
35	#ifdef IN_RING3
36	# include <iprt/memcache.h>
37	# include <iprt/mem.h>
38	# include <iprt/param.h>
39	# include <iprt/uuid.h>
40	# include <iprt/time.h>
41	#endif
42
43	#include "DevLsiLogicSCSI.h"
44	#include "VBoxSCSI.h"
45
46	#include "VBoxDD.h"
47
48
49	/*********************************************************************************************************************************
50	* Defined Constants And Macros *
51	*********************************************************************************************************************************/
52	/** The current saved state version. */
53	#define LSILOGIC_SAVED_STATE_VERSION 6
54	/** The saved state version used by VirtualBox before removal of the
55	* VBoxSCSI BIOS interface. */
56	#define LSILOGIC_SAVED_STATE_VERSION_PRE_VBOXSCSI_REMOVAL 5
57	/** The saved state version used by VirtualBox before the diagnostic
58	* memory access was implemented. */
59	#define LSILOGIC_SAVED_STATE_VERSION_PRE_DIAG_MEM 4
60	/** The saved state version used by VirtualBox before the doorbell status flag
61	* was changed from bool to a 32bit enum. */
62	#define LSILOGIC_SAVED_STATE_VERSION_BOOL_DOORBELL 3
63	/** The saved state version used by VirtualBox before SAS support was added. */
64	#define LSILOGIC_SAVED_STATE_VERSION_PRE_SAS 2
65	/** The saved state version used by VirtualBox 3.0 and earlier. It does not
66	* include the device config part. */
67	#define LSILOGIC_SAVED_STATE_VERSION_VBOX_30 1
68
69	/** Maximum number of entries in the release log. */
70	#define MAX_REL_LOG_ERRORS 1024
71
72	#define LSILOGIC_RTGCPHYS_FROM_U32(Hi, Lo) ( (RTGCPHYS)RT_MAKE_U64(Lo, Hi) )
73
74	/** Upper number a buffer is freed if it was too big before. */
75	#define LSILOGIC_MAX_ALLOC_TOO_MUCH 20
76
77	/** Maximum size of the memory regions (prevents teh guest from DOSing the host by
78	* allocating loadds of memory). */
79	#define LSILOGIC_MEMORY_REGIONS_MAX _1M
80
81
82	/*********************************************************************************************************************************
83	* Structures and Typedefs *
84	*********************************************************************************************************************************/
85
86	/** Pointer to the shared instance data for the LsiLogic emulation. */
87	typedef struct LSILOGICSCSI *PLSILOGICSCSI;
88
89	#ifdef IN_RING3
90	/**
91	* Memory buffer callback.
92	*
93	* @returns nothing.
94	* @param pDevIns The device instance.
95	* @param GCPhys The guest physical address of the memory buffer.
96	* @param pSgBuf The pointer to the host R3 S/G buffer.
97	* @param cbCopy How many bytes to copy between the two buffers.
98	* @param pcbSkip Initially contains the amount of bytes to skip
99	* starting from the guest physical address before
100	* accessing the S/G buffer and start copying data.
101	* On return this contains the remaining amount if
102	* cbCopy < *pcbSkip or 0 otherwise.
103	*/
104	typedef DECLCALLBACKTYPE(void, FNLSILOGICR3MEMCOPYCALLBACK,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys,
105	PRTSGBUF pSgBuf, size_t cbCopy, size_t *pcbSkip));
106	/** Pointer to a memory copy buffer callback. */
107	typedef FNLSILOGICR3MEMCOPYCALLBACK *PFNLSILOGICR3MEMCOPYCALLBACK;
108	#endif
109
110	/**
111	* Reply data.
112	*/
113	typedef struct LSILOGICSCSIREPLY
114	{
115	/** Lower 32 bits of the reply address in memory. */
116	uint32_t u32HostMFALowAddress;
117	/** Full address of the reply in guest memory. */
118	RTGCPHYS GCPhysReplyAddress;
119	/** Size of the reply. */
120	uint32_t cbReply;
121	/** Different views to the reply depending on the request type. */
122	MptReplyUnion Reply;
123	} LSILOGICSCSIREPLY;
124	/** Pointer to reply data. */
125	typedef LSILOGICSCSIREPLY *PLSILOGICSCSIREPLY;
126
127	/**
128	* Memory region of the IOC.
129	*/
130	typedef struct LSILOGICMEMREGN
131	{
132	/** List node. */
133	RTLISTNODE NodeList;
134	/** 32bit address the region starts to describe. */
135	uint32_t u32AddrStart;
136	/** 32bit address the region ends (inclusive). */
137	uint32_t u32AddrEnd;
138	/** Data for this region - variable. */
139	uint32_t au32Data[1];
140	} LSILOGICMEMREGN;
141	/** Pointer to a memory region. */
142	typedef LSILOGICMEMREGN *PLSILOGICMEMREGN;
143
144	/**
145	* State of a device attached to the buslogic host adapter.
146	*
147	* @implements PDMIBASE
148	* @implements PDMISCSIPORT
149	* @implements PDMILEDPORTS
150	*/
151	typedef struct LSILOGICDEVICE
152	{
153	/** Pointer to the owning lsilogic device instance - R3 pointer */
154	PPDMDEVINSR3 pDevIns;
155
156	/** LUN of the device. */
157	uint32_t iLUN;
158	/** Number of outstanding tasks on the port. */
159	volatile uint32_t cOutstandingRequests;
160
161	/** Our base interface. */
162	PDMIBASE IBase;
163	/** Media port interface. */
164	PDMIMEDIAPORT IMediaPort;
165	/** Extended media port interface. */
166	PDMIMEDIAEXPORT IMediaExPort;
167	/** Led interface. */
168	PDMILEDPORTS ILed;
169	/** Pointer to the attached driver's base interface. */
170	R3PTRTYPE(PPDMIBASE) pDrvBase;
171	/** Pointer to the attached driver's media interface. */
172	R3PTRTYPE(PPDMIMEDIA) pDrvMedia;
173	/** Pointer to the attached driver's extended media interface. */
174	R3PTRTYPE(PPDMIMEDIAEX) pDrvMediaEx;
175	/** The status LED state for this device. */
176	PDMLED Led;
177	/** Device name. */
178	char szName[16];
179	} LSILOGICDEVICE;
180	/** Pointer to a device state. */
181	typedef LSILOGICDEVICE *PLSILOGICDEVICE;
182
183	/** Pointer to a task state. */
184	typedef struct LSILOGICREQ *PLSILOGICREQ;
185
186
187	/**
188	* Shared instance data for the LsiLogic emulation.
189	*/
190	typedef struct LSILOGICSCSI
191	{
192	/** The state the controller is currently in. */
193	LSILOGICSTATE enmState;
194	/** Who needs to init the driver to get into operational state. */
195	LSILOGICWHOINIT enmWhoInit;
196	/** Flag whether we are in doorbell function. */
197	LSILOGICDOORBELLSTATE enmDoorbellState;
198	/** Flag whether diagnostic access is enabled. */
199	bool fDiagnosticEnabled;
200	/** Flag whether a notification was send to R3. */
201	bool fNotificationSent;
202	/** Flag whether the guest enabled event notification from the IOC. */
203	bool fEventNotificationEnabled;
204	/** Flag whether the diagnostic address and RW registers are enabled. */
205	bool fDiagRegsEnabled;
206
207	/** Number of device states allocated. */
208	uint32_t cDeviceStates;
209	uint32_t u32Padding1;
210
211	/** Interrupt mask. */
212	volatile uint32_t uInterruptMask;
213	/** Interrupt status register. */
214	volatile uint32_t uInterruptStatus;
215
216	/** Buffer for messages which are passed through the doorbell using the
217	* handshake method. */
218	uint32_t aMessage[sizeof(MptConfigurationRequest)]; /** @todo r=bird: Looks like 4 times the required size? Please explain in comment if this correct... */
219	/** Actual position in the buffer. */
220	uint32_t iMessage;
221	/** Size of the message which is given in the doorbell message in dwords. */
222	uint32_t cMessage;
223
224	/** Reply buffer.
225	* @note 60 bytes */
226	MptReplyUnion ReplyBuffer;
227	/** Next entry to read. */
228	uint32_t uNextReplyEntryRead;
229	/** Size of the reply in the buffer in 16bit words. */
230	uint32_t cReplySize;
231
232	/** The fault code of the I/O controller if we are in the fault state. */
233	uint16_t u16IOCFaultCode;
234	uint16_t u16Padding2;
235
236	/** Upper 32 bits of the message frame address to locate requests in guest memory. */
237	uint32_t u32HostMFAHighAddr;
238	/** Upper 32 bits of the sense buffer address. */
239	uint32_t u32SenseBufferHighAddr;
240	/** Maximum number of devices the driver reported he can handle. */
241	uint8_t cMaxDevices;
242	/** Maximum number of buses the driver reported he can handle. */
243	uint8_t cMaxBuses;
244	/** Current size of reply message frames in the guest. */
245	uint16_t cbReplyFrame;
246
247	/** Next key to write in the sequence to get access
248	* to diagnostic memory. */
249	uint32_t iDiagnosticAccess;
250
251	/** Number entries configured for the reply queue. */
252	uint32_t cReplyQueueEntries;
253	/** Number entries configured for the outstanding request queue. */
254	uint32_t cRequestQueueEntries;
255
256	/** Critical section protecting the reply post queue. */
257	PDMCRITSECT ReplyPostQueueCritSect;
258	/** Critical section protecting the reply free queue. */
259	PDMCRITSECT ReplyFreeQueueCritSect;
260	/** Critical section protecting the request queue against
261	* concurrent access from the guest. */
262	PDMCRITSECT RequestQueueCritSect;
263	/** Critical section protecting the reply free queue against
264	* concurrent write access from the guest. */
265	PDMCRITSECT ReplyFreeQueueWriteCritSect;
266
267	/** The reply free qeueue (only the first cReplyQueueEntries are used). */
268	uint32_t volatile aReplyFreeQueue[LSILOGICSCSI_REPLY_QUEUE_DEPTH_MAX];
269	/** The reply post qeueue (only the first cReplyQueueEntries are used). */
270	uint32_t volatile aReplyPostQueue[LSILOGICSCSI_REPLY_QUEUE_DEPTH_MAX];
271	/** The request qeueue (only the first cRequestQueueEntries are used). */
272	uint32_t volatile aRequestQueue[LSILOGICSCSI_REQUEST_QUEUE_DEPTH_MAX];
273
274	/** Next free entry in the reply queue the guest can write a address to. */
275	volatile uint32_t uReplyFreeQueueNextEntryFreeWrite;
276	/** Next valid entry the controller can read a valid address for reply frames from. */
277	volatile uint32_t uReplyFreeQueueNextAddressRead;
278
279	/** Next free entry in the reply queue the guest can write a address to. */
280	volatile uint32_t uReplyPostQueueNextEntryFreeWrite;
281	/** Next valid entry the controller can read a valid address for reply frames from. */
282	volatile uint32_t uReplyPostQueueNextAddressRead;
283
284	/** Next free entry the guest can write a address to a request frame to. */
285	volatile uint32_t uRequestQueueNextEntryFreeWrite;
286	/** Next valid entry the controller can read a valid address for request frames from. */
287	volatile uint32_t uRequestQueueNextAddressRead;
288
289	/** Indicates that PDMDevHlpAsyncNotificationCompleted should be called when
290	* a port is entering the idle state. */
291	bool volatile fSignalIdle;
292	/** Flag whether the worker thread is sleeping. */
293	volatile bool fWrkThreadSleeping;
294	bool afPadding3[2];
295
296	/** Current address to read from or write to in the diagnostic memory region. */
297	uint32_t u32DiagMemAddr;
298
299	/** Emulated controller type */
300	LSILOGICCTRLTYPE enmCtrlType;
301	/** Handle counter */
302	uint16_t u16NextHandle;
303
304	/** Number of ports this controller has. */
305	uint8_t cPorts;
306	uint8_t afPadding4;
307
308	/** The event semaphore the processing thread waits on. */
309	SUPSEMEVENT hEvtProcess;
310
311	/** PCI Region \#0: I/O ports register access. */
312	IOMIOPORTHANDLE hIoPortsReg;
313	/** PCI Region \#1: MMIO register access. */
314	IOMMMIOHANDLE hMmioReg;
315	/** PCI Region \#2: MMIO diag. */
316	IOMMMIOHANDLE hMmioDiag;
317	/** ISA Ports for the BIOS (when booting is configured). */
318	IOMIOPORTHANDLE hIoPortsBios;
319	} LSILOGICSCSI;
320	AssertCompileMemberAlignment(LSILOGICSCSI, ReplyPostQueueCritSect, 8);
321
322	/**
323	* Ring-3 instance data for the LsiLogic emulation.
324	*/
325	typedef struct LSILOGICSCSIR3
326	{
327	/** States for attached devices. */
328	R3PTRTYPE(PLSILOGICDEVICE) paDeviceStates;
329	/** Status LUN: The base interface. */
330	PDMIBASE IBase;
331	/** Status LUN: Leds interface. */
332	PDMILEDPORTS ILeds;
333	/** Status LUN: Partner of ILeds. */
334	R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
335	/** Status LUN: Media Notifys. */
336	R3PTRTYPE(PPDMIMEDIANOTIFY) pMediaNotify;
337	/** Pointer to the configuration page area. */
338	R3PTRTYPE(PMptConfigurationPagesSupported) pConfigurationPages;
339
340	/** Current size of the memory regions. */
341	uint32_t cbMemRegns;
342	uint32_t u32Padding3;
343
344	/** Critical section protecting the memory regions. */
345	RTCRITSECT CritSectMemRegns;
346	/** List of memory regions - PLSILOGICMEMREGN. */
347	RTLISTANCHORR3 ListMemRegns;
348
349	/** Worker thread. */
350	R3PTRTYPE(PPDMTHREAD) pThreadWrk;
351
352	/** The device instace - only for getting bearings in interface methods. */
353	PPDMDEVINSR3 pDevIns;
354	} LSILOGICSCSIR3;
355	/** Pointer to the ring-3 instance data for the LsiLogic emulation. */
356	typedef LSILOGICSCSIR3 *PLSILOGICSCSIR3;
357
358
359	/**
360	* Ring-0 instance data for the LsiLogic emulation.
361	*/
362	typedef struct LSILOGICSCSIR0
363	{
364	uint64_t u64Unused;
365	} LSILOGICSCSIR0;
366	/** Pointer to the ring-0 instance data for the LsiLogic emulation. */
367	typedef LSILOGICSCSIR0 *PLSILOGICSCSIR0;
368
369
370	/**
371	* Raw-mode instance data for the LsiLogic emulation.
372	*/
373	typedef struct LSILOGICSCSIRC
374	{
375	uint64_t u64Unused;
376	} LSILOGICSCSIRC;
377	/** Pointer to the raw-mode instance data for the LsiLogic emulation. */
378	typedef LSILOGICSCSIRC *PLSILOGICSCSIRC;
379
380
381	/** The current context instance data for the LsiLogic emulation. */
382	typedef CTX_SUFF(LSILOGICSCSI) LSILOGICSCSICC;
383	/** Pointer to the current context instance data for the LsiLogic emulation. */
384	typedef CTX_SUFF(PLSILOGICSCSI) PLSILOGICSCSICC;
385
386
387	/**
388	* Task state object which holds all necessary data while
389	* processing the request from the guest.
390	*/
391	typedef struct LSILOGICREQ
392	{
393	/** I/O request handle. */
394	PDMMEDIAEXIOREQ hIoReq;
395	/** Next in the redo list. */
396	PLSILOGICREQ pRedoNext;
397	/** Target device. */
398	PLSILOGICDEVICE pTargetDevice;
399	/** The message request from the guest. */
400	MptRequestUnion GuestRequest;
401	/** Address of the message request frame in guests memory.
402	* Used to read the S/G entries in the second step. */
403	RTGCPHYS GCPhysMessageFrameAddr;
404	/** Physical start address of the S/G list. */
405	RTGCPHYS GCPhysSgStart;
406	/** Chain offset */
407	uint32_t cChainOffset;
408	/** Pointer to the sense buffer. */
409	uint8_t abSenseBuffer[18];
410	/** SCSI status code. */
411	uint8_t u8ScsiSts;
412	} LSILOGICREQ;
413
414
415	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
416
417
418	/*********************************************************************************************************************************
419	* Internal Functions *
420	*********************************************************************************************************************************/
421	RT_C_DECLS_BEGIN
422	#ifdef IN_RING3
423	static void lsilogicR3InitializeConfigurationPages(PPDMDEVINS pDevIns, PLSILOGICSCSI pThis, PLSILOGICSCSICC pThisCC);
424	static void lsilogicR3ConfigurationPagesFree(PLSILOGICSCSI pThis, PLSILOGICSCSICC pThisCC);
425	static int lsilogicR3ProcessConfigurationRequest(PPDMDEVINS pDevIns, PLSILOGICSCSI pThis, PLSILOGICSCSICC pThisCC,
426	PMptConfigurationRequest pConfigurationReq, PMptConfigurationReply pReply);
427	#endif
428	RT_C_DECLS_END
429
430
431	/*********************************************************************************************************************************
432	* Global Variables *
433	*********************************************************************************************************************************/
434	/** Key sequence the guest has to write to enable access
435	* to diagnostic memory. */
436	static const uint8_t g_lsilogicDiagnosticAccess[] = {0x04, 0x0b, 0x02, 0x07, 0x0d};
437
438	/**
439	* Updates the status of the interrupt pin of the device.
440	*
441	* @returns nothing.
442	* @param pDevIns The device instance.
443	* @param pThis Pointer to the shared LsiLogic device state.
444	*/
445	static void lsilogicUpdateInterrupt(PPDMDEVINS pDevIns, PLSILOGICSCSI pThis)
446	{
447	uint32_t uIntSts;
448
449	LogFlowFunc(("Updating interrupts\n"));
450
451	/* Mask out doorbell status so that it does not affect interrupt updating. */
452	uIntSts = (ASMAtomicReadU32(&pThis->uInterruptStatus) & ~LSILOGIC_REG_HOST_INTR_STATUS_DOORBELL_STS);
453	/* Check maskable interrupts. */
454	uIntSts &= ~(ASMAtomicReadU32(&pThis->uInterruptMask) & ~LSILOGIC_REG_HOST_INTR_MASK_IRQ_ROUTING);
455
456	if (uIntSts)
457	{
458	LogFlowFunc(("Setting interrupt\n"));
459	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
460	}
461	else
462	{
463	LogFlowFunc(("Clearing interrupt\n"));
464	PDMDevHlpPCISetIrq(pDevIns, 0, 0);
465	}
466	}
467
468	/**
469	* Sets a given interrupt status bit in the status register and
470	* updates the interrupt status.
471	*
472	* @returns nothing.
473	* @param pDevIns The device instance.
474	* @param pThis Pointer to the shared LsiLogic device state.
475	* @param uStatus The status bit to set.
476	*/
477	DECLINLINE(void) lsilogicSetInterrupt(PPDMDEVINS pDevIns, PLSILOGICSCSI pThis, uint32_t uStatus)
478	{
479	ASMAtomicOrU32(&pThis->uInterruptStatus, uStatus);
480	lsilogicUpdateInterrupt(pDevIns, pThis);
481	}
482
483	/**
484	* Clears a given interrupt status bit in the status register and
485	* updates the interrupt status.
486	*
487	* @returns nothing.
488	* @param pDevIns The device instance.
489	* @param pThis Pointer to the shared LsiLogic device state.
490	* @param uStatus The status bit to set.
491	*/
492	DECLINLINE(void) lsilogicClearInterrupt(PPDMDEVINS pDevIns, PLSILOGICSCSI pThis, uint32_t uStatus)
493	{
494	ASMAtomicAndU32(&pThis->uInterruptStatus, ~uStatus);
495	lsilogicUpdateInterrupt(pDevIns, pThis);
496	}
497
498
499	#ifdef IN_RING3
500	/**
501	* Sets the I/O controller into fault state and sets the fault code.
502	*
503	* @returns nothing
504	* @param pThis Pointer to the shared LsiLogic device state.
505	* @param uIOCFaultCode Fault code to set.
506	*/
507	DECLINLINE(void) lsilogicSetIOCFaultCode(PLSILOGICSCSI pThis, uint16_t uIOCFaultCode)
508	{
509	if (pThis->enmState != LSILOGICSTATE_FAULT)
510	{
511	LogFunc(("Setting I/O controller into FAULT state: uIOCFaultCode=%u\n", uIOCFaultCode));
512	pThis->enmState = LSILOGICSTATE_FAULT;
513	pThis->u16IOCFaultCode = uIOCFaultCode;
514	}
515	else
516	LogFunc(("We are already in FAULT state\n"));
517	}
518	#endif /* IN_RING3 */
519
520
521	/**
522	* Returns the number of frames in the reply free queue.
523	*
524	* @returns Number of frames in the reply free queue.
525	* @param pThis Pointer to the shared LsiLogic device state.
526	*/
527	DECLINLINE(uint32_t) lsilogicReplyFreeQueueGetFrameCount(PLSILOGICSCSI pThis)
528	{
529	uint32_t cReplyFrames = 0;
530
531	if (pThis->uReplyFreeQueueNextAddressRead <= pThis->uReplyFreeQueueNextEntryFreeWrite)
532	cReplyFrames = pThis->uReplyFreeQueueNextEntryFreeWrite - pThis->uReplyFreeQueueNextAddressRead;
533	else
534	cReplyFrames = pThis->cReplyQueueEntries - pThis->uReplyFreeQueueNextAddressRead + pThis->uReplyFreeQueueNextEntryFreeWrite;
535
536	return cReplyFrames;
537	}
538
539	#ifdef IN_RING3
540
541	/**
542	* Returns the number of free entries in the reply post queue.
543	*
544	* @returns Number of frames in the reply free queue.
545	* @param pThis Pointer to the shared LsiLogic device state.
546	*/
547	DECLINLINE(uint32_t) lsilogicReplyPostQueueGetFrameCount(PLSILOGICSCSI pThis)
548	{
549	uint32_t cReplyFrames = 0;
550
551	if (pThis->uReplyPostQueueNextAddressRead <= pThis->uReplyPostQueueNextEntryFreeWrite)
552	cReplyFrames = pThis->cReplyQueueEntries - pThis->uReplyPostQueueNextEntryFreeWrite + pThis->uReplyPostQueueNextAddressRead;
553	else
554	cReplyFrames = pThis->uReplyPostQueueNextEntryFreeWrite - pThis->uReplyPostQueueNextAddressRead;
555
556	return cReplyFrames;
557	}
558
559
560	/**
561	* Performs a hard reset on the controller.
562	*
563	* @returns VBox status code.
564	* @param pDevIns The device instance.
565	* @param pThis Pointer to the shared LsiLogic device state.
566	* @param pThisCC Pointer to the ring-3 LsiLogic device state.
567	*/
568	static int lsilogicR3HardReset(PPDMDEVINS pDevIns, PLSILOGICSCSI pThis, PLSILOGICSCSICC pThisCC)
569	{
570	pThis->enmState = LSILOGICSTATE_RESET;
571	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_NOT_IN_USE;
572
573	/* The interrupts are masked out. */
574	pThis->uInterruptMask \|= LSILOGIC_REG_HOST_INTR_MASK_DOORBELL
575	\| LSILOGIC_REG_HOST_INTR_MASK_REPLY;
576	/* Reset interrupt states. */
577	pThis->uInterruptStatus = 0;
578	lsilogicUpdateInterrupt(pDevIns, pThis);
579
580	/* Reset the queues. */
581	pThis->uReplyFreeQueueNextEntryFreeWrite = 0;
582	pThis->uReplyFreeQueueNextAddressRead = 0;
583	pThis->uReplyPostQueueNextEntryFreeWrite = 0;
584	pThis->uReplyPostQueueNextAddressRead = 0;
585	pThis->uRequestQueueNextEntryFreeWrite = 0;
586	pThis->uRequestQueueNextAddressRead = 0;
587
588	/* Disable diagnostic access. */
589	pThis->iDiagnosticAccess = 0;
590	pThis->fDiagnosticEnabled = false;
591	pThis->fDiagRegsEnabled = false;
592
593	/* Set default values. */
594	pThis->cMaxDevices = pThis->cDeviceStates;
595	pThis->cMaxBuses = 1;
596	pThis->cbReplyFrame = 128; /** @todo Figure out where it is needed. */
597	pThis->u16NextHandle = 1;
598	pThis->u32DiagMemAddr = 0;
599
600	lsilogicR3InitializeConfigurationPages(pDevIns, pThis, pThisCC);
601
602	/* Mark that we finished performing the reset. */
603	pThis->enmState = LSILOGICSTATE_READY;
604	return VINF_SUCCESS;
605	}
606
607	/**
608	* Allocates the configuration pages based on the device.
609	*
610	* @returns nothing.
611	* @param pThis Pointer to the shared LsiLogic device state.
612	* @param pThisCC Pointer to the ring-3 LsiLogic device state.
613	*/
614	static int lsilogicR3ConfigurationPagesAlloc(PLSILOGICSCSI pThis, PLSILOGICSCSICC pThisCC)
615	{
616	pThisCC->pConfigurationPages = (PMptConfigurationPagesSupported)RTMemAllocZ(sizeof(MptConfigurationPagesSupported));
617	if (!pThisCC->pConfigurationPages)
618	return VERR_NO_MEMORY;
619
620	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
621	{
622	PMptConfigurationPagesSas pPages = &pThisCC->pConfigurationPages->u.SasPages;
623
624	pPages->cbManufacturingPage7 = LSILOGICSCSI_MANUFACTURING7_GET_SIZE(pThis->cPorts);
625	PMptConfigurationPageManufacturing7 pManufacturingPage7 = (PMptConfigurationPageManufacturing7)RTMemAllocZ(pPages->cbManufacturingPage7);
626	AssertPtrReturn(pManufacturingPage7, VERR_NO_MEMORY);
627	pPages->pManufacturingPage7 = pManufacturingPage7;
628
629	/* SAS I/O unit page 0 - Port specific information. */
630	pPages->cbSASIOUnitPage0 = LSILOGICSCSI_SASIOUNIT0_GET_SIZE(pThis->cPorts);
631	PMptConfigurationPageSASIOUnit0 pSASPage0 = (PMptConfigurationPageSASIOUnit0)RTMemAllocZ(pPages->cbSASIOUnitPage0);
632	AssertPtrReturn(pSASPage0, VERR_NO_MEMORY);
633	pPages->pSASIOUnitPage0 = pSASPage0;
634
635	/* SAS I/O unit page 1 - Port specific settings. */
636	pPages->cbSASIOUnitPage1 = LSILOGICSCSI_SASIOUNIT1_GET_SIZE(pThis->cPorts);
637	PMptConfigurationPageSASIOUnit1 pSASPage1 = (PMptConfigurationPageSASIOUnit1)RTMemAllocZ(pPages->cbSASIOUnitPage1);
638	AssertPtrReturn(pSASPage1, VERR_NO_MEMORY);
639	pPages->pSASIOUnitPage1 = pSASPage1;
640
641	pPages->cPHYs = pThis->cPorts;
642	pPages->paPHYs = (PMptPHY)RTMemAllocZ(pPages->cPHYs * sizeof(MptPHY));
643	AssertPtrReturn(pPages->paPHYs, VERR_NO_MEMORY);
644
645	/* Initialize the PHY configuration */
646	for (unsigned i = 0; i < pThis->cPorts; i++)
647	{
648	/* Settings for present devices. */
649	if (pThisCC->paDeviceStates[i].pDrvBase)
650	{
651	PMptSASDevice pSASDevice = (PMptSASDevice)RTMemAllocZ(sizeof(MptSASDevice));
652	AssertPtrReturn(pSASDevice, VERR_NO_MEMORY);
653
654	/* Link into device list. */
655	if (!pPages->cDevices)
656	{
657	pPages->pSASDeviceHead = pSASDevice;
658	pPages->pSASDeviceTail = pSASDevice;
659	pPages->cDevices = 1;
660	}
661	else
662	{
663	pSASDevice->pPrev = pPages->pSASDeviceTail;
664	pPages->pSASDeviceTail->pNext = pSASDevice;
665	pPages->pSASDeviceTail = pSASDevice;
666	pPages->cDevices++;
667	}
668	}
669	}
670	}
671
672	return VINF_SUCCESS;
673	}
674
675	/**
676	* Frees the configuration pages if allocated.
677	*
678	* @returns nothing.
679	* @param pThis Pointer to the shared LsiLogic device state.
680	* @param pThisCC Pointer to the ring-3 LsiLogic device state.
681	*/
682	static void lsilogicR3ConfigurationPagesFree(PLSILOGICSCSI pThis, PLSILOGICSCSICC pThisCC)
683	{
684
685	if (pThisCC->pConfigurationPages)
686	{
687	/* Destroy device list if we emulate a SAS controller. */
688	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
689	{
690	PMptConfigurationPagesSas pSasPages = &pThisCC->pConfigurationPages->u.SasPages;
691	PMptSASDevice pSASDeviceCurr = pSasPages->pSASDeviceHead;
692
693	while (pSASDeviceCurr)
694	{
695	PMptSASDevice pFree = pSASDeviceCurr;
696
697	pSASDeviceCurr = pSASDeviceCurr->pNext;
698	RTMemFree(pFree);
699	}
700	if (pSasPages->paPHYs)
701	RTMemFree(pSasPages->paPHYs);
702	if (pSasPages->pManufacturingPage7)
703	RTMemFree(pSasPages->pManufacturingPage7);
704	if (pSasPages->pSASIOUnitPage0)
705	RTMemFree(pSasPages->pSASIOUnitPage0);
706	if (pSasPages->pSASIOUnitPage1)
707	RTMemFree(pSasPages->pSASIOUnitPage1);
708
709	pSasPages->pSASDeviceHead = NULL;
710	pSasPages->paPHYs = NULL;
711	pSasPages->pManufacturingPage7 = NULL;
712	pSasPages->pSASIOUnitPage0 = NULL;
713	pSasPages->pSASIOUnitPage1 = NULL;
714	}
715
716	RTMemFree(pThisCC->pConfigurationPages);
717	pThisCC->pConfigurationPages = NULL;
718	}
719	}
720
721	/**
722	* Finishes a context reply.
723	*
724	* @returns nothing
725	* @param pDevIns The device instance.
726	* @param pThis Pointer to the shared LsiLogic device state.
727	* @param u32MessageContext The message context ID to post.
728	*/
729	static void lsilogicR3FinishContextReply(PPDMDEVINS pDevIns, PLSILOGICSCSI pThis, uint32_t u32MessageContext)
730	{
731	int rc;
732
733	LogFlowFunc(("pThis=%#p u32MessageContext=%#x\n", pThis, u32MessageContext));
734
735	AssertMsg(pThis->enmDoorbellState == LSILOGICDOORBELLSTATE_NOT_IN_USE, ("We are in a doorbell function\n"));
736
737	/* Write message context ID into reply post queue. */
738	rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->ReplyPostQueueCritSect, VINF_SUCCESS);
739	AssertRC(rc);
740
741	/* Check for a entry in the queue. */
742	if (!lsilogicReplyPostQueueGetFrameCount(pThis))
743	{
744	/* Set error code. */
745	lsilogicSetIOCFaultCode(pThis, LSILOGIC_IOCSTATUS_INSUFFICIENT_RESOURCES);
746	PDMDevHlpCritSectLeave(pDevIns, &pThis->ReplyPostQueueCritSect);
747	return;
748	}
749
750	/* We have a context reply. */
751	ASMAtomicWriteU32(&pThis->aReplyPostQueue[pThis->uReplyPostQueueNextEntryFreeWrite], u32MessageContext);
752	ASMAtomicIncU32(&pThis->uReplyPostQueueNextEntryFreeWrite);
753	pThis->uReplyPostQueueNextEntryFreeWrite %= pThis->cReplyQueueEntries;
754
755	/* Set interrupt. */
756	lsilogicSetInterrupt(pDevIns, pThis, LSILOGIC_REG_HOST_INTR_STATUS_REPLY_INTR);
757
758	PDMDevHlpCritSectLeave(pDevIns, &pThis->ReplyPostQueueCritSect);
759	}
760
761
762	/**
763	* Takes necessary steps to finish a reply frame.
764	*
765	* @returns nothing
766	* @param pDevIns The device instance.
767	* @param pThis Pointer to the shared LsiLogic device state.
768	* @param pReply Pointer to the reply message.
769	* @param fForceReplyFifo Flag whether the use of the reply post fifo is forced.
770	*/
771	static void lsilogicFinishAddressReply(PPDMDEVINS pDevIns, PLSILOGICSCSI pThis, PMptReplyUnion pReply, bool fForceReplyFifo)
772	{
773	/*
774	* If we are in a doorbell function we set the reply size now and
775	* set the system doorbell status interrupt to notify the guest that
776	* we are ready to send the reply.
777	*/
778	if (pThis->enmDoorbellState != LSILOGICDOORBELLSTATE_NOT_IN_USE && !fForceReplyFifo)
779	{
780	/* Set size of the reply in 16bit words. The size in the reply is in 32bit dwords. */
781	pThis->cReplySize = pReply->Header.u8MessageLength * 2;
782	Log(("%s: cReplySize=%u\n", __FUNCTION__, pThis->cReplySize));
783	pThis->uNextReplyEntryRead = 0;
784	lsilogicSetInterrupt(pDevIns, pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
785	}
786	else
787	{
788	/*
789	* The reply queues are only used if the request was fetched from the request queue.
790	* Requests from the request queue are always transferred to R3. So it is not possible
791	* that this case happens in R0 or GC.
792	*/
793	# ifdef IN_RING3
794	int rc;
795	/* Grab a free reply message from the queue. */
796	rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->ReplyFreeQueueCritSect, VINF_SUCCESS);
797	AssertRC(rc);
798
799	/* Check for a free reply frame. */
800	if (!lsilogicReplyFreeQueueGetFrameCount(pThis))
801	{
802	/* Set error code. */
803	lsilogicSetIOCFaultCode(pThis, LSILOGIC_IOCSTATUS_INSUFFICIENT_RESOURCES);
804	PDMDevHlpCritSectLeave(pDevIns, &pThis->ReplyFreeQueueCritSect);
805	return;
806	}
807
808	uint32_t u32ReplyFrameAddressLow = pThis->aReplyFreeQueue[pThis->uReplyFreeQueueNextAddressRead];
809
810	pThis->uReplyFreeQueueNextAddressRead++;
811	pThis->uReplyFreeQueueNextAddressRead %= pThis->cReplyQueueEntries;
812
813	PDMDevHlpCritSectLeave(pDevIns, &pThis->ReplyFreeQueueCritSect);
814
815	/* Build 64bit physical address. */
816	RTGCPHYS GCPhysReplyMessage = LSILOGIC_RTGCPHYS_FROM_U32(pThis->u32HostMFAHighAddr, u32ReplyFrameAddressLow);
817	size_t cbReplyCopied = (pThis->cbReplyFrame < sizeof(MptReplyUnion)) ? pThis->cbReplyFrame : sizeof(MptReplyUnion);
818
819	/* Write reply to guest memory. */
820	PDMDevHlpPCIPhysWriteMeta(pDevIns, GCPhysReplyMessage, pReply, cbReplyCopied);
821
822	/* Write low 32bits of reply frame into post reply queue. */
823	rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->ReplyPostQueueCritSect, VINF_SUCCESS);
824	AssertRC(rc);
825
826	/* Check for a entry in the queue. */
827	if (!lsilogicReplyPostQueueGetFrameCount(pThis))
828	{
829	/* Set error code. */
830	lsilogicSetIOCFaultCode(pThis, LSILOGIC_IOCSTATUS_INSUFFICIENT_RESOURCES);
831	PDMDevHlpCritSectLeave(pDevIns, &pThis->ReplyPostQueueCritSect);
832	return;
833	}
834
835	/* We have a address reply. Set the 31th bit to indicate that. */
836	ASMAtomicWriteU32(&pThis->aReplyPostQueue[pThis->uReplyPostQueueNextEntryFreeWrite],
837	RT_BIT(31) \| (u32ReplyFrameAddressLow >> 1));
838	ASMAtomicIncU32(&pThis->uReplyPostQueueNextEntryFreeWrite);
839	pThis->uReplyPostQueueNextEntryFreeWrite %= pThis->cReplyQueueEntries;
840
841	if (fForceReplyFifo)
842	{
843	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_NOT_IN_USE;
844	lsilogicSetInterrupt(pDevIns, pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
845	}
846
847	/* Set interrupt. */
848	lsilogicSetInterrupt(pDevIns, pThis, LSILOGIC_REG_HOST_INTR_STATUS_REPLY_INTR);
849
850	PDMDevHlpCritSectLeave(pDevIns, &pThis->ReplyPostQueueCritSect);
851	# else
852	AssertMsgFailed(("This is not allowed to happen.\n"));
853	# endif
854	}
855	}
856
857
858	/**
859	* Tries to find a memory region which covers the given address.
860	*
861	* @returns Pointer to memory region or NULL if not found.
862	* @param pThisCC Pointer to the ring-3 LsiLogic device state.
863	* @param u32Addr The 32bit address to search for.
864	*/
865	static PLSILOGICMEMREGN lsilogicR3MemRegionFindByAddr(PLSILOGICSCSICC pThisCC, uint32_t u32Addr)
866	{
867	PLSILOGICMEMREGN pRegion = NULL;
868
869	PLSILOGICMEMREGN pIt;
870	RTListForEach(&pThisCC->ListMemRegns, pIt, LSILOGICMEMREGN, NodeList)
871	{
872	if ( u32Addr >= pIt->u32AddrStart
873	&& u32Addr <= pIt->u32AddrEnd)
874	{
875	pRegion = pIt;
876	break;
877	}
878	}
879
880	return pRegion;
881	}
882
883	/**
884	* Frees all allocated memory regions.
885	*
886	* @returns nothing.
887	* @param pThisCC Pointer to the ring-3 LsiLogic device state.
888	*/
889	static void lsilogicR3MemRegionsFree(PLSILOGICSCSICC pThisCC)
890	{
891	PLSILOGICMEMREGN pItNext;
892
893	PLSILOGICMEMREGN pIt;
894	RTListForEachSafe(&pThisCC->ListMemRegns, pIt, pItNext, LSILOGICMEMREGN, NodeList)
895	{
896	RTListNodeRemove(&pIt->NodeList);
897	RTMemFree(pIt);
898	}
899	pThisCC->cbMemRegns = 0;
900	}
901
902	/**
903	* Inserts a given memory region into the list.
904	*
905	* @returns nothing.
906	* @param pThisCC Pointer to the ring-3 LsiLogic device state.
907	* @param pRegion The region to insert.
908	*/
909	static void lsilogicR3MemRegionInsert(PLSILOGICSCSICC pThisCC, PLSILOGICMEMREGN pRegion)
910	{
911	bool fInserted = false;
912
913	/* Insert at the right position. */
914	PLSILOGICMEMREGN pIt;
915	RTListForEach(&pThisCC->ListMemRegns, pIt, LSILOGICMEMREGN, NodeList)
916	{
917	if (pRegion->u32AddrEnd < pIt->u32AddrStart)
918	{
919	RTListNodeInsertBefore(&pIt->NodeList, &pRegion->NodeList);
920	fInserted = true;
921	break;
922	}
923	}
924	if (!fInserted)
925	RTListAppend(&pThisCC->ListMemRegns, &pRegion->NodeList);
926	}
927
928	/**
929	* Count number of memory regions.
930	*
931	* @returns Number of memory regions.
932	* @param pThisCC Pointer to the ring-3 LsiLogic device state.
933	*/
934	static uint32_t lsilogicR3MemRegionsCount(PLSILOGICSCSICC pThisCC)
935	{
936	uint32_t cRegions = 0;
937
938	PLSILOGICMEMREGN pIt;
939	RTListForEach(&pThisCC->ListMemRegns, pIt, LSILOGICMEMREGN, NodeList)
940	{
941	cRegions++;
942	}
943
944	return cRegions;
945	}
946
947	/**
948	* Handles a write to the diagnostic data register.
949	*
950	* @returns nothing.
951	* @param pThis Pointer to the shared LsiLogic device state.
952	* @param pThisCC Pointer to the ring-3 LsiLogic device state.
953	* @param u32Data Data to write.
954	*/
955	static void lsilogicR3DiagRegDataWrite(PLSILOGICSCSI pThis, PLSILOGICSCSICC pThisCC, uint32_t u32Data)
956	{
957	RTCritSectEnter(&pThisCC->CritSectMemRegns);
958
959	PLSILOGICMEMREGN pRegion = lsilogicR3MemRegionFindByAddr(pThisCC, pThis->u32DiagMemAddr);
960	if (pRegion)
961	{
962	uint32_t offRegion = pThis->u32DiagMemAddr - pRegion->u32AddrStart;
963
964	AssertMsg( offRegion % 4 == 0
965	&& pThis->u32DiagMemAddr <= pRegion->u32AddrEnd,
966	("Region offset not on a word boundary or crosses memory region\n"));
967
968	offRegion /= 4;
969	pRegion->au32Data[offRegion] = u32Data;
970	}
971	else
972	{
973	pRegion = NULL;
974
975	/* Create new region, first check whether we can extend another region. */
976	PLSILOGICMEMREGN pIt;
977	RTListForEach(&pThisCC->ListMemRegns, pIt, LSILOGICMEMREGN, NodeList)
978	{
979	if (pThis->u32DiagMemAddr == pIt->u32AddrEnd + sizeof(uint32_t))
980	{
981	pRegion = pIt;
982	break;
983	}
984	}
985
986	if (pRegion)
987	{
988	/* Reallocate. */
989	RTListNodeRemove(&pRegion->NodeList);
990
991	uint32_t cRegionSizeOld = (pRegion->u32AddrEnd - pRegion->u32AddrStart) / 4 + 1;
992	uint32_t cRegionSizeNew = cRegionSizeOld + 512;
993
994	if (pThisCC->cbMemRegns + 512 * sizeof(uint32_t) < LSILOGIC_MEMORY_REGIONS_MAX)
995	{
996	PLSILOGICMEMREGN pRegionNew;
997	pRegionNew = (PLSILOGICMEMREGN)RTMemRealloc(pRegion, RT_UOFFSETOF_DYN(LSILOGICMEMREGN, au32Data[cRegionSizeNew]));
998	if (pRegionNew)
999	{
1000	pRegion = pRegionNew;
1001	memset(&pRegion->au32Data[cRegionSizeOld], 0, 512 * sizeof(uint32_t));
1002	pRegion->au32Data[cRegionSizeOld] = u32Data;
1003	pRegion->u32AddrEnd = pRegion->u32AddrStart + (cRegionSizeNew - 1) * sizeof(uint32_t);
1004	pThisCC->cbMemRegns += 512 * sizeof(uint32_t);
1005	}
1006	/* else: Silently fail, there is nothing we can do here and the guest might work nevertheless. */
1007
1008	lsilogicR3MemRegionInsert(pThisCC, pRegion);
1009	}
1010	}
1011	else
1012	{
1013	if (pThisCC->cbMemRegns + 512 * sizeof(uint32_t) < LSILOGIC_MEMORY_REGIONS_MAX)
1014	{
1015	/* Create completely new. */
1016	pRegion = (PLSILOGICMEMREGN)RTMemAllocZ(RT_OFFSETOF(LSILOGICMEMREGN, au32Data[512]));
1017	if (pRegion)
1018	{
1019	pRegion->u32AddrStart = pThis->u32DiagMemAddr;
1020	pRegion->u32AddrEnd = pRegion->u32AddrStart + (512 - 1) * sizeof(uint32_t);
1021	pRegion->au32Data[0] = u32Data;
1022	pThisCC->cbMemRegns += 512 * sizeof(uint32_t);
1023
1024	lsilogicR3MemRegionInsert(pThisCC, pRegion);
1025	}
1026	/* else: Silently fail, there is nothing we can do here and the guest might work nevertheless. */
1027	}
1028	}
1029
1030	}
1031
1032	/* Memory access is always 32bit big. */
1033	pThis->u32DiagMemAddr += sizeof(uint32_t);
1034	RTCritSectLeave(&pThisCC->CritSectMemRegns);
1035	}
1036
1037	/**
1038	* Handles a read from the diagnostic data register.
1039	*
1040	* @returns nothing.
1041	* @param pThis Pointer to the shared LsiLogic device state.
1042	* @param pThisCC Pointer to the ring-3 LsiLogic device state.
1043	* @param pu32Data Where to store the data.
1044	*/
1045	static void lsilogicR3DiagRegDataRead(PLSILOGICSCSI pThis, PLSILOGICSCSICC pThisCC, uint32_t *pu32Data)
1046	{
1047	RTCritSectEnter(&pThisCC->CritSectMemRegns);
1048
1049	PLSILOGICMEMREGN pRegion = lsilogicR3MemRegionFindByAddr(pThisCC, pThis->u32DiagMemAddr);
1050	if (pRegion)
1051	{
1052	uint32_t offRegion = pThis->u32DiagMemAddr - pRegion->u32AddrStart;
1053
1054	AssertMsg( offRegion % 4 == 0
1055	&& pThis->u32DiagMemAddr <= pRegion->u32AddrEnd,
1056	("Region offset not on a word boundary or crosses memory region\n"));
1057
1058	offRegion /= 4;
1059	*pu32Data = pRegion->au32Data[offRegion];
1060	}
1061	else /* No region, default value 0. */
1062	*pu32Data = 0;
1063
1064	/* Memory access is always 32bit big. */
1065	pThis->u32DiagMemAddr += sizeof(uint32_t);
1066	RTCritSectLeave(&pThisCC->CritSectMemRegns);
1067	}
1068
1069	/**
1070	* Handles a write to the diagnostic memory address register.
1071	*
1072	* @returns nothing.
1073	* @param pThis Pointer to the shared LsiLogic device state.
1074	* @param u32Addr Address to write.
1075	*/
1076	static void lsilogicR3DiagRegAddressWrite(PLSILOGICSCSI pThis, uint32_t u32Addr)
1077	{
1078	pThis->u32DiagMemAddr = u32Addr & ~UINT32_C(0x3); /* 32bit alignment. */
1079	}
1080
1081	/**
1082	* Handles a read from the diagnostic memory address register.
1083	*
1084	* @returns nothing.
1085	* @param pThis Pointer to the shared LsiLogic device state.
1086	* @param pu32Addr Where to store the current address.
1087	*/
1088	static void lsilogicR3DiagRegAddressRead(PLSILOGICSCSI pThis, uint32_t *pu32Addr)
1089	{
1090	*pu32Addr = pThis->u32DiagMemAddr;
1091	}
1092
1093	/**
1094	* Processes a given Request from the guest
1095	*
1096	* @returns VBox status code.
1097	* @param pDevIns The device instance.
1098	* @param pThis Pointer to the shared LsiLogic device state.
1099	* @param pThisCC Pointer to the ring-3 LsiLogic device state.
1100	* @param pMessageHdr Pointer to the message header of the request.
1101	* @param pReply Pointer to the reply.
1102	*/
1103	static int lsilogicR3ProcessMessageRequest(PPDMDEVINS pDevIns, PLSILOGICSCSI pThis, PLSILOGICSCSICC pThisCC,
1104	PMptMessageHdr pMessageHdr, PMptReplyUnion pReply)
1105	{
1106	int rc = VINF_SUCCESS;
1107	bool fForceReplyPostFifo = false;
1108
1109	# ifdef LOG_ENABLED
1110	if (pMessageHdr->u8Function < RT_ELEMENTS(g_apszMPTFunctionNames))
1111	Log(("Message request function: %s\n", g_apszMPTFunctionNames[pMessageHdr->u8Function]));
1112	else
1113	Log(("Message request function: <unknown>\n"));
1114	# endif
1115
1116	memset(pReply, 0, sizeof(MptReplyUnion));
1117
1118	switch (pMessageHdr->u8Function)
1119	{
1120	case MPT_MESSAGE_HDR_FUNCTION_SCSI_TASK_MGMT:
1121	{
1122	PMptSCSITaskManagementRequest pTaskMgmtReq = (PMptSCSITaskManagementRequest)pMessageHdr;
1123
1124	LogFlow(("u8TaskType=%u\n", pTaskMgmtReq->u8TaskType));
1125	LogFlow(("u32TaskMessageContext=%#x\n", pTaskMgmtReq->u32TaskMessageContext));
1126
1127	pReply->SCSITaskManagement.u8MessageLength = 6; /* 6 32bit dwords. */
1128	pReply->SCSITaskManagement.u8TaskType = pTaskMgmtReq->u8TaskType;
1129	pReply->SCSITaskManagement.u32TerminationCount = 0;
1130	fForceReplyPostFifo = true;
1131	break;
1132	}
1133	case MPT_MESSAGE_HDR_FUNCTION_IOC_INIT:
1134	{
1135	/*
1136	* This request sets the I/O controller to the
1137	* operational state.
1138	*/
1139	PMptIOCInitRequest pIOCInitReq = (PMptIOCInitRequest)pMessageHdr;
1140
1141	/* Update configuration values. */
1142	pThis->enmWhoInit = (LSILOGICWHOINIT)pIOCInitReq->u8WhoInit;
1143	pThis->cbReplyFrame = pIOCInitReq->u16ReplyFrameSize;
1144	pThis->cMaxBuses = pIOCInitReq->u8MaxBuses;
1145	pThis->cMaxDevices = pIOCInitReq->u8MaxDevices;
1146	pThis->u32HostMFAHighAddr = pIOCInitReq->u32HostMfaHighAddr;
1147	pThis->u32SenseBufferHighAddr = pIOCInitReq->u32SenseBufferHighAddr;
1148
1149	if (pThis->enmState == LSILOGICSTATE_READY)
1150	{
1151	pThis->enmState = LSILOGICSTATE_OPERATIONAL;
1152	}
1153
1154	/* Return reply. */
1155	pReply->IOCInit.u8MessageLength = 5;
1156	pReply->IOCInit.u8WhoInit = pThis->enmWhoInit;
1157	pReply->IOCInit.u8MaxDevices = pThis->cMaxDevices;
1158	pReply->IOCInit.u8MaxBuses = pThis->cMaxBuses;
1159	break;
1160	}
1161	case MPT_MESSAGE_HDR_FUNCTION_IOC_FACTS:
1162	{
1163	pReply->IOCFacts.u8MessageLength = 15; /* 15 32bit dwords. */
1164
1165	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
1166	{
1167	pReply->IOCFacts.u16MessageVersion = 0x0102; /* Version from the specification. */
1168	pReply->IOCFacts.u8NumberOfPorts = pThis->cPorts;
1169	}
1170	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
1171	{
1172	pReply->IOCFacts.u16MessageVersion = 0x0105; /* Version from the specification. */
1173	pReply->IOCFacts.u8NumberOfPorts = pThis->cPorts;
1174	}
1175	else
1176	AssertMsgFailed(("Invalid controller type %d\n", pThis->enmCtrlType));
1177
1178	pReply->IOCFacts.u8IOCNumber = 0; /* PCI function number. */
1179	pReply->IOCFacts.u16IOCExceptions = 0;
1180	pReply->IOCFacts.u8MaxChainDepth = LSILOGICSCSI_MAXIMUM_CHAIN_DEPTH;
1181	pReply->IOCFacts.u8WhoInit = pThis->enmWhoInit;
1182	pReply->IOCFacts.u8BlockSize = 12; /* Block size in 32bit dwords. This is the largest request we can get (SCSI I/O). */
1183	pReply->IOCFacts.u8Flags = 0; /* Bit 0 is set if the guest must upload the FW prior to using the controller. Obviously not needed here. */
1184	pReply->IOCFacts.u16ReplyQueueDepth = pThis->cReplyQueueEntries - 1; /* One entry is always free. */
1185	pReply->IOCFacts.u16RequestFrameSize = 128; /** @todo Figure out where it is needed. */
1186	pReply->IOCFacts.u32CurrentHostMFAHighAddr = pThis->u32HostMFAHighAddr;
1187	pReply->IOCFacts.u16GlobalCredits = pThis->cRequestQueueEntries - 1; /* One entry is always free. */
1188
1189	pReply->IOCFacts.u8EventState = 0; /* Event notifications not enabled. */
1190	pReply->IOCFacts.u32CurrentSenseBufferHighAddr = pThis->u32SenseBufferHighAddr;
1191	pReply->IOCFacts.u16CurReplyFrameSize = pThis->cbReplyFrame;
1192	pReply->IOCFacts.u8MaxDevices = pThis->cMaxDevices;
1193	pReply->IOCFacts.u8MaxBuses = pThis->cMaxBuses;
1194
1195	pReply->IOCFacts.u16ProductID = 0xcafe; /* Our own product ID :) */
1196	pReply->IOCFacts.u32FwImageSize = 0; /* No image needed. */
1197	pReply->IOCFacts.u32FWVersion = 0;
1198
1199	/* Check for a valid firmware image in the IOC memory which was downloaded by the guest earlier and use that. */
1200	RTCritSectEnter(&pThisCC->CritSectMemRegns);
1201	PLSILOGICMEMREGN pRegion = lsilogicR3MemRegionFindByAddr(pThisCC, LSILOGIC_FWIMGHDR_LOAD_ADDRESS);
1202	if (pRegion)
1203	{
1204	uint32_t offImgHdr = (LSILOGIC_FWIMGHDR_LOAD_ADDRESS - pRegion->u32AddrStart);
1205	if (pRegion->u32AddrEnd - offImgHdr + 1 >= sizeof(FwImageHdr)) /* End address is inclusive. */
1206	{
1207	PFwImageHdr pFwImgHdr = (PFwImageHdr)&pRegion->au32Data[offImgHdr / 4];
1208
1209	/* Check for the signature. */
1210	/** @todo Checksum validation. */
1211	if ( pFwImgHdr->u32Signature1 == LSILOGIC_FWIMGHDR_SIGNATURE1
1212	&& pFwImgHdr->u32Signature2 == LSILOGIC_FWIMGHDR_SIGNATURE2
1213	&& pFwImgHdr->u32Signature3 == LSILOGIC_FWIMGHDR_SIGNATURE3)
1214	{
1215	LogFlowFunc(("IOC Facts: Found valid firmware image header in memory, using version (%#x), size (%d) and product ID (%#x) from there\n",
1216	pFwImgHdr->u32FwVersion, pFwImgHdr->u32ImageSize, pFwImgHdr->u16ProductId));
1217
1218	pReply->IOCFacts.u16ProductID = pFwImgHdr->u16ProductId;
1219	pReply->IOCFacts.u32FwImageSize = pFwImgHdr->u32ImageSize;
1220	pReply->IOCFacts.u32FWVersion = pFwImgHdr->u32FwVersion;
1221	}
1222	}
1223	}
1224	RTCritSectLeave(&pThisCC->CritSectMemRegns);
1225	break;
1226	}
1227	case MPT_MESSAGE_HDR_FUNCTION_PORT_FACTS:
1228	{
1229	PMptPortFactsRequest pPortFactsReq = (PMptPortFactsRequest)pMessageHdr;
1230
1231	pReply->PortFacts.u8MessageLength = 10;
1232	pReply->PortFacts.u8PortNumber = pPortFactsReq->u8PortNumber;
1233
1234	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
1235	{
1236	/* This controller only supports one bus with bus number 0. */
1237	if (pPortFactsReq->u8PortNumber >= pThis->cPorts)
1238	{
1239	pReply->PortFacts.u8PortType = 0; /* Not existant. */
1240	}
1241	else
1242	{
1243	pReply->PortFacts.u8PortType = 0x01; /* SCSI Port. */
1244	pReply->PortFacts.u16MaxDevices = LSILOGICSCSI_PCI_SPI_DEVICES_PER_BUS_MAX;
1245	pReply->PortFacts.u16ProtocolFlags = RT_BIT(3) \| RT_BIT(0); /* SCSI initiator and LUN supported. */
1246	pReply->PortFacts.u16PortSCSIID = 7; /* Default */
1247	pReply->PortFacts.u16MaxPersistentIDs = 0;
1248	pReply->PortFacts.u16MaxPostedCmdBuffers = 0; /* Only applies for target mode which we dont support. */
1249	pReply->PortFacts.u16MaxLANBuckets = 0; /* Only for the LAN controller. */
1250	}
1251	}
1252	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
1253	{
1254	if (pPortFactsReq->u8PortNumber >= pThis->cPorts)
1255	{
1256	pReply->PortFacts.u8PortType = 0; /* Not existant. */
1257	}
1258	else
1259	{
1260	pReply->PortFacts.u8PortType = 0x30; /* SAS Port. */
1261	pReply->PortFacts.u16MaxDevices = pThis->cPorts;
1262	pReply->PortFacts.u16ProtocolFlags = RT_BIT(3) \| RT_BIT(0); /* SCSI initiator and LUN supported. */
1263	pReply->PortFacts.u16PortSCSIID = pThis->cPorts;
1264	pReply->PortFacts.u16MaxPersistentIDs = 0;
1265	pReply->PortFacts.u16MaxPostedCmdBuffers = 0; /* Only applies for target mode which we dont support. */
1266	pReply->PortFacts.u16MaxLANBuckets = 0; /* Only for the LAN controller. */
1267	}
1268	}
1269	else
1270	AssertMsgFailed(("Invalid controller type %d\n", pThis->enmCtrlType));
1271	break;
1272	}
1273	case MPT_MESSAGE_HDR_FUNCTION_PORT_ENABLE:
1274	{
1275	/*
1276	* The port enable request notifies the IOC to make the port available and perform
1277	* appropriate discovery on the associated link.
1278	*/
1279	PMptPortEnableRequest pPortEnableReq = (PMptPortEnableRequest)pMessageHdr;
1280
1281	pReply->PortEnable.u8MessageLength = 5;
1282	pReply->PortEnable.u8PortNumber = pPortEnableReq->u8PortNumber;
1283	break;
1284	}
1285	case MPT_MESSAGE_HDR_FUNCTION_EVENT_NOTIFICATION:
1286	{
1287	PMptEventNotificationRequest pEventNotificationReq = (PMptEventNotificationRequest)pMessageHdr;
1288
1289	if (pEventNotificationReq->u8Switch)
1290	pThis->fEventNotificationEnabled = true;
1291	else
1292	pThis->fEventNotificationEnabled = false;
1293
1294	pReply->EventNotification.u16EventDataLength = 1; /* 1 32bit D-Word. */
1295	pReply->EventNotification.u8MessageLength = 8;
1296	pReply->EventNotification.u8MessageFlags = (1 << 7);
1297	pReply->EventNotification.u8AckRequired = 0;
1298	pReply->EventNotification.u32Event = MPT_EVENT_EVENT_CHANGE;
1299	pReply->EventNotification.u32EventContext = 0;
1300	pReply->EventNotification.u32EventData = pThis->fEventNotificationEnabled ? 1 : 0;
1301
1302	break;
1303	}
1304	case MPT_MESSAGE_HDR_FUNCTION_EVENT_ACK:
1305	{
1306	AssertMsgFailed(("todo"));
1307	break;
1308	}
1309	case MPT_MESSAGE_HDR_FUNCTION_CONFIG:
1310	{
1311	PMptConfigurationRequest pConfigurationReq = (PMptConfigurationRequest)pMessageHdr;
1312
1313	rc = lsilogicR3ProcessConfigurationRequest(pDevIns, pThis, pThisCC, pConfigurationReq, &pReply->Configuration);
1314	AssertRC(rc);
1315	break;
1316	}
1317	case MPT_MESSAGE_HDR_FUNCTION_FW_UPLOAD:
1318	{
1319	PMptFWUploadRequest pFWUploadReq = (PMptFWUploadRequest)pMessageHdr;
1320
1321	pReply->FWUpload.u8ImageType = pFWUploadReq->u8ImageType;
1322	pReply->FWUpload.u8MessageLength = 6;
1323	pReply->FWUpload.u32ActualImageSize = 0;
1324	break;
1325	}
1326	case MPT_MESSAGE_HDR_FUNCTION_FW_DOWNLOAD:
1327	{
1328	//PMptFWDownloadRequest pFWDownloadReq = (PMptFWDownloadRequest)pMessageHdr;
1329
1330	pReply->FWDownload.u8MessageLength = 5;
1331	LogFlowFunc(("FW Download request issued\n"));
1332	break;
1333	}
1334	case MPT_MESSAGE_HDR_FUNCTION_SCSI_IO_REQUEST: /* Should be handled already. */
1335	default:
1336	AssertMsgFailed(("Invalid request function %#x\n", pMessageHdr->u8Function));
1337	}
1338
1339	/* Copy common bits from request message frame to reply. */
1340	pReply->Header.u8Function = pMessageHdr->u8Function;
1341	pReply->Header.u32MessageContext = pMessageHdr->u32MessageContext;
1342
1343	lsilogicFinishAddressReply(pDevIns, pThis, pReply, fForceReplyPostFifo);
1344	return rc;
1345	}
1346
1347	#endif /* IN_RING3 */
1348
1349	/**
1350	* Writes a value to a register at a given offset.
1351	*
1352	* @returns Strict VBox status code.
1353	* @param pDevIns The devie instance.
1354	* @param pThis Pointer to the shared LsiLogic device state.
1355	* @param offReg Offset of the register to write.
1356	* @param u32 The value being written.
1357	*/
1358	static VBOXSTRICTRC lsilogicRegisterWrite(PPDMDEVINS pDevIns, PLSILOGICSCSI pThis, uint32_t offReg, uint32_t u32)
1359	{
1360	LogFlowFunc(("pThis=%#p offReg=%#x u32=%#x\n", pThis, offReg, u32));
1361	switch (offReg)
1362	{
1363	case LSILOGIC_REG_REPLY_QUEUE:
1364	{
1365	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->ReplyFreeQueueWriteCritSect, VINF_IOM_R3_MMIO_WRITE);
1366	if (rc != VINF_SUCCESS)
1367	return rc;
1368	/* Add the entry to the reply free queue. */
1369	ASMAtomicWriteU32(&pThis->aReplyFreeQueue[pThis->uReplyFreeQueueNextEntryFreeWrite], u32);
1370	pThis->uReplyFreeQueueNextEntryFreeWrite++;
1371	pThis->uReplyFreeQueueNextEntryFreeWrite %= pThis->cReplyQueueEntries;
1372	PDMDevHlpCritSectLeave(pDevIns, &pThis->ReplyFreeQueueWriteCritSect);
1373	break;
1374	}
1375	case LSILOGIC_REG_REQUEST_QUEUE:
1376	{
1377	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->RequestQueueCritSect, VINF_IOM_R3_MMIO_WRITE);
1378	if (rc != VINF_SUCCESS)
1379	return rc;
1380
1381	uint32_t uNextWrite = ASMAtomicReadU32(&pThis->uRequestQueueNextEntryFreeWrite);
1382
1383	ASMAtomicWriteU32(&pThis->aRequestQueue[uNextWrite], u32);
1384
1385	/*
1386	* Don't update the value in place. It can happen that we get preempted
1387	* after the increment but before the modulo.
1388	* Another EMT will read the wrong value when processing the queues
1389	* and hang in an endless loop creating thousands of requests.
1390	*/
1391	uNextWrite++;
1392	uNextWrite %= pThis->cRequestQueueEntries;
1393	ASMAtomicWriteU32(&pThis->uRequestQueueNextEntryFreeWrite, uNextWrite);
1394	PDMDevHlpCritSectLeave(pDevIns, &pThis->RequestQueueCritSect);
1395
1396	/* Send notification to R3 if there is not one sent already. Do this
1397	* only if the worker thread is not sleeping or might go sleeping. */
1398	if (!ASMAtomicXchgBool(&pThis->fNotificationSent, true))
1399	{
1400	if (ASMAtomicReadBool(&pThis->fWrkThreadSleeping))
1401	{
1402	LogFlowFunc(("Signal event semaphore\n"));
1403	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtProcess);
1404	AssertRC(rc);
1405	}
1406	}
1407	break;
1408	}
1409	case LSILOGIC_REG_DOORBELL:
1410	{
1411	/*
1412	* When the guest writes to this register a real device would set the
1413	* doorbell status bit in the interrupt status register to indicate that the IOP
1414	* has still to process the message.
1415	* The guest needs to wait with posting new messages here until the bit is cleared.
1416	* Because the guest is not continuing execution while we are here we can skip this.
1417	*/
1418	if (pThis->enmDoorbellState == LSILOGICDOORBELLSTATE_NOT_IN_USE)
1419	{
1420	uint32_t uFunction = LSILOGIC_REG_DOORBELL_GET_FUNCTION(u32);
1421
1422	switch (uFunction)
1423	{
1424	case LSILOGIC_DOORBELL_FUNCTION_IO_UNIT_RESET:
1425	case LSILOGIC_DOORBELL_FUNCTION_IOC_MSG_UNIT_RESET:
1426	{
1427	/*
1428	* The I/O unit reset does much more on real hardware like
1429	* reloading the firmware, nothing we need to do here,
1430	* so this is like the IOC message unit reset.
1431	*/
1432	pThis->enmState = LSILOGICSTATE_RESET;
1433
1434	/* Reset interrupt status. */
1435	pThis->uInterruptStatus = 0;
1436	lsilogicUpdateInterrupt(pDevIns, pThis);
1437
1438	/* Reset the queues. */
1439	pThis->uReplyFreeQueueNextEntryFreeWrite = 0;
1440	pThis->uReplyFreeQueueNextAddressRead = 0;
1441	pThis->uReplyPostQueueNextEntryFreeWrite = 0;
1442	pThis->uReplyPostQueueNextAddressRead = 0;
1443	pThis->uRequestQueueNextEntryFreeWrite = 0;
1444	pThis->uRequestQueueNextAddressRead = 0;
1445
1446	/* Only the IOC message unit reset transisionts to the ready state. */
1447	if (uFunction == LSILOGIC_DOORBELL_FUNCTION_IOC_MSG_UNIT_RESET)
1448	pThis->enmState = LSILOGICSTATE_READY;
1449	break;
1450	}
1451	case LSILOGIC_DOORBELL_FUNCTION_HANDSHAKE:
1452	{
1453	pThis->cMessage = LSILOGIC_REG_DOORBELL_GET_SIZE(u32);
1454	pThis->iMessage = 0;
1455
1456	/* This is not supposed to happen and the result is undefined, just stay in the current state. */
1457	AssertMsgReturn(pThis->cMessage <= RT_ELEMENTS(pThis->aMessage),
1458	("Message doesn't fit into the buffer, cMessage=%u", pThis->cMessage),
1459	VINF_SUCCESS);
1460
1461	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_FN_HANDSHAKE;
1462	/* Update the interrupt status to notify the guest that a doorbell function was started. */
1463	lsilogicSetInterrupt(pDevIns, pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1464	break;
1465	}
1466	case LSILOGIC_DOORBELL_FUNCTION_REPLY_FRAME_REMOVAL:
1467	{
1468	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_RFR_FRAME_COUNT_LOW;
1469	/* Update the interrupt status to notify the guest that a doorbell function was started. */
1470	lsilogicSetInterrupt(pDevIns, pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1471	break;
1472	}
1473	default:
1474	AssertMsgFailed(("Unknown function %u to perform\n", uFunction));
1475	}
1476	}
1477	else if (pThis->enmDoorbellState == LSILOGICDOORBELLSTATE_FN_HANDSHAKE)
1478	{
1479	/*
1480	* We are already performing a doorbell function.
1481	* Get the remaining parameters, ignore any excess writes.
1482	*/
1483	AssertMsgReturn(pThis->iMessage < pThis->cMessage,
1484	("Guest is trying to write more than was indicated in the handshake\n"),
1485	VINF_SUCCESS);
1486
1487	/*
1488	* If the last byte of the message is written, force a switch to R3 because some requests might force
1489	* a reply through the FIFO which cannot be handled in GC or R0.
1490	*/
1491	#ifndef IN_RING3
1492	if (pThis->iMessage == pThis->cMessage - 1)
1493	return VINF_IOM_R3_MMIO_WRITE;
1494	#endif
1495	pThis->aMessage[pThis->iMessage++] = u32;
1496	#ifdef IN_RING3
1497	if (pThis->iMessage == pThis->cMessage)
1498	{
1499	int rc = lsilogicR3ProcessMessageRequest(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PLSILOGICSCSICC),
1500	(PMptMessageHdr)pThis->aMessage, &pThis->ReplyBuffer);
1501	AssertRC(rc);
1502	}
1503	#endif
1504	}
1505	break;
1506	}
1507	case LSILOGIC_REG_HOST_INTR_STATUS:
1508	{
1509	/*
1510	* Clear the bits the guest wants except the system doorbell interrupt and the IO controller
1511	* status bit.
1512	* The former bit is always cleared no matter what the guest writes to the register and
1513	* the latter one is read only.
1514	*/
1515	ASMAtomicAndU32(&pThis->uInterruptStatus, ~LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1516
1517	/*
1518	* Check if there is still a doorbell function in progress. Set the
1519	* system doorbell interrupt bit again if it is.
1520	* We do not use lsilogicSetInterrupt here because the interrupt status
1521	* is updated afterwards anyway.
1522	*/
1523	if ( (pThis->enmDoorbellState == LSILOGICDOORBELLSTATE_FN_HANDSHAKE)
1524	&& (pThis->cMessage == pThis->iMessage))
1525	{
1526	if (pThis->uNextReplyEntryRead == pThis->cReplySize)
1527	{
1528	/* Reply finished. Reset doorbell in progress status. */
1529	Log(("%s: Doorbell function finished\n", __FUNCTION__));
1530	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_NOT_IN_USE;
1531	}
1532	ASMAtomicOrU32(&pThis->uInterruptStatus, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1533	}
1534	else if ( pThis->enmDoorbellState != LSILOGICDOORBELLSTATE_NOT_IN_USE
1535	&& pThis->enmDoorbellState != LSILOGICDOORBELLSTATE_FN_HANDSHAKE)
1536	{
1537	/* Reply frame removal, check whether the reply free queue is empty. */
1538	if ( pThis->uReplyFreeQueueNextAddressRead == pThis->uReplyFreeQueueNextEntryFreeWrite
1539	&& pThis->enmDoorbellState == LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_LOW)
1540	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_NOT_IN_USE;
1541	ASMAtomicOrU32(&pThis->uInterruptStatus, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1542	}
1543
1544	lsilogicUpdateInterrupt(pDevIns, pThis);
1545	break;
1546	}
1547	case LSILOGIC_REG_HOST_INTR_MASK:
1548	{
1549	ASMAtomicWriteU32(&pThis->uInterruptMask, u32 & LSILOGIC_REG_HOST_INTR_MASK_W_MASK);
1550	lsilogicUpdateInterrupt(pDevIns, pThis);
1551	break;
1552	}
1553	case LSILOGIC_REG_WRITE_SEQUENCE:
1554	{
1555	if (pThis->fDiagnosticEnabled)
1556	{
1557	/* Any value will cause a reset and disabling access. */
1558	pThis->fDiagnosticEnabled = false;
1559	pThis->iDiagnosticAccess = 0;
1560	pThis->fDiagRegsEnabled = false;
1561	}
1562	else if ((u32 & 0xf) == g_lsilogicDiagnosticAccess[pThis->iDiagnosticAccess])
1563	{
1564	pThis->iDiagnosticAccess++;
1565	if (pThis->iDiagnosticAccess == RT_ELEMENTS(g_lsilogicDiagnosticAccess))
1566	{
1567	/*
1568	* Key sequence successfully written. Enable access to diagnostic
1569	* memory and register.
1570	*/
1571	pThis->fDiagnosticEnabled = true;
1572	}
1573	}
1574	else
1575	{
1576	/* Wrong value written - reset to beginning. */
1577	pThis->iDiagnosticAccess = 0;
1578	}
1579	break;
1580	}
1581	case LSILOGIC_REG_HOST_DIAGNOSTIC:
1582	{
1583	if (pThis->fDiagnosticEnabled)
1584	{
1585	#ifndef IN_RING3
1586	return VINF_IOM_R3_MMIO_WRITE;
1587	#else
1588	if (u32 & LSILOGIC_REG_HOST_DIAGNOSTIC_RESET_ADAPTER)
1589	lsilogicR3HardReset(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PLSILOGICSCSICC));
1590	else if (u32 & LSILOGIC_REG_HOST_DIAGNOSTIC_DIAG_RW_ENABLE)
1591	pThis->fDiagRegsEnabled = true;
1592	#endif
1593	}
1594	break;
1595	}
1596	case LSILOGIC_REG_DIAG_RW_DATA:
1597	{
1598	if (pThis->fDiagRegsEnabled)
1599	{
1600	#ifndef IN_RING3
1601	return VINF_IOM_R3_MMIO_WRITE;
1602	#else
1603	lsilogicR3DiagRegDataWrite(pThis, PDMDEVINS_2_DATA_CC(pDevIns, PLSILOGICSCSICC), u32);
1604	#endif
1605	}
1606	break;
1607	}
1608	case LSILOGIC_REG_DIAG_RW_ADDRESS:
1609	{
1610	if (pThis->fDiagRegsEnabled)
1611	{
1612	#ifndef IN_RING3
1613	return VINF_IOM_R3_MMIO_WRITE;
1614	#else
1615	lsilogicR3DiagRegAddressWrite(pThis, u32);
1616	#endif
1617	}
1618	break;
1619	}
1620	default: /* Ignore. */
1621	{
1622	break;
1623	}
1624	}
1625	return VINF_SUCCESS;
1626	}
1627
1628	/**
1629	* Reads the content of a register at a given offset.
1630	*
1631	* @returns VBox status code.
1632	* @param pDevIns The device instance.
1633	* @param pThis Pointer to the shared LsiLogic device state.
1634	* @param offReg Offset of the register to read.
1635	* @param pu32 Where to store the content of the register.
1636	*/
1637	static VBOXSTRICTRC lsilogicRegisterRead(PPDMDEVINS pDevIns, PLSILOGICSCSI pThis, uint32_t offReg, uint32_t *pu32)
1638	{
1639	int rc = VINF_SUCCESS;
1640	uint32_t u32 = 0;
1641	Assert(!(offReg & 3));
1642
1643	/* Align to a 4 byte offset. */
1644	switch (offReg)
1645	{
1646	case LSILOGIC_REG_REPLY_QUEUE:
1647	{
1648	rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->ReplyPostQueueCritSect, VINF_IOM_R3_MMIO_READ);
1649	if (rc != VINF_SUCCESS)
1650	break;
1651
1652	uint32_t idxReplyPostQueueWrite = ASMAtomicUoReadU32(&pThis->uReplyPostQueueNextEntryFreeWrite);
1653	uint32_t idxReplyPostQueueRead = ASMAtomicUoReadU32(&pThis->uReplyPostQueueNextAddressRead);
1654
1655	if (idxReplyPostQueueWrite != idxReplyPostQueueRead)
1656	{
1657	u32 = pThis->aReplyPostQueue[idxReplyPostQueueRead];
1658	idxReplyPostQueueRead++;
1659	idxReplyPostQueueRead %= pThis->cReplyQueueEntries;
1660	ASMAtomicWriteU32(&pThis->uReplyPostQueueNextAddressRead, idxReplyPostQueueRead);
1661	}
1662	else
1663	{
1664	/* The reply post queue is empty. Reset interrupt. */
1665	u32 = UINT32_C(0xffffffff);
1666	lsilogicClearInterrupt(pDevIns, pThis, LSILOGIC_REG_HOST_INTR_STATUS_REPLY_INTR);
1667	}
1668	PDMDevHlpCritSectLeave(pDevIns, &pThis->ReplyPostQueueCritSect);
1669
1670	Log(("%s: Returning address %#x\n", __FUNCTION__, u32));
1671	break;
1672	}
1673	case LSILOGIC_REG_DOORBELL:
1674	{
1675	u32 = LSILOGIC_REG_DOORBELL_SET_STATE(pThis->enmState);
1676	u32 \|= LSILOGIC_REG_DOORBELL_SET_USED(pThis->enmDoorbellState);
1677	u32 \|= LSILOGIC_REG_DOORBELL_SET_WHOINIT(pThis->enmWhoInit);
1678	/*
1679	* If there is a doorbell function in progress we pass the return value
1680	* instead of the status code. We transfer 16bit of the reply
1681	* during one read.
1682	*/
1683	switch (pThis->enmDoorbellState)
1684	{
1685	case LSILOGICDOORBELLSTATE_NOT_IN_USE:
1686	/* We return the status code of the I/O controller. */
1687	u32 \|= pThis->u16IOCFaultCode;
1688	break;
1689	case LSILOGICDOORBELLSTATE_FN_HANDSHAKE:
1690	/* Return next 16bit value. */
1691	if (pThis->uNextReplyEntryRead < pThis->cReplySize)
1692	u32 \|= pThis->ReplyBuffer.au16Reply[pThis->uNextReplyEntryRead++];
1693	lsilogicSetInterrupt(pDevIns, pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1694	break;
1695	case LSILOGICDOORBELLSTATE_RFR_FRAME_COUNT_LOW:
1696	{
1697	uint32_t cReplyFrames = lsilogicReplyFreeQueueGetFrameCount(pThis);
1698
1699	u32 \|= cReplyFrames & UINT32_C(0xffff);
1700	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_RFR_FRAME_COUNT_HIGH;
1701	lsilogicSetInterrupt(pDevIns, pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1702	break;
1703	}
1704	case LSILOGICDOORBELLSTATE_RFR_FRAME_COUNT_HIGH:
1705	{
1706	uint32_t cReplyFrames = lsilogicReplyFreeQueueGetFrameCount(pThis);
1707
1708	u32 \|= cReplyFrames >> 16;
1709	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_LOW;
1710	lsilogicSetInterrupt(pDevIns, pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1711	break;
1712	}
1713	case LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_LOW:
1714	if (pThis->uReplyFreeQueueNextEntryFreeWrite != pThis->uReplyFreeQueueNextAddressRead)
1715	{
1716	u32 \|= pThis->aReplyFreeQueue[pThis->uReplyFreeQueueNextAddressRead] & UINT32_C(0xffff);
1717	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_HIGH;
1718	lsilogicSetInterrupt(pDevIns, pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1719	}
1720	break;
1721	case LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_HIGH:
1722	u32 \|= pThis->aReplyFreeQueue[pThis->uReplyFreeQueueNextAddressRead] >> 16;
1723	pThis->uReplyFreeQueueNextAddressRead++;
1724	pThis->uReplyFreeQueueNextAddressRead %= pThis->cReplyQueueEntries;
1725	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_LOW;
1726	lsilogicSetInterrupt(pDevIns, pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1727	break;
1728	default:
1729	AssertMsgFailed(("Invalid doorbell state %d\n", pThis->enmDoorbellState));
1730	}
1731
1732	break;
1733	}
1734	case LSILOGIC_REG_HOST_INTR_STATUS:
1735	{
1736	u32 = ASMAtomicReadU32(&pThis->uInterruptStatus);
1737	break;
1738	}
1739	case LSILOGIC_REG_HOST_INTR_MASK:
1740	{
1741	u32 = ASMAtomicReadU32(&pThis->uInterruptMask);
1742	break;
1743	}
1744	case LSILOGIC_REG_HOST_DIAGNOSTIC:
1745	{
1746	if (pThis->fDiagnosticEnabled)
1747	u32 \|= LSILOGIC_REG_HOST_DIAGNOSTIC_DRWE;
1748	if (pThis->fDiagRegsEnabled)
1749	u32 \|= LSILOGIC_REG_HOST_DIAGNOSTIC_DIAG_RW_ENABLE;
1750	break;
1751	}
1752	case LSILOGIC_REG_DIAG_RW_DATA:
1753	{
1754	if (pThis->fDiagRegsEnabled)
1755	{
1756	#ifndef IN_RING3
1757	return VINF_IOM_R3_MMIO_READ;
1758	#else
1759	lsilogicR3DiagRegDataRead(pThis, PDMDEVINS_2_DATA_CC(pDevIns, PLSILOGICSCSICC), &u32);
1760	#endif
1761	}
1762	}
1763	RT_FALL_THRU();
1764	case LSILOGIC_REG_DIAG_RW_ADDRESS:
1765	{
1766	if (pThis->fDiagRegsEnabled)
1767	{
1768	#ifndef IN_RING3
1769	return VINF_IOM_R3_MMIO_READ;
1770	#else
1771	lsilogicR3DiagRegAddressRead(pThis, &u32);
1772	#endif
1773	}
1774	}
1775	RT_FALL_THRU();
1776	case LSILOGIC_REG_TEST_BASE_ADDRESS: /* The spec doesn't say anything about these registers, so we just ignore them */
1777	default: /* Ignore. */
1778	{
1779	/** @todo LSILOGIC_REG_DIAG_* should return all F's when accessed by MMIO. We
1780	* return 0. Likely to apply to undefined offsets as well. */
1781	break;
1782	}
1783	}
1784
1785	*pu32 = u32;
1786	LogFlowFunc(("pThis=%#p offReg=%#x u32=%#x\n", pThis, offReg, u32));
1787	return rc;
1788	}
1789
1790	/**
1791	* @callback_method_impl{FNIOMIOPORTNEWOUT}
1792	*/
1793	static DECLCALLBACK(VBOXSTRICTRC)
1794	lsilogicIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1795	{
1796	PLSILOGICSCSI pThis = PDMDEVINS_2_DATA(pDevIns, PLSILOGICSCSI);
1797	VBOXSTRICTRC rcStrict;
1798	RT_NOREF2(pvUser, cb);
1799
1800	if (!(offPort & 3))
1801	{
1802	rcStrict = lsilogicRegisterWrite(pDevIns, pThis, offPort, u32);
1803	if (rcStrict == VINF_IOM_R3_MMIO_WRITE)
1804	rcStrict = VINF_IOM_R3_IOPORT_WRITE;
1805	}
1806	else
1807	{
1808	Log(("lsilogicIOPortWrite: Ignoring misaligned write - offPort=%#x u32=%#x cb=%#x\n", offPort, u32, cb));
1809	rcStrict = VINF_SUCCESS;
1810	}
1811
1812	return rcStrict;
1813	}
1814
1815	/**
1816	* @callback_method_impl{FNIOMIOPORTNEWIN}
1817	*/
1818	static DECLCALLBACK(VBOXSTRICTRC)
1819	lsilogicIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
1820	{
1821	PLSILOGICSCSI pThis = PDMDEVINS_2_DATA(pDevIns, PLSILOGICSCSI);
1822	RT_NOREF_PV(pvUser);
1823	RT_NOREF_PV(cb);
1824
1825	VBOXSTRICTRC rcStrict = lsilogicRegisterRead(pDevIns, pThis, offPort & ~(uint32_t)3, pu32);
1826	if (rcStrict == VINF_IOM_R3_MMIO_READ)
1827	rcStrict = VINF_IOM_R3_IOPORT_READ;
1828
1829	return rcStrict;
1830	}
1831
1832	/**
1833	* @callback_method_impl{FNIOMMMIONEWWRITE}
1834	*/
1835	static DECLCALLBACK(VBOXSTRICTRC) lsilogicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
1836	{
1837	PLSILOGICSCSI pThis = PDMDEVINS_2_DATA(pDevIns, PLSILOGICSCSI);
1838	uint32_t u32;
1839	RT_NOREF_PV(pvUser);
1840
1841	/* See comments in lsilogicR3Construct regarding size and alignment. */
1842	if (cb == 4)
1843	u32 = (uint32_t const )pv;
1844	else
1845	{
1846	if (cb > 4)
1847	u32 = (uint32_t const )pv;
1848	else if (cb >= 2)
1849	u32 = (uint16_t const )pv;
1850	else
1851	u32 = (uint8_t const )pv;
1852	Log(("lsilogicMMIOWrite: Non-DWORD write access - off=%#RGp u32=%#x cb=%#x\n", off, u32, cb));
1853	}
1854
1855	VBOXSTRICTRC rcStrict;
1856	if (!(off & 3))
1857	rcStrict = lsilogicRegisterWrite(pDevIns, pThis, (uint32_t)off, u32);
1858	else
1859	{
1860	Log(("lsilogicMMIOWrite: Ignoring misaligned write - off=%#RGp u32=%#x cb=%#x\n", off, u32, cb));
1861	rcStrict = VINF_SUCCESS;
1862	}
1863	return rcStrict;
1864	}
1865
1866	/**
1867	* @callback_method_impl{FNIOMMMIONEWREAD}
1868	*/
1869	static DECLCALLBACK(VBOXSTRICTRC) lsilogicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
1870	{
1871	PLSILOGICSCSI pThis = PDMDEVINS_2_DATA(pDevIns, PLSILOGICSCSI);
1872	Assert(!(off & 3)); Assert(cb == 4); /* If any of these trigger you've changed the registration flags or IOM is busted. */
1873	RT_NOREF2(pvUser, cb);
1874
1875	return lsilogicRegisterRead(pDevIns, pThis, off, (uint32_t *)pv);
1876	}
1877
1878	/**
1879	* @callback_method_impl{FNIOMMMIONEWWRITE}
1880	*/
1881	static DECLCALLBACK(VBOXSTRICTRC)
1882	lsilogicDiagnosticWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
1883	{
1884	RT_NOREF(pDevIns, pvUser, off, pv, cb);
1885	LogFlowFunc(("pThis=%#p GCPhysAddr=%RGp pv=%#p{%.*Rhxs} cb=%u\n", PDMDEVINS_2_DATA(pDevIns, PLSILOGICSCSI), off, pv, cb, pv, cb));
1886	return VINF_SUCCESS;
1887	}
1888
1889	/**
1890	* @callback_method_impl{FNIOMMMIONEWREAD}
1891	*/
1892	static DECLCALLBACK(VBOXSTRICTRC) lsilogicDiagnosticRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
1893	{
1894	RT_NOREF(pDevIns, pvUser, off, pv, cb);
1895	LogFlowFunc(("pThis=%#p off=%RGp pv=%#p{%.*Rhxs} cb=%u\n", PDMDEVINS_2_DATA(pDevIns, PLSILOGICSCSI), off, pv, cb, pv, cb));
1896	return VINF_SUCCESS;
1897	}
1898
1899	#ifdef IN_RING3
1900
1901	# ifdef LOG_ENABLED
1902	/**
1903	* Dump an SG entry.
1904	*
1905	* @returns nothing.
1906	* @param pSGEntry Pointer to the SG entry to dump
1907	*/
1908	static void lsilogicDumpSGEntry(PMptSGEntryUnion pSGEntry)
1909	{
1910	if (LogIsEnabled())
1911	{
1912	switch (pSGEntry->Simple32.u2ElementType)
1913	{
1914	case MPTSGENTRYTYPE_SIMPLE:
1915	{
1916	Log(("%s: Dumping info for SIMPLE SG entry:\n", __FUNCTION__));
1917	Log(("%s: u24Length=%u\n", __FUNCTION__, pSGEntry->Simple32.u24Length));
1918	Log(("%s: fEndOfList=%d\n", __FUNCTION__, pSGEntry->Simple32.fEndOfList));
1919	Log(("%s: f64BitAddress=%d\n", __FUNCTION__, pSGEntry->Simple32.f64BitAddress));
1920	Log(("%s: fBufferContainsData=%d\n", __FUNCTION__, pSGEntry->Simple32.fBufferContainsData));
1921	Log(("%s: fLocalAddress=%d\n", __FUNCTION__, pSGEntry->Simple32.fLocalAddress));
1922	Log(("%s: fEndOfBuffer=%d\n", __FUNCTION__, pSGEntry->Simple32.fEndOfBuffer));
1923	Log(("%s: fLastElement=%d\n", __FUNCTION__, pSGEntry->Simple32.fLastElement));
1924	Log(("%s: u32DataBufferAddressLow=%u\n", __FUNCTION__, pSGEntry->Simple32.u32DataBufferAddressLow));
1925	if (pSGEntry->Simple32.f64BitAddress)
1926	{
1927	Log(("%s: u32DataBufferAddressHigh=%u\n", __FUNCTION__, pSGEntry->Simple64.u32DataBufferAddressHigh));
1928	Log(("%s: GCDataBufferAddress=%RGp\n", __FUNCTION__,
1929	((uint64_t)pSGEntry->Simple64.u32DataBufferAddressHigh << 32)
1930	\| pSGEntry->Simple64.u32DataBufferAddressLow));
1931	}
1932	else
1933	Log(("%s: GCDataBufferAddress=%RGp\n", __FUNCTION__, pSGEntry->Simple32.u32DataBufferAddressLow));
1934
1935	break;
1936	}
1937	case MPTSGENTRYTYPE_CHAIN:
1938	{
1939	Log(("%s: Dumping info for CHAIN SG entry:\n", __FUNCTION__));
1940	Log(("%s: u16Length=%u\n", __FUNCTION__, pSGEntry->Chain.u16Length));
1941	Log(("%s: u8NExtChainOffset=%d\n", __FUNCTION__, pSGEntry->Chain.u8NextChainOffset));
1942	Log(("%s: f64BitAddress=%d\n", __FUNCTION__, pSGEntry->Chain.f64BitAddress));
1943	Log(("%s: fLocalAddress=%d\n", __FUNCTION__, pSGEntry->Chain.fLocalAddress));
1944	Log(("%s: u32SegmentAddressLow=%u\n", __FUNCTION__, pSGEntry->Chain.u32SegmentAddressLow));
1945	Log(("%s: u32SegmentAddressHigh=%u\n", __FUNCTION__, pSGEntry->Chain.u32SegmentAddressHigh));
1946	if (pSGEntry->Chain.f64BitAddress)
1947	Log(("%s: GCSegmentAddress=%RGp\n", __FUNCTION__,
1948	((uint64_t)pSGEntry->Chain.u32SegmentAddressHigh << 32) \| pSGEntry->Chain.u32SegmentAddressLow));
1949	else
1950	Log(("%s: GCSegmentAddress=%RGp\n", __FUNCTION__, pSGEntry->Chain.u32SegmentAddressLow));
1951	break;
1952	}
1953	}
1954	}
1955	}
1956	# endif /* LOG_ENABLED */
1957
1958	/**
1959	* Copy from guest to host memory worker.
1960	*
1961	* @copydoc FNLSILOGICR3MEMCOPYCALLBACK
1962	*/
1963	static DECLCALLBACK(void) lsilogicR3CopyBufferFromGuestWorker(PPDMDEVINS pDevIns, RTGCPHYS GCPhys,
1964	PRTSGBUF pSgBuf, size_t cbCopy, size_t *pcbSkip)
1965	{
1966	size_t cbSkipped = RT_MIN(cbCopy, *pcbSkip);
1967	cbCopy -= cbSkipped;
1968	GCPhys += cbSkipped;
1969	*pcbSkip -= cbSkipped;
1970
1971	while (cbCopy)
1972	{
1973	size_t cbSeg = cbCopy;
1974	void *pvSeg = RTSgBufGetNextSegment(pSgBuf, &cbSeg);
1975
1976	AssertPtr(pvSeg);
1977	PDMDevHlpPCIPhysReadUser(pDevIns, GCPhys, pvSeg, cbSeg);
1978	GCPhys += cbSeg;
1979	cbCopy -= cbSeg;
1980	}
1981	}
1982
1983	/**
1984	* Copy from host to guest memory worker.
1985	*
1986	* @copydoc FNLSILOGICR3MEMCOPYCALLBACK
1987	*/
1988	static DECLCALLBACK(void) lsilogicR3CopyBufferToGuestWorker(PPDMDEVINS pDevIns, RTGCPHYS GCPhys,
1989	PRTSGBUF pSgBuf, size_t cbCopy, size_t *pcbSkip)
1990	{
1991	size_t cbSkipped = RT_MIN(cbCopy, *pcbSkip);
1992	cbCopy -= cbSkipped;
1993	GCPhys += cbSkipped;
1994	*pcbSkip -= cbSkipped;
1995
1996	while (cbCopy)
1997	{
1998	size_t cbSeg = cbCopy;
1999	void *pvSeg = RTSgBufGetNextSegment(pSgBuf, &cbSeg);
2000
2001	AssertPtr(pvSeg);
2002	PDMDevHlpPCIPhysWriteUser(pDevIns, GCPhys, pvSeg, cbSeg);
2003	GCPhys += cbSeg;
2004	cbCopy -= cbSeg;
2005	}
2006	}
2007
2008	/**
2009	* Walks the guest S/G buffer calling the given copy worker for every buffer.
2010	*
2011	* @returns The amout of bytes actually copied.
2012	* @param pDevIns The device instance.
2013	* @param pLsiReq LSI request state.
2014	* @param pfnCopyWorker The copy method to apply for each guest buffer.
2015	* @param pSgBuf The host S/G buffer.
2016	* @param cbSkip How many bytes to skip in advance before starting to
2017	* copy.
2018	* @param cbCopy How many bytes to copy.
2019	*/
2020	static size_t lsilogicSgBufWalker(PPDMDEVINS pDevIns, PLSILOGICREQ pLsiReq,
2021	PFNLSILOGICR3MEMCOPYCALLBACK pfnCopyWorker,
2022	PRTSGBUF pSgBuf, size_t cbSkip, size_t cbCopy)
2023	{
2024	bool fEndOfList = false;
2025	RTGCPHYS GCPhysSgEntryNext = pLsiReq->GCPhysSgStart;
2026	RTGCPHYS GCPhysSegmentStart = pLsiReq->GCPhysSgStart;
2027	uint32_t cChainOffsetNext = pLsiReq->cChainOffset;
2028	size_t cbCopied = 0;
2029
2030	/*
2031	* Add the amount to skip to the host buffer size to avoid a
2032	* few conditionals later on.
2033	*/
2034	cbCopy += cbSkip;
2035
2036	/* Go through the list until we reach the end. */
2037	while ( !fEndOfList
2038	&& cbCopy)
2039	{
2040	bool fEndOfSegment = false;
2041
2042	while ( !fEndOfSegment
2043	&& cbCopy)
2044	{
2045	MptSGEntryUnion SGEntry;
2046
2047	Log(("%s: Reading SG entry from %RGp\n", __FUNCTION__, GCPhysSgEntryNext));
2048
2049	/* Read the entry. */
2050	PDMDevHlpPCIPhysReadMeta(pDevIns, GCPhysSgEntryNext, &SGEntry, sizeof(MptSGEntryUnion));
2051
2052	# ifdef LOG_ENABLED
2053	lsilogicDumpSGEntry(&SGEntry);
2054	# endif
2055
2056	AssertMsg(SGEntry.Simple32.u2ElementType == MPTSGENTRYTYPE_SIMPLE, ("Invalid SG entry type\n"));
2057
2058	/* Check if this is a zero element and abort. */
2059	if ( !SGEntry.Simple32.u24Length
2060	&& SGEntry.Simple32.fEndOfList
2061	&& SGEntry.Simple32.fEndOfBuffer)
2062	return cbCopied - RT_MIN(cbSkip, cbCopied);
2063
2064	size_t cbCopyThis = RT_MIN(SGEntry.Simple32.u24Length, cbCopy);
2065	RTGCPHYS GCPhysAddrDataBuffer = SGEntry.Simple32.u32DataBufferAddressLow;
2066
2067	if (SGEntry.Simple32.f64BitAddress)
2068	{
2069	GCPhysAddrDataBuffer \|= ((uint64_t)SGEntry.Simple64.u32DataBufferAddressHigh) << 32;
2070	GCPhysSgEntryNext += sizeof(MptSGEntrySimple64);
2071	}
2072	else
2073	GCPhysSgEntryNext += sizeof(MptSGEntrySimple32);
2074
2075	pfnCopyWorker(pDevIns, GCPhysAddrDataBuffer, pSgBuf, cbCopyThis, &cbSkip);
2076	cbCopy -= cbCopyThis;
2077	cbCopied += cbCopyThis;
2078
2079	/* Check if we reached the end of the list. */
2080	if (SGEntry.Simple32.fEndOfList)
2081	{
2082	/* We finished. */
2083	fEndOfSegment = true;
2084	fEndOfList = true;
2085	}
2086	else if (SGEntry.Simple32.fLastElement)
2087	fEndOfSegment = true;
2088	} /* while (!fEndOfSegment) */
2089
2090	/* Get next chain element. */
2091	if (cChainOffsetNext)
2092	{
2093	MptSGEntryChain SGEntryChain;
2094
2095	PDMDevHlpPCIPhysReadMeta(pDevIns, GCPhysSegmentStart + cChainOffsetNext, &SGEntryChain, sizeof(MptSGEntryChain));
2096
2097	AssertMsg(SGEntryChain.u2ElementType == MPTSGENTRYTYPE_CHAIN, ("Invalid SG entry type\n"));
2098
2099	/* Set the next address now. */
2100	GCPhysSgEntryNext = SGEntryChain.u32SegmentAddressLow;
2101	if (SGEntryChain.f64BitAddress)
2102	GCPhysSgEntryNext \|= ((uint64_t)SGEntryChain.u32SegmentAddressHigh) << 32;
2103
2104	GCPhysSegmentStart = GCPhysSgEntryNext;
2105	cChainOffsetNext = SGEntryChain.u8NextChainOffset * sizeof(uint32_t);
2106	}
2107	} /* while (!fEndOfList) */
2108
2109	return cbCopied - RT_MIN(cbSkip, cbCopied);
2110	}
2111
2112	/**
2113	* Copies a data buffer into the S/G buffer set up by the guest.
2114	*
2115	* @returns Amount of bytes copied to the guest.
2116	* @param pDevIns The device instance.
2117	* @param pReq Request structure.
2118	* @param pSgBuf The S/G buffer to copy from.
2119	* @param cbSkip How many bytes to skip in advance before starting to copy.
2120	* @param cbCopy How many bytes to copy.
2121	*/
2122	static size_t lsilogicR3CopySgBufToGuest(PPDMDEVINS pDevIns, PLSILOGICREQ pReq, PRTSGBUF pSgBuf,
2123	size_t cbSkip, size_t cbCopy)
2124	{
2125	return lsilogicSgBufWalker(pDevIns, pReq, lsilogicR3CopyBufferToGuestWorker, pSgBuf, cbSkip, cbCopy);
2126	}
2127
2128	/**
2129	* Copies the guest S/G buffer into a host data buffer.
2130	*
2131	* @returns Amount of bytes copied from the guest.
2132	* @param pDevIns The device instance.
2133	* @param pReq Request structure.
2134	* @param pSgBuf The S/G buffer to copy into.
2135	* @param cbSkip How many bytes to skip in advance before starting to copy.
2136	* @param cbCopy How many bytes to copy.
2137	*/
2138	static size_t lsilogicR3CopySgBufFromGuest(PPDMDEVINS pDevIns, PLSILOGICREQ pReq, PRTSGBUF pSgBuf,
2139	size_t cbSkip, size_t cbCopy)
2140	{
2141	return lsilogicSgBufWalker(pDevIns, pReq, lsilogicR3CopyBufferFromGuestWorker, pSgBuf, cbSkip, cbCopy);
2142	}
2143
2144	#if 0 /* unused */
2145	/**
2146	* Copy a simple memory buffer to the guest memory buffer.
2147	*
2148	* @returns Amount of bytes copied to the guest.
2149	* @param pThis The LsiLogic controller device instance.
2150	* @param pReq Request structure.
2151	* @param pvSrc The buffer to copy from.
2152	* @param cbSrc How many bytes to copy.
2153	* @param cbSkip How many bytes to skip initially.
2154	*/
2155	static size_t lsilogicR3CopyBufferToGuest(PLSILOGICSCSI pThis, PLSILOGICREQ pReq, const void *pvSrc,
2156	size_t cbSrc, size_t cbSkip)
2157	{
2158	RTSGSEG Seg;
2159	RTSGBUF SgBuf;
2160	Seg.pvSeg = (void *)pvSrc;
2161	Seg.cbSeg = cbSrc;
2162	RTSgBufInit(&SgBuf, &Seg, 1);
2163	return lsilogicR3CopySgBufToGuest(pThis, pReq, &SgBuf, cbSkip, cbSrc);
2164	}
2165
2166	/**
2167	* Copy a guest memry buffe into simple host memory buffer.
2168	*
2169	* @returns Amount of bytes copied to the guest.
2170	* @param pThis The LsiLogic controller device instance.
2171	* @param pReq Request structure.
2172	* @param pvSrc The buffer to copy from.
2173	* @param cbSrc How many bytes to copy.
2174	* @param cbSkip How many bytes to skip initially.
2175	*/
2176	static size_t lsilogicR3CopyBufferFromGuest(PLSILOGICSCSI pThis, PLSILOGICREQ pReq, void *pvDst,
2177	size_t cbDst, size_t cbSkip)
2178	{
2179	RTSGSEG Seg;
2180	RTSGBUF SgBuf;
2181	Seg.pvSeg = (void *)pvDst;
2182	Seg.cbSeg = cbDst;
2183	RTSgBufInit(&SgBuf, &Seg, 1);
2184	return lsilogicR3CopySgBufFromGuest(pThis, pReq, &SgBuf, cbSkip, cbDst);
2185	}
2186	#endif
2187
2188	# ifdef LOG_ENABLED
2189	static void lsilogicR3DumpSCSIIORequest(PMptSCSIIORequest pSCSIIORequest)
2190	{
2191	if (LogIsEnabled())
2192	{
2193	Log(("%s: u8TargetID=%d\n", __FUNCTION__, pSCSIIORequest->u8TargetID));
2194	Log(("%s: u8Bus=%d\n", __FUNCTION__, pSCSIIORequest->u8Bus));
2195	Log(("%s: u8ChainOffset=%d\n", __FUNCTION__, pSCSIIORequest->u8ChainOffset));
2196	Log(("%s: u8Function=%d\n", __FUNCTION__, pSCSIIORequest->u8Function));
2197	Log(("%s: u8CDBLength=%d\n", __FUNCTION__, pSCSIIORequest->u8CDBLength));
2198	Log(("%s: u8SenseBufferLength=%d\n", __FUNCTION__, pSCSIIORequest->u8SenseBufferLength));
2199	Log(("%s: u8MessageFlags=%d\n", __FUNCTION__, pSCSIIORequest->u8MessageFlags));
2200	Log(("%s: u32MessageContext=%#x\n", __FUNCTION__, pSCSIIORequest->u32MessageContext));
2201	for (unsigned i = 0; i < RT_ELEMENTS(pSCSIIORequest->au8LUN); i++)
2202	Log(("%s: u8LUN[%d]=%d\n", __FUNCTION__, i, pSCSIIORequest->au8LUN[i]));
2203	Log(("%s: u32Control=%#x\n", __FUNCTION__, pSCSIIORequest->u32Control));
2204	for (unsigned i = 0; i < RT_ELEMENTS(pSCSIIORequest->au8CDB); i++)
2205	Log(("%s: u8CDB[%d]=%d\n", __FUNCTION__, i, pSCSIIORequest->au8CDB[i]));
2206	Log(("%s: u32DataLength=%#x\n", __FUNCTION__, pSCSIIORequest->u32DataLength));
2207	Log(("%s: u32SenseBufferLowAddress=%#x\n", __FUNCTION__, pSCSIIORequest->u32SenseBufferLowAddress));
2208	}
2209	}
2210	# endif
2211
2212	/**
2213	* Handles the completion of th given request.
2214	*
2215	* @returns nothing.
2216	* @param pDevIns The device instance.
2217	* @param pThis Pointer to the shared LsiLogic device state.
2218	* @param pReq The request to complete.
2219	* @param rcReq Status code of the request.
2220	*/
2221	static void lsilogicR3ReqComplete(PPDMDEVINS pDevIns, PLSILOGICSCSI pThis, PLSILOGICREQ pReq, int rcReq)
2222	{
2223	PLSILOGICDEVICE pTgtDev = pReq->pTargetDevice;
2224	RTGCPHYS GCPhysAddrSenseBuffer;
2225
2226	GCPhysAddrSenseBuffer = pReq->GuestRequest.SCSIIO.u32SenseBufferLowAddress;
2227	GCPhysAddrSenseBuffer \|= ((uint64_t)pThis->u32SenseBufferHighAddr << 32);
2228
2229	/* Copy the sense buffer over. */
2230	if (pReq->GuestRequest.SCSIIO.u8SenseBufferLength > 0)
2231	PDMDevHlpPCIPhysWriteMeta(pDevIns, GCPhysAddrSenseBuffer, pReq->abSenseBuffer,
2232	RT_UNLIKELY( pReq->GuestRequest.SCSIIO.u8SenseBufferLength
2233	< sizeof(pReq->abSenseBuffer))
2234	? pReq->GuestRequest.SCSIIO.u8SenseBufferLength
2235	: sizeof(pReq->abSenseBuffer));
2236
2237	if (RT_SUCCESS(rcReq) && RT_LIKELY(pReq->u8ScsiSts == SCSI_STATUS_OK))
2238	{
2239	uint32_t u32MsgCtx = pReq->GuestRequest.SCSIIO.u32MessageContext;
2240
2241	/* Free the request before posting completion. */
2242	pTgtDev->pDrvMediaEx->pfnIoReqFree(pTgtDev->pDrvMediaEx, pReq->hIoReq);
2243	lsilogicR3FinishContextReply(pDevIns, pThis, u32MsgCtx);
2244	}
2245	else
2246	{
2247	MptReplyUnion IOCReply;
2248	RT_ZERO(IOCReply);
2249
2250	/* The SCSI target encountered an error during processing post a reply. */
2251	IOCReply.SCSIIOError.u8TargetID = pReq->GuestRequest.SCSIIO.u8TargetID;
2252	IOCReply.SCSIIOError.u8Bus = pReq->GuestRequest.SCSIIO.u8Bus;
2253	IOCReply.SCSIIOError.u8MessageLength = 8;
2254	IOCReply.SCSIIOError.u8Function = pReq->GuestRequest.SCSIIO.u8Function;
2255	IOCReply.SCSIIOError.u8CDBLength = pReq->GuestRequest.SCSIIO.u8CDBLength;
2256	IOCReply.SCSIIOError.u8SenseBufferLength = pReq->GuestRequest.SCSIIO.u8SenseBufferLength;
2257	IOCReply.SCSIIOError.u8MessageFlags = pReq->GuestRequest.SCSIIO.u8MessageFlags;
2258	IOCReply.SCSIIOError.u32MessageContext = pReq->GuestRequest.SCSIIO.u32MessageContext;
2259	IOCReply.SCSIIOError.u8SCSIStatus = pReq->u8ScsiSts;
2260	IOCReply.SCSIIOError.u8SCSIState = MPT_SCSI_IO_ERROR_SCSI_STATE_AUTOSENSE_VALID;
2261	IOCReply.SCSIIOError.u16IOCStatus = 0;
2262	IOCReply.SCSIIOError.u32IOCLogInfo = 0;
2263	IOCReply.SCSIIOError.u32TransferCount = 0;
2264	IOCReply.SCSIIOError.u32SenseCount = sizeof(pReq->abSenseBuffer);
2265	IOCReply.SCSIIOError.u32ResponseInfo = 0;
2266
2267	/* Free the request before posting completion. */
2268	pTgtDev->pDrvMediaEx->pfnIoReqFree(pTgtDev->pDrvMediaEx, pReq->hIoReq);
2269	lsilogicFinishAddressReply(pDevIns, pThis, &IOCReply, false);
2270	}
2271
2272	ASMAtomicDecU32(&pTgtDev->cOutstandingRequests);
2273
2274	if (pTgtDev->cOutstandingRequests == 0 && pThis->fSignalIdle)
2275	PDMDevHlpAsyncNotificationCompleted(pDevIns);
2276	}
2277
2278	/**
2279	* Processes a SCSI I/O request by setting up the request
2280	* and sending it to the underlying SCSI driver.
2281	* Steps needed to complete request are done in the
2282	* callback called by the driver below upon completion of
2283	* the request.
2284	*
2285	* @returns VBox status code.
2286	* @param pDevIns The device instance.
2287	* @param pThis Pointer to the shared LsiLogic device state.
2288	* @param pThisCC Pointer to the ring-3 LsiLogic device state.
2289	* @param GCPhysMessageFrameAddr Guest physical address where the request is located.
2290	* @param pGuestReq The request read fro th guest memory.
2291	*/
2292	static int lsilogicR3ProcessSCSIIORequest(PPDMDEVINS pDevIns, PLSILOGICSCSI pThis, PLSILOGICSCSICC pThisCC,
2293	RTGCPHYS GCPhysMessageFrameAddr, PMptRequestUnion pGuestReq)
2294	{
2295	MptReplyUnion IOCReply;
2296	int rc = VINF_SUCCESS;
2297
2298	# ifdef LOG_ENABLED
2299	lsilogicR3DumpSCSIIORequest(&pGuestReq->SCSIIO);
2300	# endif
2301
2302	if (RT_LIKELY( (pGuestReq->SCSIIO.u8TargetID < pThis->cDeviceStates)
2303	&& (pGuestReq->SCSIIO.u8Bus == 0)))
2304	{
2305	PLSILOGICDEVICE pTgtDev = &pThisCC->paDeviceStates[pGuestReq->SCSIIO.u8TargetID];
2306
2307	if (pTgtDev->pDrvBase)
2308	{
2309	/* Allocate and prepare a new request. */
2310	PDMMEDIAEXIOREQ hIoReq;
2311	PLSILOGICREQ pLsiReq = NULL;
2312	rc = pTgtDev->pDrvMediaEx->pfnIoReqAlloc(pTgtDev->pDrvMediaEx, &hIoReq, (void **)&pLsiReq,
2313	pGuestReq->SCSIIO.u32MessageContext,
2314	PDMIMEDIAEX_F_SUSPEND_ON_RECOVERABLE_ERR);
2315	if (RT_SUCCESS(rc))
2316	{
2317	pLsiReq->hIoReq = hIoReq;
2318	pLsiReq->pTargetDevice = pTgtDev;
2319	pLsiReq->GCPhysMessageFrameAddr = GCPhysMessageFrameAddr;
2320	pLsiReq->GCPhysSgStart = GCPhysMessageFrameAddr + sizeof(MptSCSIIORequest);
2321	pLsiReq->cChainOffset = pGuestReq->SCSIIO.u8ChainOffset;
2322	if (pLsiReq->cChainOffset)
2323	pLsiReq->cChainOffset = pLsiReq->cChainOffset * sizeof(uint32_t) - sizeof(MptSCSIIORequest);
2324	memcpy(&pLsiReq->GuestRequest, pGuestReq, sizeof(MptRequestUnion));
2325	RT_BZERO(&pLsiReq->abSenseBuffer[0], sizeof(pLsiReq->abSenseBuffer));
2326
2327	PDMMEDIAEXIOREQSCSITXDIR enmXferDir = PDMMEDIAEXIOREQSCSITXDIR_UNKNOWN;
2328	uint8_t uDataDirection = MPT_SCSIIO_REQUEST_CONTROL_TXDIR_GET(pLsiReq->GuestRequest.SCSIIO.u32Control);
2329
2330	/*
2331	* Keep the direction to unknown if there is a mismatch between the data length
2332	* and the transfer direction bit.
2333	* The Solaris 9 driver is buggy and sets it to none for INQUIRY requests.
2334	*/
2335	if ( uDataDirection == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_NONE
2336	&& pLsiReq->GuestRequest.SCSIIO.u32DataLength == 0)
2337	enmXferDir = PDMMEDIAEXIOREQSCSITXDIR_NONE;
2338	else if (uDataDirection == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_WRITE)
2339	enmXferDir = PDMMEDIAEXIOREQSCSITXDIR_TO_DEVICE;
2340	else if (uDataDirection == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_READ)
2341	enmXferDir = PDMMEDIAEXIOREQSCSITXDIR_FROM_DEVICE;
2342
2343	ASMAtomicIncU32(&pTgtDev->cOutstandingRequests);
2344	rc = pTgtDev->pDrvMediaEx->pfnIoReqSendScsiCmd(pTgtDev->pDrvMediaEx, pLsiReq->hIoReq, pLsiReq->GuestRequest.SCSIIO.au8LUN[1],
2345	&pLsiReq->GuestRequest.SCSIIO.au8CDB[0], pLsiReq->GuestRequest.SCSIIO.u8CDBLength,
2346	enmXferDir, NULL, pLsiReq->GuestRequest.SCSIIO.u32DataLength,
2347	&pLsiReq->abSenseBuffer[0], sizeof(pLsiReq->abSenseBuffer), NULL,
2348	&pLsiReq->u8ScsiSts, 30 * RT_MS_1SEC);
2349	if (rc != VINF_PDM_MEDIAEX_IOREQ_IN_PROGRESS)
2350	lsilogicR3ReqComplete(pDevIns, pThis, pLsiReq, rc);
2351
2352	return VINF_SUCCESS;
2353	}
2354	else
2355	IOCReply.SCSIIOError.u16IOCStatus = MPT_SCSI_IO_ERROR_IOCSTATUS_DEVICE_NOT_THERE;
2356	}
2357	else
2358	{
2359	/* Device is not present report SCSI selection timeout. */
2360	IOCReply.SCSIIOError.u16IOCStatus = MPT_SCSI_IO_ERROR_IOCSTATUS_DEVICE_NOT_THERE;
2361	}
2362	}
2363	else
2364	{
2365	/* Report out of bounds target ID or bus. */
2366	if (pGuestReq->SCSIIO.u8Bus != 0)
2367	IOCReply.SCSIIOError.u16IOCStatus = MPT_SCSI_IO_ERROR_IOCSTATUS_INVALID_BUS;
2368	else
2369	IOCReply.SCSIIOError.u16IOCStatus = MPT_SCSI_IO_ERROR_IOCSTATUS_INVALID_TARGETID;
2370	}
2371
2372	static int g_cLogged = 0;
2373
2374	if (g_cLogged++ < MAX_REL_LOG_ERRORS)
2375	{
2376	LogRel(("LsiLogic#%d: %d/%d (Bus/Target) doesn't exist\n", pDevIns->iInstance,
2377	pGuestReq->SCSIIO.u8TargetID, pGuestReq->SCSIIO.u8Bus));
2378	/* Log the CDB too */
2379	LogRel(("LsiLogic#%d: Guest issued CDB {%#x",
2380	pDevIns->iInstance, pGuestReq->SCSIIO.au8CDB[0]));
2381	for (unsigned i = 1; i < pGuestReq->SCSIIO.u8CDBLength; i++)
2382	LogRel((", %#x", pGuestReq->SCSIIO.au8CDB[i]));
2383	LogRel(("}\n"));
2384	}
2385
2386	/* The rest is equal to both errors. */
2387	IOCReply.SCSIIOError.u8TargetID = pGuestReq->SCSIIO.u8TargetID;
2388	IOCReply.SCSIIOError.u8Bus = pGuestReq->SCSIIO.u8Bus;
2389	IOCReply.SCSIIOError.u8MessageLength = sizeof(MptSCSIIOErrorReply) / 4;
2390	IOCReply.SCSIIOError.u8Function = pGuestReq->SCSIIO.u8Function;
2391	IOCReply.SCSIIOError.u8CDBLength = pGuestReq->SCSIIO.u8CDBLength;
2392	IOCReply.SCSIIOError.u8SenseBufferLength = pGuestReq->SCSIIO.u8SenseBufferLength;
2393	IOCReply.SCSIIOError.u8Reserved = 0;
2394	IOCReply.SCSIIOError.u8MessageFlags = 0;
2395	IOCReply.SCSIIOError.u32MessageContext = pGuestReq->SCSIIO.u32MessageContext;
2396	IOCReply.SCSIIOError.u8SCSIStatus = SCSI_STATUS_OK;
2397	IOCReply.SCSIIOError.u8SCSIState = MPT_SCSI_IO_ERROR_SCSI_STATE_TERMINATED;
2398	IOCReply.SCSIIOError.u32IOCLogInfo = 0;
2399	IOCReply.SCSIIOError.u32TransferCount = 0;
2400	IOCReply.SCSIIOError.u32SenseCount = 0;
2401	IOCReply.SCSIIOError.u32ResponseInfo = 0;
2402
2403	lsilogicFinishAddressReply(pDevIns, pThis, &IOCReply, false);
2404
2405	return rc;
2406	}
2407
2408
2409	/**
2410	* @interface_method_impl{PDMIMEDIAPORT,pfnQueryDeviceLocation}
2411	*/
2412	static DECLCALLBACK(int) lsilogicR3QueryDeviceLocation(PPDMIMEDIAPORT pInterface, const char **ppcszController,
2413	uint32_t piInstance, uint32_t piLUN)
2414	{
2415	PLSILOGICDEVICE pTgtDev = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, IMediaPort);
2416	PPDMDEVINS pDevIns = pTgtDev->pDevIns;
2417
2418	AssertPtrReturn(ppcszController, VERR_INVALID_POINTER);
2419	AssertPtrReturn(piInstance, VERR_INVALID_POINTER);
2420	AssertPtrReturn(piLUN, VERR_INVALID_POINTER);
2421
2422	*ppcszController = pDevIns->pReg->szName;
2423	*piInstance = pDevIns->iInstance;
2424	*piLUN = pTgtDev->iLUN;
2425
2426	return VINF_SUCCESS;
2427	}
2428
2429
2430	/**
2431	* @interface_method_impl{PDMIMEDIAEXPORT,pfnIoReqCopyFromBuf}
2432	*/
2433	static DECLCALLBACK(int) lsilogicR3IoReqCopyFromBuf(PPDMIMEDIAEXPORT pInterface, PDMMEDIAEXIOREQ hIoReq,
2434	void *pvIoReqAlloc, uint32_t offDst, PRTSGBUF pSgBuf,
2435	size_t cbCopy)
2436	{
2437	RT_NOREF1(hIoReq);
2438	PLSILOGICDEVICE pTgtDev = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, IMediaExPort);
2439	PPDMDEVINS pDevIns = pTgtDev->pDevIns;
2440	PLSILOGICREQ pReq = (PLSILOGICREQ)pvIoReqAlloc;
2441
2442	size_t cbCopied = lsilogicR3CopySgBufToGuest(pDevIns, pReq, pSgBuf, offDst, cbCopy);
2443	return cbCopied == cbCopy ? VINF_SUCCESS : VERR_PDM_MEDIAEX_IOBUF_OVERFLOW;
2444	}
2445
2446	/**
2447	* @interface_method_impl{PDMIMEDIAEXPORT,pfnIoReqCopyToBuf}
2448	*/
2449	static DECLCALLBACK(int) lsilogicR3IoReqCopyToBuf(PPDMIMEDIAEXPORT pInterface, PDMMEDIAEXIOREQ hIoReq,
2450	void *pvIoReqAlloc, uint32_t offSrc, PRTSGBUF pSgBuf,
2451	size_t cbCopy)
2452	{
2453	RT_NOREF1(hIoReq);
2454	PLSILOGICDEVICE pTgtDev = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, IMediaExPort);
2455	PPDMDEVINS pDevIns = pTgtDev->pDevIns;
2456	PLSILOGICREQ pReq = (PLSILOGICREQ)pvIoReqAlloc;
2457
2458	size_t cbCopied = lsilogicR3CopySgBufFromGuest(pDevIns, pReq, pSgBuf, offSrc, cbCopy);
2459	return cbCopied == cbCopy ? VINF_SUCCESS : VERR_PDM_MEDIAEX_IOBUF_UNDERRUN;
2460	}
2461
2462	/**
2463	* @interface_method_impl{PDMIMEDIAEXPORT,pfnIoReqCompleteNotify}
2464	*/
2465	static DECLCALLBACK(int) lsilogicR3IoReqCompleteNotify(PPDMIMEDIAEXPORT pInterface, PDMMEDIAEXIOREQ hIoReq,
2466	void *pvIoReqAlloc, int rcReq)
2467	{
2468	RT_NOREF(hIoReq);
2469	PLSILOGICDEVICE pTgtDev = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, IMediaExPort);
2470	PPDMDEVINS pDevIns = pTgtDev->pDevIns;
2471	PLSILOGICSCSI pThis = PDMDEVINS_2_DATA(pDevIns, PLSILOGICSCSI);
2472	lsilogicR3ReqComplete(pDevIns, pThis, (PLSILOGICREQ)pvIoReqAlloc, rcReq);
2473	return VINF_SUCCESS;
2474	}
2475
2476	/**
2477	* @interface_method_impl{PDMIMEDIAEXPORT,pfnIoReqStateChanged}
2478	*/
2479	static DECLCALLBACK(void) lsilogicR3IoReqStateChanged(PPDMIMEDIAEXPORT pInterface, PDMMEDIAEXIOREQ hIoReq,
2480	void *pvIoReqAlloc, PDMMEDIAEXIOREQSTATE enmState)
2481	{
2482	RT_NOREF3(hIoReq, pvIoReqAlloc, enmState);
2483	PLSILOGICDEVICE pTgtDev = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, IMediaExPort);
2484
2485	switch (enmState)
2486	{
2487	case PDMMEDIAEXIOREQSTATE_SUSPENDED:
2488	{
2489	/* Make sure the request is not accounted for so the VM can suspend successfully. */
2490	PPDMDEVINS pDevIns = pTgtDev->pDevIns;
2491	PLSILOGICSCSI pThis = PDMDEVINS_2_DATA(pDevIns, PLSILOGICSCSI);
2492	uint32_t cTasksActive = ASMAtomicDecU32(&pTgtDev->cOutstandingRequests);
2493	if (!cTasksActive && pThis->fSignalIdle)
2494	PDMDevHlpAsyncNotificationCompleted(pDevIns);
2495	break;
2496	}
2497	case PDMMEDIAEXIOREQSTATE_ACTIVE:
2498	/* Make sure the request is accounted for so the VM suspends only when the request is complete. */
2499	ASMAtomicIncU32(&pTgtDev->cOutstandingRequests);
2500	break;
2501	default:
2502	AssertMsgFailed(("Invalid request state given %u\n", enmState));
2503	}
2504	}
2505
2506	/**
2507	* @interface_method_impl{PDMIMEDIAEXPORT,pfnMediumEjected}
2508	*/
2509	static DECLCALLBACK(void) lsilogicR3MediumEjected(PPDMIMEDIAEXPORT pInterface)
2510	{
2511	PLSILOGICDEVICE pTgtDev = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, IMediaExPort);
2512	PPDMDEVINS pDevIns = pTgtDev->pDevIns;
2513	PLSILOGICSCSICC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PLSILOGICSCSICC);
2514
2515	if (pThisCC->pMediaNotify)
2516	{
2517	int rc = VMR3ReqCallNoWait(PDMDevHlpGetVM(pDevIns), VMCPUID_ANY,
2518	(PFNRT)pThisCC->pMediaNotify->pfnEjected, 2,
2519	pThisCC->pMediaNotify, pTgtDev->iLUN);
2520	AssertRC(rc);
2521	}
2522	}
2523
2524
2525	/**
2526	* Return the configuration page header and data
2527	* which matches the given page type and number.
2528	*
2529	* @returns VINF_SUCCESS if successful
2530	* VERR_NOT_FOUND if the requested page could be found.
2531	* @param pThis Pointer to the shared LsiLogic device state. data.
2532	* @param pPages The pages supported by the controller.
2533	* @param u8PageNumber Number of the page to get.
2534	* @param ppPageHeader Where to store the pointer to the page header.
2535	* @param ppbPageData Where to store the pointer to the page data.
2536	* @param pcbPage Where to store the size of the page data in bytes on success.
2537	*/
2538	static int lsilogicR3ConfigurationIOUnitPageGetFromNumber(PLSILOGICSCSI pThis,
2539	PMptConfigurationPagesSupported pPages,
2540	uint8_t u8PageNumber,
2541	PMptConfigurationPageHeader *ppPageHeader,
2542	uint8_t *ppbPageData, size_t pcbPage)
2543	{
2544	RT_NOREF(pThis);
2545	int rc = VINF_SUCCESS;
2546
2547	AssertPtr(ppPageHeader); Assert(ppbPageData);
2548
2549	switch (u8PageNumber)
2550	{
2551	case 0:
2552	*ppPageHeader = &pPages->IOUnitPage0.u.fields.Header;
2553	*ppbPageData = pPages->IOUnitPage0.u.abPageData;
2554	*pcbPage = sizeof(pPages->IOUnitPage0);
2555	break;
2556	case 1:
2557	*ppPageHeader = &pPages->IOUnitPage1.u.fields.Header;
2558	*ppbPageData = pPages->IOUnitPage1.u.abPageData;
2559	*pcbPage = sizeof(pPages->IOUnitPage1);
2560	break;
2561	case 2:
2562	*ppPageHeader = &pPages->IOUnitPage2.u.fields.Header;
2563	*ppbPageData = pPages->IOUnitPage2.u.abPageData;
2564	*pcbPage = sizeof(pPages->IOUnitPage2);
2565	break;
2566	case 3:
2567	*ppPageHeader = &pPages->IOUnitPage3.u.fields.Header;
2568	*ppbPageData = pPages->IOUnitPage3.u.abPageData;
2569	*pcbPage = sizeof(pPages->IOUnitPage3);
2570	break;
2571	case 4:
2572	*ppPageHeader = &pPages->IOUnitPage4.u.fields.Header;
2573	*ppbPageData = pPages->IOUnitPage4.u.abPageData;
2574	*pcbPage = sizeof(pPages->IOUnitPage4);
2575	break;
2576	default:
2577	rc = VERR_NOT_FOUND;
2578	}
2579
2580	return rc;
2581	}
2582
2583	/**
2584	* Return the configuration page header and data
2585	* which matches the given page type and number.
2586	*
2587	* @returns VINF_SUCCESS if successful
2588	* VERR_NOT_FOUND if the requested page could be found.
2589	* @param pThis Pointer to the shared LsiLogic device state. data.
2590	* @param pPages The pages supported by the controller.
2591	* @param u8PageNumber Number of the page to get.
2592	* @param ppPageHeader Where to store the pointer to the page header.
2593	* @param ppbPageData Where to store the pointer to the page data.
2594	* @param pcbPage Where to store the size of the page data in bytes on success.
2595	*/
2596	static int lsilogicR3ConfigurationIOCPageGetFromNumber(PLSILOGICSCSI pThis,
2597	PMptConfigurationPagesSupported pPages,
2598	uint8_t u8PageNumber,
2599	PMptConfigurationPageHeader *ppPageHeader,
2600	uint8_t *ppbPageData, size_t pcbPage)
2601	{
2602	RT_NOREF(pThis);
2603	int rc = VINF_SUCCESS;
2604
2605	AssertPtr(ppPageHeader); Assert(ppbPageData);
2606
2607	switch (u8PageNumber)
2608	{
2609	case 0:
2610	*ppPageHeader = &pPages->IOCPage0.u.fields.Header;
2611	*ppbPageData = pPages->IOCPage0.u.abPageData;
2612	*pcbPage = sizeof(pPages->IOCPage0);
2613	break;
2614	case 1:
2615	*ppPageHeader = &pPages->IOCPage1.u.fields.Header;
2616	*ppbPageData = pPages->IOCPage1.u.abPageData;
2617	*pcbPage = sizeof(pPages->IOCPage1);
2618	break;
2619	case 2:
2620	*ppPageHeader = &pPages->IOCPage2.u.fields.Header;
2621	*ppbPageData = pPages->IOCPage2.u.abPageData;
2622	*pcbPage = sizeof(pPages->IOCPage2);
2623	break;
2624	case 3:
2625	*ppPageHeader = &pPages->IOCPage3.u.fields.Header;
2626	*ppbPageData = pPages->IOCPage3.u.abPageData;
2627	*pcbPage = sizeof(pPages->IOCPage3);
2628	break;
2629	case 4:
2630	*ppPageHeader = &pPages->IOCPage4.u.fields.Header;
2631	*ppbPageData = pPages->IOCPage4.u.abPageData;
2632	*pcbPage = sizeof(pPages->IOCPage4);
2633	break;
2634	case 6:
2635	*ppPageHeader = &pPages->IOCPage6.u.fields.Header;
2636	*ppbPageData = pPages->IOCPage6.u.abPageData;
2637	*pcbPage = sizeof(pPages->IOCPage6);
2638	break;
2639	default:
2640	rc = VERR_NOT_FOUND;
2641	}
2642
2643	return rc;
2644	}
2645
2646	/**
2647	* Return the configuration page header and data
2648	* which matches the given page type and number.
2649	*
2650	* @returns VINF_SUCCESS if successful
2651	* VERR_NOT_FOUND if the requested page could be found.
2652	* @param pThis Pointer to the shared LsiLogic device state. data.
2653	* @param pPages The pages supported by the controller.
2654	* @param u8PageNumber Number of the page to get.
2655	* @param ppPageHeader Where to store the pointer to the page header.
2656	* @param ppbPageData Where to store the pointer to the page data.
2657	* @param pcbPage Where to store the size of the page data in bytes on success.
2658	*/
2659	static int lsilogicR3ConfigurationManufacturingPageGetFromNumber(PLSILOGICSCSI pThis,
2660	PMptConfigurationPagesSupported pPages,
2661	uint8_t u8PageNumber,
2662	PMptConfigurationPageHeader *ppPageHeader,
2663	uint8_t *ppbPageData, size_t pcbPage)
2664	{
2665	int rc = VINF_SUCCESS;
2666
2667	AssertPtr(ppPageHeader); Assert(ppbPageData);
2668
2669	switch (u8PageNumber)
2670	{
2671	case 0:
2672	*ppPageHeader = &pPages->ManufacturingPage0.u.fields.Header;
2673	*ppbPageData = pPages->ManufacturingPage0.u.abPageData;
2674	*pcbPage = sizeof(pPages->ManufacturingPage0);
2675	break;
2676	case 1:
2677	*ppPageHeader = &pPages->ManufacturingPage1.u.fields.Header;
2678	*ppbPageData = pPages->ManufacturingPage1.u.abPageData;
2679	*pcbPage = sizeof(pPages->ManufacturingPage1);
2680	break;
2681	case 2:
2682	*ppPageHeader = &pPages->ManufacturingPage2.u.fields.Header;
2683	*ppbPageData = pPages->ManufacturingPage2.u.abPageData;
2684	*pcbPage = sizeof(pPages->ManufacturingPage2);
2685	break;
2686	case 3:
2687	*ppPageHeader = &pPages->ManufacturingPage3.u.fields.Header;
2688	*ppbPageData = pPages->ManufacturingPage3.u.abPageData;
2689	*pcbPage = sizeof(pPages->ManufacturingPage3);
2690	break;
2691	case 4:
2692	*ppPageHeader = &pPages->ManufacturingPage4.u.fields.Header;
2693	*ppbPageData = pPages->ManufacturingPage4.u.abPageData;
2694	*pcbPage = sizeof(pPages->ManufacturingPage4);
2695	break;
2696	case 5:
2697	*ppPageHeader = &pPages->ManufacturingPage5.u.fields.Header;
2698	*ppbPageData = pPages->ManufacturingPage5.u.abPageData;
2699	*pcbPage = sizeof(pPages->ManufacturingPage5);
2700	break;
2701	case 6:
2702	*ppPageHeader = &pPages->ManufacturingPage6.u.fields.Header;
2703	*ppbPageData = pPages->ManufacturingPage6.u.abPageData;
2704	*pcbPage = sizeof(pPages->ManufacturingPage6);
2705	break;
2706	case 7:
2707	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
2708	{
2709	*ppPageHeader = &pPages->u.SasPages.pManufacturingPage7->u.fields.Header;
2710	*ppbPageData = pPages->u.SasPages.pManufacturingPage7->u.abPageData;
2711	*pcbPage = pPages->u.SasPages.cbManufacturingPage7;
2712	}
2713	else
2714	rc = VERR_NOT_FOUND;
2715	break;
2716	case 8:
2717	*ppPageHeader = &pPages->ManufacturingPage8.u.fields.Header;
2718	*ppbPageData = pPages->ManufacturingPage8.u.abPageData;
2719	*pcbPage = sizeof(pPages->ManufacturingPage8);
2720	break;
2721	case 9:
2722	*ppPageHeader = &pPages->ManufacturingPage9.u.fields.Header;
2723	*ppbPageData = pPages->ManufacturingPage9.u.abPageData;
2724	*pcbPage = sizeof(pPages->ManufacturingPage9);
2725	break;
2726	case 10:
2727	*ppPageHeader = &pPages->ManufacturingPage10.u.fields.Header;
2728	*ppbPageData = pPages->ManufacturingPage10.u.abPageData;
2729	*pcbPage = sizeof(pPages->ManufacturingPage10);
2730	break;
2731	default:
2732	rc = VERR_NOT_FOUND;
2733	}
2734
2735	return rc;
2736	}
2737
2738	/**
2739	* Return the configuration page header and data
2740	* which matches the given page type and number.
2741	*
2742	* @returns VINF_SUCCESS if successful
2743	* VERR_NOT_FOUND if the requested page could be found.
2744	* @param pThis Pointer to the shared LsiLogic device state. data.
2745	* @param pPages The pages supported by the controller.
2746	* @param u8PageNumber Number of the page to get.
2747	* @param ppPageHeader Where to store the pointer to the page header.
2748	* @param ppbPageData Where to store the pointer to the page data.
2749	* @param pcbPage Where to store the size of the page data in bytes on success.
2750	*/
2751	static int lsilogicR3ConfigurationBiosPageGetFromNumber(PLSILOGICSCSI pThis,
2752	PMptConfigurationPagesSupported pPages,
2753	uint8_t u8PageNumber,
2754	PMptConfigurationPageHeader *ppPageHeader,
2755	uint8_t *ppbPageData, size_t pcbPage)
2756	{
2757	RT_NOREF(pThis);
2758	int rc = VINF_SUCCESS;
2759
2760	AssertPtr(ppPageHeader); Assert(ppbPageData);
2761
2762	switch (u8PageNumber)
2763	{
2764	case 1:
2765	*ppPageHeader = &pPages->BIOSPage1.u.fields.Header;
2766	*ppbPageData = pPages->BIOSPage1.u.abPageData;
2767	*pcbPage = sizeof(pPages->BIOSPage1);
2768	break;
2769	case 2:
2770	*ppPageHeader = &pPages->BIOSPage2.u.fields.Header;
2771	*ppbPageData = pPages->BIOSPage2.u.abPageData;
2772	*pcbPage = sizeof(pPages->BIOSPage2);
2773	break;
2774	case 4:
2775	*ppPageHeader = &pPages->BIOSPage4.u.fields.Header;
2776	*ppbPageData = pPages->BIOSPage4.u.abPageData;
2777	*pcbPage = sizeof(pPages->BIOSPage4);
2778	break;
2779	default:
2780	rc = VERR_NOT_FOUND;
2781	}
2782
2783	return rc;
2784	}
2785
2786	/**
2787	* Return the configuration page header and data
2788	* which matches the given page type and number.
2789	*
2790	* @returns VINF_SUCCESS if successful
2791	* VERR_NOT_FOUND if the requested page could be found.
2792	* @param pThis Pointer to the shared LsiLogic device state. data.
2793	* @param pPages The pages supported by the controller.
2794	* @param u8Port The port to retrieve the page for.
2795	* @param u8PageNumber Number of the page to get.
2796	* @param ppPageHeader Where to store the pointer to the page header.
2797	* @param ppbPageData Where to store the pointer to the page data.
2798	* @param pcbPage Where to store the size of the page data in bytes on success.
2799	*/
2800	static int lsilogicR3ConfigurationSCSISPIPortPageGetFromNumber(PLSILOGICSCSI pThis,
2801	PMptConfigurationPagesSupported pPages,
2802	uint8_t u8Port,
2803	uint8_t u8PageNumber,
2804	PMptConfigurationPageHeader *ppPageHeader,
2805	uint8_t *ppbPageData, size_t pcbPage)
2806	{
2807	RT_NOREF(pThis);
2808	int rc = VINF_SUCCESS;
2809	AssertPtr(ppPageHeader); Assert(ppbPageData);
2810
2811
2812	if (u8Port >= RT_ELEMENTS(pPages->u.SpiPages.aPortPages))
2813	return VERR_NOT_FOUND;
2814
2815	switch (u8PageNumber)
2816	{
2817	case 0:
2818	*ppPageHeader = &pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage0.u.fields.Header;
2819	*ppbPageData = pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage0.u.abPageData;
2820	*pcbPage = sizeof(pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage0);
2821	break;
2822	case 1:
2823	*ppPageHeader = &pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage1.u.fields.Header;
2824	*ppbPageData = pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage1.u.abPageData;
2825	*pcbPage = sizeof(pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage1);
2826	break;
2827	case 2:
2828	*ppPageHeader = &pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage2.u.fields.Header;
2829	*ppbPageData = pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage2.u.abPageData;
2830	*pcbPage = sizeof(pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage2);
2831	break;
2832	default:
2833	rc = VERR_NOT_FOUND;
2834	}
2835
2836	return rc;
2837	}
2838
2839	/**
2840	* Return the configuration page header and data
2841	* which matches the given page type and number.
2842	*
2843	* @returns VINF_SUCCESS if successful
2844	* VERR_NOT_FOUND if the requested page could be found.
2845	* @param pThis Pointer to the shared LsiLogic device state. data.
2846	* @param pPages The pages supported by the controller.
2847	* @param u8Bus The bus the device is on the page should be returned.
2848	* @param u8TargetID The target ID of the device to return the page for.
2849	* @param u8PageNumber Number of the page to get.
2850	* @param ppPageHeader Where to store the pointer to the page header.
2851	* @param ppbPageData Where to store the pointer to the page data.
2852	* @param pcbPage Where to store the size of the page data in bytes on success.
2853	*/
2854	static int lsilogicR3ConfigurationSCSISPIDevicePageGetFromNumber(PLSILOGICSCSI pThis,
2855	PMptConfigurationPagesSupported pPages,
2856	uint8_t u8Bus,
2857	uint8_t u8TargetID, uint8_t u8PageNumber,
2858	PMptConfigurationPageHeader *ppPageHeader,
2859	uint8_t *ppbPageData, size_t pcbPage)
2860	{
2861	RT_NOREF(pThis);
2862	int rc = VINF_SUCCESS;
2863	AssertPtr(ppPageHeader); Assert(ppbPageData);
2864
2865	if (u8Bus >= RT_ELEMENTS(pPages->u.SpiPages.aBuses))
2866	return VERR_NOT_FOUND;
2867
2868	if (u8TargetID >= RT_ELEMENTS(pPages->u.SpiPages.aBuses[u8Bus].aDevicePages))
2869	return VERR_NOT_FOUND;
2870
2871	switch (u8PageNumber)
2872	{
2873	case 0:
2874	*ppPageHeader = &pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage0.u.fields.Header;
2875	*ppbPageData = pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage0.u.abPageData;
2876	*pcbPage = sizeof(pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage0);
2877	break;
2878	case 1:
2879	*ppPageHeader = &pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage1.u.fields.Header;
2880	*ppbPageData = pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage1.u.abPageData;
2881	*pcbPage = sizeof(pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage1);
2882	break;
2883	case 2:
2884	*ppPageHeader = &pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage2.u.fields.Header;
2885	*ppbPageData = pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage2.u.abPageData;
2886	*pcbPage = sizeof(pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage2);
2887	break;
2888	case 3:
2889	*ppPageHeader = &pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage3.u.fields.Header;
2890	*ppbPageData = pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage3.u.abPageData;
2891	*pcbPage = sizeof(pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage3);
2892	break;
2893	default:
2894	rc = VERR_NOT_FOUND;
2895	}
2896
2897	return rc;
2898	}
2899
2900	static int lsilogicR3ConfigurationSASIOUnitPageGetFromNumber(PMptConfigurationPagesSupported pPages,
2901	uint8_t u8PageNumber,
2902	PMptExtendedConfigurationPageHeader *ppPageHeader,
2903	uint8_t *ppbPageData, size_t pcbPage)
2904	{
2905	int rc = VINF_SUCCESS;
2906
2907	switch (u8PageNumber)
2908	{
2909	case 0:
2910	*ppPageHeader = &pPages->u.SasPages.pSASIOUnitPage0->u.fields.ExtHeader;
2911	*ppbPageData = pPages->u.SasPages.pSASIOUnitPage0->u.abPageData;
2912	*pcbPage = pPages->u.SasPages.cbSASIOUnitPage0;
2913	break;
2914	case 1:
2915	*ppPageHeader = &pPages->u.SasPages.pSASIOUnitPage1->u.fields.ExtHeader;
2916	*ppbPageData = pPages->u.SasPages.pSASIOUnitPage1->u.abPageData;
2917	*pcbPage = pPages->u.SasPages.cbSASIOUnitPage1;
2918	break;
2919	case 2:
2920	*ppPageHeader = &pPages->u.SasPages.SASIOUnitPage2.u.fields.ExtHeader;
2921	*ppbPageData = pPages->u.SasPages.SASIOUnitPage2.u.abPageData;
2922	*pcbPage = sizeof(pPages->u.SasPages.SASIOUnitPage2);
2923	break;
2924	case 3:
2925	*ppPageHeader = &pPages->u.SasPages.SASIOUnitPage3.u.fields.ExtHeader;
2926	*ppbPageData = pPages->u.SasPages.SASIOUnitPage3.u.abPageData;
2927	*pcbPage = sizeof(pPages->u.SasPages.SASIOUnitPage3);
2928	break;
2929	default:
2930	rc = VERR_NOT_FOUND;
2931	}
2932
2933	return rc;
2934	}
2935
2936	static int lsilogicR3ConfigurationSASPHYPageGetFromNumber(PMptConfigurationPagesSupported pPages,
2937	uint8_t u8PageNumber,
2938	MptConfigurationPageAddress PageAddress,
2939	PMptExtendedConfigurationPageHeader *ppPageHeader,
2940	uint8_t *ppbPageData, size_t pcbPage)
2941	{
2942	int rc = VINF_SUCCESS;
2943	uint8_t uAddressForm = MPT_CONFIGURATION_PAGE_ADDRESS_GET_SAS_FORM(PageAddress);
2944	PMptConfigurationPagesSas pPagesSas = &pPages->u.SasPages;
2945	PMptPHY pPHYPages = NULL;
2946
2947	Log(("Address form %d\n", uAddressForm));
2948
2949	if (uAddressForm == 0) /* PHY number */
2950	{
2951	uint8_t u8PhyNumber = PageAddress.SASPHY.Form0.u8PhyNumber;
2952
2953	Log(("PHY number %d\n", u8PhyNumber));
2954
2955	if (u8PhyNumber >= pPagesSas->cPHYs)
2956	return VERR_NOT_FOUND;
2957
2958	pPHYPages = &pPagesSas->paPHYs[u8PhyNumber];
2959	}
2960	else if (uAddressForm == 1) /* Index form */
2961	{
2962	uint16_t u16Index = PageAddress.SASPHY.Form1.u16Index;
2963
2964	Log(("PHY index %d\n", u16Index));
2965
2966	if (u16Index >= pPagesSas->cPHYs)
2967	return VERR_NOT_FOUND;
2968
2969	pPHYPages = &pPagesSas->paPHYs[u16Index];
2970	}
2971	else
2972	rc = VERR_NOT_FOUND; /* Correct? */
2973
2974	if (pPHYPages)
2975	{
2976	switch (u8PageNumber)
2977	{
2978	case 0:
2979	*ppPageHeader = &pPHYPages->SASPHYPage0.u.fields.ExtHeader;
2980	*ppbPageData = pPHYPages->SASPHYPage0.u.abPageData;
2981	*pcbPage = sizeof(pPHYPages->SASPHYPage0);
2982	break;
2983	case 1:
2984	*ppPageHeader = &pPHYPages->SASPHYPage1.u.fields.ExtHeader;
2985	*ppbPageData = pPHYPages->SASPHYPage1.u.abPageData;
2986	*pcbPage = sizeof(pPHYPages->SASPHYPage1);
2987	break;
2988	default:
2989	rc = VERR_NOT_FOUND;
2990	}
2991	}
2992	else
2993	rc = VERR_NOT_FOUND;
2994
2995	return rc;
2996	}
2997
2998	static int lsilogicR3ConfigurationSASDevicePageGetFromNumber(PMptConfigurationPagesSupported pPages,
2999	uint8_t u8PageNumber,
3000	MptConfigurationPageAddress PageAddress,
3001	PMptExtendedConfigurationPageHeader *ppPageHeader,
3002	uint8_t *ppbPageData, size_t pcbPage)
3003	{
3004	int rc = VINF_SUCCESS;
3005	uint8_t uAddressForm = MPT_CONFIGURATION_PAGE_ADDRESS_GET_SAS_FORM(PageAddress);
3006	PMptConfigurationPagesSas pPagesSas = &pPages->u.SasPages;
3007	PMptSASDevice pSASDevice = NULL;
3008
3009	Log(("Address form %d\n", uAddressForm));
3010
3011	if (uAddressForm == 0)
3012	{
3013	uint16_t u16Handle = PageAddress.SASDevice.Form0And2.u16Handle;
3014
3015	Log(("Get next handle %#x\n", u16Handle));
3016
3017	pSASDevice = pPagesSas->pSASDeviceHead;
3018
3019	/* Get the first device? */
3020	if (u16Handle != 0xffff)
3021	{
3022	/* No, search for the right one. */
3023
3024	while ( pSASDevice
3025	&& pSASDevice->SASDevicePage0.u.fields.u16DevHandle != u16Handle)
3026	pSASDevice = pSASDevice->pNext;
3027
3028	if (pSASDevice)
3029	pSASDevice = pSASDevice->pNext;
3030	}
3031	}
3032	else if (uAddressForm == 1)
3033	{
3034	uint8_t u8TargetID = PageAddress.SASDevice.Form1.u8TargetID;
3035	uint8_t u8Bus = PageAddress.SASDevice.Form1.u8Bus;
3036
3037	Log(("u8TargetID=%d u8Bus=%d\n", u8TargetID, u8Bus));
3038
3039	pSASDevice = pPagesSas->pSASDeviceHead;
3040
3041	while ( pSASDevice
3042	&& ( pSASDevice->SASDevicePage0.u.fields.u8TargetID != u8TargetID
3043	\|\| pSASDevice->SASDevicePage0.u.fields.u8Bus != u8Bus))
3044	pSASDevice = pSASDevice->pNext;
3045	}
3046	else if (uAddressForm == 2)
3047	{
3048	uint16_t u16Handle = PageAddress.SASDevice.Form0And2.u16Handle;
3049
3050	Log(("Handle %#x\n", u16Handle));
3051
3052	pSASDevice = pPagesSas->pSASDeviceHead;
3053
3054	while ( pSASDevice
3055	&& pSASDevice->SASDevicePage0.u.fields.u16DevHandle != u16Handle)
3056	pSASDevice = pSASDevice->pNext;
3057	}
3058
3059	if (pSASDevice)
3060	{
3061	switch (u8PageNumber)
3062	{
3063	case 0:
3064	*ppPageHeader = &pSASDevice->SASDevicePage0.u.fields.ExtHeader;
3065	*ppbPageData = pSASDevice->SASDevicePage0.u.abPageData;
3066	*pcbPage = sizeof(pSASDevice->SASDevicePage0);
3067	break;
3068	case 1:
3069	*ppPageHeader = &pSASDevice->SASDevicePage1.u.fields.ExtHeader;
3070	*ppbPageData = pSASDevice->SASDevicePage1.u.abPageData;
3071	*pcbPage = sizeof(pSASDevice->SASDevicePage1);
3072	break;
3073	case 2:
3074	*ppPageHeader = &pSASDevice->SASDevicePage2.u.fields.ExtHeader;
3075	*ppbPageData = pSASDevice->SASDevicePage2.u.abPageData;
3076	*pcbPage = sizeof(pSASDevice->SASDevicePage2);
3077	break;
3078	default:
3079	rc = VERR_NOT_FOUND;
3080	}
3081	}
3082	else
3083	rc = VERR_NOT_FOUND;
3084
3085	return rc;
3086	}
3087
3088	/**
3089	* Returns the extended configuration page header and data.
3090	* @returns VINF_SUCCESS if successful
3091	* VERR_NOT_FOUND if the requested page could be found.
3092	* @param pThisCC Pointer to the ring-3 LsiLogic device state.
3093	* @param pConfigurationReq The configuration request.
3094	* @param ppPageHeader Where to return the pointer to the page header on success.
3095	* @param ppbPageData Where to store the pointer to the page data.
3096	* @param pcbPage Where to store the size of the page in bytes.
3097	*/
3098	static int lsilogicR3ConfigurationPageGetExtended(PLSILOGICSCSICC pThisCC, PMptConfigurationRequest pConfigurationReq,
3099	PMptExtendedConfigurationPageHeader *ppPageHeader,
3100	uint8_t *ppbPageData, size_t pcbPage)
3101	{
3102	int rc = VINF_SUCCESS;
3103
3104	Log(("Extended page requested:\n"));
3105	Log(("u8ExtPageType=%#x\n", pConfigurationReq->u8ExtPageType));
3106	Log(("u8ExtPageLength=%d\n", pConfigurationReq->u16ExtPageLength));
3107
3108	switch (pConfigurationReq->u8ExtPageType)
3109	{
3110	case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT:
3111	{
3112	rc = lsilogicR3ConfigurationSASIOUnitPageGetFromNumber(pThisCC->pConfigurationPages,
3113	pConfigurationReq->u8PageNumber,
3114	ppPageHeader, ppbPageData, pcbPage);
3115	break;
3116	}
3117	case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASPHYS:
3118	{
3119	rc = lsilogicR3ConfigurationSASPHYPageGetFromNumber(pThisCC->pConfigurationPages,
3120	pConfigurationReq->u8PageNumber,
3121	pConfigurationReq->PageAddress,
3122	ppPageHeader, ppbPageData, pcbPage);
3123	break;
3124	}
3125	case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASDEVICE:
3126	{
3127	rc = lsilogicR3ConfigurationSASDevicePageGetFromNumber(pThisCC->pConfigurationPages,
3128	pConfigurationReq->u8PageNumber,
3129	pConfigurationReq->PageAddress,
3130	ppPageHeader, ppbPageData, pcbPage);
3131	break;
3132	}
3133	case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASEXPANDER: /* No expanders supported */
3134	case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_ENCLOSURE: /* No enclosures supported */
3135	default:
3136	rc = VERR_NOT_FOUND;
3137	}
3138
3139	return rc;
3140	}
3141
3142	/**
3143	* Processes a Configuration request.
3144	*
3145	* @returns VBox status code.
3146	* @param pDevIns The device instance.
3147	* @param pThis Pointer to the shared LsiLogic device state.
3148	* @param pThisCC Pointer to the ring-3 LsiLogic device state.
3149	* @param pConfigurationReq Pointer to the request structure.
3150	* @param pReply Pointer to the reply message frame
3151	*/
3152	static int lsilogicR3ProcessConfigurationRequest(PPDMDEVINS pDevIns, PLSILOGICSCSI pThis, PLSILOGICSCSICC pThisCC,
3153	PMptConfigurationRequest pConfigurationReq, PMptConfigurationReply pReply)
3154	{
3155	int rc = VINF_SUCCESS;
3156	uint8_t *pbPageData = NULL;
3157	PMptConfigurationPageHeader pPageHeader = NULL;
3158	PMptExtendedConfigurationPageHeader pExtPageHeader = NULL;
3159	uint8_t u8PageType;
3160	uint8_t u8PageAttribute;
3161	size_t cbPage = 0;
3162
3163	LogFlowFunc(("pThis=%#p\n", pThis));
3164
3165	u8PageType = MPT_CONFIGURATION_PAGE_TYPE_GET(pConfigurationReq->u8PageType);
3166	u8PageAttribute = MPT_CONFIGURATION_PAGE_ATTRIBUTE_GET(pConfigurationReq->u8PageType);
3167
3168	Log(("GuestRequest:\n"));
3169	Log(("u8Action=%#x\n", pConfigurationReq->u8Action));
3170	Log(("u8PageType=%#x\n", u8PageType));
3171	Log(("u8PageNumber=%d\n", pConfigurationReq->u8PageNumber));
3172	Log(("u8PageLength=%d\n", pConfigurationReq->u8PageLength));
3173	Log(("u8PageVersion=%d\n", pConfigurationReq->u8PageVersion));
3174
3175	/* Copy common bits from the request into the reply. */
3176	pReply->u8MessageLength = 6; /* 6 32bit D-Words. */
3177	pReply->u8Action = pConfigurationReq->u8Action;
3178	pReply->u8Function = pConfigurationReq->u8Function;
3179	pReply->u32MessageContext = pConfigurationReq->u32MessageContext;
3180
3181	switch (u8PageType)
3182	{
3183	case MPT_CONFIGURATION_PAGE_TYPE_IO_UNIT:
3184	{
3185	/* Get the page data. */
3186	rc = lsilogicR3ConfigurationIOUnitPageGetFromNumber(pThis,
3187	pThisCC->pConfigurationPages,
3188	pConfigurationReq->u8PageNumber,
3189	&pPageHeader, &pbPageData, &cbPage);
3190	break;
3191	}
3192	case MPT_CONFIGURATION_PAGE_TYPE_IOC:
3193	{
3194	/* Get the page data. */
3195	rc = lsilogicR3ConfigurationIOCPageGetFromNumber(pThis,
3196	pThisCC->pConfigurationPages,
3197	pConfigurationReq->u8PageNumber,
3198	&pPageHeader, &pbPageData, &cbPage);
3199	break;
3200	}
3201	case MPT_CONFIGURATION_PAGE_TYPE_MANUFACTURING:
3202	{
3203	/* Get the page data. */
3204	rc = lsilogicR3ConfigurationManufacturingPageGetFromNumber(pThis,
3205	pThisCC->pConfigurationPages,
3206	pConfigurationReq->u8PageNumber,
3207	&pPageHeader, &pbPageData, &cbPage);
3208	break;
3209	}
3210	case MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_PORT:
3211	{
3212	/* Get the page data. */
3213	rc = lsilogicR3ConfigurationSCSISPIPortPageGetFromNumber(pThis,
3214	pThisCC->pConfigurationPages,
3215	pConfigurationReq->PageAddress.MPIPortNumber.u8PortNumber,
3216	pConfigurationReq->u8PageNumber,
3217	&pPageHeader, &pbPageData, &cbPage);
3218	break;
3219	}
3220	case MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE:
3221	{
3222	/* Get the page data. */
3223	rc = lsilogicR3ConfigurationSCSISPIDevicePageGetFromNumber(pThis,
3224	pThisCC->pConfigurationPages,
3225	pConfigurationReq->PageAddress.BusAndTargetId.u8Bus,
3226	pConfigurationReq->PageAddress.BusAndTargetId.u8TargetID,
3227	pConfigurationReq->u8PageNumber,
3228	&pPageHeader, &pbPageData, &cbPage);
3229	break;
3230	}
3231	case MPT_CONFIGURATION_PAGE_TYPE_BIOS:
3232	{
3233	rc = lsilogicR3ConfigurationBiosPageGetFromNumber(pThis,
3234	pThisCC->pConfigurationPages,
3235	pConfigurationReq->u8PageNumber,
3236	&pPageHeader, &pbPageData, &cbPage);
3237	break;
3238	}
3239	case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED:
3240	{
3241	rc = lsilogicR3ConfigurationPageGetExtended(pThisCC,
3242	pConfigurationReq,
3243	&pExtPageHeader, &pbPageData, &cbPage);
3244	break;
3245	}
3246	default:
3247	rc = VERR_NOT_FOUND;
3248	}
3249
3250	if (rc == VERR_NOT_FOUND)
3251	{
3252	Log(("Page not found\n"));
3253	pReply->u8PageType = pConfigurationReq->u8PageType;
3254	pReply->u8PageNumber = pConfigurationReq->u8PageNumber;
3255	pReply->u8PageLength = pConfigurationReq->u8PageLength;
3256	pReply->u8PageVersion = pConfigurationReq->u8PageVersion;
3257	pReply->u16IOCStatus = MPT_IOCSTATUS_CONFIG_INVALID_PAGE;
3258	return VINF_SUCCESS;
3259	}
3260
3261	if (u8PageType == MPT_CONFIGURATION_PAGE_TYPE_EXTENDED)
3262	{
3263	pReply->u8PageType = pExtPageHeader->u8PageType;
3264	pReply->u8PageNumber = pExtPageHeader->u8PageNumber;
3265	pReply->u8PageVersion = pExtPageHeader->u8PageVersion;
3266	pReply->u8ExtPageType = pExtPageHeader->u8ExtPageType;
3267	pReply->u16ExtPageLength = pExtPageHeader->u16ExtPageLength;
3268
3269	for (int i = 0; i < pExtPageHeader->u16ExtPageLength; i++)
3270	LogFlowFunc(("PageData[%d]=%#x\n", i, ((uint32_t *)pbPageData)[i]));
3271	}
3272	else
3273	{
3274	pReply->u8PageType = pPageHeader->u8PageType;
3275	pReply->u8PageNumber = pPageHeader->u8PageNumber;
3276	pReply->u8PageLength = pPageHeader->u8PageLength;
3277	pReply->u8PageVersion = pPageHeader->u8PageVersion;
3278
3279	for (int i = 0; i < pReply->u8PageLength; i++)
3280	LogFlowFunc(("PageData[%d]=%#x\n", i, ((uint32_t *)pbPageData)[i]));
3281	}
3282
3283	/*
3284	* Don't use the scatter gather handling code as the configuration request always have only one
3285	* simple element.
3286	*/
3287	switch (pConfigurationReq->u8Action)
3288	{
3289	case MPT_CONFIGURATION_REQUEST_ACTION_DEFAULT: /* Nothing to do. We are always using the defaults. */
3290	case MPT_CONFIGURATION_REQUEST_ACTION_HEADER:
3291	{
3292	/* Already copied above nothing to do. */
3293	break;
3294	}
3295	case MPT_CONFIGURATION_REQUEST_ACTION_READ_NVRAM:
3296	case MPT_CONFIGURATION_REQUEST_ACTION_READ_CURRENT:
3297	case MPT_CONFIGURATION_REQUEST_ACTION_READ_DEFAULT:
3298	{
3299	uint32_t cbBuffer = pConfigurationReq->SimpleSGElement.u24Length;
3300	if (cbBuffer != 0)
3301	{
3302	RTGCPHYS GCPhysAddrPageBuffer = pConfigurationReq->SimpleSGElement.u32DataBufferAddressLow;
3303	if (pConfigurationReq->SimpleSGElement.f64BitAddress)
3304	GCPhysAddrPageBuffer \|= (uint64_t)pConfigurationReq->SimpleSGElement.u32DataBufferAddressHigh << 32;
3305
3306	PDMDevHlpPCIPhysWriteMeta(pDevIns, GCPhysAddrPageBuffer, pbPageData, RT_MIN(cbBuffer, cbPage));
3307	}
3308	break;
3309	}
3310	case MPT_CONFIGURATION_REQUEST_ACTION_WRITE_CURRENT:
3311	case MPT_CONFIGURATION_REQUEST_ACTION_WRITE_NVRAM:
3312	{
3313	uint32_t cbBuffer = pConfigurationReq->SimpleSGElement.u24Length;
3314	if (cbBuffer != 0)
3315	{
3316	RTGCPHYS GCPhysAddrPageBuffer = pConfigurationReq->SimpleSGElement.u32DataBufferAddressLow;
3317	if (pConfigurationReq->SimpleSGElement.f64BitAddress)
3318	GCPhysAddrPageBuffer \|= (uint64_t)pConfigurationReq->SimpleSGElement.u32DataBufferAddressHigh << 32;
3319
3320	LogFlow(("cbBuffer=%u cbPage=%u\n", cbBuffer, cbPage));
3321
3322	PDMDevHlpPCIPhysReadMeta(pDevIns, GCPhysAddrPageBuffer, pbPageData, RT_MIN(cbBuffer, cbPage));
3323	}
3324	break;
3325	}
3326	default:
3327	AssertMsgFailed(("todo\n"));
3328	}
3329
3330	return VINF_SUCCESS;
3331	}
3332
3333	/**
3334	* Initializes the configuration pages for the SPI SCSI controller.
3335	*
3336	* @returns nothing
3337	* @param pThis Pointer to the shared LsiLogic device state.
3338	* @param pThisCC Pointer to the ring-3 LsiLogic device state.
3339	*/
3340	static void lsilogicR3InitializeConfigurationPagesSpi(PLSILOGICSCSI pThis, PLSILOGICSCSICC pThisCC)
3341	{
3342	PMptConfigurationPagesSpi pPages = &pThisCC->pConfigurationPages->u.SpiPages;
3343
3344	AssertMsg(pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI, ("Controller is not the SPI SCSI one\n"));
3345	LogFlowFunc(("pThis=%#p\n", pThis));
3346	RT_NOREF(pThis);
3347
3348	/* Clear everything first. */
3349	memset(pPages, 0, sizeof(MptConfigurationPagesSpi));
3350
3351	for (unsigned i = 0; i < RT_ELEMENTS(pPages->aPortPages); i++)
3352	{
3353	/* SCSI-SPI port page 0. */
3354	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3355	\| MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_PORT;
3356	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.Header.u8PageNumber = 0;
3357	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIPort0) / 4;
3358	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.fInformationUnitTransfersCapable = true;
3359	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.fDTCapable = true;
3360	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.fQASCapable = true;
3361	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.u8MinimumSynchronousTransferPeriod = 0;
3362	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.u8MaximumSynchronousOffset = 0xff;
3363	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.fWide = true;
3364	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.fAIPCapable = true;
3365	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.u2SignalingType = 0x3; /* Single Ended. */
3366
3367	/* SCSI-SPI port page 1. */
3368	pPages->aPortPages[i].SCSISPIPortPage1.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE
3369	\| MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_PORT;
3370	pPages->aPortPages[i].SCSISPIPortPage1.u.fields.Header.u8PageNumber = 1;
3371	pPages->aPortPages[i].SCSISPIPortPage1.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIPort1) / 4;
3372	pPages->aPortPages[i].SCSISPIPortPage1.u.fields.u8SCSIID = 7;
3373	pPages->aPortPages[i].SCSISPIPortPage1.u.fields.u16PortResponseIDsBitmask = (1 << 7);
3374	pPages->aPortPages[i].SCSISPIPortPage1.u.fields.u32OnBusTimerValue = 0;
3375
3376	/* SCSI-SPI port page 2. */
3377	pPages->aPortPages[i].SCSISPIPortPage2.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE
3378	\| MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_PORT;
3379	pPages->aPortPages[i].SCSISPIPortPage2.u.fields.Header.u8PageNumber = 2;
3380	pPages->aPortPages[i].SCSISPIPortPage2.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIPort2) / 4;
3381	pPages->aPortPages[i].SCSISPIPortPage2.u.fields.u4HostSCSIID = 7;
3382	pPages->aPortPages[i].SCSISPIPortPage2.u.fields.u2InitializeHBA = 0x3;
3383	pPages->aPortPages[i].SCSISPIPortPage2.u.fields.fTerminationDisabled = true;
3384	for (unsigned iDevice = 0; iDevice < RT_ELEMENTS(pPages->aPortPages[i].SCSISPIPortPage2.u.fields.aDeviceSettings); iDevice++)
3385	{
3386	pPages->aPortPages[i].SCSISPIPortPage2.u.fields.aDeviceSettings[iDevice].fBootChoice = true;
3387	}
3388	/* Everything else 0 for now. */
3389	}
3390
3391	for (unsigned uBusCurr = 0; uBusCurr < RT_ELEMENTS(pPages->aBuses); uBusCurr++)
3392	{
3393	for (unsigned uDeviceCurr = 0; uDeviceCurr < RT_ELEMENTS(pPages->aBuses[uBusCurr].aDevicePages); uDeviceCurr++)
3394	{
3395	/* SCSI-SPI device page 0. */
3396	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage0.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3397	\| MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE;
3398	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage0.u.fields.Header.u8PageNumber = 0;
3399	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage0.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIDevice0) / 4;
3400	/* Everything else 0 for now. */
3401
3402	/* SCSI-SPI device page 1. */
3403	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage1.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE
3404	\| MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE;
3405	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage1.u.fields.Header.u8PageNumber = 1;
3406	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage1.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIDevice1) / 4;
3407	/* Everything else 0 for now. */
3408
3409	/* SCSI-SPI device page 2. */
3410	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage2.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE
3411	\| MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE;
3412	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage2.u.fields.Header.u8PageNumber = 2;
3413	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage2.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIDevice2) / 4;
3414	/* Everything else 0 for now. */
3415
3416	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage3.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3417	\| MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE;
3418	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage3.u.fields.Header.u8PageNumber = 3;
3419	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage3.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIDevice3) / 4;
3420	/* Everything else 0 for now. */
3421	}
3422	}
3423	}
3424
3425	/**
3426	* Generates a handle.
3427	*
3428	* @returns the handle.
3429	* @param pThis Pointer to the shared LsiLogic device state.
3430	*/
3431	DECLINLINE(uint16_t) lsilogicGetHandle(PLSILOGICSCSI pThis)
3432	{
3433	uint16_t u16Handle = pThis->u16NextHandle++;
3434	return u16Handle;
3435	}
3436
3437	/**
3438	* Generates a SAS address (WWID)
3439	*
3440	* @returns nothing.
3441	* @param pSASAddress Pointer to an unitialised SAS address.
3442	* @param iId iId which will go into the address.
3443	*
3444	* @todo Generate better SAS addresses. (Request a block from SUN probably)
3445	*/
3446	void lsilogicSASAddressGenerate(PSASADDRESS pSASAddress, unsigned iId)
3447	{
3448	pSASAddress->u8Address[0] = (0x5 << 5);
3449	pSASAddress->u8Address[1] = 0x01;
3450	pSASAddress->u8Address[2] = 0x02;
3451	pSASAddress->u8Address[3] = 0x03;
3452	pSASAddress->u8Address[4] = 0x04;
3453	pSASAddress->u8Address[5] = 0x05;
3454	pSASAddress->u8Address[6] = 0x06;
3455	pSASAddress->u8Address[7] = iId;
3456	}
3457
3458	/**
3459	* Initializes the configuration pages for the SAS SCSI controller.
3460	*
3461	* @returns nothing
3462	* @param pThis Pointer to the shared LsiLogic device state.
3463	* @param pThisCC Pointer to the ring-3 LsiLogic device state.
3464	*/
3465	static void lsilogicR3InitializeConfigurationPagesSas(PLSILOGICSCSI pThis, PLSILOGICSCSICC pThisCC)
3466	{
3467	PMptConfigurationPagesSas pPages = &pThisCC->pConfigurationPages->u.SasPages;
3468
3469	AssertMsg(pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS, ("Controller is not the SAS SCSI one\n"));
3470
3471	LogFlowFunc(("pThis=%#p\n", pThis));
3472
3473	/* Manufacturing Page 7 - Connector settings. */
3474	PMptConfigurationPageManufacturing7 pManufacturingPage7 = pPages->pManufacturingPage7;
3475	AssertPtr(pManufacturingPage7);
3476
3477	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(pManufacturingPage7,
3478	0, 7,
3479	MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3480	/* Set size manually. */
3481	if (pPages->cbManufacturingPage7 / 4 > 255)
3482	pManufacturingPage7->u.fields.Header.u8PageLength = 255;
3483	else
3484	pManufacturingPage7->u.fields.Header.u8PageLength = pPages->cbManufacturingPage7 / 4;
3485	pManufacturingPage7->u.fields.u8NumPhys = pThis->cPorts;
3486
3487	/* SAS I/O unit page 0 - Port specific information. */
3488	PMptConfigurationPageSASIOUnit0 pSASPage0 = pPages->pSASIOUnitPage0;
3489	AssertPtr(pSASPage0);
3490
3491	MPT_CONFIG_EXTENDED_PAGE_HEADER_INIT(pSASPage0, pPages->cbSASIOUnitPage0,
3492	0, MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY,
3493	MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT);
3494	pSASPage0->u.fields.u8NumPhys = pThis->cPorts;
3495	pPages->pSASIOUnitPage0 = pSASPage0;
3496
3497	/* SAS I/O unit page 1 - Port specific settings. */
3498	PMptConfigurationPageSASIOUnit1 pSASPage1 = pPages->pSASIOUnitPage1;
3499	AssertPtr(pSASPage1);
3500
3501	MPT_CONFIG_EXTENDED_PAGE_HEADER_INIT(pSASPage1, pPages->cbSASIOUnitPage1,
3502	1, MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE,
3503	MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT);
3504	pSASPage1->u.fields.u8NumPhys = pSASPage0->u.fields.u8NumPhys;
3505	pSASPage1->u.fields.u16ControlFlags = 0;
3506	pSASPage1->u.fields.u16AdditionalControlFlags = 0;
3507
3508	/* SAS I/O unit page 2 - Port specific information. */
3509	pPages->SASIOUnitPage2.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3510	\| MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3511	pPages->SASIOUnitPage2.u.fields.ExtHeader.u8PageNumber = 2;
3512	pPages->SASIOUnitPage2.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT;
3513	pPages->SASIOUnitPage2.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASIOUnit2) / 4;
3514
3515	/* SAS I/O unit page 3 - Port specific information. */
3516	pPages->SASIOUnitPage3.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3517	\| MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3518	pPages->SASIOUnitPage3.u.fields.ExtHeader.u8PageNumber = 3;
3519	pPages->SASIOUnitPage3.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT;
3520	pPages->SASIOUnitPage3.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASIOUnit3) / 4;
3521
3522	Assert(pPages->cPHYs == pThis->cPorts);
3523	AssertPtr(pPages->paPHYs);
3524
3525	/* Initialize the PHY configuration */
3526	PMptSASDevice pSASDevice = pPages->pSASDeviceHead;
3527	for (unsigned i = 0; i < pThis->cPorts; i++)
3528	{
3529	PMptPHY pPHYPages = &pPages->paPHYs[i];
3530	uint16_t u16ControllerHandle = lsilogicGetHandle(pThis);
3531
3532	pManufacturingPage7->u.fields.aPHY[i].u8Location = LSILOGICSCSI_MANUFACTURING7_LOCATION_AUTO;
3533
3534	pSASPage0->u.fields.aPHY[i].u8Port = i;
3535	pSASPage0->u.fields.aPHY[i].u8PortFlags = 0;
3536	pSASPage0->u.fields.aPHY[i].u8PhyFlags = 0;
3537	pSASPage0->u.fields.aPHY[i].u8NegotiatedLinkRate = LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_FAILED;
3538	pSASPage0->u.fields.aPHY[i].u32ControllerPhyDeviceInfo = LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_SET(LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_NO);
3539	pSASPage0->u.fields.aPHY[i].u16ControllerDevHandle = u16ControllerHandle;
3540	pSASPage0->u.fields.aPHY[i].u16AttachedDevHandle = 0; /* No device attached. */
3541	pSASPage0->u.fields.aPHY[i].u32DiscoveryStatus = 0; /* No errors */
3542
3543	pSASPage1->u.fields.aPHY[i].u8Port = i;
3544	pSASPage1->u.fields.aPHY[i].u8PortFlags = 0;
3545	pSASPage1->u.fields.aPHY[i].u8PhyFlags = 0;
3546	pSASPage1->u.fields.aPHY[i].u8MaxMinLinkRate = LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MIN_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_15GB)
3547	\| LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MAX_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_30GB);
3548	pSASPage1->u.fields.aPHY[i].u32ControllerPhyDeviceInfo = LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_SET(LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_NO);
3549
3550	/* SAS PHY page 0. */
3551	pPHYPages->SASPHYPage0.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3552	\| MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3553	pPHYPages->SASPHYPage0.u.fields.ExtHeader.u8PageNumber = 0;
3554	pPHYPages->SASPHYPage0.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASPHYS;
3555	pPHYPages->SASPHYPage0.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASPHY0) / 4;
3556	pPHYPages->SASPHYPage0.u.fields.u8AttachedPhyIdentifier = i;
3557	pPHYPages->SASPHYPage0.u.fields.u32AttachedDeviceInfo = LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_SET(LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_NO);
3558	pPHYPages->SASPHYPage0.u.fields.u8ProgrammedLinkRate = LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MIN_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_15GB)
3559	\| LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MAX_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_30GB);
3560	pPHYPages->SASPHYPage0.u.fields.u8HwLinkRate = LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MIN_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_15GB)
3561	\| LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MAX_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_30GB);
3562
3563	/* SAS PHY page 1. */
3564	pPHYPages->SASPHYPage1.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3565	\| MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3566	pPHYPages->SASPHYPage1.u.fields.ExtHeader.u8PageNumber = 1;
3567	pPHYPages->SASPHYPage1.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASPHYS;
3568	pPHYPages->SASPHYPage1.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASPHY1) / 4;
3569
3570	/* Settings for present devices. */
3571	if (pThisCC->paDeviceStates[i].pDrvBase)
3572	{
3573	uint16_t u16DeviceHandle = lsilogicGetHandle(pThis);
3574	SASADDRESS SASAddress;
3575	AssertPtr(pSASDevice);
3576
3577	memset(&SASAddress, 0, sizeof(SASADDRESS));
3578	lsilogicSASAddressGenerate(&SASAddress, i);
3579
3580	pSASPage0->u.fields.aPHY[i].u8NegotiatedLinkRate = LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_SET(LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_30GB);
3581	pSASPage0->u.fields.aPHY[i].u32ControllerPhyDeviceInfo = LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_SET(LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_END)
3582	\| LSILOGICSCSI_SASIOUNIT0_DEVICE_SSP_TARGET;
3583	pSASPage0->u.fields.aPHY[i].u16AttachedDevHandle = u16DeviceHandle;
3584	pSASPage1->u.fields.aPHY[i].u32ControllerPhyDeviceInfo = LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_SET(LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_END)
3585	\| LSILOGICSCSI_SASIOUNIT0_DEVICE_SSP_TARGET;
3586	pSASPage0->u.fields.aPHY[i].u16ControllerDevHandle = u16DeviceHandle;
3587
3588	pPHYPages->SASPHYPage0.u.fields.u32AttachedDeviceInfo = LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_SET(LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_END);
3589	pPHYPages->SASPHYPage0.u.fields.SASAddress = SASAddress;
3590	pPHYPages->SASPHYPage0.u.fields.u16OwnerDevHandle = u16DeviceHandle;
3591	pPHYPages->SASPHYPage0.u.fields.u16AttachedDevHandle = u16DeviceHandle;
3592
3593	/* SAS device page 0. */
3594	pSASDevice->SASDevicePage0.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3595	\| MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3596	pSASDevice->SASDevicePage0.u.fields.ExtHeader.u8PageNumber = 0;
3597	pSASDevice->SASDevicePage0.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASDEVICE;
3598	pSASDevice->SASDevicePage0.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASDevice0) / 4;
3599	pSASDevice->SASDevicePage0.u.fields.SASAddress = SASAddress;
3600	pSASDevice->SASDevicePage0.u.fields.u16ParentDevHandle = u16ControllerHandle;
3601	pSASDevice->SASDevicePage0.u.fields.u8PhyNum = i;
3602	pSASDevice->SASDevicePage0.u.fields.u8AccessStatus = LSILOGICSCSI_SASDEVICE0_STATUS_NO_ERRORS;
3603	pSASDevice->SASDevicePage0.u.fields.u16DevHandle = u16DeviceHandle;
3604	pSASDevice->SASDevicePage0.u.fields.u8TargetID = i;
3605	pSASDevice->SASDevicePage0.u.fields.u8Bus = 0;
3606	pSASDevice->SASDevicePage0.u.fields.u32DeviceInfo = LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_SET(LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_END)
3607	\| LSILOGICSCSI_SASIOUNIT0_DEVICE_SSP_TARGET;
3608	pSASDevice->SASDevicePage0.u.fields.u16Flags = LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_PRESENT
3609	\| LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_MAPPED_TO_BUS_AND_TARGET_ID
3610	\| LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_MAPPING_PERSISTENT;
3611	pSASDevice->SASDevicePage0.u.fields.u8PhysicalPort = i;
3612
3613	/* SAS device page 1. */
3614	pSASDevice->SASDevicePage1.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3615	\| MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3616	pSASDevice->SASDevicePage1.u.fields.ExtHeader.u8PageNumber = 1;
3617	pSASDevice->SASDevicePage1.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASDEVICE;
3618	pSASDevice->SASDevicePage1.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASDevice1) / 4;
3619	pSASDevice->SASDevicePage1.u.fields.SASAddress = SASAddress;
3620	pSASDevice->SASDevicePage1.u.fields.u16DevHandle = u16DeviceHandle;
3621	pSASDevice->SASDevicePage1.u.fields.u8TargetID = i;
3622	pSASDevice->SASDevicePage1.u.fields.u8Bus = 0;
3623
3624	/* SAS device page 2. */
3625	pSASDevice->SASDevicePage2.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3626	\| MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3627	pSASDevice->SASDevicePage2.u.fields.ExtHeader.u8PageNumber = 2;
3628	pSASDevice->SASDevicePage2.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASDEVICE;
3629	pSASDevice->SASDevicePage2.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASDevice2) / 4;
3630	pSASDevice->SASDevicePage2.u.fields.SASAddress = SASAddress;
3631
3632	pSASDevice = pSASDevice->pNext;
3633	}
3634	}
3635	}
3636
3637	/**
3638	* Initializes the configuration pages.
3639	*
3640	* @returns nothing
3641	* @param pDevIns The device instance.
3642	* @param pThis Pointer to the shared LsiLogic device state.
3643	* @param pThisCC Pointer to the ring-3 LsiLogic device state.
3644	*/
3645	static void lsilogicR3InitializeConfigurationPages(PPDMDEVINS pDevIns, PLSILOGICSCSI pThis, PLSILOGICSCSICC pThisCC)
3646	{
3647	/* Initialize the common pages. */
3648
3649	LogFlowFunc(("pThis=%#p\n", pThis));
3650
3651	AssertPtrReturnVoid(pThisCC->pConfigurationPages);
3652	PMptConfigurationPagesSupported pPages = pThisCC->pConfigurationPages;
3653
3654	/* Manufacturing Page 0. */
3655	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage0,
3656	MptConfigurationPageManufacturing0, 0,
3657	MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3658	strncpy((char *)pPages->ManufacturingPage0.u.fields.abChipName, "VBox MPT Fusion", 16);
3659	strncpy((char *)pPages->ManufacturingPage0.u.fields.abChipRevision, "1.0", 8);
3660	strncpy((char *)pPages->ManufacturingPage0.u.fields.abBoardName, "VBox MPT Fusion", 16);
3661	strncpy((char *)pPages->ManufacturingPage0.u.fields.abBoardAssembly, "SUN", 8);
3662	memcpy(pPages->ManufacturingPage0.u.fields.abBoardTracerNumber, "CAFECAFECAFECAFE", 16);
3663
3664	/* Manufacturing Page 1 - I don't know what this contains so we leave it 0 for now. */
3665	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage1,
3666	MptConfigurationPageManufacturing1, 1,
3667	MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3668
3669	/* Manufacturing Page 2. */
3670	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage2,
3671	MptConfigurationPageManufacturing2, 2,
3672	MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3673
3674	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
3675	{
3676	pPages->ManufacturingPage2.u.fields.u16PCIDeviceID = LSILOGICSCSI_PCI_SPI_DEVICE_ID;
3677	pPages->ManufacturingPage2.u.fields.u8PCIRevisionID = LSILOGICSCSI_PCI_SPI_REVISION_ID;
3678	}
3679	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
3680	{
3681	pPages->ManufacturingPage2.u.fields.u16PCIDeviceID = LSILOGICSCSI_PCI_SAS_DEVICE_ID;
3682	pPages->ManufacturingPage2.u.fields.u8PCIRevisionID = LSILOGICSCSI_PCI_SAS_REVISION_ID;
3683	}
3684
3685	/* Manufacturing Page 3. */
3686	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage3,
3687	MptConfigurationPageManufacturing3, 3,
3688	MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3689
3690	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
3691	{
3692	pPages->ManufacturingPage3.u.fields.u16PCIDeviceID = LSILOGICSCSI_PCI_SPI_DEVICE_ID;
3693	pPages->ManufacturingPage3.u.fields.u8PCIRevisionID = LSILOGICSCSI_PCI_SPI_REVISION_ID;
3694	}
3695	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
3696	{
3697	pPages->ManufacturingPage3.u.fields.u16PCIDeviceID = LSILOGICSCSI_PCI_SAS_DEVICE_ID;
3698	pPages->ManufacturingPage3.u.fields.u8PCIRevisionID = LSILOGICSCSI_PCI_SAS_REVISION_ID;
3699	}
3700
3701	/* Manufacturing Page 4 - I don't know what this contains so we leave it 0 for now. */
3702	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage4,
3703	MptConfigurationPageManufacturing4, 4,
3704	MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3705
3706	/* Manufacturing Page 5 - WWID settings. */
3707	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage5,
3708	MptConfigurationPageManufacturing5, 5,
3709	MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3710
3711	/* Manufacturing Page 6 - Product specific settings. */
3712	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage6,
3713	MptConfigurationPageManufacturing6, 6,
3714	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3715
3716	/* Manufacturing Page 8 - Product specific settings. */
3717	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage8,
3718	MptConfigurationPageManufacturing8, 8,
3719	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3720
3721	/* Manufacturing Page 9 - Product specific settings. */
3722	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage9,
3723	MptConfigurationPageManufacturing9, 9,
3724	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3725
3726	/* Manufacturing Page 10 - Product specific settings. */
3727	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage10,
3728	MptConfigurationPageManufacturing10, 10,
3729	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3730
3731	/* I/O Unit page 0. */
3732	MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(&pPages->IOUnitPage0,
3733	MptConfigurationPageIOUnit0, 0,
3734	MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3735	pPages->IOUnitPage0.u.fields.u64UniqueIdentifier = 0xcafe;
3736
3737	/* I/O Unit page 1. */
3738	MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(&pPages->IOUnitPage1,
3739	MptConfigurationPageIOUnit1, 1,
3740	MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3741	pPages->IOUnitPage1.u.fields.fSingleFunction = true;
3742	pPages->IOUnitPage1.u.fields.fAllPathsMapped = false;
3743	pPages->IOUnitPage1.u.fields.fIntegratedRAIDDisabled = true;
3744	pPages->IOUnitPage1.u.fields.f32BitAccessForced = false;
3745
3746	/* I/O Unit page 2. */
3747	MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(&pPages->IOUnitPage2,
3748	MptConfigurationPageIOUnit2, 2,
3749	MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT);
3750	pPages->IOUnitPage2.u.fields.fPauseOnError = false;
3751	pPages->IOUnitPage2.u.fields.fVerboseModeEnabled = false;
3752	pPages->IOUnitPage2.u.fields.fDisableColorVideo = false;
3753	pPages->IOUnitPage2.u.fields.fNotHookInt40h = false;
3754	pPages->IOUnitPage2.u.fields.u32BIOSVersion = 0xcafecafe;
3755	pPages->IOUnitPage2.u.fields.aAdapterOrder[0].fAdapterEnabled = true;
3756	pPages->IOUnitPage2.u.fields.aAdapterOrder[0].fAdapterEmbedded = true;
3757	pPages->IOUnitPage2.u.fields.aAdapterOrder[0].u8PCIBusNumber = 0;
3758	pPages->IOUnitPage2.u.fields.aAdapterOrder[0].u8PCIDevFn = pDevIns->apPciDevs[0]->uDevFn;
3759
3760	/* I/O Unit page 3. */
3761	MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(&pPages->IOUnitPage3,
3762	MptConfigurationPageIOUnit3, 3,
3763	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3764	pPages->IOUnitPage3.u.fields.u8GPIOCount = 0;
3765
3766	/* I/O Unit page 4. */
3767	MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(&pPages->IOUnitPage4,
3768	MptConfigurationPageIOUnit4, 4,
3769	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3770
3771	/* IOC page 0. */
3772	MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage0,
3773	MptConfigurationPageIOC0, 0,
3774	MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3775	pPages->IOCPage0.u.fields.u32TotalNVStore = 0;
3776	pPages->IOCPage0.u.fields.u32FreeNVStore = 0;
3777
3778	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
3779	{
3780	pPages->IOCPage0.u.fields.u16VendorId = LSILOGICSCSI_PCI_VENDOR_ID;
3781	pPages->IOCPage0.u.fields.u16DeviceId = LSILOGICSCSI_PCI_SPI_DEVICE_ID;
3782	pPages->IOCPage0.u.fields.u8RevisionId = LSILOGICSCSI_PCI_SPI_REVISION_ID;
3783	pPages->IOCPage0.u.fields.u32ClassCode = LSILOGICSCSI_PCI_SPI_CLASS_CODE;
3784	pPages->IOCPage0.u.fields.u16SubsystemVendorId = LSILOGICSCSI_PCI_SPI_SUBSYSTEM_VENDOR_ID;
3785	pPages->IOCPage0.u.fields.u16SubsystemId = LSILOGICSCSI_PCI_SPI_SUBSYSTEM_ID;
3786	}
3787	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
3788	{
3789	pPages->IOCPage0.u.fields.u16VendorId = LSILOGICSCSI_PCI_VENDOR_ID;
3790	pPages->IOCPage0.u.fields.u16DeviceId = LSILOGICSCSI_PCI_SAS_DEVICE_ID;
3791	pPages->IOCPage0.u.fields.u8RevisionId = LSILOGICSCSI_PCI_SAS_REVISION_ID;
3792	pPages->IOCPage0.u.fields.u32ClassCode = LSILOGICSCSI_PCI_SAS_CLASS_CODE;
3793	pPages->IOCPage0.u.fields.u16SubsystemVendorId = LSILOGICSCSI_PCI_SAS_SUBSYSTEM_VENDOR_ID;
3794	pPages->IOCPage0.u.fields.u16SubsystemId = LSILOGICSCSI_PCI_SAS_SUBSYSTEM_ID;
3795	}
3796
3797	/* IOC page 1. */
3798	MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage1,
3799	MptConfigurationPageIOC1, 1,
3800	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3801	pPages->IOCPage1.u.fields.fReplyCoalescingEnabled = false;
3802	pPages->IOCPage1.u.fields.u32CoalescingTimeout = 0;
3803	pPages->IOCPage1.u.fields.u8CoalescingDepth = 0;
3804
3805	/* IOC page 2. */
3806	MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage2,
3807	MptConfigurationPageIOC2, 2,
3808	MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3809	/* Everything else here is 0. */
3810
3811	/* IOC page 3. */
3812	MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage3,
3813	MptConfigurationPageIOC3, 3,
3814	MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3815	/* Everything else here is 0. */
3816
3817	/* IOC page 4. */
3818	MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage4,
3819	MptConfigurationPageIOC4, 4,
3820	MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3821	/* Everything else here is 0. */
3822
3823	/* IOC page 6. */
3824	MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage6,
3825	MptConfigurationPageIOC6, 6,
3826	MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3827	/* Everything else here is 0. */
3828
3829	/* BIOS page 1. */
3830	MPT_CONFIG_PAGE_HEADER_INIT_BIOS(&pPages->BIOSPage1,
3831	MptConfigurationPageBIOS1, 1,
3832	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3833
3834	/* BIOS page 2. */
3835	MPT_CONFIG_PAGE_HEADER_INIT_BIOS(&pPages->BIOSPage2,
3836	MptConfigurationPageBIOS2, 2,
3837	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3838
3839	/* BIOS page 4. */
3840	MPT_CONFIG_PAGE_HEADER_INIT_BIOS(&pPages->BIOSPage4,
3841	MptConfigurationPageBIOS4, 4,
3842	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3843
3844	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
3845	lsilogicR3InitializeConfigurationPagesSpi(pThis, pThisCC);
3846	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
3847	lsilogicR3InitializeConfigurationPagesSas(pThis, pThisCC);
3848	else
3849	AssertMsgFailed(("Invalid controller type %d\n", pThis->enmCtrlType));
3850	}
3851
3852	/**
3853	* Sets the emulated controller type from a given string.
3854	*
3855	* @returns VBox status code.
3856	*
3857	* @param pThis Pointer to the shared LsiLogic device state.
3858	* @param pcszCtrlType The string to use.
3859	*/
3860	static int lsilogicR3GetCtrlTypeFromString(PLSILOGICSCSI pThis, const char *pcszCtrlType)
3861	{
3862	int rc = VERR_INVALID_PARAMETER;
3863
3864	if (!RTStrCmp(pcszCtrlType, LSILOGICSCSI_PCI_SPI_CTRLNAME))
3865	{
3866	pThis->enmCtrlType = LSILOGICCTRLTYPE_SCSI_SPI;
3867	rc = VINF_SUCCESS;
3868	}
3869	else if (!RTStrCmp(pcszCtrlType, LSILOGICSCSI_PCI_SAS_CTRLNAME))
3870	{
3871	pThis->enmCtrlType = LSILOGICCTRLTYPE_SCSI_SAS;
3872	rc = VINF_SUCCESS;
3873	}
3874
3875	return rc;
3876	}
3877
3878	/**
3879	* @callback_method_impl{PFNDBGFHANDLERDEV}
3880	*/
3881	static DECLCALLBACK(void) lsilogicR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3882	{
3883	PLSILOGICSCSI pThis = PDMDEVINS_2_DATA(pDevIns, PLSILOGICSCSI);
3884	PLSILOGICSCSICC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PLSILOGICSCSICC);
3885
3886	/*
3887	* Parse args.
3888	*/
3889	bool const fVerbose = pszArgs && strstr(pszArgs, "verbose") != NULL;
3890
3891	/*
3892	* Show info.
3893	*/
3894	pHlp->pfnPrintf(pHlp,
3895	"%s#%d: port=%04x mmio=%RGp max-devices=%u GC=%RTbool R0=%RTbool\n",
3896	pDevIns->pReg->szName, pDevIns->iInstance,
3897	PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortsReg),
3898	PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmioReg),
3899	pThis->cDeviceStates, pDevIns->fRCEnabled, pDevIns->fR0Enabled);
3900
3901	/*
3902	* Show general state.
3903	*/
3904	pHlp->pfnPrintf(pHlp, "enmState=%u\n", pThis->enmState);
3905	pHlp->pfnPrintf(pHlp, "enmWhoInit=%u\n", pThis->enmWhoInit);
3906	pHlp->pfnPrintf(pHlp, "enmDoorbellState=%d\n", pThis->enmDoorbellState);
3907	pHlp->pfnPrintf(pHlp, "fDiagnosticEnabled=%RTbool\n", pThis->fDiagnosticEnabled);
3908	pHlp->pfnPrintf(pHlp, "fNotificationSent=%RTbool\n", pThis->fNotificationSent);
3909	pHlp->pfnPrintf(pHlp, "fEventNotificationEnabled=%RTbool\n", pThis->fEventNotificationEnabled);
3910	pHlp->pfnPrintf(pHlp, "uInterruptMask=%#x\n", pThis->uInterruptMask);
3911	pHlp->pfnPrintf(pHlp, "uInterruptStatus=%#x\n", pThis->uInterruptStatus);
3912	pHlp->pfnPrintf(pHlp, "u16IOCFaultCode=%#06x\n", pThis->u16IOCFaultCode);
3913	pHlp->pfnPrintf(pHlp, "u32HostMFAHighAddr=%#x\n", pThis->u32HostMFAHighAddr);
3914	pHlp->pfnPrintf(pHlp, "u32SenseBufferHighAddr=%#x\n", pThis->u32SenseBufferHighAddr);
3915	pHlp->pfnPrintf(pHlp, "cMaxDevices=%u\n", pThis->cMaxDevices);
3916	pHlp->pfnPrintf(pHlp, "cMaxBuses=%u\n", pThis->cMaxBuses);
3917	pHlp->pfnPrintf(pHlp, "cbReplyFrame=%u\n", pThis->cbReplyFrame);
3918	pHlp->pfnPrintf(pHlp, "cReplyQueueEntries=%u\n", pThis->cReplyQueueEntries);
3919	pHlp->pfnPrintf(pHlp, "cRequestQueueEntries=%u\n", pThis->cRequestQueueEntries);
3920	pHlp->pfnPrintf(pHlp, "cPorts=%u\n", pThis->cPorts);
3921
3922	/*
3923	* Show queue status.
3924	*/
3925	pHlp->pfnPrintf(pHlp, "uReplyFreeQueueNextEntryFreeWrite=%u\n", pThis->uReplyFreeQueueNextEntryFreeWrite);
3926	pHlp->pfnPrintf(pHlp, "uReplyFreeQueueNextAddressRead=%u\n", pThis->uReplyFreeQueueNextAddressRead);
3927	pHlp->pfnPrintf(pHlp, "uReplyPostQueueNextEntryFreeWrite=%u\n", pThis->uReplyPostQueueNextEntryFreeWrite);
3928	pHlp->pfnPrintf(pHlp, "uReplyPostQueueNextAddressRead=%u\n", pThis->uReplyPostQueueNextAddressRead);
3929	pHlp->pfnPrintf(pHlp, "uRequestQueueNextEntryFreeWrite=%u\n", pThis->uRequestQueueNextEntryFreeWrite);
3930	pHlp->pfnPrintf(pHlp, "uRequestQueueNextAddressRead=%u\n", pThis->uRequestQueueNextAddressRead);
3931
3932	/*
3933	* Show queue content if verbose
3934	*/
3935	if (fVerbose)
3936	{
3937	for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
3938	pHlp->pfnPrintf(pHlp, "RFQ[%u]=%#x\n", i, pThis->aReplyFreeQueue[i]);
3939
3940	pHlp->pfnPrintf(pHlp, "\n");
3941
3942	for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
3943	pHlp->pfnPrintf(pHlp, "RPQ[%u]=%#x\n", i, pThis->aReplyPostQueue[i]);
3944
3945	pHlp->pfnPrintf(pHlp, "\n");
3946
3947	for (unsigned i = 0; i < pThis->cRequestQueueEntries; i++)
3948	pHlp->pfnPrintf(pHlp, "ReqQ[%u]=%#x\n", i, pThis->aRequestQueue[i]);
3949	}
3950
3951	/*
3952	* Print the device status.
3953	*/
3954	for (unsigned i = 0; i < pThis->cDeviceStates; i++)
3955	{
3956	PLSILOGICDEVICE pDevice = &pThisCC->paDeviceStates[i];
3957
3958	pHlp->pfnPrintf(pHlp, "\n");
3959
3960	pHlp->pfnPrintf(pHlp, "Device[%u]: device-attached=%RTbool cOutstandingRequests=%u\n",
3961	i, pDevice->pDrvBase != NULL, pDevice->cOutstandingRequests);
3962	}
3963	}
3964
3965
3966	/**
3967	* @callback_method_impl{FNPDMTHREADDEV}
3968	*/
3969	static DECLCALLBACK(int) lsilogicR3Worker(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3970	{
3971	PLSILOGICSCSI pThis = PDMDEVINS_2_DATA(pDevIns, PLSILOGICSCSI);
3972	PLSILOGICSCSICC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PLSILOGICSCSICC);
3973	int rc = VINF_SUCCESS;
3974
3975	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3976	return VINF_SUCCESS;
3977
3978	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3979	{
3980	ASMAtomicWriteBool(&pThis->fWrkThreadSleeping, true);
3981	bool fNotificationSent = ASMAtomicXchgBool(&pThis->fNotificationSent, false);
3982	if (!fNotificationSent)
3983	{
3984	Assert(ASMAtomicReadBool(&pThis->fWrkThreadSleeping));
3985	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtProcess, RT_INDEFINITE_WAIT);
3986	AssertLogRelMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
3987	if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
3988	break;
3989	LogFlowFunc(("Woken up with rc=%Rrc\n", rc));
3990	ASMAtomicWriteBool(&pThis->fNotificationSent, false);
3991	}
3992
3993	ASMAtomicWriteBool(&pThis->fWrkThreadSleeping, false);
3994
3995	/* Only process request which arrived before we received the notification. */
3996	uint32_t uRequestQueueNextEntryWrite = ASMAtomicReadU32(&pThis->uRequestQueueNextEntryFreeWrite);
3997
3998	/* Go through the messages now and process them. */
3999	while ( RT_LIKELY(pThis->enmState == LSILOGICSTATE_OPERATIONAL)
4000	&& (pThis->uRequestQueueNextAddressRead != uRequestQueueNextEntryWrite))
4001	{
4002	MptRequestUnion GuestRequest;
4003	uint32_t u32RequestMessageFrameDesc = pThis->aRequestQueue[pThis->uRequestQueueNextAddressRead];
4004	RTGCPHYS GCPhysMessageFrameAddr = LSILOGIC_RTGCPHYS_FROM_U32(pThis->u32HostMFAHighAddr,
4005	(u32RequestMessageFrameDesc & ~0x07));
4006
4007	/* Read the message header from the guest first. */
4008	PDMDevHlpPCIPhysReadMeta(pDevIns, GCPhysMessageFrameAddr, &GuestRequest, sizeof(MptMessageHdr));
4009
4010	/* Determine the size of the request. */
4011	uint32_t cbRequest = 0;
4012	switch (GuestRequest.Header.u8Function)
4013	{
4014	case MPT_MESSAGE_HDR_FUNCTION_SCSI_IO_REQUEST:
4015	cbRequest = sizeof(MptSCSIIORequest);
4016	break;
4017	case MPT_MESSAGE_HDR_FUNCTION_SCSI_TASK_MGMT:
4018	cbRequest = sizeof(MptSCSITaskManagementRequest);
4019	break;
4020	case MPT_MESSAGE_HDR_FUNCTION_IOC_INIT:
4021	cbRequest = sizeof(MptIOCInitRequest);
4022	break;
4023	case MPT_MESSAGE_HDR_FUNCTION_IOC_FACTS:
4024	cbRequest = sizeof(MptIOCFactsRequest);
4025	break;
4026	case MPT_MESSAGE_HDR_FUNCTION_CONFIG:
4027	cbRequest = sizeof(MptConfigurationRequest);
4028	break;
4029	case MPT_MESSAGE_HDR_FUNCTION_PORT_FACTS:
4030	cbRequest = sizeof(MptPortFactsRequest);
4031	break;
4032	case MPT_MESSAGE_HDR_FUNCTION_PORT_ENABLE:
4033	cbRequest = sizeof(MptPortEnableRequest);
4034	break;
4035	case MPT_MESSAGE_HDR_FUNCTION_EVENT_NOTIFICATION:
4036	cbRequest = sizeof(MptEventNotificationRequest);
4037	break;
4038	case MPT_MESSAGE_HDR_FUNCTION_EVENT_ACK:
4039	AssertMsgFailed(("todo\n"));
4040	//cbRequest = sizeof(MptEventAckRequest);
4041	break;
4042	case MPT_MESSAGE_HDR_FUNCTION_FW_DOWNLOAD:
4043	cbRequest = sizeof(MptFWDownloadRequest);
4044	break;
4045	case MPT_MESSAGE_HDR_FUNCTION_FW_UPLOAD:
4046	cbRequest = sizeof(MptFWUploadRequest);
4047	break;
4048	default:
4049	AssertMsgFailed(("Unknown function issued %u\n", GuestRequest.Header.u8Function));
4050	lsilogicSetIOCFaultCode(pThis, LSILOGIC_IOCSTATUS_INVALID_FUNCTION);
4051	}
4052
4053	if (cbRequest != 0)
4054	{
4055	/* Read the complete message frame from guest memory now. */
4056	PDMDevHlpPCIPhysReadMeta(pDevIns, GCPhysMessageFrameAddr, &GuestRequest, cbRequest);
4057
4058	/* Handle SCSI I/O requests now. */
4059	if (GuestRequest.Header.u8Function == MPT_MESSAGE_HDR_FUNCTION_SCSI_IO_REQUEST)
4060	{
4061	rc = lsilogicR3ProcessSCSIIORequest(pDevIns, pThis, pThisCC, GCPhysMessageFrameAddr, &GuestRequest);
4062	AssertRC(rc);
4063	}
4064	else
4065	{
4066	MptReplyUnion Reply;
4067	rc = lsilogicR3ProcessMessageRequest(pDevIns, pThis, pThisCC, &GuestRequest.Header, &Reply);
4068	AssertRC(rc);
4069	}
4070
4071	pThis->uRequestQueueNextAddressRead++;
4072	pThis->uRequestQueueNextAddressRead %= pThis->cRequestQueueEntries;
4073	}
4074	} /* While request frames available. */
4075	} /* While running */
4076
4077	return VINF_SUCCESS;
4078	}
4079
4080
4081	/**
4082	* @callback_method_impl{FNPDMTHREADWAKEUPDEV}
4083	*/
4084	static DECLCALLBACK(int) lsilogicR3WorkerWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4085	{
4086	RT_NOREF(pThread);
4087	PLSILOGICSCSI pThis = PDMDEVINS_2_DATA(pDevIns, PLSILOGICSCSI);
4088	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtProcess);
4089	}
4090
4091
4092	/**
4093	* Kicks the controller to process pending tasks after the VM was resumed
4094	* or loaded from a saved state.
4095	*
4096	* @returns nothing.
4097	* @param pDevIns The device instance.
4098	* @param pThis Pointer to the shared LsiLogic device state.
4099	*/
4100	static void lsilogicR3Kick(PPDMDEVINS pDevIns, PLSILOGICSCSI pThis)
4101	{
4102	if (pThis->fNotificationSent)
4103	{
4104	/* Notify the worker thread that there are pending requests. */
4105	LogFlowFunc(("Signal event semaphore\n"));
4106	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtProcess);
4107	AssertRC(rc);
4108	}
4109	}
4110
4111
4112	/*
4113	* Saved state.
4114	*/
4115
4116	/**
4117	* @callback_method_impl{FNSSMDEVLIVEEXEC}
4118	*/
4119	static DECLCALLBACK(int) lsilogicR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
4120	{
4121	RT_NOREF(uPass);
4122	PLSILOGICSCSI pThis = PDMDEVINS_2_DATA(pDevIns, PLSILOGICSCSI);
4123	PLSILOGICSCSICC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PLSILOGICSCSICC);
4124	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
4125
4126	pHlp->pfnSSMPutU32(pSSM, pThis->enmCtrlType);
4127	pHlp->pfnSSMPutU32(pSSM, pThis->cDeviceStates);
4128	pHlp->pfnSSMPutU32(pSSM, pThis->cPorts);
4129
4130	/* Save the device config. */
4131	for (unsigned i = 0; i < pThis->cDeviceStates; i++)
4132	pHlp->pfnSSMPutBool(pSSM, pThisCC->paDeviceStates[i].pDrvBase != NULL);
4133
4134	return VINF_SSM_DONT_CALL_AGAIN;
4135	}
4136
4137	/**
4138	* @callback_method_impl{FNSSMDEVSAVEEXEC}
4139	*/
4140	static DECLCALLBACK(int) lsilogicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4141	{
4142	PLSILOGICSCSI pThis = PDMDEVINS_2_DATA(pDevIns, PLSILOGICSCSI);
4143	PLSILOGICSCSICC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PLSILOGICSCSICC);
4144	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
4145
4146	/* Every device first. */
4147	lsilogicR3LiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
4148	for (unsigned i = 0; i < pThis->cDeviceStates; i++)
4149	{
4150	PLSILOGICDEVICE pDevice = &pThisCC->paDeviceStates[i];
4151
4152	AssertMsg(!pDevice->cOutstandingRequests,
4153	("There are still outstanding requests on this device\n"));
4154	pHlp->pfnSSMPutU32(pSSM, pDevice->cOutstandingRequests);
4155
4156	/* Query all suspended requests and store them in the request queue. */
4157	if (pDevice->pDrvMediaEx)
4158	{
4159	uint32_t cReqsRedo = pDevice->pDrvMediaEx->pfnIoReqGetSuspendedCount(pDevice->pDrvMediaEx);
4160	if (cReqsRedo)
4161	{
4162	PDMMEDIAEXIOREQ hIoReq;
4163	PLSILOGICREQ pReq;
4164	int rc = pDevice->pDrvMediaEx->pfnIoReqQuerySuspendedStart(pDevice->pDrvMediaEx, &hIoReq,
4165	(void **)&pReq);
4166	AssertRCBreak(rc);
4167
4168	for (;;)
4169	{
4170	/* Write only the lower 32bit part of the address. */
4171	ASMAtomicWriteU32(&pThis->aRequestQueue[pThis->uRequestQueueNextEntryFreeWrite],
4172	pReq->GCPhysMessageFrameAddr & UINT32_C(0xffffffff));
4173
4174	pThis->uRequestQueueNextEntryFreeWrite++;
4175	pThis->uRequestQueueNextEntryFreeWrite %= pThis->cRequestQueueEntries;
4176
4177	cReqsRedo--;
4178	if (!cReqsRedo)
4179	break;
4180
4181	rc = pDevice->pDrvMediaEx->pfnIoReqQuerySuspendedNext(pDevice->pDrvMediaEx, hIoReq,
4182	&hIoReq, (void **)&pReq);
4183	AssertRCBreak(rc);
4184	}
4185	}
4186	}
4187	}
4188
4189	/* Now the main device state. */
4190	pHlp->pfnSSMPutU32(pSSM, pThis->enmState);
4191	pHlp->pfnSSMPutU32(pSSM, pThis->enmWhoInit);
4192	pHlp->pfnSSMPutU32(pSSM, pThis->enmDoorbellState);
4193	pHlp->pfnSSMPutBool(pSSM, pThis->fDiagnosticEnabled);
4194	pHlp->pfnSSMPutBool(pSSM, pThis->fNotificationSent);
4195	pHlp->pfnSSMPutBool(pSSM, pThis->fEventNotificationEnabled);
4196	pHlp->pfnSSMPutU32(pSSM, pThis->uInterruptMask);
4197	pHlp->pfnSSMPutU32(pSSM, pThis->uInterruptStatus);
4198	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMessage); i++)
4199	pHlp->pfnSSMPutU32(pSSM, pThis->aMessage[i]);
4200	pHlp->pfnSSMPutU32(pSSM, pThis->iMessage);
4201	pHlp->pfnSSMPutU32(pSSM, pThis->cMessage);
4202	pHlp->pfnSSMPutMem(pSSM, &pThis->ReplyBuffer, sizeof(pThis->ReplyBuffer));
4203	pHlp->pfnSSMPutU32(pSSM, pThis->uNextReplyEntryRead);
4204	pHlp->pfnSSMPutU32(pSSM, pThis->cReplySize);
4205	pHlp->pfnSSMPutU16(pSSM, pThis->u16IOCFaultCode);
4206	pHlp->pfnSSMPutU32(pSSM, pThis->u32HostMFAHighAddr);
4207	pHlp->pfnSSMPutU32(pSSM, pThis->u32SenseBufferHighAddr);
4208	pHlp->pfnSSMPutU8(pSSM, pThis->cMaxDevices);
4209	pHlp->pfnSSMPutU8(pSSM, pThis->cMaxBuses);
4210	pHlp->pfnSSMPutU16(pSSM, pThis->cbReplyFrame);
4211	pHlp->pfnSSMPutU32(pSSM, pThis->iDiagnosticAccess);
4212	pHlp->pfnSSMPutU32(pSSM, pThis->cReplyQueueEntries);
4213	pHlp->pfnSSMPutU32(pSSM, pThis->cRequestQueueEntries);
4214	pHlp->pfnSSMPutU32(pSSM, pThis->uReplyFreeQueueNextEntryFreeWrite);
4215	pHlp->pfnSSMPutU32(pSSM, pThis->uReplyFreeQueueNextAddressRead);
4216	pHlp->pfnSSMPutU32(pSSM, pThis->uReplyPostQueueNextEntryFreeWrite);
4217	pHlp->pfnSSMPutU32(pSSM, pThis->uReplyPostQueueNextAddressRead);
4218	pHlp->pfnSSMPutU32(pSSM, pThis->uRequestQueueNextEntryFreeWrite);
4219	pHlp->pfnSSMPutU32(pSSM, pThis->uRequestQueueNextAddressRead);
4220
4221	for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
4222	pHlp->pfnSSMPutU32(pSSM, pThis->aReplyFreeQueue[i]);
4223	for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
4224	pHlp->pfnSSMPutU32(pSSM, pThis->aReplyPostQueue[i]);
4225	for (unsigned i = 0; i < pThis->cRequestQueueEntries; i++)
4226	pHlp->pfnSSMPutU32(pSSM, pThis->aRequestQueue[i]);
4227
4228	pHlp->pfnSSMPutU16(pSSM, pThis->u16NextHandle);
4229
4230	/* Save diagnostic memory register and data regions. */
4231	pHlp->pfnSSMPutU32(pSSM, pThis->u32DiagMemAddr);
4232	pHlp->pfnSSMPutU32(pSSM, lsilogicR3MemRegionsCount(pThisCC));
4233
4234	PLSILOGICMEMREGN pIt;
4235	RTListForEach(&pThisCC->ListMemRegns, pIt, LSILOGICMEMREGN, NodeList)
4236	{
4237	pHlp->pfnSSMPutU32(pSSM, pIt->u32AddrStart);
4238	pHlp->pfnSSMPutU32(pSSM, pIt->u32AddrEnd);
4239	pHlp->pfnSSMPutMem(pSSM, &pIt->au32Data[0], (pIt->u32AddrEnd - pIt->u32AddrStart + 1) * sizeof(uint32_t));
4240	}
4241
4242	PMptConfigurationPagesSupported pPages = pThisCC->pConfigurationPages;
4243
4244	pHlp->pfnSSMPutMem(pSSM, &pPages->ManufacturingPage0, sizeof(MptConfigurationPageManufacturing0));
4245	pHlp->pfnSSMPutMem(pSSM, &pPages->ManufacturingPage1, sizeof(MptConfigurationPageManufacturing1));
4246	pHlp->pfnSSMPutMem(pSSM, &pPages->ManufacturingPage2, sizeof(MptConfigurationPageManufacturing2));
4247	pHlp->pfnSSMPutMem(pSSM, &pPages->ManufacturingPage3, sizeof(MptConfigurationPageManufacturing3));
4248	pHlp->pfnSSMPutMem(pSSM, &pPages->ManufacturingPage4, sizeof(MptConfigurationPageManufacturing4));
4249	pHlp->pfnSSMPutMem(pSSM, &pPages->ManufacturingPage5, sizeof(MptConfigurationPageManufacturing5));
4250	pHlp->pfnSSMPutMem(pSSM, &pPages->ManufacturingPage6, sizeof(MptConfigurationPageManufacturing6));
4251	pHlp->pfnSSMPutMem(pSSM, &pPages->ManufacturingPage8, sizeof(MptConfigurationPageManufacturing8));
4252	pHlp->pfnSSMPutMem(pSSM, &pPages->ManufacturingPage9, sizeof(MptConfigurationPageManufacturing9));
4253	pHlp->pfnSSMPutMem(pSSM, &pPages->ManufacturingPage10, sizeof(MptConfigurationPageManufacturing10));
4254	pHlp->pfnSSMPutMem(pSSM, &pPages->IOUnitPage0, sizeof(MptConfigurationPageIOUnit0));
4255	pHlp->pfnSSMPutMem(pSSM, &pPages->IOUnitPage1, sizeof(MptConfigurationPageIOUnit1));
4256	pHlp->pfnSSMPutMem(pSSM, &pPages->IOUnitPage2, sizeof(MptConfigurationPageIOUnit2));
4257	pHlp->pfnSSMPutMem(pSSM, &pPages->IOUnitPage3, sizeof(MptConfigurationPageIOUnit3));
4258	pHlp->pfnSSMPutMem(pSSM, &pPages->IOUnitPage4, sizeof(MptConfigurationPageIOUnit4));
4259	pHlp->pfnSSMPutMem(pSSM, &pPages->IOCPage0, sizeof(MptConfigurationPageIOC0));
4260	pHlp->pfnSSMPutMem(pSSM, &pPages->IOCPage1, sizeof(MptConfigurationPageIOC1));
4261	pHlp->pfnSSMPutMem(pSSM, &pPages->IOCPage2, sizeof(MptConfigurationPageIOC2));
4262	pHlp->pfnSSMPutMem(pSSM, &pPages->IOCPage3, sizeof(MptConfigurationPageIOC3));
4263	pHlp->pfnSSMPutMem(pSSM, &pPages->IOCPage4, sizeof(MptConfigurationPageIOC4));
4264	pHlp->pfnSSMPutMem(pSSM, &pPages->IOCPage6, sizeof(MptConfigurationPageIOC6));
4265	pHlp->pfnSSMPutMem(pSSM, &pPages->BIOSPage1, sizeof(MptConfigurationPageBIOS1));
4266	pHlp->pfnSSMPutMem(pSSM, &pPages->BIOSPage2, sizeof(MptConfigurationPageBIOS2));
4267	pHlp->pfnSSMPutMem(pSSM, &pPages->BIOSPage4, sizeof(MptConfigurationPageBIOS4));
4268
4269	/* Device dependent pages */
4270	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
4271	{
4272	PMptConfigurationPagesSpi pSpiPages = &pPages->u.SpiPages;
4273
4274	pHlp->pfnSSMPutMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage0, sizeof(MptConfigurationPageSCSISPIPort0));
4275	pHlp->pfnSSMPutMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage1, sizeof(MptConfigurationPageSCSISPIPort1));
4276	pHlp->pfnSSMPutMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage2, sizeof(MptConfigurationPageSCSISPIPort2));
4277
4278	for (unsigned i = 0; i < RT_ELEMENTS(pSpiPages->aBuses[0].aDevicePages); i++)
4279	{
4280	pHlp->pfnSSMPutMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage0, sizeof(MptConfigurationPageSCSISPIDevice0));
4281	pHlp->pfnSSMPutMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage1, sizeof(MptConfigurationPageSCSISPIDevice1));
4282	pHlp->pfnSSMPutMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage2, sizeof(MptConfigurationPageSCSISPIDevice2));
4283	pHlp->pfnSSMPutMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage3, sizeof(MptConfigurationPageSCSISPIDevice3));
4284	}
4285	}
4286	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
4287	{
4288	PMptConfigurationPagesSas pSasPages = &pPages->u.SasPages;
4289
4290	pHlp->pfnSSMPutU32(pSSM, pSasPages->cbManufacturingPage7);
4291	pHlp->pfnSSMPutU32(pSSM, pSasPages->cbSASIOUnitPage0);
4292	pHlp->pfnSSMPutU32(pSSM, pSasPages->cbSASIOUnitPage1);
4293
4294	pHlp->pfnSSMPutMem(pSSM, pSasPages->pManufacturingPage7, pSasPages->cbManufacturingPage7);
4295	pHlp->pfnSSMPutMem(pSSM, pSasPages->pSASIOUnitPage0, pSasPages->cbSASIOUnitPage0);
4296	pHlp->pfnSSMPutMem(pSSM, pSasPages->pSASIOUnitPage1, pSasPages->cbSASIOUnitPage1);
4297
4298	pHlp->pfnSSMPutMem(pSSM, &pSasPages->SASIOUnitPage2, sizeof(MptConfigurationPageSASIOUnit2));
4299	pHlp->pfnSSMPutMem(pSSM, &pSasPages->SASIOUnitPage3, sizeof(MptConfigurationPageSASIOUnit3));
4300
4301	pHlp->pfnSSMPutU32(pSSM, pSasPages->cPHYs);
4302	for (unsigned i = 0; i < pSasPages->cPHYs; i++)
4303	{
4304	pHlp->pfnSSMPutMem(pSSM, &pSasPages->paPHYs[i].SASPHYPage0, sizeof(MptConfigurationPageSASPHY0));
4305	pHlp->pfnSSMPutMem(pSSM, &pSasPages->paPHYs[i].SASPHYPage1, sizeof(MptConfigurationPageSASPHY1));
4306	}
4307
4308	/* The number of devices first. */
4309	pHlp->pfnSSMPutU32(pSSM, pSasPages->cDevices);
4310
4311	for (PMptSASDevice pCurr = pSasPages->pSASDeviceHead; pCurr; pCurr = pCurr->pNext)
4312	{
4313	pHlp->pfnSSMPutMem(pSSM, &pCurr->SASDevicePage0, sizeof(MptConfigurationPageSASDevice0));
4314	pHlp->pfnSSMPutMem(pSSM, &pCurr->SASDevicePage1, sizeof(MptConfigurationPageSASDevice1));
4315	pHlp->pfnSSMPutMem(pSSM, &pCurr->SASDevicePage2, sizeof(MptConfigurationPageSASDevice2));
4316	}
4317	}
4318	else
4319	AssertMsgFailed(("Invalid controller type %d\n", pThis->enmCtrlType));
4320
4321	return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX);
4322	}
4323
4324	/**
4325	* @callback_method_impl{FNSSMDEVLOADDONE}
4326	*/
4327	static DECLCALLBACK(int) lsilogicR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4328	{
4329	RT_NOREF(pSSM);
4330	PLSILOGICSCSI pThis = PDMDEVINS_2_DATA(pDevIns, PLSILOGICSCSI);
4331
4332	lsilogicR3Kick(pDevIns, pThis);
4333	return VINF_SUCCESS;
4334	}
4335
4336	/**
4337	* @callback_method_impl{FNSSMDEVLOADEXEC}
4338	*/
4339	static DECLCALLBACK(int) lsilogicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4340	{
4341	PLSILOGICSCSI pThis = PDMDEVINS_2_DATA(pDevIns, PLSILOGICSCSI);
4342	PLSILOGICSCSICC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PLSILOGICSCSICC);
4343	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
4344	int rc;
4345
4346	if ( uVersion > LSILOGIC_SAVED_STATE_VERSION
4347	\|\| uVersion < LSILOGIC_SAVED_STATE_VERSION_VBOX_30)
4348	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
4349
4350	/* device config */
4351	if (uVersion > LSILOGIC_SAVED_STATE_VERSION_PRE_SAS)
4352	{
4353	LSILOGICCTRLTYPE enmCtrlType;
4354	uint32_t cDeviceStates, cPorts;
4355
4356	PDMDEVHLP_SSM_GET_ENUM32_RET(pHlp, pSSM, enmCtrlType, LSILOGICCTRLTYPE);
4357	pHlp->pfnSSMGetU32(pSSM, &cDeviceStates);
4358	rc = pHlp->pfnSSMGetU32(pSSM, &cPorts);
4359	AssertRCReturn(rc, rc);
4360
4361	if (enmCtrlType != pThis->enmCtrlType)
4362	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Target config mismatch (Controller type): config=%d state=%d"),
4363	pThis->enmCtrlType, enmCtrlType);
4364	if (cDeviceStates != pThis->cDeviceStates)
4365	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Target config mismatch (Device states): config=%u state=%u"),
4366	pThis->cDeviceStates, cDeviceStates);
4367	if (cPorts != pThis->cPorts)
4368	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Target config mismatch (Ports): config=%u state=%u"),
4369	pThis->cPorts, cPorts);
4370	}
4371	if (uVersion > LSILOGIC_SAVED_STATE_VERSION_VBOX_30)
4372	{
4373	for (unsigned i = 0; i < pThis->cDeviceStates; i++)
4374	{
4375	bool fPresent;
4376	rc = pHlp->pfnSSMGetBool(pSSM, &fPresent);
4377	AssertRCReturn(rc, rc);
4378	if (fPresent != (pThisCC->paDeviceStates[i].pDrvBase != NULL))
4379	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Target %u config mismatch: config=%RTbool state=%RTbool"),
4380	i, pThisCC->paDeviceStates[i].pDrvBase != NULL, fPresent);
4381	}
4382	}
4383	if (uPass != SSM_PASS_FINAL)
4384	return VINF_SUCCESS;
4385
4386	/* Every device first. */
4387	for (unsigned i = 0; i < pThis->cDeviceStates; i++)
4388	{
4389	PLSILOGICDEVICE pDevice = &pThisCC->paDeviceStates[i];
4390
4391	AssertMsg(!pDevice->cOutstandingRequests,
4392	("There are still outstanding requests on this device\n"));
4393	pHlp->pfnSSMGetU32V(pSSM, &pDevice->cOutstandingRequests);
4394	}
4395	/* Now the main device state. */
4396	PDMDEVHLP_SSM_GET_ENUM32_RET(pHlp, pSSM, pThis->enmState, LSILOGICSTATE);
4397	PDMDEVHLP_SSM_GET_ENUM32_RET(pHlp, pSSM, pThis->enmWhoInit, LSILOGICWHOINIT);
4398	if (uVersion <= LSILOGIC_SAVED_STATE_VERSION_BOOL_DOORBELL)
4399	{
4400	/*
4401	* The doorbell status flag distinguishes only between
4402	* doorbell not in use or a Function handshake is currently in progress.
4403	*/
4404	bool fDoorbellInProgress = false;
4405	rc = pHlp->pfnSSMGetBool(pSSM, &fDoorbellInProgress);
4406	AssertRCReturn(rc, rc);
4407	if (fDoorbellInProgress)
4408	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_FN_HANDSHAKE;
4409	else
4410	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_NOT_IN_USE;
4411	}
4412	else
4413	PDMDEVHLP_SSM_GET_ENUM32_RET(pHlp, pSSM, pThis->enmDoorbellState, LSILOGICDOORBELLSTATE);
4414	pHlp->pfnSSMGetBool(pSSM, &pThis->fDiagnosticEnabled);
4415	pHlp->pfnSSMGetBool(pSSM, &pThis->fNotificationSent);
4416	pHlp->pfnSSMGetBool(pSSM, &pThis->fEventNotificationEnabled);
4417	pHlp->pfnSSMGetU32V(pSSM, &pThis->uInterruptMask);
4418	pHlp->pfnSSMGetU32V(pSSM, &pThis->uInterruptStatus);
4419	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMessage); i++)
4420	pHlp->pfnSSMGetU32(pSSM, &pThis->aMessage[i]);
4421	pHlp->pfnSSMGetU32(pSSM, &pThis->iMessage);
4422	pHlp->pfnSSMGetU32(pSSM, &pThis->cMessage);
4423	pHlp->pfnSSMGetMem(pSSM, &pThis->ReplyBuffer, sizeof(pThis->ReplyBuffer));
4424	pHlp->pfnSSMGetU32(pSSM, &pThis->uNextReplyEntryRead);
4425	pHlp->pfnSSMGetU32(pSSM, &pThis->cReplySize);
4426	pHlp->pfnSSMGetU16(pSSM, &pThis->u16IOCFaultCode);
4427	pHlp->pfnSSMGetU32(pSSM, &pThis->u32HostMFAHighAddr);
4428	pHlp->pfnSSMGetU32(pSSM, &pThis->u32SenseBufferHighAddr);
4429	pHlp->pfnSSMGetU8(pSSM, &pThis->cMaxDevices);
4430	pHlp->pfnSSMGetU8(pSSM, &pThis->cMaxBuses);
4431	pHlp->pfnSSMGetU16(pSSM, &pThis->cbReplyFrame);
4432	pHlp->pfnSSMGetU32(pSSM, &pThis->iDiagnosticAccess);
4433
4434	uint32_t cReplyQueueEntries, cRequestQueueEntries;
4435	pHlp->pfnSSMGetU32(pSSM, &cReplyQueueEntries);
4436	rc = pHlp->pfnSSMGetU32(pSSM, &cRequestQueueEntries);
4437	AssertRCReturn(rc, rc);
4438
4439	if ( cReplyQueueEntries != pThis->cReplyQueueEntries
4440	\|\| cRequestQueueEntries != pThis->cRequestQueueEntries)
4441	{
4442	LogRel(("Changing queue sizes: cReplyQueueEntries=%u cRequestQueuEntries=%u\n", cReplyQueueEntries, cRequestQueueEntries));
4443	if ( cReplyQueueEntries > RT_ELEMENTS(pThis->aReplyFreeQueue)
4444	\|\| cReplyQueueEntries < LSILOGICSCSI_REQUEST_QUEUE_DEPTH_MIN
4445	\|\| cRequestQueueEntries > RT_ELEMENTS(pThis->aRequestQueue)
4446	\|\| cRequestQueueEntries < LSILOGICSCSI_REPLY_QUEUE_DEPTH_MIN)
4447	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Out of bounds: cReplyQueueEntries=%u cRequestQueueEntries=%u"),
4448	cReplyQueueEntries, cRequestQueueEntries);
4449	pThis->cReplyQueueEntries = cReplyQueueEntries;
4450	pThis->cRequestQueueEntries = cRequestQueueEntries;
4451	}
4452
4453	pHlp->pfnSSMGetU32V(pSSM, &pThis->uReplyFreeQueueNextEntryFreeWrite);
4454	pHlp->pfnSSMGetU32V(pSSM, &pThis->uReplyFreeQueueNextAddressRead);
4455	pHlp->pfnSSMGetU32V(pSSM, &pThis->uReplyPostQueueNextEntryFreeWrite);
4456	pHlp->pfnSSMGetU32V(pSSM, &pThis->uReplyPostQueueNextAddressRead);
4457	pHlp->pfnSSMGetU32V(pSSM, &pThis->uRequestQueueNextEntryFreeWrite);
4458	pHlp->pfnSSMGetU32V(pSSM, &pThis->uRequestQueueNextAddressRead);
4459
4460	PMptConfigurationPagesSupported pPages = pThisCC->pConfigurationPages;
4461
4462	if (uVersion <= LSILOGIC_SAVED_STATE_VERSION_PRE_SAS)
4463	{
4464	PMptConfigurationPagesSpi pSpiPages = &pPages->u.SpiPages;
4465	MptConfigurationPagesSupported_SSM_V2 ConfigPagesV2;
4466
4467	if (pThis->enmCtrlType != LSILOGICCTRLTYPE_SCSI_SPI)
4468	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: Expected SPI SCSI controller"));
4469
4470	pHlp->pfnSSMGetMem(pSSM, &ConfigPagesV2, sizeof(MptConfigurationPagesSupported_SSM_V2));
4471
4472	pPages->ManufacturingPage0 = ConfigPagesV2.ManufacturingPage0;
4473	pPages->ManufacturingPage1 = ConfigPagesV2.ManufacturingPage1;
4474	pPages->ManufacturingPage2 = ConfigPagesV2.ManufacturingPage2;
4475	pPages->ManufacturingPage3 = ConfigPagesV2.ManufacturingPage3;
4476	pPages->ManufacturingPage4 = ConfigPagesV2.ManufacturingPage4;
4477	pPages->IOUnitPage0 = ConfigPagesV2.IOUnitPage0;
4478	pPages->IOUnitPage1 = ConfigPagesV2.IOUnitPage1;
4479	pPages->IOUnitPage2 = ConfigPagesV2.IOUnitPage2;
4480	pPages->IOUnitPage3 = ConfigPagesV2.IOUnitPage3;
4481	pPages->IOCPage0 = ConfigPagesV2.IOCPage0;
4482	pPages->IOCPage1 = ConfigPagesV2.IOCPage1;
4483	pPages->IOCPage2 = ConfigPagesV2.IOCPage2;
4484	pPages->IOCPage3 = ConfigPagesV2.IOCPage3;
4485	pPages->IOCPage4 = ConfigPagesV2.IOCPage4;
4486	pPages->IOCPage6 = ConfigPagesV2.IOCPage6;
4487
4488	pSpiPages->aPortPages[0].SCSISPIPortPage0 = ConfigPagesV2.aPortPages[0].SCSISPIPortPage0;
4489	pSpiPages->aPortPages[0].SCSISPIPortPage1 = ConfigPagesV2.aPortPages[0].SCSISPIPortPage1;
4490	pSpiPages->aPortPages[0].SCSISPIPortPage2 = ConfigPagesV2.aPortPages[0].SCSISPIPortPage2;
4491
4492	for (unsigned i = 0; i < RT_ELEMENTS(pPages->u.SpiPages.aBuses[0].aDevicePages); i++)
4493	{
4494	pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage0 = ConfigPagesV2.aBuses[0].aDevicePages[i].SCSISPIDevicePage0;
4495	pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage1 = ConfigPagesV2.aBuses[0].aDevicePages[i].SCSISPIDevicePage1;
4496	pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage2 = ConfigPagesV2.aBuses[0].aDevicePages[i].SCSISPIDevicePage2;
4497	pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage3 = ConfigPagesV2.aBuses[0].aDevicePages[i].SCSISPIDevicePage3;
4498	}
4499	}
4500	else
4501	{
4502	/* Queue content */
4503	for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
4504	pHlp->pfnSSMGetU32V(pSSM, &pThis->aReplyFreeQueue[i]);
4505	for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
4506	pHlp->pfnSSMGetU32V(pSSM, &pThis->aReplyPostQueue[i]);
4507	for (unsigned i = 0; i < pThis->cRequestQueueEntries; i++)
4508	pHlp->pfnSSMGetU32V(pSSM, &pThis->aRequestQueue[i]);
4509
4510	pHlp->pfnSSMGetU16(pSSM, &pThis->u16NextHandle);
4511
4512	if (uVersion > LSILOGIC_SAVED_STATE_VERSION_PRE_DIAG_MEM)
4513	{
4514
4515	/* Save diagnostic memory register and data regions. */
4516	pHlp->pfnSSMGetU32(pSSM, &pThis->u32DiagMemAddr);
4517	uint32_t cMemRegions = 0;
4518	rc = pHlp->pfnSSMGetU32(pSSM, &cMemRegions);
4519	AssertLogRelRCReturn(rc, rc);
4520
4521	while (cMemRegions)
4522	{
4523	uint32_t u32AddrStart = 0;
4524	pHlp->pfnSSMGetU32(pSSM, &u32AddrStart);
4525	uint32_t u32AddrEnd = 0;
4526	rc = pHlp->pfnSSMGetU32(pSSM, &u32AddrEnd);
4527	AssertLogRelRCReturn(rc, rc);
4528
4529	uint32_t cRegion = u32AddrEnd - u32AddrStart + 1;
4530	PLSILOGICMEMREGN pRegion = (PLSILOGICMEMREGN)RTMemAllocZ(RT_UOFFSETOF_DYN(LSILOGICMEMREGN, au32Data[cRegion]));
4531	if (pRegion)
4532	{
4533	pRegion->u32AddrStart = u32AddrStart;
4534	pRegion->u32AddrEnd = u32AddrEnd;
4535	pHlp->pfnSSMGetMem(pSSM, &pRegion->au32Data[0], cRegion * sizeof(uint32_t));
4536	lsilogicR3MemRegionInsert(pThisCC, pRegion);
4537	pThisCC->cbMemRegns += cRegion * sizeof(uint32_t);
4538	}
4539	else
4540	{
4541	/* Leave a log message but continue. */
4542	LogRel(("LsiLogic: Out of memory while restoring the state, might not work as expected\n"));
4543	pHlp->pfnSSMSkip(pSSM, cRegion * sizeof(uint32_t));
4544	}
4545	cMemRegions--;
4546	}
4547	}
4548
4549	/* Configuration pages */
4550	pHlp->pfnSSMGetMem(pSSM, &pPages->ManufacturingPage0, sizeof(MptConfigurationPageManufacturing0));
4551	pHlp->pfnSSMGetMem(pSSM, &pPages->ManufacturingPage1, sizeof(MptConfigurationPageManufacturing1));
4552	pHlp->pfnSSMGetMem(pSSM, &pPages->ManufacturingPage2, sizeof(MptConfigurationPageManufacturing2));
4553	pHlp->pfnSSMGetMem(pSSM, &pPages->ManufacturingPage3, sizeof(MptConfigurationPageManufacturing3));
4554	pHlp->pfnSSMGetMem(pSSM, &pPages->ManufacturingPage4, sizeof(MptConfigurationPageManufacturing4));
4555	pHlp->pfnSSMGetMem(pSSM, &pPages->ManufacturingPage5, sizeof(MptConfigurationPageManufacturing5));
4556	pHlp->pfnSSMGetMem(pSSM, &pPages->ManufacturingPage6, sizeof(MptConfigurationPageManufacturing6));
4557	pHlp->pfnSSMGetMem(pSSM, &pPages->ManufacturingPage8, sizeof(MptConfigurationPageManufacturing8));
4558	pHlp->pfnSSMGetMem(pSSM, &pPages->ManufacturingPage9, sizeof(MptConfigurationPageManufacturing9));
4559	pHlp->pfnSSMGetMem(pSSM, &pPages->ManufacturingPage10, sizeof(MptConfigurationPageManufacturing10));
4560	pHlp->pfnSSMGetMem(pSSM, &pPages->IOUnitPage0, sizeof(MptConfigurationPageIOUnit0));
4561	pHlp->pfnSSMGetMem(pSSM, &pPages->IOUnitPage1, sizeof(MptConfigurationPageIOUnit1));
4562	pHlp->pfnSSMGetMem(pSSM, &pPages->IOUnitPage2, sizeof(MptConfigurationPageIOUnit2));
4563	pHlp->pfnSSMGetMem(pSSM, &pPages->IOUnitPage3, sizeof(MptConfigurationPageIOUnit3));
4564	pHlp->pfnSSMGetMem(pSSM, &pPages->IOUnitPage4, sizeof(MptConfigurationPageIOUnit4));
4565	pHlp->pfnSSMGetMem(pSSM, &pPages->IOCPage0, sizeof(MptConfigurationPageIOC0));
4566	pHlp->pfnSSMGetMem(pSSM, &pPages->IOCPage1, sizeof(MptConfigurationPageIOC1));
4567	pHlp->pfnSSMGetMem(pSSM, &pPages->IOCPage2, sizeof(MptConfigurationPageIOC2));
4568	pHlp->pfnSSMGetMem(pSSM, &pPages->IOCPage3, sizeof(MptConfigurationPageIOC3));
4569	pHlp->pfnSSMGetMem(pSSM, &pPages->IOCPage4, sizeof(MptConfigurationPageIOC4));
4570	pHlp->pfnSSMGetMem(pSSM, &pPages->IOCPage6, sizeof(MptConfigurationPageIOC6));
4571	pHlp->pfnSSMGetMem(pSSM, &pPages->BIOSPage1, sizeof(MptConfigurationPageBIOS1));
4572	pHlp->pfnSSMGetMem(pSSM, &pPages->BIOSPage2, sizeof(MptConfigurationPageBIOS2));
4573	pHlp->pfnSSMGetMem(pSSM, &pPages->BIOSPage4, sizeof(MptConfigurationPageBIOS4));
4574
4575	/* Device dependent pages */
4576	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
4577	{
4578	PMptConfigurationPagesSpi pSpiPages = &pPages->u.SpiPages;
4579
4580	pHlp->pfnSSMGetMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage0, sizeof(MptConfigurationPageSCSISPIPort0));
4581	pHlp->pfnSSMGetMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage1, sizeof(MptConfigurationPageSCSISPIPort1));
4582	pHlp->pfnSSMGetMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage2, sizeof(MptConfigurationPageSCSISPIPort2));
4583
4584	for (unsigned i = 0; i < RT_ELEMENTS(pSpiPages->aBuses[0].aDevicePages); i++)
4585	{
4586	pHlp->pfnSSMGetMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage0, sizeof(MptConfigurationPageSCSISPIDevice0));
4587	pHlp->pfnSSMGetMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage1, sizeof(MptConfigurationPageSCSISPIDevice1));
4588	pHlp->pfnSSMGetMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage2, sizeof(MptConfigurationPageSCSISPIDevice2));
4589	pHlp->pfnSSMGetMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage3, sizeof(MptConfigurationPageSCSISPIDevice3));
4590	}
4591	}
4592	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
4593	{
4594	uint32_t cbPage0, cbPage1, cPHYs, cbManufacturingPage7;
4595	PMptConfigurationPagesSas pSasPages = &pPages->u.SasPages;
4596
4597	pHlp->pfnSSMGetU32(pSSM, &cbManufacturingPage7);
4598	pHlp->pfnSSMGetU32(pSSM, &cbPage0);
4599	rc = pHlp->pfnSSMGetU32(pSSM, &cbPage1);
4600	AssertRCReturn(rc, rc);
4601
4602	if ( (cbPage0 != pSasPages->cbSASIOUnitPage0)
4603	\|\| (cbPage1 != pSasPages->cbSASIOUnitPage1)
4604	\|\| (cbManufacturingPage7 != pSasPages->cbManufacturingPage7))
4605	return VERR_SSM_LOAD_CONFIG_MISMATCH;
4606
4607	AssertPtr(pSasPages->pManufacturingPage7);
4608	AssertPtr(pSasPages->pSASIOUnitPage0);
4609	AssertPtr(pSasPages->pSASIOUnitPage1);
4610
4611	pHlp->pfnSSMGetMem(pSSM, pSasPages->pManufacturingPage7, pSasPages->cbManufacturingPage7);
4612	pHlp->pfnSSMGetMem(pSSM, pSasPages->pSASIOUnitPage0, pSasPages->cbSASIOUnitPage0);
4613	pHlp->pfnSSMGetMem(pSSM, pSasPages->pSASIOUnitPage1, pSasPages->cbSASIOUnitPage1);
4614
4615	pHlp->pfnSSMGetMem(pSSM, &pSasPages->SASIOUnitPage2, sizeof(MptConfigurationPageSASIOUnit2));
4616	pHlp->pfnSSMGetMem(pSSM, &pSasPages->SASIOUnitPage3, sizeof(MptConfigurationPageSASIOUnit3));
4617
4618	rc = pHlp->pfnSSMGetU32(pSSM, &cPHYs);
4619	AssertRCReturn(rc, rc);
4620	if (cPHYs != pSasPages->cPHYs)
4621	return VERR_SSM_LOAD_CONFIG_MISMATCH;
4622
4623	AssertPtr(pSasPages->paPHYs);
4624	for (unsigned i = 0; i < pSasPages->cPHYs; i++)
4625	{
4626	pHlp->pfnSSMGetMem(pSSM, &pSasPages->paPHYs[i].SASPHYPage0, sizeof(MptConfigurationPageSASPHY0));
4627	pHlp->pfnSSMGetMem(pSSM, &pSasPages->paPHYs[i].SASPHYPage1, sizeof(MptConfigurationPageSASPHY1));
4628	}
4629
4630	/* The number of devices first. */
4631	rc = pHlp->pfnSSMGetU32(pSSM, &pSasPages->cDevices);
4632	AssertRCReturn(rc, rc);
4633
4634	PMptSASDevice pCurr = pSasPages->pSASDeviceHead;
4635
4636	for (unsigned i = 0; i < pSasPages->cDevices; i++)
4637	{
4638	AssertReturn(pCurr, VERR_SSM_LOAD_CONFIG_MISMATCH);
4639
4640	pHlp->pfnSSMGetMem(pSSM, &pCurr->SASDevicePage0, sizeof(MptConfigurationPageSASDevice0));
4641	pHlp->pfnSSMGetMem(pSSM, &pCurr->SASDevicePage1, sizeof(MptConfigurationPageSASDevice1));
4642	rc = pHlp->pfnSSMGetMem(pSSM, &pCurr->SASDevicePage2, sizeof(MptConfigurationPageSASDevice2));
4643	AssertRCReturn(rc, rc);
4644
4645	pCurr = pCurr->pNext;
4646	}
4647
4648	Assert(!pCurr);
4649	}
4650	else
4651	AssertMsgFailed(("Invalid controller type %d\n", pThis->enmCtrlType));
4652	}
4653
4654	if (uVersion <= LSILOGIC_SAVED_STATE_VERSION_PRE_VBOXSCSI_REMOVAL)
4655	vboxscsiR3LoadExecLegacy(pHlp, pSSM);
4656
4657	uint32_t u32;
4658	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
4659	if (RT_FAILURE(rc))
4660	return rc;
4661	AssertMsgReturn(u32 == UINT32_MAX, ("%#x\n", u32), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
4662
4663	return VINF_SUCCESS;
4664	}
4665
4666
4667	/*
4668	* The device level IBASE and LED interfaces.
4669	*/
4670
4671	/**
4672	* @interface_method_impl{PDMILEDPORTS,pfnQueryStatusLed, For a SCSI device.}
4673	*
4674	* @remarks Called by the scsi driver, proxying the main calls.
4675	*/
4676	static DECLCALLBACK(int) lsilogicR3DeviceQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
4677	{
4678	PLSILOGICDEVICE pDevice = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, ILed);
4679	if (iLUN == 0)
4680	{
4681	*ppLed = &pDevice->Led;
4682	Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
4683	return VINF_SUCCESS;
4684	}
4685	return VERR_PDM_LUN_NOT_FOUND;
4686	}
4687
4688
4689	/**
4690	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
4691	*/
4692	static DECLCALLBACK(void ) lsilogicR3DeviceQueryInterface(PPDMIBASE pInterface, const char pszIID)
4693	{
4694	PLSILOGICDEVICE pDevice = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, IBase);
4695
4696	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevice->IBase);
4697	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIMEDIAPORT, &pDevice->IMediaPort);
4698	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIMEDIAEXPORT, &pDevice->IMediaExPort);
4699	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pDevice->ILed);
4700	return NULL;
4701	}
4702
4703
4704	/*
4705	* The controller level IBASE and LED interfaces.
4706	*/
4707
4708	/**
4709	* Gets the pointer to the status LED of a unit.
4710	*
4711	* @returns VBox status code.
4712	* @param pInterface Pointer to the interface structure containing the called function pointer.
4713	* @param iLUN The unit which status LED we desire.
4714	* @param ppLed Where to store the LED pointer.
4715	*/
4716	static DECLCALLBACK(int) lsilogicR3StatusQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
4717	{
4718	PLSILOGICSCSICC pThisCC = RT_FROM_MEMBER(pInterface, LSILOGICSCSICC, ILeds);
4719	PLSILOGICSCSI pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PLSILOGICSCSI);
4720	if (iLUN < pThis->cDeviceStates)
4721	{
4722	*ppLed = &pThisCC->paDeviceStates[iLUN].Led;
4723	Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
4724	return VINF_SUCCESS;
4725	}
4726	return VERR_PDM_LUN_NOT_FOUND;
4727	}
4728
4729	/**
4730	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
4731	*/
4732	static DECLCALLBACK(void ) lsilogicR3StatusQueryInterface(PPDMIBASE pInterface, const char pszIID)
4733	{
4734	PLSILOGICSCSICC pThisCC = RT_FROM_MEMBER(pInterface, LSILOGICSCSICC, IBase);
4735	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
4736	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThisCC->ILeds);
4737	return NULL;
4738	}
4739
4740
4741	/*
4742	* The PDM device interface and some helpers.
4743	*/
4744
4745	/**
4746	* Checks if all asynchronous I/O is finished.
4747	*
4748	* Used by lsilogicR3Reset, lsilogicR3Suspend and lsilogicR3PowerOff.
4749	*
4750	* @returns true if quiesced, false if busy.
4751	* @param pDevIns The device instance.
4752	*/
4753	static bool lsilogicR3AllAsyncIOIsFinished(PPDMDEVINS pDevIns)
4754	{
4755	PLSILOGICSCSI pThis = PDMDEVINS_2_DATA(pDevIns, PLSILOGICSCSI);
4756	PLSILOGICSCSICC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PLSILOGICSCSICC);
4757
4758	for (uint32_t i = 0; i < pThis->cDeviceStates; i++)
4759	{
4760	PLSILOGICDEVICE pThisDevice = &pThisCC->paDeviceStates[i];
4761	if (pThisDevice->pDrvBase)
4762	{
4763	if (pThisDevice->cOutstandingRequests != 0)
4764	return false;
4765	}
4766	}
4767
4768	return true;
4769	}
4770
4771	/**
4772	* @callback_method_impl{FNPDMDEVASYNCNOTIFY,
4773	* Callback employed by lsilogicR3Suspend and lsilogicR3PowerOff.}
4774	*/
4775	static DECLCALLBACK(bool) lsilogicR3IsAsyncSuspendOrPowerOffDone(PPDMDEVINS pDevIns)
4776	{
4777	if (!lsilogicR3AllAsyncIOIsFinished(pDevIns))
4778	return false;
4779
4780	PLSILOGICSCSI pThis = PDMDEVINS_2_DATA(pDevIns, PLSILOGICSCSI);
4781	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
4782	return true;
4783	}
4784
4785	/**
4786	* Common worker for ahciR3Suspend and ahciR3PowerOff.
4787	*/
4788	static void lsilogicR3SuspendOrPowerOff(PPDMDEVINS pDevIns)
4789	{
4790	PLSILOGICSCSI pThis = PDMDEVINS_2_DATA(pDevIns, PLSILOGICSCSI);
4791	PLSILOGICSCSICC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PLSILOGICSCSICC);
4792
4793	ASMAtomicWriteBool(&pThis->fSignalIdle, true);
4794	if (!lsilogicR3AllAsyncIOIsFinished(pDevIns))
4795	PDMDevHlpSetAsyncNotification(pDevIns, lsilogicR3IsAsyncSuspendOrPowerOffDone);
4796	else
4797	{
4798	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
4799
4800	AssertMsg(!pThis->fNotificationSent, ("The PDM Queue should be empty at this point\n"));
4801	}
4802
4803	for (uint32_t i = 0; i < pThis->cDeviceStates; i++)
4804	{
4805	PLSILOGICDEVICE pThisDevice = &pThisCC->paDeviceStates[i];
4806	if (pThisDevice->pDrvMediaEx)
4807	pThisDevice->pDrvMediaEx->pfnNotifySuspend(pThisDevice->pDrvMediaEx);
4808	}
4809	}
4810
4811	/**
4812	* @interface_method_impl{PDMDEVREG,pfnSuspend}
4813	*/
4814	static DECLCALLBACK(void) lsilogicR3Suspend(PPDMDEVINS pDevIns)
4815	{
4816	Log(("lsilogicR3Suspend\n"));
4817	lsilogicR3SuspendOrPowerOff(pDevIns);
4818	}
4819
4820	/**
4821	* @interface_method_impl{PDMDEVREG,pfnResume}
4822	*/
4823	static DECLCALLBACK(void) lsilogicR3Resume(PPDMDEVINS pDevIns)
4824	{
4825	PLSILOGICSCSI pThis = PDMDEVINS_2_DATA(pDevIns, PLSILOGICSCSI);
4826
4827	Log(("lsilogicR3Resume\n"));
4828
4829	lsilogicR3Kick(pDevIns, pThis);
4830	}
4831
4832	/**
4833	* @interface_method_impl{PDMDEVREG,pfnDetach}
4834	*
4835	* One harddisk at one port has been unplugged.
4836	* The VM is suspended at this point.
4837	*/
4838	static DECLCALLBACK(void) lsilogicR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4839	{
4840	PLSILOGICSCSI pThis = PDMDEVINS_2_DATA(pDevIns, PLSILOGICSCSI);
4841	PLSILOGICSCSICC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PLSILOGICSCSICC);
4842	Log(("%s: iLUN=%#x\n", __FUNCTION__, iLUN));
4843	RT_NOREF(fFlags);
4844
4845	AssertMsg(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG, ("LsiLogic: Device does not support hotplugging\n"));
4846
4847	if (iLUN >= pThis->cDeviceStates)
4848	return;
4849
4850	/*
4851	* Zero some important members.
4852	*/
4853	PLSILOGICDEVICE pDevice = &pThisCC->paDeviceStates[iLUN];
4854	pDevice->pDrvBase = NULL;
4855	pDevice->pDrvMedia = NULL;
4856	pDevice->pDrvMediaEx = NULL;
4857	}
4858
4859	/**
4860	* @interface_method_impl{PDMDEVREG,pfnAttach}
4861	*/
4862	static DECLCALLBACK(int) lsilogicR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4863	{
4864	PLSILOGICSCSI pThis = PDMDEVINS_2_DATA(pDevIns, PLSILOGICSCSI);
4865	PLSILOGICSCSICC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PLSILOGICSCSICC);
4866	PLSILOGICDEVICE pDevice = &pThisCC->paDeviceStates[iLUN];
4867	int rc;
4868
4869	if (iLUN >= pThis->cDeviceStates)
4870	return VERR_PDM_LUN_NOT_FOUND;
4871
4872	AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
4873	("LsiLogic: Device does not support hotplugging\n"),
4874	VERR_INVALID_PARAMETER);
4875
4876	/* the usual paranoia */
4877	AssertRelease(!pDevice->pDrvBase);
4878	AssertRelease(!pDevice->pDrvMedia);
4879	AssertRelease(!pDevice->pDrvMediaEx);
4880	Assert(pDevice->iLUN == iLUN);
4881
4882	/*
4883	* Try attach the block device and get the interfaces,
4884	* required as well as optional.
4885	*/
4886	rc = PDMDevHlpDriverAttach(pDevIns, pDevice->iLUN, &pDevice->IBase, &pDevice->pDrvBase, NULL);
4887	if (RT_SUCCESS(rc))
4888	{
4889	/* Query the media interface. */
4890	pDevice->pDrvMedia = PDMIBASE_QUERY_INTERFACE(pDevice->pDrvBase, PDMIMEDIA);
4891	AssertMsgReturn(VALID_PTR(pDevice->pDrvMedia),
4892	("LsiLogic configuration error: LUN#%d misses the basic media interface!\n", pDevice->iLUN),
4893	VERR_PDM_MISSING_INTERFACE);
4894
4895	/* Get the extended media interface. */
4896	pDevice->pDrvMediaEx = PDMIBASE_QUERY_INTERFACE(pDevice->pDrvBase, PDMIMEDIAEX);
4897	AssertMsgReturn(VALID_PTR(pDevice->pDrvMediaEx),
4898	("LsiLogic configuration error: LUN#%d misses the extended media interface!\n", pDevice->iLUN),
4899	VERR_PDM_MISSING_INTERFACE);
4900
4901	rc = pDevice->pDrvMediaEx->pfnIoReqAllocSizeSet(pDevice->pDrvMediaEx, sizeof(LSILOGICREQ));
4902	AssertMsgRCReturn(rc, ("LsiLogic configuration error: LUN#%u: Failed to set I/O request size!", pDevice->iLUN),
4903	rc);
4904	}
4905	else
4906	AssertMsgFailed(("Failed to attach LUN#%d. rc=%Rrc\n", pDevice->iLUN, rc));
4907
4908	if (RT_FAILURE(rc))
4909	{
4910	pDevice->pDrvBase = NULL;
4911	pDevice->pDrvMedia = NULL;
4912	pDevice->pDrvMediaEx = NULL;
4913	}
4914	return rc;
4915	}
4916
4917	/**
4918	* Common reset worker.
4919	*
4920	* @param pDevIns The device instance data.
4921	*/
4922	static void lsilogicR3ResetCommon(PPDMDEVINS pDevIns)
4923	{
4924	PLSILOGICSCSI pThis = PDMDEVINS_2_DATA(pDevIns, PLSILOGICSCSI);
4925	PLSILOGICSCSICC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PLSILOGICSCSICC);
4926	int rc;
4927
4928	rc = lsilogicR3HardReset(pDevIns, pThis, pThisCC);
4929	AssertRC(rc);
4930	}
4931
4932	/**
4933	* @callback_method_impl{FNPDMDEVASYNCNOTIFY,
4934	* Callback employed by lsilogicR3Reset.}
4935	*/
4936	static DECLCALLBACK(bool) lsilogicR3IsAsyncResetDone(PPDMDEVINS pDevIns)
4937	{
4938	PLSILOGICSCSI pThis = PDMDEVINS_2_DATA(pDevIns, PLSILOGICSCSI);
4939
4940	if (!lsilogicR3AllAsyncIOIsFinished(pDevIns))
4941	return false;
4942	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
4943
4944	lsilogicR3ResetCommon(pDevIns);
4945	return true;
4946	}
4947
4948	/**
4949	* @interface_method_impl{PDMDEVREG,pfnReset}
4950	*/
4951	static DECLCALLBACK(void) lsilogicR3Reset(PPDMDEVINS pDevIns)
4952	{
4953	PLSILOGICSCSI pThis = PDMDEVINS_2_DATA(pDevIns, PLSILOGICSCSI);
4954
4955	ASMAtomicWriteBool(&pThis->fSignalIdle, true);
4956	if (!lsilogicR3AllAsyncIOIsFinished(pDevIns))
4957	PDMDevHlpSetAsyncNotification(pDevIns, lsilogicR3IsAsyncResetDone);
4958	else
4959	{
4960	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
4961	lsilogicR3ResetCommon(pDevIns);
4962	}
4963	}
4964
4965	/**
4966	* @interface_method_impl{PDMDEVREG,pfnPowerOff}
4967	*/
4968	static DECLCALLBACK(void) lsilogicR3PowerOff(PPDMDEVINS pDevIns)
4969	{
4970	Log(("lsilogicR3PowerOff\n"));
4971	lsilogicR3SuspendOrPowerOff(pDevIns);
4972	}
4973
4974	/**
4975	* @interface_method_impl{PDMDEVREG,pfnDestruct}
4976	*/
4977	static DECLCALLBACK(int) lsilogicR3Destruct(PPDMDEVINS pDevIns)
4978	{
4979	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
4980	PLSILOGICSCSI pThis = PDMDEVINS_2_DATA(pDevIns, PLSILOGICSCSI);
4981	PLSILOGICSCSICC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PLSILOGICSCSICC);
4982
4983	PDMDevHlpCritSectDelete(pDevIns, &pThis->ReplyFreeQueueCritSect);
4984	PDMDevHlpCritSectDelete(pDevIns, &pThis->ReplyPostQueueCritSect);
4985	PDMDevHlpCritSectDelete(pDevIns, &pThis->RequestQueueCritSect);
4986	PDMDevHlpCritSectDelete(pDevIns, &pThis->ReplyFreeQueueWriteCritSect);
4987
4988	if (RTCritSectIsInitialized(&pThisCC->CritSectMemRegns))
4989	RTCritSectDelete(&pThisCC->CritSectMemRegns);
4990
4991	RTMemFree(pThisCC->paDeviceStates);
4992	pThisCC->paDeviceStates = NULL;
4993
4994	if (pThis->hEvtProcess != NIL_SUPSEMEVENT)
4995	{
4996	PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtProcess);
4997	pThis->hEvtProcess = NIL_SUPSEMEVENT;
4998	}
4999
5000	lsilogicR3ConfigurationPagesFree(pThis, pThisCC);
5001	lsilogicR3MemRegionsFree(pThisCC);
5002	return VINF_SUCCESS;
5003	}
5004
5005	/**
5006	* @interface_method_impl{PDMDEVREG,pfnConstruct}
5007	*/
5008	static DECLCALLBACK(int) lsilogicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
5009	{
5010	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5011	PLSILOGICSCSI pThis = PDMDEVINS_2_DATA(pDevIns, PLSILOGICSCSI);
5012	PLSILOGICSCSICC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PLSILOGICSCSICC);
5013	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5014	int rc = VINF_SUCCESS;
5015
5016	/*
5017	* Initialize enought of the state to make the destructure not trip up.
5018	*/
5019	pThis->hEvtProcess = NIL_SUPSEMEVENT;
5020	RTListInit(&pThisCC->ListMemRegns);
5021	pThis->hMmioReg = NIL_IOMMMIOHANDLE;
5022	pThis->hMmioDiag = NIL_IOMMMIOHANDLE;
5023	pThis->hIoPortsReg = NIL_IOMIOPORTHANDLE;
5024	pThis->hIoPortsBios = NIL_IOMIOPORTHANDLE;
5025	pThisCC->pDevIns = pDevIns;
5026	pThisCC->IBase.pfnQueryInterface = lsilogicR3StatusQueryInterface;
5027	pThisCC->ILeds.pfnQueryStatusLed = lsilogicR3StatusQueryStatusLed;
5028
5029
5030	/*
5031	* Validate and read configuration.
5032	*/
5033	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns,
5034	"ReplyQueueDepth\|"
5035	"RequestQueueDepth\|"
5036	"ControllerType\|"
5037	"NumPorts\|"
5038	"Bootable", /* Keep it for legacy configs, even though it doesn't do anything anymore, see @bugref{4841}. */
5039	"");
5040
5041	rc = pHlp->pfnCFGMQueryU32Def(pCfg, "ReplyQueueDepth",
5042	&pThis->cReplyQueueEntries, LSILOGICSCSI_REPLY_QUEUE_DEPTH_DEFAULT);
5043	if (RT_FAILURE(rc))
5044	return PDMDEV_SET_ERROR(pDevIns, rc,
5045	N_("LsiLogic configuration error: failed to read ReplyQueue as integer"));
5046	if ( pThis->cReplyQueueEntries < LSILOGICSCSI_REPLY_QUEUE_DEPTH_MIN
5047	\|\| pThis->cReplyQueueEntries > LSILOGICSCSI_REPLY_QUEUE_DEPTH_MAX - 1 /* see +1 later in the function */)
5048	return PDMDevHlpVMSetError(pDevIns, VERR_OUT_OF_RANGE, RT_SRC_POS,
5049	N_("LsiLogic configuration error: 'ReplyQueueDepth' = %u is out of ranage (%u..%u)"),
5050	pThis->cReplyQueueEntries, LSILOGICSCSI_REPLY_QUEUE_DEPTH_MIN,
5051	LSILOGICSCSI_REPLY_QUEUE_DEPTH_MAX - 1);
5052	Log(("%s: ReplyQueueDepth=%u\n", __FUNCTION__, pThis->cReplyQueueEntries));
5053
5054	rc = pHlp->pfnCFGMQueryU32Def(pCfg, "RequestQueueDepth",
5055	&pThis->cRequestQueueEntries, LSILOGICSCSI_REQUEST_QUEUE_DEPTH_DEFAULT);
5056	if (RT_FAILURE(rc))
5057	return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic configuration error: failed to read RequestQueue as integer"));
5058	if ( pThis->cRequestQueueEntries < LSILOGICSCSI_REQUEST_QUEUE_DEPTH_MIN
5059	\|\| pThis->cRequestQueueEntries > LSILOGICSCSI_REQUEST_QUEUE_DEPTH_MAX - 1 /* see +1 later in the function */)
5060	return PDMDevHlpVMSetError(pDevIns, VERR_OUT_OF_RANGE, RT_SRC_POS,
5061	N_("LsiLogic configuration error: 'RequestQueue' = %u is out of ranage (%u..%u)"),
5062	pThis->cRequestQueueEntries, LSILOGICSCSI_REQUEST_QUEUE_DEPTH_MIN,
5063	LSILOGICSCSI_REQUEST_QUEUE_DEPTH_MIN - 1);
5064	Log(("%s: RequestQueueDepth=%u\n", __FUNCTION__, pThis->cRequestQueueEntries));
5065
5066	char szCtrlType[64];
5067	rc = pHlp->pfnCFGMQueryStringDef(pCfg, "ControllerType", szCtrlType, sizeof(szCtrlType), LSILOGICSCSI_PCI_SPI_CTRLNAME);
5068	if (RT_FAILURE(rc))
5069	return PDMDEV_SET_ERROR(pDevIns, rc,
5070	N_("LsiLogic configuration error: failed to read ControllerType as string"));
5071	Log(("%s: ControllerType=%s\n", __FUNCTION__, szCtrlType));
5072	rc = lsilogicR3GetCtrlTypeFromString(pThis, szCtrlType);
5073	if (RT_FAILURE(rc))
5074	return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic configuration error: failed to determine controller type from string"));
5075
5076	char szDevTag[20];
5077	RTStrPrintf(szDevTag, sizeof(szDevTag), "LSILOGIC%s-%u",
5078	pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI ? "SPI" : "SAS",
5079	iInstance);
5080
5081	rc = pHlp->pfnCFGMQueryU8(pCfg, "NumPorts", &pThis->cPorts);
5082	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
5083	{
5084	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
5085	pThis->cPorts = LSILOGICSCSI_PCI_SPI_PORTS_MAX;
5086	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
5087	pThis->cPorts = LSILOGICSCSI_PCI_SAS_PORTS_DEFAULT;
5088	else
5089	AssertMsgFailed(("Invalid controller type: %d\n", pThis->enmCtrlType));
5090	}
5091	else if (RT_FAILURE(rc))
5092	return PDMDEV_SET_ERROR(pDevIns, rc,
5093	N_("LsiLogic configuration error: failed to read NumPorts as integer"));
5094
5095	/* Init static parts. */
5096	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
5097	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
5098
5099	PDMPciDevSetVendorId(pPciDev, LSILOGICSCSI_PCI_VENDOR_ID); /* LsiLogic */
5100	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
5101	{
5102	PDMPciDevSetDeviceId(pPciDev, LSILOGICSCSI_PCI_SPI_DEVICE_ID); /* LSI53C1030 */
5103	PDMPciDevSetSubSystemVendorId(pPciDev, LSILOGICSCSI_PCI_SPI_SUBSYSTEM_VENDOR_ID);
5104	PDMPciDevSetSubSystemId(pPciDev, LSILOGICSCSI_PCI_SPI_SUBSYSTEM_ID);
5105	}
5106	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
5107	{
5108	PDMPciDevSetDeviceId(pPciDev, LSILOGICSCSI_PCI_SAS_DEVICE_ID); /* SAS1068 */
5109	PDMPciDevSetSubSystemVendorId(pPciDev, LSILOGICSCSI_PCI_SAS_SUBSYSTEM_VENDOR_ID);
5110	PDMPciDevSetSubSystemId(pPciDev, LSILOGICSCSI_PCI_SAS_SUBSYSTEM_ID);
5111	}
5112	else
5113	AssertMsgFailed(("Invalid controller type: %d\n", pThis->enmCtrlType));
5114
5115	PDMPciDevSetClassProg(pPciDev, 0x00); /* SCSI */
5116	PDMPciDevSetClassSub(pPciDev, 0x00); /* SCSI */
5117	PDMPciDevSetClassBase(pPciDev, 0x01); /* Mass storage */
5118	PDMPciDevSetInterruptPin(pPciDev, 0x01); /* Interrupt pin A */
5119
5120	# ifdef VBOX_WITH_MSI_DEVICES
5121	PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST);
5122	PDMPciDevSetCapabilityList(pPciDev, 0x80);
5123	# endif
5124
5125	/*
5126	* Create critical sections protecting the reply post and free queues.
5127	*/
5128	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->ReplyFreeQueueCritSect, RT_SRC_POS, "%sRFQ", szDevTag);
5129	if (RT_FAILURE(rc))
5130	return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic: cannot create critical section for reply free queue"));
5131
5132	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->ReplyPostQueueCritSect, RT_SRC_POS, "%sRPQ", szDevTag);
5133	if (RT_FAILURE(rc))
5134	return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic: cannot create critical section for reply post queue"));
5135
5136	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->RequestQueueCritSect, RT_SRC_POS, "%sRQ", szDevTag);
5137	if (RT_FAILURE(rc))
5138	return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic: cannot create critical section for request queue"));
5139
5140	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->ReplyFreeQueueWriteCritSect, RT_SRC_POS, "%sRFQW", szDevTag);
5141	if (RT_FAILURE(rc))
5142	return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic: cannot create critical section for reply free queue write access"));
5143
5144	/*
5145	* Critical section protecting the memory regions.
5146	*/
5147	rc = RTCritSectInit(&pThisCC->CritSectMemRegns);
5148	if (RT_FAILURE(rc))
5149	return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic: Failed to initialize critical section protecting the memory regions"));
5150
5151	/*
5152	* Register the PCI device, it's I/O regions.
5153	*/
5154	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
5155	if (RT_FAILURE(rc))
5156	return rc;
5157
5158	# ifdef VBOX_WITH_MSI_DEVICES
5159	PDMMSIREG MsiReg;
5160	RT_ZERO(MsiReg);
5161	/* use this code for MSI-X support */
5162	# if 0
5163	MsiReg.cMsixVectors = 1;
5164	MsiReg.iMsixCapOffset = 0x80;
5165	MsiReg.iMsixNextOffset = 0x00;
5166	MsiReg.iMsixBar = 3;
5167	Assert(pDevIns->pReg->cMaxMsixVectors >= MsiReg.cMsixVectors); /* fix device registration when enabling this */
5168	# else
5169	MsiReg.cMsiVectors = 1;
5170	MsiReg.iMsiCapOffset = 0x80;
5171	MsiReg.iMsiNextOffset = 0x00;
5172	# endif
5173	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
5174	if (RT_FAILURE (rc))
5175	{
5176	/* That's OK, we can work without MSI */
5177	PDMPciDevSetCapabilityList(pPciDev, 0x0);
5178	}
5179	# endif
5180
5181	/* Region #0: I/O ports. */
5182	rc = PDMDevHlpPCIIORegionCreateIo(pDevIns, 0 /iPciRegion/, LSILOGIC_PCI_SPACE_IO_SIZE,
5183	lsilogicIOPortWrite, lsilogicIOPortRead, NULL /pvUser/,
5184	pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI ? "LsiLogic" : "LsiLogicSas",
5185	NULL /paExtDesc/, &pThis->hIoPortsReg);
5186	AssertRCReturn(rc, rc);
5187
5188	/* Region #1: MMIO.
5189	*
5190	* Non-4-byte read access to LSILOGIC_REG_REPLY_QUEUE may cause real strange behavior
5191	* because the data is part of a physical guest address. But some drivers use 1-byte
5192	* access to scan for SCSI controllers. So, we simplify our code by telling IOM to
5193	* read DWORDs.
5194	*
5195	* Regarding writes, we couldn't find anything specific in the specs about what should
5196	* happen. So far we've ignored unaligned writes and assumed the missing bytes of
5197	* byte and word access to be zero. We suspect that IOMMMIO_FLAGS_WRITE_ONLY_DWORD
5198	* or IOMMMIO_FLAGS_WRITE_DWORD_ZEROED would be the most appropriate here, but since we
5199	* don't have real hw to test one, the old behavior is kept exactly like it used to be.
5200	*/
5201	/** @todo Check out unaligned writes and non-dword writes on real LsiLogic
5202	* hardware. */
5203	rc = PDMDevHlpPCIIORegionCreateMmio(pDevIns, 1 /iPciRegion/, LSILOGIC_PCI_SPACE_MEM_SIZE, PCI_ADDRESS_SPACE_MEM,
5204	lsilogicMMIOWrite, lsilogicMMIORead, NULL /pvUser/,
5205	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
5206	pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI ? "LsiLogic" : "LsiLogicSas",
5207	&pThis->hMmioReg);
5208	AssertRCReturn(rc, rc);
5209
5210	/* Region #2: MMIO - Diag. */
5211	rc = PDMDevHlpPCIIORegionCreateMmio(pDevIns, 2 /iPciRegion/, LSILOGIC_PCI_SPACE_MEM_SIZE, PCI_ADDRESS_SPACE_MEM,
5212	lsilogicDiagnosticWrite, lsilogicDiagnosticRead, NULL /pvUser/,
5213	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
5214	pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI ? "LsiLogicDiag" : "LsiLogicSasDiag",
5215	&pThis->hMmioDiag);
5216	AssertRCReturn(rc, rc);
5217
5218	/*
5219	* We need one entry free in the queue.
5220	*/
5221	pThis->cReplyQueueEntries++;
5222	AssertLogRelReturn(pThis->cReplyQueueEntries <= RT_ELEMENTS(pThis->aReplyFreeQueue), VERR_INTERNAL_ERROR_3);
5223	AssertLogRelReturn(pThis->cReplyQueueEntries <= RT_ELEMENTS(pThis->aReplyPostQueue), VERR_INTERNAL_ERROR_3);
5224
5225	pThis->cRequestQueueEntries++;
5226	AssertLogRelReturn(pThis->cRequestQueueEntries <= RT_ELEMENTS(pThis->aRequestQueue), VERR_INTERNAL_ERROR_3);
5227
5228	/*
5229	* Device states.
5230	*/
5231	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
5232	pThis->cDeviceStates = pThis->cPorts * LSILOGICSCSI_PCI_SPI_DEVICES_PER_BUS_MAX;
5233	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
5234	pThis->cDeviceStates = pThis->cPorts * LSILOGICSCSI_PCI_SAS_DEVICES_PER_PORT_MAX;
5235	else
5236	AssertLogRelMsgFailedReturn(("Invalid controller type: %d\n", pThis->enmCtrlType), VERR_INTERNAL_ERROR_4);
5237
5238	/*
5239	* Create event semaphore and worker thread.
5240	*/
5241	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->pThreadWrk, pThis, lsilogicR3Worker,
5242	lsilogicR3WorkerWakeUp, 0, RTTHREADTYPE_IO, szDevTag);
5243	if (RT_FAILURE(rc))
5244	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
5245	N_("LsiLogic: Failed to create worker thread %s"), szDevTag);
5246
5247	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtProcess);
5248	if (RT_FAILURE(rc))
5249	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
5250	N_("LsiLogic: Failed to create SUP event semaphore"));
5251
5252	/*
5253	* Allocate device states.
5254	*/
5255	pThisCC->paDeviceStates = (PLSILOGICDEVICE)RTMemAllocZ(sizeof(LSILOGICDEVICE) * pThis->cDeviceStates);
5256	if (!pThisCC->paDeviceStates)
5257	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to allocate memory for device states"));
5258
5259	for (unsigned i = 0; i < pThis->cDeviceStates; i++)
5260	{
5261	PLSILOGICDEVICE pDevice = &pThisCC->paDeviceStates[i];
5262
5263	/* Initialize static parts of the device. */
5264	pDevice->iLUN = i;
5265	pDevice->pDevIns = pDevIns;
5266	pDevice->Led.u32Magic = PDMLED_MAGIC;
5267	pDevice->IBase.pfnQueryInterface = lsilogicR3DeviceQueryInterface;
5268	pDevice->IMediaPort.pfnQueryDeviceLocation = lsilogicR3QueryDeviceLocation;
5269	pDevice->IMediaExPort.pfnIoReqCompleteNotify = lsilogicR3IoReqCompleteNotify;
5270	pDevice->IMediaExPort.pfnIoReqCopyFromBuf = lsilogicR3IoReqCopyFromBuf;
5271	pDevice->IMediaExPort.pfnIoReqCopyToBuf = lsilogicR3IoReqCopyToBuf;
5272	pDevice->IMediaExPort.pfnIoReqQueryBuf = NULL;
5273	pDevice->IMediaExPort.pfnIoReqQueryDiscardRanges = NULL;
5274	pDevice->IMediaExPort.pfnIoReqStateChanged = lsilogicR3IoReqStateChanged;
5275	pDevice->IMediaExPort.pfnMediumEjected = lsilogicR3MediumEjected;
5276	pDevice->ILed.pfnQueryStatusLed = lsilogicR3DeviceQueryStatusLed;
5277	RTStrPrintf(pDevice->szName, sizeof(pDevice->szName), "Device%u", i);
5278
5279	/* Attach SCSI driver. */
5280	rc = PDMDevHlpDriverAttach(pDevIns, pDevice->iLUN, &pDevice->IBase, &pDevice->pDrvBase, pDevice->szName);
5281	if (RT_SUCCESS(rc))
5282	{
5283	/* Query the media interface. */
5284	pDevice->pDrvMedia = PDMIBASE_QUERY_INTERFACE(pDevice->pDrvBase, PDMIMEDIA);
5285	AssertMsgReturn(VALID_PTR(pDevice->pDrvMedia),
5286	("LsiLogic configuration error: LUN#%d misses the basic media interface!\n", pDevice->iLUN),
5287	VERR_PDM_MISSING_INTERFACE);
5288
5289	/* Get the extended media interface. */
5290	pDevice->pDrvMediaEx = PDMIBASE_QUERY_INTERFACE(pDevice->pDrvBase, PDMIMEDIAEX);
5291	AssertMsgReturn(VALID_PTR(pDevice->pDrvMediaEx),
5292	("LsiLogic configuration error: LUN#%d misses the extended media interface!\n", pDevice->iLUN),
5293	VERR_PDM_MISSING_INTERFACE);
5294
5295	rc = pDevice->pDrvMediaEx->pfnIoReqAllocSizeSet(pDevice->pDrvMediaEx, sizeof(LSILOGICREQ));
5296	if (RT_FAILURE(rc))
5297	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
5298	N_("LsiLogic configuration error: LUN#%u: Failed to set I/O request size!"),
5299	pDevice->iLUN);
5300	}
5301	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5302	{
5303	pDevice->pDrvBase = NULL;
5304	rc = VINF_SUCCESS;
5305	Log(("LsiLogic: no driver attached to device %s\n", pDevice->szName));
5306	}
5307	else
5308	{
5309	AssertLogRelMsgFailed(("LsiLogic: Failed to attach %s\n", pDevice->szName));
5310	return rc;
5311	}
5312	}
5313
5314	/*
5315	* Attach status driver (optional).
5316	*/
5317	PPDMIBASE pBase;
5318	rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThisCC->IBase, &pBase, "Status Port");
5319	if (RT_SUCCESS(rc))
5320	{
5321	pThisCC->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
5322	pThisCC->pMediaNotify = PDMIBASE_QUERY_INTERFACE(pBase, PDMIMEDIANOTIFY);
5323	}
5324	else
5325	AssertMsgReturn(rc == VERR_PDM_NO_ATTACHED_DRIVER,
5326	("Failed to attach to status driver. rc=%Rrc\n", rc),
5327	PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic cannot attach to status driver")));
5328
5329	/* Register save state handlers. */
5330	rc = PDMDevHlpSSMRegisterEx(pDevIns, LSILOGIC_SAVED_STATE_VERSION, sizeof(*pThis), NULL,
5331	NULL, lsilogicR3LiveExec, NULL,
5332	NULL, lsilogicR3SaveExec, NULL,
5333	NULL, lsilogicR3LoadExec, lsilogicR3LoadDone);
5334	if (RT_FAILURE(rc))
5335	return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic cannot register save state handlers"));
5336
5337	pThis->enmWhoInit = LSILOGICWHOINIT_SYSTEM_BIOS;
5338
5339	/*
5340	* Register the info item.
5341	*/
5342	char szTmp[128];
5343	RTStrPrintf(szTmp, sizeof(szTmp), "%s%u", pDevIns->pReg->szName, pDevIns->iInstance);
5344	PDMDevHlpDBGFInfoRegister(pDevIns, szTmp,
5345	pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI
5346	? "LsiLogic SPI info."
5347	: "LsiLogic SAS info.", lsilogicR3Info);
5348
5349	/* Allocate configuration pages. */
5350	rc = lsilogicR3ConfigurationPagesAlloc(pThis, pThisCC);
5351	if (RT_FAILURE(rc))
5352	PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic: Failed to allocate memory for configuration pages"));
5353
5354	/* Perform hard reset. */
5355	rc = lsilogicR3HardReset(pDevIns, pThis, pThisCC);
5356	AssertRC(rc);
5357
5358	return rc;
5359	}
5360
5361	#else /* !IN_RING3 */
5362
5363	/**
5364	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
5365	*/
5366	static DECLCALLBACK(int) lsilogicRZConstruct(PPDMDEVINS pDevIns)
5367	{
5368	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5369	PLSILOGICSCSI pThis = PDMDEVINS_2_DATA(pDevIns, PLSILOGICSCSI);
5370
5371	/* Setup callbacks for this context: */
5372	int rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortsReg, lsilogicIOPortWrite, lsilogicIOPortRead, NULL /pvUser/);
5373	AssertRCReturn(rc, rc);
5374
5375	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmioReg, lsilogicMMIOWrite, lsilogicMMIORead, NULL /pvUser/);
5376	AssertRCReturn(rc, rc);
5377
5378	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmioDiag, lsilogicDiagnosticWrite, lsilogicDiagnosticRead, NULL /pvUser/);
5379	AssertRCReturn(rc, rc);
5380
5381	return VINF_SUCCESS;
5382	}
5383
5384	#endif /* !IN_RING3 */
5385
5386	/**
5387	* The device registration structure - SPI SCSI controller.
5388	*/
5389	const PDMDEVREG g_DeviceLsiLogicSCSI =
5390	{
5391	/* .u32Version = */ PDM_DEVREG_VERSION,
5392	/* .uReserved0 = */ 0,
5393	/* .szName = */ "lsilogicscsi",
5394	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE
5395	\| PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION \| PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION,
5396	/* .fClass = */ PDM_DEVREG_CLASS_STORAGE,
5397	/* .cMaxInstances = */ ~0U,
5398	/* .uSharedVersion = */ 42,
5399	/* .cbInstanceShared = */ sizeof(LSILOGICSCSI),
5400	/* .cbInstanceCC = */ sizeof(LSILOGICSCSICC),
5401	/* .cbInstanceRC = */ sizeof(LSILOGICSCSIRC),
5402	/* .cMaxPciDevices = */ 1,
5403	/* .cMaxMsixVectors = */ 0,
5404	/* .pszDescription = */ "LSI Logic 53c1030 SCSI controller.\n",
5405	#if defined(IN_RING3)
5406	/* .pszRCMod = */ "VBoxDDRC.rc",
5407	/* .pszR0Mod = */ "VBoxDDR0.r0",
5408	/* .pfnConstruct = */ lsilogicR3Construct,
5409	/* .pfnDestruct = */ lsilogicR3Destruct,
5410	/* .pfnRelocate = */ NULL,
5411	/* .pfnMemSetup = */ NULL,
5412	/* .pfnPowerOn = */ NULL,
5413	/* .pfnReset = */ lsilogicR3Reset,
5414	/* .pfnSuspend = */ lsilogicR3Suspend,
5415	/* .pfnResume = */ lsilogicR3Resume,
5416	/* .pfnAttach = */ lsilogicR3Attach,
5417	/* .pfnDetach = */ lsilogicR3Detach,
5418	/* .pfnQueryInterface = */ NULL,
5419	/* .pfnInitComplete = */ NULL,
5420	/* .pfnPowerOff = */ lsilogicR3PowerOff,
5421	/* .pfnSoftReset = */ NULL,
5422	/* .pfnReserved0 = */ NULL,
5423	/* .pfnReserved1 = */ NULL,
5424	/* .pfnReserved2 = */ NULL,
5425	/* .pfnReserved3 = */ NULL,
5426	/* .pfnReserved4 = */ NULL,
5427	/* .pfnReserved5 = */ NULL,
5428	/* .pfnReserved6 = */ NULL,
5429	/* .pfnReserved7 = */ NULL,
5430	#elif defined(IN_RING0)
5431	/* .pfnEarlyConstruct = */ NULL,
5432	/* .pfnConstruct = */ lsilogicRZConstruct,
5433	/* .pfnDestruct = */ NULL,
5434	/* .pfnFinalDestruct = */ NULL,
5435	/* .pfnRequest = */ NULL,
5436	/* .pfnReserved0 = */ NULL,
5437	/* .pfnReserved1 = */ NULL,
5438	/* .pfnReserved2 = */ NULL,
5439	/* .pfnReserved3 = */ NULL,
5440	/* .pfnReserved4 = */ NULL,
5441	/* .pfnReserved5 = */ NULL,
5442	/* .pfnReserved6 = */ NULL,
5443	/* .pfnReserved7 = */ NULL,
5444	#elif defined(IN_RC)
5445	/* .pfnConstruct = */ lsilogicRZConstruct,
5446	/* .pfnReserved0 = */ NULL,
5447	/* .pfnReserved1 = */ NULL,
5448	/* .pfnReserved2 = */ NULL,
5449	/* .pfnReserved3 = */ NULL,
5450	/* .pfnReserved4 = */ NULL,
5451	/* .pfnReserved5 = */ NULL,
5452	/* .pfnReserved6 = */ NULL,
5453	/* .pfnReserved7 = */ NULL,
5454	#else
5455	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
5456	#endif
5457	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
5458	};
5459
5460	/**
5461	* The device registration structure - SAS controller.
5462	*/
5463	const PDMDEVREG g_DeviceLsiLogicSAS =
5464	{
5465	/* .u32Version = */ PDM_DEVREG_VERSION,
5466	/* .uReserved0 = */ 0,
5467	/* .szName = */ "lsilogicsas",
5468	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE
5469	\| PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION \| PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION
5470	\| PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION,
5471	/* .fClass = */ PDM_DEVREG_CLASS_STORAGE,
5472	/* .cMaxInstances = */ ~0U,
5473	/* .uSharedVersion = */ 42,
5474	/* .cbInstanceShared = */ sizeof(LSILOGICSCSI),
5475	/* .cbInstanceCC = */ sizeof(LSILOGICSCSICC),
5476	/* .cbInstanceRC = */ sizeof(LSILOGICSCSIRC),
5477	/* .cMaxPciDevices = */ 1,
5478	/* .cMaxMsixVectors = */ 0,
5479	/* .pszDescription = */ "LSI Logic SAS1068 controller.\n",
5480	#if defined(IN_RING3)
5481	/* .pszRCMod = */ "VBoxDDRC.rc",
5482	/* .pszR0Mod = */ "VBoxDDR0.r0",
5483	/* .pfnConstruct = */ lsilogicR3Construct,
5484	/* .pfnDestruct = */ lsilogicR3Destruct,
5485	/* .pfnRelocate = */ NULL,
5486	/* .pfnMemSetup = */ NULL,
5487	/* .pfnPowerOn = */ NULL,
5488	/* .pfnReset = */ lsilogicR3Reset,
5489	/* .pfnSuspend = */ lsilogicR3Suspend,
5490	/* .pfnResume = */ lsilogicR3Resume,
5491	/* .pfnAttach = */ lsilogicR3Attach,
5492	/* .pfnDetach = */ lsilogicR3Detach,
5493	/* .pfnQueryInterface = */ NULL,
5494	/* .pfnInitComplete = */ NULL,
5495	/* .pfnPowerOff = */ lsilogicR3PowerOff,
5496	/* .pfnSoftReset = */ NULL,
5497	/* .pfnReserved0 = */ NULL,
5498	/* .pfnReserved1 = */ NULL,
5499	/* .pfnReserved2 = */ NULL,
5500	/* .pfnReserved3 = */ NULL,
5501	/* .pfnReserved4 = */ NULL,
5502	/* .pfnReserved5 = */ NULL,
5503	/* .pfnReserved6 = */ NULL,
5504	/* .pfnReserved7 = */ NULL,
5505	#elif defined(IN_RING0)
5506	/* .pfnEarlyConstruct = */ NULL,
5507	/* .pfnConstruct = */ lsilogicRZConstruct,
5508	/* .pfnDestruct = */ NULL,
5509	/* .pfnFinalDestruct = */ NULL,
5510	/* .pfnRequest = */ NULL,
5511	/* .pfnReserved0 = */ NULL,
5512	/* .pfnReserved1 = */ NULL,
5513	/* .pfnReserved2 = */ NULL,
5514	/* .pfnReserved3 = */ NULL,
5515	/* .pfnReserved4 = */ NULL,
5516	/* .pfnReserved5 = */ NULL,
5517	/* .pfnReserved6 = */ NULL,
5518	/* .pfnReserved7 = */ NULL,
5519	#elif defined(IN_RC)
5520	/* .pfnConstruct = */ lsilogicRZConstruct,
5521	/* .pfnReserved0 = */ NULL,
5522	/* .pfnReserved1 = */ NULL,
5523	/* .pfnReserved2 = */ NULL,
5524	/* .pfnReserved3 = */ NULL,
5525	/* .pfnReserved4 = */ NULL,
5526	/* .pfnReserved5 = */ NULL,
5527	/* .pfnReserved6 = */ NULL,
5528	/* .pfnReserved7 = */ NULL,
5529	#else
5530	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
5531	#endif
5532	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
5533	};
5534
5535	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Storage/DevLsiLogicSCSI.cpp@ 90330

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