VirtualBox

source: vbox/trunk/src/VBox/Devices/Storage/DevLsiLogicSCSI.h@ 56622

Last change on this file since 56622 was 56292, checked in by vboxsync, 10 years ago

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1/* $Id: DevLsiLogicSCSI.h 56292 2015-06-09 14:20:46Z vboxsync $ */
2/** @file
3 * VBox storage devices: LsiLogic LSI53c1030 SCSI controller - Defines and structures.
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17#ifndef __DEVLSILOGICSCSI_H__
18#define __DEVLSILOGICSCSI_H__
19
20#include <iprt/stdint.h>
21
22/*
23 * Custom fixed I/O ports for BIOS controller access. Note that these should
24 * not be in the ISA range (below 400h) to avoid conflicts with ISA device
25 * probing. Addresses in the 300h-340h range should be especially avoided.
26 */
27#define LSILOGIC_BIOS_IO_PORT 0x434
28#define LSILOGIC_SAS_BIOS_IO_PORT 0x438
29
30#define LSILOGICSCSI_REQUEST_QUEUE_DEPTH_DEFAULT 256
31#define LSILOGICSCSI_REPLY_QUEUE_DEPTH_DEFAULT 256
32
33#define LSILOGICSCSI_MAXIMUM_CHAIN_DEPTH 3
34
35#define LSILOGIC_NR_OF_ALLOWED_BIGGER_LISTS 100
36
37/** Equal for all devices */
38#define LSILOGICSCSI_PCI_VENDOR_ID (0x1000)
39
40/** SPI SCSI controller (LSI53C1030) */
41#define LSILOGICSCSI_PCI_SPI_CTRLNAME "LSI53C1030"
42#define LSILOGICSCSI_PCI_SPI_DEVICE_ID (0x0030)
43#define LSILOGICSCSI_PCI_SPI_REVISION_ID (0x00)
44#define LSILOGICSCSI_PCI_SPI_CLASS_CODE (0x01)
45#define LSILOGICSCSI_PCI_SPI_SUBSYSTEM_VENDOR_ID (0x1000)
46#define LSILOGICSCSI_PCI_SPI_SUBSYSTEM_ID (0x8000)
47#define LSILOGICSCSI_PCI_SPI_PORTS_MAX 1
48#define LSILOGICSCSI_PCI_SPI_BUSES_MAX 1
49#define LSILOGICSCSI_PCI_SPI_DEVICES_PER_BUS_MAX 16
50#define LSILOGICSCSI_PCI_SPI_DEVICES_MAX (LSILOGICSCSI_PCI_SPI_BUSES_MAX*LSILOGICSCSI_PCI_SPI_DEVICES_PER_BUS_MAX)
51
52/** SAS SCSI controller (SAS1068 PCI-X Fusion-MPT SAS) */
53#define LSILOGICSCSI_PCI_SAS_CTRLNAME "SAS1068"
54#define LSILOGICSCSI_PCI_SAS_DEVICE_ID (0x0054)
55#define LSILOGICSCSI_PCI_SAS_REVISION_ID (0x00)
56#define LSILOGICSCSI_PCI_SAS_CLASS_CODE (0x00)
57#define LSILOGICSCSI_PCI_SAS_SUBSYSTEM_VENDOR_ID (0x1000)
58#define LSILOGICSCSI_PCI_SAS_SUBSYSTEM_ID (0x8000)
59#define LSILOGICSCSI_PCI_SAS_PORTS_MAX 256
60#define LSILOGICSCSI_PCI_SAS_PORTS_DEFAULT 8
61#define LSILOGICSCSI_PCI_SAS_DEVICES_PER_PORT_MAX 1
62#define LSILOGICSCSI_PCI_SAS_DEVICES_MAX (LSILOGICSCSI_PCI_SAS_PORTS_MAX * LSILOGICSCSI_PCI_SAS_DEVICES_PER_PORT_MAX)
63
64/**
65 * A SAS address.
66 */
67#pragma pack(1)
68typedef union SASADDRESS
69{
70 /** 64bit view. */
71 uint64_t u64Address;
72 /** 32bit view. */
73 uint32_t u32Address[2];
74 /** 16bit view. */
75 uint16_t u16Address[4];
76 /** Byte view. */
77 uint8_t u8Address[8];
78} SASADDRESS, *PSASADDRESS;
79#pragma pack()
80AssertCompileSize(SASADDRESS, 8);
81
82/**
83 * Possible device types we support.
84 */
85typedef enum LSILOGICCTRLTYPE
86{
87 /** SPI SCSI controller (PCI dev id 0x0030) */
88 LSILOGICCTRLTYPE_SCSI_SPI = 0,
89 /** SAS SCSI controller (PCI dev id 0x0054) */
90 LSILOGICCTRLTYPE_SCSI_SAS = 1,
91 /** 32bit hack */
92 LSILOGICCTRLTYPE_32BIT_HACK = 0x7fffffff
93} LSILOGICCTRLTYPE, *PLSILOGICCTRLTYPE;
94
95/**
96 * A simple SG element for a 64bit address.
97 */
98#pragma pack(1)
99typedef struct MptSGEntrySimple64
100{
101 /** Length of the buffer this entry describes. */
102 unsigned u24Length: 24;
103 /** Flag whether this element is the end of the list. */
104 unsigned fEndOfList: 1;
105 /** Flag whether the address is 32bit or 64bits wide. */
106 unsigned f64BitAddress: 1;
107 /** Flag whether this buffer contains data to be transferred or is the destination. */
108 unsigned fBufferContainsData: 1;
109 /** Flag whether this is a local address or a system address. */
110 unsigned fLocalAddress: 1;
111 /** Element type. */
112 unsigned u2ElementType: 2;
113 /** Flag whether this is the last element of the buffer. */
114 unsigned fEndOfBuffer: 1;
115 /** Flag whether this is the last element of the current segment. */
116 unsigned fLastElement: 1;
117 /** Lower 32bits of the address of the data buffer. */
118 unsigned u32DataBufferAddressLow: 32;
119 /** Upper 32bits of the address of the data buffer. */
120 unsigned u32DataBufferAddressHigh: 32;
121} MptSGEntrySimple64, *PMptSGEntrySimple64;
122#pragma pack()
123AssertCompileSize(MptSGEntrySimple64, 12);
124
125/**
126 * A simple SG element for a 32bit address.
127 */
128#pragma pack(1)
129typedef struct MptSGEntrySimple32
130{
131 /** Length of the buffer this entry describes. */
132 unsigned u24Length: 24;
133 /** Flag whether this element is the end of the list. */
134 unsigned fEndOfList: 1;
135 /** Flag whether the address is 32bit or 64bits wide. */
136 unsigned f64BitAddress: 1;
137 /** Flag whether this buffer contains data to be transferred or is the destination. */
138 unsigned fBufferContainsData: 1;
139 /** Flag whether this is a local address or a system address. */
140 unsigned fLocalAddress: 1;
141 /** Element type. */
142 unsigned u2ElementType: 2;
143 /** Flag whether this is the last element of the buffer. */
144 unsigned fEndOfBuffer: 1;
145 /** Flag whether this is the last element of the current segment. */
146 unsigned fLastElement: 1;
147 /** Lower 32bits of the address of the data buffer. */
148 unsigned u32DataBufferAddressLow: 32;
149} MptSGEntrySimple32, *PMptSGEntrySimple32;
150#pragma pack()
151AssertCompileSize(MptSGEntrySimple32, 8);
152
153/**
154 * A chain SG element.
155 */
156#pragma pack(1)
157typedef struct MptSGEntryChain
158{
159 /** Size of the segment. */
160 unsigned u16Length: 16;
161 /** Offset in 32bit words of the next chain element in the segment
162 * identified by this element. */
163 unsigned u8NextChainOffset: 8;
164 /** Reserved. */
165 unsigned fReserved0: 1;
166 /** Flag whether the address is 32bit or 64bits wide. */
167 unsigned f64BitAddress: 1;
168 /** Reserved. */
169 unsigned fReserved1: 1;
170 /** Flag whether this is a local address or a system address. */
171 unsigned fLocalAddress: 1;
172 /** Element type. */
173 unsigned u2ElementType: 2;
174 /** Flag whether this is the last element of the buffer. */
175 unsigned u2Reserved2: 2;
176 /** Lower 32bits of the address of the data buffer. */
177 unsigned u32SegmentAddressLow: 32;
178 /** Upper 32bits of the address of the data buffer. */
179 unsigned u32SegmentAddressHigh: 32;
180} MptSGEntryChain, *PMptSGEntryChain;
181#pragma pack()
182AssertCompileSize(MptSGEntryChain, 12);
183
184typedef union MptSGEntryUnion
185{
186 MptSGEntrySimple64 Simple64;
187 MptSGEntrySimple32 Simple32;
188 MptSGEntryChain Chain;
189} MptSGEntryUnion, *PMptSGEntryUnion;
190
191/**
192 * MPT Fusion message header - Common for all message frames.
193 * This is filled in by the guest.
194 */
195#pragma pack(1)
196typedef struct MptMessageHdr
197{
198 /** Function dependent data. */
199 uint16_t u16FunctionDependent;
200 /** Chain offset. */
201 uint8_t u8ChainOffset;
202 /** The function code. */
203 uint8_t u8Function;
204 /** Function dependent data. */
205 uint8_t au8FunctionDependent[3];
206 /** Message flags. */
207 uint8_t u8MessageFlags;
208 /** Message context - Unique ID from the guest unmodified by the device. */
209 uint32_t u32MessageContext;
210} MptMessageHdr, *PMptMessageHdr;
211#pragma pack()
212AssertCompileSize(MptMessageHdr, 12);
213
214/** Defined function codes found in the message header. */
215#define MPT_MESSAGE_HDR_FUNCTION_SCSI_IO_REQUEST (0x00)
216#define MPT_MESSAGE_HDR_FUNCTION_SCSI_TASK_MGMT (0x01)
217#define MPT_MESSAGE_HDR_FUNCTION_IOC_INIT (0x02)
218#define MPT_MESSAGE_HDR_FUNCTION_IOC_FACTS (0x03)
219#define MPT_MESSAGE_HDR_FUNCTION_CONFIG (0x04)
220#define MPT_MESSAGE_HDR_FUNCTION_PORT_FACTS (0x05)
221#define MPT_MESSAGE_HDR_FUNCTION_PORT_ENABLE (0x06)
222#define MPT_MESSAGE_HDR_FUNCTION_EVENT_NOTIFICATION (0x07)
223#define MPT_MESSAGE_HDR_FUNCTION_EVENT_ACK (0x08)
224#define MPT_MESSAGE_HDR_FUNCTION_FW_DOWNLOAD (0x09)
225#define MPT_MESSAGE_HDR_FUNCTION_TARGET_CMD_BUFFER_POST (0x0A)
226#define MPT_MESSAGE_HDR_FUNCTION_TARGET_ASSIST (0x0B)
227#define MPT_MESSAGE_HDR_FUNCTION_TARGET_STATUS_SEND (0x0C)
228#define MPT_MESSAGE_HDR_FUNCTION_TARGET_MODE_ABORT (0x0D)
229#define MPT_MESSAGE_HDR_FUNCTION_FW_UPLOAD (0x12)
230
231#ifdef DEBUG
232/**
233 * Function names
234 */
235static const char * const g_apszMPTFunctionNames[] =
236{
237 "SCSI I/O Request",
238 "SCSI Task Management",
239 "IOC Init",
240 "IOC Facts",
241 "Config",
242 "Port Facts",
243 "Port Enable",
244 "Event Notification",
245 "Event Ack",
246 "Firmware Download"
247};
248#endif
249
250/**
251 * Default reply message.
252 * Send from the device to the guest upon completion of a request.
253 */
254 #pragma pack(1)
255typedef struct MptDefaultReplyMessage
256{
257 /** Function dependent data. */
258 uint16_t u16FunctionDependent;
259 /** Length of the message in 32bit DWords. */
260 uint8_t u8MessageLength;
261 /** Function which completed. */
262 uint8_t u8Function;
263 /** Function dependent. */
264 uint8_t au8FunctionDependent[3];
265 /** Message flags. */
266 uint8_t u8MessageFlags;
267 /** Message context given in the request. */
268 uint32_t u32MessageContext;
269 /** Function dependent status code. */
270 uint16_t u16FunctionDependentStatus;
271 /** Status of the IOC. */
272 uint16_t u16IOCStatus;
273 /** Additional log info. */
274 uint32_t u32IOCLogInfo;
275} MptDefaultReplyMessage, *PMptDefaultReplyMessage;
276#pragma pack()
277AssertCompileSize(MptDefaultReplyMessage, 20);
278
279/**
280 * IO controller init request.
281 */
282#pragma pack(1)
283typedef struct MptIOCInitRequest
284{
285 /** Which system send this init request. */
286 uint8_t u8WhoInit;
287 /** Reserved */
288 uint8_t u8Reserved;
289 /** Chain offset in the SG list. */
290 uint8_t u8ChainOffset;
291 /** Function to execute. */
292 uint8_t u8Function;
293 /** Flags */
294 uint8_t u8Flags;
295 /** Maximum number of devices the driver can handle. */
296 uint8_t u8MaxDevices;
297 /** Maximum number of buses the driver can handle. */
298 uint8_t u8MaxBuses;
299 /** Message flags. */
300 uint8_t u8MessageFlags;
301 /** Message context ID. */
302 uint32_t u32MessageContext;
303 /** Reply frame size. */
304 uint16_t u16ReplyFrameSize;
305 /** Reserved */
306 uint16_t u16Reserved;
307 /** Upper 32bit part of the 64bit address the message frames are in.
308 * That means all frames must be in the same 4GB segment. */
309 uint32_t u32HostMfaHighAddr;
310 /** Upper 32bit of the sense buffer. */
311 uint32_t u32SenseBufferHighAddr;
312} MptIOCInitRequest, *PMptIOCInitRequest;
313#pragma pack()
314AssertCompileSize(MptIOCInitRequest, 24);
315
316/**
317 * IO controller init reply.
318 */
319#pragma pack(1)
320typedef struct MptIOCInitReply
321{
322 /** Which subsystem send this init request. */
323 uint8_t u8WhoInit;
324 /** Reserved */
325 uint8_t u8Reserved;
326 /** Message length */
327 uint8_t u8MessageLength;
328 /** Function. */
329 uint8_t u8Function;
330 /** Flags */
331 uint8_t u8Flags;
332 /** Maximum number of devices the driver can handle. */
333 uint8_t u8MaxDevices;
334 /** Maximum number of busses the driver can handle. */
335 uint8_t u8MaxBuses;
336 /** Message flags. */
337 uint8_t u8MessageFlags;
338 /** Message context ID */
339 uint32_t u32MessageContext;
340 /** Reserved */
341 uint16_t u16Reserved;
342 /** IO controller status. */
343 uint16_t u16IOCStatus;
344 /** IO controller log information. */
345 uint32_t u32IOCLogInfo;
346} MptIOCInitReply, *PMptIOCInitReply;
347#pragma pack()
348AssertCompileSize(MptIOCInitReply, 20);
349
350/**
351 * IO controller facts request.
352 */
353#pragma pack(1)
354typedef struct MptIOCFactsRequest
355{
356 /** Reserved. */
357 uint16_t u16Reserved;
358 /** Chain offset in SG list. */
359 uint8_t u8ChainOffset;
360 /** Function number. */
361 uint8_t u8Function;
362 /** Reserved */
363 uint8_t u8Reserved[3];
364 /** Message flags. */
365 uint8_t u8MessageFlags;
366 /** Message context ID. */
367 uint32_t u32MessageContext;
368} MptIOCFactsRequest, *PMptIOCFactsRequest;
369#pragma pack()
370AssertCompileSize(MptIOCFactsRequest, 12);
371
372/**
373 * IO controller facts reply.
374 */
375#pragma pack(1)
376typedef struct MptIOCFactsReply
377{
378 /** Message version. */
379 uint16_t u16MessageVersion;
380 /** Message length. */
381 uint8_t u8MessageLength;
382 /** Function number. */
383 uint8_t u8Function;
384 /** Reserved */
385 uint16_t u16Reserved1;
386 /** IO controller number */
387 uint8_t u8IOCNumber;
388 /** Message flags. */
389 uint8_t u8MessageFlags;
390 /** Message context ID. */
391 uint32_t u32MessageContext;
392 /** IO controller exceptions */
393 uint16_t u16IOCExceptions;
394 /** IO controller status. */
395 uint16_t u16IOCStatus;
396 /** IO controller log information. */
397 uint32_t u32IOCLogInfo;
398 /** Maximum chain depth. */
399 uint8_t u8MaxChainDepth;
400 /** The current value of the WhoInit field. */
401 uint8_t u8WhoInit;
402 /** Block size. */
403 uint8_t u8BlockSize;
404 /** Flags. */
405 uint8_t u8Flags;
406 /** Depth of the reply queue. */
407 uint16_t u16ReplyQueueDepth;
408 /** Size of a request frame. */
409 uint16_t u16RequestFrameSize;
410 /** Reserved */
411 uint16_t u16Reserved2;
412 /** Product ID. */
413 uint16_t u16ProductID;
414 /** Current value of the high 32bit MFA address. */
415 uint32_t u32CurrentHostMFAHighAddr;
416 /** Global credits - Number of entries allocated to queues */
417 uint16_t u16GlobalCredits;
418 /** Number of ports on the IO controller */
419 uint8_t u8NumberOfPorts;
420 /** Event state. */
421 uint8_t u8EventState;
422 /** Current value of the high 32bit sense buffer address. */
423 uint32_t u32CurrentSenseBufferHighAddr;
424 /** Current reply frame size. */
425 uint16_t u16CurReplyFrameSize;
426 /** Maximum number of devices. */
427 uint8_t u8MaxDevices;
428 /** Maximum number of buses. */
429 uint8_t u8MaxBuses;
430 /** Size of the firmware image. */
431 uint32_t u32FwImageSize;
432 /** Reserved. */
433 uint32_t u32Reserved;
434 /** Firmware version */
435 uint32_t u32FWVersion;
436} MptIOCFactsReply, *PMptIOCFactsReply;
437#pragma pack()
438AssertCompileSize(MptIOCFactsReply, 60);
439
440/**
441 * Port facts request
442 */
443#pragma pack(1)
444typedef struct MptPortFactsRequest
445{
446 /** Reserved */
447 uint16_t u16Reserved1;
448 /** Message length. */
449 uint8_t u8MessageLength;
450 /** Function number. */
451 uint8_t u8Function;
452 /** Reserved */
453 uint16_t u16Reserved2;
454 /** Port number to get facts for. */
455 uint8_t u8PortNumber;
456 /** Message flags. */
457 uint8_t u8MessageFlags;
458 /** Message context ID. */
459 uint32_t u32MessageContext;
460} MptPortFactsRequest, *PMptPortFactsRequest;
461#pragma pack()
462AssertCompileSize(MptPortFactsRequest, 12);
463
464/**
465 * Port facts reply.
466 */
467#pragma pack(1)
468typedef struct MptPortFactsReply
469{
470 /** Reserved. */
471 uint16_t u16Reserved1;
472 /** Message length. */
473 uint8_t u8MessageLength;
474 /** Function number. */
475 uint8_t u8Function;
476 /** Reserved */
477 uint16_t u16Reserved2;
478 /** Port number the facts are for. */
479 uint8_t u8PortNumber;
480 /** Message flags. */
481 uint8_t u8MessageFlags;
482 /** Message context ID. */
483 uint32_t u32MessageContext;
484 /** Reserved. */
485 uint16_t u16Reserved3;
486 /** IO controller status. */
487 uint16_t u16IOCStatus;
488 /** IO controller log information. */
489 uint32_t u32IOCLogInfo;
490 /** Reserved */
491 uint8_t u8Reserved;
492 /** Port type */
493 uint8_t u8PortType;
494 /** Maximum number of devices on this port. */
495 uint16_t u16MaxDevices;
496 /** SCSI ID of this port on the attached bus. */
497 uint16_t u16PortSCSIID;
498 /** Protocol flags. */
499 uint16_t u16ProtocolFlags;
500 /** Maximum number of target command buffers which can be posted to this port at a time. */
501 uint16_t u16MaxPostedCmdBuffers;
502 /** Maximum number of target IDs that remain persistent between power/reset cycles. */
503 uint16_t u16MaxPersistentIDs;
504 /** Maximum number of LAN buckets. */
505 uint16_t u16MaxLANBuckets;
506 /** Reserved. */
507 uint16_t u16Reserved4;
508 /** Reserved. */
509 uint32_t u32Reserved;
510} MptPortFactsReply, *PMptPortFactsReply;
511#pragma pack()
512AssertCompileSize(MptPortFactsReply, 40);
513
514/**
515 * Port Enable request.
516 */
517#pragma pack(1)
518typedef struct MptPortEnableRequest
519{
520 /** Reserved. */
521 uint16_t u16Reserved1;
522 /** Message length. */
523 uint8_t u8MessageLength;
524 /** Function number. */
525 uint8_t u8Function;
526 /** Reserved. */
527 uint16_t u16Reserved2;
528 /** Port number to enable. */
529 uint8_t u8PortNumber;
530 /** Message flags. */
531 uint8_t u8MessageFlags;
532 /** Message context ID. */
533 uint32_t u32MessageContext;
534} MptPortEnableRequest, *PMptPortEnableRequest;
535#pragma pack()
536AssertCompileSize(MptPortEnableRequest, 12);
537
538/**
539 * Port enable reply.
540 */
541#pragma pack(1)
542typedef struct MptPortEnableReply
543{
544 /** Reserved. */
545 uint16_t u16Reserved1;
546 /** Message length. */
547 uint8_t u8MessageLength;
548 /** Function number. */
549 uint8_t u8Function;
550 /** Reserved */
551 uint16_t u16Reserved2;
552 /** Port number which was enabled. */
553 uint8_t u8PortNumber;
554 /** Message flags. */
555 uint8_t u8MessageFlags;
556 /** Message context ID. */
557 uint32_t u32MessageContext;
558 /** Reserved. */
559 uint16_t u16Reserved3;
560 /** IO controller status */
561 uint16_t u16IOCStatus;
562 /** IO controller log information. */
563 uint32_t u32IOCLogInfo;
564} MptPortEnableReply, *PMptPortEnableReply;
565#pragma pack()
566AssertCompileSize(MptPortEnableReply, 20);
567
568/**
569 * Event notification request.
570 */
571#pragma pack(1)
572typedef struct MptEventNotificationRequest
573{
574 /** Switch - Turns event notification on and off. */
575 uint8_t u8Switch;
576 /** Reserved. */
577 uint8_t u8Reserved1;
578 /** Chain offset. */
579 uint8_t u8ChainOffset;
580 /** Function number. */
581 uint8_t u8Function;
582 /** Reserved. */
583 uint8_t u8reserved2[3];
584 /** Message flags. */
585 uint8_t u8MessageFlags;
586 /** Message context ID. */
587 uint32_t u32MessageContext;
588} MptEventNotificationRequest, *PMptEventNotificationRequest;
589#pragma pack()
590AssertCompileSize(MptEventNotificationRequest, 12);
591
592/**
593 * Event notification reply.
594 */
595#pragma pack(1)
596typedef struct MptEventNotificationReply
597{
598 /** Event data length. */
599 uint16_t u16EventDataLength;
600 /** Message length. */
601 uint8_t u8MessageLength;
602 /** Function number. */
603 uint8_t u8Function;
604 /** Reserved. */
605 uint16_t u16Reserved1;
606 /** Ack required. */
607 uint8_t u8AckRequired;
608 /** Message flags. */
609 uint8_t u8MessageFlags;
610 /** Message context ID. */
611 uint32_t u32MessageContext;
612 /** Reserved. */
613 uint16_t u16Reserved2;
614 /** IO controller status. */
615 uint16_t u16IOCStatus;
616 /** IO controller log information. */
617 uint32_t u32IOCLogInfo;
618 /** Notification event. */
619 uint32_t u32Event;
620 /** Event context. */
621 uint32_t u32EventContext;
622 /** Event data. */
623 uint32_t u32EventData;
624} MptEventNotificationReply, *PMptEventNotificationReply;
625#pragma pack()
626AssertCompileSize(MptEventNotificationReply, 32);
627
628#define MPT_EVENT_EVENT_CHANGE (0x0000000a)
629
630/**
631 * FW download request.
632 */
633#pragma pack(1)
634typedef struct MptFWDownloadRequest
635{
636 /** Switch - Turns event notification on and off. */
637 uint8_t u8ImageType;
638 /** Reserved. */
639 uint8_t u8Reserved1;
640 /** Chain offset. */
641 uint8_t u8ChainOffset;
642 /** Function number. */
643 uint8_t u8Function;
644 /** Reserved. */
645 uint8_t u8Reserved2[3];
646 /** Message flags. */
647 uint8_t u8MessageFlags;
648 /** Message context ID. */
649 uint32_t u32MessageContext;
650} MptFWDownloadRequest, *PMptFWDownloadRequest;
651#pragma pack()
652AssertCompileSize(MptFWDownloadRequest, 12);
653
654#define MPT_FW_DOWNLOAD_REQUEST_IMAGE_TYPE_RESERVED 0
655#define MPT_FW_DOWNLOAD_REQUEST_IMAGE_TYPE_FIRMWARE 1
656#define MPT_FW_DOWNLOAD_REQUEST_IMAGE_TYPE_MPI_BIOS 2
657#define MPT_FW_DOWNLOAD_REQUEST_IMAGE_TYPE_NVDATA 3
658
659/**
660 * FW download reply.
661 */
662#pragma pack(1)
663typedef struct MptFWDownloadReply
664{
665 /** Reserved. */
666 uint16_t u16Reserved1;
667 /** Message length. */
668 uint8_t u8MessageLength;
669 /** Function number. */
670 uint8_t u8Function;
671 /** Reserved. */
672 uint8_t u8Reserved2[3];
673 /** Message flags. */
674 uint8_t u8MessageFlags;
675 /** Message context ID. */
676 uint32_t u32MessageContext;
677 /** Reserved. */
678 uint16_t u16Reserved2;
679 /** IO controller status. */
680 uint16_t u16IOCStatus;
681 /** IO controller log information. */
682 uint32_t u32IOCLogInfo;
683} MptFWDownloadReply, *PMptFWDownloadReply;
684#pragma pack()
685AssertCompileSize(MptFWDownloadReply, 20);
686
687/**
688 * FW upload request.
689 */
690#pragma pack(1)
691typedef struct MptFWUploadRequest
692{
693 /** Requested image type. */
694 uint8_t u8ImageType;
695 /** Reserved. */
696 uint8_t u8Reserved1;
697 /** Chain offset. */
698 uint8_t u8ChainOffset;
699 /** Function number. */
700 uint8_t u8Function;
701 /** Reserved. */
702 uint8_t u8Reserved2[3];
703 /** Message flags. */
704 uint8_t u8MessageFlags;
705 /** Message context ID. */
706 uint32_t u32MessageContext;
707} MptFWUploadRequest, *PMptFWUploadRequest;
708#pragma pack()
709AssertCompileSize(MptFWUploadRequest, 12);
710
711/**
712 * FW upload reply.
713 */
714#pragma pack(1)
715typedef struct MptFWUploadReply
716{
717 /** Image type. */
718 uint8_t u8ImageType;
719 /** Reserved. */
720 uint8_t u8Reserved1;
721 /** Message length. */
722 uint8_t u8MessageLength;
723 /** Function number. */
724 uint8_t u8Function;
725 /** Reserved. */
726 uint8_t u8Reserved2[3];
727 /** Message flags. */
728 uint8_t u8MessageFlags;
729 /** Message context ID. */
730 uint32_t u32MessageContext;
731 /** Reserved. */
732 uint16_t u16Reserved2;
733 /** IO controller status. */
734 uint16_t u16IOCStatus;
735 /** IO controller log information. */
736 uint32_t u32IOCLogInfo;
737 /** Uploaded image size. */
738 uint32_t u32ActualImageSize;
739} MptFWUploadReply, *PMptFWUploadReply;
740#pragma pack()
741AssertCompileSize(MptFWUploadReply, 24);
742
743/**
744 * SCSI IO Request
745 */
746#pragma pack(1)
747typedef struct MptSCSIIORequest
748{
749 /** Target ID */
750 uint8_t u8TargetID;
751 /** Bus number */
752 uint8_t u8Bus;
753 /** Chain offset */
754 uint8_t u8ChainOffset;
755 /** Function number. */
756 uint8_t u8Function;
757 /** CDB length. */
758 uint8_t u8CDBLength;
759 /** Sense buffer length. */
760 uint8_t u8SenseBufferLength;
761 /** Reserved */
762 uint8_t u8Reserved;
763 /** Message flags. */
764 uint8_t u8MessageFlags;
765 /** Message context ID. */
766 uint32_t u32MessageContext;
767 /** LUN */
768 uint8_t au8LUN[8];
769 /** Control values. */
770 uint32_t u32Control;
771 /** The CDB. */
772 uint8_t au8CDB[16];
773 /** Data length. */
774 uint32_t u32DataLength;
775 /** Sense buffer low 32bit address. */
776 uint32_t u32SenseBufferLowAddress;
777} MptSCSIIORequest, *PMptSCSIIORequest;
778#pragma pack()
779AssertCompileSize(MptSCSIIORequest, 48);
780
781#define MPT_SCSIIO_REQUEST_CONTROL_TXDIR_GET(x) (((x) & 0x3000000) >> 24)
782#define MPT_SCSIIO_REQUEST_CONTROL_TXDIR_NONE (0x0)
783#define MPT_SCSIIO_REQUEST_CONTROL_TXDIR_WRITE (0x1)
784#define MPT_SCSIIO_REQUEST_CONTROL_TXDIR_READ (0x2)
785
786/**
787 * SCSI IO error reply.
788 */
789#pragma pack(1)
790typedef struct MptSCSIIOErrorReply
791{
792 /** Target ID */
793 uint8_t u8TargetID;
794 /** Bus number */
795 uint8_t u8Bus;
796 /** Message length. */
797 uint8_t u8MessageLength;
798 /** Function number. */
799 uint8_t u8Function;
800 /** CDB length */
801 uint8_t u8CDBLength;
802 /** Sense buffer length */
803 uint8_t u8SenseBufferLength;
804 /** Reserved */
805 uint8_t u8Reserved;
806 /** Message flags */
807 uint8_t u8MessageFlags;
808 /** Message context ID */
809 uint32_t u32MessageContext;
810 /** SCSI status. */
811 uint8_t u8SCSIStatus;
812 /** SCSI state */
813 uint8_t u8SCSIState;
814 /** IO controller status */
815 uint16_t u16IOCStatus;
816 /** IO controller log information */
817 uint32_t u32IOCLogInfo;
818 /** Transfer count */
819 uint32_t u32TransferCount;
820 /** Sense count */
821 uint32_t u32SenseCount;
822 /** Response information */
823 uint32_t u32ResponseInfo;
824} MptSCSIIOErrorReply, *PMptSCSIIOErrorReply;
825#pragma pack()
826AssertCompileSize(MptSCSIIOErrorReply, 32);
827
828#define MPT_SCSI_IO_ERROR_SCSI_STATE_AUTOSENSE_VALID (0x01)
829#define MPT_SCSI_IO_ERROR_SCSI_STATE_TERMINATED (0x08)
830
831/**
832 * IOC status codes specific to the SCSI I/O error reply.
833 */
834#define MPT_SCSI_IO_ERROR_IOCSTATUS_INVALID_BUS (0x0041)
835#define MPT_SCSI_IO_ERROR_IOCSTATUS_INVALID_TARGETID (0x0042)
836#define MPT_SCSI_IO_ERROR_IOCSTATUS_DEVICE_NOT_THERE (0x0043)
837
838/**
839 * SCSI task management request.
840 */
841#pragma pack(1)
842typedef struct MptSCSITaskManagementRequest
843{
844 /** Target ID */
845 uint8_t u8TargetID;
846 /** Bus number */
847 uint8_t u8Bus;
848 /** Chain offset */
849 uint8_t u8ChainOffset;
850 /** Function number */
851 uint8_t u8Function;
852 /** Reserved */
853 uint8_t u8Reserved1;
854 /** Task type */
855 uint8_t u8TaskType;
856 /** Reserved */
857 uint8_t u8Reserved2;
858 /** Message flags */
859 uint8_t u8MessageFlags;
860 /** Message context ID */
861 uint32_t u32MessageContext;
862 /** LUN */
863 uint8_t au8LUN[8];
864 /** Reserved */
865 uint8_t auReserved[28];
866 /** Task message context ID. */
867 uint32_t u32TaskMessageContext;
868} MptSCSITaskManagementRequest, *PMptSCSITaskManagementRequest;
869#pragma pack()
870AssertCompileSize(MptSCSITaskManagementRequest, 52);
871
872/**
873 * SCSI task management reply.
874 */
875#pragma pack(1)
876typedef struct MptSCSITaskManagementReply
877{
878 /** Target ID */
879 uint8_t u8TargetID;
880 /** Bus number */
881 uint8_t u8Bus;
882 /** Message length */
883 uint8_t u8MessageLength;
884 /** Function number */
885 uint8_t u8Function;
886 /** Reserved */
887 uint8_t u8Reserved1;
888 /** Task type */
889 uint8_t u8TaskType;
890 /** Reserved */
891 uint8_t u8Reserved2;
892 /** Message flags */
893 uint8_t u8MessageFlags;
894 /** Message context ID */
895 uint32_t u32MessageContext;
896 /** Reserved */
897 uint16_t u16Reserved;
898 /** IO controller status */
899 uint16_t u16IOCStatus;
900 /** IO controller log information */
901 uint32_t u32IOCLogInfo;
902 /** Termination count */
903 uint32_t u32TerminationCount;
904} MptSCSITaskManagementReply, *PMptSCSITaskManagementReply;
905#pragma pack()
906AssertCompileSize(MptSCSITaskManagementReply, 24);
907
908/**
909 * Page address for SAS expander page types.
910 */
911#pragma pack(1)
912typedef union MptConfigurationPageAddressSASExpander
913{
914 struct
915 {
916 uint16_t u16Handle;
917 uint16_t u16Reserved;
918 } Form0And2;
919 struct
920 {
921 uint16_t u16Handle;
922 uint8_t u8PhyNum;
923 uint8_t u8Reserved;
924 } Form1;
925} MptConfigurationPageAddressSASExpander, *PMptConfigurationPageAddressSASExpander;
926#pragma pack()
927
928/**
929 * Page address for SAS device page types.
930 */
931#pragma pack(1)
932typedef union MptConfigurationPageAddressSASDevice
933{
934 struct
935 {
936 uint16_t u16Handle;
937 uint16_t u16Reserved;
938 } Form0And2;
939 struct
940 {
941 uint8_t u8TargetID;
942 uint8_t u8Bus;
943 uint8_t u8Reserved;
944 } Form1;
945} MptConfigurationPageAddressSASDevice, *PMptConfigurationPageAddressSASDevice;
946#pragma pack()
947
948/**
949 * Page address for SAS PHY page types.
950 */
951#pragma pack(1)
952typedef union MptConfigurationPageAddressSASPHY
953{
954 struct
955 {
956 uint8_t u8PhyNumber;
957 uint8_t u8Reserved[3];
958 } Form0;
959 struct
960 {
961 uint16_t u16Index;
962 uint16_t u16Reserved;
963 } Form1;
964} MptConfigurationPageAddressSASPHY, *PMptConfigurationPageAddressSASPHY;
965#pragma pack()
966
967/**
968 * Page address for SAS Enclosure page types.
969 */
970#pragma pack(1)
971typedef struct MptConfigurationPageAddressSASEnclosure
972{
973 uint16_t u16Handle;
974 uint16_t u16Reserved;
975} MptConfigurationPageAddressSASEnclosure, *PMptConfigurationPageAddressSASEnclosure;
976#pragma pack()
977
978/**
979 * Union of all possible address types.
980 */
981#pragma pack(1)
982typedef union MptConfigurationPageAddress
983{
984 /** 32bit view. */
985 uint32_t u32PageAddress;
986 struct
987 {
988 /** Port number to get the configuration page for. */
989 uint8_t u8PortNumber;
990 /** Reserved. */
991 uint8_t u8Reserved[3];
992 } MPIPortNumber;
993 struct
994 {
995 /** Target ID to get the configuration page for. */
996 uint8_t u8TargetID;
997 /** Bus number to get the configuration page for. */
998 uint8_t u8Bus;
999 /** Reserved. */
1000 uint8_t u8Reserved[2];
1001 } BusAndTargetId;
1002 MptConfigurationPageAddressSASExpander SASExpander;
1003 MptConfigurationPageAddressSASDevice SASDevice;
1004 MptConfigurationPageAddressSASPHY SASPHY;
1005 MptConfigurationPageAddressSASEnclosure SASEnclosure;
1006} MptConfigurationPageAddress, *PMptConfigurationPageAddress;
1007#pragma pack()
1008AssertCompileSize(MptConfigurationPageAddress, 4);
1009
1010#define MPT_CONFIGURATION_PAGE_ADDRESS_GET_SAS_FORM(x) (((x).u32PageAddress >> 28) & 0x0f)
1011
1012/**
1013 * Configuration request
1014 */
1015#pragma pack(1)
1016typedef struct MptConfigurationRequest
1017{
1018 /** Action code. */
1019 uint8_t u8Action;
1020 /** Reserved. */
1021 uint8_t u8Reserved1;
1022 /** Chain offset. */
1023 uint8_t u8ChainOffset;
1024 /** Function number. */
1025 uint8_t u8Function;
1026 /** Extended page length. */
1027 uint16_t u16ExtPageLength;
1028 /** Extended page type */
1029 uint8_t u8ExtPageType;
1030 /** Message flags. */
1031 uint8_t u8MessageFlags;
1032 /** Message context ID. */
1033 uint32_t u32MessageContext;
1034 /** Reserved. */
1035 uint8_t u8Reserved2[8];
1036 /** Version number of the page. */
1037 uint8_t u8PageVersion;
1038 /** Length of the page in 32bit Dwords. */
1039 uint8_t u8PageLength;
1040 /** Page number to access. */
1041 uint8_t u8PageNumber;
1042 /** Type of the page being accessed. */
1043 uint8_t u8PageType;
1044 /** Page type dependent address. */
1045 MptConfigurationPageAddress PageAddress;
1046 /** Simple SG element describing the buffer. */
1047 MptSGEntrySimple64 SimpleSGElement;
1048} MptConfigurationRequest, *PMptConfigurationRequest;
1049#pragma pack()
1050AssertCompileSize(MptConfigurationRequest, 40);
1051
1052/** Possible action codes. */
1053#define MPT_CONFIGURATION_REQUEST_ACTION_HEADER (0x00)
1054#define MPT_CONFIGURATION_REQUEST_ACTION_READ_CURRENT (0x01)
1055#define MPT_CONFIGURATION_REQUEST_ACTION_WRITE_CURRENT (0x02)
1056#define MPT_CONFIGURATION_REQUEST_ACTION_DEFAULT (0x03)
1057#define MPT_CONFIGURATION_REQUEST_ACTION_WRITE_NVRAM (0x04)
1058#define MPT_CONFIGURATION_REQUEST_ACTION_READ_DEFAULT (0x05)
1059#define MPT_CONFIGURATION_REQUEST_ACTION_READ_NVRAM (0x06)
1060
1061/** Page type codes. */
1062#define MPT_CONFIGURATION_REQUEST_PAGE_TYPE_IO_UNIT (0x00)
1063#define MPT_CONFIGURATION_REQUEST_PAGE_TYPE_IOC (0x01)
1064#define MPT_CONFIGURATION_REQUEST_PAGE_TYPE_BIOS (0x02)
1065#define MPT_CONFIGURATION_REQUEST_PAGE_TYPE_SCSI_PORT (0x03)
1066#define MPT_CONFIGURATION_REQUEST_PAGE_TYPE_EXTENDED (0x0F)
1067
1068/**
1069 * Configuration reply.
1070 */
1071#pragma pack(1)
1072typedef struct MptConfigurationReply
1073{
1074 /** Action code. */
1075 uint8_t u8Action;
1076 /** Reserved. */
1077 uint8_t u8Reserved;
1078 /** Message length. */
1079 uint8_t u8MessageLength;
1080 /** Function number. */
1081 uint8_t u8Function;
1082 /** Extended page length. */
1083 uint16_t u16ExtPageLength;
1084 /** Extended page type */
1085 uint8_t u8ExtPageType;
1086 /** Message flags. */
1087 uint8_t u8MessageFlags;
1088 /** Message context ID. */
1089 uint32_t u32MessageContext;
1090 /** Reserved. */
1091 uint16_t u16Reserved;
1092 /** I/O controller status. */
1093 uint16_t u16IOCStatus;
1094 /** I/O controller log information. */
1095 uint32_t u32IOCLogInfo;
1096 /** Version number of the page. */
1097 uint8_t u8PageVersion;
1098 /** Length of the page in 32bit Dwords. */
1099 uint8_t u8PageLength;
1100 /** Page number to access. */
1101 uint8_t u8PageNumber;
1102 /** Type of the page being accessed. */
1103 uint8_t u8PageType;
1104} MptConfigurationReply, *PMptConfigurationReply;
1105#pragma pack()
1106AssertCompileSize(MptConfigurationReply, 24);
1107
1108/** Additional I/O controller status codes for the configuration reply. */
1109#define MPT_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
1110#define MPT_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
1111#define MPT_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
1112#define MPT_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
1113#define MPT_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
1114#define MPT_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
1115
1116/**
1117 * Union of all possible request messages.
1118 */
1119typedef union MptRequestUnion
1120{
1121 MptMessageHdr Header;
1122 MptIOCInitRequest IOCInit;
1123 MptIOCFactsRequest IOCFacts;
1124 MptPortFactsRequest PortFacts;
1125 MptPortEnableRequest PortEnable;
1126 MptEventNotificationRequest EventNotification;
1127 MptSCSIIORequest SCSIIO;
1128 MptSCSITaskManagementRequest SCSITaskManagement;
1129 MptConfigurationRequest Configuration;
1130 MptFWDownloadRequest FWDownload;
1131 MptFWUploadRequest FWUpload;
1132} MptRequestUnion, *PMptRequestUnion;
1133
1134/**
1135 * Union of all possible reply messages.
1136 */
1137typedef union MptReplyUnion
1138{
1139 /** 16bit view. */
1140 uint16_t au16Reply[30];
1141 MptDefaultReplyMessage Header;
1142 MptIOCInitReply IOCInit;
1143 MptIOCFactsReply IOCFacts;
1144 MptPortFactsReply PortFacts;
1145 MptPortEnableReply PortEnable;
1146 MptEventNotificationReply EventNotification;
1147 MptSCSIIOErrorReply SCSIIOError;
1148 MptSCSITaskManagementReply SCSITaskManagement;
1149 MptConfigurationReply Configuration;
1150 MptFWDownloadReply FWDownload;
1151 MptFWUploadReply FWUpload;
1152} MptReplyUnion, *PMptReplyUnion;
1153AssertCompileSize(MptReplyUnion, 60);
1154
1155/**
1156 * Firmware image header.
1157 */
1158#pragma pack(1)
1159typedef struct FwImageHdr
1160{
1161 /** ARM branch instruction. */
1162 uint32_t u32ArmBrInsn;
1163 /** Signature part 1. */
1164 uint32_t u32Signature1;
1165 /** Signature part 2. */
1166 uint32_t u32Signature2;
1167 /** Signature part 3. */
1168 uint32_t u32Signature3;
1169 /** Another ARM branch instruction. */
1170 uint32_t u32ArmBrInsn2;
1171 /** Yet another ARM branch instruction. */
1172 uint32_t u32ArmBrInsn3;
1173 /** Reserved. */
1174 uint32_t u32Reserved;
1175 /** Checksum of the image. */
1176 uint32_t u32Checksum;
1177 /** Vendor ID. */
1178 uint16_t u16VendorId;
1179 /** Product ID. */
1180 uint16_t u16ProductId;
1181 /** Firmware version. */
1182 uint32_t u32FwVersion;
1183 /** Firmware sequencer Code version. */
1184 uint32_t u32SeqCodeVersion;
1185 /** Image size in bytes including the header. */
1186 uint32_t u32ImageSize;
1187 /** Offset of the first extended image header. */
1188 uint32_t u32NextImageHeaderOffset;
1189 /** Start address of the image in IOC memory. */
1190 uint32_t u32LoadStartAddress;
1191 /** Absolute start address of the Iop ARM. */
1192 uint32_t u32IopResetVectorValue;
1193 /** Address of the IopResetVector register. */
1194 uint32_t u32IopResetVectorRegAddr;
1195 /** Marker value for what utility. */
1196 uint32_t u32VersionNameWhat;
1197 /** ASCII string of version. */
1198 uint8_t aszVersionName[256];
1199 /** Marker value for what utility. */
1200 uint32_t u32VendorNameWhat;
1201 /** ASCII string of vendor name. */
1202 uint8_t aszVendorName[256];
1203} FwImageHdr, *PFwImageHdr;
1204#pragma pack()
1205AssertCompileSize(FwImageHdr, 584);
1206
1207/** First part of the signature. */
1208#define LSILOGIC_FWIMGHDR_SIGNATURE1 UINT32_C(0x5aeaa55a)
1209/** Second part of the signature. */
1210#define LSILOGIC_FWIMGHDR_SIGNATURE2 UINT32_C(0xa55aeaa5)
1211/** Third part of the signature. */
1212#define LSILOGIC_FWIMGHDR_SIGNATURE3 UINT32_C(0x5aa55aea)
1213/** Load address of the firmware image to watch for,
1214 * seen used by Solaris 9. When this value is written to the
1215 * diagnostic address register we know a firmware image is downloaded.
1216 */
1217#define LSILOGIC_FWIMGHDR_LOAD_ADDRESS UINT32_C(0x21ff5e00)
1218
1219/**
1220 * Configuration Page attributes.
1221 */
1222#define MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY (0x00)
1223#define MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE (0x10)
1224#define MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT (0x20)
1225#define MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY (0x30)
1226
1227#define MPT_CONFIGURATION_PAGE_ATTRIBUTE_GET(u8PageType) ((u8PageType) & 0xf0)
1228
1229/**
1230 * Configuration Page types.
1231 */
1232#define MPT_CONFIGURATION_PAGE_TYPE_IO_UNIT (0x00)
1233#define MPT_CONFIGURATION_PAGE_TYPE_IOC (0x01)
1234#define MPT_CONFIGURATION_PAGE_TYPE_BIOS (0x02)
1235#define MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_PORT (0x03)
1236#define MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE (0x04)
1237#define MPT_CONFIGURATION_PAGE_TYPE_MANUFACTURING (0x09)
1238#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED (0x0F)
1239
1240#define MPT_CONFIGURATION_PAGE_TYPE_GET(u8PageType) ((u8PageType) & 0x0f)
1241
1242/**
1243 * Extented page types.
1244 */
1245#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT (0x10)
1246#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASEXPANDER (0x11)
1247#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASDEVICE (0x12)
1248#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASPHYS (0x13)
1249#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_LOG (0x14)
1250#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_ENCLOSURE (0x15)
1251
1252/**
1253 * Configuration Page header - Common to all pages.
1254 */
1255#pragma pack(1)
1256typedef struct MptConfigurationPageHeader
1257{
1258 /** Version of the page. */
1259 uint8_t u8PageVersion;
1260 /** The length of the page in 32bit D-Words. */
1261 uint8_t u8PageLength;
1262 /** Number of the page. */
1263 uint8_t u8PageNumber;
1264 /** Type of the page. */
1265 uint8_t u8PageType;
1266} MptConfigurationPageHeader, *PMptConfigurationPageHeader;
1267#pragma pack()
1268AssertCompileSize(MptConfigurationPageHeader, 4);
1269
1270/**
1271 * Extended configuration page header - Common to all extended pages.
1272 */
1273#pragma pack(1)
1274typedef struct MptExtendedConfigurationPageHeader
1275{
1276 /** Version of the page. */
1277 uint8_t u8PageVersion;
1278 /** Reserved. */
1279 uint8_t u8Reserved1;
1280 /** Number of the page. */
1281 uint8_t u8PageNumber;
1282 /** Type of the page. */
1283 uint8_t u8PageType;
1284 /** Extended page length. */
1285 uint16_t u16ExtPageLength;
1286 /** Extended page type. */
1287 uint8_t u8ExtPageType;
1288 /** Reserved */
1289 uint8_t u8Reserved2;
1290} MptExtendedConfigurationPageHeader, *PMptExtendedConfigurationPageHeader;
1291#pragma pack()
1292AssertCompileSize(MptExtendedConfigurationPageHeader, 8);
1293
1294/**
1295 * Manufacturing page 0. - Readonly.
1296 */
1297#pragma pack(1)
1298typedef struct MptConfigurationPageManufacturing0
1299{
1300 /** Union. */
1301 union
1302 {
1303 /** Byte view. */
1304 uint8_t abPageData[76];
1305 /** Field view. */
1306 struct
1307 {
1308 /** The omnipresent header. */
1309 MptConfigurationPageHeader Header;
1310 /** Name of the chip. */
1311 uint8_t abChipName[16];
1312 /** Chip revision. */
1313 uint8_t abChipRevision[8];
1314 /** Board name. */
1315 uint8_t abBoardName[16];
1316 /** Board assembly. */
1317 uint8_t abBoardAssembly[16];
1318 /** Board tracer number. */
1319 uint8_t abBoardTracerNumber[16];
1320 } fields;
1321 } u;
1322} MptConfigurationPageManufacturing0, *PMptConfigurationPageManufacturing0;
1323#pragma pack()
1324AssertCompileSize(MptConfigurationPageManufacturing0, 76);
1325
1326/**
1327 * Manufacturing page 1. - Readonly Persistent.
1328 */
1329#pragma pack(1)
1330typedef struct MptConfigurationPageManufacturing1
1331{
1332 /** Union */
1333 union
1334 {
1335 /** Byte view */
1336 uint8_t abPageData[260];
1337 /** Field view */
1338 struct
1339 {
1340 /** The omnipresent header. */
1341 MptConfigurationPageHeader Header;
1342 /** VPD info - don't know what belongs here so all zero. */
1343 uint8_t abVPDInfo[256];
1344 } fields;
1345 } u;
1346} MptConfigurationPageManufacturing1, *PMptConfigurationPageManufacturing1;
1347#pragma pack()
1348AssertCompileSize(MptConfigurationPageManufacturing1, 260);
1349
1350/**
1351 * Manufacturing page 2. - Readonly.
1352 */
1353#pragma pack(1)
1354typedef struct MptConfigurationPageManufacturing2
1355{
1356 /** Union. */
1357 union
1358 {
1359 /** Byte view. */
1360 uint8_t abPageData[8];
1361 /** Field view. */
1362 struct
1363 {
1364 /** The omnipresent header. */
1365 MptConfigurationPageHeader Header;
1366 /** PCI Device ID. */
1367 uint16_t u16PCIDeviceID;
1368 /** PCI Revision ID. */
1369 uint8_t u8PCIRevisionID;
1370 /** Reserved. */
1371 uint8_t u8Reserved;
1372 /** Hardware specific settings... */
1373 } fields;
1374 } u;
1375} MptConfigurationPageManufacturing2, *PMptConfigurationPageManufacturing2;
1376#pragma pack()
1377AssertCompileSize(MptConfigurationPageManufacturing2, 8);
1378
1379/**
1380 * Manufacturing page 3. - Readonly.
1381 */
1382#pragma pack(1)
1383typedef struct MptConfigurationPageManufacturing3
1384{
1385 /** Union. */
1386 union
1387 {
1388 /** Byte view. */
1389 uint8_t abPageData[8];
1390 /** Field view. */
1391 struct
1392 {
1393 /** The omnipresent header. */
1394 MptConfigurationPageHeader Header;
1395 /** PCI Device ID. */
1396 uint16_t u16PCIDeviceID;
1397 /** PCI Revision ID. */
1398 uint8_t u8PCIRevisionID;
1399 /** Reserved. */
1400 uint8_t u8Reserved;
1401 /** Chip specific settings... */
1402 } fields;
1403 } u;
1404} MptConfigurationPageManufacturing3, *PMptConfigurationPageManufacturing3;
1405#pragma pack()
1406AssertCompileSize(MptConfigurationPageManufacturing3, 8);
1407
1408/**
1409 * Manufacturing page 4. - Readonly.
1410 */
1411#pragma pack(1)
1412typedef struct MptConfigurationPageManufacturing4
1413{
1414 /** Union. */
1415 union
1416 {
1417 /** Byte view. */
1418 uint8_t abPageData[84];
1419 /** Field view. */
1420 struct
1421 {
1422 /** The omnipresent header. */
1423 MptConfigurationPageHeader Header;
1424 /** Reserved. */
1425 uint32_t u32Reserved;
1426 /** InfoOffset0. */
1427 uint8_t u8InfoOffset0;
1428 /** Info size. */
1429 uint8_t u8InfoSize0;
1430 /** InfoOffset1. */
1431 uint8_t u8InfoOffset1;
1432 /** Info size. */
1433 uint8_t u8InfoSize1;
1434 /** Size of the inquiry data. */
1435 uint8_t u8InquirySize;
1436 /** Reserved. */
1437 uint8_t abReserved[3];
1438 /** Inquiry data. */
1439 uint8_t abInquiryData[56];
1440 /** IS volume settings. */
1441 uint32_t u32ISVolumeSettings;
1442 /** IME volume settings. */
1443 uint32_t u32IMEVolumeSettings;
1444 /** IM volume settings. */
1445 uint32_t u32IMVolumeSettings;
1446 } fields;
1447 } u;
1448} MptConfigurationPageManufacturing4, *PMptConfigurationPageManufacturing4;
1449#pragma pack()
1450AssertCompileSize(MptConfigurationPageManufacturing4, 84);
1451
1452/**
1453 * Manufacturing page 5 - Readonly.
1454 */
1455#pragma pack(1)
1456typedef struct MptConfigurationPageManufacturing5
1457{
1458 /** Union. */
1459 union
1460 {
1461 /** Byte view. */
1462 uint8_t abPageData[88];
1463 /** Field view. */
1464 struct
1465 {
1466 /** The omnipresent header. */
1467 MptConfigurationPageHeader Header;
1468 /** Base WWID. */
1469 uint64_t u64BaseWWID;
1470 /** Flags */
1471 uint8_t u8Flags;
1472 /** Number of ForceWWID fields in this page. */
1473 uint8_t u8NumForceWWID;
1474 /** Reserved */
1475 uint16_t u16Reserved;
1476 /** Reserved */
1477 uint32_t au32Reserved[2];
1478 /** ForceWWID entries Maximum of 8 because the SAS controller doesn't has more */
1479 uint64_t au64ForceWWID[8];
1480 } fields;
1481 } u;
1482} MptConfigurationPageManufacturing5, *PMptConfigurationPageManufacturing5;
1483#pragma pack()
1484AssertCompileSize(MptConfigurationPageManufacturing5, 24+64);
1485
1486/**
1487 * Manufacturing page 6 - Readonly.
1488 */
1489#pragma pack(1)
1490typedef struct MptConfigurationPageManufacturing6
1491{
1492 /** Union. */
1493 union
1494 {
1495 /** Byte view. */
1496 uint8_t abPageData[4];
1497 /** Field view. */
1498 struct
1499 {
1500 /** The omnipresent header. */
1501 MptConfigurationPageHeader Header;
1502 /** Product specific data - 0 for now */
1503 } fields;
1504 } u;
1505} MptConfigurationPageManufacturing6, *PMptConfigurationPageManufacturing6;
1506#pragma pack()
1507AssertCompileSize(MptConfigurationPageManufacturing6, 4);
1508
1509/**
1510 * Manufacutring page 7 - PHY element.
1511 */
1512#pragma pack(1)
1513typedef struct MptConfigurationPageManufacturing7PHY
1514{
1515 /** Pinout */
1516 uint32_t u32Pinout;
1517 /** Connector name */
1518 uint8_t szConnector[16];
1519 /** Location */
1520 uint8_t u8Location;
1521 /** reserved */
1522 uint8_t u8Reserved;
1523 /** Slot */
1524 uint16_t u16Slot;
1525} MptConfigurationPageManufacturing7PHY, *PMptConfigurationPageManufacturing7PHY;
1526#pragma pack()
1527AssertCompileSize(MptConfigurationPageManufacturing7PHY, 24);
1528
1529/**
1530 * Manufacturing page 7 - Readonly.
1531 */
1532#pragma pack(1)
1533typedef struct MptConfigurationPageManufacturing7
1534{
1535 /** Union. */
1536 union
1537 {
1538 /** Byte view. */
1539 uint8_t abPageData[1];
1540 /** Field view. */
1541 struct
1542 {
1543 /** The omnipresent header. */
1544 MptConfigurationPageHeader Header;
1545 /** Reserved */
1546 uint32_t au32Reserved[2];
1547 /** Flags */
1548 uint32_t u32Flags;
1549 /** Enclosure name */
1550 uint8_t szEnclosureName[16];
1551 /** Number of PHYs */
1552 uint8_t u8NumPhys;
1553 /** Reserved */
1554 uint8_t au8Reserved[3];
1555 /** PHY list for the SAS controller - variable depending on the number of ports */
1556 MptConfigurationPageManufacturing7PHY aPHY[1];
1557 } fields;
1558 } u;
1559} MptConfigurationPageManufacturing7, *PMptConfigurationPageManufacturing7;
1560#pragma pack()
1561AssertCompileSize(MptConfigurationPageManufacturing7, 36+sizeof(MptConfigurationPageManufacturing7PHY));
1562
1563#define LSILOGICSCSI_MANUFACTURING7_GET_SIZE(ports) (sizeof(MptConfigurationPageManufacturing7) + ((ports) - 1) * sizeof(MptConfigurationPageManufacturing7PHY))
1564
1565/** Flags for the flags field */
1566#define LSILOGICSCSI_MANUFACTURING7_FLAGS_USE_PROVIDED_INFORMATION RT_BIT(0)
1567
1568/** Flags for the pinout field */
1569#define LSILOGICSCSI_MANUFACTURING7_PINOUT_UNKNOWN RT_BIT(0)
1570#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8482 RT_BIT(1)
1571#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8470_LANE1 RT_BIT(8)
1572#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8470_LANE2 RT_BIT(9)
1573#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8470_LANE3 RT_BIT(10)
1574#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8470_LANE4 RT_BIT(11)
1575#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8484_LANE1 RT_BIT(16)
1576#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8484_LANE2 RT_BIT(17)
1577#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8484_LANE3 RT_BIT(18)
1578#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8484_LANE4 RT_BIT(19)
1579
1580/** Flags for the location field */
1581#define LSILOGICSCSI_MANUFACTURING7_LOCATION_UNKNOWN 0x01
1582#define LSILOGICSCSI_MANUFACTURING7_LOCATION_INTERNAL 0x02
1583#define LSILOGICSCSI_MANUFACTURING7_LOCATION_EXTERNAL 0x04
1584#define LSILOGICSCSI_MANUFACTURING7_LOCATION_SWITCHABLE 0x08
1585#define LSILOGICSCSI_MANUFACTURING7_LOCATION_AUTO 0x10
1586#define LSILOGICSCSI_MANUFACTURING7_LOCATION_NOT_PRESENT 0x20
1587#define LSILOGICSCSI_MANUFACTURING7_LOCATION_NOT_CONNECTED 0x80
1588
1589/**
1590 * Manufacturing page 8 - Readonly.
1591 */
1592#pragma pack(1)
1593typedef struct MptConfigurationPageManufacturing8
1594{
1595 /** Union. */
1596 union
1597 {
1598 /** Byte view. */
1599 uint8_t abPageData[4];
1600 /** Field view. */
1601 struct
1602 {
1603 /** The omnipresent header. */
1604 MptConfigurationPageHeader Header;
1605 /** Product specific information */
1606 } fields;
1607 } u;
1608} MptConfigurationPageManufacturing8, *PMptConfigurationPageManufacturing8;
1609#pragma pack()
1610AssertCompileSize(MptConfigurationPageManufacturing8, 4);
1611
1612/**
1613 * Manufacturing page 9 - Readonly.
1614 */
1615#pragma pack(1)
1616typedef struct MptConfigurationPageManufacturing9
1617{
1618 /** Union. */
1619 union
1620 {
1621 /** Byte view. */
1622 uint8_t abPageData[4];
1623 /** Field view. */
1624 struct
1625 {
1626 /** The omnipresent header. */
1627 MptConfigurationPageHeader Header;
1628 /** Product specific information */
1629 } fields;
1630 } u;
1631} MptConfigurationPageManufacturing9, *PMptConfigurationPageManufacturing9;
1632#pragma pack()
1633AssertCompileSize(MptConfigurationPageManufacturing9, 4);
1634
1635/**
1636 * Manufacturing page 10 - Readonly.
1637 */
1638#pragma pack(1)
1639typedef struct MptConfigurationPageManufacturing10
1640{
1641 /** Union. */
1642 union
1643 {
1644 /** Byte view. */
1645 uint8_t abPageData[4];
1646 /** Field view. */
1647 struct
1648 {
1649 /** The omnipresent header. */
1650 MptConfigurationPageHeader Header;
1651 /** Product specific information */
1652 } fields;
1653 } u;
1654} MptConfigurationPageManufacturing10, *PMptConfigurationPageManufacturing10;
1655#pragma pack()
1656AssertCompileSize(MptConfigurationPageManufacturing10, 4);
1657
1658/**
1659 * IO Unit page 0. - Readonly.
1660 */
1661#pragma pack(1)
1662typedef struct MptConfigurationPageIOUnit0
1663{
1664 /** Union. */
1665 union
1666 {
1667 /** Byte view. */
1668 uint8_t abPageData[12];
1669 /** Field view. */
1670 struct
1671 {
1672 /** The omnipresent header. */
1673 MptConfigurationPageHeader Header;
1674 /** A unique identifier. */
1675 uint64_t u64UniqueIdentifier;
1676 } fields;
1677 } u;
1678} MptConfigurationPageIOUnit0, *PMptConfigurationPageIOUnit0;
1679#pragma pack()
1680AssertCompileSize(MptConfigurationPageIOUnit0, 12);
1681
1682/**
1683 * IO Unit page 1. - Read/Write.
1684 */
1685#pragma pack(1)
1686typedef struct MptConfigurationPageIOUnit1
1687{
1688 /** Union. */
1689 union
1690 {
1691 /** Byte view. */
1692 uint8_t abPageData[8];
1693 /** Field view. */
1694 struct
1695 {
1696 /** The omnipresent header. */
1697 MptConfigurationPageHeader Header;
1698 /** Flag whether this is a single function PCI device. */
1699 unsigned fSingleFunction: 1;
1700 /** Flag whether all possible paths to a device are mapped. */
1701 unsigned fAllPathsMapped: 1;
1702 /** Reserved. */
1703 unsigned u4Reserved: 4;
1704 /** Flag whether all RAID functionality is disabled. */
1705 unsigned fIntegratedRAIDDisabled: 1;
1706 /** Flag whether 32bit PCI accesses are forced. */
1707 unsigned f32BitAccessForced: 1;
1708 /** Reserved. */
1709 unsigned abReserved: 24;
1710 } fields;
1711 } u;
1712} MptConfigurationPageIOUnit1, *PMptConfigurationPageIOUnit1;
1713#pragma pack()
1714AssertCompileSize(MptConfigurationPageIOUnit1, 8);
1715
1716/**
1717 * Adapter Ordering.
1718 */
1719#pragma pack(1)
1720typedef struct MptConfigurationPageIOUnit2AdapterOrdering
1721{
1722 /** PCI bus number. */
1723 unsigned u8PCIBusNumber: 8;
1724 /** PCI device and function number. */
1725 unsigned u8PCIDevFn: 8;
1726 /** Flag whether the adapter is embedded. */
1727 unsigned fAdapterEmbedded: 1;
1728 /** Flag whether the adapter is enabled. */
1729 unsigned fAdapterEnabled: 1;
1730 /** Reserved. */
1731 unsigned u6Reserved: 6;
1732 /** Reserved. */
1733 unsigned u8Reserved: 8;
1734} MptConfigurationPageIOUnit2AdapterOrdering, *PMptConfigurationPageIOUnit2AdapterOrdering;
1735#pragma pack()
1736AssertCompileSize(MptConfigurationPageIOUnit2AdapterOrdering, 4);
1737
1738/**
1739 * IO Unit page 2. - Read/Write.
1740 */
1741#pragma pack(1)
1742typedef struct MptConfigurationPageIOUnit2
1743{
1744 /** Union. */
1745 union
1746 {
1747 /** Byte view. */
1748 uint8_t abPageData[28];
1749 /** Field view. */
1750 struct
1751 {
1752 /** The omnipresent header. */
1753 MptConfigurationPageHeader Header;
1754 /** Reserved. */
1755 unsigned fReserved: 1;
1756 /** Flag whether Pause on error is enabled. */
1757 unsigned fPauseOnError: 1;
1758 /** Flag whether verbose mode is enabled. */
1759 unsigned fVerboseModeEnabled: 1;
1760 /** Set to disable color video. */
1761 unsigned fDisableColorVideo: 1;
1762 /** Flag whether int 40h is hooked. */
1763 unsigned fNotHookInt40h: 1;
1764 /** Reserved. */
1765 unsigned u3Reserved: 3;
1766 /** Reserved. */
1767 unsigned abReserved: 24;
1768 /** BIOS version. */
1769 uint32_t u32BIOSVersion;
1770 /** Adapter ordering. */
1771 MptConfigurationPageIOUnit2AdapterOrdering aAdapterOrder[4];
1772 } fields;
1773 } u;
1774} MptConfigurationPageIOUnit2, *PMptConfigurationPageIOUnit2;
1775#pragma pack()
1776AssertCompileSize(MptConfigurationPageIOUnit2, 28);
1777
1778/*
1779 * IO Unit page 3. - Read/Write.
1780 */
1781#pragma pack(1)
1782typedef struct MptConfigurationPageIOUnit3
1783{
1784 /** Union. */
1785 union
1786 {
1787 /** Byte view. */
1788 uint8_t abPageData[8];
1789 /** Field view. */
1790 struct
1791 {
1792 /** The omnipresent header. */
1793 MptConfigurationPageHeader Header;
1794 /** Number of GPIO values. */
1795 uint8_t u8GPIOCount;
1796 /** Reserved. */
1797 uint8_t abReserved[3];
1798 } fields;
1799 } u;
1800} MptConfigurationPageIOUnit3, *PMptConfigurationPageIOUnit3;
1801#pragma pack()
1802AssertCompileSize(MptConfigurationPageIOUnit3, 8);
1803
1804/*
1805 * IO Unit page 4. - Readonly for everyone except the BIOS.
1806 */
1807#pragma pack(1)
1808typedef struct MptConfigurationPageIOUnit4
1809{
1810 /** Union. */
1811 union
1812 {
1813 /** Byte view. */
1814 uint8_t abPageData[20];
1815 /** Field view. */
1816 struct
1817 {
1818 /** The omnipresent header. */
1819 MptConfigurationPageHeader Header;
1820 /** Reserved */
1821 uint32_t u32Reserved;
1822 /** SG entry describing the Firmware location. */
1823 MptSGEntrySimple64 FWImageSGE;
1824 } fields;
1825 } u;
1826} MptConfigurationPageIOUnit4, *PMptConfigurationPageIOUnit4;
1827#pragma pack()
1828AssertCompileSize(MptConfigurationPageIOUnit4, 20);
1829
1830/**
1831 * IOC page 0. - Readonly
1832 */
1833#pragma pack(1)
1834typedef struct MptConfigurationPageIOC0
1835{
1836 /** Union. */
1837 union
1838 {
1839 /** Byte view. */
1840 uint8_t abPageData[28];
1841 /** Field view. */
1842 struct
1843 {
1844 /** The omnipresent header. */
1845 MptConfigurationPageHeader Header;
1846 /** Total amount of NV memory in bytes. */
1847 uint32_t u32TotalNVStore;
1848 /** Number of free bytes in the NV store. */
1849 uint32_t u32FreeNVStore;
1850 /** PCI vendor ID. */
1851 uint16_t u16VendorId;
1852 /** PCI device ID. */
1853 uint16_t u16DeviceId;
1854 /** PCI revision ID. */
1855 uint8_t u8RevisionId;
1856 /** Reserved. */
1857 uint8_t abReserved[3];
1858 /** PCI class code. */
1859 uint32_t u32ClassCode;
1860 /** Subsystem vendor Id. */
1861 uint16_t u16SubsystemVendorId;
1862 /** Subsystem Id. */
1863 uint16_t u16SubsystemId;
1864 } fields;
1865 } u;
1866} MptConfigurationPageIOC0, *PMptConfigurationPageIOC0;
1867#pragma pack()
1868AssertCompileSize(MptConfigurationPageIOC0, 28);
1869
1870/**
1871 * IOC page 1. - Read/Write
1872 */
1873#pragma pack(1)
1874typedef struct MptConfigurationPageIOC1
1875{
1876 /** Union. */
1877 union
1878 {
1879 /** Byte view. */
1880 uint8_t abPageData[16];
1881 /** Field view. */
1882 struct
1883 {
1884 /** The omnipresent header. */
1885 MptConfigurationPageHeader Header;
1886 /** Flag whether reply coalescing is enabled. */
1887 unsigned fReplyCoalescingEnabled: 1;
1888 /** Reserved. */
1889 unsigned u31Reserved: 31;
1890 /** Coalescing Timeout in microseconds. */
1891 unsigned u32CoalescingTimeout: 32;
1892 /** Coalescing depth. */
1893 unsigned u8CoalescingDepth: 8;
1894 /** Reserved. */
1895 unsigned u8Reserved0: 8;
1896 unsigned u8Reserved1: 8;
1897 unsigned u8Reserved2: 8;
1898 } fields;
1899 } u;
1900} MptConfigurationPageIOC1, *PMptConfigurationPageIOC1;
1901#pragma pack()
1902AssertCompileSize(MptConfigurationPageIOC1, 16);
1903
1904/**
1905 * IOC page 2. - Readonly
1906 */
1907#pragma pack(1)
1908typedef struct MptConfigurationPageIOC2
1909{
1910 /** Union. */
1911 union
1912 {
1913 /** Byte view. */
1914 uint8_t abPageData[12];
1915 /** Field view. */
1916 struct
1917 {
1918 /** The omnipresent header. */
1919 MptConfigurationPageHeader Header;
1920 /** Flag whether striping is supported. */
1921 unsigned fStripingSupported: 1;
1922 /** Flag whether enhanced mirroring is supported. */
1923 unsigned fEnhancedMirroringSupported: 1;
1924 /** Flag whether mirroring is supported. */
1925 unsigned fMirroringSupported: 1;
1926 /** Reserved. */
1927 unsigned u26Reserved: 26;
1928 /** Flag whether SES is supported. */
1929 unsigned fSESSupported: 1;
1930 /** Flag whether SAF-TE is supported. */
1931 unsigned fSAFTESupported: 1;
1932 /** Flag whether cross channel volumes are supported. */
1933 unsigned fCrossChannelVolumesSupported: 1;
1934 /** Number of active integrated RAID volumes. */
1935 unsigned u8NumActiveVolumes: 8;
1936 /** Maximum number of integrated RAID volumes supported. */
1937 unsigned u8MaxVolumes: 8;
1938 /** Number of active integrated RAID physical disks. */
1939 unsigned u8NumActivePhysDisks: 8;
1940 /** Maximum number of integrated RAID physical disks supported. */
1941 unsigned u8MaxPhysDisks: 8;
1942 /** RAID volumes... - not supported. */
1943 } fields;
1944 } u;
1945} MptConfigurationPageIOC2, *PMptConfigurationPageIOC2;
1946#pragma pack()
1947AssertCompileSize(MptConfigurationPageIOC2, 12);
1948
1949/**
1950 * IOC page 3. - Readonly
1951 */
1952#pragma pack(1)
1953typedef struct MptConfigurationPageIOC3
1954{
1955 /** Union. */
1956 union
1957 {
1958 /** Byte view. */
1959 uint8_t abPageData[8];
1960 /** Field view. */
1961 struct
1962 {
1963 /** The omnipresent header. */
1964 MptConfigurationPageHeader Header;
1965 /** Number of active integrated RAID physical disks. */
1966 uint8_t u8NumPhysDisks;
1967 /** Reserved. */
1968 uint8_t abReserved[3];
1969 } fields;
1970 } u;
1971} MptConfigurationPageIOC3, *PMptConfigurationPageIOC3;
1972#pragma pack()
1973AssertCompileSize(MptConfigurationPageIOC3, 8);
1974
1975/**
1976 * IOC page 4. - Read/Write
1977 */
1978#pragma pack(1)
1979typedef struct MptConfigurationPageIOC4
1980{
1981 /** Union. */
1982 union
1983 {
1984 /** Byte view. */
1985 uint8_t abPageData[8];
1986 /** Field view. */
1987 struct
1988 {
1989 /** The omnipresent header. */
1990 MptConfigurationPageHeader Header;
1991 /** Number of SEP entries in this page. */
1992 uint8_t u8ActiveSEP;
1993 /** Maximum number of SEp entries supported. */
1994 uint8_t u8MaxSEP;
1995 /** Reserved. */
1996 uint16_t u16Reserved;
1997 /** SEP entries... - not supported. */
1998 } fields;
1999 } u;
2000} MptConfigurationPageIOC4, *PMptConfigurationPageIOC4;
2001#pragma pack()
2002AssertCompileSize(MptConfigurationPageIOC4, 8);
2003
2004/**
2005 * IOC page 6. - Read/Write
2006 */
2007#pragma pack(1)
2008typedef struct MptConfigurationPageIOC6
2009{
2010 /** Union. */
2011 union
2012 {
2013 /** Byte view. */
2014 uint8_t abPageData[60];
2015 /** Field view. */
2016 struct
2017 {
2018 /** The omnipresent header. */
2019 MptConfigurationPageHeader Header;
2020 uint32_t u32CapabilitiesFlags;
2021 uint8_t u8MaxDrivesIS;
2022 uint8_t u8MaxDrivesIM;
2023 uint8_t u8MaxDrivesIME;
2024 uint8_t u8Reserved1;
2025 uint8_t u8MinDrivesIS;
2026 uint8_t u8MinDrivesIM;
2027 uint8_t u8MinDrivesIME;
2028 uint8_t u8Reserved2;
2029 uint8_t u8MaxGlobalHotSpares;
2030 uint8_t u8Reserved3;
2031 uint16_t u16Reserved4;
2032 uint32_t u32Reserved5;
2033 uint32_t u32SupportedStripeSizeMapIS;
2034 uint32_t u32SupportedStripeSizeMapIME;
2035 uint32_t u32Reserved6;
2036 uint8_t u8MetadataSize;
2037 uint8_t u8Reserved7;
2038 uint16_t u16Reserved8;
2039 uint16_t u16MaxBadBlockTableEntries;
2040 uint16_t u16Reserved9;
2041 uint16_t u16IRNvsramUsage;
2042 uint16_t u16Reserved10;
2043 uint32_t u32IRNvsramVersion;
2044 uint32_t u32Reserved11;
2045 } fields;
2046 } u;
2047} MptConfigurationPageIOC6, *PMptConfigurationPageIOC6;
2048#pragma pack()
2049AssertCompileSize(MptConfigurationPageIOC6, 60);
2050
2051/**
2052 * BIOS page 1 - Read/write.
2053 */
2054#pragma pack(1)
2055typedef struct MptConfigurationPageBIOS1
2056{
2057 /** Union. */
2058 union
2059 {
2060 /** Byte view. */
2061 uint8_t abPageData[48];
2062 /** Field view. */
2063 struct
2064 {
2065 /** The omnipresent header. */
2066 MptConfigurationPageHeader Header;
2067 /** BIOS options */
2068 uint32_t u32BiosOptions;
2069 /** IOC settings */
2070 uint32_t u32IOCSettings;
2071 /** Reserved */
2072 uint32_t u32Reserved;
2073 /** Device settings */
2074 uint32_t u32DeviceSettings;
2075 /** Number of devices */
2076 uint16_t u16NumberOfDevices;
2077 /** Expander spinup */
2078 uint8_t u8ExpanderSpinup;
2079 /** Reserved */
2080 uint8_t u8Reserved;
2081 /** I/O timeout of block devices without removable media */
2082 uint16_t u16IOTimeoutBlockDevicesNonRM;
2083 /** I/O timeout sequential */
2084 uint16_t u16IOTimeoutSequential;
2085 /** I/O timeout other */
2086 uint16_t u16IOTimeoutOther;
2087 /** I/O timeout of block devices with removable media */
2088 uint16_t u16IOTimeoutBlockDevicesRM;
2089 } fields;
2090 } u;
2091} MptConfigurationPageBIOS1, *PMptConfigurationPageBIOS1;
2092#pragma pack()
2093AssertCompileSize(MptConfigurationPageBIOS1, 48);
2094
2095#define LSILOGICSCSI_BIOS1_BIOSOPTIONS_BIOS_DISABLE RT_BIT(0)
2096#define LSILOGICSCSI_BIOS1_BIOSOPTIONS_SCAN_FROM_HIGH_TO_LOW RT_BIT(1)
2097#define LSILOGICSCSI_BIOS1_BIOSOPTIONS_BIOS_EXTENDED_SAS_SUPPORT RT_BIT(8)
2098#define LSILOGICSCSI_BIOS1_BIOSOPTIONS_BIOS_EXTENDED_FC_SUPPORT RT_BIT(9)
2099#define LSILOGICSCSI_BIOS1_BIOSOPTIONS_BIOS_EXTENDED_SPI_SUPPORT RT_BIT(10)
2100
2101#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ALTERNATE_CHS RT_BIT(3)
2102
2103#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ADAPTER_SUPPORT_SET(x) ((x) << 4)
2104#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ADAPTER_SUPPORT_DISABLED 0x00
2105#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ADAPTER_SUPPORT_BIOS_ONLY 0x01
2106#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ADAPTER_SUPPORT_OS_ONLY 0x02
2107#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ADAPTER_SUPPORT_BOT 0x03
2108
2109#define LSILOGICSCSI_BIOS1_IOCSETTINGS_REMOVABLE_MEDIA_SET(x) ((x) << 6)
2110#define LSILOGICSCSI_BIOS1_IOCSETTINGS_REMOVABLE_MEDIA_NO_INT13H 0x00
2111#define LSILOGICSCSI_BIOS1_IOCSETTINGS_REMOVABLE_BOOT_MEDIA_INT13H 0x01
2112#define LSILOGICSCSI_BIOS1_IOCSETTINGS_REMOVABLE_MEDIA_INT13H 0x02
2113
2114#define LSILOGICSCSI_BIOS1_IOCSETTINGS_SPINUP_DELAY_SET(x) ((x & 0xF) << 8)
2115#define LSILOGICSCSI_BIOS1_IOCSETTINGS_SPINUP_DELAY_GET(x) ((x >> 8) & 0x0F)
2116#define LSILOGICSCSI_BIOS1_IOCSETTINGS_MAX_TARGET_SPINUP_SET(x) ((x & 0xF) << 12)
2117#define LSILOGICSCSI_BIOS1_IOCSETTINGS_MAX_TARGET_SPINUP_GET(x) ((x >> 12) & 0x0F)
2118
2119#define LSILOGICSCSI_BIOS1_IOCSETTINGS_BOOT_PREFERENCE_SET(x) (((x) & 0x3) << 16)
2120#define LSILOGICSCSI_BIOS1_IOCSETTINGS_BOOT_PREFERENCE_ENCLOSURE 0x0
2121#define LSILOGICSCSI_BIOS1_IOCSETTINGS_BOOT_PREFERENCE_SAS_ADDRESS 0x1
2122
2123#define LSILOGICSCSI_BIOS1_IOCSETTINGS_DIRECT_ATTACH_SPINUP_MODE_ALL RT_BIT(18)
2124#define LSILOGICSCSI_BIOS1_IOCSETTINGS_AUTO_PORT_ENABLE RT_BIT(19)
2125
2126#define LSILOGICSCSI_BIOS1_IOCSETTINGS_PORT_ENABLE_REPLY_DELAY_SET(x) (((x) & 0xF) << 20)
2127#define LSILOGICSCSI_BIOS1_IOCSETTINGS_PORT_ENABLE_REPLY_DELAY_GET(x) ((x >> 20) & 0x0F)
2128
2129#define LSILOGICSCSI_BIOS1_IOCSETTINGS_PORT_ENABLE_SPINUP_DELAY_SET(x) (((x) & 0xF) << 24)
2130#define LSILOGICSCSI_BIOS1_IOCSETTINGS_PORT_ENABLE_SPINUP_DELAY_GET(x) ((x >> 24) & 0x0F)
2131
2132#define LSILOGICSCSI_BIOS1_DEVICESETTINGS_DISABLE_LUN_SCANS RT_BIT(0)
2133#define LSILOGICSCSI_BIOS1_DEVICESETTINGS_DISABLE_LUN_SCANS_FOR_NON_REMOVABLE_DEVICES RT_BIT(1)
2134#define LSILOGICSCSI_BIOS1_DEVICESETTINGS_DISABLE_LUN_SCANS_FOR_REMOVABLE_DEVICES RT_BIT(2)
2135#define LSILOGICSCSI_BIOS1_DEVICESETTINGS_DISABLE_LUN_SCANS2 RT_BIT(3)
2136#define LSILOGICSCSI_BIOS1_DEVICESETTINGS_DISABLE_SMART_POLLING RT_BIT(4)
2137
2138#define LSILOGICSCSI_BIOS1_EXPANDERSPINUP_SPINUP_DELAY_SET(x) ((x) & 0x0F)
2139#define LSILOGICSCSI_BIOS1_EXPANDERSPINUP_SPINUP_DELAY_GET(x) ((x) & 0x0F)
2140#define LSILOGICSCSI_BIOS1_EXPANDERSPINUP_MAX_SPINUP_DELAY_SET(x) (((x) & 0x0F) << 4)
2141#define LSILOGICSCSI_BIOS1_EXPANDERSPINUP_MAX_SPINUP_DELAY_GET(x) ((x >> 4) & 0x0F)
2142
2143/**
2144 * BIOS page 2 - Read/write.
2145 */
2146#pragma pack(1)
2147typedef struct MptConfigurationPageBIOS2
2148{
2149 /** Union. */
2150 union
2151 {
2152 /** Byte view. */
2153 uint8_t abPageData[384];
2154 /** Field view. */
2155 struct
2156 {
2157 /** The omnipresent header. */
2158 MptConfigurationPageHeader Header;
2159 /** Reserved */
2160 uint32_t au32Reserved[6];
2161 /** Format of the boot device field. */
2162 uint8_t u8BootDeviceForm;
2163 /** Previous format of the boot device field. */
2164 uint8_t u8PrevBootDeviceForm;
2165 /** Reserved */
2166 uint16_t u16Reserved;
2167 /** Boot device fields - dependent on the format */
2168 union
2169 {
2170 /** Device for AdapterNumber:Bus:Target:LUN */
2171 struct
2172 {
2173 /** Target ID */
2174 uint8_t u8TargetID;
2175 /** Bus */
2176 uint8_t u8Bus;
2177 /** Adapter Number */
2178 uint8_t u8AdapterNumber;
2179 /** Reserved */
2180 uint8_t u8Reserved;
2181 /** Reserved */
2182 uint32_t au32Reserved[3];
2183 /** LUN */
2184 uint32_t aLUN[5];
2185 /** Reserved */
2186 uint32_t au32Reserved2[56];
2187 } AdapterNumberBusTargetLUN;
2188 /** Device for PCIAddress:Bus:Target:LUN */
2189 struct
2190 {
2191 /** Target ID */
2192 uint8_t u8TargetID;
2193 /** Bus */
2194 uint8_t u8Bus;
2195 /** Adapter Number */
2196 uint16_t u16PCIAddress;
2197 /** Reserved */
2198 uint32_t au32Reserved[3];
2199 /** LUN */
2200 uint32_t aLUN[5];
2201 /** Reserved */
2202 uint32_t au32Reserved2[56];
2203 } PCIAddressBusTargetLUN;
2204 /** Device for PCISlotNo:Bus:Target:LUN */
2205 struct
2206 {
2207 /** Target ID */
2208 uint8_t u8TargetID;
2209 /** Bus */
2210 uint8_t u8Bus;
2211 /** PCI Slot Number */
2212 uint8_t u16PCISlotNo;
2213 /** Reserved */
2214 uint32_t au32Reserved[3];
2215 /** LUN */
2216 uint32_t aLUN[5];
2217 /** Reserved */
2218 uint32_t au32Reserved2[56];
2219 } PCIAddressBusSlotLUN;
2220 /** Device for FC channel world wide name */
2221 struct
2222 {
2223 /** World wide port name low */
2224 uint32_t u32WorldWidePortNameLow;
2225 /** World wide port name high */
2226 uint32_t u32WorldWidePortNameHigh;
2227 /** Reserved */
2228 uint32_t au32Reserved[3];
2229 /** LUN */
2230 uint32_t aLUN[5];
2231 /** Reserved */
2232 uint32_t au32Reserved2[56];
2233 } FCWorldWideName;
2234 /** Device for FC channel world wide name */
2235 struct
2236 {
2237 /** SAS address */
2238 SASADDRESS SASAddress;
2239 /** Reserved */
2240 uint32_t au32Reserved[3];
2241 /** LUN */
2242 uint32_t aLUN[5];
2243 /** Reserved */
2244 uint32_t au32Reserved2[56];
2245 } SASWorldWideName;
2246 /** Device for Enclosure/Slot */
2247 struct
2248 {
2249 /** Enclosure logical ID */
2250 uint64_t u64EnclosureLogicalID;
2251 /** Reserved */
2252 uint32_t au32Reserved[3];
2253 /** LUN */
2254 uint32_t aLUN[5];
2255 /** Reserved */
2256 uint32_t au32Reserved2[56];
2257 } EnclosureSlot;
2258 } BootDevice;
2259 } fields;
2260 } u;
2261} MptConfigurationPageBIOS2, *PMptConfigurationPageBIOS2;
2262#pragma pack()
2263AssertCompileSize(MptConfigurationPageBIOS2, 384);
2264
2265#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_SET(x) ((x) & 0x0F)
2266#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_FIRST 0x0
2267#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_ADAPTER_BUS_TARGET_LUN 0x1
2268#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_PCIADDR_BUS_TARGET_LUN 0x2
2269#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_PCISLOT_BUS_TARGET_LUN 0x3
2270#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_FC_WWN 0x4
2271#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_SAS_WWN 0x5
2272#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_ENCLOSURE_SLOT 0x6
2273
2274/**
2275 * BIOS page 4 - Read/Write (Where is 3? - not defined in the spec)
2276 */
2277#pragma pack(1)
2278typedef struct MptConfigurationPageBIOS4
2279{
2280 /** Union. */
2281 union
2282 {
2283 /** Byte view. */
2284 uint8_t abPageData[12];
2285 /** Field view. */
2286 struct
2287 {
2288 /** The omnipresent header. */
2289 MptConfigurationPageHeader Header;
2290 /** Reassignment Base WWID */
2291 uint64_t u64ReassignmentBaseWWID;
2292 } fields;
2293 } u;
2294} MptConfigurationPageBIOS4, *PMptConfigurationPageBIOS4;
2295#pragma pack()
2296AssertCompileSize(MptConfigurationPageBIOS4, 12);
2297
2298/**
2299 * SCSI-SPI port page 0. - Readonly
2300 */
2301#pragma pack(1)
2302typedef struct MptConfigurationPageSCSISPIPort0
2303{
2304 /** Union. */
2305 union
2306 {
2307 /** Byte view. */
2308 uint8_t abPageData[12];
2309 /** Field view. */
2310 struct
2311 {
2312 /** The omnipresent header. */
2313 MptConfigurationPageHeader Header;
2314 /** Flag whether this port is information unit transfers capable. */
2315 unsigned fInformationUnitTransfersCapable: 1;
2316 /** Flag whether the port is DT (Dual Transfer) capable. */
2317 unsigned fDTCapable: 1;
2318 /** Flag whether the port is QAS (Quick Arbitrate and Select) capable. */
2319 unsigned fQASCapable: 1;
2320 /** Reserved. */
2321 unsigned u5Reserved1: 5;
2322 /** Minimum Synchronous transfer period. */
2323 unsigned u8MinimumSynchronousTransferPeriod: 8;
2324 /** Maximum synchronous offset. */
2325 unsigned u8MaximumSynchronousOffset: 8;
2326 /** Reserved. */
2327 unsigned u5Reserved2: 5;
2328 /** Flag whether indicating the width of the bus - 0 narrow and 1 for wide. */
2329 unsigned fWide: 1;
2330 /** Reserved */
2331 unsigned fReserved: 1;
2332 /** Flag whether the port is AIP (Asynchronous Information Protection) capable. */
2333 unsigned fAIPCapable: 1;
2334 /** Signaling Type. */
2335 unsigned u2SignalingType: 2;
2336 /** Reserved. */
2337 unsigned u30Reserved: 30;
2338 } fields;
2339 } u;
2340} MptConfigurationPageSCSISPIPort0, *PMptConfigurationPageSCSISPIPort0;
2341#pragma pack()
2342AssertCompileSize(MptConfigurationPageSCSISPIPort0, 12);
2343
2344/**
2345 * SCSI-SPI port page 1. - Read/Write
2346 */
2347#pragma pack(1)
2348typedef struct MptConfigurationPageSCSISPIPort1
2349{
2350 /** Union. */
2351 union
2352 {
2353 /** Byte view. */
2354 uint8_t abPageData[12];
2355 /** Field view. */
2356 struct
2357 {
2358 /** The omnipresent header. */
2359 MptConfigurationPageHeader Header;
2360 /** The SCSI ID of the port. */
2361 uint8_t u8SCSIID;
2362 /** Reserved. */
2363 uint8_t u8Reserved;
2364 /** Port response IDs Bit mask field. */
2365 uint16_t u16PortResponseIDsBitmask;
2366 /** Value for the on BUS timer. */
2367 uint32_t u32OnBusTimerValue;
2368 } fields;
2369 } u;
2370} MptConfigurationPageSCSISPIPort1, *PMptConfigurationPageSCSISPIPort1;
2371#pragma pack()
2372AssertCompileSize(MptConfigurationPageSCSISPIPort1, 12);
2373
2374/**
2375 * Device settings for one device.
2376 */
2377#pragma pack(1)
2378typedef struct MptDeviceSettings
2379{
2380 /** Timeout for I/O in seconds. */
2381 unsigned u8Timeout: 8;
2382 /** Minimum synchronous factor. */
2383 unsigned u8SyncFactor: 8;
2384 /** Flag whether disconnect is enabled. */
2385 unsigned fDisconnectEnable: 1;
2386 /** Flag whether Scan ID is enabled. */
2387 unsigned fScanIDEnable: 1;
2388 /** Flag whether Scan LUNs is enabled. */
2389 unsigned fScanLUNEnable: 1;
2390 /** Flag whether tagged queuing is enabled. */
2391 unsigned fTaggedQueuingEnabled: 1;
2392 /** Flag whether wide is enabled. */
2393 unsigned fWideDisable: 1;
2394 /** Flag whether this device is bootable. */
2395 unsigned fBootChoice: 1;
2396 /** Reserved. */
2397 unsigned u10Reserved: 10;
2398} MptDeviceSettings, *PMptDeviceSettings;
2399#pragma pack()
2400AssertCompileSize(MptDeviceSettings, 4);
2401
2402/**
2403 * SCSI-SPI port page 2. - Read/Write for the BIOS
2404 */
2405#pragma pack(1)
2406typedef struct MptConfigurationPageSCSISPIPort2
2407{
2408 /** Union. */
2409 union
2410 {
2411 /** Byte view. */
2412 uint8_t abPageData[76];
2413 /** Field view. */
2414 struct
2415 {
2416 /** The omnipresent header. */
2417 MptConfigurationPageHeader Header;
2418 /** Flag indicating the bus scan order. */
2419 unsigned fBusScanOrderHighToLow: 1;
2420 /** Reserved. */
2421 unsigned fReserved: 1;
2422 /** Flag whether SCSI Bus resets are avoided. */
2423 unsigned fAvoidSCSIBusResets: 1;
2424 /** Flag whether alternate CHS is used. */
2425 unsigned fAlternateCHS: 1;
2426 /** Flag whether termination is disabled. */
2427 unsigned fTerminationDisabled: 1;
2428 /** Reserved. */
2429 unsigned u27Reserved: 27;
2430 /** Host SCSI ID. */
2431 unsigned u4HostSCSIID: 4;
2432 /** Initialize HBA. */
2433 unsigned u2InitializeHBA: 2;
2434 /** Removeable media setting. */
2435 unsigned u2RemovableMediaSetting: 2;
2436 /** Spinup delay. */
2437 unsigned u4SpinupDelay: 4;
2438 /** Negotiating settings. */
2439 unsigned u2NegotitatingSettings: 2;
2440 /** Reserved. */
2441 unsigned u18Reserved: 18;
2442 /** Device Settings. */
2443 MptDeviceSettings aDeviceSettings[16];
2444 } fields;
2445 } u;
2446} MptConfigurationPageSCSISPIPort2, *PMptConfigurationPageSCSISPIPort2;
2447#pragma pack()
2448AssertCompileSize(MptConfigurationPageSCSISPIPort2, 76);
2449
2450/**
2451 * SCSI-SPI device page 0. - Readonly
2452 */
2453#pragma pack(1)
2454typedef struct MptConfigurationPageSCSISPIDevice0
2455{
2456 /** Union. */
2457 union
2458 {
2459 /** Byte view. */
2460 uint8_t abPageData[12];
2461 /** Field view. */
2462 struct
2463 {
2464 /** The omnipresent header. */
2465 MptConfigurationPageHeader Header;
2466 /** Negotiated Parameters. */
2467 /** Information Units enabled. */
2468 unsigned fInformationUnitsEnabled: 1;
2469 /** Dual Transfers Enabled. */
2470 unsigned fDTEnabled: 1;
2471 /** QAS enabled. */
2472 unsigned fQASEnabled: 1;
2473 /** Reserved. */
2474 unsigned u5Reserved1: 5;
2475 /** Synchronous Transfer period. */
2476 unsigned u8NegotiatedSynchronousTransferPeriod: 8;
2477 /** Synchronous offset. */
2478 unsigned u8NegotiatedSynchronousOffset: 8;
2479 /** Reserved. */
2480 unsigned u5Reserved2: 5;
2481 /** Width - 0 for narrow and 1 for wide. */
2482 unsigned fWide: 1;
2483 /** Reserved. */
2484 unsigned fReserved: 1;
2485 /** AIP enabled. */
2486 unsigned fAIPEnabled: 1;
2487 /** Flag whether negotiation occurred. */
2488 unsigned fNegotationOccured: 1;
2489 /** Flag whether a SDTR message was rejected. */
2490 unsigned fSDTRRejected: 1;
2491 /** Flag whether a WDTR message was rejected. */
2492 unsigned fWDTRRejected: 1;
2493 /** Flag whether a PPR message was rejected. */
2494 unsigned fPPRRejected: 1;
2495 /** Reserved. */
2496 unsigned u28Reserved: 28;
2497 } fields;
2498 } u;
2499} MptConfigurationPageSCSISPIDevice0, *PMptConfigurationPageSCSISPIDevice0;
2500#pragma pack()
2501AssertCompileSize(MptConfigurationPageSCSISPIDevice0, 12);
2502
2503/**
2504 * SCSI-SPI device page 1. - Read/Write
2505 */
2506#pragma pack(1)
2507typedef struct MptConfigurationPageSCSISPIDevice1
2508{
2509 /** Union. */
2510 union
2511 {
2512 /** Byte view. */
2513 uint8_t abPageData[16];
2514 /** Field view. */
2515 struct
2516 {
2517 /** The omnipresent header. */
2518 MptConfigurationPageHeader Header;
2519 /** Requested Parameters. */
2520 /** Information Units enable. */
2521 bool fInformationUnitsEnable: 1;
2522 /** Dual Transfers Enable. */
2523 bool fDTEnable: 1;
2524 /** QAS enable. */
2525 bool fQASEnable: 1;
2526 /** Reserved. */
2527 unsigned u5Reserved1: 5;
2528 /** Synchronous Transfer period. */
2529 unsigned u8NegotiatedSynchronousTransferPeriod: 8;
2530 /** Synchronous offset. */
2531 unsigned u8NegotiatedSynchronousOffset: 8;
2532 /** Reserved. */
2533 unsigned u5Reserved2: 5;
2534 /** Width - 0 for narrow and 1 for wide. */
2535 bool fWide: 1;
2536 /** Reserved. */
2537 bool fReserved1: 1;
2538 /** AIP enable. */
2539 bool fAIPEnable: 1;
2540 /** Reserved. */
2541 bool fReserved2: 1;
2542 /** WDTR disallowed. */
2543 bool fWDTRDisallowed: 1;
2544 /** SDTR disallowed. */
2545 bool fSDTRDisallowed: 1;
2546 /** Reserved. */
2547 unsigned u29Reserved: 29;
2548 } fields;
2549 } u;
2550} MptConfigurationPageSCSISPIDevice1, *PMptConfigurationPageSCSISPIDevice1;
2551#pragma pack()
2552AssertCompileSize(MptConfigurationPageSCSISPIDevice1, 16);
2553
2554/**
2555 * SCSI-SPI device page 2. - Read/Write
2556 */
2557#pragma pack(1)
2558typedef struct MptConfigurationPageSCSISPIDevice2
2559{
2560 /** Union. */
2561 union
2562 {
2563 /** Byte view. */
2564 uint8_t abPageData[16];
2565 /** Field view. */
2566 struct
2567 {
2568 /** The omnipresent header. */
2569 MptConfigurationPageHeader Header;
2570 /** Reserved. */
2571 unsigned u4Reserved: 4;
2572 /** ISI enable. */
2573 unsigned fISIEnable: 1;
2574 /** Secondary driver enable. */
2575 unsigned fSecondaryDriverEnable: 1;
2576 /** Reserved. */
2577 unsigned fReserved: 1;
2578 /** Slew create controller. */
2579 unsigned u3SlewRateControler: 3;
2580 /** Primary drive strength controller. */
2581 unsigned u3PrimaryDriveStrengthControl: 3;
2582 /** Secondary drive strength controller. */
2583 unsigned u3SecondaryDriveStrengthControl: 3;
2584 /** Reserved. */
2585 unsigned u12Reserved: 12;
2586 /** XCLKH_ST. */
2587 unsigned fXCLKH_ST: 1;
2588 /** XCLKS_ST. */
2589 unsigned fXCLKS_ST: 1;
2590 /** XCLKH_DT. */
2591 unsigned fXCLKH_DT: 1;
2592 /** XCLKS_DT. */
2593 unsigned fXCLKS_DT: 1;
2594 /** Parity pipe select. */
2595 unsigned u2ParityPipeSelect: 2;
2596 /** Reserved. */
2597 unsigned u30Reserved: 30;
2598 /** Data bit pipeline select. */
2599 unsigned u32DataPipelineSelect: 32;
2600 } fields;
2601 } u;
2602} MptConfigurationPageSCSISPIDevice2, *PMptConfigurationPageSCSISPIDevice2;
2603#pragma pack()
2604AssertCompileSize(MptConfigurationPageSCSISPIDevice2, 16);
2605
2606/**
2607 * SCSI-SPI device page 3 (Revision G). - Readonly
2608 */
2609#pragma pack(1)
2610typedef struct MptConfigurationPageSCSISPIDevice3
2611{
2612 /** Union. */
2613 union
2614 {
2615 /** Byte view. */
2616 uint8_t abPageData[1];
2617 /** Field view. */
2618 struct
2619 {
2620 /** The omnipresent header. */
2621 MptConfigurationPageHeader Header;
2622 /** Number of times the IOC rejected a message because it doesn't support the operation. */
2623 uint16_t u16MsgRejectCount;
2624 /** Number of times the SCSI bus entered an invalid operation state. */
2625 uint16_t u16PhaseErrorCount;
2626 /** Number of parity errors. */
2627 uint16_t u16ParityCount;
2628 /** Reserved. */
2629 uint16_t u16Reserved;
2630 } fields;
2631 } u;
2632} MptConfigurationPageSCSISPIDevice3, *PMptConfigurationPageSCSISPIDevice3;
2633#pragma pack()
2634AssertCompileSize(MptConfigurationPageSCSISPIDevice3, 12);
2635
2636/**
2637 * PHY entry for the SAS I/O unit page 0
2638 */
2639#pragma pack(1)
2640typedef struct MptConfigurationPageSASIOUnit0PHY
2641{
2642 /** Port number */
2643 uint8_t u8Port;
2644 /** Port flags */
2645 uint8_t u8PortFlags;
2646 /** Phy flags */
2647 uint8_t u8PhyFlags;
2648 /** negotiated link rate */
2649 uint8_t u8NegotiatedLinkRate;
2650 /** Controller phy device info */
2651 uint32_t u32ControllerPhyDeviceInfo;
2652 /** Attached device handle */
2653 uint16_t u16AttachedDevHandle;
2654 /** Controller device handle */
2655 uint16_t u16ControllerDevHandle;
2656 /** Discovery status */
2657 uint32_t u32DiscoveryStatus;
2658} MptConfigurationPageSASIOUnit0PHY, *PMptConfigurationPageSASIOUnit0PHY;
2659#pragma pack()
2660AssertCompileSize(MptConfigurationPageSASIOUnit0PHY, 16);
2661
2662/**
2663 * SAS I/O Unit page 0 - Readonly
2664 */
2665#pragma pack(1)
2666typedef struct MptConfigurationPageSASIOUnit0
2667{
2668 /** Union. */
2669 union
2670 {
2671 /** Byte view - variable. */
2672 uint8_t abPageData[1];
2673 /** Field view. */
2674 struct
2675 {
2676 /** The omnipresent header. */
2677 MptExtendedConfigurationPageHeader ExtHeader;
2678 /** Nvdata version default */
2679 uint16_t u16NvdataVersionDefault;
2680 /** Nvdata version persistent */
2681 uint16_t u16NvdataVersionPersistent;
2682 /** Number of physical ports */
2683 uint8_t u8NumPhys;
2684 /** Reserved */
2685 uint8_t au8Reserved[3];
2686 /** Content for each physical port - variable depending on the amount of ports. */
2687 MptConfigurationPageSASIOUnit0PHY aPHY[1];
2688 } fields;
2689 } u;
2690} MptConfigurationPageSASIOUnit0, *PMptConfigurationPageSASIOUnit0;
2691#pragma pack()
2692AssertCompileSize(MptConfigurationPageSASIOUnit0, 8+2+2+1+3+sizeof(MptConfigurationPageSASIOUnit0PHY));
2693
2694#define LSILOGICSCSI_SASIOUNIT0_GET_SIZE(ports) (sizeof(MptConfigurationPageSASIOUnit0) + ((ports) - 1) * sizeof(MptConfigurationPageSASIOUnit0PHY))
2695
2696#define LSILOGICSCSI_SASIOUNIT0_PORT_CONFIGURATION_AUTO RT_BIT(0)
2697#define LSILOGICSCSI_SASIOUNIT0_PORT_TARGET_IOC RT_BIT(2)
2698#define LSILOGICSCSI_SASIOUNIT0_PORT_DISCOVERY_IN_STATUS RT_BIT(3)
2699
2700#define LSILOGICSCSI_SASIOUNIT0_PHY_RX_INVERTED RT_BIT(0)
2701#define LSILOGICSCSI_SASIOUNIT0_PHY_TX_INVERTED RT_BIT(1)
2702#define LSILOGICSCSI_SASIOUNIT0_PHY_DISABLED RT_BIT(2)
2703
2704#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_SET(x) ((x) & 0x0F)
2705#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_GET(x) ((x) & 0x0F)
2706#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_UNKNOWN 0x00
2707#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_DISABLED 0x01
2708#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_FAILED 0x02
2709#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_SATA_OOB 0x03
2710#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_15GB 0x08
2711#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_30GB 0x09
2712
2713#define LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_SET(x) ((x) & 0x3)
2714#define LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_NO 0x0
2715#define LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_END 0x1
2716#define LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_EDGE_EXPANDER 0x2
2717#define LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_FANOUT_EXPANDER 0x3
2718
2719#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SATA_HOST RT_BIT(3)
2720#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SMP_INITIATOR RT_BIT(4)
2721#define LSILOGICSCSI_SASIOUNIT0_DEVICE_STP_INITIATOR RT_BIT(5)
2722#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SSP_INITIATOR RT_BIT(6)
2723#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SATA RT_BIT(7)
2724#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SMP_TARGET RT_BIT(8)
2725#define LSILOGICSCSI_SASIOUNIT0_DEVICE_STP_TARGET RT_BIT(9)
2726#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SSP_TARGET RT_BIT(10)
2727#define LSILOGICSCSI_SASIOUNIT0_DEVICE_DIRECT_ATTACHED RT_BIT(11)
2728#define LSILOGICSCSI_SASIOUNIT0_DEVICE_LSI RT_BIT(12)
2729#define LSILOGICSCSI_SASIOUNIT0_DEVICE_ATAPI_DEVICE RT_BIT(13)
2730#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SEP_DEVICE RT_BIT(14)
2731
2732#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_LOOP RT_BIT(0)
2733#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_UNADDRESSABLE RT_BIT(1)
2734#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_SAME_SAS_ADDR RT_BIT(2)
2735#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_EXPANDER_ERROR RT_BIT(3)
2736#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_SMP_TIMEOUT RT_BIT(4)
2737#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_EXP_ROUTE_OOE RT_BIT(5)
2738#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_EXP_ROUTE_IDX RT_BIT(6)
2739#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_SMP_FUNC_FAILED RT_BIT(7)
2740#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_SMP_CRC_ERROR RT_BIT(8)
2741#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_SUBTRSCTIVE_LNK RT_BIT(9)
2742#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_TBL_LNK RT_BIT(10)
2743#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_UNSUPPORTED_DEV RT_BIT(11)
2744#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_MAX_SATA_TGTS RT_BIT(12)
2745#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_MULT_CTRLS RT_BIT(13)
2746
2747/**
2748 * PHY entry for the SAS I/O unit page 1
2749 */
2750#pragma pack(1)
2751typedef struct MptConfigurationPageSASIOUnit1PHY
2752{
2753 /** Port number */
2754 uint8_t u8Port;
2755 /** Port flags */
2756 uint8_t u8PortFlags;
2757 /** Phy flags */
2758 uint8_t u8PhyFlags;
2759 /** Max link rate */
2760 uint8_t u8MaxMinLinkRate;
2761 /** Controller phy device info */
2762 uint32_t u32ControllerPhyDeviceInfo;
2763 /** Maximum target port connect time */
2764 uint16_t u16MaxTargetPortConnectTime;
2765 /** Reserved */
2766 uint16_t u16Reserved;
2767} MptConfigurationPageSASIOUnit1PHY, *PMptConfigurationPageSASIOUnit1PHY;
2768#pragma pack()
2769AssertCompileSize(MptConfigurationPageSASIOUnit1PHY, 12);
2770
2771/**
2772 * SAS I/O Unit page 1 - Read/Write
2773 */
2774#pragma pack(1)
2775typedef struct MptConfigurationPageSASIOUnit1
2776{
2777 /** Union. */
2778 union
2779 {
2780 /** Byte view - variable. */
2781 uint8_t abPageData[1];
2782 /** Field view. */
2783 struct
2784 {
2785 /** The omnipresent header. */
2786 MptExtendedConfigurationPageHeader ExtHeader;
2787 /** Control flags */
2788 uint16_t u16ControlFlags;
2789 /** maximum number of SATA targets */
2790 uint16_t u16MaxNumSATATargets;
2791 /** additional control flags */
2792 uint16_t u16AdditionalControlFlags;
2793 /** Reserved */
2794 uint16_t u16Reserved;
2795 /** Number of PHYs */
2796 uint8_t u8NumPhys;
2797 /** maximum SATA queue depth */
2798 uint8_t u8SATAMaxQDepth;
2799 /** Delay for reporting missing devices. */
2800 uint8_t u8ReportDeviceMissingDelay;
2801 /** I/O device missing delay */
2802 uint8_t u8IODeviceMissingDelay;
2803 /** Content for each physical port - variable depending on the number of ports */
2804 MptConfigurationPageSASIOUnit1PHY aPHY[1];
2805 } fields;
2806 } u;
2807} MptConfigurationPageSASIOUnit1, *PMptConfigurationPageSASIOUnit1;
2808#pragma pack()
2809AssertCompileSize(MptConfigurationPageSASIOUnit1, 8+12+sizeof(MptConfigurationPageSASIOUnit1PHY));
2810
2811#define LSILOGICSCSI_SASIOUNIT1_GET_SIZE(ports) (sizeof(MptConfigurationPageSASIOUnit1) + ((ports) - 1) * sizeof(MptConfigurationPageSASIOUnit1PHY))
2812
2813#define LSILOGICSCSI_SASIOUNIT1_CONTROL_CLEAR_SATA_AFFILIATION RT_BIT(0)
2814#define LSILOGICSCSI_SASIOUNIT1_CONTROL_FIRST_LEVEL_DISCOVERY_ONLY RT_BIT(1)
2815#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SUBTRACTIVE_LNK_ILLEGAL RT_BIT(2)
2816#define LSILOGICSCSI_SASIOUNIT1_CONTROL_IOC_ENABLE_HIGH_PHY RT_BIT(3)
2817#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED RT_BIT(4)
2818#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED RT_BIT(5)
2819#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED RT_BIT(6)
2820#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_LBA48_REQUIRED RT_BIT(7)
2821#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_INIT_POSTPONED RT_BIT(8)
2822
2823#define LSILOGICSCSI_SASIOUNIT1_CONTROL_DEVICE_SUPPORT_SET(x) (((x) & 0x3) << 9)
2824#define LSILOGICSCSI_SASIOUNIT1_CONTROL_DEVICE_SUPPORT_GET(x) (((x) >> 9) & 0x3)
2825#define LSILOGICSCSI_SASIOUNIT1_CONTROL_DEVICE_SUPPORT_SAS_AND_SATA 0x00
2826#define LSILOGICSCSI_SASIOUNIT1_CONTROL_DEVICE_SUPPORT_SAS 0x01
2827#define LSILOGICSCSI_SASIOUNIT1_CONTROL_DEVICE_SUPPORT_SATA 0x02
2828
2829#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_EXP_ADDR RT_BIT(11)
2830#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_SETTINGS_PRESERV_REQUIRED RT_BIT(12)
2831#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_LIMIT_RATE_15GB RT_BIT(13)
2832#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_LIMIT_RATE_30GB RT_BIT(14)
2833#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SAS_SELF_TEST_ENABLED RT_BIT(15)
2834
2835#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_TBL_LNKS_ALLOW RT_BIT(0)
2836#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_SATA_RST_NO_AFFIL RT_BIT(1)
2837#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_SATA_RST_SELF_AFFIL RT_BIT(2)
2838#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_SATA_RST_OTHER_AFFIL RT_BIT(3)
2839#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_SATA_RST_PORT_EN_ONLY RT_BIT(4)
2840#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_HIDE_NON_ZERO_PHYS RT_BIT(5)
2841#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_SATA_ASYNC_NOTIF RT_BIT(6)
2842#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_MULT_PORTS_ILL_SAME_DOMAIN RT_BIT(7)
2843
2844#define LSILOGICSCSI_SASIOUNIT1_MISSING_DEVICE_DELAY_UNITS_16_SEC RT_BIT(7)
2845#define LSILOGICSCSI_SASIOUNIT1_MISSING_DEVICE_DELAY_SET(x) ((x) & 0x7F)
2846#define LSILOGICSCSI_SASIOUNIT1_MISSING_DEVICE_DELAY_GET(x) ((x) & 0x7F)
2847
2848#define LSILOGICSCSI_SASIOUNIT1_PORT_CONFIGURATION_AUTO RT_BIT(0)
2849#define LSILOGICSCSI_SASIOUNIT1_PORT_CONFIGURATION_IOC1 RT_BIT(2)
2850
2851#define LSILOGICSCSI_SASIOUNIT1_PHY_RX_INVERT RT_BIT(0)
2852#define LSILOGICSCSI_SASIOUNIT1_PHY_TX_INVERT RT_BIT(1)
2853#define LSILOGICSCSI_SASIOUNIT1_PHY_DISABLE RT_BIT(2)
2854
2855#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MIN_SET(x) ((x) & 0x0F)
2856#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MIN_GET(x) ((x) & 0x0F)
2857#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MAX_SET(x) (((x) & 0x0F) << 4)
2858#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MAX_GET(x) ((x >> 4) & 0x0F)
2859#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_15GB 0x8
2860#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_30GB 0x9
2861
2862#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_SET(x) ((x) & 0x3)
2863#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_GET(x) ((x) & 0x3)
2864#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_NO 0x0
2865#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_END 0x1
2866#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_EDGE_EXPANDER 0x2
2867#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_FANOUT_EXPANDER 0x3
2868#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_SMP_INITIATOR RT_BIT(4)
2869#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_STP_INITIATOR RT_BIT(5)
2870#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_SSP_INITIATOR RT_BIT(6)
2871#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_SMP_TARGET RT_BIT(8)
2872#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_STP_TARGET RT_BIT(9)
2873#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_SSP_TARGET RT_BIT(10)
2874#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_DIRECT_ATTACHED RT_BIT(11)
2875#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_LSI RT_BIT(12)
2876#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_ATAPI RT_BIT(13)
2877#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_SEP RT_BIT(14)
2878
2879/**
2880 * SAS I/O unit page 2 - Read/Write
2881 */
2882#pragma pack(1)
2883typedef struct MptConfigurationPageSASIOUnit2
2884{
2885 /** Union. */
2886 union
2887 {
2888 /** Byte view - variable. */
2889 uint8_t abPageData[1];
2890 /** Field view. */
2891 struct
2892 {
2893 /** The omnipresent header. */
2894 MptExtendedConfigurationPageHeader ExtHeader;
2895 /** Device numbers per enclosure */
2896 uint8_t u8NumDevsPerEnclosure;
2897 /** Boot device wait time */
2898 uint8_t u8BootDeviceWaitTime;
2899 /** Reserved */
2900 uint16_t u16Reserved;
2901 /** Maximum number of persistent Bus and target ID mappings */
2902 uint16_t u16MaxPersistentIDs;
2903 /** Number of persistent IDs used */
2904 uint16_t u16NumPersistentIDsUsed;
2905 /** Status */
2906 uint8_t u8Status;
2907 /** Flags */
2908 uint8_t u8Flags;
2909 /** Maximum number of physical mapped IDs */
2910 uint16_t u16MaxNumPhysicalMappedIDs;
2911 } fields;
2912 } u;
2913} MptConfigurationPageSASIOUnit2, *PMptConfigurationPageSASIOUnit2;
2914#pragma pack()
2915AssertCompileSize(MptConfigurationPageSASIOUnit2, 20);
2916
2917#define LSILOGICSCSI_SASIOUNIT2_STATUS_PERSISTENT_MAP_TBL_FULL RT_BIT(0)
2918#define LSILOGICSCSI_SASIOUNIT2_STATUS_PERSISTENT_MAP_DISABLED RT_BIT(1)
2919#define LSILOGICSCSI_SASIOUNIT2_STATUS_PERSISTENT_ENC_DEV_UNMAPPED RT_BIT(2)
2920#define LSILOGICSCSI_SASIOUNIT2_STATUS_PERSISTENT_DEV_LIMIT_EXCEEDED RT_BIT(3)
2921
2922#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_MAP_DISABLE RT_BIT(0)
2923#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_SET(x) ((x & 0x7) << 1)
2924#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_GET(x) ((x >> 1) & 0x7)
2925#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_NO 0x0
2926#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_DIRECT_ATTACHED 0x1
2927#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_ENC 0x2
2928#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_HOST 0x7
2929#define LSILOGICSCSI_SASIOUNIT2_FLAGS_RESERVE_TARGET_ID_ZERO RT_BIT(4)
2930#define LSILOGICSCSI_SASIOUNIT2_FLAGS_START_SLOT_NUMBER_ONE RT_BIT(5)
2931
2932/**
2933 * SAS I/O unit page 3 - Read/Write
2934 */
2935#pragma pack(1)
2936typedef struct MptConfigurationPageSASIOUnit3
2937{
2938 /** Union. */
2939 union
2940 {
2941 /** Byte view - variable. */
2942 uint8_t abPageData[1];
2943 /** Field view. */
2944 struct
2945 {
2946 /** The omnipresent header. */
2947 MptExtendedConfigurationPageHeader ExtHeader;
2948 /** Reserved */
2949 uint32_t u32Reserved;
2950 uint32_t u32MaxInvalidDwordCount;
2951 uint32_t u32InvalidDwordCountTime;
2952 uint32_t u32MaxRunningDisparityErrorCount;
2953 uint32_t u32RunningDisparityErrorTime;
2954 uint32_t u32MaxLossDwordSynchCount;
2955 uint32_t u32LossDwordSynchCountTime;
2956 uint32_t u32MaxPhysResetProblemCount;
2957 uint32_t u32PhyResetProblemTime;
2958 } fields;
2959 } u;
2960} MptConfigurationPageSASIOUnit3, *PMptConfigurationPageSASIOUnit3;
2961#pragma pack()
2962AssertCompileSize(MptConfigurationPageSASIOUnit3, 44);
2963
2964/**
2965 * SAS PHY page 0 - Readonly
2966 */
2967#pragma pack(1)
2968typedef struct MptConfigurationPageSASPHY0
2969{
2970 /** Union. */
2971 union
2972 {
2973 /** Byte view - variable. */
2974 uint8_t abPageData[1];
2975 /** Field view. */
2976 struct
2977 {
2978 /** The omnipresent header. */
2979 MptExtendedConfigurationPageHeader ExtHeader;
2980 /** Owner dev handle. */
2981 uint16_t u16OwnerDevHandle;
2982 /** Reserved */
2983 uint16_t u16Reserved0;
2984 /** SAS address */
2985 SASADDRESS SASAddress;
2986 /** Attached device handle */
2987 uint16_t u16AttachedDevHandle;
2988 /** Attached phy identifier */
2989 uint8_t u8AttachedPhyIdentifier;
2990 /** Reserved */
2991 uint8_t u8Reserved1;
2992 /** Attached device information */
2993 uint32_t u32AttachedDeviceInfo;
2994 /** Programmed link rate */
2995 uint8_t u8ProgrammedLinkRate;
2996 /** Hardware link rate */
2997 uint8_t u8HwLinkRate;
2998 /** Change count */
2999 uint8_t u8ChangeCount;
3000 /** Flags */
3001 uint8_t u8Flags;
3002 /** Phy information */
3003 uint32_t u32PhyInfo;
3004 } fields;
3005 } u;
3006} MptConfigurationPageSASPHY0, *PMptConfigurationPageSASPHY0;
3007#pragma pack()
3008AssertCompileSize(MptConfigurationPageSASPHY0, 36);
3009
3010#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_SET(x) ((x) & 0x3)
3011#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_GET(x) ((x) & 0x3)
3012#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_NO 0x0
3013#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_END 0x1
3014#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_EDGE_EXPANDER 0x2
3015#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_FANOUT_EXPANDER 0x3
3016#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_SMP_INITIATOR RT_BIT(4)
3017#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_STP_INITIATOR RT_BIT(5)
3018#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_SSP_INITIATOR RT_BIT(6)
3019#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_SMP_TARGET RT_BIT(8)
3020#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_STP_TARGET RT_BIT(9)
3021#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_SSP_TARGET RT_BIT(10)
3022#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_DIRECT_ATTACHED RT_BIT(11)
3023#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_LSI RT_BIT(12)
3024#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_ATAPI RT_BIT(13)
3025#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_SEP RT_BIT(14)
3026
3027/**
3028 * SAS PHY page 1 - Readonly
3029 */
3030#pragma pack(1)
3031typedef struct MptConfigurationPageSASPHY1
3032{
3033 /** Union. */
3034 union
3035 {
3036 /** Byte view - variable. */
3037 uint8_t abPageData[1];
3038 /** Field view. */
3039 struct
3040 {
3041 /** The omnipresent header. */
3042 MptExtendedConfigurationPageHeader ExtHeader;
3043 /** Reserved */
3044 uint32_t u32Reserved0;
3045 uint32_t u32InvalidDwordCound;
3046 uint32_t u32RunningDisparityErrorCount;
3047 uint32_t u32LossDwordSynchCount;
3048 uint32_t u32PhyResetProblemCount;
3049 } fields;
3050 } u;
3051} MptConfigurationPageSASPHY1, *PMptConfigurationPageSASPHY1;
3052#pragma pack()
3053AssertCompileSize(MptConfigurationPageSASPHY1, 28);
3054
3055/**
3056 * SAS Device page 0 - Readonly
3057 */
3058#pragma pack(1)
3059typedef struct MptConfigurationPageSASDevice0
3060{
3061 /** Union. */
3062 union
3063 {
3064 /** Byte view - variable. */
3065 uint8_t abPageData[1];
3066 /** Field view. */
3067 struct
3068 {
3069 /** The omnipresent header. */
3070 MptExtendedConfigurationPageHeader ExtHeader;
3071 /** Slot number */
3072 uint16_t u16Slot;
3073 /** Enclosure handle. */
3074 uint16_t u16EnclosureHandle;
3075 /** SAS address */
3076 SASADDRESS SASAddress;
3077 /** Parent device handle */
3078 uint16_t u16ParentDevHandle;
3079 /** Phy number */
3080 uint8_t u8PhyNum;
3081 /** Access status */
3082 uint8_t u8AccessStatus;
3083 /** Device handle */
3084 uint16_t u16DevHandle;
3085 /** Target ID */
3086 uint8_t u8TargetID;
3087 /** Bus */
3088 uint8_t u8Bus;
3089 /** Device info */
3090 uint32_t u32DeviceInfo;
3091 /** Flags */
3092 uint16_t u16Flags;
3093 /** Physical port */
3094 uint8_t u8PhysicalPort;
3095 /** Reserved */
3096 uint8_t u8Reserved0;
3097 } fields;
3098 } u;
3099} MptConfigurationPageSASDevice0, *PMptConfigurationPageSASDevice0;
3100#pragma pack()
3101AssertCompileSize(MptConfigurationPageSASDevice0, 36);
3102
3103#define LSILOGICSCSI_SASDEVICE0_STATUS_NO_ERRORS (0x00)
3104
3105#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_SET(x) ((x) & 0x3)
3106#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_GET(x) ((x) & 0x3)
3107#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_NO 0x0
3108#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_END 0x1
3109#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_EDGE_EXPANDER 0x2
3110#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_FANOUT_EXPANDER 0x3
3111#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_SMP_INITIATOR RT_BIT(4)
3112#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_STP_INITIATOR RT_BIT(5)
3113#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_SSP_INITIATOR RT_BIT(6)
3114#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_SMP_TARGET RT_BIT(8)
3115#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_STP_TARGET RT_BIT(9)
3116#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_SSP_TARGET RT_BIT(10)
3117#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_DIRECT_ATTACHED RT_BIT(11)
3118#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_LSI RT_BIT(12)
3119#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_ATAPI RT_BIT(13)
3120#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_SEP RT_BIT(14)
3121
3122#define LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_PRESENT (RT_BIT(0))
3123#define LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_MAPPED_TO_BUS_AND_TARGET_ID (RT_BIT(1))
3124#define LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_MAPPING_PERSISTENT (RT_BIT(2))
3125
3126/**
3127 * SAS Device page 1 - Readonly
3128 */
3129#pragma pack(1)
3130typedef struct MptConfigurationPageSASDevice1
3131{
3132 /** Union. */
3133 union
3134 {
3135 /** Byte view - variable. */
3136 uint8_t abPageData[1];
3137 /** Field view. */
3138 struct
3139 {
3140 /** The omnipresent header. */
3141 MptExtendedConfigurationPageHeader ExtHeader;
3142 /** Reserved */
3143 uint32_t u32Reserved0;
3144 /** SAS address */
3145 SASADDRESS SASAddress;
3146 /** Reserved */
3147 uint32_t u32Reserved;
3148 /** Device handle */
3149 uint16_t u16DevHandle;
3150 /** Target ID */
3151 uint8_t u8TargetID;
3152 /** Bus */
3153 uint8_t u8Bus;
3154 /** Initial REgister device FIS */
3155 uint32_t au32InitialRegDeviceFIS[5];
3156 } fields;
3157 } u;
3158} MptConfigurationPageSASDevice1, *PMptConfigurationPageSASDevice1;
3159#pragma pack()
3160AssertCompileSize(MptConfigurationPageSASDevice1, 48);
3161
3162/**
3163 * SAS Device page 2 - Read/Write persistent
3164 */
3165#pragma pack(1)
3166typedef struct MptConfigurationPageSASDevice2
3167{
3168 /** Union. */
3169 union
3170 {
3171 /** Byte view - variable. */
3172 uint8_t abPageData[1];
3173 /** Field view. */
3174 struct
3175 {
3176 /** The omnipresent header. */
3177 MptExtendedConfigurationPageHeader ExtHeader;
3178 /** Physical identifier */
3179 SASADDRESS SASAddress;
3180 /** Enclosure mapping */
3181 uint32_t u32EnclosureMapping;
3182 } fields;
3183 } u;
3184} MptConfigurationPageSASDevice2, *PMptConfigurationPageSASDevice2;
3185#pragma pack()
3186AssertCompileSize(MptConfigurationPageSASDevice2, 20);
3187
3188/**
3189 * A device entitiy containing all pages.
3190 */
3191typedef struct MptSASDevice
3192{
3193 /** Pointer to the next device if any. */
3194 struct MptSASDevice *pNext;
3195 /** Pointer to the previous device if any. */
3196 struct MptSASDevice *pPrev;
3197
3198 MptConfigurationPageSASDevice0 SASDevicePage0;
3199 MptConfigurationPageSASDevice1 SASDevicePage1;
3200 MptConfigurationPageSASDevice2 SASDevicePage2;
3201} MptSASDevice, *PMptSASDevice;
3202
3203/**
3204 * SAS Expander page 0 - Readonly
3205 */
3206#pragma pack(1)
3207typedef struct MptConfigurationPageSASExpander0
3208{
3209 /** Union. */
3210 union
3211 {
3212 /** Byte view - variable. */
3213 uint8_t abPageData[1];
3214 /** Field view. */
3215 struct
3216 {
3217 /** The omnipresent header. */
3218 MptExtendedConfigurationPageHeader ExtHeader;
3219 /** Physical port */
3220 uint8_t u8PhysicalPort;
3221 /** Reserved */
3222 uint8_t u8Reserved0;
3223 /** Enclosure handle */
3224 uint16_t u16EnclosureHandle;
3225 /** SAS address */
3226 SASADDRESS SASAddress;
3227 /** Discovery status */
3228 uint32_t u32DiscoveryStatus;
3229 /** Device handle. */
3230 uint16_t u16DevHandle;
3231 /** Parent device handle */
3232 uint16_t u16ParentDevHandle;
3233 /** Expander change count */
3234 uint16_t u16ExpanderChangeCount;
3235 /** Expander route indexes */
3236 uint16_t u16ExpanderRouteIndexes;
3237 /** Number of PHys in this expander */
3238 uint8_t u8NumPhys;
3239 /** SAS level */
3240 uint8_t u8SASLevel;
3241 /** Flags */
3242 uint8_t u8Flags;
3243 /** Reserved */
3244 uint8_t u8Reserved1;
3245 } fields;
3246 } u;
3247} MptConfigurationPageSASExpander0, *PMptConfigurationPageSASExpander0;
3248#pragma pack()
3249AssertCompileSize(MptConfigurationPageSASExpander0, 36);
3250
3251/**
3252 * SAS Expander page 1 - Readonly
3253 */
3254#pragma pack(1)
3255typedef struct MptConfigurationPageSASExpander1
3256{
3257 /** Union. */
3258 union
3259 {
3260 /** Byte view - variable. */
3261 uint8_t abPageData[1];
3262 /** Field view. */
3263 struct
3264 {
3265 /** The omnipresent header. */
3266 MptExtendedConfigurationPageHeader ExtHeader;
3267 /** Physical port */
3268 uint8_t u8PhysicalPort;
3269 /** Reserved */
3270 uint8_t u8Reserved0[3];
3271 /** Number of PHYs */
3272 uint8_t u8NumPhys;
3273 /** Number of the Phy the information in this page is for. */
3274 uint8_t u8Phy;
3275 /** Number of routing table entries */
3276 uint16_t u16NumTableEntriesProgrammed;
3277 /** Programmed link rate */
3278 uint8_t u8ProgrammedLinkRate;
3279 /** Hardware link rate */
3280 uint8_t u8HwLinkRate;
3281 /** Attached device handle */
3282 uint16_t u16AttachedDevHandle;
3283 /** Phy information */
3284 uint32_t u32PhyInfo;
3285 /** Attached device information */
3286 uint32_t u32AttachedDeviceInfo;
3287 /** Owner device handle. */
3288 uint16_t u16OwnerDevHandle;
3289 /** Change count */
3290 uint8_t u8ChangeCount;
3291 /** Negotiated link rate */
3292 uint8_t u8NegotiatedLinkRate;
3293 /** Phy identifier */
3294 uint8_t u8PhyIdentifier;
3295 /** Attached phy identifier */
3296 uint8_t u8AttachedPhyIdentifier;
3297 /** Reserved */
3298 uint8_t u8Reserved1;
3299 /** Discovery information */
3300 uint8_t u8DiscoveryInfo;
3301 /** Reserved */
3302 uint32_t u32Reserved;
3303 } fields;
3304 } u;
3305} MptConfigurationPageSASExpander1, *PMptConfigurationPageSASExpander1;
3306#pragma pack()
3307AssertCompileSize(MptConfigurationPageSASExpander1, 40);
3308
3309/**
3310 * Structure of all supported pages for the SCSI SPI controller.
3311 * Used to load the device state from older versions.
3312 */
3313typedef struct MptConfigurationPagesSupported_SSM_V2
3314{
3315 MptConfigurationPageManufacturing0 ManufacturingPage0;
3316 MptConfigurationPageManufacturing1 ManufacturingPage1;
3317 MptConfigurationPageManufacturing2 ManufacturingPage2;
3318 MptConfigurationPageManufacturing3 ManufacturingPage3;
3319 MptConfigurationPageManufacturing4 ManufacturingPage4;
3320 MptConfigurationPageIOUnit0 IOUnitPage0;
3321 MptConfigurationPageIOUnit1 IOUnitPage1;
3322 MptConfigurationPageIOUnit2 IOUnitPage2;
3323 MptConfigurationPageIOUnit3 IOUnitPage3;
3324 MptConfigurationPageIOC0 IOCPage0;
3325 MptConfigurationPageIOC1 IOCPage1;
3326 MptConfigurationPageIOC2 IOCPage2;
3327 MptConfigurationPageIOC3 IOCPage3;
3328 MptConfigurationPageIOC4 IOCPage4;
3329 MptConfigurationPageIOC6 IOCPage6;
3330 struct
3331 {
3332 MptConfigurationPageSCSISPIPort0 SCSISPIPortPage0;
3333 MptConfigurationPageSCSISPIPort1 SCSISPIPortPage1;
3334 MptConfigurationPageSCSISPIPort2 SCSISPIPortPage2;
3335 } aPortPages[1]; /* Currently only one port supported. */
3336 struct
3337 {
3338 struct
3339 {
3340 MptConfigurationPageSCSISPIDevice0 SCSISPIDevicePage0;
3341 MptConfigurationPageSCSISPIDevice1 SCSISPIDevicePage1;
3342 MptConfigurationPageSCSISPIDevice2 SCSISPIDevicePage2;
3343 MptConfigurationPageSCSISPIDevice3 SCSISPIDevicePage3;
3344 } aDevicePages[LSILOGICSCSI_PCI_SPI_DEVICES_MAX];
3345 } aBuses[1]; /* Only one bus at the moment. */
3346} MptConfigurationPagesSupported_SSM_V2, *PMptConfigurationPagesSupported_SSM_V2;
3347
3348typedef struct MptConfigurationPagesSpi
3349{
3350 struct
3351 {
3352 MptConfigurationPageSCSISPIPort0 SCSISPIPortPage0;
3353 MptConfigurationPageSCSISPIPort1 SCSISPIPortPage1;
3354 MptConfigurationPageSCSISPIPort2 SCSISPIPortPage2;
3355 } aPortPages[1]; /* Currently only one port supported. */
3356 struct
3357 {
3358 struct
3359 {
3360 MptConfigurationPageSCSISPIDevice0 SCSISPIDevicePage0;
3361 MptConfigurationPageSCSISPIDevice1 SCSISPIDevicePage1;
3362 MptConfigurationPageSCSISPIDevice2 SCSISPIDevicePage2;
3363 MptConfigurationPageSCSISPIDevice3 SCSISPIDevicePage3;
3364 } aDevicePages[LSILOGICSCSI_PCI_SPI_DEVICES_MAX];
3365 } aBuses[1]; /* Only one bus at the moment. */
3366} MptConfigurationPagesSpi, *PMptConfigurationPagesSpi;
3367
3368typedef struct MptPHY
3369{
3370 MptConfigurationPageSASPHY0 SASPHYPage0;
3371 MptConfigurationPageSASPHY1 SASPHYPage1;
3372} MptPHY, *PMptPHY;
3373
3374#pragma pack(1)
3375typedef struct MptConfigurationPagesSas
3376{
3377 /** Size of the manufacturing page 7 */
3378 uint32_t cbManufacturingPage7;
3379 /** Pointer to the manufacturing page 7 */
3380 PMptConfigurationPageManufacturing7 pManufacturingPage7;
3381 /** Size of the I/O unit page 0 */
3382 uint32_t cbSASIOUnitPage0;
3383 /** Pointer to the I/O unit page 0 */
3384 PMptConfigurationPageSASIOUnit0 pSASIOUnitPage0;
3385 /** Size of the I/O unit page 1 */
3386 uint32_t cbSASIOUnitPage1;
3387 /** Pointer to the I/O unit page 1 */
3388 PMptConfigurationPageSASIOUnit1 pSASIOUnitPage1;
3389 /** I/O unit page 2 */
3390 MptConfigurationPageSASIOUnit2 SASIOUnitPage2;
3391 /** I/O unit page 3 */
3392 MptConfigurationPageSASIOUnit3 SASIOUnitPage3;
3393
3394 /** Number of PHYs in the array. */
3395 uint32_t cPHYs;
3396 /** Pointer to an array of per PHYS pages. */
3397 R3PTRTYPE(PMptPHY) paPHYs;
3398
3399 /** Number of devices detected. */
3400 uint32_t cDevices;
3401 /** Pointer to the first SAS device. */
3402 R3PTRTYPE(PMptSASDevice) pSASDeviceHead;
3403 /** Pointer to the last SAS device. */
3404 R3PTRTYPE(PMptSASDevice) pSASDeviceTail;
3405} MptConfigurationPagesSas, *PMptConfigurationPagesSas;
3406#pragma pack()
3407
3408/**
3409 * Structure of all supported pages for both controllers.
3410 */
3411typedef struct MptConfigurationPagesSupported
3412{
3413 MptConfigurationPageManufacturing0 ManufacturingPage0;
3414 MptConfigurationPageManufacturing1 ManufacturingPage1;
3415 MptConfigurationPageManufacturing2 ManufacturingPage2;
3416 MptConfigurationPageManufacturing3 ManufacturingPage3;
3417 MptConfigurationPageManufacturing4 ManufacturingPage4;
3418 MptConfigurationPageManufacturing5 ManufacturingPage5;
3419 MptConfigurationPageManufacturing6 ManufacturingPage6;
3420 MptConfigurationPageManufacturing8 ManufacturingPage8;
3421 MptConfigurationPageManufacturing9 ManufacturingPage9;
3422 MptConfigurationPageManufacturing10 ManufacturingPage10;
3423 MptConfigurationPageIOUnit0 IOUnitPage0;
3424 MptConfigurationPageIOUnit1 IOUnitPage1;
3425 MptConfigurationPageIOUnit2 IOUnitPage2;
3426 MptConfigurationPageIOUnit3 IOUnitPage3;
3427 MptConfigurationPageIOUnit4 IOUnitPage4;
3428 MptConfigurationPageIOC0 IOCPage0;
3429 MptConfigurationPageIOC1 IOCPage1;
3430 MptConfigurationPageIOC2 IOCPage2;
3431 MptConfigurationPageIOC3 IOCPage3;
3432 MptConfigurationPageIOC4 IOCPage4;
3433 MptConfigurationPageIOC6 IOCPage6;
3434 /* BIOS page 0 is not described */
3435 MptConfigurationPageBIOS1 BIOSPage1;
3436 MptConfigurationPageBIOS2 BIOSPage2;
3437 /* BIOS page 3 is not described */
3438 MptConfigurationPageBIOS4 BIOSPage4;
3439
3440 /** Controller dependent data. */
3441 union
3442 {
3443 MptConfigurationPagesSpi SpiPages;
3444 MptConfigurationPagesSas SasPages;
3445 } u;
3446} MptConfigurationPagesSupported, *PMptConfigurationPagesSupported;
3447
3448/**
3449 * Initializes a page header.
3450 */
3451#define MPT_CONFIG_PAGE_HEADER_INIT(pg, type, nr, flags) \
3452 (pg)->u.fields.Header.u8PageType = flags; \
3453 (pg)->u.fields.Header.u8PageNumber = nr; \
3454 (pg)->u.fields.Header.u8PageLength = sizeof(type) / 4
3455
3456#define MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(pg, type, nr, flags) \
3457 MPT_CONFIG_PAGE_HEADER_INIT(pg, type, nr, flags | MPT_CONFIGURATION_PAGE_TYPE_MANUFACTURING)
3458
3459#define MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(pg, type, nr, flags) \
3460 MPT_CONFIG_PAGE_HEADER_INIT(pg, type, nr, flags | MPT_CONFIGURATION_PAGE_TYPE_IO_UNIT)
3461
3462#define MPT_CONFIG_PAGE_HEADER_INIT_IOC(pg, type, nr, flags) \
3463 MPT_CONFIG_PAGE_HEADER_INIT(pg, type, nr, flags | MPT_CONFIGURATION_PAGE_TYPE_IOC)
3464
3465#define MPT_CONFIG_PAGE_HEADER_INIT_BIOS(pg, type, nr, flags) \
3466 MPT_CONFIG_PAGE_HEADER_INIT(pg, type, nr, flags | MPT_CONFIGURATION_PAGE_TYPE_BIOS)
3467
3468/**
3469 * Initializes a extended page header.
3470 */
3471#define MPT_CONFIG_EXTENDED_PAGE_HEADER_INIT(pg, cb, nr, flags, exttype) \
3472 (pg)->u.fields.ExtHeader.u8PageType = flags | MPT_CONFIGURATION_PAGE_TYPE_EXTENDED; \
3473 (pg)->u.fields.ExtHeader.u8PageNumber = nr; \
3474 (pg)->u.fields.ExtHeader.u8ExtPageType = exttype; \
3475 (pg)->u.fields.ExtHeader.u16ExtPageLength = cb / 4
3476
3477/**
3478 * Possible SG element types.
3479 */
3480enum MPTSGENTRYTYPE
3481{
3482 MPTSGENTRYTYPE_TRANSACTION_CONTEXT = 0x00,
3483 MPTSGENTRYTYPE_SIMPLE = 0x01,
3484 MPTSGENTRYTYPE_CHAIN = 0x03
3485};
3486
3487/**
3488 * Register interface.
3489 */
3490
3491/**
3492 * Defined states that the SCSI controller can have.
3493 */
3494typedef enum LSILOGICSTATE
3495{
3496 /** Reset state. */
3497 LSILOGICSTATE_RESET = 0x00,
3498 /** Ready state. */
3499 LSILOGICSTATE_READY = 0x01,
3500 /** Operational state. */
3501 LSILOGICSTATE_OPERATIONAL = 0x02,
3502 /** Fault state. */
3503 LSILOGICSTATE_FAULT = 0x04,
3504 /** 32bit size hack */
3505 LSILOGICSTATE_32BIT_HACK = 0x7fffffff
3506} LSILOGICSTATE;
3507
3508/**
3509 * Which entity needs to initialize the controller
3510 * to get into the operational state.
3511 */
3512typedef enum LSILOGICWHOINIT
3513{
3514 /** Not initialized. */
3515 LSILOGICWHOINIT_NOT_INITIALIZED = 0x00,
3516 /** System BIOS. */
3517 LSILOGICWHOINIT_SYSTEM_BIOS = 0x01,
3518 /** ROM Bios. */
3519 LSILOGICWHOINIT_ROM_BIOS = 0x02,
3520 /** PCI Peer. */
3521 LSILOGICWHOINIT_PCI_PEER = 0x03,
3522 /** Host driver. */
3523 LSILOGICWHOINIT_HOST_DRIVER = 0x04,
3524 /** Manufacturing. */
3525 LSILOGICWHOINIT_MANUFACTURING = 0x05,
3526 /** 32bit size hack. */
3527 LSILOGICWHOINIT_32BIT_HACK = 0x7fffffff
3528} LSILOGICWHOINIT;
3529
3530
3531/**
3532 * Doorbell state.
3533 */
3534typedef enum LSILOGICDOORBELLSTATE
3535{
3536 /** Invalid value. */
3537 LSILOGICDOORBELLSTATE_INVALID = 0,
3538 /** Doorbell not in use. */
3539 LSILOGICDOORBELLSTATE_NOT_IN_USE,
3540 /** Reply frame removal, transfer number of entries, low 16bits. */
3541 LSILOGICDOORBELLSTATE_RFR_FRAME_COUNT_LOW,
3542 /** Reply frame removal, transfer number of entries, high 16bits. */
3543 LSILOGICDOORBELLSTATE_RFR_FRAME_COUNT_HIGH,
3544 /** Reply frame removal, remove next free frame, low part. */
3545 LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_LOW,
3546 /** Reply frame removal, remove next free frame, high part. */
3547 LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_HIGH,
3548 /** Function handshake. */
3549 LSILOGICDOORBELLSTATE_FN_HANDSHAKE,
3550 /** 32bit hack. */
3551 LSILOGICDOORBELLSTATE_32BIT_HACK = 0x7fffffff
3552} LSILOGICDOORBELLSTATE;
3553/** Pointer to a doorbell state. */
3554typedef LSILOGICDOORBELLSTATE *PLSILOGICDOORBELLSTATE;
3555
3556
3557/**
3558 * IOC status codes.
3559 */
3560#define LSILOGIC_IOCSTATUS_SUCCESS 0x0000
3561#define LSILOGIC_IOCSTATUS_INVALID_FUNCTION 0x0001
3562#define LSILOGIC_IOCSTATUS_BUSY 0x0002
3563#define LSILOGIC_IOCSTATUS_INVALID_SGL 0x0003
3564#define LSILOGIC_IOCSTATUS_INTERNAL_ERROR 0x0004
3565#define LSILOGIC_IOCSTATUS_RESERVED 0x0005
3566#define LSILOGIC_IOCSTATUS_INSUFFICIENT_RESOURCES 0x0006
3567#define LSILOGIC_IOCSTATUS_INVALID_FIELD 0x0007
3568#define LSILOGIC_IOCSTATUS_INVALID_STATE 0x0008
3569#define LSILOGIC_IOCSTATUS_OP_STATE_NOT_SUPPOTED 0x0009
3570
3571/**
3572 * Size of the I/O and MMIO space.
3573 */
3574#define LSILOGIC_PCI_SPACE_IO_SIZE 256
3575#define LSILOGIC_PCI_SPACE_MEM_SIZE 128 * _1K
3576
3577/**
3578 * Doorbell register - Used to get the status of the controller and
3579 * initialise it.
3580 */
3581#define LSILOGIC_REG_DOORBELL 0x00
3582# define LSILOGIC_REG_DOORBELL_SET_STATE(enmState) (((enmState) & 0x0f) << 28)
3583# define LSILOGIC_REG_DOORBELL_SET_USED(enmDoorbell) (((enmDoorbell != LSILOGICDOORBELLSTATE_NOT_IN_USE) ? 1 : 0) << 27)
3584# define LSILOGIC_REG_DOORBELL_SET_WHOINIT(enmWhoInit) (((enmWhoInit) & 0x07) << 24)
3585# define LSILOGIC_REG_DOORBELL_SET_FAULT_CODE(u16Code) (u16Code)
3586# define LSILOGIC_REG_DOORBELL_GET_FUNCTION(x) (((x) & 0xff000000) >> 24)
3587# define LSILOGIC_REG_DOORBELL_GET_SIZE(x) (((x) & 0x00ff0000) >> 16)
3588
3589/**
3590 * Functions which can be passed through the system doorbell.
3591 */
3592#define LSILOGIC_DOORBELL_FUNCTION_IOC_MSG_UNIT_RESET 0x40
3593#define LSILOGIC_DOORBELL_FUNCTION_IO_UNIT_RESET 0x41
3594#define LSILOGIC_DOORBELL_FUNCTION_HANDSHAKE 0x42
3595#define LSILOGIC_DOORBELL_FUNCTION_REPLY_FRAME_REMOVAL 0x43
3596
3597/**
3598 * Write sequence register for the diagnostic register.
3599 */
3600#define LSILOGIC_REG_WRITE_SEQUENCE 0x04
3601
3602/**
3603 * Diagnostic register - used to reset the controller.
3604 */
3605#define LSILOGIC_REG_HOST_DIAGNOSTIC 0x08
3606# define LSILOGIC_REG_HOST_DIAGNOSTIC_DIAG_MEM_ENABLE (RT_BIT(0))
3607# define LSILOGIC_REG_HOST_DIAGNOSTIC_DISABLE_ARM (RT_BIT(1))
3608# define LSILOGIC_REG_HOST_DIAGNOSTIC_RESET_ADAPTER (RT_BIT(2))
3609# define LSILOGIC_REG_HOST_DIAGNOSTIC_DIAG_RW_ENABLE (RT_BIT(4))
3610# define LSILOGIC_REG_HOST_DIAGNOSTIC_RESET_HISTORY (RT_BIT(5))
3611# define LSILOGIC_REG_HOST_DIAGNOSTIC_FLASH_BAD_SIG (RT_BIT(6))
3612# define LSILOGIC_REG_HOST_DIAGNOSTIC_DRWE (RT_BIT(7))
3613# define LSILOGIC_REG_HOST_DIAGNOSTIC_PREVENT_IOC_BOOT (RT_BIT(9))
3614# define LSILOGIC_REG_HOST_DIAGNOSTIC_CLEAR_FLASH_BAD_SIG (RT_BIT(10))
3615
3616#define LSILOGIC_REG_TEST_BASE_ADDRESS 0x0c
3617#define LSILOGIC_REG_DIAG_RW_DATA 0x10
3618#define LSILOGIC_REG_DIAG_RW_ADDRESS 0x14
3619
3620/**
3621 * Interrupt status register.
3622 */
3623#define LSILOGIC_REG_HOST_INTR_STATUS 0x30
3624# define LSILOGIC_REG_HOST_INTR_STATUS_W_MASK (RT_BIT(3))
3625# define LSILOGIC_REG_HOST_INTR_STATUS_DOORBELL_STS (RT_BIT(31))
3626# define LSILOGIC_REG_HOST_INTR_STATUS_REPLY_INTR (RT_BIT(3))
3627# define LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL (RT_BIT(0))
3628
3629/**
3630 * Interrupt mask register.
3631 */
3632#define LSILOGIC_REG_HOST_INTR_MASK 0x34
3633# define LSILOGIC_REG_HOST_INTR_MASK_W_MASK (RT_BIT(0) | RT_BIT(3) | RT_BIT(8) | RT_BIT(9))
3634# define LSILOGIC_REG_HOST_INTR_MASK_IRQ_ROUTING (RT_BIT(8) | RT_BIT(9))
3635# define LSILOGIC_REG_HOST_INTR_MASK_DOORBELL RT_BIT(0)
3636# define LSILOGIC_REG_HOST_INTR_MASK_REPLY RT_BIT(3)
3637
3638/**
3639 * Queue registers.
3640 */
3641#define LSILOGIC_REG_REQUEST_QUEUE 0x40
3642#define LSILOGIC_REG_REPLY_QUEUE 0x44
3643
3644#endif /* __DEVLSILOGICSCSI_H__ */
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