| 1 | /* $Id: $ */
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| 2 | /** @file
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| 3 | *
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| 4 | * VBox storage devices:
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| 5 | * PIIX3 ATA busmaster controller definitions
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| 6 | */
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| 7 |
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| 8 | /*
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| 9 | * Copyright (C) 2006-2015 Oracle Corporation
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| 10 | *
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| 11 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 12 | * available from http://www.virtualbox.org. This file is free software;
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| 13 | * you can redistribute it and/or modify it under the terms of the GNU
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| 14 | * General Public License (GPL) as published by the Free Software
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| 15 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 16 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 17 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 18 | */
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| 19 |
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| 20 | #ifndef __PIIX3ATABmDma_h__
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| 21 | #define __PIIX3ATABmDma_h__
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| 22 |
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| 23 |
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| 24 | /** @defgroup grp_piix3atabmdma PIIX3 ATA Bus Master DMA
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| 25 | * @{
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| 26 | */
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| 27 |
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| 28 | /** @name BM_STATUS
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| 29 | * @{
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| 30 | */
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| 31 | /** Currently performing a DMA operation. */
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| 32 | #define BM_STATUS_DMAING 0x01
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| 33 | /** An error occurred during the DMA operation. */
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| 34 | #define BM_STATUS_ERROR 0x02
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| 35 | /** The DMA unit has raised the IDE interrupt line. */
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| 36 | #define BM_STATUS_INT 0x04
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| 37 | /** User-defined bit 0, commonly used to signal that drive 0 supports DMA. */
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| 38 | #define BM_STATUS_D0DMA 0x20
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| 39 | /** User-defined bit 1, commonly used to signal that drive 1 supports DMA. */
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| 40 | #define BM_STATUS_D1DMA 0x40
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| 41 | /** @} */
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| 42 |
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| 43 | /** @name BM_CMD
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| 44 | * @{
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| 45 | */
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| 46 | /** Start the DMA operation. */
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| 47 | #define BM_CMD_START 0x01
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| 48 | /** Data transfer direction: from device to memory if set. */
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| 49 | #define BM_CMD_WRITE 0x08
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| 50 | /** @} */
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| 51 |
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| 52 |
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| 53 | /** PIIX3 Bus Master DMA unit state. */
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| 54 | typedef struct BMDMAState {
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| 55 | /** Command register. */
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| 56 | uint8_t u8Cmd;
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| 57 | /** Status register. */
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| 58 | uint8_t u8Status;
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| 59 | /** Address of the MMIO region in the guest's memory space. */
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| 60 | RTGCPHYS32 pvAddr;
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| 61 | } BMDMAState;
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| 62 |
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| 63 |
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| 64 | /** PIIX3 Bus Master DMA descriptor entry. */
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| 65 | typedef struct BMDMADesc {
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| 66 | /** Address of the DMA source/target buffer. */
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| 67 | RTGCPHYS32 pBuffer;
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| 68 | /** Size of the DMA source/target buffer. */
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| 69 | uint32_t cbBuffer;
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| 70 | } BMDMADesc;
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| 71 |
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| 72 | /** @} */
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| 73 |
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| 74 |
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| 75 | #endif /* !__PIIX3ATABmDma_h__ */
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