Virtio.cpp@ 71371

Last change on this file since 71371 was 71112, checked in by vboxsync, 7 years ago
virtio: Workaround for older guests which do not enable PCI bus mastering.
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File size: 34.4 KB

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1	/* $Id: Virtio.cpp 71112 2018-02-23 09:22:21Z vboxsync $ */
2	/** @file
3	* Virtio - Virtio Common Functions (VRing, VQueue, Virtio PCI)
4	*/
5
6	/*
7	* Copyright (C) 2009-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_VIRTIO
23
24	#include <iprt/param.h>
25	#include <iprt/uuid.h>
26	#include <VBox/vmm/pdmdev.h>
27	#include "Virtio.h"
28
29	#define INSTANCE(pState) pState->szInstance
30	#define IFACE_TO_STATE(pIface, ifaceName) ((VPCISTATE )((char)pIface - RT_OFFSETOF(VPCISTATE, ifaceName)))
31
32	#ifdef LOG_ENABLED
33	# define QUEUENAME(s, q) (q->pcszName)
34	#endif
35
36
37
38	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
39
40	//RT_C_DECLS_BEGIN
41	//RT_C_DECLS_END
42
43
44	static void vqueueReset(PVQUEUE pQueue)
45	{
46	pQueue->VRing.addrDescriptors = 0;
47	pQueue->VRing.addrAvail = 0;
48	pQueue->VRing.addrUsed = 0;
49	pQueue->uNextAvailIndex = 0;
50	pQueue->uNextUsedIndex = 0;
51	pQueue->uPageNumber = 0;
52	}
53
54	static void vqueueInit(PVQUEUE pQueue, uint32_t uPageNumber)
55	{
56	pQueue->VRing.addrDescriptors = (uint64_t)uPageNumber << PAGE_SHIFT;
57	pQueue->VRing.addrAvail = pQueue->VRing.addrDescriptors
58	+ sizeof(VRINGDESC) * pQueue->VRing.uSize;
59	pQueue->VRing.addrUsed = RT_ALIGN(
60	pQueue->VRing.addrAvail + RT_OFFSETOF(VRINGAVAIL, auRing[pQueue->VRing.uSize]),
61	PAGE_SIZE); /* The used ring must start from the next page. */
62	pQueue->uNextAvailIndex = 0;
63	pQueue->uNextUsedIndex = 0;
64	}
65
66	// void vqueueElemFree(PVQUEUEELEM pElem)
67	// {
68	// }
69
70	void vringReadDesc(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex, PVRINGDESC pDesc)
71	{
72	//Log(("%s vringReadDesc: ring=%p idx=%u\n", INSTANCE(pState), pVRing, uIndex));
73	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
74	pVRing->addrDescriptors + sizeof(VRINGDESC) * (uIndex % pVRing->uSize),
75	pDesc, sizeof(VRINGDESC));
76	}
77
78	uint16_t vringReadAvail(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex)
79	{
80	uint16_t tmp;
81
82	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
83	pVRing->addrAvail + RT_OFFSETOF(VRINGAVAIL, auRing[uIndex % pVRing->uSize]),
84	&tmp, sizeof(tmp));
85	return tmp;
86	}
87
88	uint16_t vringReadAvailFlags(PVPCISTATE pState, PVRING pVRing)
89	{
90	uint16_t tmp;
91
92	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
93	pVRing->addrAvail + RT_OFFSETOF(VRINGAVAIL, uFlags),
94	&tmp, sizeof(tmp));
95	return tmp;
96	}
97
98	void vringSetNotification(PVPCISTATE pState, PVRING pVRing, bool fEnabled)
99	{
100	uint16_t tmp;
101
102	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
103	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uFlags),
104	&tmp, sizeof(tmp));
105
106	if (fEnabled)
107	tmp &= ~ VRINGUSED_F_NO_NOTIFY;
108	else
109	tmp \|= VRINGUSED_F_NO_NOTIFY;
110
111	PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns),
112	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uFlags),
113	&tmp, sizeof(tmp));
114	}
115
116	bool vqueueSkip(PVPCISTATE pState, PVQUEUE pQueue)
117	{
118	if (vqueueIsEmpty(pState, pQueue))
119	return false;
120
121	Log2(("%s vqueueSkip: %s avail_idx=%u\n", INSTANCE(pState),
122	QUEUENAME(pState, pQueue), pQueue->uNextAvailIndex));
123	pQueue->uNextAvailIndex++;
124	return true;
125	}
126
127	bool vqueueGet(PVPCISTATE pState, PVQUEUE pQueue, PVQUEUEELEM pElem, bool fRemove)
128	{
129	if (vqueueIsEmpty(pState, pQueue))
130	return false;
131
132	pElem->nIn = pElem->nOut = 0;
133
134	Log2(("%s vqueueGet: %s avail_idx=%u\n", INSTANCE(pState),
135	QUEUENAME(pState, pQueue), pQueue->uNextAvailIndex));
136
137	VRINGDESC desc;
138	uint16_t idx = vringReadAvail(pState, &pQueue->VRing, pQueue->uNextAvailIndex);
139	if (fRemove)
140	pQueue->uNextAvailIndex++;
141	pElem->uIndex = idx;
142	do
143	{
144	VQUEUESEG *pSeg;
145
146	/*
147	* Malicious guests may try to trick us into writing beyond aSegsIn or
148	* aSegsOut boundaries by linking several descriptors into a loop. We
149	* cannot possibly get a sequence of linked descriptors exceeding the
150	* total number of descriptors in the ring (see @bugref{8620}).
151	*/
152	if (pElem->nIn + pElem->nOut >= VRING_MAX_SIZE)
153	{
154	static volatile uint32_t s_cMessages = 0;
155	static volatile uint32_t s_cThreshold = 1;
156	if (ASMAtomicIncU32(&s_cMessages) == ASMAtomicReadU32(&s_cThreshold))
157	{
158	LogRel(("%s: too many linked descriptors; check if the guest arranges descriptors in a loop.\n",
159	INSTANCE(pState)));
160	if (ASMAtomicReadU32(&s_cMessages) != 1)
161	LogRel(("%s: (the above error has occured %u times so far)\n",
162	INSTANCE(pState), ASMAtomicReadU32(&s_cMessages)));
163	ASMAtomicWriteU32(&s_cThreshold, ASMAtomicReadU32(&s_cThreshold) * 10);
164	}
165	break;
166	}
167
168	vringReadDesc(pState, &pQueue->VRing, idx, &desc);
169	if (desc.u16Flags & VRINGDESC_F_WRITE)
170	{
171	Log2(("%s vqueueGet: %s IN seg=%u desc_idx=%u addr=%p cb=%u\n", INSTANCE(pState),
172	QUEUENAME(pState, pQueue), pElem->nIn, idx, desc.u64Addr, desc.uLen));
173	pSeg = &pElem->aSegsIn[pElem->nIn++];
174	}
175	else
176	{
177	Log2(("%s vqueueGet: %s OUT seg=%u desc_idx=%u addr=%p cb=%u\n", INSTANCE(pState),
178	QUEUENAME(pState, pQueue), pElem->nOut, idx, desc.u64Addr, desc.uLen));
179	pSeg = &pElem->aSegsOut[pElem->nOut++];
180	}
181
182	pSeg->addr = desc.u64Addr;
183	pSeg->cb = desc.uLen;
184	pSeg->pv = NULL;
185
186	idx = desc.u16Next;
187	} while (desc.u16Flags & VRINGDESC_F_NEXT);
188
189	Log2(("%s vqueueGet: %s head_desc_idx=%u nIn=%u nOut=%u\n", INSTANCE(pState),
190	QUEUENAME(pState, pQueue), pElem->uIndex, pElem->nIn, pElem->nOut));
191	return true;
192	}
193
194	uint16_t vringReadUsedIndex(PVPCISTATE pState, PVRING pVRing)
195	{
196	uint16_t tmp;
197	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
198	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uIndex),
199	&tmp, sizeof(tmp));
200	return tmp;
201	}
202
203	void vringWriteUsedIndex(PVPCISTATE pState, PVRING pVRing, uint16_t u16Value)
204	{
205	PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns),
206	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uIndex),
207	&u16Value, sizeof(u16Value));
208	}
209
210	void vringWriteUsedElem(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex, uint32_t uId, uint32_t uLen)
211	{
212	VRINGUSEDELEM elem;
213
214	elem.uId = uId;
215	elem.uLen = uLen;
216	PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns),
217	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, aRing[uIndex % pVRing->uSize]),
218	&elem, sizeof(elem));
219	}
220
221
222	void vqueuePut(PVPCISTATE pState, PVQUEUE pQueue,
223	PVQUEUEELEM pElem, uint32_t uTotalLen, uint32_t uReserved)
224	{
225	Log2(("%s vqueuePut: %s"
226	" desc_idx=%u acb=%u (%u)\n",
227	INSTANCE(pState), QUEUENAME(pState, pQueue),
228	pElem->uIndex, uTotalLen, uReserved));
229
230	Assert(uReserved < uTotalLen);
231
232	uint32_t cbLen = uTotalLen - uReserved;
233	uint32_t cbSkip = uReserved;
234
235	for (unsigned i = 0; i < pElem->nIn && cbLen > 0; ++i)
236	{
237	if (cbSkip >= pElem->aSegsIn[i].cb) /* segment completely skipped? */
238	{
239	cbSkip -= pElem->aSegsIn[i].cb;
240	continue;
241	}
242
243	uint32_t cbSegLen = pElem->aSegsIn[i].cb - cbSkip;
244	if (cbSegLen > cbLen) /* last segment only partially used? */
245	cbSegLen = cbLen;
246
247	/*
248	* XXX: We should assert pv != NULL, but we need to check and
249	* fix all callers first.
250	*/
251	if (pElem->aSegsIn[i].pv != NULL)
252	{
253	Log2(("%s vqueuePut: %s"
254	" used_idx=%u seg=%u addr=%p pv=%p cb=%u acb=%u\n",
255	INSTANCE(pState), QUEUENAME(pState, pQueue),
256	pQueue->uNextUsedIndex, i,
257	(void *)pElem->aSegsIn[i].addr, pElem->aSegsIn[i].pv,
258	pElem->aSegsIn[i].cb, cbSegLen));
259
260	PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns),
261	pElem->aSegsIn[i].addr + cbSkip,
262	pElem->aSegsIn[i].pv,
263	cbSegLen);
264	}
265
266	cbSkip = 0;
267	cbLen -= cbSegLen;
268	}
269
270	Log2(("%s vqueuePut: %s"
271	" used_idx=%u guest_used_idx=%u id=%u len=%u\n",
272	INSTANCE(pState), QUEUENAME(pState, pQueue),
273	pQueue->uNextUsedIndex, vringReadUsedIndex(pState, &pQueue->VRing),
274	pElem->uIndex, uTotalLen));
275
276	vringWriteUsedElem(pState, &pQueue->VRing,
277	pQueue->uNextUsedIndex++,
278	pElem->uIndex, uTotalLen);
279	}
280
281
282	void vqueueNotify(PVPCISTATE pState, PVQUEUE pQueue)
283	{
284	LogFlow(("%s vqueueNotify: %s availFlags=%x guestFeatures=%x vqueue is %sempty\n",
285	INSTANCE(pState), QUEUENAME(pState, pQueue),
286	vringReadAvailFlags(pState, &pQueue->VRing),
287	pState->uGuestFeatures, vqueueIsEmpty(pState, pQueue)?"":"not "));
288	if (!(vringReadAvailFlags(pState, &pQueue->VRing) & VRINGAVAIL_F_NO_INTERRUPT)
289	\|\| ((pState->uGuestFeatures & VPCI_F_NOTIFY_ON_EMPTY) && vqueueIsEmpty(pState, pQueue)))
290	{
291	int rc = vpciRaiseInterrupt(pState, VERR_INTERNAL_ERROR, VPCI_ISR_QUEUE);
292	if (RT_FAILURE(rc))
293	Log(("%s vqueueNotify: Failed to raise an interrupt (%Rrc).\n", INSTANCE(pState), rc));
294	}
295	else
296	{
297	STAM_COUNTER_INC(&pState->StatIntsSkipped);
298	}
299
300	}
301
302	void vqueueSync(PVPCISTATE pState, PVQUEUE pQueue)
303	{
304	Log2(("%s vqueueSync: %s old_used_idx=%u new_used_idx=%u\n", INSTANCE(pState),
305	QUEUENAME(pState, pQueue), vringReadUsedIndex(pState, &pQueue->VRing), pQueue->uNextUsedIndex));
306	vringWriteUsedIndex(pState, &pQueue->VRing, pQueue->uNextUsedIndex);
307	vqueueNotify(pState, pQueue);
308	}
309
310	void vpciReset(PVPCISTATE pState)
311	{
312	pState->uGuestFeatures = 0;
313	pState->uQueueSelector = 0;
314	pState->uStatus = 0;
315	pState->uISR = 0;
316
317	for (unsigned i = 0; i < pState->nQueues; i++)
318	vqueueReset(&pState->Queues[i]);
319	}
320
321
322	/**
323	* Raise interrupt.
324	*
325	* @param pState The device state structure.
326	* @param rcBusy Status code to return when the critical section is busy.
327	* @param u8IntCause Interrupt cause bit mask to set in PCI ISR port.
328	*/
329	int vpciRaiseInterrupt(VPCISTATE *pState, int rcBusy, uint8_t u8IntCause)
330	{
331	RT_NOREF_PV(rcBusy);
332	// int rc = vpciCsEnter(pState, rcBusy);
333	// if (RT_UNLIKELY(rc != VINF_SUCCESS))
334	// return rc;
335
336	STAM_COUNTER_INC(&pState->StatIntsRaised);
337	LogFlow(("%s vpciRaiseInterrupt: u8IntCause=%x\n",
338	INSTANCE(pState), u8IntCause));
339
340	pState->uISR \|= u8IntCause;
341	PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 1);
342	// vpciCsLeave(pState);
343	return VINF_SUCCESS;
344	}
345
346	/**
347	* Lower interrupt.
348	*
349	* @param pState The device state structure.
350	*/
351	static void vpciLowerInterrupt(VPCISTATE *pState)
352	{
353	LogFlow(("%s vpciLowerInterrupt\n", INSTANCE(pState)));
354	PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 0);
355	}
356
357	DECLINLINE(uint32_t) vpciGetHostFeatures(PVPCISTATE pState,
358	PFNGETHOSTFEATURES pfnGetHostFeatures)
359	{
360	return pfnGetHostFeatures(pState)
361	\| VPCI_F_NOTIFY_ON_EMPTY;
362	}
363
364	/**
365	* Port I/O Handler for IN operations.
366	*
367	* @returns VBox status code.
368	*
369	* @param pDevIns The device instance.
370	* @param pvUser Pointer to the device state structure.
371	* @param Port Port number used for the IN operation.
372	* @param pu32 Where to store the result.
373	* @param cb Number of bytes read.
374	* @param pCallbacks Pointer to the callbacks.
375	* @thread EMT
376	*/
377	int vpciIOPortIn(PPDMDEVINS pDevIns,
378	void *pvUser,
379	RTIOPORT Port,
380	uint32_t *pu32,
381	unsigned cb,
382	PCVPCIIOCALLBACKS pCallbacks)
383	{
384	VPCISTATE pState = PDMINS_2_DATA(pDevIns, VPCISTATE );
385	int rc = VINF_SUCCESS;
386	STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIORead), a);
387	RT_NOREF_PV(pvUser);
388
389	/*
390	* We probably do not need to enter critical section when reading registers
391	* as the most of them are either constant or being changed during
392	* initialization only, the exception being ISR which can be raced by all
393	* threads but I see no big harm in it. It also happens to be the most read
394	* register as it gets read in interrupt handler. By dropping cs protection
395	* here we gain the ability to deliver RX packets to the guest while TX is
396	* holding cs transmitting queued packets.
397	*
398	rc = vpciCsEnter(pState, VINF_IOM_R3_IOPORT_READ);
399	if (RT_UNLIKELY(rc != VINF_SUCCESS))
400	{
401	STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIORead), a);
402	return rc;
403	}*/
404
405	Port -= pState->IOPortBase;
406	switch (Port)
407	{
408	case VPCI_HOST_FEATURES:
409	/* Tell the guest what features we support. */
410	*pu32 = vpciGetHostFeatures(pState, pCallbacks->pfnGetHostFeatures)
411	\| VPCI_F_BAD_FEATURE;
412	break;
413
414	case VPCI_GUEST_FEATURES:
415	*pu32 = pState->uGuestFeatures;
416	break;
417
418	case VPCI_QUEUE_PFN:
419	*pu32 = pState->Queues[pState->uQueueSelector].uPageNumber;
420	break;
421
422	case VPCI_QUEUE_NUM:
423	Assert(cb == 2);
424	(uint16_t)pu32 = pState->Queues[pState->uQueueSelector].VRing.uSize;
425	break;
426
427	case VPCI_QUEUE_SEL:
428	Assert(cb == 2);
429	(uint16_t)pu32 = pState->uQueueSelector;
430	break;
431
432	case VPCI_STATUS:
433	Assert(cb == 1);
434	(uint8_t)pu32 = pState->uStatus;
435	break;
436
437	case VPCI_ISR:
438	Assert(cb == 1);
439	(uint8_t)pu32 = pState->uISR;
440	pState->uISR = 0; /* read clears all interrupts */
441	vpciLowerInterrupt(pState);
442	break;
443
444	default:
445	if (Port >= VPCI_CONFIG)
446	rc = pCallbacks->pfnGetConfig(pState, Port - VPCI_CONFIG, cb, pu32);
447	else
448	{
449	*pu32 = 0xFFFFFFFF;
450	rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortIn: no valid port at offset port=%RTiop cb=%08x\n",
451	INSTANCE(pState), Port, cb);
452	}
453	break;
454	}
455	Log3(("%s vpciIOPortIn: At %RTiop in %0x\n", INSTANCE(pState), Port, cb2, *pu32));
456	STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIORead), a);
457	//vpciCsLeave(pState);
458	return rc;
459	}
460
461
462	/**
463	* Port I/O Handler for OUT operations.
464	*
465	* @returns VBox status code.
466	*
467	* @param pDevIns The device instance.
468	* @param pvUser User argument.
469	* @param Port Port number used for the IN operation.
470	* @param u32 The value to output.
471	* @param cb The value size in bytes.
472	* @param pCallbacks Pointer to the callbacks.
473	* @thread EMT
474	*/
475	int vpciIOPortOut(PPDMDEVINS pDevIns,
476	void *pvUser,
477	RTIOPORT Port,
478	uint32_t u32,
479	unsigned cb,
480	PCVPCIIOCALLBACKS pCallbacks)
481	{
482	VPCISTATE pState = PDMINS_2_DATA(pDevIns, VPCISTATE );
483	int rc = VINF_SUCCESS;
484	bool fHasBecomeReady;
485	STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIOWrite), a);
486	RT_NOREF_PV(pvUser);
487
488	Port -= pState->IOPortBase;
489	Log3(("%s virtioIOPortOut: At %RTiop out %0x\n", INSTANCE(pState), Port, cb2, u32));
490
491	switch (Port)
492	{
493	case VPCI_GUEST_FEATURES:
494	{
495	const uint32_t uHostFeatures = vpciGetHostFeatures(pState, pCallbacks->pfnGetHostFeatures);
496
497	if (RT_LIKELY((u32 & ~uHostFeatures) == 0))
498	{
499	pState->uGuestFeatures = u32;
500	}
501	else
502	{
503	/*
504	* Guest requests features we don't advertise. Stick
505	* to the minimum if negotiation looks completely
506	* botched, otherwise restrict to advertised features.
507	*/
508	if (u32 & VPCI_F_BAD_FEATURE)
509	{
510	Log(("%s WARNING! Guest failed to negotiate properly (guest=%x)\n",
511	INSTANCE(pState), u32));
512	pState->uGuestFeatures = pCallbacks->pfnGetHostMinimalFeatures(pState);
513	}
514	else
515	{
516	Log(("%s Guest asked for features host does not support! (host=%x guest=%x)\n",
517	INSTANCE(pState), uHostFeatures, u32));
518	pState->uGuestFeatures = u32 & uHostFeatures;
519	}
520	}
521	pCallbacks->pfnSetHostFeatures(pState, pState->uGuestFeatures);
522	break;
523	}
524
525	case VPCI_QUEUE_PFN:
526	/*
527	* The guest is responsible for allocating the pages for queues,
528	* here it provides us with the page number of descriptor table.
529	* Note that we provide the size of the queue to the guest via
530	* VIRTIO_PCI_QUEUE_NUM.
531	*/
532	pState->Queues[pState->uQueueSelector].uPageNumber = u32;
533	if (u32)
534	vqueueInit(&pState->Queues[pState->uQueueSelector], u32);
535	else
536	rc = pCallbacks->pfnReset(pState);
537	break;
538
539	case VPCI_QUEUE_SEL:
540	Assert(cb == 2);
541	u32 &= 0xFFFF;
542	if (u32 < pState->nQueues)
543	pState->uQueueSelector = u32;
544	else
545	Log3(("%s vpciIOPortOut: Invalid queue selector %08x\n", INSTANCE(pState), u32));
546	break;
547
548	case VPCI_QUEUE_NOTIFY:
549	#ifdef IN_RING3
550	Assert(cb == 2);
551	u32 &= 0xFFFF;
552	if (u32 < pState->nQueues)
553	if (pState->Queues[u32].VRing.addrDescriptors)
554	{
555	// rc = vpciCsEnter(pState, VERR_SEM_BUSY);
556	// if (RT_LIKELY(rc == VINF_SUCCESS))
557	// {
558	pState->Queues[u32].pfnCallback(pState, &pState->Queues[u32]);
559	// vpciCsLeave(pState);
560	// }
561	}
562	else
563	Log(("%s The queue (#%d) being notified has not been initialized.\n",
564	INSTANCE(pState), u32));
565	else
566	Log(("%s Invalid queue number (%d)\n", INSTANCE(pState), u32));
567	#else
568	rc = VINF_IOM_R3_IOPORT_WRITE;
569	#endif
570	break;
571
572	case VPCI_STATUS:
573	Assert(cb == 1);
574	u32 &= 0xFF;
575	fHasBecomeReady = !(pState->uStatus & VPCI_STATUS_DRV_OK) && (u32 & VPCI_STATUS_DRV_OK);
576	pState->uStatus = u32;
577	/* Writing 0 to the status port triggers device reset. */
578	if (u32 == 0)
579	rc = pCallbacks->pfnReset(pState);
580	else if (fHasBecomeReady)
581	{
582	/* Older hypervisors were lax and did not enforce bus mastering. Older guests
583	* (Linux prior to 2.6.34, NetBSD 6.x) were lazy and did not enable bus mastering.
584	* We automagically enable bus mastering on driver initialization to make existing
585	* drivers work.
586	*/
587	PDMPciDevSetCommand(&pState->pciDevice, PDMPciDevGetCommand(&pState->pciDevice) \| PCI_COMMAND_BUSMASTER);
588
589	pCallbacks->pfnReady(pState);
590	}
591	break;
592
593	default:
594	if (Port >= VPCI_CONFIG)
595	rc = pCallbacks->pfnSetConfig(pState, Port - VPCI_CONFIG, cb, &u32);
596	else
597	rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortOut: no valid port at offset Port=%RTiop cb=%08x\n",
598	INSTANCE(pState), Port, cb);
599	break;
600	}
601
602	STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIOWrite), a);
603	return rc;
604	}
605
606	#ifdef IN_RING3
607
608	/**
609	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
610	*/
611	void vpciQueryInterface(struct PDMIBASE pInterface, const char *pszIID)
612	{
613	VPCISTATE *pThis = IFACE_TO_STATE(pInterface, IBase);
614	Assert(&pThis->IBase == pInterface);
615
616	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
617	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
618	return NULL;
619	}
620
621	/**
622	* Gets the pointer to the status LED of a unit.
623	*
624	* @returns VBox status code.
625	* @param pInterface Pointer to the interface structure.
626	* @param iLUN The unit which status LED we desire.
627	* @param ppLed Where to store the LED pointer.
628	* @thread EMT
629	*/
630	static DECLCALLBACK(int) vpciQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
631	{
632	VPCISTATE *pState = IFACE_TO_STATE(pInterface, ILeds);
633	int rc = VERR_PDM_LUN_NOT_FOUND;
634
635	if (iLUN == 0)
636	{
637	*ppLed = &pState->led;
638	rc = VINF_SUCCESS;
639	}
640	return rc;
641	}
642
643	/**
644	* Turns on/off the write status LED.
645	*
646	* @returns VBox status code.
647	* @param pState Pointer to the device state structure.
648	* @param fOn New LED state.
649	*/
650	void vpciSetWriteLed(PVPCISTATE pState, bool fOn)
651	{
652	LogFlow(("%s vpciSetWriteLed: %s\n", INSTANCE(pState), fOn?"on":"off"));
653	if (fOn)
654	pState->led.Asserted.s.fWriting = pState->led.Actual.s.fWriting = 1;
655	else
656	pState->led.Actual.s.fWriting = fOn;
657	}
658
659	/**
660	* Turns on/off the read status LED.
661	*
662	* @returns VBox status code.
663	* @param pState Pointer to the device state structure.
664	* @param fOn New LED state.
665	*/
666	void vpciSetReadLed(PVPCISTATE pState, bool fOn)
667	{
668	LogFlow(("%s vpciSetReadLed: %s\n", INSTANCE(pState), fOn?"on":"off"));
669	if (fOn)
670	pState->led.Asserted.s.fReading = pState->led.Actual.s.fReading = 1;
671	else
672	pState->led.Actual.s.fReading = fOn;
673	}
674
675
676	#if 0 /* unused */
677	/**
678	* Sets 32-bit register in PCI configuration space.
679	* @param refPciDev The PCI device.
680	* @param uOffset The register offset.
681	* @param u32Value The value to store in the register.
682	* @thread EMT
683	*/
684	DECLINLINE(void) vpciCfgSetU32(PDMPCIDEV& refPciDev, uint32_t uOffset, uint32_t u32Value)
685	{
686	Assert(uOffset+sizeof(u32Value) <= sizeof(refPciDev.config));
687	(uint32_t)&refPciDev.config[uOffset] = u32Value;
688	}
689	#endif /* unused */
690
691
692	#ifdef DEBUG
693	static void vpciDumpState(PVPCISTATE pState, const char *pcszCaller)
694	{
695	Log2(("vpciDumpState: (called from %s)\n"
696	" uGuestFeatures = 0x%08x\n"
697	" uQueueSelector = 0x%04x\n"
698	" uStatus = 0x%02x\n"
699	" uISR = 0x%02x\n",
700	pcszCaller,
701	pState->uGuestFeatures,
702	pState->uQueueSelector,
703	pState->uStatus,
704	pState->uISR));
705
706	for (unsigned i = 0; i < pState->nQueues; i++)
707	Log2((" %s queue:\n"
708	" VRing.uSize = %u\n"
709	" VRing.addrDescriptors = %p\n"
710	" VRing.addrAvail = %p\n"
711	" VRing.addrUsed = %p\n"
712	" uNextAvailIndex = %u\n"
713	" uNextUsedIndex = %u\n"
714	" uPageNumber = %x\n",
715	pState->Queues[i].pcszName,
716	pState->Queues[i].VRing.uSize,
717	pState->Queues[i].VRing.addrDescriptors,
718	pState->Queues[i].VRing.addrAvail,
719	pState->Queues[i].VRing.addrUsed,
720	pState->Queues[i].uNextAvailIndex,
721	pState->Queues[i].uNextUsedIndex,
722	pState->Queues[i].uPageNumber));
723	}
724	#else
725	# define vpciDumpState(x, s) do {} while (0)
726	#endif
727
728	/**
729	* Saves the state of device.
730	*
731	* @returns VBox status code.
732	* @param pDevIns The device instance.
733	* @param pSSM The handle to the saved state.
734	*/
735	int vpciSaveExec(PVPCISTATE pState, PSSMHANDLE pSSM)
736	{
737	int rc;
738
739	vpciDumpState(pState, "vpciSaveExec");
740
741	rc = SSMR3PutU32(pSSM, pState->uGuestFeatures);
742	AssertRCReturn(rc, rc);
743	rc = SSMR3PutU16(pSSM, pState->uQueueSelector);
744	AssertRCReturn(rc, rc);
745	rc = SSMR3PutU8( pSSM, pState->uStatus);
746	AssertRCReturn(rc, rc);
747	rc = SSMR3PutU8( pSSM, pState->uISR);
748	AssertRCReturn(rc, rc);
749
750	/* Save queue states */
751	rc = SSMR3PutU32(pSSM, pState->nQueues);
752	AssertRCReturn(rc, rc);
753	for (unsigned i = 0; i < pState->nQueues; i++)
754	{
755	rc = SSMR3PutU16(pSSM, pState->Queues[i].VRing.uSize);
756	AssertRCReturn(rc, rc);
757	rc = SSMR3PutU32(pSSM, pState->Queues[i].uPageNumber);
758	AssertRCReturn(rc, rc);
759	rc = SSMR3PutU16(pSSM, pState->Queues[i].uNextAvailIndex);
760	AssertRCReturn(rc, rc);
761	rc = SSMR3PutU16(pSSM, pState->Queues[i].uNextUsedIndex);
762	AssertRCReturn(rc, rc);
763	}
764
765	return VINF_SUCCESS;
766	}
767
768	/**
769	* Loads a saved device state.
770	*
771	* @returns VBox status code.
772	* @param pDevIns The device instance.
773	* @param pSSM The handle to the saved state.
774	* @param uVersion The data unit version number.
775	* @param uPass The data pass.
776	*/
777	int vpciLoadExec(PVPCISTATE pState, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass, uint32_t nQueues)
778	{
779	int rc;
780
781	if (uPass == SSM_PASS_FINAL)
782	{
783	/* Restore state data */
784	rc = SSMR3GetU32(pSSM, &pState->uGuestFeatures);
785	AssertRCReturn(rc, rc);
786	rc = SSMR3GetU16(pSSM, &pState->uQueueSelector);
787	AssertRCReturn(rc, rc);
788	rc = SSMR3GetU8( pSSM, &pState->uStatus);
789	AssertRCReturn(rc, rc);
790	rc = SSMR3GetU8( pSSM, &pState->uISR);
791	AssertRCReturn(rc, rc);
792
793	/* Restore queues */
794	if (uVersion > VIRTIO_SAVEDSTATE_VERSION_3_1_BETA1)
795	{
796	rc = SSMR3GetU32(pSSM, &pState->nQueues);
797	AssertRCReturn(rc, rc);
798	}
799	else
800	pState->nQueues = nQueues;
801	for (unsigned i = 0; i < pState->nQueues; i++)
802	{
803	rc = SSMR3GetU16(pSSM, &pState->Queues[i].VRing.uSize);
804	AssertRCReturn(rc, rc);
805	rc = SSMR3GetU32(pSSM, &pState->Queues[i].uPageNumber);
806	AssertRCReturn(rc, rc);
807
808	if (pState->Queues[i].uPageNumber)
809	vqueueInit(&pState->Queues[i], pState->Queues[i].uPageNumber);
810
811	rc = SSMR3GetU16(pSSM, &pState->Queues[i].uNextAvailIndex);
812	AssertRCReturn(rc, rc);
813	rc = SSMR3GetU16(pSSM, &pState->Queues[i].uNextUsedIndex);
814	AssertRCReturn(rc, rc);
815	}
816	}
817
818	vpciDumpState(pState, "vpciLoadExec");
819
820	return VINF_SUCCESS;
821	}
822
823	/**
824	* Set PCI configuration space registers.
825	*
826	* @param pci Reference to PCI device structure.
827	* @param uDeviceId VirtiO Device Id
828	* @param uClass Class of PCI device (network, etc)
829	* @thread EMT
830	*/
831	static DECLCALLBACK(void) vpciConfigure(PDMPCIDEV& pci,
832	uint16_t uDeviceId,
833	uint16_t uClass)
834	{
835	/* Configure PCI Device, assume 32-bit mode ******************************/
836	PCIDevSetVendorId(&pci, DEVICE_PCI_VENDOR_ID);
837	PCIDevSetDeviceId(&pci, DEVICE_PCI_BASE_ID + uDeviceId);
838	PDMPciDevSetWord(&pci, VBOX_PCI_SUBSYSTEM_VENDOR_ID, DEVICE_PCI_SUBSYSTEM_VENDOR_ID);
839	PDMPciDevSetWord(&pci, VBOX_PCI_SUBSYSTEM_ID, DEVICE_PCI_SUBSYSTEM_BASE_ID + uDeviceId);
840
841	/* ABI version, must be equal 0 as of 2.6.30 kernel. */
842	PDMPciDevSetByte(&pci, VBOX_PCI_REVISION_ID, 0x00);
843	/* Ethernet adapter */
844	PDMPciDevSetByte(&pci, VBOX_PCI_CLASS_PROG, 0x00);
845	PDMPciDevSetWord(&pci, VBOX_PCI_CLASS_DEVICE, uClass);
846	/* Interrupt Pin: INTA# */
847	PDMPciDevSetByte(&pci, VBOX_PCI_INTERRUPT_PIN, 0x01);
848
849	#ifdef VBOX_WITH_MSI_DEVICES
850	PCIDevSetCapabilityList(&pci, 0x80);
851	PCIDevSetStatus( &pci, VBOX_PCI_STATUS_CAP_LIST);
852	#endif
853	}
854
855	#ifdef VBOX_WITH_STATISTICS
856	/* WARNING! This function must never be used in multithreaded context! */
857	static const char vpciCounter(const char pszDevFmt,
858	const char *pszCounter)
859	{
860	static char s_szCounterName[80];
861
862	RTStrPrintf(s_szCounterName, sizeof(s_szCounterName),
863	"/Devices/%s/%s", pszDevFmt, pszCounter);
864
865	return s_szCounterName;
866	}
867	#endif
868
869	/// @todo header
870	int vpciConstruct(PPDMDEVINS pDevIns, VPCISTATE *pState,
871	int iInstance, const char *pcszNameFmt,
872	uint16_t uDeviceId, uint16_t uClass,
873	uint32_t nQueues)
874	{
875	/* Init handles and log related stuff. */
876	RTStrPrintf(pState->szInstance, sizeof(pState->szInstance),
877	pcszNameFmt, iInstance);
878
879	pState->pDevInsR3 = pDevIns;
880	pState->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
881	pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
882	pState->led.u32Magic = PDMLED_MAGIC;
883
884	pState->ILeds.pfnQueryStatusLed = vpciQueryStatusLed;
885
886	/* Initialize critical section. */
887	int rc = PDMDevHlpCritSectInit(pDevIns, &pState->cs, RT_SRC_POS, "%s", pState->szInstance);
888	if (RT_FAILURE(rc))
889	return rc;
890
891	/* Set PCI config registers */
892	vpciConfigure(pState->pciDevice, uDeviceId, uClass);
893	/* Register PCI device */
894	rc = PDMDevHlpPCIRegister(pDevIns, &pState->pciDevice);
895	if (RT_FAILURE(rc))
896	return rc;
897
898	#ifdef VBOX_WITH_MSI_DEVICES
899	#if 0
900	{
901	PDMMSIREG aMsiReg;
902
903	RT_ZERO(aMsiReg);
904	aMsiReg.cMsixVectors = 1;
905	aMsiReg.iMsixCapOffset = 0x80;
906	aMsiReg.iMsixNextOffset = 0x0;
907	aMsiReg.iMsixBar = 0;
908	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &aMsiReg);
909	if (RT_FAILURE (rc))
910	PCIDevSetCapabilityList(&pState->pciDevice, 0x0);
911	}
912	#endif
913	#endif
914
915	/* Status driver */
916	PPDMIBASE pBase;
917	rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pState->IBase, &pBase, "Status Port");
918	if (RT_FAILURE(rc))
919	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the status LUN"));
920	pState->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
921
922	pState->nQueues = nQueues;
923
924	#if defined(VBOX_WITH_STATISTICS)
925	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in GC", vpciCounter(pcszNameFmt, "IO/ReadGC"), iInstance);
926	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in HC", vpciCounter(pcszNameFmt, "IO/ReadHC"), iInstance);
927	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in GC", vpciCounter(pcszNameFmt, "IO/WriteGC"), iInstance);
928	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in HC", vpciCounter(pcszNameFmt, "IO/WriteHC"), iInstance);
929	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsRaised, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of raised interrupts", vpciCounter(pcszNameFmt, "Interrupts/Raised"), iInstance);
930	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsSkipped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of skipped interrupts", vpciCounter(pcszNameFmt, "Interrupts/Skipped"), iInstance);
931	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatCsGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling CS wait in GC", vpciCounter(pcszNameFmt, "Cs/CsGC"), iInstance);
932	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatCsHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling CS wait in HC", vpciCounter(pcszNameFmt, "Cs/CsHC"), iInstance);
933	#endif /* VBOX_WITH_STATISTICS */
934
935	return rc;
936	}
937
938	/**
939	* Destruct PCI-related part of device.
940	*
941	* We need to free non-VM resources only.
942	*
943	* @returns VBox status code.
944	* @param pState The device state structure.
945	*/
946	int vpciDestruct(VPCISTATE* pState)
947	{
948	Log(("%s Destroying PCI instance\n", INSTANCE(pState)));
949
950	if (PDMCritSectIsInitialized(&pState->cs))
951	PDMR3CritSectDelete(&pState->cs);
952
953	return VINF_SUCCESS;
954	}
955
956	/**
957	* Device relocation callback.
958	*
959	* When this callback is called the device instance data, and if the
960	* device have a GC component, is being relocated, or/and the selectors
961	* have been changed. The device must use the chance to perform the
962	* necessary pointer relocations and data updates.
963	*
964	* Before the GC code is executed the first time, this function will be
965	* called with a 0 delta so GC pointer calculations can be one in one place.
966	*
967	* @param pDevIns Pointer to the device instance.
968	* @param offDelta The relocation delta relative to the old location.
969	*
970	* @remark A relocation CANNOT fail.
971	*/
972	void vpciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
973	{
974	RT_NOREF(offDelta);
975	VPCISTATE pState = PDMINS_2_DATA(pDevIns, VPCISTATE);
976	pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
977	// TBD
978	}
979
980	PVQUEUE vpciAddQueue(VPCISTATE* pState, unsigned uSize, PFNVPCIQUEUECALLBACK pfnCallback, const char *pcszName)
981	{
982	PVQUEUE pQueue = NULL;
983	/* Find an empty queue slot */
984	for (unsigned i = 0; i < pState->nQueues; i++)
985	{
986	if (pState->Queues[i].VRing.uSize == 0)
987	{
988	pQueue = &pState->Queues[i];
989	break;
990	}
991	}
992
993	if (!pQueue)
994	{
995	Log(("%s Too many queues being added, no empty slots available!\n", INSTANCE(pState)));
996	}
997	else
998	{
999	pQueue->VRing.uSize = uSize;
1000	pQueue->VRing.addrDescriptors = 0;
1001	pQueue->uPageNumber = 0;
1002	pQueue->pfnCallback = pfnCallback;
1003	pQueue->pcszName = pcszName;
1004	}
1005
1006	return pQueue;
1007	}
1008
1009	#endif /* IN_RING3 */
1010
1011	#endif /* VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/VirtIO/Virtio.cpp@ 71371

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