Virtio.cpp@ 25985

Last change on this file since 25985 was 25985, checked in by vboxsync, 15 years ago
pdmifs.h: the final batch of refactored interface ID code.
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1	/* $Id: Virtio.cpp 25985 2010-01-23 00:51:04Z vboxsync $ */
2	/** @file
3	* Virtio - Virtio Common Functions (VRing, VQueue, Virtio PCI)
4	*/
5
6	/*
7	* Copyright (C) 2009-2010 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	#define LOG_GROUP LOG_GROUP_DEV_VIRTIO
24
25	#include <iprt/param.h>
26	#include <iprt/uuid.h>
27	#include <VBox/pdmdev.h>
28	#include "Virtio.h"
29
30	#define INSTANCE(pState) pState->szInstance
31	#define IFACE_TO_STATE(pIface, ifaceName) ((VPCISTATE )((char)pIface - RT_OFFSETOF(VPCISTATE, ifaceName)))
32
33	#ifdef DEBUG
34	#define QUEUENAME(s, q) (q->pcszName)
35	#endif /* DEBUG */
36
37
38
39	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
40
41	//RT_C_DECLS_BEGIN
42	//RT_C_DECLS_END
43
44
45	static void vqueueReset(PVQUEUE pQueue)
46	{
47	pQueue->VRing.addrDescriptors = 0;
48	pQueue->VRing.addrAvail = 0;
49	pQueue->VRing.addrUsed = 0;
50	pQueue->uNextAvailIndex = 0;
51	pQueue->uNextUsedIndex = 0;
52	pQueue->uPageNumber = 0;
53	}
54
55	static void vqueueInit(PVQUEUE pQueue, uint32_t uPageNumber)
56	{
57	pQueue->VRing.addrDescriptors = uPageNumber << PAGE_SHIFT;
58	pQueue->VRing.addrAvail = pQueue->VRing.addrDescriptors
59	+ sizeof(VRINGDESC) * pQueue->VRing.uSize;
60	pQueue->VRing.addrUsed = RT_ALIGN(
61	pQueue->VRing.addrAvail + RT_OFFSETOF(VRINGAVAIL, auRing[pQueue->VRing.uSize]),
62	PAGE_SIZE); /* The used ring must start from the next page. */
63	pQueue->uNextAvailIndex = 0;
64	pQueue->uNextUsedIndex = 0;
65	}
66
67	// void vqueueElemFree(PVQUEUEELEM pElem)
68	// {
69	// }
70
71	void vringReadDesc(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex, PVRINGDESC pDesc)
72	{
73	//Log(("%s vringReadDesc: ring=%p idx=%u\n", INSTANCE(pState), pVRing, uIndex));
74	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
75	pVRing->addrDescriptors + sizeof(VRINGDESC) * (uIndex % pVRing->uSize),
76	pDesc, sizeof(VRINGDESC));
77	}
78
79	uint16_t vringReadAvail(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex)
80	{
81	uint16_t tmp;
82
83	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
84	pVRing->addrAvail + RT_OFFSETOF(VRINGAVAIL, auRing[uIndex % pVRing->uSize]),
85	&tmp, sizeof(tmp));
86	return tmp;
87	}
88
89	uint16_t vringReadAvailFlags(PVPCISTATE pState, PVRING pVRing)
90	{
91	uint16_t tmp;
92
93	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
94	pVRing->addrAvail + RT_OFFSETOF(VRINGAVAIL, uFlags),
95	&tmp, sizeof(tmp));
96	return tmp;
97	}
98
99	void vringSetNotification(PVPCISTATE pState, PVRING pVRing, bool fEnabled)
100	{
101	uint16_t tmp;
102
103	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
104	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uFlags),
105	&tmp, sizeof(tmp));
106
107	if (fEnabled)
108	tmp &= ~ VRINGUSED_F_NO_NOTIFY;
109	else
110	tmp \|= VRINGUSED_F_NO_NOTIFY;
111
112	PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns),
113	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uFlags),
114	&tmp, sizeof(tmp));
115	}
116
117	bool vqueueGet(PVPCISTATE pState, PVQUEUE pQueue, PVQUEUEELEM pElem)
118	{
119	if (vqueueIsEmpty(pState, pQueue))
120	return false;
121
122	pElem->nIn = pElem->nOut = 0;
123
124	Log2(("%s vqueueGet: %s avail_idx=%u\n", INSTANCE(pState),
125	QUEUENAME(pState, pQueue), pQueue->uNextAvailIndex));
126
127	VRINGDESC desc;
128	uint16_t idx = vringReadAvail(pState, &pQueue->VRing, pQueue->uNextAvailIndex++);
129	pElem->uIndex = idx;
130	do
131	{
132	VQUEUESEG *pSeg;
133
134	vringReadDesc(pState, &pQueue->VRing, idx, &desc);
135	if (desc.u16Flags & VRINGDESC_F_WRITE)
136	{
137	Log2(("%s vqueueGet: %s IN seg=%u desc_idx=%u addr=%p cb=%u\n", INSTANCE(pState),
138	QUEUENAME(pState, pQueue), pElem->nIn, idx, desc.u64Addr, desc.uLen));
139	pSeg = &pElem->aSegsIn[pElem->nIn++];
140	}
141	else
142	{
143	Log2(("%s vqueueGet: %s OUT seg=%u desc_idx=%u addr=%p cb=%u\n", INSTANCE(pState),
144	QUEUENAME(pState, pQueue), pElem->nOut, idx, desc.u64Addr, desc.uLen));
145	pSeg = &pElem->aSegsOut[pElem->nOut++];
146	}
147
148	pSeg->addr = desc.u64Addr;
149	pSeg->cb = desc.uLen;
150	pSeg->pv = NULL;
151
152	idx = desc.u16Next;
153	} while (desc.u16Flags & VRINGDESC_F_NEXT);
154
155	Log2(("%s vqueueGet: %s head_desc_idx=%u nIn=%u nOut=%u\n", INSTANCE(pState),
156	QUEUENAME(pState, pQueue), pElem->uIndex, pElem->nIn, pElem->nOut));
157	return true;
158	}
159
160	uint16_t vringReadUsedIndex(PVPCISTATE pState, PVRING pVRing)
161	{
162	uint16_t tmp;
163	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
164	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uIndex),
165	&tmp, sizeof(tmp));
166	return tmp;
167	}
168
169	void vringWriteUsedIndex(PVPCISTATE pState, PVRING pVRing, uint16_t u16Value)
170	{
171	PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns),
172	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uIndex),
173	&u16Value, sizeof(u16Value));
174	}
175
176	void vringWriteUsedElem(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex, uint32_t uId, uint32_t uLen)
177	{
178	VRINGUSEDELEM elem;
179
180	elem.uId = uId;
181	elem.uLen = uLen;
182	PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns),
183	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, aRing[uIndex % pVRing->uSize]),
184	&elem, sizeof(elem));
185	}
186
187	void vqueuePut(PVPCISTATE pState, PVQUEUE pQueue, PVQUEUEELEM pElem, uint32_t uLen)
188	{
189	unsigned int i, uOffset;
190
191	Log2(("%s vqueuePut: %s desc_idx=%u acb=%u\n", INSTANCE(pState),
192	QUEUENAME(pState, pQueue), pElem->uIndex, uLen));
193	for (i = uOffset = 0; i < pElem->nIn && uOffset < uLen; i++)
194	{
195	uint32_t cbSegLen = RT_MIN(uLen - uOffset, pElem->aSegsIn[i].cb);
196	if (pElem->aSegsIn[i].pv)
197	{
198	Log2(("%s vqueuePut: %s used_idx=%u seg=%u addr=%p pv=%p cb=%u acb=%u\n", INSTANCE(pState),
199	QUEUENAME(pState, pQueue), pQueue->uNextUsedIndex, i, pElem->aSegsIn[i].addr, pElem->aSegsIn[i].pv, pElem->aSegsIn[i].cb, cbSegLen));
200	PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns), pElem->aSegsIn[i].addr,
201	pElem->aSegsIn[i].pv, cbSegLen);
202	}
203	uOffset += cbSegLen;
204	}
205
206	Log2(("%s vqueuePut: %s used_idx=%u guest_used_idx=%u id=%u len=%u\n", INSTANCE(pState),
207	QUEUENAME(pState, pQueue), pQueue->uNextUsedIndex, vringReadUsedIndex(pState, &pQueue->VRing), pElem->uIndex, uLen));
208	vringWriteUsedElem(pState, &pQueue->VRing, pQueue->uNextUsedIndex++, pElem->uIndex, uLen);
209	}
210
211	void vqueueNotify(PVPCISTATE pState, PVQUEUE pQueue)
212	{
213	LogFlow(("%s vqueueNotify: %s availFlags=%x guestFeatures=%x vqueue is %sempty\n",
214	INSTANCE(pState), QUEUENAME(pState, pQueue),
215	vringReadAvailFlags(pState, &pQueue->VRing),
216	pState->uGuestFeatures, vqueueIsEmpty(pState, pQueue)?"":"not "));
217	if (!(vringReadAvailFlags(pState, &pQueue->VRing) & VRINGAVAIL_F_NO_INTERRUPT)
218	\|\| ((pState->uGuestFeatures & VPCI_F_NOTIFY_ON_EMPTY) && vqueueIsEmpty(pState, pQueue)))
219	{
220	int rc = vpciRaiseInterrupt(pState, VERR_INTERNAL_ERROR, VPCI_ISR_QUEUE);
221	if (RT_FAILURE(rc))
222	Log(("%s vqueueNotify: Failed to raise an interrupt (%Vrc).\n", INSTANCE(pState), rc));
223	}
224	else
225	{
226	STAM_COUNTER_INC(&pState->StatIntsSkipped);
227	}
228
229	}
230
231	void vqueueSync(PVPCISTATE pState, PVQUEUE pQueue)
232	{
233	Log2(("%s vqueueSync: %s old_used_idx=%u new_used_idx=%u\n", INSTANCE(pState),
234	QUEUENAME(pState, pQueue), vringReadUsedIndex(pState, &pQueue->VRing), pQueue->uNextUsedIndex));
235	vringWriteUsedIndex(pState, &pQueue->VRing, pQueue->uNextUsedIndex);
236	vqueueNotify(pState, pQueue);
237	}
238
239	void vpciReset(PVPCISTATE pState)
240	{
241	pState->uGuestFeatures = 0;
242	pState->uQueueSelector = 0;
243	pState->uStatus = 0;
244	pState->uISR = 0;
245
246	for (unsigned i = 0; i < pState->nQueues; i++)
247	vqueueReset(&pState->Queues[i]);
248	}
249
250
251	/**
252	* Raise interrupt.
253	*
254	* @param pState The device state structure.
255	* @param rcBusy Status code to return when the critical section is busy.
256	* @param u8IntCause Interrupt cause bit mask to set in PCI ISR port.
257	*/
258	int vpciRaiseInterrupt(VPCISTATE *pState, int rcBusy, uint8_t u8IntCause)
259	{
260	// int rc = vpciCsEnter(pState, rcBusy);
261	// if (RT_UNLIKELY(rc != VINF_SUCCESS))
262	// return rc;
263
264	STAM_COUNTER_INC(&pState->StatIntsRaised);
265	LogFlow(("%s vpciRaiseInterrupt: u8IntCause=%x\n",
266	INSTANCE(pState), u8IntCause));
267
268	pState->uISR \|= u8IntCause;
269	PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 1);
270	// vpciCsLeave(pState);
271	return VINF_SUCCESS;
272	}
273
274	/**
275	* Lower interrupt.
276	*
277	* @param pState The device state structure.
278	*/
279	PDMBOTHCBDECL(void) vpciLowerInterrupt(VPCISTATE *pState)
280	{
281	LogFlow(("%s vpciLowerInterrupt\n", INSTANCE(pState)));
282	PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 0);
283	}
284
285	DECLINLINE(uint32_t) vpciGetHostFeatures(PVPCISTATE pState,
286	PFNGETHOSTFEATURES pfnGetHostFeatures)
287	{
288	return pfnGetHostFeatures(pState)
289	\| VPCI_F_NOTIFY_ON_EMPTY;
290	}
291
292	/**
293	* Port I/O Handler for IN operations.
294	*
295	* @returns VBox status code.
296	*
297	* @param pDevIns The device instance.
298	* @param pvUser Pointer to the device state structure.
299	* @param port Port number used for the IN operation.
300	* @param pu32 Where to store the result.
301	* @param cb Number of bytes read.
302	* @thread EMT
303	*/
304	int vpciIOPortIn(PPDMDEVINS pDevIns,
305	void *pvUser,
306	RTIOPORT port,
307	uint32_t *pu32,
308	unsigned cb,
309	PFNGETHOSTFEATURES pfnGetHostFeatures,
310	PFNGETCONFIG pfnGetConfig)
311	{
312	VPCISTATE pState = PDMINS_2_DATA(pDevIns, VPCISTATE );
313	int rc = VINF_SUCCESS;
314	const char *szInst = INSTANCE(pState);
315	STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIORead), a);
316
317	/*
318	* We probably do not need to enter critical section when reading registers
319	* as the most of them are either constant or being changed during
320	* initialization only, the exception being ISR which can be raced by all
321	* threads but I see no big harm in it. It also happens to be the most read
322	* register as it gets read in interrupt handler. By dropping cs protection
323	* here we gain the ability to deliver RX packets to the guest while TX is
324	* holding cs transmitting queued packets.
325	*
326	rc = vpciCsEnter(pState, VINF_IOM_HC_IOPORT_READ);
327	if (RT_UNLIKELY(rc != VINF_SUCCESS))
328	{
329	STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIORead), a);
330	return rc;
331	}*/
332
333	port -= pState->addrIOPort;
334	switch (port)
335	{
336	case VPCI_HOST_FEATURES:
337	/* Tell the guest what features we support. */
338	*pu32 = vpciGetHostFeatures(pState, pfnGetHostFeatures)
339	\| VPCI_F_BAD_FEATURE;
340	break;
341
342	case VPCI_GUEST_FEATURES:
343	*pu32 = pState->uGuestFeatures;
344	break;
345
346	case VPCI_QUEUE_PFN:
347	*pu32 = pState->Queues[pState->uQueueSelector].uPageNumber;
348	break;
349
350	case VPCI_QUEUE_NUM:
351	Assert(cb == 2);
352	(uint16_t)pu32 = pState->Queues[pState->uQueueSelector].VRing.uSize;
353	break;
354
355	case VPCI_QUEUE_SEL:
356	Assert(cb == 2);
357	(uint16_t)pu32 = pState->uQueueSelector;
358	break;
359
360	case VPCI_STATUS:
361	Assert(cb == 1);
362	(uint8_t)pu32 = pState->uStatus;
363	break;
364
365	case VPCI_ISR:
366	Assert(cb == 1);
367	(uint8_t)pu32 = pState->uISR;
368	pState->uISR = 0; /* read clears all interrupts */
369	vpciLowerInterrupt(pState);
370	break;
371
372	default:
373	if (port >= VPCI_CONFIG)
374	{
375	rc = pfnGetConfig(pState, port - VPCI_CONFIG, cb, pu32);
376	}
377	else
378	{
379	*pu32 = 0xFFFFFFFF;
380	rc = PDMDeviceDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortIn: "
381	"no valid port at offset port=%RTiop "
382	"cb=%08x\n", szInst, port, cb);
383	}
384	break;
385	}
386	Log3(("%s vpciIOPortIn: At %RTiop in %0*x\n",
387	szInst, port, cb2, pu32));
388	STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIORead), a);
389	//vpciCsLeave(pState);
390	return rc;
391	}
392
393
394	/**
395	* Port I/O Handler for OUT operations.
396	*
397	* @returns VBox status code.
398	*
399	* @param pDevIns The device instance.
400	* @param pvUser User argument.
401	* @param Port Port number used for the IN operation.
402	* @param u32 The value to output.
403	* @param cb The value size in bytes.
404	* @thread EMT
405	*/
406	int vpciIOPortOut(PPDMDEVINS pDevIns,
407	void *pvUser,
408	RTIOPORT port,
409	uint32_t u32,
410	unsigned cb,
411	PFNGETHOSTMINIMALFEATURES pfnGetHostMinimalFeatures,
412	PFNGETHOSTFEATURES pfnGetHostFeatures,
413	PFNSETHOSTFEATURES pfnSetHostFeatures,
414	PFNRESET pfnReset,
415	PFNREADY pfnReady,
416	PFNSETCONFIG pfnSetConfig)
417
418	{
419	VPCISTATE pState = PDMINS_2_DATA(pDevIns, VPCISTATE );
420	int rc = VINF_SUCCESS;
421	const char *szInst = INSTANCE(pState);
422	bool fHasBecomeReady;
423	STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIOWrite), a);
424
425	port -= pState->addrIOPort;
426	Log3(("%s virtioIOPortOut: At %RTiop out %0x\n", szInst, port, cb2, u32));
427
428	switch (port)
429	{
430	case VPCI_GUEST_FEATURES:
431	/* Check if the guest negotiates properly, fall back to basics if it does not. */
432	if (VPCI_F_BAD_FEATURE & u32)
433	{
434	Log(("%s WARNING! Guest failed to negotiate properly (guest=%x)\n",
435	INSTANCE(pState), u32));
436	pState->uGuestFeatures = pfnGetHostMinimalFeatures(pState);
437	}
438	/* The guest may potentially desire features we don't support! */
439	else if (~vpciGetHostFeatures(pState, pfnGetHostFeatures) & u32)
440	{
441	Log(("%s Guest asked for features host does not support! (host=%x guest=%x)\n",
442	INSTANCE(pState),
443	vpciGetHostFeatures(pState, pfnGetHostFeatures), u32));
444	pState->uGuestFeatures =
445	vpciGetHostFeatures(pState, pfnGetHostFeatures);
446	}
447	else
448	pState->uGuestFeatures = u32;
449	pfnSetHostFeatures(pState, pState->uGuestFeatures);
450	break;
451
452	case VPCI_QUEUE_PFN:
453	/*
454	* The guest is responsible for allocating the pages for queues,
455	* here it provides us with the page number of descriptor table.
456	* Note that we provide the size of the queue to the guest via
457	* VIRTIO_PCI_QUEUE_NUM.
458	*/
459	pState->Queues[pState->uQueueSelector].uPageNumber = u32;
460	if (u32)
461	vqueueInit(&pState->Queues[pState->uQueueSelector], u32);
462	else
463	pfnReset(pState);
464	break;
465
466	case VPCI_QUEUE_SEL:
467	Assert(cb == 2);
468	u32 &= 0xFFFF;
469	if (u32 < pState->nQueues)
470	pState->uQueueSelector = u32;
471	else
472	Log3(("%s vpciIOPortOut: Invalid queue selector %08x\n", szInst, u32));
473	break;
474
475	case VPCI_QUEUE_NOTIFY:
476	#ifdef IN_RING3
477	Assert(cb == 2);
478	u32 &= 0xFFFF;
479	if (u32 < pState->nQueues)
480	if (pState->Queues[u32].VRing.addrDescriptors)
481	{
482	// rc = vpciCsEnter(pState, VERR_SEM_BUSY);
483	// if (RT_LIKELY(rc == VINF_SUCCESS))
484	// {
485	pState->Queues[u32].pfnCallback(pState, &pState->Queues[u32]);
486	// vpciCsLeave(pState);
487	// }
488	}
489	else
490	Log(("%s The queue (#%d) being notified has not been initialized.\n",
491	INSTANCE(pState), u32));
492	else
493	Log(("%s Invalid queue number (%d)\n", INSTANCE(pState), u32));
494	#else
495	rc = VINF_IOM_HC_IOPORT_WRITE;
496	#endif
497	break;
498
499	case VPCI_STATUS:
500	Assert(cb == 1);
501	u32 &= 0xFF;
502	fHasBecomeReady = !(pState->uStatus & VPCI_STATUS_DRV_OK) && (u32 & VPCI_STATUS_DRV_OK);
503	pState->uStatus = u32;
504	/* Writing 0 to the status port triggers device reset. */
505	if (u32 == 0)
506	pfnReset(pState);
507	else if (fHasBecomeReady)
508	pfnReady(pState);
509	break;
510
511	default:
512	if (port >= VPCI_CONFIG)
513	rc = pfnSetConfig(pState, port - VPCI_CONFIG, cb, &u32);
514	else
515	rc = PDMDeviceDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortOut: no valid port at offset port=%RTiop cb=%08x\n", szInst, port, cb);
516	break;
517	}
518
519	STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIOWrite), a);
520	return rc;
521	}
522
523	#ifdef IN_RING3
524
525	/**
526	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
527	*/
528	void vpciQueryInterface(struct PDMIBASE pInterface, const char *pszIID)
529	{
530	VPCISTATE *pThis = IFACE_TO_STATE(pInterface, IBase);
531	Assert(&pThis->IBase == pInterface);
532
533	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
534	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
535	return NULL;
536	}
537
538	/**
539	* Gets the pointer to the status LED of a unit.
540	*
541	* @returns VBox status code.
542	* @param pInterface Pointer to the interface structure.
543	* @param iLUN The unit which status LED we desire.
544	* @param ppLed Where to store the LED pointer.
545	* @thread EMT
546	*/
547	static DECLCALLBACK(int) vpciQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
548	{
549	VPCISTATE *pState = IFACE_TO_STATE(pInterface, ILeds);
550	int rc = VERR_PDM_LUN_NOT_FOUND;
551
552	if (iLUN == 0)
553	{
554	*ppLed = &pState->led;
555	rc = VINF_SUCCESS;
556	}
557	return rc;
558	}
559
560	/**
561	* Turns on/off the write status LED.
562	*
563	* @returns VBox status code.
564	* @param pState Pointer to the device state structure.
565	* @param fOn New LED state.
566	*/
567	void vpciSetWriteLed(PVPCISTATE pState, bool fOn)
568	{
569	LogFlow(("%s vpciSetWriteLed: %s\n", INSTANCE(pState), fOn?"on":"off"));
570	if (fOn)
571	pState->led.Asserted.s.fWriting = pState->led.Actual.s.fWriting = 1;
572	else
573	pState->led.Actual.s.fWriting = fOn;
574	}
575
576	/**
577	* Turns on/off the read status LED.
578	*
579	* @returns VBox status code.
580	* @param pState Pointer to the device state structure.
581	* @param fOn New LED state.
582	*/
583	void vpciSetReadLed(PVPCISTATE pState, bool fOn)
584	{
585	LogFlow(("%s vpciSetReadLed: %s\n", INSTANCE(pState), fOn?"on":"off"));
586	if (fOn)
587	pState->led.Asserted.s.fReading = pState->led.Actual.s.fReading = 1;
588	else
589	pState->led.Actual.s.fReading = fOn;
590	}
591
592	/**
593	* Sets 8-bit register in PCI configuration space.
594	* @param refPciDev The PCI device.
595	* @param uOffset The register offset.
596	* @param u16Value The value to store in the register.
597	* @thread EMT
598	*/
599	DECLINLINE(void) vpciCfgSetU8(PCIDEVICE& refPciDev, uint32_t uOffset, uint8_t u8Value)
600	{
601	Assert(uOffset < sizeof(refPciDev.config));
602	refPciDev.config[uOffset] = u8Value;
603	}
604
605	/**
606	* Sets 16-bit register in PCI configuration space.
607	* @param refPciDev The PCI device.
608	* @param uOffset The register offset.
609	* @param u16Value The value to store in the register.
610	* @thread EMT
611	*/
612	DECLINLINE(void) vpciCfgSetU16(PCIDEVICE& refPciDev, uint32_t uOffset, uint16_t u16Value)
613	{
614	Assert(uOffset+sizeof(u16Value) <= sizeof(refPciDev.config));
615	(uint16_t)&refPciDev.config[uOffset] = u16Value;
616	}
617
618	/**
619	* Sets 32-bit register in PCI configuration space.
620	* @param refPciDev The PCI device.
621	* @param uOffset The register offset.
622	* @param u32Value The value to store in the register.
623	* @thread EMT
624	*/
625	DECLINLINE(void) vpciCfgSetU32(PCIDEVICE& refPciDev, uint32_t uOffset, uint32_t u32Value)
626	{
627	Assert(uOffset+sizeof(u32Value) <= sizeof(refPciDev.config));
628	(uint32_t)&refPciDev.config[uOffset] = u32Value;
629	}
630
631
632	#ifdef DEBUG
633	static void vpciDumpState(PVPCISTATE pState, const char *pcszCaller)
634	{
635	Log2(("vpciDumpState: (called from %s)\n"
636	" uGuestFeatures = 0x%08x\n"
637	" uQueueSelector = 0x%04x\n"
638	" uStatus = 0x%02x\n"
639	" uISR = 0x%02x\n",
640	pcszCaller,
641	pState->uGuestFeatures,
642	pState->uQueueSelector,
643	pState->uStatus,
644	pState->uISR));
645
646	for (unsigned i = 0; i < pState->nQueues; i++)
647	Log2((" %s queue:\n"
648	" VRing.uSize = %u\n"
649	" VRing.addrDescriptors = %p\n"
650	" VRing.addrAvail = %p\n"
651	" VRing.addrUsed = %p\n"
652	" uNextAvailIndex = %u\n"
653	" uNextUsedIndex = %u\n"
654	" uPageNumber = %x\n",
655	pState->Queues[i].pcszName,
656	pState->Queues[i].VRing.uSize,
657	pState->Queues[i].VRing.addrDescriptors,
658	pState->Queues[i].VRing.addrAvail,
659	pState->Queues[i].VRing.addrUsed,
660	pState->Queues[i].uNextAvailIndex,
661	pState->Queues[i].uNextUsedIndex,
662	pState->Queues[i].uPageNumber));
663	}
664	#else
665	# define vpciDumpState(x, s) do {} while (0)
666	#endif
667
668	/**
669	* Saves the state of device.
670	*
671	* @returns VBox status code.
672	* @param pDevIns The device instance.
673	* @param pSSM The handle to the saved state.
674	*/
675	int vpciSaveExec(PVPCISTATE pState, PSSMHANDLE pSSM)
676	{
677	int rc;
678
679	vpciDumpState(pState, "vpciSaveExec");
680
681	rc = SSMR3PutU32(pSSM, pState->uGuestFeatures);
682	AssertRCReturn(rc, rc);
683	rc = SSMR3PutU16(pSSM, pState->uQueueSelector);
684	AssertRCReturn(rc, rc);
685	rc = SSMR3PutU8( pSSM, pState->uStatus);
686	AssertRCReturn(rc, rc);
687	rc = SSMR3PutU8( pSSM, pState->uISR);
688	AssertRCReturn(rc, rc);
689
690	/* Save queue states */
691	rc = SSMR3PutU32(pSSM, pState->nQueues);
692	AssertRCReturn(rc, rc);
693	for (unsigned i = 0; i < pState->nQueues; i++)
694	{
695	rc = SSMR3PutU16(pSSM, pState->Queues[i].VRing.uSize);
696	AssertRCReturn(rc, rc);
697	rc = SSMR3PutU32(pSSM, pState->Queues[i].uPageNumber);
698	AssertRCReturn(rc, rc);
699	rc = SSMR3PutU16(pSSM, pState->Queues[i].uNextAvailIndex);
700	AssertRCReturn(rc, rc);
701	rc = SSMR3PutU16(pSSM, pState->Queues[i].uNextUsedIndex);
702	AssertRCReturn(rc, rc);
703	}
704
705	return VINF_SUCCESS;
706	}
707
708	/**
709	* Loads a saved device state.
710	*
711	* @returns VBox status code.
712	* @param pDevIns The device instance.
713	* @param pSSM The handle to the saved state.
714	* @param uVersion The data unit version number.
715	* @param uPass The data pass.
716	*/
717	int vpciLoadExec(PVPCISTATE pState, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass, uint32_t nQueues)
718	{
719	int rc;
720
721	if (uPass == SSM_PASS_FINAL)
722	{
723	/* Restore state data */
724	rc = SSMR3GetU32(pSSM, &pState->uGuestFeatures);
725	AssertRCReturn(rc, rc);
726	rc = SSMR3GetU16(pSSM, &pState->uQueueSelector);
727	AssertRCReturn(rc, rc);
728	rc = SSMR3GetU8( pSSM, &pState->uStatus);
729	AssertRCReturn(rc, rc);
730	rc = SSMR3GetU8( pSSM, &pState->uISR);
731	AssertRCReturn(rc, rc);
732
733	/* Restore queues */
734	if (uVersion > VIRTIO_SAVEDSTATE_VERSION_3_1_BETA1)
735	{
736	rc = SSMR3GetU32(pSSM, &pState->nQueues);
737	AssertRCReturn(rc, rc);
738	}
739	else
740	pState->nQueues = nQueues;
741	for (unsigned i = 0; i < pState->nQueues; i++)
742	{
743	rc = SSMR3GetU16(pSSM, &pState->Queues[i].VRing.uSize);
744	AssertRCReturn(rc, rc);
745	rc = SSMR3GetU32(pSSM, &pState->Queues[i].uPageNumber);
746	AssertRCReturn(rc, rc);
747
748	if (pState->Queues[i].uPageNumber)
749	vqueueInit(&pState->Queues[i], pState->Queues[i].uPageNumber);
750
751	rc = SSMR3GetU16(pSSM, &pState->Queues[i].uNextAvailIndex);
752	AssertRCReturn(rc, rc);
753	rc = SSMR3GetU16(pSSM, &pState->Queues[i].uNextUsedIndex);
754	AssertRCReturn(rc, rc);
755	}
756	}
757
758	vpciDumpState(pState, "vpciLoadExec");
759
760	return VINF_SUCCESS;
761	}
762
763	/**
764	* Set PCI configuration space registers.
765	*
766	* @param pci Reference to PCI device structure.
767	* @param uSubsystemId PCI Subsystem Id
768	* @param uClass Class of PCI device (network, etc)
769	* @thread EMT
770	*/
771	static DECLCALLBACK(void) vpciConfigure(PCIDEVICE& pci,
772	uint16_t uSubsystemId,
773	uint16_t uClass)
774	{
775	/* Configure PCI Device, assume 32-bit mode ******************************/
776	PCIDevSetVendorId(&pci, DEVICE_PCI_VENDOR_ID);
777	PCIDevSetDeviceId(&pci, DEVICE_PCI_DEVICE_ID);
778	vpciCfgSetU16(pci, VBOX_PCI_SUBSYSTEM_VENDOR_ID, DEVICE_PCI_SUBSYSTEM_VENDOR_ID);
779	vpciCfgSetU16(pci, VBOX_PCI_SUBSYSTEM_ID, uSubsystemId);
780
781	/* ABI version, must be equal 0 as of 2.6.30 kernel. */
782	vpciCfgSetU8( pci, VBOX_PCI_REVISION_ID, 0x00);
783	/* Ethernet adapter */
784	vpciCfgSetU8( pci, VBOX_PCI_CLASS_PROG, 0x00);
785	vpciCfgSetU16(pci, VBOX_PCI_CLASS_DEVICE, uClass);
786	/* Interrupt Pin: INTA# */
787	vpciCfgSetU8( pci, VBOX_PCI_INTERRUPT_PIN, 0x01);
788	}
789
790	/* WARNING! This function must never be used in multithreaded context! */
791	static const char vpciCounter(const char pszDevFmt,
792	const char *pszCounter)
793	{
794	static char g_szCounterName[80];
795
796	RTStrPrintf(g_szCounterName, sizeof(g_szCounterName),
797	"/Devices/%s/%s", pszDevFmt, pszCounter);
798
799	return g_szCounterName;
800	}
801
802	// TODO: header
803	DECLCALLBACK(int) vpciConstruct(PPDMDEVINS pDevIns, VPCISTATE *pState,
804	int iInstance, const char *pcszNameFmt,
805	uint16_t uSubsystemId, uint16_t uClass,
806	uint32_t nQueues)
807	{
808	int rc = VINF_SUCCESS;
809	/* Init handles and log related stuff. */
810	RTStrPrintf(pState->szInstance, sizeof(pState->szInstance),
811	pcszNameFmt, iInstance);
812
813	pState->pDevInsR3 = pDevIns;
814	pState->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
815	pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
816	pState->led.u32Magic = PDMLED_MAGIC;
817
818	pState->ILeds.pfnQueryStatusLed = vpciQueryStatusLed;
819
820	/* Initialize critical section. */
821	rc = PDMDevHlpCritSectInit(pDevIns, &pState->cs, RT_SRC_POS, "%s", pState->szInstance);
822	if (RT_FAILURE(rc))
823	return rc;
824
825	/* Set PCI config registers */
826	vpciConfigure(pState->pciDevice, uSubsystemId, uClass);
827	/* Register PCI device */
828	rc = PDMDevHlpPCIRegister(pDevIns, &pState->pciDevice);
829	if (RT_FAILURE(rc))
830	return rc;
831
832	/* Status driver */
833	PPDMIBASE pBase;
834	rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pState->IBase, &pBase, "Status Port");
835	if (RT_FAILURE(rc))
836	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the status LUN"));
837	pState->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
838
839	pState->nQueues = nQueues;
840
841	#if defined(VBOX_WITH_STATISTICS)
842	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in GC", vpciCounter(pcszNameFmt, "IO/ReadGC"), iInstance);
843	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in HC", vpciCounter(pcszNameFmt, "IO/ReadHC"), iInstance);
844	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in GC", vpciCounter(pcszNameFmt, "IO/WriteGC"), iInstance);
845	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in HC", vpciCounter(pcszNameFmt, "IO/WriteHC"), iInstance);
846	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsRaised, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of raised interrupts", vpciCounter(pcszNameFmt, "Interrupts/Raised"), iInstance);
847	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsSkipped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of skipped interrupts", vpciCounter(pcszNameFmt, "Interrupts/Skipped"), iInstance);
848	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatCsGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling CS wait in GC", vpciCounter(pcszNameFmt, "Cs/CsGC"), iInstance);
849	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatCsHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling CS wait in HC", vpciCounter(pcszNameFmt, "Cs/CsHC"), iInstance);
850	#endif /* VBOX_WITH_STATISTICS */
851
852	return rc;
853	}
854
855	/**
856	* Destruct PCI-related part of device.
857	*
858	* We need to free non-VM resources only.
859	*
860	* @returns VBox status.
861	* @param pState The device state structure.
862	*/
863	int vpciDestruct(VPCISTATE* pState)
864	{
865	Log(("%s Destroying PCI instance\n", INSTANCE(pState)));
866
867	if (PDMCritSectIsInitialized(&pState->cs))
868	PDMR3CritSectDelete(&pState->cs);
869
870	return VINF_SUCCESS;
871	}
872
873	/**
874	* Device relocation callback.
875	*
876	* When this callback is called the device instance data, and if the
877	* device have a GC component, is being relocated, or/and the selectors
878	* have been changed. The device must use the chance to perform the
879	* necessary pointer relocations and data updates.
880	*
881	* Before the GC code is executed the first time, this function will be
882	* called with a 0 delta so GC pointer calculations can be one in one place.
883	*
884	* @param pDevIns Pointer to the device instance.
885	* @param offDelta The relocation delta relative to the old location.
886	*
887	* @remark A relocation CANNOT fail.
888	*/
889	void vpciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
890	{
891	VPCISTATE* pState = PDMINS_2_DATA(pDevIns, VPCISTATE*);
892	pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
893	// TBD
894	}
895
896	PVQUEUE vpciAddQueue(VPCISTATE* pState, unsigned uSize,
897	void (pfnCallback)(void pvState, PVQUEUE pQueue),
898	const char *pcszName)
899	{
900	PVQUEUE pQueue = NULL;
901	/* Find an empty queue slot */
902	for (unsigned i = 0; i < pState->nQueues; i++)
903	{
904	if (pState->Queues[i].VRing.uSize == 0)
905	{
906	pQueue = &pState->Queues[i];
907	break;
908	}
909	}
910
911	if (!pQueue)
912	{
913	Log(("%s Too many queues being added, no empty slots available!\n", INSTANCE(pState)));
914	}
915	else
916	{
917	pQueue->VRing.uSize = uSize;
918	pQueue->VRing.addrDescriptors = 0;
919	pQueue->uPageNumber = 0;
920	pQueue->pfnCallback = pfnCallback;
921	pQueue->pcszName = pcszName;
922	}
923
924	return pQueue;
925	}
926
927	#endif /* IN_RING3 */
928
929	#endif /* VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/VirtIO/Virtio.cpp@ 25985

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