Virtio.cpp@ 28800

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1	/* $Id: Virtio.cpp 28800 2010-04-27 08:22:32Z vboxsync $ */
2	/** @file
3	* Virtio - Virtio Common Functions (VRing, VQueue, Virtio PCI)
4	*/
5
6	/*
7	* Copyright (C) 2009-2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	#define LOG_GROUP LOG_GROUP_DEV_VIRTIO
20
21	#include <iprt/param.h>
22	#include <iprt/uuid.h>
23	#include <VBox/pdmdev.h>
24	#include "Virtio.h"
25
26	#define INSTANCE(pState) pState->szInstance
27	#define IFACE_TO_STATE(pIface, ifaceName) ((VPCISTATE )((char)pIface - RT_OFFSETOF(VPCISTATE, ifaceName)))
28
29	#ifdef DEBUG
30	#define QUEUENAME(s, q) (q->pcszName)
31	#endif /* DEBUG */
32
33
34
35	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
36
37	//RT_C_DECLS_BEGIN
38	//RT_C_DECLS_END
39
40
41	static void vqueueReset(PVQUEUE pQueue)
42	{
43	pQueue->VRing.addrDescriptors = 0;
44	pQueue->VRing.addrAvail = 0;
45	pQueue->VRing.addrUsed = 0;
46	pQueue->uNextAvailIndex = 0;
47	pQueue->uNextUsedIndex = 0;
48	pQueue->uPageNumber = 0;
49	}
50
51	static void vqueueInit(PVQUEUE pQueue, uint32_t uPageNumber)
52	{
53	pQueue->VRing.addrDescriptors = uPageNumber << PAGE_SHIFT;
54	pQueue->VRing.addrAvail = pQueue->VRing.addrDescriptors
55	+ sizeof(VRINGDESC) * pQueue->VRing.uSize;
56	pQueue->VRing.addrUsed = RT_ALIGN(
57	pQueue->VRing.addrAvail + RT_OFFSETOF(VRINGAVAIL, auRing[pQueue->VRing.uSize]),
58	PAGE_SIZE); /* The used ring must start from the next page. */
59	pQueue->uNextAvailIndex = 0;
60	pQueue->uNextUsedIndex = 0;
61	}
62
63	// void vqueueElemFree(PVQUEUEELEM pElem)
64	// {
65	// }
66
67	void vringReadDesc(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex, PVRINGDESC pDesc)
68	{
69	//Log(("%s vringReadDesc: ring=%p idx=%u\n", INSTANCE(pState), pVRing, uIndex));
70	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
71	pVRing->addrDescriptors + sizeof(VRINGDESC) * (uIndex % pVRing->uSize),
72	pDesc, sizeof(VRINGDESC));
73	}
74
75	uint16_t vringReadAvail(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex)
76	{
77	uint16_t tmp;
78
79	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
80	pVRing->addrAvail + RT_OFFSETOF(VRINGAVAIL, auRing[uIndex % pVRing->uSize]),
81	&tmp, sizeof(tmp));
82	return tmp;
83	}
84
85	uint16_t vringReadAvailFlags(PVPCISTATE pState, PVRING pVRing)
86	{
87	uint16_t tmp;
88
89	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
90	pVRing->addrAvail + RT_OFFSETOF(VRINGAVAIL, uFlags),
91	&tmp, sizeof(tmp));
92	return tmp;
93	}
94
95	void vringSetNotification(PVPCISTATE pState, PVRING pVRing, bool fEnabled)
96	{
97	uint16_t tmp;
98
99	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
100	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uFlags),
101	&tmp, sizeof(tmp));
102
103	if (fEnabled)
104	tmp &= ~ VRINGUSED_F_NO_NOTIFY;
105	else
106	tmp \|= VRINGUSED_F_NO_NOTIFY;
107
108	PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns),
109	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uFlags),
110	&tmp, sizeof(tmp));
111	}
112
113	bool vqueueGet(PVPCISTATE pState, PVQUEUE pQueue, PVQUEUEELEM pElem)
114	{
115	if (vqueueIsEmpty(pState, pQueue))
116	return false;
117
118	pElem->nIn = pElem->nOut = 0;
119
120	Log2(("%s vqueueGet: %s avail_idx=%u\n", INSTANCE(pState),
121	QUEUENAME(pState, pQueue), pQueue->uNextAvailIndex));
122
123	VRINGDESC desc;
124	uint16_t idx = vringReadAvail(pState, &pQueue->VRing, pQueue->uNextAvailIndex++);
125	pElem->uIndex = idx;
126	do
127	{
128	VQUEUESEG *pSeg;
129
130	vringReadDesc(pState, &pQueue->VRing, idx, &desc);
131	if (desc.u16Flags & VRINGDESC_F_WRITE)
132	{
133	Log2(("%s vqueueGet: %s IN seg=%u desc_idx=%u addr=%p cb=%u\n", INSTANCE(pState),
134	QUEUENAME(pState, pQueue), pElem->nIn, idx, desc.u64Addr, desc.uLen));
135	pSeg = &pElem->aSegsIn[pElem->nIn++];
136	}
137	else
138	{
139	Log2(("%s vqueueGet: %s OUT seg=%u desc_idx=%u addr=%p cb=%u\n", INSTANCE(pState),
140	QUEUENAME(pState, pQueue), pElem->nOut, idx, desc.u64Addr, desc.uLen));
141	pSeg = &pElem->aSegsOut[pElem->nOut++];
142	}
143
144	pSeg->addr = desc.u64Addr;
145	pSeg->cb = desc.uLen;
146	pSeg->pv = NULL;
147
148	idx = desc.u16Next;
149	} while (desc.u16Flags & VRINGDESC_F_NEXT);
150
151	Log2(("%s vqueueGet: %s head_desc_idx=%u nIn=%u nOut=%u\n", INSTANCE(pState),
152	QUEUENAME(pState, pQueue), pElem->uIndex, pElem->nIn, pElem->nOut));
153	return true;
154	}
155
156	uint16_t vringReadUsedIndex(PVPCISTATE pState, PVRING pVRing)
157	{
158	uint16_t tmp;
159	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
160	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uIndex),
161	&tmp, sizeof(tmp));
162	return tmp;
163	}
164
165	void vringWriteUsedIndex(PVPCISTATE pState, PVRING pVRing, uint16_t u16Value)
166	{
167	PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns),
168	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uIndex),
169	&u16Value, sizeof(u16Value));
170	}
171
172	void vringWriteUsedElem(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex, uint32_t uId, uint32_t uLen)
173	{
174	VRINGUSEDELEM elem;
175
176	elem.uId = uId;
177	elem.uLen = uLen;
178	PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns),
179	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, aRing[uIndex % pVRing->uSize]),
180	&elem, sizeof(elem));
181	}
182
183	void vqueuePut(PVPCISTATE pState, PVQUEUE pQueue, PVQUEUEELEM pElem, uint32_t uLen)
184	{
185	unsigned int i, uOffset;
186
187	Log2(("%s vqueuePut: %s desc_idx=%u acb=%u\n", INSTANCE(pState),
188	QUEUENAME(pState, pQueue), pElem->uIndex, uLen));
189	for (i = uOffset = 0; i < pElem->nIn && uOffset < uLen; i++)
190	{
191	uint32_t cbSegLen = RT_MIN(uLen - uOffset, pElem->aSegsIn[i].cb);
192	if (pElem->aSegsIn[i].pv)
193	{
194	Log2(("%s vqueuePut: %s used_idx=%u seg=%u addr=%p pv=%p cb=%u acb=%u\n", INSTANCE(pState),
195	QUEUENAME(pState, pQueue), pQueue->uNextUsedIndex, i, pElem->aSegsIn[i].addr, pElem->aSegsIn[i].pv, pElem->aSegsIn[i].cb, cbSegLen));
196	PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns), pElem->aSegsIn[i].addr,
197	pElem->aSegsIn[i].pv, cbSegLen);
198	}
199	uOffset += cbSegLen;
200	}
201
202	Log2(("%s vqueuePut: %s used_idx=%u guest_used_idx=%u id=%u len=%u\n", INSTANCE(pState),
203	QUEUENAME(pState, pQueue), pQueue->uNextUsedIndex, vringReadUsedIndex(pState, &pQueue->VRing), pElem->uIndex, uLen));
204	vringWriteUsedElem(pState, &pQueue->VRing, pQueue->uNextUsedIndex++, pElem->uIndex, uLen);
205	}
206
207	void vqueueNotify(PVPCISTATE pState, PVQUEUE pQueue)
208	{
209	LogFlow(("%s vqueueNotify: %s availFlags=%x guestFeatures=%x vqueue is %sempty\n",
210	INSTANCE(pState), QUEUENAME(pState, pQueue),
211	vringReadAvailFlags(pState, &pQueue->VRing),
212	pState->uGuestFeatures, vqueueIsEmpty(pState, pQueue)?"":"not "));
213	if (!(vringReadAvailFlags(pState, &pQueue->VRing) & VRINGAVAIL_F_NO_INTERRUPT)
214	\|\| ((pState->uGuestFeatures & VPCI_F_NOTIFY_ON_EMPTY) && vqueueIsEmpty(pState, pQueue)))
215	{
216	int rc = vpciRaiseInterrupt(pState, VERR_INTERNAL_ERROR, VPCI_ISR_QUEUE);
217	if (RT_FAILURE(rc))
218	Log(("%s vqueueNotify: Failed to raise an interrupt (%Rrc).\n", INSTANCE(pState), rc));
219	}
220	else
221	{
222	STAM_COUNTER_INC(&pState->StatIntsSkipped);
223	}
224
225	}
226
227	void vqueueSync(PVPCISTATE pState, PVQUEUE pQueue)
228	{
229	Log2(("%s vqueueSync: %s old_used_idx=%u new_used_idx=%u\n", INSTANCE(pState),
230	QUEUENAME(pState, pQueue), vringReadUsedIndex(pState, &pQueue->VRing), pQueue->uNextUsedIndex));
231	vringWriteUsedIndex(pState, &pQueue->VRing, pQueue->uNextUsedIndex);
232	vqueueNotify(pState, pQueue);
233	}
234
235	void vpciReset(PVPCISTATE pState)
236	{
237	pState->uGuestFeatures = 0;
238	pState->uQueueSelector = 0;
239	pState->uStatus = 0;
240	pState->uISR = 0;
241
242	for (unsigned i = 0; i < pState->nQueues; i++)
243	vqueueReset(&pState->Queues[i]);
244	}
245
246
247	/**
248	* Raise interrupt.
249	*
250	* @param pState The device state structure.
251	* @param rcBusy Status code to return when the critical section is busy.
252	* @param u8IntCause Interrupt cause bit mask to set in PCI ISR port.
253	*/
254	int vpciRaiseInterrupt(VPCISTATE *pState, int rcBusy, uint8_t u8IntCause)
255	{
256	// int rc = vpciCsEnter(pState, rcBusy);
257	// if (RT_UNLIKELY(rc != VINF_SUCCESS))
258	// return rc;
259
260	STAM_COUNTER_INC(&pState->StatIntsRaised);
261	LogFlow(("%s vpciRaiseInterrupt: u8IntCause=%x\n",
262	INSTANCE(pState), u8IntCause));
263
264	pState->uISR \|= u8IntCause;
265	PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 1);
266	// vpciCsLeave(pState);
267	return VINF_SUCCESS;
268	}
269
270	/**
271	* Lower interrupt.
272	*
273	* @param pState The device state structure.
274	*/
275	PDMBOTHCBDECL(void) vpciLowerInterrupt(VPCISTATE *pState)
276	{
277	LogFlow(("%s vpciLowerInterrupt\n", INSTANCE(pState)));
278	PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 0);
279	}
280
281	DECLINLINE(uint32_t) vpciGetHostFeatures(PVPCISTATE pState,
282	PFNGETHOSTFEATURES pfnGetHostFeatures)
283	{
284	return pfnGetHostFeatures(pState)
285	\| VPCI_F_NOTIFY_ON_EMPTY;
286	}
287
288	/**
289	* Port I/O Handler for IN operations.
290	*
291	* @returns VBox status code.
292	*
293	* @param pDevIns The device instance.
294	* @param pvUser Pointer to the device state structure.
295	* @param port Port number used for the IN operation.
296	* @param pu32 Where to store the result.
297	* @param cb Number of bytes read.
298	* @thread EMT
299	*/
300	int vpciIOPortIn(PPDMDEVINS pDevIns,
301	void *pvUser,
302	RTIOPORT port,
303	uint32_t *pu32,
304	unsigned cb,
305	PFNGETHOSTFEATURES pfnGetHostFeatures,
306	PFNGETCONFIG pfnGetConfig)
307	{
308	VPCISTATE pState = PDMINS_2_DATA(pDevIns, VPCISTATE );
309	int rc = VINF_SUCCESS;
310	const char *szInst = INSTANCE(pState);
311	STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIORead), a);
312
313	/*
314	* We probably do not need to enter critical section when reading registers
315	* as the most of them are either constant or being changed during
316	* initialization only, the exception being ISR which can be raced by all
317	* threads but I see no big harm in it. It also happens to be the most read
318	* register as it gets read in interrupt handler. By dropping cs protection
319	* here we gain the ability to deliver RX packets to the guest while TX is
320	* holding cs transmitting queued packets.
321	*
322	rc = vpciCsEnter(pState, VINF_IOM_HC_IOPORT_READ);
323	if (RT_UNLIKELY(rc != VINF_SUCCESS))
324	{
325	STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIORead), a);
326	return rc;
327	}*/
328
329	port -= pState->addrIOPort;
330	switch (port)
331	{
332	case VPCI_HOST_FEATURES:
333	/* Tell the guest what features we support. */
334	*pu32 = vpciGetHostFeatures(pState, pfnGetHostFeatures)
335	\| VPCI_F_BAD_FEATURE;
336	break;
337
338	case VPCI_GUEST_FEATURES:
339	*pu32 = pState->uGuestFeatures;
340	break;
341
342	case VPCI_QUEUE_PFN:
343	*pu32 = pState->Queues[pState->uQueueSelector].uPageNumber;
344	break;
345
346	case VPCI_QUEUE_NUM:
347	Assert(cb == 2);
348	(uint16_t)pu32 = pState->Queues[pState->uQueueSelector].VRing.uSize;
349	break;
350
351	case VPCI_QUEUE_SEL:
352	Assert(cb == 2);
353	(uint16_t)pu32 = pState->uQueueSelector;
354	break;
355
356	case VPCI_STATUS:
357	Assert(cb == 1);
358	(uint8_t)pu32 = pState->uStatus;
359	break;
360
361	case VPCI_ISR:
362	Assert(cb == 1);
363	(uint8_t)pu32 = pState->uISR;
364	pState->uISR = 0; /* read clears all interrupts */
365	vpciLowerInterrupt(pState);
366	break;
367
368	default:
369	if (port >= VPCI_CONFIG)
370	{
371	rc = pfnGetConfig(pState, port - VPCI_CONFIG, cb, pu32);
372	}
373	else
374	{
375	*pu32 = 0xFFFFFFFF;
376	rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortIn: "
377	"no valid port at offset port=%RTiop "
378	"cb=%08x\n", szInst, port, cb);
379	}
380	break;
381	}
382	Log3(("%s vpciIOPortIn: At %RTiop in %0*x\n",
383	szInst, port, cb2, pu32));
384	STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIORead), a);
385	//vpciCsLeave(pState);
386	return rc;
387	}
388
389
390	/**
391	* Port I/O Handler for OUT operations.
392	*
393	* @returns VBox status code.
394	*
395	* @param pDevIns The device instance.
396	* @param pvUser User argument.
397	* @param Port Port number used for the IN operation.
398	* @param u32 The value to output.
399	* @param cb The value size in bytes.
400	* @thread EMT
401	*/
402	int vpciIOPortOut(PPDMDEVINS pDevIns,
403	void *pvUser,
404	RTIOPORT port,
405	uint32_t u32,
406	unsigned cb,
407	PFNGETHOSTMINIMALFEATURES pfnGetHostMinimalFeatures,
408	PFNGETHOSTFEATURES pfnGetHostFeatures,
409	PFNSETHOSTFEATURES pfnSetHostFeatures,
410	PFNRESET pfnReset,
411	PFNREADY pfnReady,
412	PFNSETCONFIG pfnSetConfig)
413
414	{
415	VPCISTATE pState = PDMINS_2_DATA(pDevIns, VPCISTATE );
416	int rc = VINF_SUCCESS;
417	const char *szInst = INSTANCE(pState);
418	bool fHasBecomeReady;
419	STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIOWrite), a);
420
421	port -= pState->addrIOPort;
422	Log3(("%s virtioIOPortOut: At %RTiop out %0x\n", szInst, port, cb2, u32));
423
424	switch (port)
425	{
426	case VPCI_GUEST_FEATURES:
427	/* Check if the guest negotiates properly, fall back to basics if it does not. */
428	if (VPCI_F_BAD_FEATURE & u32)
429	{
430	Log(("%s WARNING! Guest failed to negotiate properly (guest=%x)\n",
431	INSTANCE(pState), u32));
432	pState->uGuestFeatures = pfnGetHostMinimalFeatures(pState);
433	}
434	/* The guest may potentially desire features we don't support! */
435	else if (~vpciGetHostFeatures(pState, pfnGetHostFeatures) & u32)
436	{
437	Log(("%s Guest asked for features host does not support! (host=%x guest=%x)\n",
438	INSTANCE(pState),
439	vpciGetHostFeatures(pState, pfnGetHostFeatures), u32));
440	pState->uGuestFeatures =
441	vpciGetHostFeatures(pState, pfnGetHostFeatures);
442	}
443	else
444	pState->uGuestFeatures = u32;
445	pfnSetHostFeatures(pState, pState->uGuestFeatures);
446	break;
447
448	case VPCI_QUEUE_PFN:
449	/*
450	* The guest is responsible for allocating the pages for queues,
451	* here it provides us with the page number of descriptor table.
452	* Note that we provide the size of the queue to the guest via
453	* VIRTIO_PCI_QUEUE_NUM.
454	*/
455	pState->Queues[pState->uQueueSelector].uPageNumber = u32;
456	if (u32)
457	vqueueInit(&pState->Queues[pState->uQueueSelector], u32);
458	else
459	rc = pfnReset(pState);
460	break;
461
462	case VPCI_QUEUE_SEL:
463	Assert(cb == 2);
464	u32 &= 0xFFFF;
465	if (u32 < pState->nQueues)
466	pState->uQueueSelector = u32;
467	else
468	Log3(("%s vpciIOPortOut: Invalid queue selector %08x\n", szInst, u32));
469	break;
470
471	case VPCI_QUEUE_NOTIFY:
472	#ifdef IN_RING3
473	Assert(cb == 2);
474	u32 &= 0xFFFF;
475	if (u32 < pState->nQueues)
476	if (pState->Queues[u32].VRing.addrDescriptors)
477	{
478	// rc = vpciCsEnter(pState, VERR_SEM_BUSY);
479	// if (RT_LIKELY(rc == VINF_SUCCESS))
480	// {
481	pState->Queues[u32].pfnCallback(pState, &pState->Queues[u32]);
482	// vpciCsLeave(pState);
483	// }
484	}
485	else
486	Log(("%s The queue (#%d) being notified has not been initialized.\n",
487	INSTANCE(pState), u32));
488	else
489	Log(("%s Invalid queue number (%d)\n", INSTANCE(pState), u32));
490	#else
491	rc = VINF_IOM_HC_IOPORT_WRITE;
492	#endif
493	break;
494
495	case VPCI_STATUS:
496	Assert(cb == 1);
497	u32 &= 0xFF;
498	fHasBecomeReady = !(pState->uStatus & VPCI_STATUS_DRV_OK) && (u32 & VPCI_STATUS_DRV_OK);
499	pState->uStatus = u32;
500	/* Writing 0 to the status port triggers device reset. */
501	if (u32 == 0)
502	rc = pfnReset(pState);
503	else if (fHasBecomeReady)
504	pfnReady(pState);
505	break;
506
507	default:
508	if (port >= VPCI_CONFIG)
509	rc = pfnSetConfig(pState, port - VPCI_CONFIG, cb, &u32);
510	else
511	rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortOut: no valid port at offset port=%RTiop cb=%08x\n", szInst, port, cb);
512	break;
513	}
514
515	STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIOWrite), a);
516	return rc;
517	}
518
519	#ifdef IN_RING3
520
521	/**
522	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
523	*/
524	void vpciQueryInterface(struct PDMIBASE pInterface, const char *pszIID)
525	{
526	VPCISTATE *pThis = IFACE_TO_STATE(pInterface, IBase);
527	Assert(&pThis->IBase == pInterface);
528
529	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
530	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
531	return NULL;
532	}
533
534	/**
535	* Gets the pointer to the status LED of a unit.
536	*
537	* @returns VBox status code.
538	* @param pInterface Pointer to the interface structure.
539	* @param iLUN The unit which status LED we desire.
540	* @param ppLed Where to store the LED pointer.
541	* @thread EMT
542	*/
543	static DECLCALLBACK(int) vpciQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
544	{
545	VPCISTATE *pState = IFACE_TO_STATE(pInterface, ILeds);
546	int rc = VERR_PDM_LUN_NOT_FOUND;
547
548	if (iLUN == 0)
549	{
550	*ppLed = &pState->led;
551	rc = VINF_SUCCESS;
552	}
553	return rc;
554	}
555
556	/**
557	* Turns on/off the write status LED.
558	*
559	* @returns VBox status code.
560	* @param pState Pointer to the device state structure.
561	* @param fOn New LED state.
562	*/
563	void vpciSetWriteLed(PVPCISTATE pState, bool fOn)
564	{
565	LogFlow(("%s vpciSetWriteLed: %s\n", INSTANCE(pState), fOn?"on":"off"));
566	if (fOn)
567	pState->led.Asserted.s.fWriting = pState->led.Actual.s.fWriting = 1;
568	else
569	pState->led.Actual.s.fWriting = fOn;
570	}
571
572	/**
573	* Turns on/off the read status LED.
574	*
575	* @returns VBox status code.
576	* @param pState Pointer to the device state structure.
577	* @param fOn New LED state.
578	*/
579	void vpciSetReadLed(PVPCISTATE pState, bool fOn)
580	{
581	LogFlow(("%s vpciSetReadLed: %s\n", INSTANCE(pState), fOn?"on":"off"));
582	if (fOn)
583	pState->led.Asserted.s.fReading = pState->led.Actual.s.fReading = 1;
584	else
585	pState->led.Actual.s.fReading = fOn;
586	}
587
588	/**
589	* Sets 8-bit register in PCI configuration space.
590	* @param refPciDev The PCI device.
591	* @param uOffset The register offset.
592	* @param u16Value The value to store in the register.
593	* @thread EMT
594	*/
595	DECLINLINE(void) vpciCfgSetU8(PCIDEVICE& refPciDev, uint32_t uOffset, uint8_t u8Value)
596	{
597	Assert(uOffset < sizeof(refPciDev.config));
598	refPciDev.config[uOffset] = u8Value;
599	}
600
601	/**
602	* Sets 16-bit register in PCI configuration space.
603	* @param refPciDev The PCI device.
604	* @param uOffset The register offset.
605	* @param u16Value The value to store in the register.
606	* @thread EMT
607	*/
608	DECLINLINE(void) vpciCfgSetU16(PCIDEVICE& refPciDev, uint32_t uOffset, uint16_t u16Value)
609	{
610	Assert(uOffset+sizeof(u16Value) <= sizeof(refPciDev.config));
611	(uint16_t)&refPciDev.config[uOffset] = u16Value;
612	}
613
614	/**
615	* Sets 32-bit register in PCI configuration space.
616	* @param refPciDev The PCI device.
617	* @param uOffset The register offset.
618	* @param u32Value The value to store in the register.
619	* @thread EMT
620	*/
621	DECLINLINE(void) vpciCfgSetU32(PCIDEVICE& refPciDev, uint32_t uOffset, uint32_t u32Value)
622	{
623	Assert(uOffset+sizeof(u32Value) <= sizeof(refPciDev.config));
624	(uint32_t)&refPciDev.config[uOffset] = u32Value;
625	}
626
627
628	#ifdef DEBUG
629	static void vpciDumpState(PVPCISTATE pState, const char *pcszCaller)
630	{
631	Log2(("vpciDumpState: (called from %s)\n"
632	" uGuestFeatures = 0x%08x\n"
633	" uQueueSelector = 0x%04x\n"
634	" uStatus = 0x%02x\n"
635	" uISR = 0x%02x\n",
636	pcszCaller,
637	pState->uGuestFeatures,
638	pState->uQueueSelector,
639	pState->uStatus,
640	pState->uISR));
641
642	for (unsigned i = 0; i < pState->nQueues; i++)
643	Log2((" %s queue:\n"
644	" VRing.uSize = %u\n"
645	" VRing.addrDescriptors = %p\n"
646	" VRing.addrAvail = %p\n"
647	" VRing.addrUsed = %p\n"
648	" uNextAvailIndex = %u\n"
649	" uNextUsedIndex = %u\n"
650	" uPageNumber = %x\n",
651	pState->Queues[i].pcszName,
652	pState->Queues[i].VRing.uSize,
653	pState->Queues[i].VRing.addrDescriptors,
654	pState->Queues[i].VRing.addrAvail,
655	pState->Queues[i].VRing.addrUsed,
656	pState->Queues[i].uNextAvailIndex,
657	pState->Queues[i].uNextUsedIndex,
658	pState->Queues[i].uPageNumber));
659	}
660	#else
661	# define vpciDumpState(x, s) do {} while (0)
662	#endif
663
664	/**
665	* Saves the state of device.
666	*
667	* @returns VBox status code.
668	* @param pDevIns The device instance.
669	* @param pSSM The handle to the saved state.
670	*/
671	int vpciSaveExec(PVPCISTATE pState, PSSMHANDLE pSSM)
672	{
673	int rc;
674
675	vpciDumpState(pState, "vpciSaveExec");
676
677	rc = SSMR3PutU32(pSSM, pState->uGuestFeatures);
678	AssertRCReturn(rc, rc);
679	rc = SSMR3PutU16(pSSM, pState->uQueueSelector);
680	AssertRCReturn(rc, rc);
681	rc = SSMR3PutU8( pSSM, pState->uStatus);
682	AssertRCReturn(rc, rc);
683	rc = SSMR3PutU8( pSSM, pState->uISR);
684	AssertRCReturn(rc, rc);
685
686	/* Save queue states */
687	rc = SSMR3PutU32(pSSM, pState->nQueues);
688	AssertRCReturn(rc, rc);
689	for (unsigned i = 0; i < pState->nQueues; i++)
690	{
691	rc = SSMR3PutU16(pSSM, pState->Queues[i].VRing.uSize);
692	AssertRCReturn(rc, rc);
693	rc = SSMR3PutU32(pSSM, pState->Queues[i].uPageNumber);
694	AssertRCReturn(rc, rc);
695	rc = SSMR3PutU16(pSSM, pState->Queues[i].uNextAvailIndex);
696	AssertRCReturn(rc, rc);
697	rc = SSMR3PutU16(pSSM, pState->Queues[i].uNextUsedIndex);
698	AssertRCReturn(rc, rc);
699	}
700
701	return VINF_SUCCESS;
702	}
703
704	/**
705	* Loads a saved device state.
706	*
707	* @returns VBox status code.
708	* @param pDevIns The device instance.
709	* @param pSSM The handle to the saved state.
710	* @param uVersion The data unit version number.
711	* @param uPass The data pass.
712	*/
713	int vpciLoadExec(PVPCISTATE pState, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass, uint32_t nQueues)
714	{
715	int rc;
716
717	if (uPass == SSM_PASS_FINAL)
718	{
719	/* Restore state data */
720	rc = SSMR3GetU32(pSSM, &pState->uGuestFeatures);
721	AssertRCReturn(rc, rc);
722	rc = SSMR3GetU16(pSSM, &pState->uQueueSelector);
723	AssertRCReturn(rc, rc);
724	rc = SSMR3GetU8( pSSM, &pState->uStatus);
725	AssertRCReturn(rc, rc);
726	rc = SSMR3GetU8( pSSM, &pState->uISR);
727	AssertRCReturn(rc, rc);
728
729	/* Restore queues */
730	if (uVersion > VIRTIO_SAVEDSTATE_VERSION_3_1_BETA1)
731	{
732	rc = SSMR3GetU32(pSSM, &pState->nQueues);
733	AssertRCReturn(rc, rc);
734	}
735	else
736	pState->nQueues = nQueues;
737	for (unsigned i = 0; i < pState->nQueues; i++)
738	{
739	rc = SSMR3GetU16(pSSM, &pState->Queues[i].VRing.uSize);
740	AssertRCReturn(rc, rc);
741	rc = SSMR3GetU32(pSSM, &pState->Queues[i].uPageNumber);
742	AssertRCReturn(rc, rc);
743
744	if (pState->Queues[i].uPageNumber)
745	vqueueInit(&pState->Queues[i], pState->Queues[i].uPageNumber);
746
747	rc = SSMR3GetU16(pSSM, &pState->Queues[i].uNextAvailIndex);
748	AssertRCReturn(rc, rc);
749	rc = SSMR3GetU16(pSSM, &pState->Queues[i].uNextUsedIndex);
750	AssertRCReturn(rc, rc);
751	}
752	}
753
754	vpciDumpState(pState, "vpciLoadExec");
755
756	return VINF_SUCCESS;
757	}
758
759	/**
760	* Set PCI configuration space registers.
761	*
762	* @param pci Reference to PCI device structure.
763	* @param uSubsystemId PCI Subsystem Id
764	* @param uClass Class of PCI device (network, etc)
765	* @thread EMT
766	*/
767	static DECLCALLBACK(void) vpciConfigure(PCIDEVICE& pci,
768	uint16_t uSubsystemId,
769	uint16_t uClass)
770	{
771	/* Configure PCI Device, assume 32-bit mode ******************************/
772	PCIDevSetVendorId(&pci, DEVICE_PCI_VENDOR_ID);
773	PCIDevSetDeviceId(&pci, DEVICE_PCI_DEVICE_ID);
774	vpciCfgSetU16(pci, VBOX_PCI_SUBSYSTEM_VENDOR_ID, DEVICE_PCI_SUBSYSTEM_VENDOR_ID);
775	vpciCfgSetU16(pci, VBOX_PCI_SUBSYSTEM_ID, uSubsystemId);
776
777	/* ABI version, must be equal 0 as of 2.6.30 kernel. */
778	vpciCfgSetU8( pci, VBOX_PCI_REVISION_ID, 0x00);
779	/* Ethernet adapter */
780	vpciCfgSetU8( pci, VBOX_PCI_CLASS_PROG, 0x00);
781	vpciCfgSetU16(pci, VBOX_PCI_CLASS_DEVICE, uClass);
782	/* Interrupt Pin: INTA# */
783	vpciCfgSetU8( pci, VBOX_PCI_INTERRUPT_PIN, 0x01);
784	}
785
786	/* WARNING! This function must never be used in multithreaded context! */
787	static const char vpciCounter(const char pszDevFmt,
788	const char *pszCounter)
789	{
790	static char g_szCounterName[80];
791
792	RTStrPrintf(g_szCounterName, sizeof(g_szCounterName),
793	"/Devices/%s/%s", pszDevFmt, pszCounter);
794
795	return g_szCounterName;
796	}
797
798	// TODO: header
799	DECLCALLBACK(int) vpciConstruct(PPDMDEVINS pDevIns, VPCISTATE *pState,
800	int iInstance, const char *pcszNameFmt,
801	uint16_t uSubsystemId, uint16_t uClass,
802	uint32_t nQueues)
803	{
804	int rc = VINF_SUCCESS;
805	/* Init handles and log related stuff. */
806	RTStrPrintf(pState->szInstance, sizeof(pState->szInstance),
807	pcszNameFmt, iInstance);
808
809	pState->pDevInsR3 = pDevIns;
810	pState->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
811	pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
812	pState->led.u32Magic = PDMLED_MAGIC;
813
814	pState->ILeds.pfnQueryStatusLed = vpciQueryStatusLed;
815
816	/* Initialize critical section. */
817	rc = PDMDevHlpCritSectInit(pDevIns, &pState->cs, RT_SRC_POS, "%s", pState->szInstance);
818	if (RT_FAILURE(rc))
819	return rc;
820
821	/* Set PCI config registers */
822	vpciConfigure(pState->pciDevice, uSubsystemId, uClass);
823	/* Register PCI device */
824	rc = PDMDevHlpPCIRegister(pDevIns, &pState->pciDevice);
825	if (RT_FAILURE(rc))
826	return rc;
827
828	/* Status driver */
829	PPDMIBASE pBase;
830	rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pState->IBase, &pBase, "Status Port");
831	if (RT_FAILURE(rc))
832	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the status LUN"));
833	pState->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
834
835	pState->nQueues = nQueues;
836
837	#if defined(VBOX_WITH_STATISTICS)
838	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in GC", vpciCounter(pcszNameFmt, "IO/ReadGC"), iInstance);
839	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in HC", vpciCounter(pcszNameFmt, "IO/ReadHC"), iInstance);
840	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in GC", vpciCounter(pcszNameFmt, "IO/WriteGC"), iInstance);
841	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in HC", vpciCounter(pcszNameFmt, "IO/WriteHC"), iInstance);
842	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsRaised, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of raised interrupts", vpciCounter(pcszNameFmt, "Interrupts/Raised"), iInstance);
843	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsSkipped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of skipped interrupts", vpciCounter(pcszNameFmt, "Interrupts/Skipped"), iInstance);
844	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatCsGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling CS wait in GC", vpciCounter(pcszNameFmt, "Cs/CsGC"), iInstance);
845	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatCsHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling CS wait in HC", vpciCounter(pcszNameFmt, "Cs/CsHC"), iInstance);
846	#endif /* VBOX_WITH_STATISTICS */
847
848	return rc;
849	}
850
851	/**
852	* Destruct PCI-related part of device.
853	*
854	* We need to free non-VM resources only.
855	*
856	* @returns VBox status.
857	* @param pState The device state structure.
858	*/
859	int vpciDestruct(VPCISTATE* pState)
860	{
861	Log(("%s Destroying PCI instance\n", INSTANCE(pState)));
862
863	if (PDMCritSectIsInitialized(&pState->cs))
864	PDMR3CritSectDelete(&pState->cs);
865
866	return VINF_SUCCESS;
867	}
868
869	/**
870	* Device relocation callback.
871	*
872	* When this callback is called the device instance data, and if the
873	* device have a GC component, is being relocated, or/and the selectors
874	* have been changed. The device must use the chance to perform the
875	* necessary pointer relocations and data updates.
876	*
877	* Before the GC code is executed the first time, this function will be
878	* called with a 0 delta so GC pointer calculations can be one in one place.
879	*
880	* @param pDevIns Pointer to the device instance.
881	* @param offDelta The relocation delta relative to the old location.
882	*
883	* @remark A relocation CANNOT fail.
884	*/
885	void vpciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
886	{
887	VPCISTATE* pState = PDMINS_2_DATA(pDevIns, VPCISTATE*);
888	pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
889	// TBD
890	}
891
892	PVQUEUE vpciAddQueue(VPCISTATE* pState, unsigned uSize,
893	void (pfnCallback)(void pvState, PVQUEUE pQueue),
894	const char *pcszName)
895	{
896	PVQUEUE pQueue = NULL;
897	/* Find an empty queue slot */
898	for (unsigned i = 0; i < pState->nQueues; i++)
899	{
900	if (pState->Queues[i].VRing.uSize == 0)
901	{
902	pQueue = &pState->Queues[i];
903	break;
904	}
905	}
906
907	if (!pQueue)
908	{
909	Log(("%s Too many queues being added, no empty slots available!\n", INSTANCE(pState)));
910	}
911	else
912	{
913	pQueue->VRing.uSize = uSize;
914	pQueue->VRing.addrDescriptors = 0;
915	pQueue->uPageNumber = 0;
916	pQueue->pfnCallback = pfnCallback;
917	pQueue->pcszName = pcszName;
918	}
919
920	return pQueue;
921	}
922
923	#endif /* IN_RING3 */
924
925	#endif /* VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/VirtIO/Virtio.cpp@ 28800

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