Virtio.cpp@ 63562

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1	/* $Id: Virtio.cpp 63562 2016-08-16 14:04:03Z vboxsync $ */
2	/** @file
3	* Virtio - Virtio Common Functions (VRing, VQueue, Virtio PCI)
4	*/
5
6	/*
7	* Copyright (C) 2009-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_VIRTIO
23
24	#include <iprt/param.h>
25	#include <iprt/uuid.h>
26	#include <VBox/vmm/pdmdev.h>
27	#include "Virtio.h"
28
29	#define INSTANCE(pState) pState->szInstance
30	#define IFACE_TO_STATE(pIface, ifaceName) ((VPCISTATE )((char)pIface - RT_OFFSETOF(VPCISTATE, ifaceName)))
31
32	#ifdef LOG_ENABLED
33	# define QUEUENAME(s, q) (q->pcszName)
34	#endif
35
36
37
38	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
39
40	//RT_C_DECLS_BEGIN
41	//RT_C_DECLS_END
42
43
44	static void vqueueReset(PVQUEUE pQueue)
45	{
46	pQueue->VRing.addrDescriptors = 0;
47	pQueue->VRing.addrAvail = 0;
48	pQueue->VRing.addrUsed = 0;
49	pQueue->uNextAvailIndex = 0;
50	pQueue->uNextUsedIndex = 0;
51	pQueue->uPageNumber = 0;
52	}
53
54	static void vqueueInit(PVQUEUE pQueue, uint32_t uPageNumber)
55	{
56	pQueue->VRing.addrDescriptors = (uint64_t)uPageNumber << PAGE_SHIFT;
57	pQueue->VRing.addrAvail = pQueue->VRing.addrDescriptors
58	+ sizeof(VRINGDESC) * pQueue->VRing.uSize;
59	pQueue->VRing.addrUsed = RT_ALIGN(
60	pQueue->VRing.addrAvail + RT_OFFSETOF(VRINGAVAIL, auRing[pQueue->VRing.uSize]),
61	PAGE_SIZE); /* The used ring must start from the next page. */
62	pQueue->uNextAvailIndex = 0;
63	pQueue->uNextUsedIndex = 0;
64	}
65
66	// void vqueueElemFree(PVQUEUEELEM pElem)
67	// {
68	// }
69
70	void vringReadDesc(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex, PVRINGDESC pDesc)
71	{
72	//Log(("%s vringReadDesc: ring=%p idx=%u\n", INSTANCE(pState), pVRing, uIndex));
73	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
74	pVRing->addrDescriptors + sizeof(VRINGDESC) * (uIndex % pVRing->uSize),
75	pDesc, sizeof(VRINGDESC));
76	}
77
78	uint16_t vringReadAvail(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex)
79	{
80	uint16_t tmp;
81
82	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
83	pVRing->addrAvail + RT_OFFSETOF(VRINGAVAIL, auRing[uIndex % pVRing->uSize]),
84	&tmp, sizeof(tmp));
85	return tmp;
86	}
87
88	uint16_t vringReadAvailFlags(PVPCISTATE pState, PVRING pVRing)
89	{
90	uint16_t tmp;
91
92	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
93	pVRing->addrAvail + RT_OFFSETOF(VRINGAVAIL, uFlags),
94	&tmp, sizeof(tmp));
95	return tmp;
96	}
97
98	void vringSetNotification(PVPCISTATE pState, PVRING pVRing, bool fEnabled)
99	{
100	uint16_t tmp;
101
102	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
103	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uFlags),
104	&tmp, sizeof(tmp));
105
106	if (fEnabled)
107	tmp &= ~ VRINGUSED_F_NO_NOTIFY;
108	else
109	tmp \|= VRINGUSED_F_NO_NOTIFY;
110
111	PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns),
112	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uFlags),
113	&tmp, sizeof(tmp));
114	}
115
116	bool vqueueSkip(PVPCISTATE pState, PVQUEUE pQueue)
117	{
118	if (vqueueIsEmpty(pState, pQueue))
119	return false;
120
121	Log2(("%s vqueueSkip: %s avail_idx=%u\n", INSTANCE(pState),
122	QUEUENAME(pState, pQueue), pQueue->uNextAvailIndex));
123	pQueue->uNextAvailIndex++;
124	return true;
125	}
126
127	bool vqueueGet(PVPCISTATE pState, PVQUEUE pQueue, PVQUEUEELEM pElem, bool fRemove)
128	{
129	if (vqueueIsEmpty(pState, pQueue))
130	return false;
131
132	pElem->nIn = pElem->nOut = 0;
133
134	Log2(("%s vqueueGet: %s avail_idx=%u\n", INSTANCE(pState),
135	QUEUENAME(pState, pQueue), pQueue->uNextAvailIndex));
136
137	VRINGDESC desc;
138	uint16_t idx = vringReadAvail(pState, &pQueue->VRing, pQueue->uNextAvailIndex);
139	if (fRemove)
140	pQueue->uNextAvailIndex++;
141	pElem->uIndex = idx;
142	do
143	{
144	VQUEUESEG *pSeg;
145
146	vringReadDesc(pState, &pQueue->VRing, idx, &desc);
147	if (desc.u16Flags & VRINGDESC_F_WRITE)
148	{
149	Log2(("%s vqueueGet: %s IN seg=%u desc_idx=%u addr=%p cb=%u\n", INSTANCE(pState),
150	QUEUENAME(pState, pQueue), pElem->nIn, idx, desc.u64Addr, desc.uLen));
151	pSeg = &pElem->aSegsIn[pElem->nIn++];
152	}
153	else
154	{
155	Log2(("%s vqueueGet: %s OUT seg=%u desc_idx=%u addr=%p cb=%u\n", INSTANCE(pState),
156	QUEUENAME(pState, pQueue), pElem->nOut, idx, desc.u64Addr, desc.uLen));
157	pSeg = &pElem->aSegsOut[pElem->nOut++];
158	}
159
160	pSeg->addr = desc.u64Addr;
161	pSeg->cb = desc.uLen;
162	pSeg->pv = NULL;
163
164	idx = desc.u16Next;
165	} while (desc.u16Flags & VRINGDESC_F_NEXT);
166
167	Log2(("%s vqueueGet: %s head_desc_idx=%u nIn=%u nOut=%u\n", INSTANCE(pState),
168	QUEUENAME(pState, pQueue), pElem->uIndex, pElem->nIn, pElem->nOut));
169	return true;
170	}
171
172	uint16_t vringReadUsedIndex(PVPCISTATE pState, PVRING pVRing)
173	{
174	uint16_t tmp;
175	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
176	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uIndex),
177	&tmp, sizeof(tmp));
178	return tmp;
179	}
180
181	void vringWriteUsedIndex(PVPCISTATE pState, PVRING pVRing, uint16_t u16Value)
182	{
183	PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns),
184	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uIndex),
185	&u16Value, sizeof(u16Value));
186	}
187
188	void vringWriteUsedElem(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex, uint32_t uId, uint32_t uLen)
189	{
190	VRINGUSEDELEM elem;
191
192	elem.uId = uId;
193	elem.uLen = uLen;
194	PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns),
195	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, aRing[uIndex % pVRing->uSize]),
196	&elem, sizeof(elem));
197	}
198
199	void vqueuePut(PVPCISTATE pState, PVQUEUE pQueue, PVQUEUEELEM pElem, uint32_t uLen, uint32_t uReserved)
200	{
201	unsigned int i, uOffset, cbReserved = uReserved;
202
203	Log2(("%s vqueuePut: %s desc_idx=%u acb=%u\n", INSTANCE(pState),
204	QUEUENAME(pState, pQueue), pElem->uIndex, uLen));
205	for (i = uOffset = 0; i < pElem->nIn && uOffset < uLen - uReserved; i++)
206	{
207	uint32_t cbSegLen = RT_MIN(uLen - cbReserved - uOffset, pElem->aSegsIn[i].cb - cbReserved);
208	if (pElem->aSegsIn[i].pv)
209	{
210	Log2(("%s vqueuePut: %s used_idx=%u seg=%u addr=%p pv=%p cb=%u acb=%u\n", INSTANCE(pState),
211	QUEUENAME(pState, pQueue), pQueue->uNextUsedIndex, i, pElem->aSegsIn[i].addr, pElem->aSegsIn[i].pv, pElem->aSegsIn[i].cb, cbSegLen));
212	PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns), pElem->aSegsIn[i].addr + cbReserved,
213	pElem->aSegsIn[i].pv, cbSegLen);
214	cbReserved = 0;
215	}
216	uOffset += cbSegLen;
217	}
218
219	Assert((uReserved + uOffset) == uLen \|\| pElem->nIn == 0);
220	Log2(("%s vqueuePut: %s used_idx=%u guest_used_idx=%u id=%u len=%u\n", INSTANCE(pState),
221	QUEUENAME(pState, pQueue), pQueue->uNextUsedIndex, vringReadUsedIndex(pState, &pQueue->VRing), pElem->uIndex, uLen));
222	vringWriteUsedElem(pState, &pQueue->VRing, pQueue->uNextUsedIndex++, pElem->uIndex, uLen);
223	}
224
225	void vqueueNotify(PVPCISTATE pState, PVQUEUE pQueue)
226	{
227	LogFlow(("%s vqueueNotify: %s availFlags=%x guestFeatures=%x vqueue is %sempty\n",
228	INSTANCE(pState), QUEUENAME(pState, pQueue),
229	vringReadAvailFlags(pState, &pQueue->VRing),
230	pState->uGuestFeatures, vqueueIsEmpty(pState, pQueue)?"":"not "));
231	if (!(vringReadAvailFlags(pState, &pQueue->VRing) & VRINGAVAIL_F_NO_INTERRUPT)
232	\|\| ((pState->uGuestFeatures & VPCI_F_NOTIFY_ON_EMPTY) && vqueueIsEmpty(pState, pQueue)))
233	{
234	int rc = vpciRaiseInterrupt(pState, VERR_INTERNAL_ERROR, VPCI_ISR_QUEUE);
235	if (RT_FAILURE(rc))
236	Log(("%s vqueueNotify: Failed to raise an interrupt (%Rrc).\n", INSTANCE(pState), rc));
237	}
238	else
239	{
240	STAM_COUNTER_INC(&pState->StatIntsSkipped);
241	}
242
243	}
244
245	void vqueueSync(PVPCISTATE pState, PVQUEUE pQueue)
246	{
247	Log2(("%s vqueueSync: %s old_used_idx=%u new_used_idx=%u\n", INSTANCE(pState),
248	QUEUENAME(pState, pQueue), vringReadUsedIndex(pState, &pQueue->VRing), pQueue->uNextUsedIndex));
249	vringWriteUsedIndex(pState, &pQueue->VRing, pQueue->uNextUsedIndex);
250	vqueueNotify(pState, pQueue);
251	}
252
253	void vpciReset(PVPCISTATE pState)
254	{
255	pState->uGuestFeatures = 0;
256	pState->uQueueSelector = 0;
257	pState->uStatus = 0;
258	pState->uISR = 0;
259
260	for (unsigned i = 0; i < pState->nQueues; i++)
261	vqueueReset(&pState->Queues[i]);
262	}
263
264
265	/**
266	* Raise interrupt.
267	*
268	* @param pState The device state structure.
269	* @param rcBusy Status code to return when the critical section is busy.
270	* @param u8IntCause Interrupt cause bit mask to set in PCI ISR port.
271	*/
272	int vpciRaiseInterrupt(VPCISTATE *pState, int rcBusy, uint8_t u8IntCause)
273	{
274	RT_NOREF_PV(rcBusy);
275	// int rc = vpciCsEnter(pState, rcBusy);
276	// if (RT_UNLIKELY(rc != VINF_SUCCESS))
277	// return rc;
278
279	STAM_COUNTER_INC(&pState->StatIntsRaised);
280	LogFlow(("%s vpciRaiseInterrupt: u8IntCause=%x\n",
281	INSTANCE(pState), u8IntCause));
282
283	pState->uISR \|= u8IntCause;
284	PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 1);
285	// vpciCsLeave(pState);
286	return VINF_SUCCESS;
287	}
288
289	/**
290	* Lower interrupt.
291	*
292	* @param pState The device state structure.
293	*/
294	static void vpciLowerInterrupt(VPCISTATE *pState)
295	{
296	LogFlow(("%s vpciLowerInterrupt\n", INSTANCE(pState)));
297	PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 0);
298	}
299
300	DECLINLINE(uint32_t) vpciGetHostFeatures(PVPCISTATE pState,
301	PFNGETHOSTFEATURES pfnGetHostFeatures)
302	{
303	return pfnGetHostFeatures(pState)
304	\| VPCI_F_NOTIFY_ON_EMPTY;
305	}
306
307	/**
308	* Port I/O Handler for IN operations.
309	*
310	* @returns VBox status code.
311	*
312	* @param pDevIns The device instance.
313	* @param pvUser Pointer to the device state structure.
314	* @param Port Port number used for the IN operation.
315	* @param pu32 Where to store the result.
316	* @param cb Number of bytes read.
317	* @param pCallbacks Pointer to the callbacks.
318	* @thread EMT
319	*/
320	int vpciIOPortIn(PPDMDEVINS pDevIns,
321	void *pvUser,
322	RTIOPORT Port,
323	uint32_t *pu32,
324	unsigned cb,
325	PCVPCIIOCALLBACKS pCallbacks)
326	{
327	VPCISTATE pState = PDMINS_2_DATA(pDevIns, VPCISTATE );
328	int rc = VINF_SUCCESS;
329	STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIORead), a);
330	RT_NOREF_PV(pvUser);
331
332	/*
333	* We probably do not need to enter critical section when reading registers
334	* as the most of them are either constant or being changed during
335	* initialization only, the exception being ISR which can be raced by all
336	* threads but I see no big harm in it. It also happens to be the most read
337	* register as it gets read in interrupt handler. By dropping cs protection
338	* here we gain the ability to deliver RX packets to the guest while TX is
339	* holding cs transmitting queued packets.
340	*
341	rc = vpciCsEnter(pState, VINF_IOM_R3_IOPORT_READ);
342	if (RT_UNLIKELY(rc != VINF_SUCCESS))
343	{
344	STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIORead), a);
345	return rc;
346	}*/
347
348	Port -= pState->IOPortBase;
349	switch (Port)
350	{
351	case VPCI_HOST_FEATURES:
352	/* Tell the guest what features we support. */
353	*pu32 = vpciGetHostFeatures(pState, pCallbacks->pfnGetHostFeatures)
354	\| VPCI_F_BAD_FEATURE;
355	break;
356
357	case VPCI_GUEST_FEATURES:
358	*pu32 = pState->uGuestFeatures;
359	break;
360
361	case VPCI_QUEUE_PFN:
362	*pu32 = pState->Queues[pState->uQueueSelector].uPageNumber;
363	break;
364
365	case VPCI_QUEUE_NUM:
366	Assert(cb == 2);
367	(uint16_t)pu32 = pState->Queues[pState->uQueueSelector].VRing.uSize;
368	break;
369
370	case VPCI_QUEUE_SEL:
371	Assert(cb == 2);
372	(uint16_t)pu32 = pState->uQueueSelector;
373	break;
374
375	case VPCI_STATUS:
376	Assert(cb == 1);
377	(uint8_t)pu32 = pState->uStatus;
378	break;
379
380	case VPCI_ISR:
381	Assert(cb == 1);
382	(uint8_t)pu32 = pState->uISR;
383	pState->uISR = 0; /* read clears all interrupts */
384	vpciLowerInterrupt(pState);
385	break;
386
387	default:
388	if (Port >= VPCI_CONFIG)
389	rc = pCallbacks->pfnGetConfig(pState, Port - VPCI_CONFIG, cb, pu32);
390	else
391	{
392	*pu32 = 0xFFFFFFFF;
393	rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortIn: no valid port at offset port=%RTiop cb=%08x\n",
394	INSTANCE(pState), Port, cb);
395	}
396	break;
397	}
398	Log3(("%s vpciIOPortIn: At %RTiop in %0x\n", INSTANCE(pState), Port, cb2, *pu32));
399	STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIORead), a);
400	//vpciCsLeave(pState);
401	return rc;
402	}
403
404
405	/**
406	* Port I/O Handler for OUT operations.
407	*
408	* @returns VBox status code.
409	*
410	* @param pDevIns The device instance.
411	* @param pvUser User argument.
412	* @param Port Port number used for the IN operation.
413	* @param u32 The value to output.
414	* @param cb The value size in bytes.
415	* @param pCallbacks Pointer to the callbacks.
416	* @thread EMT
417	*/
418	int vpciIOPortOut(PPDMDEVINS pDevIns,
419	void *pvUser,
420	RTIOPORT Port,
421	uint32_t u32,
422	unsigned cb,
423	PCVPCIIOCALLBACKS pCallbacks)
424	{
425	VPCISTATE pState = PDMINS_2_DATA(pDevIns, VPCISTATE );
426	int rc = VINF_SUCCESS;
427	bool fHasBecomeReady;
428	STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIOWrite), a);
429	RT_NOREF_PV(pvUser);
430
431	Port -= pState->IOPortBase;
432	Log3(("%s virtioIOPortOut: At %RTiop out %0x\n", INSTANCE(pState), Port, cb2, u32));
433
434	switch (Port)
435	{
436	case VPCI_GUEST_FEATURES:
437	/* Check if the guest negotiates properly, fall back to basics if it does not. */
438	if (VPCI_F_BAD_FEATURE & u32)
439	{
440	Log(("%s WARNING! Guest failed to negotiate properly (guest=%x)\n",
441	INSTANCE(pState), u32));
442	pState->uGuestFeatures = pCallbacks->pfnGetHostMinimalFeatures(pState);
443	}
444	/* The guest may potentially desire features we don't support! */
445	else if (~vpciGetHostFeatures(pState, pCallbacks->pfnGetHostFeatures) & u32)
446	{
447	Log(("%s Guest asked for features host does not support! (host=%x guest=%x)\n",
448	INSTANCE(pState),
449	vpciGetHostFeatures(pState, pCallbacks->pfnGetHostFeatures), u32));
450	pState->uGuestFeatures =
451	vpciGetHostFeatures(pState, pCallbacks->pfnGetHostFeatures);
452	}
453	else
454	pState->uGuestFeatures = u32;
455	pCallbacks->pfnSetHostFeatures(pState, pState->uGuestFeatures);
456	break;
457
458	case VPCI_QUEUE_PFN:
459	/*
460	* The guest is responsible for allocating the pages for queues,
461	* here it provides us with the page number of descriptor table.
462	* Note that we provide the size of the queue to the guest via
463	* VIRTIO_PCI_QUEUE_NUM.
464	*/
465	pState->Queues[pState->uQueueSelector].uPageNumber = u32;
466	if (u32)
467	vqueueInit(&pState->Queues[pState->uQueueSelector], u32);
468	else
469	rc = pCallbacks->pfnReset(pState);
470	break;
471
472	case VPCI_QUEUE_SEL:
473	Assert(cb == 2);
474	u32 &= 0xFFFF;
475	if (u32 < pState->nQueues)
476	pState->uQueueSelector = u32;
477	else
478	Log3(("%s vpciIOPortOut: Invalid queue selector %08x\n", INSTANCE(pState), u32));
479	break;
480
481	case VPCI_QUEUE_NOTIFY:
482	#ifdef IN_RING3
483	Assert(cb == 2);
484	u32 &= 0xFFFF;
485	if (u32 < pState->nQueues)
486	if (pState->Queues[u32].VRing.addrDescriptors)
487	{
488	// rc = vpciCsEnter(pState, VERR_SEM_BUSY);
489	// if (RT_LIKELY(rc == VINF_SUCCESS))
490	// {
491	pState->Queues[u32].pfnCallback(pState, &pState->Queues[u32]);
492	// vpciCsLeave(pState);
493	// }
494	}
495	else
496	Log(("%s The queue (#%d) being notified has not been initialized.\n",
497	INSTANCE(pState), u32));
498	else
499	Log(("%s Invalid queue number (%d)\n", INSTANCE(pState), u32));
500	#else
501	rc = VINF_IOM_R3_IOPORT_WRITE;
502	#endif
503	break;
504
505	case VPCI_STATUS:
506	Assert(cb == 1);
507	u32 &= 0xFF;
508	fHasBecomeReady = !(pState->uStatus & VPCI_STATUS_DRV_OK) && (u32 & VPCI_STATUS_DRV_OK);
509	pState->uStatus = u32;
510	/* Writing 0 to the status port triggers device reset. */
511	if (u32 == 0)
512	rc = pCallbacks->pfnReset(pState);
513	else if (fHasBecomeReady)
514	pCallbacks->pfnReady(pState);
515	break;
516
517	default:
518	if (Port >= VPCI_CONFIG)
519	rc = pCallbacks->pfnSetConfig(pState, Port - VPCI_CONFIG, cb, &u32);
520	else
521	rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortOut: no valid port at offset Port=%RTiop cb=%08x\n",
522	INSTANCE(pState), Port, cb);
523	break;
524	}
525
526	STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIOWrite), a);
527	return rc;
528	}
529
530	#ifdef IN_RING3
531
532	/**
533	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
534	*/
535	void vpciQueryInterface(struct PDMIBASE pInterface, const char *pszIID)
536	{
537	VPCISTATE *pThis = IFACE_TO_STATE(pInterface, IBase);
538	Assert(&pThis->IBase == pInterface);
539
540	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
541	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
542	return NULL;
543	}
544
545	/**
546	* Gets the pointer to the status LED of a unit.
547	*
548	* @returns VBox status code.
549	* @param pInterface Pointer to the interface structure.
550	* @param iLUN The unit which status LED we desire.
551	* @param ppLed Where to store the LED pointer.
552	* @thread EMT
553	*/
554	static DECLCALLBACK(int) vpciQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
555	{
556	VPCISTATE *pState = IFACE_TO_STATE(pInterface, ILeds);
557	int rc = VERR_PDM_LUN_NOT_FOUND;
558
559	if (iLUN == 0)
560	{
561	*ppLed = &pState->led;
562	rc = VINF_SUCCESS;
563	}
564	return rc;
565	}
566
567	/**
568	* Turns on/off the write status LED.
569	*
570	* @returns VBox status code.
571	* @param pState Pointer to the device state structure.
572	* @param fOn New LED state.
573	*/
574	void vpciSetWriteLed(PVPCISTATE pState, bool fOn)
575	{
576	LogFlow(("%s vpciSetWriteLed: %s\n", INSTANCE(pState), fOn?"on":"off"));
577	if (fOn)
578	pState->led.Asserted.s.fWriting = pState->led.Actual.s.fWriting = 1;
579	else
580	pState->led.Actual.s.fWriting = fOn;
581	}
582
583	/**
584	* Turns on/off the read status LED.
585	*
586	* @returns VBox status code.
587	* @param pState Pointer to the device state structure.
588	* @param fOn New LED state.
589	*/
590	void vpciSetReadLed(PVPCISTATE pState, bool fOn)
591	{
592	LogFlow(("%s vpciSetReadLed: %s\n", INSTANCE(pState), fOn?"on":"off"));
593	if (fOn)
594	pState->led.Asserted.s.fReading = pState->led.Actual.s.fReading = 1;
595	else
596	pState->led.Actual.s.fReading = fOn;
597	}
598
599	/**
600	* Sets 8-bit register in PCI configuration space.
601	* @param refPciDev The PCI device.
602	* @param uOffset The register offset.
603	* @param u16Value The value to store in the register.
604	* @thread EMT
605	*/
606	DECLINLINE(void) vpciCfgSetU8(PCIDEVICE& refPciDev, uint32_t uOffset, uint8_t u8Value)
607	{
608	Assert(uOffset < sizeof(refPciDev.config));
609	refPciDev.config[uOffset] = u8Value;
610	}
611
612	/**
613	* Sets 16-bit register in PCI configuration space.
614	* @param refPciDev The PCI device.
615	* @param uOffset The register offset.
616	* @param u16Value The value to store in the register.
617	* @thread EMT
618	*/
619	DECLINLINE(void) vpciCfgSetU16(PCIDEVICE& refPciDev, uint32_t uOffset, uint16_t u16Value)
620	{
621	Assert(uOffset+sizeof(u16Value) <= sizeof(refPciDev.config));
622	(uint16_t)&refPciDev.config[uOffset] = u16Value;
623	}
624
625	#if 0 /* unused */
626	/**
627	* Sets 32-bit register in PCI configuration space.
628	* @param refPciDev The PCI device.
629	* @param uOffset The register offset.
630	* @param u32Value The value to store in the register.
631	* @thread EMT
632	*/
633	DECLINLINE(void) vpciCfgSetU32(PCIDEVICE& refPciDev, uint32_t uOffset, uint32_t u32Value)
634	{
635	Assert(uOffset+sizeof(u32Value) <= sizeof(refPciDev.config));
636	(uint32_t)&refPciDev.config[uOffset] = u32Value;
637	}
638	#endif /* unused */
639
640
641	#ifdef DEBUG
642	static void vpciDumpState(PVPCISTATE pState, const char *pcszCaller)
643	{
644	Log2(("vpciDumpState: (called from %s)\n"
645	" uGuestFeatures = 0x%08x\n"
646	" uQueueSelector = 0x%04x\n"
647	" uStatus = 0x%02x\n"
648	" uISR = 0x%02x\n",
649	pcszCaller,
650	pState->uGuestFeatures,
651	pState->uQueueSelector,
652	pState->uStatus,
653	pState->uISR));
654
655	for (unsigned i = 0; i < pState->nQueues; i++)
656	Log2((" %s queue:\n"
657	" VRing.uSize = %u\n"
658	" VRing.addrDescriptors = %p\n"
659	" VRing.addrAvail = %p\n"
660	" VRing.addrUsed = %p\n"
661	" uNextAvailIndex = %u\n"
662	" uNextUsedIndex = %u\n"
663	" uPageNumber = %x\n",
664	pState->Queues[i].pcszName,
665	pState->Queues[i].VRing.uSize,
666	pState->Queues[i].VRing.addrDescriptors,
667	pState->Queues[i].VRing.addrAvail,
668	pState->Queues[i].VRing.addrUsed,
669	pState->Queues[i].uNextAvailIndex,
670	pState->Queues[i].uNextUsedIndex,
671	pState->Queues[i].uPageNumber));
672	}
673	#else
674	# define vpciDumpState(x, s) do {} while (0)
675	#endif
676
677	/**
678	* Saves the state of device.
679	*
680	* @returns VBox status code.
681	* @param pDevIns The device instance.
682	* @param pSSM The handle to the saved state.
683	*/
684	int vpciSaveExec(PVPCISTATE pState, PSSMHANDLE pSSM)
685	{
686	int rc;
687
688	vpciDumpState(pState, "vpciSaveExec");
689
690	rc = SSMR3PutU32(pSSM, pState->uGuestFeatures);
691	AssertRCReturn(rc, rc);
692	rc = SSMR3PutU16(pSSM, pState->uQueueSelector);
693	AssertRCReturn(rc, rc);
694	rc = SSMR3PutU8( pSSM, pState->uStatus);
695	AssertRCReturn(rc, rc);
696	rc = SSMR3PutU8( pSSM, pState->uISR);
697	AssertRCReturn(rc, rc);
698
699	/* Save queue states */
700	rc = SSMR3PutU32(pSSM, pState->nQueues);
701	AssertRCReturn(rc, rc);
702	for (unsigned i = 0; i < pState->nQueues; i++)
703	{
704	rc = SSMR3PutU16(pSSM, pState->Queues[i].VRing.uSize);
705	AssertRCReturn(rc, rc);
706	rc = SSMR3PutU32(pSSM, pState->Queues[i].uPageNumber);
707	AssertRCReturn(rc, rc);
708	rc = SSMR3PutU16(pSSM, pState->Queues[i].uNextAvailIndex);
709	AssertRCReturn(rc, rc);
710	rc = SSMR3PutU16(pSSM, pState->Queues[i].uNextUsedIndex);
711	AssertRCReturn(rc, rc);
712	}
713
714	return VINF_SUCCESS;
715	}
716
717	/**
718	* Loads a saved device state.
719	*
720	* @returns VBox status code.
721	* @param pDevIns The device instance.
722	* @param pSSM The handle to the saved state.
723	* @param uVersion The data unit version number.
724	* @param uPass The data pass.
725	*/
726	int vpciLoadExec(PVPCISTATE pState, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass, uint32_t nQueues)
727	{
728	int rc;
729
730	if (uPass == SSM_PASS_FINAL)
731	{
732	/* Restore state data */
733	rc = SSMR3GetU32(pSSM, &pState->uGuestFeatures);
734	AssertRCReturn(rc, rc);
735	rc = SSMR3GetU16(pSSM, &pState->uQueueSelector);
736	AssertRCReturn(rc, rc);
737	rc = SSMR3GetU8( pSSM, &pState->uStatus);
738	AssertRCReturn(rc, rc);
739	rc = SSMR3GetU8( pSSM, &pState->uISR);
740	AssertRCReturn(rc, rc);
741
742	/* Restore queues */
743	if (uVersion > VIRTIO_SAVEDSTATE_VERSION_3_1_BETA1)
744	{
745	rc = SSMR3GetU32(pSSM, &pState->nQueues);
746	AssertRCReturn(rc, rc);
747	}
748	else
749	pState->nQueues = nQueues;
750	for (unsigned i = 0; i < pState->nQueues; i++)
751	{
752	rc = SSMR3GetU16(pSSM, &pState->Queues[i].VRing.uSize);
753	AssertRCReturn(rc, rc);
754	rc = SSMR3GetU32(pSSM, &pState->Queues[i].uPageNumber);
755	AssertRCReturn(rc, rc);
756
757	if (pState->Queues[i].uPageNumber)
758	vqueueInit(&pState->Queues[i], pState->Queues[i].uPageNumber);
759
760	rc = SSMR3GetU16(pSSM, &pState->Queues[i].uNextAvailIndex);
761	AssertRCReturn(rc, rc);
762	rc = SSMR3GetU16(pSSM, &pState->Queues[i].uNextUsedIndex);
763	AssertRCReturn(rc, rc);
764	}
765	}
766
767	vpciDumpState(pState, "vpciLoadExec");
768
769	return VINF_SUCCESS;
770	}
771
772	/**
773	* Set PCI configuration space registers.
774	*
775	* @param pci Reference to PCI device structure.
776	* @param uDeviceId VirtiO Device Id
777	* @param uClass Class of PCI device (network, etc)
778	* @thread EMT
779	*/
780	static DECLCALLBACK(void) vpciConfigure(PCIDEVICE& pci,
781	uint16_t uDeviceId,
782	uint16_t uClass)
783	{
784	/* Configure PCI Device, assume 32-bit mode ******************************/
785	PCIDevSetVendorId(&pci, DEVICE_PCI_VENDOR_ID);
786	PCIDevSetDeviceId(&pci, DEVICE_PCI_BASE_ID + uDeviceId);
787	vpciCfgSetU16(pci, VBOX_PCI_SUBSYSTEM_VENDOR_ID, DEVICE_PCI_SUBSYSTEM_VENDOR_ID);
788	vpciCfgSetU16(pci, VBOX_PCI_SUBSYSTEM_ID, DEVICE_PCI_SUBSYSTEM_BASE_ID + uDeviceId);
789
790	/* ABI version, must be equal 0 as of 2.6.30 kernel. */
791	vpciCfgSetU8( pci, VBOX_PCI_REVISION_ID, 0x00);
792	/* Ethernet adapter */
793	vpciCfgSetU8( pci, VBOX_PCI_CLASS_PROG, 0x00);
794	vpciCfgSetU16(pci, VBOX_PCI_CLASS_DEVICE, uClass);
795	/* Interrupt Pin: INTA# */
796	vpciCfgSetU8( pci, VBOX_PCI_INTERRUPT_PIN, 0x01);
797
798	#ifdef VBOX_WITH_MSI_DEVICES
799	PCIDevSetCapabilityList (&pci, 0x80);
800	PCIDevSetStatus (&pci, VBOX_PCI_STATUS_CAP_LIST);
801	#endif
802	}
803
804	#ifdef VBOX_WITH_STATISTICS
805	/* WARNING! This function must never be used in multithreaded context! */
806	static const char vpciCounter(const char pszDevFmt,
807	const char *pszCounter)
808	{
809	static char s_szCounterName[80];
810
811	RTStrPrintf(s_szCounterName, sizeof(s_szCounterName),
812	"/Devices/%s/%s", pszDevFmt, pszCounter);
813
814	return s_szCounterName;
815	}
816	#endif
817
818	/// @todo header
819	int vpciConstruct(PPDMDEVINS pDevIns, VPCISTATE *pState,
820	int iInstance, const char *pcszNameFmt,
821	uint16_t uDeviceId, uint16_t uClass,
822	uint32_t nQueues)
823	{
824	/* Init handles and log related stuff. */
825	RTStrPrintf(pState->szInstance, sizeof(pState->szInstance),
826	pcszNameFmt, iInstance);
827
828	pState->pDevInsR3 = pDevIns;
829	pState->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
830	pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
831	pState->led.u32Magic = PDMLED_MAGIC;
832
833	pState->ILeds.pfnQueryStatusLed = vpciQueryStatusLed;
834
835	/* Initialize critical section. */
836	int rc = PDMDevHlpCritSectInit(pDevIns, &pState->cs, RT_SRC_POS, "%s", pState->szInstance);
837	if (RT_FAILURE(rc))
838	return rc;
839
840	/* Set PCI config registers */
841	vpciConfigure(pState->pciDevice, uDeviceId, uClass);
842	/* Register PCI device */
843	rc = PDMDevHlpPCIRegister(pDevIns, &pState->pciDevice);
844	if (RT_FAILURE(rc))
845	return rc;
846
847	#ifdef VBOX_WITH_MSI_DEVICES
848	#if 0
849	{
850	PDMMSIREG aMsiReg;
851
852	RT_ZERO(aMsiReg);
853	aMsiReg.cMsixVectors = 1;
854	aMsiReg.iMsixCapOffset = 0x80;
855	aMsiReg.iMsixNextOffset = 0x0;
856	aMsiReg.iMsixBar = 0;
857	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &aMsiReg);
858	if (RT_FAILURE (rc))
859	PCIDevSetCapabilityList(&pState->pciDevice, 0x0);
860	}
861	#endif
862	#endif
863
864	/* Status driver */
865	PPDMIBASE pBase;
866	rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pState->IBase, &pBase, "Status Port");
867	if (RT_FAILURE(rc))
868	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the status LUN"));
869	pState->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
870
871	pState->nQueues = nQueues;
872
873	#if defined(VBOX_WITH_STATISTICS)
874	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in GC", vpciCounter(pcszNameFmt, "IO/ReadGC"), iInstance);
875	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in HC", vpciCounter(pcszNameFmt, "IO/ReadHC"), iInstance);
876	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in GC", vpciCounter(pcszNameFmt, "IO/WriteGC"), iInstance);
877	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in HC", vpciCounter(pcszNameFmt, "IO/WriteHC"), iInstance);
878	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsRaised, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of raised interrupts", vpciCounter(pcszNameFmt, "Interrupts/Raised"), iInstance);
879	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsSkipped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of skipped interrupts", vpciCounter(pcszNameFmt, "Interrupts/Skipped"), iInstance);
880	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatCsGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling CS wait in GC", vpciCounter(pcszNameFmt, "Cs/CsGC"), iInstance);
881	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatCsHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling CS wait in HC", vpciCounter(pcszNameFmt, "Cs/CsHC"), iInstance);
882	#endif /* VBOX_WITH_STATISTICS */
883
884	return rc;
885	}
886
887	/**
888	* Destruct PCI-related part of device.
889	*
890	* We need to free non-VM resources only.
891	*
892	* @returns VBox status code.
893	* @param pState The device state structure.
894	*/
895	int vpciDestruct(VPCISTATE* pState)
896	{
897	Log(("%s Destroying PCI instance\n", INSTANCE(pState)));
898
899	if (PDMCritSectIsInitialized(&pState->cs))
900	PDMR3CritSectDelete(&pState->cs);
901
902	return VINF_SUCCESS;
903	}
904
905	/**
906	* Device relocation callback.
907	*
908	* When this callback is called the device instance data, and if the
909	* device have a GC component, is being relocated, or/and the selectors
910	* have been changed. The device must use the chance to perform the
911	* necessary pointer relocations and data updates.
912	*
913	* Before the GC code is executed the first time, this function will be
914	* called with a 0 delta so GC pointer calculations can be one in one place.
915	*
916	* @param pDevIns Pointer to the device instance.
917	* @param offDelta The relocation delta relative to the old location.
918	*
919	* @remark A relocation CANNOT fail.
920	*/
921	void vpciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
922	{
923	RT_NOREF(offDelta);
924	VPCISTATE pState = PDMINS_2_DATA(pDevIns, VPCISTATE);
925	pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
926	// TBD
927	}
928
929	PVQUEUE vpciAddQueue(VPCISTATE* pState, unsigned uSize, PFNVPCIQUEUECALLBACK pfnCallback, const char *pcszName)
930	{
931	PVQUEUE pQueue = NULL;
932	/* Find an empty queue slot */
933	for (unsigned i = 0; i < pState->nQueues; i++)
934	{
935	if (pState->Queues[i].VRing.uSize == 0)
936	{
937	pQueue = &pState->Queues[i];
938	break;
939	}
940	}
941
942	if (!pQueue)
943	{
944	Log(("%s Too many queues being added, no empty slots available!\n", INSTANCE(pState)));
945	}
946	else
947	{
948	pQueue->VRing.uSize = uSize;
949	pQueue->VRing.addrDescriptors = 0;
950	pQueue->uPageNumber = 0;
951	pQueue->pfnCallback = pfnCallback;
952	pQueue->pcszName = pcszName;
953	}
954
955	return pQueue;
956	}
957
958	#endif /* IN_RING3 */
959
960	#endif /* VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/VirtIO/Virtio.cpp@ 63562

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