Virtio.cpp@ 64809

Last change on this file since 64809 was 64809, checked in by vboxsync, 8 years ago
Devices/Virtio: vqueuePut - when computing remaining transfer size, use constant uReserved, not variable cbReserved that is reset after the first loop iteration. Makes assertion at the end of function happy.
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File size: 33.2 KB

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1	/* $Id: Virtio.cpp 64809 2016-12-08 13:54:26Z vboxsync $ */
2	/** @file
3	* Virtio - Virtio Common Functions (VRing, VQueue, Virtio PCI)
4	*/
5
6	/*
7	* Copyright (C) 2009-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_VIRTIO
23
24	#include <iprt/param.h>
25	#include <iprt/uuid.h>
26	#include <VBox/vmm/pdmdev.h>
27	#include "Virtio.h"
28
29	#define INSTANCE(pState) pState->szInstance
30	#define IFACE_TO_STATE(pIface, ifaceName) ((VPCISTATE )((char)pIface - RT_OFFSETOF(VPCISTATE, ifaceName)))
31
32	#ifdef LOG_ENABLED
33	# define QUEUENAME(s, q) (q->pcszName)
34	#endif
35
36
37
38	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
39
40	//RT_C_DECLS_BEGIN
41	//RT_C_DECLS_END
42
43
44	static void vqueueReset(PVQUEUE pQueue)
45	{
46	pQueue->VRing.addrDescriptors = 0;
47	pQueue->VRing.addrAvail = 0;
48	pQueue->VRing.addrUsed = 0;
49	pQueue->uNextAvailIndex = 0;
50	pQueue->uNextUsedIndex = 0;
51	pQueue->uPageNumber = 0;
52	}
53
54	static void vqueueInit(PVQUEUE pQueue, uint32_t uPageNumber)
55	{
56	pQueue->VRing.addrDescriptors = (uint64_t)uPageNumber << PAGE_SHIFT;
57	pQueue->VRing.addrAvail = pQueue->VRing.addrDescriptors
58	+ sizeof(VRINGDESC) * pQueue->VRing.uSize;
59	pQueue->VRing.addrUsed = RT_ALIGN(
60	pQueue->VRing.addrAvail + RT_OFFSETOF(VRINGAVAIL, auRing[pQueue->VRing.uSize]),
61	PAGE_SIZE); /* The used ring must start from the next page. */
62	pQueue->uNextAvailIndex = 0;
63	pQueue->uNextUsedIndex = 0;
64	}
65
66	// void vqueueElemFree(PVQUEUEELEM pElem)
67	// {
68	// }
69
70	void vringReadDesc(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex, PVRINGDESC pDesc)
71	{
72	//Log(("%s vringReadDesc: ring=%p idx=%u\n", INSTANCE(pState), pVRing, uIndex));
73	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
74	pVRing->addrDescriptors + sizeof(VRINGDESC) * (uIndex % pVRing->uSize),
75	pDesc, sizeof(VRINGDESC));
76	}
77
78	uint16_t vringReadAvail(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex)
79	{
80	uint16_t tmp;
81
82	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
83	pVRing->addrAvail + RT_OFFSETOF(VRINGAVAIL, auRing[uIndex % pVRing->uSize]),
84	&tmp, sizeof(tmp));
85	return tmp;
86	}
87
88	uint16_t vringReadAvailFlags(PVPCISTATE pState, PVRING pVRing)
89	{
90	uint16_t tmp;
91
92	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
93	pVRing->addrAvail + RT_OFFSETOF(VRINGAVAIL, uFlags),
94	&tmp, sizeof(tmp));
95	return tmp;
96	}
97
98	void vringSetNotification(PVPCISTATE pState, PVRING pVRing, bool fEnabled)
99	{
100	uint16_t tmp;
101
102	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
103	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uFlags),
104	&tmp, sizeof(tmp));
105
106	if (fEnabled)
107	tmp &= ~ VRINGUSED_F_NO_NOTIFY;
108	else
109	tmp \|= VRINGUSED_F_NO_NOTIFY;
110
111	PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns),
112	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uFlags),
113	&tmp, sizeof(tmp));
114	}
115
116	bool vqueueSkip(PVPCISTATE pState, PVQUEUE pQueue)
117	{
118	if (vqueueIsEmpty(pState, pQueue))
119	return false;
120
121	Log2(("%s vqueueSkip: %s avail_idx=%u\n", INSTANCE(pState),
122	QUEUENAME(pState, pQueue), pQueue->uNextAvailIndex));
123	pQueue->uNextAvailIndex++;
124	return true;
125	}
126
127	bool vqueueGet(PVPCISTATE pState, PVQUEUE pQueue, PVQUEUEELEM pElem, bool fRemove)
128	{
129	if (vqueueIsEmpty(pState, pQueue))
130	return false;
131
132	pElem->nIn = pElem->nOut = 0;
133
134	Log2(("%s vqueueGet: %s avail_idx=%u\n", INSTANCE(pState),
135	QUEUENAME(pState, pQueue), pQueue->uNextAvailIndex));
136
137	VRINGDESC desc;
138	uint16_t idx = vringReadAvail(pState, &pQueue->VRing, pQueue->uNextAvailIndex);
139	if (fRemove)
140	pQueue->uNextAvailIndex++;
141	pElem->uIndex = idx;
142	do
143	{
144	VQUEUESEG *pSeg;
145
146	/*
147	* Malicious guests may try to trick us into writing beyond aSegsIn or
148	* aSegsOut boundaries by linking several descriptors into a loop. We
149	* cannot possibly get a sequence of linked descriptors exceeding the
150	* total number of descriptors in the ring (see @bugref{8620}).
151	*/
152	if (pElem->nIn + pElem->nOut >= VRING_MAX_SIZE)
153	{
154	static volatile uint32_t s_cMessages = 0;
155	static volatile uint32_t s_cThreshold = 1;
156	if (ASMAtomicIncU32(&s_cMessages) == ASMAtomicReadU32(&s_cThreshold))
157	{
158	LogRel(("%s: too many linked descriptors; check if the guest arranges descriptors in a loop.\n",
159	INSTANCE(pState)));
160	if (ASMAtomicReadU32(&s_cMessages) != 1)
161	LogRel(("%s: (the above error has occured %u times so far)\n",
162	INSTANCE(pState), ASMAtomicReadU32(&s_cMessages)));
163	ASMAtomicWriteU32(&s_cThreshold, ASMAtomicReadU32(&s_cThreshold) * 10);
164	}
165	break;
166	}
167
168	vringReadDesc(pState, &pQueue->VRing, idx, &desc);
169	if (desc.u16Flags & VRINGDESC_F_WRITE)
170	{
171	Log2(("%s vqueueGet: %s IN seg=%u desc_idx=%u addr=%p cb=%u\n", INSTANCE(pState),
172	QUEUENAME(pState, pQueue), pElem->nIn, idx, desc.u64Addr, desc.uLen));
173	pSeg = &pElem->aSegsIn[pElem->nIn++];
174	}
175	else
176	{
177	Log2(("%s vqueueGet: %s OUT seg=%u desc_idx=%u addr=%p cb=%u\n", INSTANCE(pState),
178	QUEUENAME(pState, pQueue), pElem->nOut, idx, desc.u64Addr, desc.uLen));
179	pSeg = &pElem->aSegsOut[pElem->nOut++];
180	}
181
182	pSeg->addr = desc.u64Addr;
183	pSeg->cb = desc.uLen;
184	pSeg->pv = NULL;
185
186	idx = desc.u16Next;
187	} while (desc.u16Flags & VRINGDESC_F_NEXT);
188
189	Log2(("%s vqueueGet: %s head_desc_idx=%u nIn=%u nOut=%u\n", INSTANCE(pState),
190	QUEUENAME(pState, pQueue), pElem->uIndex, pElem->nIn, pElem->nOut));
191	return true;
192	}
193
194	uint16_t vringReadUsedIndex(PVPCISTATE pState, PVRING pVRing)
195	{
196	uint16_t tmp;
197	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
198	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uIndex),
199	&tmp, sizeof(tmp));
200	return tmp;
201	}
202
203	void vringWriteUsedIndex(PVPCISTATE pState, PVRING pVRing, uint16_t u16Value)
204	{
205	PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns),
206	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uIndex),
207	&u16Value, sizeof(u16Value));
208	}
209
210	void vringWriteUsedElem(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex, uint32_t uId, uint32_t uLen)
211	{
212	VRINGUSEDELEM elem;
213
214	elem.uId = uId;
215	elem.uLen = uLen;
216	PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns),
217	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, aRing[uIndex % pVRing->uSize]),
218	&elem, sizeof(elem));
219	}
220
221	void vqueuePut(PVPCISTATE pState, PVQUEUE pQueue, PVQUEUEELEM pElem, uint32_t uLen, uint32_t uReserved)
222	{
223	unsigned int i, uOffset, cbReserved = uReserved;
224
225	Log2(("%s vqueuePut: %s desc_idx=%u acb=%u\n", INSTANCE(pState),
226	QUEUENAME(pState, pQueue), pElem->uIndex, uLen));
227	for (i = uOffset = 0; i < pElem->nIn && uOffset < uLen - uReserved; i++)
228	{
229	uint32_t cbSegLen = RT_MIN(uLen - uReserved - uOffset, pElem->aSegsIn[i].cb - cbReserved);
230	if (pElem->aSegsIn[i].pv)
231	{
232	Log2(("%s vqueuePut: %s used_idx=%u seg=%u addr=%p pv=%p cb=%u acb=%u\n", INSTANCE(pState),
233	QUEUENAME(pState, pQueue), pQueue->uNextUsedIndex, i, pElem->aSegsIn[i].addr, pElem->aSegsIn[i].pv, pElem->aSegsIn[i].cb, cbSegLen));
234	PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns), pElem->aSegsIn[i].addr + cbReserved,
235	pElem->aSegsIn[i].pv, cbSegLen);
236	cbReserved = 0;
237	}
238	uOffset += cbSegLen;
239	}
240
241	Assert((uReserved + uOffset) == uLen \|\| pElem->nIn == 0);
242	Log2(("%s vqueuePut: %s used_idx=%u guest_used_idx=%u id=%u len=%u\n", INSTANCE(pState),
243	QUEUENAME(pState, pQueue), pQueue->uNextUsedIndex, vringReadUsedIndex(pState, &pQueue->VRing), pElem->uIndex, uLen));
244	vringWriteUsedElem(pState, &pQueue->VRing, pQueue->uNextUsedIndex++, pElem->uIndex, uLen);
245	}
246
247	void vqueueNotify(PVPCISTATE pState, PVQUEUE pQueue)
248	{
249	LogFlow(("%s vqueueNotify: %s availFlags=%x guestFeatures=%x vqueue is %sempty\n",
250	INSTANCE(pState), QUEUENAME(pState, pQueue),
251	vringReadAvailFlags(pState, &pQueue->VRing),
252	pState->uGuestFeatures, vqueueIsEmpty(pState, pQueue)?"":"not "));
253	if (!(vringReadAvailFlags(pState, &pQueue->VRing) & VRINGAVAIL_F_NO_INTERRUPT)
254	\|\| ((pState->uGuestFeatures & VPCI_F_NOTIFY_ON_EMPTY) && vqueueIsEmpty(pState, pQueue)))
255	{
256	int rc = vpciRaiseInterrupt(pState, VERR_INTERNAL_ERROR, VPCI_ISR_QUEUE);
257	if (RT_FAILURE(rc))
258	Log(("%s vqueueNotify: Failed to raise an interrupt (%Rrc).\n", INSTANCE(pState), rc));
259	}
260	else
261	{
262	STAM_COUNTER_INC(&pState->StatIntsSkipped);
263	}
264
265	}
266
267	void vqueueSync(PVPCISTATE pState, PVQUEUE pQueue)
268	{
269	Log2(("%s vqueueSync: %s old_used_idx=%u new_used_idx=%u\n", INSTANCE(pState),
270	QUEUENAME(pState, pQueue), vringReadUsedIndex(pState, &pQueue->VRing), pQueue->uNextUsedIndex));
271	vringWriteUsedIndex(pState, &pQueue->VRing, pQueue->uNextUsedIndex);
272	vqueueNotify(pState, pQueue);
273	}
274
275	void vpciReset(PVPCISTATE pState)
276	{
277	pState->uGuestFeatures = 0;
278	pState->uQueueSelector = 0;
279	pState->uStatus = 0;
280	pState->uISR = 0;
281
282	for (unsigned i = 0; i < pState->nQueues; i++)
283	vqueueReset(&pState->Queues[i]);
284	}
285
286
287	/**
288	* Raise interrupt.
289	*
290	* @param pState The device state structure.
291	* @param rcBusy Status code to return when the critical section is busy.
292	* @param u8IntCause Interrupt cause bit mask to set in PCI ISR port.
293	*/
294	int vpciRaiseInterrupt(VPCISTATE *pState, int rcBusy, uint8_t u8IntCause)
295	{
296	RT_NOREF_PV(rcBusy);
297	// int rc = vpciCsEnter(pState, rcBusy);
298	// if (RT_UNLIKELY(rc != VINF_SUCCESS))
299	// return rc;
300
301	STAM_COUNTER_INC(&pState->StatIntsRaised);
302	LogFlow(("%s vpciRaiseInterrupt: u8IntCause=%x\n",
303	INSTANCE(pState), u8IntCause));
304
305	pState->uISR \|= u8IntCause;
306	PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 1);
307	// vpciCsLeave(pState);
308	return VINF_SUCCESS;
309	}
310
311	/**
312	* Lower interrupt.
313	*
314	* @param pState The device state structure.
315	*/
316	static void vpciLowerInterrupt(VPCISTATE *pState)
317	{
318	LogFlow(("%s vpciLowerInterrupt\n", INSTANCE(pState)));
319	PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 0);
320	}
321
322	DECLINLINE(uint32_t) vpciGetHostFeatures(PVPCISTATE pState,
323	PFNGETHOSTFEATURES pfnGetHostFeatures)
324	{
325	return pfnGetHostFeatures(pState)
326	\| VPCI_F_NOTIFY_ON_EMPTY;
327	}
328
329	/**
330	* Port I/O Handler for IN operations.
331	*
332	* @returns VBox status code.
333	*
334	* @param pDevIns The device instance.
335	* @param pvUser Pointer to the device state structure.
336	* @param Port Port number used for the IN operation.
337	* @param pu32 Where to store the result.
338	* @param cb Number of bytes read.
339	* @param pCallbacks Pointer to the callbacks.
340	* @thread EMT
341	*/
342	int vpciIOPortIn(PPDMDEVINS pDevIns,
343	void *pvUser,
344	RTIOPORT Port,
345	uint32_t *pu32,
346	unsigned cb,
347	PCVPCIIOCALLBACKS pCallbacks)
348	{
349	VPCISTATE pState = PDMINS_2_DATA(pDevIns, VPCISTATE );
350	int rc = VINF_SUCCESS;
351	STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIORead), a);
352	RT_NOREF_PV(pvUser);
353
354	/*
355	* We probably do not need to enter critical section when reading registers
356	* as the most of them are either constant or being changed during
357	* initialization only, the exception being ISR which can be raced by all
358	* threads but I see no big harm in it. It also happens to be the most read
359	* register as it gets read in interrupt handler. By dropping cs protection
360	* here we gain the ability to deliver RX packets to the guest while TX is
361	* holding cs transmitting queued packets.
362	*
363	rc = vpciCsEnter(pState, VINF_IOM_R3_IOPORT_READ);
364	if (RT_UNLIKELY(rc != VINF_SUCCESS))
365	{
366	STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIORead), a);
367	return rc;
368	}*/
369
370	Port -= pState->IOPortBase;
371	switch (Port)
372	{
373	case VPCI_HOST_FEATURES:
374	/* Tell the guest what features we support. */
375	*pu32 = vpciGetHostFeatures(pState, pCallbacks->pfnGetHostFeatures)
376	\| VPCI_F_BAD_FEATURE;
377	break;
378
379	case VPCI_GUEST_FEATURES:
380	*pu32 = pState->uGuestFeatures;
381	break;
382
383	case VPCI_QUEUE_PFN:
384	*pu32 = pState->Queues[pState->uQueueSelector].uPageNumber;
385	break;
386
387	case VPCI_QUEUE_NUM:
388	Assert(cb == 2);
389	(uint16_t)pu32 = pState->Queues[pState->uQueueSelector].VRing.uSize;
390	break;
391
392	case VPCI_QUEUE_SEL:
393	Assert(cb == 2);
394	(uint16_t)pu32 = pState->uQueueSelector;
395	break;
396
397	case VPCI_STATUS:
398	Assert(cb == 1);
399	(uint8_t)pu32 = pState->uStatus;
400	break;
401
402	case VPCI_ISR:
403	Assert(cb == 1);
404	(uint8_t)pu32 = pState->uISR;
405	pState->uISR = 0; /* read clears all interrupts */
406	vpciLowerInterrupt(pState);
407	break;
408
409	default:
410	if (Port >= VPCI_CONFIG)
411	rc = pCallbacks->pfnGetConfig(pState, Port - VPCI_CONFIG, cb, pu32);
412	else
413	{
414	*pu32 = 0xFFFFFFFF;
415	rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortIn: no valid port at offset port=%RTiop cb=%08x\n",
416	INSTANCE(pState), Port, cb);
417	}
418	break;
419	}
420	Log3(("%s vpciIOPortIn: At %RTiop in %0x\n", INSTANCE(pState), Port, cb2, *pu32));
421	STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIORead), a);
422	//vpciCsLeave(pState);
423	return rc;
424	}
425
426
427	/**
428	* Port I/O Handler for OUT operations.
429	*
430	* @returns VBox status code.
431	*
432	* @param pDevIns The device instance.
433	* @param pvUser User argument.
434	* @param Port Port number used for the IN operation.
435	* @param u32 The value to output.
436	* @param cb The value size in bytes.
437	* @param pCallbacks Pointer to the callbacks.
438	* @thread EMT
439	*/
440	int vpciIOPortOut(PPDMDEVINS pDevIns,
441	void *pvUser,
442	RTIOPORT Port,
443	uint32_t u32,
444	unsigned cb,
445	PCVPCIIOCALLBACKS pCallbacks)
446	{
447	VPCISTATE pState = PDMINS_2_DATA(pDevIns, VPCISTATE );
448	int rc = VINF_SUCCESS;
449	bool fHasBecomeReady;
450	STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIOWrite), a);
451	RT_NOREF_PV(pvUser);
452
453	Port -= pState->IOPortBase;
454	Log3(("%s virtioIOPortOut: At %RTiop out %0x\n", INSTANCE(pState), Port, cb2, u32));
455
456	switch (Port)
457	{
458	case VPCI_GUEST_FEATURES:
459	/* Check if the guest negotiates properly, fall back to basics if it does not. */
460	if (VPCI_F_BAD_FEATURE & u32)
461	{
462	Log(("%s WARNING! Guest failed to negotiate properly (guest=%x)\n",
463	INSTANCE(pState), u32));
464	pState->uGuestFeatures = pCallbacks->pfnGetHostMinimalFeatures(pState);
465	}
466	/* The guest may potentially desire features we don't support! */
467	else if (~vpciGetHostFeatures(pState, pCallbacks->pfnGetHostFeatures) & u32)
468	{
469	Log(("%s Guest asked for features host does not support! (host=%x guest=%x)\n",
470	INSTANCE(pState),
471	vpciGetHostFeatures(pState, pCallbacks->pfnGetHostFeatures), u32));
472	pState->uGuestFeatures =
473	vpciGetHostFeatures(pState, pCallbacks->pfnGetHostFeatures);
474	}
475	else
476	pState->uGuestFeatures = u32;
477	pCallbacks->pfnSetHostFeatures(pState, pState->uGuestFeatures);
478	break;
479
480	case VPCI_QUEUE_PFN:
481	/*
482	* The guest is responsible for allocating the pages for queues,
483	* here it provides us with the page number of descriptor table.
484	* Note that we provide the size of the queue to the guest via
485	* VIRTIO_PCI_QUEUE_NUM.
486	*/
487	pState->Queues[pState->uQueueSelector].uPageNumber = u32;
488	if (u32)
489	vqueueInit(&pState->Queues[pState->uQueueSelector], u32);
490	else
491	rc = pCallbacks->pfnReset(pState);
492	break;
493
494	case VPCI_QUEUE_SEL:
495	Assert(cb == 2);
496	u32 &= 0xFFFF;
497	if (u32 < pState->nQueues)
498	pState->uQueueSelector = u32;
499	else
500	Log3(("%s vpciIOPortOut: Invalid queue selector %08x\n", INSTANCE(pState), u32));
501	break;
502
503	case VPCI_QUEUE_NOTIFY:
504	#ifdef IN_RING3
505	Assert(cb == 2);
506	u32 &= 0xFFFF;
507	if (u32 < pState->nQueues)
508	if (pState->Queues[u32].VRing.addrDescriptors)
509	{
510	// rc = vpciCsEnter(pState, VERR_SEM_BUSY);
511	// if (RT_LIKELY(rc == VINF_SUCCESS))
512	// {
513	pState->Queues[u32].pfnCallback(pState, &pState->Queues[u32]);
514	// vpciCsLeave(pState);
515	// }
516	}
517	else
518	Log(("%s The queue (#%d) being notified has not been initialized.\n",
519	INSTANCE(pState), u32));
520	else
521	Log(("%s Invalid queue number (%d)\n", INSTANCE(pState), u32));
522	#else
523	rc = VINF_IOM_R3_IOPORT_WRITE;
524	#endif
525	break;
526
527	case VPCI_STATUS:
528	Assert(cb == 1);
529	u32 &= 0xFF;
530	fHasBecomeReady = !(pState->uStatus & VPCI_STATUS_DRV_OK) && (u32 & VPCI_STATUS_DRV_OK);
531	pState->uStatus = u32;
532	/* Writing 0 to the status port triggers device reset. */
533	if (u32 == 0)
534	rc = pCallbacks->pfnReset(pState);
535	else if (fHasBecomeReady)
536	pCallbacks->pfnReady(pState);
537	break;
538
539	default:
540	if (Port >= VPCI_CONFIG)
541	rc = pCallbacks->pfnSetConfig(pState, Port - VPCI_CONFIG, cb, &u32);
542	else
543	rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortOut: no valid port at offset Port=%RTiop cb=%08x\n",
544	INSTANCE(pState), Port, cb);
545	break;
546	}
547
548	STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIOWrite), a);
549	return rc;
550	}
551
552	#ifdef IN_RING3
553
554	/**
555	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
556	*/
557	void vpciQueryInterface(struct PDMIBASE pInterface, const char *pszIID)
558	{
559	VPCISTATE *pThis = IFACE_TO_STATE(pInterface, IBase);
560	Assert(&pThis->IBase == pInterface);
561
562	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
563	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
564	return NULL;
565	}
566
567	/**
568	* Gets the pointer to the status LED of a unit.
569	*
570	* @returns VBox status code.
571	* @param pInterface Pointer to the interface structure.
572	* @param iLUN The unit which status LED we desire.
573	* @param ppLed Where to store the LED pointer.
574	* @thread EMT
575	*/
576	static DECLCALLBACK(int) vpciQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
577	{
578	VPCISTATE *pState = IFACE_TO_STATE(pInterface, ILeds);
579	int rc = VERR_PDM_LUN_NOT_FOUND;
580
581	if (iLUN == 0)
582	{
583	*ppLed = &pState->led;
584	rc = VINF_SUCCESS;
585	}
586	return rc;
587	}
588
589	/**
590	* Turns on/off the write status LED.
591	*
592	* @returns VBox status code.
593	* @param pState Pointer to the device state structure.
594	* @param fOn New LED state.
595	*/
596	void vpciSetWriteLed(PVPCISTATE pState, bool fOn)
597	{
598	LogFlow(("%s vpciSetWriteLed: %s\n", INSTANCE(pState), fOn?"on":"off"));
599	if (fOn)
600	pState->led.Asserted.s.fWriting = pState->led.Actual.s.fWriting = 1;
601	else
602	pState->led.Actual.s.fWriting = fOn;
603	}
604
605	/**
606	* Turns on/off the read status LED.
607	*
608	* @returns VBox status code.
609	* @param pState Pointer to the device state structure.
610	* @param fOn New LED state.
611	*/
612	void vpciSetReadLed(PVPCISTATE pState, bool fOn)
613	{
614	LogFlow(("%s vpciSetReadLed: %s\n", INSTANCE(pState), fOn?"on":"off"));
615	if (fOn)
616	pState->led.Asserted.s.fReading = pState->led.Actual.s.fReading = 1;
617	else
618	pState->led.Actual.s.fReading = fOn;
619	}
620
621
622	#if 0 /* unused */
623	/**
624	* Sets 32-bit register in PCI configuration space.
625	* @param refPciDev The PCI device.
626	* @param uOffset The register offset.
627	* @param u32Value The value to store in the register.
628	* @thread EMT
629	*/
630	DECLINLINE(void) vpciCfgSetU32(PDMPCIDEV& refPciDev, uint32_t uOffset, uint32_t u32Value)
631	{
632	Assert(uOffset+sizeof(u32Value) <= sizeof(refPciDev.config));
633	(uint32_t)&refPciDev.config[uOffset] = u32Value;
634	}
635	#endif /* unused */
636
637
638	#ifdef DEBUG
639	static void vpciDumpState(PVPCISTATE pState, const char *pcszCaller)
640	{
641	Log2(("vpciDumpState: (called from %s)\n"
642	" uGuestFeatures = 0x%08x\n"
643	" uQueueSelector = 0x%04x\n"
644	" uStatus = 0x%02x\n"
645	" uISR = 0x%02x\n",
646	pcszCaller,
647	pState->uGuestFeatures,
648	pState->uQueueSelector,
649	pState->uStatus,
650	pState->uISR));
651
652	for (unsigned i = 0; i < pState->nQueues; i++)
653	Log2((" %s queue:\n"
654	" VRing.uSize = %u\n"
655	" VRing.addrDescriptors = %p\n"
656	" VRing.addrAvail = %p\n"
657	" VRing.addrUsed = %p\n"
658	" uNextAvailIndex = %u\n"
659	" uNextUsedIndex = %u\n"
660	" uPageNumber = %x\n",
661	pState->Queues[i].pcszName,
662	pState->Queues[i].VRing.uSize,
663	pState->Queues[i].VRing.addrDescriptors,
664	pState->Queues[i].VRing.addrAvail,
665	pState->Queues[i].VRing.addrUsed,
666	pState->Queues[i].uNextAvailIndex,
667	pState->Queues[i].uNextUsedIndex,
668	pState->Queues[i].uPageNumber));
669	}
670	#else
671	# define vpciDumpState(x, s) do {} while (0)
672	#endif
673
674	/**
675	* Saves the state of device.
676	*
677	* @returns VBox status code.
678	* @param pDevIns The device instance.
679	* @param pSSM The handle to the saved state.
680	*/
681	int vpciSaveExec(PVPCISTATE pState, PSSMHANDLE pSSM)
682	{
683	int rc;
684
685	vpciDumpState(pState, "vpciSaveExec");
686
687	rc = SSMR3PutU32(pSSM, pState->uGuestFeatures);
688	AssertRCReturn(rc, rc);
689	rc = SSMR3PutU16(pSSM, pState->uQueueSelector);
690	AssertRCReturn(rc, rc);
691	rc = SSMR3PutU8( pSSM, pState->uStatus);
692	AssertRCReturn(rc, rc);
693	rc = SSMR3PutU8( pSSM, pState->uISR);
694	AssertRCReturn(rc, rc);
695
696	/* Save queue states */
697	rc = SSMR3PutU32(pSSM, pState->nQueues);
698	AssertRCReturn(rc, rc);
699	for (unsigned i = 0; i < pState->nQueues; i++)
700	{
701	rc = SSMR3PutU16(pSSM, pState->Queues[i].VRing.uSize);
702	AssertRCReturn(rc, rc);
703	rc = SSMR3PutU32(pSSM, pState->Queues[i].uPageNumber);
704	AssertRCReturn(rc, rc);
705	rc = SSMR3PutU16(pSSM, pState->Queues[i].uNextAvailIndex);
706	AssertRCReturn(rc, rc);
707	rc = SSMR3PutU16(pSSM, pState->Queues[i].uNextUsedIndex);
708	AssertRCReturn(rc, rc);
709	}
710
711	return VINF_SUCCESS;
712	}
713
714	/**
715	* Loads a saved device state.
716	*
717	* @returns VBox status code.
718	* @param pDevIns The device instance.
719	* @param pSSM The handle to the saved state.
720	* @param uVersion The data unit version number.
721	* @param uPass The data pass.
722	*/
723	int vpciLoadExec(PVPCISTATE pState, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass, uint32_t nQueues)
724	{
725	int rc;
726
727	if (uPass == SSM_PASS_FINAL)
728	{
729	/* Restore state data */
730	rc = SSMR3GetU32(pSSM, &pState->uGuestFeatures);
731	AssertRCReturn(rc, rc);
732	rc = SSMR3GetU16(pSSM, &pState->uQueueSelector);
733	AssertRCReturn(rc, rc);
734	rc = SSMR3GetU8( pSSM, &pState->uStatus);
735	AssertRCReturn(rc, rc);
736	rc = SSMR3GetU8( pSSM, &pState->uISR);
737	AssertRCReturn(rc, rc);
738
739	/* Restore queues */
740	if (uVersion > VIRTIO_SAVEDSTATE_VERSION_3_1_BETA1)
741	{
742	rc = SSMR3GetU32(pSSM, &pState->nQueues);
743	AssertRCReturn(rc, rc);
744	}
745	else
746	pState->nQueues = nQueues;
747	for (unsigned i = 0; i < pState->nQueues; i++)
748	{
749	rc = SSMR3GetU16(pSSM, &pState->Queues[i].VRing.uSize);
750	AssertRCReturn(rc, rc);
751	rc = SSMR3GetU32(pSSM, &pState->Queues[i].uPageNumber);
752	AssertRCReturn(rc, rc);
753
754	if (pState->Queues[i].uPageNumber)
755	vqueueInit(&pState->Queues[i], pState->Queues[i].uPageNumber);
756
757	rc = SSMR3GetU16(pSSM, &pState->Queues[i].uNextAvailIndex);
758	AssertRCReturn(rc, rc);
759	rc = SSMR3GetU16(pSSM, &pState->Queues[i].uNextUsedIndex);
760	AssertRCReturn(rc, rc);
761	}
762	}
763
764	vpciDumpState(pState, "vpciLoadExec");
765
766	return VINF_SUCCESS;
767	}
768
769	/**
770	* Set PCI configuration space registers.
771	*
772	* @param pci Reference to PCI device structure.
773	* @param uDeviceId VirtiO Device Id
774	* @param uClass Class of PCI device (network, etc)
775	* @thread EMT
776	*/
777	static DECLCALLBACK(void) vpciConfigure(PDMPCIDEV& pci,
778	uint16_t uDeviceId,
779	uint16_t uClass)
780	{
781	/* Configure PCI Device, assume 32-bit mode ******************************/
782	PCIDevSetVendorId(&pci, DEVICE_PCI_VENDOR_ID);
783	PCIDevSetDeviceId(&pci, DEVICE_PCI_BASE_ID + uDeviceId);
784	PDMPciDevSetWord(&pci, VBOX_PCI_SUBSYSTEM_VENDOR_ID, DEVICE_PCI_SUBSYSTEM_VENDOR_ID);
785	PDMPciDevSetWord(&pci, VBOX_PCI_SUBSYSTEM_ID, DEVICE_PCI_SUBSYSTEM_BASE_ID + uDeviceId);
786
787	/* ABI version, must be equal 0 as of 2.6.30 kernel. */
788	PDMPciDevSetByte(&pci, VBOX_PCI_REVISION_ID, 0x00);
789	/* Ethernet adapter */
790	PDMPciDevSetByte(&pci, VBOX_PCI_CLASS_PROG, 0x00);
791	PDMPciDevSetWord(&pci, VBOX_PCI_CLASS_DEVICE, uClass);
792	/* Interrupt Pin: INTA# */
793	PDMPciDevSetByte(&pci, VBOX_PCI_INTERRUPT_PIN, 0x01);
794
795	#ifdef VBOX_WITH_MSI_DEVICES
796	PCIDevSetCapabilityList(&pci, 0x80);
797	PCIDevSetStatus( &pci, VBOX_PCI_STATUS_CAP_LIST);
798	#endif
799	}
800
801	#ifdef VBOX_WITH_STATISTICS
802	/* WARNING! This function must never be used in multithreaded context! */
803	static const char vpciCounter(const char pszDevFmt,
804	const char *pszCounter)
805	{
806	static char s_szCounterName[80];
807
808	RTStrPrintf(s_szCounterName, sizeof(s_szCounterName),
809	"/Devices/%s/%s", pszDevFmt, pszCounter);
810
811	return s_szCounterName;
812	}
813	#endif
814
815	/// @todo header
816	int vpciConstruct(PPDMDEVINS pDevIns, VPCISTATE *pState,
817	int iInstance, const char *pcszNameFmt,
818	uint16_t uDeviceId, uint16_t uClass,
819	uint32_t nQueues)
820	{
821	/* Init handles and log related stuff. */
822	RTStrPrintf(pState->szInstance, sizeof(pState->szInstance),
823	pcszNameFmt, iInstance);
824
825	pState->pDevInsR3 = pDevIns;
826	pState->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
827	pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
828	pState->led.u32Magic = PDMLED_MAGIC;
829
830	pState->ILeds.pfnQueryStatusLed = vpciQueryStatusLed;
831
832	/* Initialize critical section. */
833	int rc = PDMDevHlpCritSectInit(pDevIns, &pState->cs, RT_SRC_POS, "%s", pState->szInstance);
834	if (RT_FAILURE(rc))
835	return rc;
836
837	/* Set PCI config registers */
838	vpciConfigure(pState->pciDevice, uDeviceId, uClass);
839	/* Register PCI device */
840	rc = PDMDevHlpPCIRegister(pDevIns, &pState->pciDevice);
841	if (RT_FAILURE(rc))
842	return rc;
843
844	#ifdef VBOX_WITH_MSI_DEVICES
845	#if 0
846	{
847	PDMMSIREG aMsiReg;
848
849	RT_ZERO(aMsiReg);
850	aMsiReg.cMsixVectors = 1;
851	aMsiReg.iMsixCapOffset = 0x80;
852	aMsiReg.iMsixNextOffset = 0x0;
853	aMsiReg.iMsixBar = 0;
854	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &aMsiReg);
855	if (RT_FAILURE (rc))
856	PCIDevSetCapabilityList(&pState->pciDevice, 0x0);
857	}
858	#endif
859	#endif
860
861	/* Status driver */
862	PPDMIBASE pBase;
863	rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pState->IBase, &pBase, "Status Port");
864	if (RT_FAILURE(rc))
865	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the status LUN"));
866	pState->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
867
868	pState->nQueues = nQueues;
869
870	#if defined(VBOX_WITH_STATISTICS)
871	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in GC", vpciCounter(pcszNameFmt, "IO/ReadGC"), iInstance);
872	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in HC", vpciCounter(pcszNameFmt, "IO/ReadHC"), iInstance);
873	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in GC", vpciCounter(pcszNameFmt, "IO/WriteGC"), iInstance);
874	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in HC", vpciCounter(pcszNameFmt, "IO/WriteHC"), iInstance);
875	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsRaised, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of raised interrupts", vpciCounter(pcszNameFmt, "Interrupts/Raised"), iInstance);
876	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsSkipped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of skipped interrupts", vpciCounter(pcszNameFmt, "Interrupts/Skipped"), iInstance);
877	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatCsGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling CS wait in GC", vpciCounter(pcszNameFmt, "Cs/CsGC"), iInstance);
878	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatCsHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling CS wait in HC", vpciCounter(pcszNameFmt, "Cs/CsHC"), iInstance);
879	#endif /* VBOX_WITH_STATISTICS */
880
881	return rc;
882	}
883
884	/**
885	* Destruct PCI-related part of device.
886	*
887	* We need to free non-VM resources only.
888	*
889	* @returns VBox status code.
890	* @param pState The device state structure.
891	*/
892	int vpciDestruct(VPCISTATE* pState)
893	{
894	Log(("%s Destroying PCI instance\n", INSTANCE(pState)));
895
896	if (PDMCritSectIsInitialized(&pState->cs))
897	PDMR3CritSectDelete(&pState->cs);
898
899	return VINF_SUCCESS;
900	}
901
902	/**
903	* Device relocation callback.
904	*
905	* When this callback is called the device instance data, and if the
906	* device have a GC component, is being relocated, or/and the selectors
907	* have been changed. The device must use the chance to perform the
908	* necessary pointer relocations and data updates.
909	*
910	* Before the GC code is executed the first time, this function will be
911	* called with a 0 delta so GC pointer calculations can be one in one place.
912	*
913	* @param pDevIns Pointer to the device instance.
914	* @param offDelta The relocation delta relative to the old location.
915	*
916	* @remark A relocation CANNOT fail.
917	*/
918	void vpciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
919	{
920	RT_NOREF(offDelta);
921	VPCISTATE pState = PDMINS_2_DATA(pDevIns, VPCISTATE);
922	pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
923	// TBD
924	}
925
926	PVQUEUE vpciAddQueue(VPCISTATE* pState, unsigned uSize, PFNVPCIQUEUECALLBACK pfnCallback, const char *pcszName)
927	{
928	PVQUEUE pQueue = NULL;
929	/* Find an empty queue slot */
930	for (unsigned i = 0; i < pState->nQueues; i++)
931	{
932	if (pState->Queues[i].VRing.uSize == 0)
933	{
934	pQueue = &pState->Queues[i];
935	break;
936	}
937	}
938
939	if (!pQueue)
940	{
941	Log(("%s Too many queues being added, no empty slots available!\n", INSTANCE(pState)));
942	}
943	else
944	{
945	pQueue->VRing.uSize = uSize;
946	pQueue->VRing.addrDescriptors = 0;
947	pQueue->uPageNumber = 0;
948	pQueue->pfnCallback = pfnCallback;
949	pQueue->pcszName = pcszName;
950	}
951
952	return pQueue;
953	}
954
955	#endif /* IN_RING3 */
956
957	#endif /* VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/VirtIO/Virtio.cpp@ 64809

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