Virtio.cpp@ 64810

Last change on this file since 64810 was 64810, checked in by vboxsync, 8 years ago
Devices/Virtio: vqueuePut - don't call PDMDevHlpPCIPhysWrite with zero cbSegLen, it asserts that down the call chain.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 33.3 KB

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1	/* $Id: Virtio.cpp 64810 2016-12-08 13:57:47Z vboxsync $ */
2	/** @file
3	* Virtio - Virtio Common Functions (VRing, VQueue, Virtio PCI)
4	*/
5
6	/*
7	* Copyright (C) 2009-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_VIRTIO
23
24	#include <iprt/param.h>
25	#include <iprt/uuid.h>
26	#include <VBox/vmm/pdmdev.h>
27	#include "Virtio.h"
28
29	#define INSTANCE(pState) pState->szInstance
30	#define IFACE_TO_STATE(pIface, ifaceName) ((VPCISTATE )((char)pIface - RT_OFFSETOF(VPCISTATE, ifaceName)))
31
32	#ifdef LOG_ENABLED
33	# define QUEUENAME(s, q) (q->pcszName)
34	#endif
35
36
37
38	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
39
40	//RT_C_DECLS_BEGIN
41	//RT_C_DECLS_END
42
43
44	static void vqueueReset(PVQUEUE pQueue)
45	{
46	pQueue->VRing.addrDescriptors = 0;
47	pQueue->VRing.addrAvail = 0;
48	pQueue->VRing.addrUsed = 0;
49	pQueue->uNextAvailIndex = 0;
50	pQueue->uNextUsedIndex = 0;
51	pQueue->uPageNumber = 0;
52	}
53
54	static void vqueueInit(PVQUEUE pQueue, uint32_t uPageNumber)
55	{
56	pQueue->VRing.addrDescriptors = (uint64_t)uPageNumber << PAGE_SHIFT;
57	pQueue->VRing.addrAvail = pQueue->VRing.addrDescriptors
58	+ sizeof(VRINGDESC) * pQueue->VRing.uSize;
59	pQueue->VRing.addrUsed = RT_ALIGN(
60	pQueue->VRing.addrAvail + RT_OFFSETOF(VRINGAVAIL, auRing[pQueue->VRing.uSize]),
61	PAGE_SIZE); /* The used ring must start from the next page. */
62	pQueue->uNextAvailIndex = 0;
63	pQueue->uNextUsedIndex = 0;
64	}
65
66	// void vqueueElemFree(PVQUEUEELEM pElem)
67	// {
68	// }
69
70	void vringReadDesc(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex, PVRINGDESC pDesc)
71	{
72	//Log(("%s vringReadDesc: ring=%p idx=%u\n", INSTANCE(pState), pVRing, uIndex));
73	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
74	pVRing->addrDescriptors + sizeof(VRINGDESC) * (uIndex % pVRing->uSize),
75	pDesc, sizeof(VRINGDESC));
76	}
77
78	uint16_t vringReadAvail(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex)
79	{
80	uint16_t tmp;
81
82	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
83	pVRing->addrAvail + RT_OFFSETOF(VRINGAVAIL, auRing[uIndex % pVRing->uSize]),
84	&tmp, sizeof(tmp));
85	return tmp;
86	}
87
88	uint16_t vringReadAvailFlags(PVPCISTATE pState, PVRING pVRing)
89	{
90	uint16_t tmp;
91
92	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
93	pVRing->addrAvail + RT_OFFSETOF(VRINGAVAIL, uFlags),
94	&tmp, sizeof(tmp));
95	return tmp;
96	}
97
98	void vringSetNotification(PVPCISTATE pState, PVRING pVRing, bool fEnabled)
99	{
100	uint16_t tmp;
101
102	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
103	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uFlags),
104	&tmp, sizeof(tmp));
105
106	if (fEnabled)
107	tmp &= ~ VRINGUSED_F_NO_NOTIFY;
108	else
109	tmp \|= VRINGUSED_F_NO_NOTIFY;
110
111	PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns),
112	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uFlags),
113	&tmp, sizeof(tmp));
114	}
115
116	bool vqueueSkip(PVPCISTATE pState, PVQUEUE pQueue)
117	{
118	if (vqueueIsEmpty(pState, pQueue))
119	return false;
120
121	Log2(("%s vqueueSkip: %s avail_idx=%u\n", INSTANCE(pState),
122	QUEUENAME(pState, pQueue), pQueue->uNextAvailIndex));
123	pQueue->uNextAvailIndex++;
124	return true;
125	}
126
127	bool vqueueGet(PVPCISTATE pState, PVQUEUE pQueue, PVQUEUEELEM pElem, bool fRemove)
128	{
129	if (vqueueIsEmpty(pState, pQueue))
130	return false;
131
132	pElem->nIn = pElem->nOut = 0;
133
134	Log2(("%s vqueueGet: %s avail_idx=%u\n", INSTANCE(pState),
135	QUEUENAME(pState, pQueue), pQueue->uNextAvailIndex));
136
137	VRINGDESC desc;
138	uint16_t idx = vringReadAvail(pState, &pQueue->VRing, pQueue->uNextAvailIndex);
139	if (fRemove)
140	pQueue->uNextAvailIndex++;
141	pElem->uIndex = idx;
142	do
143	{
144	VQUEUESEG *pSeg;
145
146	/*
147	* Malicious guests may try to trick us into writing beyond aSegsIn or
148	* aSegsOut boundaries by linking several descriptors into a loop. We
149	* cannot possibly get a sequence of linked descriptors exceeding the
150	* total number of descriptors in the ring (see @bugref{8620}).
151	*/
152	if (pElem->nIn + pElem->nOut >= VRING_MAX_SIZE)
153	{
154	static volatile uint32_t s_cMessages = 0;
155	static volatile uint32_t s_cThreshold = 1;
156	if (ASMAtomicIncU32(&s_cMessages) == ASMAtomicReadU32(&s_cThreshold))
157	{
158	LogRel(("%s: too many linked descriptors; check if the guest arranges descriptors in a loop.\n",
159	INSTANCE(pState)));
160	if (ASMAtomicReadU32(&s_cMessages) != 1)
161	LogRel(("%s: (the above error has occured %u times so far)\n",
162	INSTANCE(pState), ASMAtomicReadU32(&s_cMessages)));
163	ASMAtomicWriteU32(&s_cThreshold, ASMAtomicReadU32(&s_cThreshold) * 10);
164	}
165	break;
166	}
167
168	vringReadDesc(pState, &pQueue->VRing, idx, &desc);
169	if (desc.u16Flags & VRINGDESC_F_WRITE)
170	{
171	Log2(("%s vqueueGet: %s IN seg=%u desc_idx=%u addr=%p cb=%u\n", INSTANCE(pState),
172	QUEUENAME(pState, pQueue), pElem->nIn, idx, desc.u64Addr, desc.uLen));
173	pSeg = &pElem->aSegsIn[pElem->nIn++];
174	}
175	else
176	{
177	Log2(("%s vqueueGet: %s OUT seg=%u desc_idx=%u addr=%p cb=%u\n", INSTANCE(pState),
178	QUEUENAME(pState, pQueue), pElem->nOut, idx, desc.u64Addr, desc.uLen));
179	pSeg = &pElem->aSegsOut[pElem->nOut++];
180	}
181
182	pSeg->addr = desc.u64Addr;
183	pSeg->cb = desc.uLen;
184	pSeg->pv = NULL;
185
186	idx = desc.u16Next;
187	} while (desc.u16Flags & VRINGDESC_F_NEXT);
188
189	Log2(("%s vqueueGet: %s head_desc_idx=%u nIn=%u nOut=%u\n", INSTANCE(pState),
190	QUEUENAME(pState, pQueue), pElem->uIndex, pElem->nIn, pElem->nOut));
191	return true;
192	}
193
194	uint16_t vringReadUsedIndex(PVPCISTATE pState, PVRING pVRing)
195	{
196	uint16_t tmp;
197	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
198	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uIndex),
199	&tmp, sizeof(tmp));
200	return tmp;
201	}
202
203	void vringWriteUsedIndex(PVPCISTATE pState, PVRING pVRing, uint16_t u16Value)
204	{
205	PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns),
206	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uIndex),
207	&u16Value, sizeof(u16Value));
208	}
209
210	void vringWriteUsedElem(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex, uint32_t uId, uint32_t uLen)
211	{
212	VRINGUSEDELEM elem;
213
214	elem.uId = uId;
215	elem.uLen = uLen;
216	PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns),
217	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, aRing[uIndex % pVRing->uSize]),
218	&elem, sizeof(elem));
219	}
220
221	void vqueuePut(PVPCISTATE pState, PVQUEUE pQueue, PVQUEUEELEM pElem, uint32_t uLen, uint32_t uReserved)
222	{
223	unsigned int i, uOffset, cbReserved = uReserved;
224
225	Log2(("%s vqueuePut: %s desc_idx=%u acb=%u\n", INSTANCE(pState),
226	QUEUENAME(pState, pQueue), pElem->uIndex, uLen));
227	for (i = uOffset = 0; i < pElem->nIn && uOffset < uLen - uReserved; i++)
228	{
229	uint32_t cbSegLen = RT_MIN(uLen - uReserved - uOffset, pElem->aSegsIn[i].cb - cbReserved);
230	if (pElem->aSegsIn[i].pv)
231	{
232	if (cbSegLen > 0)
233	{
234	Log2(("%s vqueuePut: %s used_idx=%u seg=%u addr=%p pv=%p cb=%u acb=%u\n", INSTANCE(pState),
235	QUEUENAME(pState, pQueue), pQueue->uNextUsedIndex, i, pElem->aSegsIn[i].addr, pElem->aSegsIn[i].pv, pElem->aSegsIn[i].cb, cbSegLen));
236	PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns), pElem->aSegsIn[i].addr + cbReserved,
237	pElem->aSegsIn[i].pv, cbSegLen);
238	}
239	cbReserved = 0;
240	}
241	uOffset += cbSegLen;
242	}
243
244	Assert((uReserved + uOffset) == uLen \|\| pElem->nIn == 0);
245	Log2(("%s vqueuePut: %s used_idx=%u guest_used_idx=%u id=%u len=%u\n", INSTANCE(pState),
246	QUEUENAME(pState, pQueue), pQueue->uNextUsedIndex, vringReadUsedIndex(pState, &pQueue->VRing), pElem->uIndex, uLen));
247	vringWriteUsedElem(pState, &pQueue->VRing, pQueue->uNextUsedIndex++, pElem->uIndex, uLen);
248	}
249
250	void vqueueNotify(PVPCISTATE pState, PVQUEUE pQueue)
251	{
252	LogFlow(("%s vqueueNotify: %s availFlags=%x guestFeatures=%x vqueue is %sempty\n",
253	INSTANCE(pState), QUEUENAME(pState, pQueue),
254	vringReadAvailFlags(pState, &pQueue->VRing),
255	pState->uGuestFeatures, vqueueIsEmpty(pState, pQueue)?"":"not "));
256	if (!(vringReadAvailFlags(pState, &pQueue->VRing) & VRINGAVAIL_F_NO_INTERRUPT)
257	\|\| ((pState->uGuestFeatures & VPCI_F_NOTIFY_ON_EMPTY) && vqueueIsEmpty(pState, pQueue)))
258	{
259	int rc = vpciRaiseInterrupt(pState, VERR_INTERNAL_ERROR, VPCI_ISR_QUEUE);
260	if (RT_FAILURE(rc))
261	Log(("%s vqueueNotify: Failed to raise an interrupt (%Rrc).\n", INSTANCE(pState), rc));
262	}
263	else
264	{
265	STAM_COUNTER_INC(&pState->StatIntsSkipped);
266	}
267
268	}
269
270	void vqueueSync(PVPCISTATE pState, PVQUEUE pQueue)
271	{
272	Log2(("%s vqueueSync: %s old_used_idx=%u new_used_idx=%u\n", INSTANCE(pState),
273	QUEUENAME(pState, pQueue), vringReadUsedIndex(pState, &pQueue->VRing), pQueue->uNextUsedIndex));
274	vringWriteUsedIndex(pState, &pQueue->VRing, pQueue->uNextUsedIndex);
275	vqueueNotify(pState, pQueue);
276	}
277
278	void vpciReset(PVPCISTATE pState)
279	{
280	pState->uGuestFeatures = 0;
281	pState->uQueueSelector = 0;
282	pState->uStatus = 0;
283	pState->uISR = 0;
284
285	for (unsigned i = 0; i < pState->nQueues; i++)
286	vqueueReset(&pState->Queues[i]);
287	}
288
289
290	/**
291	* Raise interrupt.
292	*
293	* @param pState The device state structure.
294	* @param rcBusy Status code to return when the critical section is busy.
295	* @param u8IntCause Interrupt cause bit mask to set in PCI ISR port.
296	*/
297	int vpciRaiseInterrupt(VPCISTATE *pState, int rcBusy, uint8_t u8IntCause)
298	{
299	RT_NOREF_PV(rcBusy);
300	// int rc = vpciCsEnter(pState, rcBusy);
301	// if (RT_UNLIKELY(rc != VINF_SUCCESS))
302	// return rc;
303
304	STAM_COUNTER_INC(&pState->StatIntsRaised);
305	LogFlow(("%s vpciRaiseInterrupt: u8IntCause=%x\n",
306	INSTANCE(pState), u8IntCause));
307
308	pState->uISR \|= u8IntCause;
309	PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 1);
310	// vpciCsLeave(pState);
311	return VINF_SUCCESS;
312	}
313
314	/**
315	* Lower interrupt.
316	*
317	* @param pState The device state structure.
318	*/
319	static void vpciLowerInterrupt(VPCISTATE *pState)
320	{
321	LogFlow(("%s vpciLowerInterrupt\n", INSTANCE(pState)));
322	PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 0);
323	}
324
325	DECLINLINE(uint32_t) vpciGetHostFeatures(PVPCISTATE pState,
326	PFNGETHOSTFEATURES pfnGetHostFeatures)
327	{
328	return pfnGetHostFeatures(pState)
329	\| VPCI_F_NOTIFY_ON_EMPTY;
330	}
331
332	/**
333	* Port I/O Handler for IN operations.
334	*
335	* @returns VBox status code.
336	*
337	* @param pDevIns The device instance.
338	* @param pvUser Pointer to the device state structure.
339	* @param Port Port number used for the IN operation.
340	* @param pu32 Where to store the result.
341	* @param cb Number of bytes read.
342	* @param pCallbacks Pointer to the callbacks.
343	* @thread EMT
344	*/
345	int vpciIOPortIn(PPDMDEVINS pDevIns,
346	void *pvUser,
347	RTIOPORT Port,
348	uint32_t *pu32,
349	unsigned cb,
350	PCVPCIIOCALLBACKS pCallbacks)
351	{
352	VPCISTATE pState = PDMINS_2_DATA(pDevIns, VPCISTATE );
353	int rc = VINF_SUCCESS;
354	STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIORead), a);
355	RT_NOREF_PV(pvUser);
356
357	/*
358	* We probably do not need to enter critical section when reading registers
359	* as the most of them are either constant or being changed during
360	* initialization only, the exception being ISR which can be raced by all
361	* threads but I see no big harm in it. It also happens to be the most read
362	* register as it gets read in interrupt handler. By dropping cs protection
363	* here we gain the ability to deliver RX packets to the guest while TX is
364	* holding cs transmitting queued packets.
365	*
366	rc = vpciCsEnter(pState, VINF_IOM_R3_IOPORT_READ);
367	if (RT_UNLIKELY(rc != VINF_SUCCESS))
368	{
369	STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIORead), a);
370	return rc;
371	}*/
372
373	Port -= pState->IOPortBase;
374	switch (Port)
375	{
376	case VPCI_HOST_FEATURES:
377	/* Tell the guest what features we support. */
378	*pu32 = vpciGetHostFeatures(pState, pCallbacks->pfnGetHostFeatures)
379	\| VPCI_F_BAD_FEATURE;
380	break;
381
382	case VPCI_GUEST_FEATURES:
383	*pu32 = pState->uGuestFeatures;
384	break;
385
386	case VPCI_QUEUE_PFN:
387	*pu32 = pState->Queues[pState->uQueueSelector].uPageNumber;
388	break;
389
390	case VPCI_QUEUE_NUM:
391	Assert(cb == 2);
392	(uint16_t)pu32 = pState->Queues[pState->uQueueSelector].VRing.uSize;
393	break;
394
395	case VPCI_QUEUE_SEL:
396	Assert(cb == 2);
397	(uint16_t)pu32 = pState->uQueueSelector;
398	break;
399
400	case VPCI_STATUS:
401	Assert(cb == 1);
402	(uint8_t)pu32 = pState->uStatus;
403	break;
404
405	case VPCI_ISR:
406	Assert(cb == 1);
407	(uint8_t)pu32 = pState->uISR;
408	pState->uISR = 0; /* read clears all interrupts */
409	vpciLowerInterrupt(pState);
410	break;
411
412	default:
413	if (Port >= VPCI_CONFIG)
414	rc = pCallbacks->pfnGetConfig(pState, Port - VPCI_CONFIG, cb, pu32);
415	else
416	{
417	*pu32 = 0xFFFFFFFF;
418	rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortIn: no valid port at offset port=%RTiop cb=%08x\n",
419	INSTANCE(pState), Port, cb);
420	}
421	break;
422	}
423	Log3(("%s vpciIOPortIn: At %RTiop in %0x\n", INSTANCE(pState), Port, cb2, *pu32));
424	STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIORead), a);
425	//vpciCsLeave(pState);
426	return rc;
427	}
428
429
430	/**
431	* Port I/O Handler for OUT operations.
432	*
433	* @returns VBox status code.
434	*
435	* @param pDevIns The device instance.
436	* @param pvUser User argument.
437	* @param Port Port number used for the IN operation.
438	* @param u32 The value to output.
439	* @param cb The value size in bytes.
440	* @param pCallbacks Pointer to the callbacks.
441	* @thread EMT
442	*/
443	int vpciIOPortOut(PPDMDEVINS pDevIns,
444	void *pvUser,
445	RTIOPORT Port,
446	uint32_t u32,
447	unsigned cb,
448	PCVPCIIOCALLBACKS pCallbacks)
449	{
450	VPCISTATE pState = PDMINS_2_DATA(pDevIns, VPCISTATE );
451	int rc = VINF_SUCCESS;
452	bool fHasBecomeReady;
453	STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIOWrite), a);
454	RT_NOREF_PV(pvUser);
455
456	Port -= pState->IOPortBase;
457	Log3(("%s virtioIOPortOut: At %RTiop out %0x\n", INSTANCE(pState), Port, cb2, u32));
458
459	switch (Port)
460	{
461	case VPCI_GUEST_FEATURES:
462	/* Check if the guest negotiates properly, fall back to basics if it does not. */
463	if (VPCI_F_BAD_FEATURE & u32)
464	{
465	Log(("%s WARNING! Guest failed to negotiate properly (guest=%x)\n",
466	INSTANCE(pState), u32));
467	pState->uGuestFeatures = pCallbacks->pfnGetHostMinimalFeatures(pState);
468	}
469	/* The guest may potentially desire features we don't support! */
470	else if (~vpciGetHostFeatures(pState, pCallbacks->pfnGetHostFeatures) & u32)
471	{
472	Log(("%s Guest asked for features host does not support! (host=%x guest=%x)\n",
473	INSTANCE(pState),
474	vpciGetHostFeatures(pState, pCallbacks->pfnGetHostFeatures), u32));
475	pState->uGuestFeatures =
476	vpciGetHostFeatures(pState, pCallbacks->pfnGetHostFeatures);
477	}
478	else
479	pState->uGuestFeatures = u32;
480	pCallbacks->pfnSetHostFeatures(pState, pState->uGuestFeatures);
481	break;
482
483	case VPCI_QUEUE_PFN:
484	/*
485	* The guest is responsible for allocating the pages for queues,
486	* here it provides us with the page number of descriptor table.
487	* Note that we provide the size of the queue to the guest via
488	* VIRTIO_PCI_QUEUE_NUM.
489	*/
490	pState->Queues[pState->uQueueSelector].uPageNumber = u32;
491	if (u32)
492	vqueueInit(&pState->Queues[pState->uQueueSelector], u32);
493	else
494	rc = pCallbacks->pfnReset(pState);
495	break;
496
497	case VPCI_QUEUE_SEL:
498	Assert(cb == 2);
499	u32 &= 0xFFFF;
500	if (u32 < pState->nQueues)
501	pState->uQueueSelector = u32;
502	else
503	Log3(("%s vpciIOPortOut: Invalid queue selector %08x\n", INSTANCE(pState), u32));
504	break;
505
506	case VPCI_QUEUE_NOTIFY:
507	#ifdef IN_RING3
508	Assert(cb == 2);
509	u32 &= 0xFFFF;
510	if (u32 < pState->nQueues)
511	if (pState->Queues[u32].VRing.addrDescriptors)
512	{
513	// rc = vpciCsEnter(pState, VERR_SEM_BUSY);
514	// if (RT_LIKELY(rc == VINF_SUCCESS))
515	// {
516	pState->Queues[u32].pfnCallback(pState, &pState->Queues[u32]);
517	// vpciCsLeave(pState);
518	// }
519	}
520	else
521	Log(("%s The queue (#%d) being notified has not been initialized.\n",
522	INSTANCE(pState), u32));
523	else
524	Log(("%s Invalid queue number (%d)\n", INSTANCE(pState), u32));
525	#else
526	rc = VINF_IOM_R3_IOPORT_WRITE;
527	#endif
528	break;
529
530	case VPCI_STATUS:
531	Assert(cb == 1);
532	u32 &= 0xFF;
533	fHasBecomeReady = !(pState->uStatus & VPCI_STATUS_DRV_OK) && (u32 & VPCI_STATUS_DRV_OK);
534	pState->uStatus = u32;
535	/* Writing 0 to the status port triggers device reset. */
536	if (u32 == 0)
537	rc = pCallbacks->pfnReset(pState);
538	else if (fHasBecomeReady)
539	pCallbacks->pfnReady(pState);
540	break;
541
542	default:
543	if (Port >= VPCI_CONFIG)
544	rc = pCallbacks->pfnSetConfig(pState, Port - VPCI_CONFIG, cb, &u32);
545	else
546	rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortOut: no valid port at offset Port=%RTiop cb=%08x\n",
547	INSTANCE(pState), Port, cb);
548	break;
549	}
550
551	STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIOWrite), a);
552	return rc;
553	}
554
555	#ifdef IN_RING3
556
557	/**
558	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
559	*/
560	void vpciQueryInterface(struct PDMIBASE pInterface, const char *pszIID)
561	{
562	VPCISTATE *pThis = IFACE_TO_STATE(pInterface, IBase);
563	Assert(&pThis->IBase == pInterface);
564
565	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
566	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
567	return NULL;
568	}
569
570	/**
571	* Gets the pointer to the status LED of a unit.
572	*
573	* @returns VBox status code.
574	* @param pInterface Pointer to the interface structure.
575	* @param iLUN The unit which status LED we desire.
576	* @param ppLed Where to store the LED pointer.
577	* @thread EMT
578	*/
579	static DECLCALLBACK(int) vpciQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
580	{
581	VPCISTATE *pState = IFACE_TO_STATE(pInterface, ILeds);
582	int rc = VERR_PDM_LUN_NOT_FOUND;
583
584	if (iLUN == 0)
585	{
586	*ppLed = &pState->led;
587	rc = VINF_SUCCESS;
588	}
589	return rc;
590	}
591
592	/**
593	* Turns on/off the write status LED.
594	*
595	* @returns VBox status code.
596	* @param pState Pointer to the device state structure.
597	* @param fOn New LED state.
598	*/
599	void vpciSetWriteLed(PVPCISTATE pState, bool fOn)
600	{
601	LogFlow(("%s vpciSetWriteLed: %s\n", INSTANCE(pState), fOn?"on":"off"));
602	if (fOn)
603	pState->led.Asserted.s.fWriting = pState->led.Actual.s.fWriting = 1;
604	else
605	pState->led.Actual.s.fWriting = fOn;
606	}
607
608	/**
609	* Turns on/off the read status LED.
610	*
611	* @returns VBox status code.
612	* @param pState Pointer to the device state structure.
613	* @param fOn New LED state.
614	*/
615	void vpciSetReadLed(PVPCISTATE pState, bool fOn)
616	{
617	LogFlow(("%s vpciSetReadLed: %s\n", INSTANCE(pState), fOn?"on":"off"));
618	if (fOn)
619	pState->led.Asserted.s.fReading = pState->led.Actual.s.fReading = 1;
620	else
621	pState->led.Actual.s.fReading = fOn;
622	}
623
624
625	#if 0 /* unused */
626	/**
627	* Sets 32-bit register in PCI configuration space.
628	* @param refPciDev The PCI device.
629	* @param uOffset The register offset.
630	* @param u32Value The value to store in the register.
631	* @thread EMT
632	*/
633	DECLINLINE(void) vpciCfgSetU32(PDMPCIDEV& refPciDev, uint32_t uOffset, uint32_t u32Value)
634	{
635	Assert(uOffset+sizeof(u32Value) <= sizeof(refPciDev.config));
636	(uint32_t)&refPciDev.config[uOffset] = u32Value;
637	}
638	#endif /* unused */
639
640
641	#ifdef DEBUG
642	static void vpciDumpState(PVPCISTATE pState, const char *pcszCaller)
643	{
644	Log2(("vpciDumpState: (called from %s)\n"
645	" uGuestFeatures = 0x%08x\n"
646	" uQueueSelector = 0x%04x\n"
647	" uStatus = 0x%02x\n"
648	" uISR = 0x%02x\n",
649	pcszCaller,
650	pState->uGuestFeatures,
651	pState->uQueueSelector,
652	pState->uStatus,
653	pState->uISR));
654
655	for (unsigned i = 0; i < pState->nQueues; i++)
656	Log2((" %s queue:\n"
657	" VRing.uSize = %u\n"
658	" VRing.addrDescriptors = %p\n"
659	" VRing.addrAvail = %p\n"
660	" VRing.addrUsed = %p\n"
661	" uNextAvailIndex = %u\n"
662	" uNextUsedIndex = %u\n"
663	" uPageNumber = %x\n",
664	pState->Queues[i].pcszName,
665	pState->Queues[i].VRing.uSize,
666	pState->Queues[i].VRing.addrDescriptors,
667	pState->Queues[i].VRing.addrAvail,
668	pState->Queues[i].VRing.addrUsed,
669	pState->Queues[i].uNextAvailIndex,
670	pState->Queues[i].uNextUsedIndex,
671	pState->Queues[i].uPageNumber));
672	}
673	#else
674	# define vpciDumpState(x, s) do {} while (0)
675	#endif
676
677	/**
678	* Saves the state of device.
679	*
680	* @returns VBox status code.
681	* @param pDevIns The device instance.
682	* @param pSSM The handle to the saved state.
683	*/
684	int vpciSaveExec(PVPCISTATE pState, PSSMHANDLE pSSM)
685	{
686	int rc;
687
688	vpciDumpState(pState, "vpciSaveExec");
689
690	rc = SSMR3PutU32(pSSM, pState->uGuestFeatures);
691	AssertRCReturn(rc, rc);
692	rc = SSMR3PutU16(pSSM, pState->uQueueSelector);
693	AssertRCReturn(rc, rc);
694	rc = SSMR3PutU8( pSSM, pState->uStatus);
695	AssertRCReturn(rc, rc);
696	rc = SSMR3PutU8( pSSM, pState->uISR);
697	AssertRCReturn(rc, rc);
698
699	/* Save queue states */
700	rc = SSMR3PutU32(pSSM, pState->nQueues);
701	AssertRCReturn(rc, rc);
702	for (unsigned i = 0; i < pState->nQueues; i++)
703	{
704	rc = SSMR3PutU16(pSSM, pState->Queues[i].VRing.uSize);
705	AssertRCReturn(rc, rc);
706	rc = SSMR3PutU32(pSSM, pState->Queues[i].uPageNumber);
707	AssertRCReturn(rc, rc);
708	rc = SSMR3PutU16(pSSM, pState->Queues[i].uNextAvailIndex);
709	AssertRCReturn(rc, rc);
710	rc = SSMR3PutU16(pSSM, pState->Queues[i].uNextUsedIndex);
711	AssertRCReturn(rc, rc);
712	}
713
714	return VINF_SUCCESS;
715	}
716
717	/**
718	* Loads a saved device state.
719	*
720	* @returns VBox status code.
721	* @param pDevIns The device instance.
722	* @param pSSM The handle to the saved state.
723	* @param uVersion The data unit version number.
724	* @param uPass The data pass.
725	*/
726	int vpciLoadExec(PVPCISTATE pState, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass, uint32_t nQueues)
727	{
728	int rc;
729
730	if (uPass == SSM_PASS_FINAL)
731	{
732	/* Restore state data */
733	rc = SSMR3GetU32(pSSM, &pState->uGuestFeatures);
734	AssertRCReturn(rc, rc);
735	rc = SSMR3GetU16(pSSM, &pState->uQueueSelector);
736	AssertRCReturn(rc, rc);
737	rc = SSMR3GetU8( pSSM, &pState->uStatus);
738	AssertRCReturn(rc, rc);
739	rc = SSMR3GetU8( pSSM, &pState->uISR);
740	AssertRCReturn(rc, rc);
741
742	/* Restore queues */
743	if (uVersion > VIRTIO_SAVEDSTATE_VERSION_3_1_BETA1)
744	{
745	rc = SSMR3GetU32(pSSM, &pState->nQueues);
746	AssertRCReturn(rc, rc);
747	}
748	else
749	pState->nQueues = nQueues;
750	for (unsigned i = 0; i < pState->nQueues; i++)
751	{
752	rc = SSMR3GetU16(pSSM, &pState->Queues[i].VRing.uSize);
753	AssertRCReturn(rc, rc);
754	rc = SSMR3GetU32(pSSM, &pState->Queues[i].uPageNumber);
755	AssertRCReturn(rc, rc);
756
757	if (pState->Queues[i].uPageNumber)
758	vqueueInit(&pState->Queues[i], pState->Queues[i].uPageNumber);
759
760	rc = SSMR3GetU16(pSSM, &pState->Queues[i].uNextAvailIndex);
761	AssertRCReturn(rc, rc);
762	rc = SSMR3GetU16(pSSM, &pState->Queues[i].uNextUsedIndex);
763	AssertRCReturn(rc, rc);
764	}
765	}
766
767	vpciDumpState(pState, "vpciLoadExec");
768
769	return VINF_SUCCESS;
770	}
771
772	/**
773	* Set PCI configuration space registers.
774	*
775	* @param pci Reference to PCI device structure.
776	* @param uDeviceId VirtiO Device Id
777	* @param uClass Class of PCI device (network, etc)
778	* @thread EMT
779	*/
780	static DECLCALLBACK(void) vpciConfigure(PDMPCIDEV& pci,
781	uint16_t uDeviceId,
782	uint16_t uClass)
783	{
784	/* Configure PCI Device, assume 32-bit mode ******************************/
785	PCIDevSetVendorId(&pci, DEVICE_PCI_VENDOR_ID);
786	PCIDevSetDeviceId(&pci, DEVICE_PCI_BASE_ID + uDeviceId);
787	PDMPciDevSetWord(&pci, VBOX_PCI_SUBSYSTEM_VENDOR_ID, DEVICE_PCI_SUBSYSTEM_VENDOR_ID);
788	PDMPciDevSetWord(&pci, VBOX_PCI_SUBSYSTEM_ID, DEVICE_PCI_SUBSYSTEM_BASE_ID + uDeviceId);
789
790	/* ABI version, must be equal 0 as of 2.6.30 kernel. */
791	PDMPciDevSetByte(&pci, VBOX_PCI_REVISION_ID, 0x00);
792	/* Ethernet adapter */
793	PDMPciDevSetByte(&pci, VBOX_PCI_CLASS_PROG, 0x00);
794	PDMPciDevSetWord(&pci, VBOX_PCI_CLASS_DEVICE, uClass);
795	/* Interrupt Pin: INTA# */
796	PDMPciDevSetByte(&pci, VBOX_PCI_INTERRUPT_PIN, 0x01);
797
798	#ifdef VBOX_WITH_MSI_DEVICES
799	PCIDevSetCapabilityList(&pci, 0x80);
800	PCIDevSetStatus( &pci, VBOX_PCI_STATUS_CAP_LIST);
801	#endif
802	}
803
804	#ifdef VBOX_WITH_STATISTICS
805	/* WARNING! This function must never be used in multithreaded context! */
806	static const char vpciCounter(const char pszDevFmt,
807	const char *pszCounter)
808	{
809	static char s_szCounterName[80];
810
811	RTStrPrintf(s_szCounterName, sizeof(s_szCounterName),
812	"/Devices/%s/%s", pszDevFmt, pszCounter);
813
814	return s_szCounterName;
815	}
816	#endif
817
818	/// @todo header
819	int vpciConstruct(PPDMDEVINS pDevIns, VPCISTATE *pState,
820	int iInstance, const char *pcszNameFmt,
821	uint16_t uDeviceId, uint16_t uClass,
822	uint32_t nQueues)
823	{
824	/* Init handles and log related stuff. */
825	RTStrPrintf(pState->szInstance, sizeof(pState->szInstance),
826	pcszNameFmt, iInstance);
827
828	pState->pDevInsR3 = pDevIns;
829	pState->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
830	pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
831	pState->led.u32Magic = PDMLED_MAGIC;
832
833	pState->ILeds.pfnQueryStatusLed = vpciQueryStatusLed;
834
835	/* Initialize critical section. */
836	int rc = PDMDevHlpCritSectInit(pDevIns, &pState->cs, RT_SRC_POS, "%s", pState->szInstance);
837	if (RT_FAILURE(rc))
838	return rc;
839
840	/* Set PCI config registers */
841	vpciConfigure(pState->pciDevice, uDeviceId, uClass);
842	/* Register PCI device */
843	rc = PDMDevHlpPCIRegister(pDevIns, &pState->pciDevice);
844	if (RT_FAILURE(rc))
845	return rc;
846
847	#ifdef VBOX_WITH_MSI_DEVICES
848	#if 0
849	{
850	PDMMSIREG aMsiReg;
851
852	RT_ZERO(aMsiReg);
853	aMsiReg.cMsixVectors = 1;
854	aMsiReg.iMsixCapOffset = 0x80;
855	aMsiReg.iMsixNextOffset = 0x0;
856	aMsiReg.iMsixBar = 0;
857	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &aMsiReg);
858	if (RT_FAILURE (rc))
859	PCIDevSetCapabilityList(&pState->pciDevice, 0x0);
860	}
861	#endif
862	#endif
863
864	/* Status driver */
865	PPDMIBASE pBase;
866	rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pState->IBase, &pBase, "Status Port");
867	if (RT_FAILURE(rc))
868	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the status LUN"));
869	pState->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
870
871	pState->nQueues = nQueues;
872
873	#if defined(VBOX_WITH_STATISTICS)
874	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in GC", vpciCounter(pcszNameFmt, "IO/ReadGC"), iInstance);
875	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in HC", vpciCounter(pcszNameFmt, "IO/ReadHC"), iInstance);
876	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in GC", vpciCounter(pcszNameFmt, "IO/WriteGC"), iInstance);
877	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in HC", vpciCounter(pcszNameFmt, "IO/WriteHC"), iInstance);
878	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsRaised, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of raised interrupts", vpciCounter(pcszNameFmt, "Interrupts/Raised"), iInstance);
879	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsSkipped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of skipped interrupts", vpciCounter(pcszNameFmt, "Interrupts/Skipped"), iInstance);
880	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatCsGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling CS wait in GC", vpciCounter(pcszNameFmt, "Cs/CsGC"), iInstance);
881	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatCsHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling CS wait in HC", vpciCounter(pcszNameFmt, "Cs/CsHC"), iInstance);
882	#endif /* VBOX_WITH_STATISTICS */
883
884	return rc;
885	}
886
887	/**
888	* Destruct PCI-related part of device.
889	*
890	* We need to free non-VM resources only.
891	*
892	* @returns VBox status code.
893	* @param pState The device state structure.
894	*/
895	int vpciDestruct(VPCISTATE* pState)
896	{
897	Log(("%s Destroying PCI instance\n", INSTANCE(pState)));
898
899	if (PDMCritSectIsInitialized(&pState->cs))
900	PDMR3CritSectDelete(&pState->cs);
901
902	return VINF_SUCCESS;
903	}
904
905	/**
906	* Device relocation callback.
907	*
908	* When this callback is called the device instance data, and if the
909	* device have a GC component, is being relocated, or/and the selectors
910	* have been changed. The device must use the chance to perform the
911	* necessary pointer relocations and data updates.
912	*
913	* Before the GC code is executed the first time, this function will be
914	* called with a 0 delta so GC pointer calculations can be one in one place.
915	*
916	* @param pDevIns Pointer to the device instance.
917	* @param offDelta The relocation delta relative to the old location.
918	*
919	* @remark A relocation CANNOT fail.
920	*/
921	void vpciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
922	{
923	RT_NOREF(offDelta);
924	VPCISTATE pState = PDMINS_2_DATA(pDevIns, VPCISTATE);
925	pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
926	// TBD
927	}
928
929	PVQUEUE vpciAddQueue(VPCISTATE* pState, unsigned uSize, PFNVPCIQUEUECALLBACK pfnCallback, const char *pcszName)
930	{
931	PVQUEUE pQueue = NULL;
932	/* Find an empty queue slot */
933	for (unsigned i = 0; i < pState->nQueues; i++)
934	{
935	if (pState->Queues[i].VRing.uSize == 0)
936	{
937	pQueue = &pState->Queues[i];
938	break;
939	}
940	}
941
942	if (!pQueue)
943	{
944	Log(("%s Too many queues being added, no empty slots available!\n", INSTANCE(pState)));
945	}
946	else
947	{
948	pQueue->VRing.uSize = uSize;
949	pQueue->VRing.addrDescriptors = 0;
950	pQueue->uPageNumber = 0;
951	pQueue->pfnCallback = pfnCallback;
952	pQueue->pcszName = pcszName;
953	}
954
955	return pQueue;
956	}
957
958	#endif /* IN_RING3 */
959
960	#endif /* VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/VirtIO/Virtio.cpp@ 64810

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