Virtio_1_0.h@ 84124

Last change on this file since 84124 was 83913, checked in by vboxsync, 5 years ago
Network/DevVirtioNet_1_0.cpp: Various fixes and improvements, most notably: Implemented SSM (save, restore, pause, resume, stop) all tested, implemented STAM similarly to DevVirtioNet.cpp, verified, added support for VIRTIO_F_EVENT_IDX feature, improved internal handling of Rx/Tx queue pair mgt (will facility multiqueue (MQ) feature better), fixed various @todo's added by bird
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 26.9 KB

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1	/* $Id: Virtio_1_0.h 83913 2020-04-22 04:52:12Z vboxsync $ */
2	/** @file
3	* Virtio_1_0.h - Virtio Declarations
4	*/
5
6	/*
7	* Copyright (C) 2009-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef VBOX_INCLUDED_SRC_VirtIO_Virtio_1_0_h
19	#define VBOX_INCLUDED_SRC_VirtIO_Virtio_1_0_h
20	#ifndef RT_WITHOUT_PRAGMA_ONCE
21	# pragma once
22	#endif
23
24	#include <iprt/ctype.h>
25	#include <iprt/sg.h>
26
27	/** Pointer to the shared VirtIO state. */
28	typedef struct VIRTIOCORE *PVIRTIOCORE;
29	/** Pointer to the ring-3 VirtIO state. */
30	typedef struct VIRTIOCORER3 *PVIRTIOCORER3;
31	/** Pointer to the ring-0 VirtIO state. */
32	typedef struct VIRTIOCORER0 *PVIRTIOCORER0;
33	/** Pointer to the raw-mode VirtIO state. */
34	typedef struct VIRTIOCORERC *PVIRTIOCORERC;
35	/** Pointer to the instance data for the current context. */
36	typedef CTX_SUFF(PVIRTIOCORE) PVIRTIOCORECC;
37
38	typedef enum VIRTIOVMSTATECHANGED
39	{
40	kvirtIoVmStateChangedInvalid = 0,
41	kvirtIoVmStateChangedReset,
42	kvirtIoVmStateChangedSuspend,
43	kvirtIoVmStateChangedPowerOff,
44	kvirtIoVmStateChangedResume,
45	kvirtIoVmStateChangedFor32BitHack = 0x7fffffff
46	} VIRTIOVMSTATECHANGED;
47
48	/**
49	* Important sizing and bounds params for this impl. of VirtIO 1.0 PCI device
50	*/
51	/**
52	* TEMPORARY NOTE: Some of these values are experimental during development and will likely change.
53	*/
54	#define VIRTIO_MAX_QUEUE_NAME_SIZE 32 /*< Maximum length of a queue name /
55	#define VIRTQ_MAX_SIZE 1024 /*< Max size (# desc elements) of a virtq /
56	#define VIRTQ_MAX_CNT 24 /*< Max queues we allow guest to create /
57	#define VIRTIO_NOTIFY_OFFSET_MULTIPLIER 2 /*< VirtIO Notify Cap. MMIO config param /
58	#define VIRTIO_REGION_PCI_CAP 2 /*< BAR for VirtIO Cap. MMIO (impl specific) /
59	#define VIRTIO_REGION_MSIX_CAP 0 /*< Bar for MSI-X handling /
60
61	#ifdef LOG_ENABLED
62	# define VIRTIO_HEX_DUMP(logLevel, pv, cb, base, title) \
63	do { \
64	if (LogIsItEnabled(logLevel, LOG_GROUP)) \
65	virtioCoreHexDump((pv), (cb), (base), (title)); \
66	} while (0)
67	#else
68	# define VIRTIO_HEX_DUMP(logLevel, pv, cb, base, title) do { } while (0)
69	#endif
70
71	typedef struct VIRTIOSGSEG /*< An S/G entry /
72	{
73	RTGCPHYS gcPhys; /*< Pointer to the segment buffer /
74	size_t cbSeg; /*< Size of the segment buffer /
75	} VIRTIOSGSEG;
76
77	typedef VIRTIOSGSEG *PVIRTIOSGSEG;
78	typedef const VIRTIOSGSEG *PCVIRTIOSGSEG;
79	typedef PVIRTIOSGSEG *PPVIRTIOSGSEG;
80
81	typedef struct VIRTIOSGBUF
82	{
83	PVIRTIOSGSEG paSegs; /*< Pointer to the scatter/gather array /
84	unsigned cSegs; /*< Number of segments /
85	unsigned idxSeg; /*< Current segment we are in /
86	/** @todo r=bird: s/gcPhys/GCPhys/g as this is how we write it everywhere. */
87	RTGCPHYS gcPhysCur; /*< Ptr to byte within the current seg /
88	size_t cbSegLeft; /*< # of bytes left in the current segment /
89	} VIRTIOSGBUF;
90
91	typedef VIRTIOSGBUF *PVIRTIOSGBUF;
92	typedef const VIRTIOSGBUF *PCVIRTIOSGBUF;
93	typedef PVIRTIOSGBUF *PPVIRTIOSGBUF;
94
95	/**
96	* Virtio descriptor chain representation.
97	*/
98	typedef struct VIRTIO_DESC_CHAIN
99	{
100	uint32_t u32Magic; /*< Magic value, VIRTIO_DESC_CHAIN_MAGIC. /
101	uint32_t volatile cRefs; /*< Reference counter. /
102	uint32_t uHeadIdx; /*< Head idx of associated desc chain /
103	uint32_t cbPhysSend; /*< Total size of src buffer /
104	PVIRTIOSGBUF pSgPhysSend; /*< Phys S/G/ buf for data from guest /
105	uint32_t cbPhysReturn; /*< Total size of dst buffer /
106	PVIRTIOSGBUF pSgPhysReturn; /*< Phys S/G buf to store result for guest /
107
108	/** @name Internal (bird combined 5 allocations into a single), fingers off.
109	* @{ */
110	VIRTIOSGBUF SgBufIn;
111	VIRTIOSGBUF SgBufOut;
112	VIRTIOSGSEG aSegsIn[VIRTQ_MAX_SIZE];
113	VIRTIOSGSEG aSegsOut[VIRTQ_MAX_SIZE];
114	/** @} */
115	} VIRTIO_DESC_CHAIN_T;
116	/** Pointer to a Virtio descriptor chain. */
117	typedef VIRTIO_DESC_CHAIN_T *PVIRTIO_DESC_CHAIN_T;
118	/** Pointer to a Virtio descriptor chain pointer. */
119	typedef VIRTIO_DESC_CHAIN_T **PPVIRTIO_DESC_CHAIN_T;
120	/** Magic value for VIRTIO_DESC_CHAIN_T::u32Magic. */
121	#define VIRTIO_DESC_CHAIN_MAGIC UINT32_C(0x19600219)
122
123	typedef struct VIRTIOPCIPARAMS
124	{
125	uint16_t uDeviceId; /*< PCI Cfg Device ID /
126	uint16_t uClassBase; /*< PCI Cfg Base Class /
127	uint16_t uClassSub; /*< PCI Cfg Subclass /
128	uint16_t uClassProg; /*< PCI Cfg Programming Interface Class /
129	uint16_t uSubsystemId; /*< PCI Cfg Card Manufacturer Vendor ID /
130	uint16_t uInterruptLine; /*< PCI Cfg Interrupt line /
131	uint16_t uInterruptPin; /*< PCI Cfg Interrupt pin /
132	} VIRTIOPCIPARAMS, *PVIRTIOPCIPARAMS;
133
134	#define VIRTIO_F_VERSION_1 RT_BIT_64(32) /*< Required feature bit for 1.0 devices /
135
136	#define VIRTIO_F_INDIRECT_DESC RT_BIT_64(28) /*< Allow descs to point to list of descs /
137	#define VIRTIO_F_EVENT_IDX RT_BIT_64(29) /*< Allow notification disable for n elems /
138	#define VIRTIO_F_RING_INDIRECT_DESC RT_BIT_64(28) /*< Doc bug: Goes under two names in spec /
139	#define VIRTIO_F_RING_EVENT_IDX RT_BIT_64(29) /*< Doc bug: Goes under two names in spec /
140
141	#define VIRTIO_DEV_INDEPENDENT_FEATURES_OFFERED ( 0 ) /*< TBD: Add VIRTIO_F_INDIRECT_DESC /
142
143	#define VIRTIO_ISR_VIRTQ_INTERRUPT RT_BIT_32(0) /*< Virtq interrupt bit of ISR register /
144	#define VIRTIO_ISR_DEVICE_CONFIG RT_BIT_32(1) /*< Device configuration changed bit of ISR /
145	#define DEVICE_PCI_VENDOR_ID_VIRTIO 0x1AF4 /*< Guest driver locates dev via (mandatory) /
146	#define DEVICE_PCI_REVISION_ID_VIRTIO 1 /*< VirtIO 1.0 non-transitional drivers >= 1 /
147
148	/** Reserved (negotiated) Feature Bits (e.g. device independent features, VirtIO 1.0 spec,section 6) */
149
150	#define VIRTIO_MSI_NO_VECTOR 0xffff /*< Vector value to disable MSI for queue /
151
152	/** Device Status field constants (from Virtio 1.0 spec) */
153	#define VIRTIO_STATUS_ACKNOWLEDGE 0x01 /*< Guest driver: Located this VirtIO device /
154	#define VIRTIO_STATUS_DRIVER 0x02 /*< Guest driver: Can drive this VirtIO dev. /
155	#define VIRTIO_STATUS_DRIVER_OK 0x04 /*< Guest driver: Driver set-up and ready /
156	#define VIRTIO_STATUS_FEATURES_OK 0x08 /*< Guest driver: Feature negotiation done /
157	#define VIRTIO_STATUS_FAILED 0x80 /*< Guest driver: Fatal error, gave up /
158	#define VIRTIO_STATUS_DEVICE_NEEDS_RESET 0x40 /*< Device experienced unrecoverable error /
159
160	/** @def Virtio Device PCI Capabilities type codes */
161	#define VIRTIO_PCI_CAP_COMMON_CFG 1 /*< Common configuration PCI capability ID /
162	#define VIRTIO_PCI_CAP_NOTIFY_CFG 2 /*< Notification area PCI capability ID /
163	#define VIRTIO_PCI_CAP_ISR_CFG 3 /*< ISR PCI capability id /
164	#define VIRTIO_PCI_CAP_DEVICE_CFG 4 /*< Device-specific PCI cfg capability ID /
165	#define VIRTIO_PCI_CAP_PCI_CFG 5 /*< PCI CFG capability ID /
166
167	#define VIRTIO_PCI_CAP_ID_VENDOR 0x09 /*< Vendor-specific PCI CFG Device Cap. ID /
168
169	/**
170	* The following is the PCI capability struct common to all VirtIO capability types
171	*/
172	typedef struct virtio_pci_cap
173	{
174	/* All little-endian */
175	uint8_t uCapVndr; /*< Generic PCI field: PCI_CAP_ID_VNDR /
176	uint8_t uCapNext; /*< Generic PCI field: next ptr. /
177	uint8_t uCapLen; /*< Generic PCI field: capability length /
178	uint8_t uCfgType; /*< Identifies the structure. /
179	uint8_t uBar; /*< Where to find it. /
180	uint8_t uPadding[3]; /*< Pad to full dword. /
181	uint32_t uOffset; /*< Offset within bar. (L.E.) /
182	uint32_t uLength; /*< Length of struct, in bytes. (L.E.) /
183	} VIRTIO_PCI_CAP_T, *PVIRTIO_PCI_CAP_T;
184
185	/**
186	* Local implementation's usage context of a queue (e.g. not part of VirtIO specification)
187	*/
188	typedef struct VIRTQSTATE
189	{
190	char szVirtqName[32]; /*< Dev-specific name of queue /
191	uint16_t uAvailIdx; /*< Consumer's position in avail ring /
192	uint16_t uUsedIdx; /*< Consumer's position in used ring /
193	bool fEventThresholdReached; /*< Don't lose track while queueing ahead /
194	} VIRTQSTATE, *PVIRTQSTATE;
195
196	/**
197	* VirtIO 1.0 Capabilities' related MMIO-mapped structs:
198	*
199	* Note: virtio_pci_device_cap is dev-specific, implemented by client. Definition unknown here.
200	*/
201	typedef struct virtio_pci_common_cfg
202	{
203	/* Per device fields */
204	uint32_t uDeviceFeaturesSelect; /*< RW (driver selects device features) /
205	uint32_t uDeviceFeatures; /*< RO (device reports features to driver) /
206	uint32_t uDriverFeaturesSelect; /*< RW (driver selects driver features) /
207	uint32_t uDriverFeatures; /*< RW (driver-accepted device features) /
208	uint16_t uMsixConfig; /*< RW (driver sets MSI-X config vector) /
209	uint16_t uNumQueues; /*< RO (device specifies max queues) /
210	uint8_t uDeviceStatus; /*< RW (driver writes device status, 0=reset) /
211	uint8_t uConfigGeneration; /*< RO (device changes when changing configs) /
212
213	/* Per virtqueue fields (as determined by uQueueSelect) */
214	uint16_t uQueueSelect; /*< RW (selects queue focus for these fields) /
215	uint16_t uQueueSize; /*< RW (queue size, 0 - 2^n) /
216	uint16_t uQueueMsixVector; /*< RW (driver selects MSI-X queue vector) /
217	uint16_t uQueueEnable; /*< RW (driver controls usability of queue) /
218	uint16_t uQueueNotifyOff; /*< RO (offset uto virtqueue; see spec) /
219	uint64_t aGCPhysQueueDesc; /*< RW (driver writes desc table phys addr) /
220	uint64_t aGCPhysQueueAvail; /*< RW (driver writes avail ring phys addr) /
221	uint64_t aGCPhysQueueUsed; /*< RW (driver writes used ring phys addr) /
222	} VIRTIO_PCI_COMMON_CFG_T, *PVIRTIO_PCI_COMMON_CFG_T;
223
224	typedef struct virtio_pci_notify_cap
225	{
226	struct virtio_pci_cap pciCap; /*< Notification MMIO mapping capability /
227	uint32_t uNotifyOffMultiplier; /*< notify_off_multiplier /
228	} VIRTIO_PCI_NOTIFY_CAP_T, *PVIRTIO_PCI_NOTIFY_CAP_T;
229
230	typedef struct virtio_pci_cfg_cap
231	{
232	struct virtio_pci_cap pciCap; /*< Cap. defines the BAR/off/len to access /
233	uint8_t uPciCfgData[4]; /*< I/O buf for above cap. /
234	} VIRTIO_PCI_CFG_CAP_T, *PVIRTIO_PCI_CFG_CAP_T;
235
236	/**
237	* PCI capability data locations (PCI CFG and MMIO).
238	*/
239	typedef struct VIRTIO_PCI_CAP_LOCATIONS_T
240	{
241	uint16_t offMmio;
242	uint16_t cbMmio;
243	uint16_t offPci;
244	uint16_t cbPci;
245	} VIRTIO_PCI_CAP_LOCATIONS_T;
246
247	/**
248	* The core/common state of the VirtIO PCI devices, shared edition.
249	*/
250	typedef struct VIRTIOCORE
251	{
252	char szInstance[16]; /*< Instance name, e.g. "VIRTIOSCSI0" /
253	PPDMDEVINS pDevIns; /*< Client device instance /
254	RTGCPHYS aGCPhysQueueDesc[VIRTQ_MAX_CNT]; /*< (MMIO) PhysAdr per-Q desc structs GUEST /
255	RTGCPHYS aGCPhysQueueAvail[VIRTQ_MAX_CNT]; /*< (MMIO) PhysAdr per-Q avail structs GUEST /
256	RTGCPHYS aGCPhysQueueUsed[VIRTQ_MAX_CNT]; /*< (MMIO) PhysAdr per-Q used structs GUEST /
257	uint16_t uQueueNotifyOff[VIRTQ_MAX_CNT]; /*< (MMIO) per-Q notify offset HOST /
258	uint16_t uQueueMsixVector[VIRTQ_MAX_CNT]; /*< (MMIO) Per-queue vector for MSI-X GUEST /
259	uint16_t uQueueEnable[VIRTQ_MAX_CNT]; /*< (MMIO) Per-queue enable GUEST /
260	uint16_t uQueueSize[VIRTQ_MAX_CNT]; /*< (MMIO) Per-queue size HOST/GUEST /
261	uint16_t uQueueSelect; /*< (MMIO) queue selector GUEST /
262	uint16_t padding;
263	uint64_t uDeviceFeatures; /*< (MMIO) Host features offered HOST /
264	uint64_t uDriverFeatures; /*< (MMIO) Host features accepted GUEST /
265	uint32_t uDeviceFeaturesSelect; /*< (MMIO) hi/lo select uDeviceFeatures GUEST /
266	uint32_t uDriverFeaturesSelect; /*< (MMIO) hi/lo select uDriverFeatures GUEST /
267	uint32_t uMsixConfig; /*< (MMIO) MSI-X vector GUEST /
268	uint8_t uDeviceStatus; /*< (MMIO) Device Status GUEST /
269	uint8_t uPrevDeviceStatus; /*< (MMIO) Prev Device Status GUEST /
270	uint8_t uConfigGeneration; /*< (MMIO) Device config sequencer HOST /
271	VIRTQSTATE virtqState[VIRTQ_MAX_CNT]; /*< Local impl-specific queue context /
272
273	/** @name The locations of the capability structures in PCI config space and the BAR.
274	* @{ */
275	VIRTIO_PCI_CAP_LOCATIONS_T LocPciCfgCap; /*< VIRTIO_PCI_CFG_CAP_T /
276	VIRTIO_PCI_CAP_LOCATIONS_T LocNotifyCap; /*< VIRTIO_PCI_NOTIFY_CAP_T /
277	VIRTIO_PCI_CAP_LOCATIONS_T LocCommonCfgCap; /*< VIRTIO_PCI_CAP_T /
278	VIRTIO_PCI_CAP_LOCATIONS_T LocIsrCap; /*< VIRTIO_PCI_CAP_T /
279	VIRTIO_PCI_CAP_LOCATIONS_T LocDeviceCap; /*< VIRTIO_PCI_CAP_T + custom data. /
280	/** @} */
281
282	bool fGenUpdatePending; /*< If set, update cfg gen after driver reads /
283	uint8_t uPciCfgDataOff;
284	uint8_t uISR; /*< Interrupt Status Register. /
285	uint8_t fMsiSupport;
286
287	/** The MMIO handle for the PCI capability region (\#2). */
288	IOMMMIOHANDLE hMmioPciCap;
289
290	/** @name Statistics
291	* @{ */
292	STAMCOUNTER StatDescChainsAllocated;
293	STAMCOUNTER StatDescChainsFreed;
294	STAMCOUNTER StatDescChainsSegsIn;
295	STAMCOUNTER StatDescChainsSegsOut;
296	/** @} */
297	} VIRTIOCORE;
298
299
300	/**
301	* The core/common state of the VirtIO PCI devices, ring-3 edition.
302	*/
303	typedef struct VIRTIOCORER3
304	{
305	/** @name Callbacks filled by the device before calling virtioCoreR3Init.
306	* @{ */
307	/**
308	* Implementation-specific client callback to notify client of significant device status
309	* changes.
310	*
311	* @param pVirtio Pointer to the shared virtio state.
312	* @param pVirtioCC Pointer to the ring-3 virtio state.
313	* @param fDriverOk True if guest driver is okay (thus queues, etc... are
314	* valid)
315	*/
316	DECLCALLBACKMEMBER(void, pfnStatusChanged)(PVIRTIOCORE pVirtio, PVIRTIOCORECC pVirtioCC, uint32_t fDriverOk);
317
318	/**
319	* When guest-to-host queue notifications are enabled, the guest driver notifies the host
320	* that the avail queue has buffers, and this callback informs the client.
321	*
322	* @param pVirtio Pointer to the shared virtio state.
323	* @param pVirtioCC Pointer to the ring-3 virtio state.
324	* @param idxQueue Index of the notified queue
325	*/
326	DECLCALLBACKMEMBER(void, pfnQueueNotified)(PVIRTIOCORE pVirtio, PVIRTIOCORECC pVirtioCC, uint16_t idxQueue);
327
328	/**
329	* Implementation-specific client callback to access VirtIO Device-specific capabilities
330	* (other VirtIO capabilities and features are handled in VirtIO implementation)
331	*
332	* @param pDevIns The device instance.
333	* @param offCap Offset within device specific capabilities struct.
334	* @param pvBuf Buffer in which to save read data.
335	* @param cbToRead Number of bytes to read.
336	*/
337	DECLCALLBACKMEMBER(int, pfnDevCapRead)(PPDMDEVINS pDevIns, uint32_t offCap, void *pvBuf, uint32_t cbToRead);
338
339	/**
340	* Implementation-specific client ballback to access VirtIO Device-specific capabilities
341	* (other VirtIO capabilities and features are handled in VirtIO implementation)
342	*
343	* @param pDevIns The device instance.
344	* @param offCap Offset within device specific capabilities struct.
345	* @param pvBuf Buffer with the bytes to write.
346	* @param cbToWrite Number of bytes to write.
347	*/
348	DECLCALLBACKMEMBER(int, pfnDevCapWrite)(PPDMDEVINS pDevIns, uint32_t offCap, const void *pvBuf, uint32_t cbWrite);
349	/** @} */
350
351	R3PTRTYPE(PVIRTIO_PCI_CFG_CAP_T) pPciCfgCap; /*< Pointer to struct in the PCI configuration area. /
352	R3PTRTYPE(PVIRTIO_PCI_NOTIFY_CAP_T) pNotifyCap; /*< Pointer to struct in the PCI configuration area. /
353	R3PTRTYPE(PVIRTIO_PCI_CAP_T) pCommonCfgCap; /*< Pointer to struct in the PCI configuration area. /
354	R3PTRTYPE(PVIRTIO_PCI_CAP_T) pIsrCap; /*< Pointer to struct in the PCI configuration area. /
355	R3PTRTYPE(PVIRTIO_PCI_CAP_T) pDeviceCap; /*< Pointer to struct in the PCI configuration area. /
356
357	uint32_t cbDevSpecificCfg; /*< Size of client's dev-specific config data /
358	R3PTRTYPE(uint8_t ) pbDevSpecificCfg; /< Pointer to client's struct /
359	R3PTRTYPE(uint8_t ) pbPrevDevSpecificCfg; /< Previous read dev-specific cfg of client /
360	bool fGenUpdatePending; /*< If set, update cfg gen after driver reads /
361	} VIRTIOCORER3;
362
363
364	/**
365	* The core/common state of the VirtIO PCI devices, ring-0 edition.
366	*/
367	typedef struct VIRTIOCORER0
368	{
369	uint64_t uUnusedAtTheMoment;
370	} VIRTIOCORER0;
371
372
373	/**
374	* The core/common state of the VirtIO PCI devices, raw-mode edition.
375	*/
376	typedef struct VIRTIOCORERC
377	{
378	uint64_t uUnusedAtTheMoment;
379	} VIRTIOCORERC;
380
381
382	/** @typedef VIRTIOCORECC
383	* The instance data for the current context. */
384	typedef CTX_SUFF(VIRTIOCORE) VIRTIOCORECC;
385
386
387	/** @name virtq related flags
388	* @{ */
389	#define VIRTQ_DESC_F_NEXT 1 /*< Indicates this descriptor chains to next /
390	#define VIRTQ_DESC_F_WRITE 2 /*< Marks buffer as write-only (default ro) /
391	#define VIRTQ_DESC_F_INDIRECT 4 /*< Buffer is list of buffer descriptors /
392
393	#define VIRTQ_USED_F_NO_NOTIFY 1 /*< Dev to Drv: Don't notify when buf added /
394	#define VIRTQ_AVAIL_F_NO_INTERRUPT 1 /*< Drv to Dev: Don't notify when buf eaten /
395	/** @} */
396
397
398	/** @name API for VirtIO parent device
399	* @{ */
400
401	int virtioCoreR3QueueAttach(PVIRTIOCORE pVirtio, uint16_t idxQueue, const char *pcszName);
402
403	int virtioCoreR3DescChainGet(PPDMDEVINS pDevIns, PVIRTIOCORE pVirtio, uint16_t idxQueue,
404	uint16_t uHeadIdx, PPVIRTIO_DESC_CHAIN_T ppDescChain);
405	uint32_t virtioCoreR3DescChainRetain(PVIRTIO_DESC_CHAIN_T pDescChain);
406	uint32_t virtioCoreR3DescChainRelease(PVIRTIOCORE pVirtio, PVIRTIO_DESC_CHAIN_T pDescChain);
407
408	int virtioCoreR3QueuePeek(PPDMDEVINS pDevIns, PVIRTIOCORE pVirtio, uint16_t idxQueue,
409	PPVIRTIO_DESC_CHAIN_T ppDescChain);
410
411	int virtioCoreR3QueueSkip(PVIRTIOCORE pVirtio, uint16_t idxQueue);
412
413	int virtioCoreR3QueueGet(PPDMDEVINS pDevIns, PVIRTIOCORE pVirtio, uint16_t idxQueue,
414	PPVIRTIO_DESC_CHAIN_T ppDescChain, bool fRemove);
415
416	int virtioCoreR3QueuePut(PPDMDEVINS pDevIns, PVIRTIOCORE pVirtio, uint16_t idxQueue, PRTSGBUF pSgVirtReturn,
417	PVIRTIO_DESC_CHAIN_T pDescChain, bool fFence);
418
419	int virtioCoreR3QueuePendingCount(PPDMDEVINS pDevIns, PVIRTIOCORE pVirtio, uint16_t idxQueue);
420	int virtioCoreQueueSync(PPDMDEVINS pDevIns, PVIRTIOCORE pVirtio, uint16_t idxQueue, bool fForce);
421	bool virtioCoreQueueIsEmpty(PPDMDEVINS pDevIns, PVIRTIOCORE pVirtio, uint16_t idxQueue);
422	void virtioCoreQueueEnable(PVIRTIOCORE pVirtio, uint16_t idxQueue, bool fEnabled);
423	void virtioCoreQueueSetNotify(PVIRTIOCORE pVirtio, uint16_t idxQueue, bool fEnabled);
424	void virtioCoreNotifyConfigChanged(PVIRTIOCORE pVirtio);
425	void virtioCoreResetAll(PVIRTIOCORE pVirtio);
426	void virtioPrintFeatures(VIRTIOCORE *pVirtio);
427
428	/**
429	* Return queue enable state
430	*
431	* @param pVirtio Pointer to the virtio state.
432	* @param idxQueue Queue number.
433	* @param fEnabled Flag indicating whether to enable queue or not
434	*/
435	DECLINLINE(bool) virtioCoreIsQueueEnabled(PVIRTIOCORE pVirtio, uint16_t idxQueue)
436	{
437	Assert(idxQueue < RT_ELEMENTS(pVirtio->virtqState));
438	return pVirtio->uQueueEnable[idxQueue] != 0;
439	}
440
441	/**
442	* Get name of queue, by idxQueue, assigned at virtioCoreR3QueueAttach()
443	*
444	* @param pVirtio Pointer to the virtio state.
445	* @param idxQueue Queue number.
446	*
447	* @returns Pointer to read-only queue name.
448	*/
449	DECLINLINE(const char *) virtioCoreQueueGetName(PVIRTIOCORE pVirtio, uint16_t idxQueue)
450	{
451	Assert((size_t)idxQueue < RT_ELEMENTS(pVirtio->virtqState));
452	return pVirtio->virtqState[idxQueue].szVirtqName;
453	}
454
455	/**
456	* Get the features VirtIO is running withnow.
457	*
458	* @returns Features the guest driver has accepted, finalizing the operational features
459	*/
460	DECLINLINE(uint64_t) virtioCoreGetNegotiatedFeatures(PVIRTIOCORE pVirtio)
461	{
462	return pVirtio->uDriverFeatures;
463	}
464
465	/**
466	* Get VirtIO accepted host-side features
467	*
468	* @returns feature bits selected or 0 if selector out of range.
469	*
470	* @param pState Virtio state
471	*/
472	DECLINLINE(uint64_t) virtioCoreGetAcceptedFeatures(PVIRTIOCORE pVirtio)
473	{
474	return pVirtio->uDriverFeatures;
475	}
476
477
478	/**
479	* Calculate the length of a GCPhys s/g buffer by tallying the size of each segment.
480	*
481	* @param pGcSgBuf GC S/G buffer to calculate length of
482	*/
483	DECLINLINE(size_t) virtioCoreSgBufCalcTotalLength(PCVIRTIOSGBUF pGcSgBuf)
484	{
485	size_t cb = 0;
486	unsigned i = pGcSgBuf->cSegs;
487	while (i-- > 0)
488	cb += pGcSgBuf->paSegs[i].cbSeg;
489	return cb;
490	}
491
492	void virtioCoreLogMappedIoValue(const char pszFunc, const char pszMember, uint32_t uMemberSize,
493	const void *pv, uint32_t cb, uint32_t uOffset,
494	int fWrite, int fHasIndex, uint32_t idx);
495
496	void virtioCoreHexDump(uint8_t pv, uint32_t cb, uint32_t uBase, const char pszTitle);
497	void virtioCoreGcPhysHexDump(PPDMDEVINS pDevIns, RTGCPHYS gcPhys, uint32_t cb, uint32_t uBase, const char *pszTitle);
498
499	void virtioCoreSgBufInit(PVIRTIOSGBUF pGcSgBuf, PVIRTIOSGSEG paSegs, size_t cSegs);
500	void virtioCoreSgBufReset(PVIRTIOSGBUF pGcSgBuf);
501	RTGCPHYS virtioCoreSgBufGetNextSegment(PVIRTIOSGBUF pGcSgBuf, size_t *pcbSeg);
502	RTGCPHYS virtioCoreSgBufAdvance(PVIRTIOSGBUF pGcSgBuf, size_t cbAdvance);
503	void virtioCoreSgBufInit(PVIRTIOSGBUF pSgBuf, PVIRTIOSGSEG paSegs, size_t cSegs);
504	size_t virtioCoreSgBufCalcTotalLength(PCVIRTIOSGBUF pGcSgBuf);
505	void virtioCoreSgBufReset(PVIRTIOSGBUF pGcSgBuf);
506	size_t virtioCoreSgBufCalcTotalLength(PVIRTIOSGBUF pGcSgBuf);
507	int virtioCoreR3SaveExec(PVIRTIOCORE pVirtio, PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM);
508	int virtioCoreR3LoadExec(PVIRTIOCORE pVirtio, PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM);
509	void virtioCoreR3VmStateChanged(PVIRTIOCORE pVirtio, VIRTIOVMSTATECHANGED enmState);
510	void virtioCoreR3Term(PPDMDEVINS pDevIns, PVIRTIOCORE pVirtio, PVIRTIOCORECC pVirtioCC);
511	int virtioCoreR3Init(PPDMDEVINS pDevIns, PVIRTIOCORE pVirtio, PVIRTIOCORECC pVirtioCC, PVIRTIOPCIPARAMS pPciParams,
512	const char pcszInstance, uint64_t fDevSpecificFeatures, void pvDevSpecificCfg, uint16_t cbDevSpecificCfg);
513	int virtioCoreRZInit(PPDMDEVINS pDevIns, PVIRTIOCORE pVirtio, PVIRTIOCORECC pVirtioCC);
514	const char *virtioCoreGetStateChangeText(VIRTIOVMSTATECHANGED enmState);
515
516	/** @} */
517
518
519	#endif /* !VBOX_INCLUDED_SRC_VirtIO_Virtio_1_0_h */

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source: vbox/trunk/src/VBox/Devices/VirtIO/Virtio_1_0.h@ 84124

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