Virtio_1_0.h@ 84803

Last change on this file since 84803 was 84803, checked in by vboxsync, 4 years ago
Network/DevVirtioNet_1_0.cpp: Rename API functions to refer to Virtq instead of Queue to be more Virtio like and disambiguate from other queue types. Temporarily enable build in Config.kmk to let the build machines catch errors
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File size: 27.2 KB

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1	/* $Id: Virtio_1_0.h 84803 2020-06-12 06:17:35Z vboxsync $ */
2	/** @file
3	* Virtio_1_0.h - Virtio Declarations
4	*/
5
6	/*
7	* Copyright (C) 2009-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef VBOX_INCLUDED_SRC_VirtIO_Virtio_1_0_h
19	#define VBOX_INCLUDED_SRC_VirtIO_Virtio_1_0_h
20	#ifndef RT_WITHOUT_PRAGMA_ONCE
21	# pragma once
22	#endif
23
24	#include <iprt/ctype.h>
25	#include <iprt/sg.h>
26
27	/** Pointer to the shared VirtIO state. */
28	typedef struct VIRTIOCORE *PVIRTIOCORE;
29	/** Pointer to the ring-3 VirtIO state. */
30	typedef struct VIRTIOCORER3 *PVIRTIOCORER3;
31	/** Pointer to the ring-0 VirtIO state. */
32	typedef struct VIRTIOCORER0 *PVIRTIOCORER0;
33	/** Pointer to the raw-mode VirtIO state. */
34	typedef struct VIRTIOCORERC *PVIRTIOCORERC;
35	/** Pointer to the instance data for the current context. */
36	typedef CTX_SUFF(PVIRTIOCORE) PVIRTIOCORECC;
37
38	typedef enum VIRTIOVMSTATECHANGED
39	{
40	kvirtIoVmStateChangedInvalid = 0,
41	kvirtIoVmStateChangedReset,
42	kvirtIoVmStateChangedSuspend,
43	kvirtIoVmStateChangedPowerOff,
44	kvirtIoVmStateChangedResume,
45	kvirtIoVmStateChangedFor32BitHack = 0x7fffffff
46	} VIRTIOVMSTATECHANGED;
47
48	/**
49	* Important sizing and bounds params for this impl. of VirtIO 1.0 PCI device
50	*/
51	/**
52	* TEMPORARY NOTE: Some of these values are experimental during development and will likely change.
53	*/
54	#define VIRTIO_MAX_VIRTQ_NAME_SIZE 32 /*< Maximum length of a queue name /
55	#define VIRTQ_MAX_ENTRIES 1024 /*< Max size (# desc elements) of a virtq /
56	#define VIRTQ_MAX_CNT 24 /*< Max queues we allow guest to create /
57	#define VIRTIO_NOTIFY_OFFSET_MULTIPLIER 2 /*< VirtIO Notify Cap. MMIO config param /
58	#define VIRTIO_REGION_PCI_CAP 2 /*< BAR for VirtIO Cap. MMIO (impl specific) /
59	#define VIRTIO_REGION_MSIX_CAP 0 /*< Bar for MSI-X handling /
60
61	#ifdef LOG_ENABLED
62	# define VIRTIO_HEX_DUMP(logLevel, pv, cb, base, title) \
63	do { \
64	if (LogIsItEnabled(logLevel, LOG_GROUP)) \
65	virtioCoreHexDump((pv), (cb), (base), (title)); \
66	} while (0)
67	#else
68	# define VIRTIO_HEX_DUMP(logLevel, pv, cb, base, title) do { } while (0)
69	#endif
70
71	typedef struct VIRTIOSGSEG /*< An S/G entry /
72	{
73	RTGCPHYS GCPhys; /*< Pointer to the segment buffer /
74	size_t cbSeg; /*< Size of the segment buffer /
75	} VIRTIOSGSEG;
76
77	typedef VIRTIOSGSEG *PVIRTIOSGSEG;
78	typedef const VIRTIOSGSEG *PCVIRTIOSGSEG;
79	typedef PVIRTIOSGSEG *PPVIRTIOSGSEG;
80
81	typedef struct VIRTIOSGBUF
82	{
83	PVIRTIOSGSEG paSegs; /*< Pointer to the scatter/gather array /
84	unsigned cSegs; /*< Number of segments /
85	unsigned idxSeg; /*< Current segment we are in /
86	RTGCPHYS GCPhysCur; /*< Ptr to byte within the current seg /
87	size_t cbSegLeft; /*< # of bytes left in the current segment /
88	} VIRTIOSGBUF;
89
90	typedef VIRTIOSGBUF *PVIRTIOSGBUF;
91	typedef const VIRTIOSGBUF *PCVIRTIOSGBUF;
92	typedef PVIRTIOSGBUF *PPVIRTIOSGBUF;
93
94	/**
95	* Virtio descriptor chain representation.
96	*/
97	typedef struct VIRTIO_DESC_CHAIN
98	{
99	uint32_t u32Magic; /*< Magic value, VIRTIO_DESC_CHAIN_MAGIC. /
100	uint32_t volatile cRefs; /*< Reference counter. /
101	uint32_t uHeadIdx; /*< Head idx of associated desc chain /
102	size_t cbPhysSend; /*< Total size of src buffer /
103	PVIRTIOSGBUF pSgPhysSend; /*< Phys S/G/ buf for data from guest /
104	size_t cbPhysReturn; /*< Total size of dst buffer /
105	PVIRTIOSGBUF pSgPhysReturn; /*< Phys S/G buf to store result for guest /
106
107	/** @name Internal (bird combined 5 allocations into a single), fingers off.
108	* @{ */
109	VIRTIOSGBUF SgBufIn;
110	VIRTIOSGBUF SgBufOut;
111	VIRTIOSGSEG aSegsIn[VIRTQ_MAX_ENTRIES];
112	VIRTIOSGSEG aSegsOut[VIRTQ_MAX_ENTRIES];
113	/** @} */
114	} VIRTIO_DESC_CHAIN_T;
115	/** Pointer to a Virtio descriptor chain. */
116	typedef VIRTIO_DESC_CHAIN_T *PVIRTIO_DESC_CHAIN_T;
117	/** Pointer to a Virtio descriptor chain pointer. */
118	typedef VIRTIO_DESC_CHAIN_T **PPVIRTIO_DESC_CHAIN_T;
119	/** Magic value for VIRTIO_DESC_CHAIN_T::u32Magic. */
120	#define VIRTIO_DESC_CHAIN_MAGIC UINT32_C(0x19600219)
121
122	typedef struct VIRTIOPCIPARAMS
123	{
124	uint16_t uDeviceId; /*< PCI Cfg Device ID /
125	uint16_t uClassBase; /*< PCI Cfg Base Class /
126	uint16_t uClassSub; /*< PCI Cfg Subclass /
127	uint16_t uClassProg; /*< PCI Cfg Programming Interface Class /
128	uint16_t uSubsystemId; /*< PCI Cfg Card Manufacturer Vendor ID /
129	uint16_t uInterruptLine; /*< PCI Cfg Interrupt line /
130	uint16_t uInterruptPin; /*< PCI Cfg Interrupt pin /
131	} VIRTIOPCIPARAMS, *PVIRTIOPCIPARAMS;
132
133	#define VIRTIO_F_VERSION_1 RT_BIT_64(32) /*< Required feature bit for 1.0 devices /
134
135	#define VIRTIO_F_INDIRECT_DESC RT_BIT_64(28) /*< Allow descs to point to list of descs /
136	#define VIRTIO_F_EVENT_IDX RT_BIT_64(29) /*< Allow notification disable for n elems /
137	#define VIRTIO_F_RING_INDIRECT_DESC RT_BIT_64(28) /*< Doc bug: Goes under two names in spec /
138	#define VIRTIO_F_RING_EVENT_IDX RT_BIT_64(29) /*< Doc bug: Goes under two names in spec /
139
140	#define VIRTIO_DEV_INDEPENDENT_FEATURES_OFFERED ( 0 ) /*< TBD: Add VIRTIO_F_INDIRECT_DESC /
141
142	#define VIRTIO_ISR_VIRTQ_INTERRUPT RT_BIT_32(0) /*< Virtq interrupt bit of ISR register /
143	#define VIRTIO_ISR_DEVICE_CONFIG RT_BIT_32(1) /*< Device configuration changed bit of ISR /
144	#define DEVICE_PCI_VENDOR_ID_VIRTIO 0x1AF4 /*< Guest driver locates dev via (mandatory) /
145	#define DEVICE_PCI_REVISION_ID_VIRTIO 1 /*< VirtIO 1.0 non-transitional drivers >= 1 /
146
147	/** Reserved (negotiated) Feature Bits (e.g. device independent features, VirtIO 1.0 spec,section 6) */
148
149	#define VIRTIO_MSI_NO_VECTOR 0xffff /*< Vector value to disable MSI for queue /
150
151	/** Device Status field constants (from Virtio 1.0 spec) */
152	#define VIRTIO_STATUS_ACKNOWLEDGE 0x01 /*< Guest driver: Located this VirtIO device /
153	#define VIRTIO_STATUS_DRIVER 0x02 /*< Guest driver: Can drive this VirtIO dev. /
154	#define VIRTIO_STATUS_DRIVER_OK 0x04 /*< Guest driver: Driver set-up and ready /
155	#define VIRTIO_STATUS_FEATURES_OK 0x08 /*< Guest driver: Feature negotiation done /
156	#define VIRTIO_STATUS_FAILED 0x80 /*< Guest driver: Fatal error, gave up /
157	#define VIRTIO_STATUS_DEVICE_NEEDS_RESET 0x40 /*< Device experienced unrecoverable error /
158
159	/** @def Virtio Device PCI Capabilities type codes */
160	#define VIRTIO_PCI_CAP_COMMON_CFG 1 /*< Common configuration PCI capability ID /
161	#define VIRTIO_PCI_CAP_NOTIFY_CFG 2 /*< Notification area PCI capability ID /
162	#define VIRTIO_PCI_CAP_ISR_CFG 3 /*< ISR PCI capability id /
163	#define VIRTIO_PCI_CAP_DEVICE_CFG 4 /*< Device-specific PCI cfg capability ID /
164	#define VIRTIO_PCI_CAP_PCI_CFG 5 /*< PCI CFG capability ID /
165
166	#define VIRTIO_PCI_CAP_ID_VENDOR 0x09 /*< Vendor-specific PCI CFG Device Cap. ID /
167
168	/**
169	* The following is the PCI capability struct common to all VirtIO capability types
170	*/
171	typedef struct virtio_pci_cap
172	{
173	/* All little-endian */
174	uint8_t uCapVndr; /*< Generic PCI field: PCI_CAP_ID_VNDR /
175	uint8_t uCapNext; /*< Generic PCI field: next ptr. /
176	uint8_t uCapLen; /*< Generic PCI field: capability length /
177	uint8_t uCfgType; /*< Identifies the structure. /
178	uint8_t uBar; /*< Where to find it. /
179	uint8_t uPadding[3]; /*< Pad to full dword. /
180	uint32_t uOffset; /*< Offset within bar. (L.E.) /
181	uint32_t uLength; /*< Length of struct, in bytes. (L.E.) /
182	} VIRTIO_PCI_CAP_T, *PVIRTIO_PCI_CAP_T;
183
184	/**
185	* Local implementation's usage context of a queue (e.g. not part of VirtIO specification)
186	*/
187	typedef struct VIRTQSTATE
188	{
189	uint16_t idxVirtq; /*< Index of this queue /
190	char szVirtqName[32]; /*< Dev-specific name of queue /
191	uint16_t uAvailIdxShadow; /*< Consumer's position in avail ring /
192	uint16_t uUsedIdxShadow; /*< Consumer's position in used ring /
193	bool fVirtqRingEventThreshold; /*< Don't lose track while queueing ahead /
194	} VIRTQSTATE, *PVIRTQSTATE;
195
196	/**
197	* VirtIO 1.0 Capabilities' related MMIO-mapped structs:
198	*
199	* Note: virtio_pci_device_cap is dev-specific, implemented by client. Definition unknown here.
200	*/
201	typedef struct virtio_pci_common_cfg
202	{
203	/* Per device fields */
204	uint32_t uDeviceFeaturesSelect; /*< RW (driver selects device features) /
205	uint32_t uDeviceFeatures; /*< RO (device reports features to driver) /
206	uint32_t uDriverFeaturesSelect; /*< RW (driver selects driver features) /
207	uint32_t uDriverFeatures; /*< RW (driver-accepted device features) /
208	uint16_t uMsixConfig; /*< RW (driver sets MSI-X config vector) /
209	uint16_t uNumVirtqs; /*< RO (device specifies max queues) /
210	uint8_t uDeviceStatus; /*< RW (driver writes device status, 0=reset) /
211	uint8_t uConfigGeneration; /*< RO (device changes when changing configs) /
212
213	/* Per virtqueue fields (as determined by uVirtqSelect) */
214	uint16_t uVirtqSelect; /*< RW (selects queue focus for these fields) /
215	uint16_t uVirtqSize; /*< RW (queue size, 0 - 2^n) /
216	uint16_t uVirtqMsixVector; /*< RW (driver selects MSI-X queue vector) /
217	uint16_t uVirtqEnable; /*< RW (driver controls usability of queue) /
218	uint16_t uVirtqNotifyOff; /*< RO (offset uto virtqueue; see spec) /
219	uint64_t aGCPhysVirtqDesc; /*< RW (driver writes desc table phys addr) /
220	uint64_t aGCPhysVirtqAvail; /*< RW (driver writes avail ring phys addr) /
221	uint64_t aGCPhysVirtqUsed; /*< RW (driver writes used ring phys addr) /
222	} VIRTIO_PCI_COMMON_CFG_T, *PVIRTIO_PCI_COMMON_CFG_T;
223
224	typedef struct virtio_pci_notify_cap
225	{
226	struct virtio_pci_cap pciCap; /*< Notification MMIO mapping capability /
227	uint32_t uNotifyOffMultiplier; /*< notify_off_multiplier /
228	} VIRTIO_PCI_NOTIFY_CAP_T, *PVIRTIO_PCI_NOTIFY_CAP_T;
229
230	typedef struct virtio_pci_cfg_cap
231	{
232	struct virtio_pci_cap pciCap; /*< Cap. defines the BAR/off/len to access /
233	uint8_t uPciCfgData[4]; /*< I/O buf for above cap. /
234	} VIRTIO_PCI_CFG_CAP_T, *PVIRTIO_PCI_CFG_CAP_T;
235
236	/**
237	* PCI capability data locations (PCI CFG and MMIO).
238	*/
239	typedef struct VIRTIO_PCI_CAP_LOCATIONS_T
240	{
241	uint16_t offMmio;
242	uint16_t cbMmio;
243	uint16_t offPci;
244	uint16_t cbPci;
245	} VIRTIO_PCI_CAP_LOCATIONS_T;
246
247	/**
248	* The core/common state of the VirtIO PCI devices, shared edition.
249	*/
250	typedef struct VIRTIOCORE
251	{
252	char szInstance[16]; /*< Instance name, e.g. "VIRTIOSCSI0" /
253	PPDMDEVINS pDevInsR0; /*< Client device instance /
254	PPDMDEVINS pDevInsR3; /*< Client device instance /
255	RTGCPHYS aGCPhysVirtqDesc[VIRTQ_MAX_CNT]; /*< (MMIO) PhysAdr per-Q desc structs GUEST /
256	RTGCPHYS aGCPhysVirtqAvail[VIRTQ_MAX_CNT]; /*< (MMIO) PhysAdr per-Q avail structs GUEST /
257	RTGCPHYS aGCPhysVirtqUsed[VIRTQ_MAX_CNT]; /*< (MMIO) PhysAdr per-Q used structs GUEST /
258	uint16_t uVirtqNotifyOff[VIRTQ_MAX_CNT]; /*< (MMIO) per-Q notify offset HOST /
259	uint16_t uVirtqMsixVector[VIRTQ_MAX_CNT]; /*< (MMIO) Per-queue vector for MSI-X GUEST /
260	uint16_t uVirtqEnable[VIRTQ_MAX_CNT]; /*< (MMIO) Per-queue enable GUEST /
261	uint16_t uVirtqSize[VIRTQ_MAX_CNT]; /*< (MMIO) Per-queue size HOST/GUEST /
262	uint16_t uVirtqSelect; /*< (MMIO) queue selector GUEST /
263	uint16_t padding;
264	uint64_t uDeviceFeatures; /*< (MMIO) Host features offered HOST /
265	uint64_t uDriverFeatures; /*< (MMIO) Host features accepted GUEST /
266	uint32_t uDeviceFeaturesSelect; /*< (MMIO) hi/lo select uDeviceFeatures GUEST /
267	uint32_t uDriverFeaturesSelect; /*< (MMIO) hi/lo select uDriverFeatures GUEST /
268	uint32_t uMsixConfig; /*< (MMIO) MSI-X vector GUEST /
269	uint8_t uDeviceStatus; /*< (MMIO) Device Status GUEST /
270	uint8_t uPrevDeviceStatus; /*< (MMIO) Prev Device Status GUEST /
271	uint8_t uConfigGeneration; /*< (MMIO) Device config sequencer HOST /
272	VIRTQSTATE aVirtqState[VIRTQ_MAX_CNT]; /*< Local impl-specific queue context /
273
274	/** @name The locations of the capability structures in PCI config space and the BAR.
275	* @{ */
276	VIRTIO_PCI_CAP_LOCATIONS_T LocPciCfgCap; /*< VIRTIO_PCI_CFG_CAP_T /
277	VIRTIO_PCI_CAP_LOCATIONS_T LocNotifyCap; /*< VIRTIO_PCI_NOTIFY_CAP_T /
278	VIRTIO_PCI_CAP_LOCATIONS_T LocCommonCfgCap; /*< VIRTIO_PCI_CAP_T /
279	VIRTIO_PCI_CAP_LOCATIONS_T LocIsrCap; /*< VIRTIO_PCI_CAP_T /
280	VIRTIO_PCI_CAP_LOCATIONS_T LocDeviceCap; /*< VIRTIO_PCI_CAP_T + custom data. /
281	/** @} */
282
283	bool fGenUpdatePending; /*< If set, update cfg gen after driver reads /
284	uint8_t uPciCfgDataOff; /*< Offset to PCI configuration data area /
285	uint8_t uISR; /*< Interrupt Status Register. /
286	uint8_t fMsiSupport; /*< Flag set if using MSI instead of ISR /
287
288	/** The MMIO handle for the PCI capability region (\#2). */
289	IOMMMIOHANDLE hMmioPciCap;
290
291	/** @name Statistics
292	* @{ */
293	STAMCOUNTER StatDescChainsAllocated;
294	STAMCOUNTER StatDescChainsFreed;
295	STAMCOUNTER StatDescChainsSegsIn;
296	STAMCOUNTER StatDescChainsSegsOut;
297	/** @} */
298	} VIRTIOCORE;
299
300	#define MAX_NAME 64
301
302
303	/**
304	* The core/common state of the VirtIO PCI devices, ring-3 edition.
305	*/
306	typedef struct VIRTIOCORER3
307	{
308	/** @name Callbacks filled by the device before calling virtioCoreR3Init.
309	* @{ */
310	/**
311	* Implementation-specific client callback to notify client of significant device status
312	* changes.
313	*
314	* @param pVirtio Pointer to the shared virtio state.
315	* @param pVirtioCC Pointer to the ring-3 virtio state.
316	* @param fDriverOk True if guest driver is okay (thus queues, etc... are
317	* valid)
318	*/
319	DECLCALLBACKMEMBER(void, pfnStatusChanged)(PVIRTIOCORE pVirtio, PVIRTIOCORECC pVirtioCC, uint32_t fDriverOk);
320
321	/**
322	* Implementation-specific client callback to access VirtIO Device-specific capabilities
323	* (other VirtIO capabilities and features are handled in VirtIO implementation)
324	*
325	* @param pDevIns The device instance.
326	* @param offCap Offset within device specific capabilities struct.
327	* @param pvBuf Buffer in which to save read data.
328	* @param cbToRead Number of bytes to read.
329	*/
330	DECLCALLBACKMEMBER(int, pfnDevCapRead)(PPDMDEVINS pDevIns, uint32_t offCap, void *pvBuf, uint32_t cbToRead);
331
332	/**
333	* Implementation-specific client ballback to access VirtIO Device-specific capabilities
334	* (other VirtIO capabilities and features are handled in VirtIO implementation)
335	*
336	* @param pDevIns The device instance.
337	* @param offCap Offset within device specific capabilities struct.
338	* @param pvBuf Buffer with the bytes to write.
339	* @param cbToWrite Number of bytes to write.
340	*/
341	DECLCALLBACKMEMBER(int, pfnDevCapWrite)(PPDMDEVINS pDevIns, uint32_t offCap, const void *pvBuf, uint32_t cbWrite);
342
343
344	/**
345	* When guest-to-host queue notifications are enabled, the guest driver notifies the host
346	* that the avail queue has buffers, and this callback informs the client.
347	*
348	* @param pVirtio Pointer to the shared virtio state.
349	* @param pVirtioCC Pointer to the ring-3 virtio state.
350	* @param idxVirtq Index of the notified queue
351	*/
352	DECLCALLBACKMEMBER(void, pfnVirtqNotified)(PPDMDEVINS pDevIns, PVIRTIOCORE pVirtio, uint16_t idxVirtq);
353
354	/** @} */
355
356
357	R3PTRTYPE(PVIRTIO_PCI_CFG_CAP_T) pPciCfgCap; /*< Pointer to struct in the PCI configuration area. /
358	R3PTRTYPE(PVIRTIO_PCI_NOTIFY_CAP_T) pNotifyCap; /*< Pointer to struct in the PCI configuration area. /
359	R3PTRTYPE(PVIRTIO_PCI_CAP_T) pCommonCfgCap; /*< Pointer to struct in the PCI configuration area. /
360	R3PTRTYPE(PVIRTIO_PCI_CAP_T) pIsrCap; /*< Pointer to struct in the PCI configuration area. /
361	R3PTRTYPE(PVIRTIO_PCI_CAP_T) pDeviceCap; /*< Pointer to struct in the PCI configuration area. /
362
363	uint32_t cbDevSpecificCfg; /*< Size of client's dev-specific config data /
364	R3PTRTYPE(uint8_t ) pbDevSpecificCfg; /< Pointer to client's struct /
365	R3PTRTYPE(uint8_t ) pbPrevDevSpecificCfg; /< Previous read dev-specific cfg of client /
366	bool fGenUpdatePending; /*< If set, update cfg gen after driver reads /
367	char pcszMmioName[MAX_NAME]; /*< MMIO mapping name /
368	} VIRTIOCORER3;
369
370
371	/**
372	* The core/common state of the VirtIO PCI devices, ring-0 edition.
373	*/
374	typedef struct VIRTIOCORER0
375	{
376
377	/**
378	* When guest-to-host queue notifications are enabled, the guest driver notifies the host
379	* that the avail queue has buffers, and this callback informs the client.
380	*
381	* @param pVirtio Pointer to the shared virtio state.
382	* @param pVirtioCC Pointer to the ring-3 virtio state.
383	* @param idxVirtq Index of the notified queue
384	*/
385	DECLCALLBACKMEMBER(void, pfnVirtqNotified)(PPDMDEVINS pDevIns, PVIRTIOCORE pVirtio, uint16_t idxVirtq);
386
387	} VIRTIOCORER0;
388
389
390	/**
391	* The core/common state of the VirtIO PCI devices, raw-mode edition.
392	*/
393	typedef struct VIRTIOCORERC
394	{
395	uint64_t uUnusedAtTheMoment;
396	} VIRTIOCORERC;
397
398
399	/** @typedef VIRTIOCORECC
400	* The instance data for the current context. */
401	typedef CTX_SUFF(VIRTIOCORE) VIRTIOCORECC;
402
403
404	/** @name API for VirtIO parent device
405	* @{ */
406
407	int virtioCoreVirtqSync(PPDMDEVINS pDevIns, PVIRTIOCORE pVirtio, uint16_t idxVirtq);
408	uint16_t virtioCoreVirtqAvailCount(PPDMDEVINS pDevIns, PVIRTIOCORE pVirtio, uint16_t idxVirtq);
409	void virtioCoreVirtqEnable(PVIRTIOCORE pVirtio, uint16_t idxVirtq, bool fEnable);
410	void virtioCoreVirtqNotifyEnable(PVIRTIOCORE pVirtio, uint16_t idxVirtq, bool fEnable);
411	void virtioCoreNotifyConfigChanged(PVIRTIOCORE pVirtio);
412	void virtioCoreResetAll(PVIRTIOCORE pVirtio);
413	void virtioCorePrintFeatures(VIRTIOCORE *pVirtio, PCDBGFINFOHLP pHlp);
414
415	uint32_t virtioCoreR3DescChainRetain(PVIRTIO_DESC_CHAIN_T pDescChain);
416	uint32_t virtioCoreR3DescChainRelease(PVIRTIOCORE pVirtio, PVIRTIO_DESC_CHAIN_T pDescChain);
417	void virtioCoreR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs);
418	void virtioCoreR3VirtqInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs, int idxVirtq);
419	int virtioCoreR3VirtqAttach(PVIRTIOCORE pVirtio, uint16_t idxVirtq, const char *pcszName);
420
421	int virtioCoreR3DescChainGet(PPDMDEVINS pDevIns, PVIRTIOCORE pVirtio, uint16_t idxVirtq,
422	uint16_t uHeadIdx, PPVIRTIO_DESC_CHAIN_T ppDescChain);
423
424	int virtioCoreR3VirtqPeek(PPDMDEVINS pDevIns, PVIRTIOCORE pVirtio, uint16_t idxVirtq,
425	PPVIRTIO_DESC_CHAIN_T ppDescChain);
426
427	int virtioCoreR3VirtqSkip(PVIRTIOCORE pVirtio, uint16_t idxVirtq);
428
429	int virtioCoreR3VirtqGet(PPDMDEVINS pDevIns, PVIRTIOCORE pVirtio, uint16_t idxVirtq,
430	PPVIRTIO_DESC_CHAIN_T ppDescChain, bool fRemove);
431
432	int virtioCoreR3VirtqPut(PPDMDEVINS pDevIns, PVIRTIOCORE pVirtio, uint16_t idxVirtq, PRTSGBUF pSgVirtReturn,
433	PVIRTIO_DESC_CHAIN_T pDescChain, bool fFence);
434
435
436	/**
437	* Return queue enable state
438	*
439	* @param pVirtio Pointer to the virtio state.
440	* @param idxVirtq Virtq number.
441	* @returns true or false indicating whether to enable queue or not
442	*/
443	DECLINLINE(bool) virtioCoreIsVirtqEnabled(PVIRTIOCORE pVirtio, uint16_t idxVirtq)
444	{
445	Assert(idxVirtq < RT_ELEMENTS(pVirtio->aVirtqState));
446	return pVirtio->uVirtqEnable[idxVirtq] != 0;
447	}
448
449	/**
450	* Get name of queue, by idxVirtq, assigned at virtioCoreR3VirtqAttach()
451	*
452	* @param pVirtio Pointer to the virtio state.
453	* @param idxVirtq Virtq number.
454	*
455	* @returns Pointer to read-only queue name.
456	*/
457	DECLINLINE(const char *) virtioCoreVirtqGetName(PVIRTIOCORE pVirtio, uint16_t idxVirtq)
458	{
459	Assert((size_t)idxVirtq < RT_ELEMENTS(pVirtio->aVirtqState));
460	return pVirtio->aVirtqState[idxVirtq].szVirtqName;
461	}
462
463	/**
464	* Get the features VirtIO is running withnow.
465	*
466	* @returns Features the guest driver has accepted, finalizing the operational features
467	*/
468	DECLINLINE(uint64_t) virtioCoreGetNegotiatedFeatures(PVIRTIOCORE pVirtio)
469	{
470	return pVirtio->uDriverFeatures;
471	}
472
473
474	/**
475	* Calculate the length of a GCPhys s/g buffer by tallying the size of each segment.
476	*
477	* @param pGcSgBuf GC S/G buffer to calculate length of
478	*/
479	DECLINLINE(size_t) virtioCoreSgBufCalcTotalLength(PCVIRTIOSGBUF pGcSgBuf)
480	{
481	size_t cb = 0;
482	unsigned i = pGcSgBuf->cSegs;
483	while (i-- > 0)
484	cb += pGcSgBuf->paSegs[i].cbSeg;
485	return cb;
486	}
487
488	void virtioCoreLogMappedIoValue(const char pszFunc, const char pszMember, uint32_t uMemberSize,
489	const void *pv, uint32_t cb, uint32_t uOffset,
490	int fWrite, int fHasIndex, uint32_t idx);
491
492	/* Debug assist functions for consumer device code */
493	void virtioCoreHexDump(uint8_t pv, uint32_t cb, uint32_t uBase, const char pszTitle);
494	void virtioCoreGCPhysHexDump(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint16_t cb, uint32_t uBase, const char *pszTitle);
495
496
497	void virtioCoreSgBufInit(PVIRTIOSGBUF pGcSgBuf, PVIRTIOSGSEG paSegs, size_t cSegs);
498	void virtioCoreSgBufReset(PVIRTIOSGBUF pGcSgBuf);
499	RTGCPHYS virtioCoreSgBufGetNextSegment(PVIRTIOSGBUF pGcSgBuf, size_t *pcbSeg);
500	RTGCPHYS virtioCoreSgBufAdvance(PVIRTIOSGBUF pGcSgBuf, size_t cbAdvance);
501	void virtioCoreSgBufInit(PVIRTIOSGBUF pSgBuf, PVIRTIOSGSEG paSegs, size_t cSegs);
502	size_t virtioCoreSgBufCalcTotalLength(PCVIRTIOSGBUF pGcSgBuf);
503	void virtioCoreSgBufReset(PVIRTIOSGBUF pGcSgBuf);
504	size_t virtioCoreSgBufCalcTotalLength(PVIRTIOSGBUF pGcSgBuf);
505
506	int virtioCoreR3SaveExec(PVIRTIOCORE pVirtio, PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM);
507	int virtioCoreR3LoadExec(PVIRTIOCORE pVirtio, PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM);
508	void virtioCoreR3VmStateChanged(PVIRTIOCORE pVirtio, VIRTIOVMSTATECHANGED enmState);
509	void virtioCoreR3Term(PPDMDEVINS pDevIns, PVIRTIOCORE pVirtio, PVIRTIOCORECC pVirtioCC);
510	int virtioCoreR3Init(PPDMDEVINS pDevIns, PVIRTIOCORE pVirtio, PVIRTIOCORECC pVirtioCC, PVIRTIOPCIPARAMS pPciParams,
511	const char pcszInstance, uint64_t fDevSpecificFeatures, void pvDevSpecificCfg, uint16_t cbDevSpecificCfg);
512	int virtioCoreRZInit(PPDMDEVINS pDevIns, PVIRTIOCORE pVirtio);
513	const char *virtioCoreGetStateChangeText(VIRTIOVMSTATECHANGED enmState);
514
515	/** @} */
516
517
518	#endif /* !VBOX_INCLUDED_SRC_VirtIO_Virtio_1_0_h */

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source: vbox/trunk/src/VBox/Devices/VirtIO/Virtio_1_0.h@ 84803

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