DisasmFormatArmV8.cpp@ 105783

Last change on this file since 105783 was 105779, checked in by vboxsync, 3 months ago
Disassembler/ARMv8: Updates, decode more instructions, add them to the testcase, bugref:10394
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 28.5 KB

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1	/* $Id: DisasmFormatArmV8.cpp 105779 2024-08-21 16:39:51Z vboxsync $ */
2	/** @file
3	* VBox Disassembler - Yasm(/Nasm) Style Formatter.
4	*/
5
6	/*
7	* Copyright (C) 2008-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#include <VBox/dis.h>
33	#include "DisasmInternal.h"
34	#include "DisasmInternal-armv8.h"
35	#include <iprt/armv8.h>
36	#include <iprt/assert.h>
37	#include <iprt/ctype.h>
38	#include <iprt/errcore.h>
39	#include <iprt/string.h>
40
41
42	/*********************************************************************************************************************************
43	* Global Variables *
44	*********************************************************************************************************************************/
45	static const char g_szSpaces[] =
46	" ";
47	static const char g_aszArmV8RegGen32[32][4] =
48	{
49	"w0\0", "w1\0", "w2\0", "w3\0", "w4\0", "w5\0", "w6\0", "w7\0", "w8\0", "w9\0", "w10", "w11", "w12", "w13", "w14", "w15",
50	"w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wzr"
51	};
52	static const char g_aszArmV8RegGen64[32][4] =
53	{
54	"x0\0", "x1\0", "x2\0", "x3\0", "x4\0", "x5\0", "x6\0", "x7\0", "x8\0", "x9\0", "x10", "x11", "x12", "x13", "x14", "x15",
55	"x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "xzr"
56	};
57	static const char g_aszArmV8Cond[16][3] =
58	{
59	"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", "hi", "ls", "ge", "lt", "gt", "le", "al", "al"
60	};
61
62
63	/**
64	* List of known system registers.
65	*
66	* The list MUST be in ascending order of the system register ID!
67	*/
68	static const struct
69	{
70	/** IPRT system register ID. */
71	uint32_t idSysReg;
72	/** Name of the system register. */
73	const char *pszSysReg;
74	/** Character count of the system register name. */
75	size_t cchSysReg;
76	} g_aArmV8SysReg64[] =
77	{
78	#define DIS_ARMV8_SYSREG(a_idSysReg) { (ARMV8_AARCH64_SYSREG_ ## a_idSysReg), #a_idSysReg, sizeof(#a_idSysReg) - 1 }
79	DIS_ARMV8_SYSREG(OSDTRRX_EL1),
80	DIS_ARMV8_SYSREG(MDSCR_EL1),
81	//DIS_ARMV8_SYSREG(DBGBVRn_EL1(a_Id)),
82	//DIS_ARMV8_SYSREG(DBGBCRn_EL1(a_Id)),
83	//DIS_ARMV8_SYSREG(DBGWVRn_EL1(a_Id)),
84	//DIS_ARMV8_SYSREG(DBGWCRn_EL1(a_Id)),
85	DIS_ARMV8_SYSREG(MDCCINT_EL1),
86	DIS_ARMV8_SYSREG(OSDTRTX_EL1),
87	DIS_ARMV8_SYSREG(OSECCR_EL1),
88	DIS_ARMV8_SYSREG(MDRAR_EL1),
89	DIS_ARMV8_SYSREG(OSLAR_EL1),
90	DIS_ARMV8_SYSREG(OSLSR_EL1),
91	DIS_ARMV8_SYSREG(OSDLR_EL1),
92	DIS_ARMV8_SYSREG(MIDR_EL1),
93	DIS_ARMV8_SYSREG(MPIDR_EL1),
94	DIS_ARMV8_SYSREG(REVIDR_EL1),
95	DIS_ARMV8_SYSREG(ID_PFR0_EL1),
96	DIS_ARMV8_SYSREG(ID_PFR1_EL1),
97	DIS_ARMV8_SYSREG(ID_DFR0_EL1),
98	DIS_ARMV8_SYSREG(ID_AFR0_EL1),
99	DIS_ARMV8_SYSREG(ID_MMFR0_EL1),
100	DIS_ARMV8_SYSREG(ID_MMFR1_EL1),
101	DIS_ARMV8_SYSREG(ID_MMFR2_EL1),
102	DIS_ARMV8_SYSREG(ID_MMFR3_EL1),
103	DIS_ARMV8_SYSREG(ID_ISAR0_EL1),
104	DIS_ARMV8_SYSREG(ID_ISAR1_EL1),
105	DIS_ARMV8_SYSREG(ID_ISAR2_EL1),
106	DIS_ARMV8_SYSREG(ID_ISAR3_EL1),
107	DIS_ARMV8_SYSREG(ID_ISAR4_EL1),
108	DIS_ARMV8_SYSREG(ID_ISAR5_EL1),
109	DIS_ARMV8_SYSREG(ID_MMFR4_EL1),
110	DIS_ARMV8_SYSREG(ID_ISAR6_EL1),
111	DIS_ARMV8_SYSREG(MVFR0_EL1),
112	DIS_ARMV8_SYSREG(MVFR1_EL1),
113	DIS_ARMV8_SYSREG(MVFR2_EL1),
114	DIS_ARMV8_SYSREG(ID_PFR2_EL1),
115	DIS_ARMV8_SYSREG(ID_DFR1_EL1),
116	DIS_ARMV8_SYSREG(ID_MMFR5_EL1),
117	DIS_ARMV8_SYSREG(ID_AA64PFR0_EL1),
118	DIS_ARMV8_SYSREG(ID_AA64PFR1_EL1),
119	DIS_ARMV8_SYSREG(ID_AA64ZFR0_EL1),
120	DIS_ARMV8_SYSREG(ID_AA64SMFR0_EL1),
121	DIS_ARMV8_SYSREG(ID_AA64DFR0_EL1),
122	DIS_ARMV8_SYSREG(ID_AA64DFR1_EL1),
123	DIS_ARMV8_SYSREG(ID_AA64AFR0_EL1),
124	DIS_ARMV8_SYSREG(ID_AA64AFR1_EL1),
125	DIS_ARMV8_SYSREG(ID_AA64ISAR0_EL1),
126	DIS_ARMV8_SYSREG(ID_AA64ISAR1_EL1),
127	DIS_ARMV8_SYSREG(ID_AA64ISAR2_EL1),
128	DIS_ARMV8_SYSREG(ID_AA64MMFR0_EL1),
129	DIS_ARMV8_SYSREG(ID_AA64MMFR1_EL1),
130	DIS_ARMV8_SYSREG(ID_AA64MMFR2_EL1),
131	DIS_ARMV8_SYSREG(SCTRL_EL1),
132	DIS_ARMV8_SYSREG(ACTRL_EL1),
133	DIS_ARMV8_SYSREG(CPACR_EL1),
134	DIS_ARMV8_SYSREG(RGSR_EL1),
135	DIS_ARMV8_SYSREG(GCR_EL1),
136	DIS_ARMV8_SYSREG(ZCR_EL1),
137	DIS_ARMV8_SYSREG(TRFCR_EL1),
138	DIS_ARMV8_SYSREG(SMPRI_EL1),
139	DIS_ARMV8_SYSREG(SMCR_EL1),
140	DIS_ARMV8_SYSREG(TTBR0_EL1),
141	DIS_ARMV8_SYSREG(TTBR1_EL1),
142	DIS_ARMV8_SYSREG(TCR_EL1),
143	DIS_ARMV8_SYSREG(APIAKeyLo_EL1),
144	DIS_ARMV8_SYSREG(APIAKeyHi_EL1),
145	DIS_ARMV8_SYSREG(APIBKeyLo_EL1),
146	DIS_ARMV8_SYSREG(APIBKeyHi_EL1),
147	DIS_ARMV8_SYSREG(APDAKeyLo_EL1),
148	DIS_ARMV8_SYSREG(APDAKeyHi_EL1),
149	DIS_ARMV8_SYSREG(APDBKeyLo_EL1),
150	DIS_ARMV8_SYSREG(APDBKeyHi_EL1),
151	DIS_ARMV8_SYSREG(APGAKeyLo_EL1),
152	DIS_ARMV8_SYSREG(APGAKeyHi_EL1),
153	DIS_ARMV8_SYSREG(SPSR_EL1),
154	DIS_ARMV8_SYSREG(ELR_EL1),
155	DIS_ARMV8_SYSREG(SP_EL0),
156	DIS_ARMV8_SYSREG(SPSEL),
157	DIS_ARMV8_SYSREG(CURRENTEL),
158	DIS_ARMV8_SYSREG(PAN),
159	DIS_ARMV8_SYSREG(UAO),
160	DIS_ARMV8_SYSREG(ALLINT),
161	DIS_ARMV8_SYSREG(ICC_PMR_EL1),
162	DIS_ARMV8_SYSREG(AFSR0_EL1),
163	DIS_ARMV8_SYSREG(AFSR1_EL1),
164	DIS_ARMV8_SYSREG(ESR_EL1),
165	DIS_ARMV8_SYSREG(ERRIDR_EL1),
166	DIS_ARMV8_SYSREG(ERRSELR_EL1),
167	DIS_ARMV8_SYSREG(FAR_EL1),
168	DIS_ARMV8_SYSREG(PAR_EL1),
169	DIS_ARMV8_SYSREG(MAIR_EL1),
170	DIS_ARMV8_SYSREG(AMAIR_EL1),
171	DIS_ARMV8_SYSREG(VBAR_EL1),
172	DIS_ARMV8_SYSREG(ICC_IAR0_EL1),
173	DIS_ARMV8_SYSREG(ICC_EOIR0_EL1),
174	DIS_ARMV8_SYSREG(ICC_HPPIR0_EL1),
175	DIS_ARMV8_SYSREG(ICC_BPR0_EL1),
176	DIS_ARMV8_SYSREG(ICC_AP0R0_EL1),
177	DIS_ARMV8_SYSREG(ICC_AP0R1_EL1),
178	DIS_ARMV8_SYSREG(ICC_AP0R2_EL1),
179	DIS_ARMV8_SYSREG(ICC_AP0R3_EL1),
180	DIS_ARMV8_SYSREG(ICC_AP1R0_EL1),
181	DIS_ARMV8_SYSREG(ICC_AP1R1_EL1),
182	DIS_ARMV8_SYSREG(ICC_AP1R2_EL1),
183	DIS_ARMV8_SYSREG(ICC_AP1R3_EL1),
184	DIS_ARMV8_SYSREG(ICC_NMIAR1_EL1),
185	DIS_ARMV8_SYSREG(ICC_DIR_EL1),
186	DIS_ARMV8_SYSREG(ICC_RPR_EL1),
187	DIS_ARMV8_SYSREG(ICC_SGI1R_EL1),
188	DIS_ARMV8_SYSREG(ICC_ASGI1R_EL1),
189	DIS_ARMV8_SYSREG(ICC_SGI0R_EL1),
190	DIS_ARMV8_SYSREG(ICC_IAR1_EL1),
191	DIS_ARMV8_SYSREG(ICC_EOIR1_EL1),
192	DIS_ARMV8_SYSREG(ICC_HPPIR1_EL1),
193	DIS_ARMV8_SYSREG(ICC_BPR1_EL1),
194	DIS_ARMV8_SYSREG(ICC_CTLR_EL1),
195	DIS_ARMV8_SYSREG(ICC_SRE_EL1),
196	DIS_ARMV8_SYSREG(ICC_IGRPEN0_EL1),
197	DIS_ARMV8_SYSREG(ICC_IGRPEN1_EL1),
198	DIS_ARMV8_SYSREG(CONTEXTIDR_EL1),
199	DIS_ARMV8_SYSREG(TPIDR_EL1),
200	DIS_ARMV8_SYSREG(CNTKCTL_EL1),
201	DIS_ARMV8_SYSREG(CSSELR_EL1),
202	DIS_ARMV8_SYSREG(NZCV),
203	DIS_ARMV8_SYSREG(DAIF),
204	DIS_ARMV8_SYSREG(SVCR),
205	DIS_ARMV8_SYSREG(DIT),
206	DIS_ARMV8_SYSREG(SSBS),
207	DIS_ARMV8_SYSREG(TCO),
208	DIS_ARMV8_SYSREG(FPCR),
209	DIS_ARMV8_SYSREG(FPSR),
210	DIS_ARMV8_SYSREG(ICC_SRE_EL2),
211	DIS_ARMV8_SYSREG(TPIDR_EL0),
212	DIS_ARMV8_SYSREG(TPIDRRO_EL0),
213	DIS_ARMV8_SYSREG(CNTFRQ_EL0),
214	DIS_ARMV8_SYSREG(CNTVCT_EL0),
215	DIS_ARMV8_SYSREG(CNTP_TVAL_EL0),
216	DIS_ARMV8_SYSREG(CNTP_CTL_EL0),
217	DIS_ARMV8_SYSREG(CNTP_CVAL_EL0),
218	DIS_ARMV8_SYSREG(CNTV_CTL_EL0),
219	DIS_ARMV8_SYSREG(VPIDR_EL2),
220	DIS_ARMV8_SYSREG(VMPIDR_EL2),
221	DIS_ARMV8_SYSREG(SCTLR_EL2),
222	DIS_ARMV8_SYSREG(ACTLR_EL2),
223	DIS_ARMV8_SYSREG(HCR_EL2),
224	DIS_ARMV8_SYSREG(MDCR_EL2),
225	DIS_ARMV8_SYSREG(CPTR_EL2),
226	DIS_ARMV8_SYSREG(HSTR_EL2),
227	DIS_ARMV8_SYSREG(HFGRTR_EL2),
228	DIS_ARMV8_SYSREG(HFGWTR_EL2),
229	DIS_ARMV8_SYSREG(HFGITR_EL2),
230	DIS_ARMV8_SYSREG(HACR_EL2),
231	DIS_ARMV8_SYSREG(ZCR_EL2),
232	DIS_ARMV8_SYSREG(TRFCR_EL2),
233	DIS_ARMV8_SYSREG(HCRX_EL2),
234	DIS_ARMV8_SYSREG(SDER32_EL2),
235	DIS_ARMV8_SYSREG(TTBR0_EL2),
236	DIS_ARMV8_SYSREG(TTBR1_EL2),
237	DIS_ARMV8_SYSREG(TCR_EL2),
238	DIS_ARMV8_SYSREG(VTTBR_EL2),
239	DIS_ARMV8_SYSREG(VTCR_EL2),
240	DIS_ARMV8_SYSREG(VNCR_EL2),
241	DIS_ARMV8_SYSREG(VSTTBR_EL2),
242	DIS_ARMV8_SYSREG(VSTCR_EL2),
243	DIS_ARMV8_SYSREG(DACR32_EL2),
244	DIS_ARMV8_SYSREG(HDFGRTR_EL2),
245	DIS_ARMV8_SYSREG(HDFGWTR_EL2),
246	DIS_ARMV8_SYSREG(HAFGRTR_EL2),
247	DIS_ARMV8_SYSREG(SPSR_EL2),
248	DIS_ARMV8_SYSREG(ELR_EL2),
249	DIS_ARMV8_SYSREG(SP_EL1),
250	DIS_ARMV8_SYSREG(IFSR32_EL2),
251	DIS_ARMV8_SYSREG(AFSR0_EL2),
252	DIS_ARMV8_SYSREG(AFSR1_EL2),
253	DIS_ARMV8_SYSREG(ESR_EL2),
254	DIS_ARMV8_SYSREG(VSESR_EL2),
255	DIS_ARMV8_SYSREG(FPEXC32_EL2),
256	DIS_ARMV8_SYSREG(TFSR_EL2),
257	DIS_ARMV8_SYSREG(FAR_EL2),
258	DIS_ARMV8_SYSREG(HPFAR_EL2),
259	DIS_ARMV8_SYSREG(PMSCR_EL2),
260	DIS_ARMV8_SYSREG(MAIR_EL2),
261	DIS_ARMV8_SYSREG(AMAIR_EL2),
262	DIS_ARMV8_SYSREG(MPAMHCR_EL2),
263	DIS_ARMV8_SYSREG(MPAMVPMV_EL2),
264	DIS_ARMV8_SYSREG(MPAM2_EL2),
265	DIS_ARMV8_SYSREG(MPAMVPM0_EL2),
266	DIS_ARMV8_SYSREG(MPAMVPM1_EL2),
267	DIS_ARMV8_SYSREG(MPAMVPM2_EL2),
268	DIS_ARMV8_SYSREG(MPAMVPM3_EL2),
269	DIS_ARMV8_SYSREG(MPAMVPM4_EL2),
270	DIS_ARMV8_SYSREG(MPAMVPM5_EL2),
271	DIS_ARMV8_SYSREG(MPAMVPM6_EL2),
272	DIS_ARMV8_SYSREG(MPAMVPM7_EL2),
273	DIS_ARMV8_SYSREG(VBAR_EL2),
274	DIS_ARMV8_SYSREG(RVBAR_EL2),
275	DIS_ARMV8_SYSREG(RMR_EL2),
276	DIS_ARMV8_SYSREG(VDISR_EL2),
277	DIS_ARMV8_SYSREG(CONTEXTIDR_EL2),
278	DIS_ARMV8_SYSREG(TPIDR_EL2),
279	DIS_ARMV8_SYSREG(SCXTNUM_EL2),
280	DIS_ARMV8_SYSREG(CNTVOFF_EL2),
281	DIS_ARMV8_SYSREG(CNTPOFF_EL2),
282	DIS_ARMV8_SYSREG(CNTHCTL_EL2),
283	DIS_ARMV8_SYSREG(CNTHP_TVAL_EL2),
284	DIS_ARMV8_SYSREG(CNTHP_CTL_EL2),
285	DIS_ARMV8_SYSREG(CNTHP_CVAL_EL2),
286	DIS_ARMV8_SYSREG(CNTHV_TVAL_EL2),
287	DIS_ARMV8_SYSREG(CNTHV_CTL_EL2),
288	DIS_ARMV8_SYSREG(CNTHV_CVAL_EL2),
289	DIS_ARMV8_SYSREG(CNTHVS_TVAL_EL2),
290	DIS_ARMV8_SYSREG(CNTHVS_CTL_EL2),
291	DIS_ARMV8_SYSREG(CNTHVS_CVAL_EL2),
292	DIS_ARMV8_SYSREG(CNTHPS_TVAL_EL2),
293	DIS_ARMV8_SYSREG(CNTHPS_CTL_EL2),
294	DIS_ARMV8_SYSREG(CNTHPS_CVAL_EL2),
295	DIS_ARMV8_SYSREG(SP_EL2)
296	#undef DIS_ARMV8_SYSREG
297	};
298
299
300	/**
301	* Gets the base register name for the given parameter.
302	*
303	* @returns Pointer to the register name.
304	* @param pDis The disassembler state.
305	* @param pParam The parameter.
306	* @param pcchReg Where to store the length of the name.
307	*/
308	static const char disasmFormatArmV8Reg(PCDISSTATE pDis, PCDISOPPARAM pParam, size_t pcchReg)
309	{
310	RT_NOREF_PV(pDis);
311
312	switch (pParam->fUse & ( DISUSE_REG_GEN8 \| DISUSE_REG_GEN16 \| DISUSE_REG_GEN32 \| DISUSE_REG_GEN64
313	\| DISUSE_REG_FP \| DISUSE_REG_MMX \| DISUSE_REG_XMM \| DISUSE_REG_YMM
314	\| DISUSE_REG_CR \| DISUSE_REG_DBG \| DISUSE_REG_SEG \| DISUSE_REG_TEST))
315
316	{
317	case DISUSE_REG_GEN32:
318	{
319	Assert(pParam->armv8.Reg.idxGenReg < RT_ELEMENTS(g_aszArmV8RegGen32));
320	const char *psz = g_aszArmV8RegGen32[pParam->armv8.Reg.idxGenReg];
321	*pcchReg = 2 + !!psz[2];
322	return psz;
323	}
324
325	case DISUSE_REG_GEN64:
326	{
327	Assert(pParam->armv8.Reg.idxGenReg < RT_ELEMENTS(g_aszArmV8RegGen64));
328	const char *psz = g_aszArmV8RegGen64[pParam->armv8.Reg.idxGenReg];
329	*pcchReg = 2 + !!psz[2];
330	return psz;
331	}
332
333	default:
334	AssertMsgFailed(("%#x\n", pParam->fUse));
335	*pcchReg = 3;
336	return "r??";
337	}
338	}
339
340
341	/**
342	* Gets the base register name for the given parameter.
343	*
344	* @returns Pointer to the register name.
345	* @param pDis The disassembler state.
346	* @param pParam The parameter.
347	* @param pachTmp Pointer to temporary string storage when building
348	* the register name.
349	* @param pcchReg Where to store the length of the name.
350	*/
351	static const char disasmFormatArmV8SysReg(PCDISSTATE pDis, PCDISOPPARAM pParam, char pachTmp, size_t *pcchReg)
352	{
353	RT_NOREF_PV(pDis);
354
355	/* Try to find the system register ID in the table. */
356	/** @todo Binary search (lazy). */
357	for (uint32_t i = 0; i < RT_ELEMENTS(g_aArmV8SysReg64); i++)
358	{
359	if (g_aArmV8SysReg64[i].idSysReg == pParam->armv8.Reg.idSysReg)
360	{
361	*pcchReg = g_aArmV8SysReg64[i].cchSysReg;
362	return g_aArmV8SysReg64[i].pszSysReg;
363	}
364	}
365
366	/* Generate S<op0>_<op1>_<Cn>_<Cm>_<op2> identifier. */
367	uint32_t const idSysReg = pParam->armv8.Reg.idSysReg;
368	uint8_t idx = 0;
369	pachTmp[idx++] = 'S';
370	pachTmp[idx++] = '2' + ((idSysReg >> 14) & 0x1);
371	pachTmp[idx++] = '_';
372	pachTmp[idx++] = '0' + ((idSysReg >> 11) & 0x7);
373	pachTmp[idx++] = '_';
374
375	uint8_t bTmp = (idSysReg >> 7) & 0xf;
376	if (bTmp >= 10)
377	{
378	pachTmp[idx++] = '1' + (bTmp - 10);
379	bTmp -= 10;
380	}
381	pachTmp[idx++] = '0' + bTmp;
382	pachTmp[idx++] = '_';
383
384	bTmp = (idSysReg >> 3) & 0xf;
385	if (bTmp >= 10)
386	{
387	pachTmp[idx++] = '1' + (bTmp - 10);
388	bTmp -= 10;
389	}
390	pachTmp[idx++] = '0' + bTmp;
391
392	pachTmp[idx++] = '_';
393	pachTmp[idx++] = '0' + (idSysReg & 0x7);
394	pachTmp[idx] = '\0';
395	*pcchReg = idx;
396	return pachTmp;
397	}
398
399
400	/**
401	* Formats the current instruction in Yasm (/ Nasm) style.
402	*
403	*
404	* @returns The number of output characters. If this is >= cchBuf, then the content
405	* of pszBuf will be truncated.
406	* @param pDis Pointer to the disassembler state.
407	* @param pszBuf The output buffer.
408	* @param cchBuf The size of the output buffer.
409	* @param fFlags Format flags, see DIS_FORMAT_FLAGS_*.
410	* @param pfnGetSymbol Get symbol name for a jmp or call target address. Optional.
411	* @param pvUser User argument for pfnGetSymbol.
412	*/
413	DISDECL(size_t) DISFormatArmV8Ex(PCDISSTATE pDis, char *pszBuf, size_t cchBuf, uint32_t fFlags,
414	PFNDISGETSYMBOL pfnGetSymbol, void *pvUser)
415	{
416	/*
417	* Input validation and massaging.
418	*/
419	AssertPtr(pDis);
420	AssertPtrNull(pszBuf);
421	Assert(pszBuf \|\| !cchBuf);
422	AssertPtrNull(pfnGetSymbol);
423	AssertMsg(DIS_FMT_FLAGS_IS_VALID(fFlags), ("%#x\n", fFlags));
424	if (fFlags & DIS_FMT_FLAGS_ADDR_COMMENT)
425	fFlags = (fFlags & ~DIS_FMT_FLAGS_ADDR_LEFT) \| DIS_FMT_FLAGS_ADDR_RIGHT;
426	if (fFlags & DIS_FMT_FLAGS_BYTES_COMMENT)
427	fFlags = (fFlags & ~DIS_FMT_FLAGS_BYTES_LEFT) \| DIS_FMT_FLAGS_BYTES_RIGHT;
428
429	PCDISOPCODE const pOp = pDis->pCurInstr;
430
431	/*
432	* Output macros
433	*/
434	char *pszDst = pszBuf;
435	size_t cchDst = cchBuf;
436	size_t cchOutput = 0;
437	#define PUT_C(ch) \
438	do { \
439	cchOutput++; \
440	if (cchDst > 1) \
441	{ \
442	cchDst--; \
443	*pszDst++ = (ch); \
444	} \
445	} while (0)
446	#define PUT_STR(pszSrc, cchSrc) \
447	do { \
448	cchOutput += (cchSrc); \
449	if (cchDst > (cchSrc)) \
450	{ \
451	memcpy(pszDst, (pszSrc), (cchSrc)); \
452	pszDst += (cchSrc); \
453	cchDst -= (cchSrc); \
454	} \
455	else if (cchDst > 1) \
456	{ \
457	memcpy(pszDst, (pszSrc), cchDst - 1); \
458	pszDst += cchDst - 1; \
459	cchDst = 1; \
460	} \
461	} while (0)
462	#define PUT_SZ(sz) \
463	PUT_STR((sz), sizeof(sz) - 1)
464	#define PUT_SZ_STRICT(szStrict, szRelaxed) \
465	do { if (fFlags & DIS_FMT_FLAGS_STRICT) PUT_SZ(szStrict); else PUT_SZ(szRelaxed); } while (0)
466	#define PUT_PSZ(psz) \
467	do { const size_t cchTmp = strlen(psz); PUT_STR((psz), cchTmp); } while (0)
468	#define PUT_NUM(cch, fmt, num) \
469	do { \
470	cchOutput += (cch); \
471	if (cchDst > 1) \
472	{ \
473	const size_t cchTmp = RTStrPrintf(pszDst, cchDst, fmt, (num)); \
474	pszDst += cchTmp; \
475	cchDst -= cchTmp; \
476	Assert(cchTmp == (cch) \|\| cchDst == 1); \
477	} \
478	} while (0)
479	/** @todo add two flags for choosing between %X / %x and h / 0x. */
480	#define PUT_NUM_8(num) PUT_NUM(4, "0x%02x", (uint8_t)(num))
481	#define PUT_NUM_16(num) PUT_NUM(6, "0x%04x", (uint16_t)(num))
482	#define PUT_NUM_32(num) PUT_NUM(10, "0x%08x", (uint32_t)(num))
483	#define PUT_NUM_64(num) PUT_NUM(18, "0x%016RX64", (uint64_t)(num))
484
485	#define PUT_NUM_SIGN(cch, fmt, num, stype, utype) \
486	do { \
487	if ((stype)(num) >= 0) \
488	{ \
489	PUT_C('+'); \
490	PUT_NUM(cch, fmt, (utype)(num)); \
491	} \
492	else \
493	{ \
494	PUT_C('-'); \
495	PUT_NUM(cch, fmt, (utype)-(stype)(num)); \
496	} \
497	} while (0)
498	#define PUT_NUM_S8(num) PUT_NUM_SIGN(4, "0x%02x", num, int8_t, uint8_t)
499	#define PUT_NUM_S16(num) PUT_NUM_SIGN(6, "0x%04x", num, int16_t, uint16_t)
500	#define PUT_NUM_S32(num) PUT_NUM_SIGN(10, "0x%08x", num, int32_t, uint32_t)
501	#define PUT_NUM_S64(num) PUT_NUM_SIGN(18, "0x%016RX64", num, int64_t, uint64_t)
502
503	#define PUT_SYMBOL_TWO(a_rcSym, a_szStart, a_chEnd) \
504	do { \
505	if (RT_SUCCESS(a_rcSym)) \
506	{ \
507	PUT_SZ(a_szStart); \
508	PUT_PSZ(szSymbol); \
509	if (off != 0) \
510	{ \
511	if ((int8_t)off == off) \
512	PUT_NUM_S8(off); \
513	else if ((int16_t)off == off) \
514	PUT_NUM_S16(off); \
515	else if ((int32_t)off == off) \
516	PUT_NUM_S32(off); \
517	else \
518	PUT_NUM_S64(off); \
519	} \
520	PUT_C(a_chEnd); \
521	} \
522	} while (0)
523
524	#define PUT_SYMBOL(a_uSeg, a_uAddr, a_szStart, a_chEnd) \
525	do { \
526	if (pfnGetSymbol) \
527	{ \
528	int rcSym = pfnGetSymbol(pDis, a_uSeg, a_uAddr, szSymbol, sizeof(szSymbol), &off, pvUser); \
529	PUT_SYMBOL_TWO(rcSym, a_szStart, a_chEnd); \
530	} \
531	} while (0)
532
533
534	/*
535	* The address?
536	*/
537	if (fFlags & DIS_FMT_FLAGS_ADDR_LEFT)
538	{
539	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
540	if (pDis->uInstrAddr >= _4G)
541	PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
542	#endif
543	PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
544	PUT_C(' ');
545	}
546
547	/*
548	* The opcode bytes?
549	*/
550	if (fFlags & DIS_FMT_FLAGS_BYTES_LEFT)
551	{
552	size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
553	cchOutput += cchTmp;
554	if (cchDst > 1)
555	{
556	if (cchTmp <= cchDst)
557	{
558	cchDst -= cchTmp;
559	pszDst += cchTmp;
560	}
561	else
562	{
563	pszDst += cchDst - 1;
564	cchDst = 1;
565	}
566	}
567
568	/* Some padding to align the instruction. */
569	size_t cchPadding = (7 * (2 + !!(fFlags & DIS_FMT_FLAGS_BYTES_SPACED)))
570	+ !!(fFlags & DIS_FMT_FLAGS_BYTES_BRACKETS) * 2
571	+ 2;
572	cchPadding = cchTmp + 1 >= cchPadding ? 1 : cchPadding - cchTmp;
573	PUT_STR(g_szSpaces, cchPadding);
574	}
575
576
577	/*
578	* Filter out invalid opcodes first as they need special
579	* treatment. UDF is an exception and should be handled normally.
580	*/
581	size_t const offInstruction = cchOutput;
582	if (pOp->uOpcode == OP_INVALID)
583	PUT_SZ("Illegal opcode");
584	else
585	{
586	/* Start with the instruction. */
587	PUT_PSZ(pOp->pszOpcode);
588
589	/* Add any conditionals. */
590	if (pDis->armv8.enmCond != kDisArmv8InstrCond_Al)
591	{
592	PUT_C('.');
593	Assert((uint16_t)pDis->armv8.enmCond < RT_ELEMENTS(g_aszArmV8Cond));
594	PUT_STR(g_aszArmV8Cond[pDis->armv8.enmCond], sizeof(g_aszArmV8Cond[0]) - 1);
595	}
596
597	/*
598	* Format the parameters.
599	*/
600	RTINTPTR off;
601	char szSymbol[128];
602	for (uint32_t i = 0; i < RT_ELEMENTS(pDis->aParams); i++)
603	{
604	PCDISOPPARAM pParam = &pDis->aParams[i];
605
606	/* First None parameter marks end of parameters. */
607	if (pParam->armv8.enmType == kDisArmv8OpParmNone)
608	break;
609
610	if (i > 0)
611	PUT_C(',');
612	PUT_C(' '); /** @todo Make the indenting configurable. */
613
614	switch (pParam->armv8.enmType)
615	{
616	case kDisArmv8OpParmImm:
617	{
618	PUT_C('#');
619	switch (pParam->fUse & ( DISUSE_IMMEDIATE8 \| DISUSE_IMMEDIATE16 \| DISUSE_IMMEDIATE32 \| DISUSE_IMMEDIATE64
620	\| DISUSE_IMMEDIATE16_SX8 \| DISUSE_IMMEDIATE32_SX8 \| DISUSE_IMMEDIATE64_SX8))
621	{
622	case DISUSE_IMMEDIATE8:
623	PUT_NUM_8(pParam->uValue);
624	break;
625	case DISUSE_IMMEDIATE16:
626	PUT_NUM_16(pParam->uValue);
627	break;
628	case DISUSE_IMMEDIATE16_SX8:
629	PUT_NUM_16(pParam->uValue);
630	break;
631	case DISUSE_IMMEDIATE32:
632	PUT_NUM_32(pParam->uValue);
633	/** @todo Symbols */
634	break;
635	case DISUSE_IMMEDIATE32_SX8:
636	PUT_NUM_32(pParam->uValue);
637	break;
638	case DISUSE_IMMEDIATE64_SX8:
639	PUT_NUM_64(pParam->uValue);
640	break;
641	case DISUSE_IMMEDIATE64:
642	PUT_NUM_64(pParam->uValue);
643	/** @todo Symbols */
644	break;
645	default:
646	AssertFailed();
647	break;
648	}
649	break;
650	}
651	case kDisArmv8OpParmImmRel:
652	/case kDisParmParseImmAdr:/
653	{
654	int32_t offDisplacement;
655
656	PUT_C('#');
657	if (pParam->fUse & DISUSE_IMMEDIATE8_REL)
658	{
659	offDisplacement = (int8_t)pParam->uValue;
660	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
661	PUT_NUM_S8(offDisplacement * sizeof(uint32_t));
662	}
663	else if (pParam->fUse & DISUSE_IMMEDIATE16_REL)
664	{
665	offDisplacement = (int16_t)pParam->uValue;
666	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
667	PUT_NUM_S16(offDisplacement * sizeof(uint32_t));
668	}
669	else
670	{
671	offDisplacement = (int32_t)pParam->uValue;
672	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
673	PUT_NUM_S32(offDisplacement * sizeof(uint32_t));
674	}
675	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
676	PUT_SZ(" ; (");
677
678	RTUINTPTR uTrgAddr = pDis->uInstrAddr + (offDisplacement * sizeof(uint32_t));
679	if ( pDis->uCpuMode == DISCPUMODE_ARMV8_A32
680	\|\| pDis->uCpuMode == DISCPUMODE_ARMV8_T32)
681	PUT_NUM_32(uTrgAddr);
682	else if (pDis->uCpuMode == DISCPUMODE_ARMV8_A64)
683	PUT_NUM_64(uTrgAddr);
684	else
685	AssertReleaseFailed();
686
687	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
688	{
689	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " = ", ' ');
690	PUT_C(')');
691	}
692	else
693	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " (", ')');
694	break;
695	}
696	case kDisArmv8OpParmGpr:
697	{
698	Assert(!(pParam->fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32)));
699
700	size_t cchReg;
701	const char *pszReg = disasmFormatArmV8Reg(pDis, pParam, &cchReg);
702	PUT_STR(pszReg, cchReg);
703	break;
704	}
705	case kDisArmv8OpParmSysReg:
706	{
707	Assert(pParam->fUse == DISUSE_REG_SYSTEM);
708
709	size_t cchReg;
710	char achTmp[32];
711	const char *pszReg = disasmFormatArmV8SysReg(pDis, pParam, &achTmp[0], &cchReg);
712	PUT_STR(pszReg, cchReg);
713	break;
714	}
715	default:
716	AssertFailed();
717	}
718
719	if (pParam->armv8.enmShift != kDisArmv8OpParmShiftNone)
720	{
721	Assert( pParam->armv8.enmType == kDisArmv8OpParmImm
722	\|\| pParam->armv8.enmType == kDisArmv8OpParmGpr);
723	PUT_SZ(", ");
724	switch (pParam->armv8.enmShift)
725	{
726	case kDisArmv8OpParmShiftLeft:
727	PUT_SZ("LSL #");
728	break;
729	case kDisArmv8OpParmShiftRight:
730	PUT_SZ("LSR #");
731	break;
732	case kDisArmv8OpParmShiftArithRight:
733	PUT_SZ("ASR #");
734	break;
735	case kDisArmv8OpParmShiftRotate:
736	PUT_SZ("ROR #");
737	break;
738	default:
739	AssertFailed();
740	}
741	PUT_NUM_8(pParam->armv8.cShift);
742	}
743	}
744	}
745
746	/*
747	* Any additional output to the right of the instruction?
748	*/
749	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
750	{
751	/* some up front padding. */
752	size_t cchPadding = cchOutput - offInstruction;
753	cchPadding = cchPadding + 1 >= 42 ? 1 : 42 - cchPadding;
754	PUT_STR(g_szSpaces, cchPadding);
755
756	/* comment? */
757	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
758	PUT_SZ(";");
759
760	/*
761	* The address?
762	*/
763	if (fFlags & DIS_FMT_FLAGS_ADDR_RIGHT)
764	{
765	PUT_C(' ');
766	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
767	if (pDis->uInstrAddr >= _4G)
768	PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
769	#endif
770	PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
771	}
772
773	/*
774	* Opcode bytes?
775	*/
776	if (fFlags & DIS_FMT_FLAGS_BYTES_RIGHT)
777	{
778	PUT_C(' ');
779	size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
780	cchOutput += cchTmp;
781	if (cchTmp >= cchDst)
782	cchTmp = cchDst - (cchDst != 0);
783	cchDst -= cchTmp;
784	pszDst += cchTmp;
785	}
786	}
787
788	/*
789	* Terminate it - on overflow we'll have reserved one byte for this.
790	*/
791	if (cchDst > 0)
792	*pszDst = '\0';
793	else
794	Assert(!cchBuf);
795
796	/* clean up macros */
797	#undef PUT_PSZ
798	#undef PUT_SZ
799	#undef PUT_STR
800	#undef PUT_C
801	return cchOutput;
802	}
803
804
805	/**
806	* Formats the current instruction in Yasm (/ Nasm) style.
807	*
808	* This is a simplified version of DISFormatYasmEx() provided for your convenience.
809	*
810	*
811	* @returns The number of output characters. If this is >= cchBuf, then the content
812	* of pszBuf will be truncated.
813	* @param pDis Pointer to the disassembler state.
814	* @param pszBuf The output buffer.
815	* @param cchBuf The size of the output buffer.
816	*/
817	DISDECL(size_t) DISFormatArmV8(PCDISSTATE pDis, char *pszBuf, size_t cchBuf)
818	{
819	return DISFormatArmV8Ex(pDis, pszBuf, cchBuf, 0 /* fFlags /, NULL / pfnGetSymbol /, NULL / pvUser */);
820	}

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source: vbox/trunk/src/VBox/Disassembler/DisasmFormatArmV8.cpp@ 105783

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