DisasmFormatArmV8.cpp@ 106718

Last change on this file since 106718 was 106657, checked in by vboxsync, 3 months ago
Disassembler: Decode pre-indexed load instructions, bugref:10394
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
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1	/* $Id: DisasmFormatArmV8.cpp 106657 2024-10-24 12:42:39Z vboxsync $ */
2	/** @file
3	* VBox Disassembler - ARMv8 Style Formatter.
4	*/
5
6	/*
7	* Copyright (C) 2008-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#include <VBox/dis.h>
33	#include "DisasmInternal.h"
34	#include "DisasmInternal-armv8.h"
35	#include <iprt/armv8.h>
36	#include <iprt/assert.h>
37	#include <iprt/ctype.h>
38	#include <iprt/errcore.h>
39	#include <iprt/string.h>
40
41
42	/*********************************************************************************************************************************
43	* Global Variables *
44	*********************************************************************************************************************************/
45	static const char g_szSpaces[] =
46	" ";
47	static const char g_aszArmV8RegGen32[32][4] =
48	{
49	"w0\0", "w1\0", "w2\0", "w3\0", "w4\0", "w5\0", "w6\0", "w7\0", "w8\0", "w9\0", "w10", "w11", "w12", "w13", "w14", "w15",
50	"w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wzr"
51	};
52	static const char g_aszArmV8RegGen64[32][4] =
53	{
54	"x0\0", "x1\0", "x2\0", "x3\0", "x4\0", "x5\0", "x6\0", "x7\0", "x8\0", "x9\0", "x10", "x11", "x12", "x13", "x14", "x15",
55	"x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "xzr"
56	};
57	static const char g_aszArmV8RegFpSingle[32][4] =
58	{
59	"s0\0", "s1\0", "s2\0", "s3\0", "s4\0", "s5\0", "s6\0", "s7\0", "s8\0", "s9\0", "s10", "s11", "s12", "s13", "s14", "s15",
60	"s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31"
61	};
62	static const char g_aszArmV8RegFpDouble[32][4] =
63	{
64	"d0\0", "d1\0", "d2\0", "d3\0", "d4\0", "d5\0", "d6\0", "d7\0", "d8\0", "d9\0", "d10", "d11", "d12", "d13", "d14", "d15",
65	"d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31"
66	};
67	static const char g_aszArmV8RegFpHalf[32][4] =
68	{
69	"h0\0", "h1\0", "h2\0", "h3\0", "h4\0", "h5\0", "h6\0", "h7\0", "h8\0", "h9\0", "h10", "h11", "h12", "h13", "h14", "h15",
70	"h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23", "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31"
71	};
72	static const char g_aszArmV8RegSimdScalar128Bit[32][4] =
73	{
74	"q0\0", "q1\0", "q2\0", "q3\0", "q4\0", "q5\0", "q6\0", "q7\0", "q8\0", "q9\0", "q10", "q11", "q12", "q13", "q14", "q15",
75	"q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23", "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31"
76	};
77	static const char g_aszArmV8Cond[16][3] =
78	{
79	"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", "hi", "ls", "ge", "lt", "gt", "le", "al", "al"
80	};
81	static const char *g_apszArmV8PState[] =
82	{
83	/* kDisArmv8InstrPState_SPSel */ "spsel",
84	/* kDisArmv8InstrPState_DAIFSet */ "daifset",
85	/* kDisArmv8InstrPState_DAIFClr */ "daifclr",
86	/* kDisArmv8InstrPState_UAO */ "uao",
87	/* kDisArmv8InstrPState_PAN */ "pan",
88	/* kDisArmv8InstrPState_ALLINT */ "allint",
89	/* kDisArmv8InstrPState_PM */ "pm",
90	/* kDisArmv8InstrPState_SSBS */ "ssbs",
91	/* kDisArmv8InstrPState_DIT */ "dit",
92	/* kDisArmv8InstrPState_SVCRSM */ "svcrsm",
93	/* kDisArmv8InstrPState_SVCRZA */ "svcrza",
94	/* kDisArmv8InstrPState_SVCRSMZA */ "svcrsmza",
95	/* kDisArmv8InstrPState_TCO */ "tco"
96	};
97
98
99	/**
100	* List of known system registers.
101	*
102	* The list MUST be in ascending order of the system register ID!
103	*/
104	static const struct
105	{
106	/** IPRT system register ID. */
107	uint32_t idSysReg;
108	/** Name of the system register. */
109	const char *pszSysReg;
110	/** Character count of the system register name. */
111	size_t cchSysReg;
112	} g_aArmV8SysReg64[] =
113	{
114	#define DIS_ARMV8_SYSREG(a_idSysReg) { (ARMV8_AARCH64_SYSREG_ ## a_idSysReg), #a_idSysReg, sizeof(#a_idSysReg) - 1 }
115	DIS_ARMV8_SYSREG(OSDTRRX_EL1),
116	DIS_ARMV8_SYSREG(MDSCR_EL1),
117	//DIS_ARMV8_SYSREG(DBGBVRn_EL1(a_Id)),
118	//DIS_ARMV8_SYSREG(DBGBCRn_EL1(a_Id)),
119	//DIS_ARMV8_SYSREG(DBGWVRn_EL1(a_Id)),
120	//DIS_ARMV8_SYSREG(DBGWCRn_EL1(a_Id)),
121	DIS_ARMV8_SYSREG(MDCCINT_EL1),
122	DIS_ARMV8_SYSREG(OSDTRTX_EL1),
123	DIS_ARMV8_SYSREG(OSECCR_EL1),
124	DIS_ARMV8_SYSREG(MDRAR_EL1),
125	DIS_ARMV8_SYSREG(OSLAR_EL1),
126	DIS_ARMV8_SYSREG(OSLSR_EL1),
127	DIS_ARMV8_SYSREG(OSDLR_EL1),
128	DIS_ARMV8_SYSREG(MIDR_EL1),
129	DIS_ARMV8_SYSREG(MPIDR_EL1),
130	DIS_ARMV8_SYSREG(REVIDR_EL1),
131	DIS_ARMV8_SYSREG(ID_PFR0_EL1),
132	DIS_ARMV8_SYSREG(ID_PFR1_EL1),
133	DIS_ARMV8_SYSREG(ID_DFR0_EL1),
134	DIS_ARMV8_SYSREG(ID_AFR0_EL1),
135	DIS_ARMV8_SYSREG(ID_MMFR0_EL1),
136	DIS_ARMV8_SYSREG(ID_MMFR1_EL1),
137	DIS_ARMV8_SYSREG(ID_MMFR2_EL1),
138	DIS_ARMV8_SYSREG(ID_MMFR3_EL1),
139	DIS_ARMV8_SYSREG(ID_ISAR0_EL1),
140	DIS_ARMV8_SYSREG(ID_ISAR1_EL1),
141	DIS_ARMV8_SYSREG(ID_ISAR2_EL1),
142	DIS_ARMV8_SYSREG(ID_ISAR3_EL1),
143	DIS_ARMV8_SYSREG(ID_ISAR4_EL1),
144	DIS_ARMV8_SYSREG(ID_ISAR5_EL1),
145	DIS_ARMV8_SYSREG(ID_MMFR4_EL1),
146	DIS_ARMV8_SYSREG(ID_ISAR6_EL1),
147	DIS_ARMV8_SYSREG(MVFR0_EL1),
148	DIS_ARMV8_SYSREG(MVFR1_EL1),
149	DIS_ARMV8_SYSREG(MVFR2_EL1),
150	DIS_ARMV8_SYSREG(ID_PFR2_EL1),
151	DIS_ARMV8_SYSREG(ID_DFR1_EL1),
152	DIS_ARMV8_SYSREG(ID_MMFR5_EL1),
153	DIS_ARMV8_SYSREG(ID_AA64PFR0_EL1),
154	DIS_ARMV8_SYSREG(ID_AA64PFR1_EL1),
155	DIS_ARMV8_SYSREG(ID_AA64ZFR0_EL1),
156	DIS_ARMV8_SYSREG(ID_AA64SMFR0_EL1),
157	DIS_ARMV8_SYSREG(ID_AA64DFR0_EL1),
158	DIS_ARMV8_SYSREG(ID_AA64DFR1_EL1),
159	DIS_ARMV8_SYSREG(ID_AA64AFR0_EL1),
160	DIS_ARMV8_SYSREG(ID_AA64AFR1_EL1),
161	DIS_ARMV8_SYSREG(ID_AA64ISAR0_EL1),
162	DIS_ARMV8_SYSREG(ID_AA64ISAR1_EL1),
163	DIS_ARMV8_SYSREG(ID_AA64ISAR2_EL1),
164	DIS_ARMV8_SYSREG(ID_AA64MMFR0_EL1),
165	DIS_ARMV8_SYSREG(ID_AA64MMFR1_EL1),
166	DIS_ARMV8_SYSREG(ID_AA64MMFR2_EL1),
167	DIS_ARMV8_SYSREG(SCTRL_EL1),
168	DIS_ARMV8_SYSREG(ACTRL_EL1),
169	DIS_ARMV8_SYSREG(CPACR_EL1),
170	DIS_ARMV8_SYSREG(RGSR_EL1),
171	DIS_ARMV8_SYSREG(GCR_EL1),
172	DIS_ARMV8_SYSREG(ZCR_EL1),
173	DIS_ARMV8_SYSREG(TRFCR_EL1),
174	DIS_ARMV8_SYSREG(SMPRI_EL1),
175	DIS_ARMV8_SYSREG(SMCR_EL1),
176	DIS_ARMV8_SYSREG(TTBR0_EL1),
177	DIS_ARMV8_SYSREG(TTBR1_EL1),
178	DIS_ARMV8_SYSREG(TCR_EL1),
179	DIS_ARMV8_SYSREG(APIAKeyLo_EL1),
180	DIS_ARMV8_SYSREG(APIAKeyHi_EL1),
181	DIS_ARMV8_SYSREG(APIBKeyLo_EL1),
182	DIS_ARMV8_SYSREG(APIBKeyHi_EL1),
183	DIS_ARMV8_SYSREG(APDAKeyLo_EL1),
184	DIS_ARMV8_SYSREG(APDAKeyHi_EL1),
185	DIS_ARMV8_SYSREG(APDBKeyLo_EL1),
186	DIS_ARMV8_SYSREG(APDBKeyHi_EL1),
187	DIS_ARMV8_SYSREG(APGAKeyLo_EL1),
188	DIS_ARMV8_SYSREG(APGAKeyHi_EL1),
189	DIS_ARMV8_SYSREG(SPSR_EL1),
190	DIS_ARMV8_SYSREG(ELR_EL1),
191	DIS_ARMV8_SYSREG(SP_EL0),
192	DIS_ARMV8_SYSREG(SPSEL),
193	DIS_ARMV8_SYSREG(CURRENTEL),
194	DIS_ARMV8_SYSREG(PAN),
195	DIS_ARMV8_SYSREG(UAO),
196	DIS_ARMV8_SYSREG(ALLINT),
197	DIS_ARMV8_SYSREG(ICC_PMR_EL1),
198	DIS_ARMV8_SYSREG(AFSR0_EL1),
199	DIS_ARMV8_SYSREG(AFSR1_EL1),
200	DIS_ARMV8_SYSREG(ESR_EL1),
201	DIS_ARMV8_SYSREG(ERRIDR_EL1),
202	DIS_ARMV8_SYSREG(ERRSELR_EL1),
203	DIS_ARMV8_SYSREG(FAR_EL1),
204	DIS_ARMV8_SYSREG(PAR_EL1),
205	DIS_ARMV8_SYSREG(MAIR_EL1),
206	DIS_ARMV8_SYSREG(AMAIR_EL1),
207	DIS_ARMV8_SYSREG(VBAR_EL1),
208	DIS_ARMV8_SYSREG(ICC_IAR0_EL1),
209	DIS_ARMV8_SYSREG(ICC_EOIR0_EL1),
210	DIS_ARMV8_SYSREG(ICC_HPPIR0_EL1),
211	DIS_ARMV8_SYSREG(ICC_BPR0_EL1),
212	DIS_ARMV8_SYSREG(ICC_AP0R0_EL1),
213	DIS_ARMV8_SYSREG(ICC_AP0R1_EL1),
214	DIS_ARMV8_SYSREG(ICC_AP0R2_EL1),
215	DIS_ARMV8_SYSREG(ICC_AP0R3_EL1),
216	DIS_ARMV8_SYSREG(ICC_AP1R0_EL1),
217	DIS_ARMV8_SYSREG(ICC_AP1R1_EL1),
218	DIS_ARMV8_SYSREG(ICC_AP1R2_EL1),
219	DIS_ARMV8_SYSREG(ICC_AP1R3_EL1),
220	DIS_ARMV8_SYSREG(ICC_NMIAR1_EL1),
221	DIS_ARMV8_SYSREG(ICC_DIR_EL1),
222	DIS_ARMV8_SYSREG(ICC_RPR_EL1),
223	DIS_ARMV8_SYSREG(ICC_SGI1R_EL1),
224	DIS_ARMV8_SYSREG(ICC_ASGI1R_EL1),
225	DIS_ARMV8_SYSREG(ICC_SGI0R_EL1),
226	DIS_ARMV8_SYSREG(ICC_IAR1_EL1),
227	DIS_ARMV8_SYSREG(ICC_EOIR1_EL1),
228	DIS_ARMV8_SYSREG(ICC_HPPIR1_EL1),
229	DIS_ARMV8_SYSREG(ICC_BPR1_EL1),
230	DIS_ARMV8_SYSREG(ICC_CTLR_EL1),
231	DIS_ARMV8_SYSREG(ICC_SRE_EL1),
232	DIS_ARMV8_SYSREG(ICC_IGRPEN0_EL1),
233	DIS_ARMV8_SYSREG(ICC_IGRPEN1_EL1),
234	DIS_ARMV8_SYSREG(CONTEXTIDR_EL1),
235	DIS_ARMV8_SYSREG(TPIDR_EL1),
236	DIS_ARMV8_SYSREG(CNTKCTL_EL1),
237	DIS_ARMV8_SYSREG(CSSELR_EL1),
238	DIS_ARMV8_SYSREG(NZCV),
239	DIS_ARMV8_SYSREG(DAIF),
240	DIS_ARMV8_SYSREG(SVCR),
241	DIS_ARMV8_SYSREG(DIT),
242	DIS_ARMV8_SYSREG(SSBS),
243	DIS_ARMV8_SYSREG(TCO),
244	DIS_ARMV8_SYSREG(FPCR),
245	DIS_ARMV8_SYSREG(FPSR),
246	DIS_ARMV8_SYSREG(ICC_SRE_EL2),
247	DIS_ARMV8_SYSREG(TPIDR_EL0),
248	DIS_ARMV8_SYSREG(TPIDRRO_EL0),
249	DIS_ARMV8_SYSREG(CNTFRQ_EL0),
250	DIS_ARMV8_SYSREG(CNTVCT_EL0),
251	DIS_ARMV8_SYSREG(CNTP_TVAL_EL0),
252	DIS_ARMV8_SYSREG(CNTP_CTL_EL0),
253	DIS_ARMV8_SYSREG(CNTP_CVAL_EL0),
254	DIS_ARMV8_SYSREG(CNTV_CTL_EL0),
255	DIS_ARMV8_SYSREG(VPIDR_EL2),
256	DIS_ARMV8_SYSREG(VMPIDR_EL2),
257	DIS_ARMV8_SYSREG(SCTLR_EL2),
258	DIS_ARMV8_SYSREG(ACTLR_EL2),
259	DIS_ARMV8_SYSREG(HCR_EL2),
260	DIS_ARMV8_SYSREG(MDCR_EL2),
261	DIS_ARMV8_SYSREG(CPTR_EL2),
262	DIS_ARMV8_SYSREG(HSTR_EL2),
263	DIS_ARMV8_SYSREG(HFGRTR_EL2),
264	DIS_ARMV8_SYSREG(HFGWTR_EL2),
265	DIS_ARMV8_SYSREG(HFGITR_EL2),
266	DIS_ARMV8_SYSREG(HACR_EL2),
267	DIS_ARMV8_SYSREG(ZCR_EL2),
268	DIS_ARMV8_SYSREG(TRFCR_EL2),
269	DIS_ARMV8_SYSREG(HCRX_EL2),
270	DIS_ARMV8_SYSREG(SDER32_EL2),
271	DIS_ARMV8_SYSREG(TTBR0_EL2),
272	DIS_ARMV8_SYSREG(TTBR1_EL2),
273	DIS_ARMV8_SYSREG(TCR_EL2),
274	DIS_ARMV8_SYSREG(VTTBR_EL2),
275	DIS_ARMV8_SYSREG(VTCR_EL2),
276	DIS_ARMV8_SYSREG(VNCR_EL2),
277	DIS_ARMV8_SYSREG(VSTTBR_EL2),
278	DIS_ARMV8_SYSREG(VSTCR_EL2),
279	DIS_ARMV8_SYSREG(DACR32_EL2),
280	DIS_ARMV8_SYSREG(HDFGRTR_EL2),
281	DIS_ARMV8_SYSREG(HDFGWTR_EL2),
282	DIS_ARMV8_SYSREG(HAFGRTR_EL2),
283	DIS_ARMV8_SYSREG(SPSR_EL2),
284	DIS_ARMV8_SYSREG(ELR_EL2),
285	DIS_ARMV8_SYSREG(SP_EL1),
286	DIS_ARMV8_SYSREG(IFSR32_EL2),
287	DIS_ARMV8_SYSREG(AFSR0_EL2),
288	DIS_ARMV8_SYSREG(AFSR1_EL2),
289	DIS_ARMV8_SYSREG(ESR_EL2),
290	DIS_ARMV8_SYSREG(VSESR_EL2),
291	DIS_ARMV8_SYSREG(FPEXC32_EL2),
292	DIS_ARMV8_SYSREG(TFSR_EL2),
293	DIS_ARMV8_SYSREG(FAR_EL2),
294	DIS_ARMV8_SYSREG(HPFAR_EL2),
295	DIS_ARMV8_SYSREG(PMSCR_EL2),
296	DIS_ARMV8_SYSREG(MAIR_EL2),
297	DIS_ARMV8_SYSREG(AMAIR_EL2),
298	DIS_ARMV8_SYSREG(MPAMHCR_EL2),
299	DIS_ARMV8_SYSREG(MPAMVPMV_EL2),
300	DIS_ARMV8_SYSREG(MPAM2_EL2),
301	DIS_ARMV8_SYSREG(MPAMVPM0_EL2),
302	DIS_ARMV8_SYSREG(MPAMVPM1_EL2),
303	DIS_ARMV8_SYSREG(MPAMVPM2_EL2),
304	DIS_ARMV8_SYSREG(MPAMVPM3_EL2),
305	DIS_ARMV8_SYSREG(MPAMVPM4_EL2),
306	DIS_ARMV8_SYSREG(MPAMVPM5_EL2),
307	DIS_ARMV8_SYSREG(MPAMVPM6_EL2),
308	DIS_ARMV8_SYSREG(MPAMVPM7_EL2),
309	DIS_ARMV8_SYSREG(VBAR_EL2),
310	DIS_ARMV8_SYSREG(RVBAR_EL2),
311	DIS_ARMV8_SYSREG(RMR_EL2),
312	DIS_ARMV8_SYSREG(VDISR_EL2),
313	DIS_ARMV8_SYSREG(CONTEXTIDR_EL2),
314	DIS_ARMV8_SYSREG(TPIDR_EL2),
315	DIS_ARMV8_SYSREG(SCXTNUM_EL2),
316	DIS_ARMV8_SYSREG(CNTVOFF_EL2),
317	DIS_ARMV8_SYSREG(CNTPOFF_EL2),
318	DIS_ARMV8_SYSREG(CNTHCTL_EL2),
319	DIS_ARMV8_SYSREG(CNTHP_TVAL_EL2),
320	DIS_ARMV8_SYSREG(CNTHP_CTL_EL2),
321	DIS_ARMV8_SYSREG(CNTHP_CVAL_EL2),
322	DIS_ARMV8_SYSREG(CNTHV_TVAL_EL2),
323	DIS_ARMV8_SYSREG(CNTHV_CTL_EL2),
324	DIS_ARMV8_SYSREG(CNTHV_CVAL_EL2),
325	DIS_ARMV8_SYSREG(CNTHVS_TVAL_EL2),
326	DIS_ARMV8_SYSREG(CNTHVS_CTL_EL2),
327	DIS_ARMV8_SYSREG(CNTHVS_CVAL_EL2),
328	DIS_ARMV8_SYSREG(CNTHPS_TVAL_EL2),
329	DIS_ARMV8_SYSREG(CNTHPS_CTL_EL2),
330	DIS_ARMV8_SYSREG(CNTHPS_CVAL_EL2),
331	DIS_ARMV8_SYSREG(SP_EL2)
332	#undef DIS_ARMV8_SYSREG
333	};
334
335
336	/**
337	* Gets the base register name for the given parameter.
338	*
339	* @returns Pointer to the register name.
340	* @param pDis The disassembler state.
341	* @param pParam The parameter.
342	* @param pcchReg Where to store the length of the name.
343	*/
344	DECLINLINE(const char ) disasmFormatArmV8Reg(PCDISSTATE pDis, PCDISOPPARAMARMV8REG pReg, size_t pcchReg)
345	{
346	RT_NOREF_PV(pDis);
347
348	switch (pReg->enmRegType)
349	{
350	case kDisOpParamArmV8RegType_Gpr_32Bit:
351	{
352	Assert(pReg->idReg < RT_ELEMENTS(g_aszArmV8RegGen32));
353	const char *psz = g_aszArmV8RegGen32[pReg->idReg];
354	*pcchReg = 2 + !!psz[2];
355	return psz;
356	}
357	case kDisOpParamArmV8RegType_Gpr_64Bit:
358	{
359	Assert(pReg->idReg < RT_ELEMENTS(g_aszArmV8RegGen64));
360	const char *psz = g_aszArmV8RegGen64[pReg->idReg];
361	*pcchReg = 2 + !!psz[2];
362	return psz;
363	}
364	case kDisOpParamArmV8RegType_FpReg_Single:
365	{
366	Assert(pDis->armv8.enmFpType != kDisArmv8InstrFpType_Invalid);
367	Assert(pReg->idReg < RT_ELEMENTS(g_aszArmV8RegFpSingle));
368	const char *psz = g_aszArmV8RegFpSingle[pReg->idReg];
369	*pcchReg = 2 + !!psz[2];
370	return psz;
371	}
372	case kDisOpParamArmV8RegType_FpReg_Double:
373	{
374	Assert(pDis->armv8.enmFpType != kDisArmv8InstrFpType_Invalid);
375	Assert(pReg->idReg < RT_ELEMENTS(g_aszArmV8RegFpDouble));
376	const char *psz = g_aszArmV8RegFpDouble[pReg->idReg];
377	*pcchReg = 2 + !!psz[2];
378	return psz;
379	}
380	case kDisOpParamArmV8RegType_FpReg_Half:
381	{
382	Assert(pDis->armv8.enmFpType != kDisArmv8InstrFpType_Invalid);
383	Assert(pReg->idReg < RT_ELEMENTS(g_aszArmV8RegFpHalf));
384	const char *psz = g_aszArmV8RegFpHalf[pReg->idReg];
385	*pcchReg = 2 + !!psz[2];
386	return psz;
387	}
388	case kDisOpParamArmV8RegType_Simd_Scalar_64Bit:
389	{
390	/* Using the floating point double register names here. */
391	Assert(pReg->idReg < RT_ELEMENTS(g_aszArmV8RegFpDouble));
392	const char *psz = g_aszArmV8RegFpDouble[pReg->idReg];
393	*pcchReg = 2 + !!psz[2];
394	return psz;
395	}
396	case kDisOpParamArmV8RegType_Simd_Scalar_128Bit:
397	{
398	Assert(pReg->idReg < RT_ELEMENTS(g_aszArmV8RegSimdScalar128Bit));
399	const char *psz = g_aszArmV8RegSimdScalar128Bit[pReg->idReg];
400	*pcchReg = 2 + !!psz[2];
401	return psz;
402	}
403	case kDisOpParamArmV8RegType_Sp:
404	{
405	*pcchReg = 2;
406	return "sp";
407	}
408	default:
409	AssertFailed();
410	*pcchReg = 0;
411	return NULL;
412	}
413	}
414
415
416	/**
417	* Gets the base register name for the given parameter.
418	*
419	* @returns Pointer to the register name.
420	* @param pDis The disassembler state.
421	* @param pParam The parameter.
422	* @param pachTmp Pointer to temporary string storage when building
423	* the register name.
424	* @param pcchReg Where to store the length of the name.
425	*/
426	static const char disasmFormatArmV8SysReg(PCDISSTATE pDis, PCDISOPPARAM pParam, char pachTmp, size_t *pcchReg)
427	{
428	RT_NOREF_PV(pDis);
429
430	/* Try to find the system register ID in the table. */
431	/** @todo Binary search (lazy). */
432	for (uint32_t i = 0; i < RT_ELEMENTS(g_aArmV8SysReg64); i++)
433	{
434	if (g_aArmV8SysReg64[i].idSysReg == pParam->armv8.Op.idSysReg)
435	{
436	*pcchReg = g_aArmV8SysReg64[i].cchSysReg;
437	return g_aArmV8SysReg64[i].pszSysReg;
438	}
439	}
440
441	/* Generate S<op0>_<op1>_<Cn>_<Cm>_<op2> identifier. */
442	uint32_t const idSysReg = pParam->armv8.Op.idSysReg;
443	uint8_t idx = 0;
444	pachTmp[idx++] = 'S';
445	pachTmp[idx++] = '2' + ((idSysReg >> 14) & 0x1);
446	pachTmp[idx++] = '_';
447	pachTmp[idx++] = '0' + ((idSysReg >> 11) & 0x7);
448	pachTmp[idx++] = '_';
449
450	uint8_t bTmp = (idSysReg >> 7) & 0xf;
451	if (bTmp >= 10)
452	{
453	pachTmp[idx++] = '1' + (bTmp - 10);
454	bTmp -= 10;
455	}
456	pachTmp[idx++] = '0' + bTmp;
457	pachTmp[idx++] = '_';
458
459	bTmp = (idSysReg >> 3) & 0xf;
460	if (bTmp >= 10)
461	{
462	pachTmp[idx++] = '1' + (bTmp - 10);
463	bTmp -= 10;
464	}
465	pachTmp[idx++] = '0' + bTmp;
466
467	pachTmp[idx++] = '_';
468	pachTmp[idx++] = '0' + (idSysReg & 0x7);
469	pachTmp[idx] = '\0';
470	*pcchReg = idx;
471	return pachTmp;
472	}
473
474
475	/**
476	* Formats the current instruction in ARMv8 style.
477	*
478	*
479	* @returns The number of output characters. If this is >= cchBuf, then the content
480	* of pszBuf will be truncated.
481	* @param pDis Pointer to the disassembler state.
482	* @param pszBuf The output buffer.
483	* @param cchBuf The size of the output buffer.
484	* @param fFlags Format flags, see DIS_FORMAT_FLAGS_*.
485	* @param pfnGetSymbol Get symbol name for a jmp or call target address. Optional.
486	* @param pvUser User argument for pfnGetSymbol.
487	*/
488	DISDECL(size_t) DISFormatArmV8Ex(PCDISSTATE pDis, char *pszBuf, size_t cchBuf, uint32_t fFlags,
489	PFNDISGETSYMBOL pfnGetSymbol, void *pvUser)
490	{
491	/*
492	* Input validation and massaging.
493	*/
494	AssertPtr(pDis);
495	AssertPtrNull(pszBuf);
496	Assert(pszBuf \|\| !cchBuf);
497	AssertPtrNull(pfnGetSymbol);
498	AssertMsg(DIS_FMT_FLAGS_IS_VALID(fFlags), ("%#x\n", fFlags));
499	if (fFlags & DIS_FMT_FLAGS_ADDR_COMMENT)
500	fFlags = (fFlags & ~DIS_FMT_FLAGS_ADDR_LEFT) \| DIS_FMT_FLAGS_ADDR_RIGHT;
501	if (fFlags & DIS_FMT_FLAGS_BYTES_COMMENT)
502	fFlags = (fFlags & ~DIS_FMT_FLAGS_BYTES_LEFT) \| DIS_FMT_FLAGS_BYTES_RIGHT;
503
504	PCDISOPCODE const pOp = pDis->pCurInstr;
505
506	/*
507	* Output macros
508	*/
509	char *pszDst = pszBuf;
510	size_t cchDst = cchBuf;
511	size_t cchOutput = 0;
512	#define PUT_C(ch) \
513	do { \
514	cchOutput++; \
515	if (cchDst > 1) \
516	{ \
517	cchDst--; \
518	*pszDst++ = (ch); \
519	} \
520	} while (0)
521	#define PUT_STR(pszSrc, cchSrc) \
522	do { \
523	cchOutput += (cchSrc); \
524	if (cchDst > (cchSrc)) \
525	{ \
526	memcpy(pszDst, (pszSrc), (cchSrc)); \
527	pszDst += (cchSrc); \
528	cchDst -= (cchSrc); \
529	} \
530	else if (cchDst > 1) \
531	{ \
532	memcpy(pszDst, (pszSrc), cchDst - 1); \
533	pszDst += cchDst - 1; \
534	cchDst = 1; \
535	} \
536	} while (0)
537	#define PUT_SZ(sz) \
538	PUT_STR((sz), sizeof(sz) - 1)
539	#define PUT_SZ_STRICT(szStrict, szRelaxed) \
540	do { if (fFlags & DIS_FMT_FLAGS_STRICT) PUT_SZ(szStrict); else PUT_SZ(szRelaxed); } while (0)
541	#define PUT_PSZ(psz) \
542	do { const size_t cchTmp = strlen(psz); PUT_STR((psz), cchTmp); } while (0)
543	#define PUT_NUM(cch, fmt, num) \
544	do { \
545	cchOutput += (cch); \
546	if (cchDst > 1) \
547	{ \
548	const size_t cchTmp = RTStrPrintf(pszDst, cchDst, fmt, (num)); \
549	pszDst += cchTmp; \
550	cchDst -= cchTmp; \
551	Assert(cchTmp == (cch) \|\| cchDst == 1); \
552	} \
553	} while (0)
554	/** @todo add two flags for choosing between %X / %x and h / 0x. */
555	#define PUT_NUM_8(num) PUT_NUM(4, "0x%02x", (uint8_t)(num))
556	#define PUT_NUM_16(num) PUT_NUM(6, "0x%04x", (uint16_t)(num))
557	#define PUT_NUM_32(num) PUT_NUM(10, "0x%08x", (uint32_t)(num))
558	#define PUT_NUM_64(num) PUT_NUM(18, "0x%016RX64", (uint64_t)(num))
559
560	#define PUT_NUM_SIGN(cch, fmt, num, stype, utype) \
561	do { \
562	if ((stype)(num) >= 0) \
563	{ \
564	PUT_C('+'); \
565	PUT_NUM(cch, fmt, (utype)(num)); \
566	} \
567	else \
568	{ \
569	PUT_C('-'); \
570	PUT_NUM(cch, fmt, (utype)-(stype)(num)); \
571	} \
572	} while (0)
573	#define PUT_NUM_S8(num) PUT_NUM_SIGN(4, "0x%02x", num, int8_t, uint8_t)
574	#define PUT_NUM_S16(num) PUT_NUM_SIGN(6, "0x%04x", num, int16_t, uint16_t)
575	#define PUT_NUM_S32(num) PUT_NUM_SIGN(10, "0x%08x", num, int32_t, uint32_t)
576	#define PUT_NUM_S64(num) PUT_NUM_SIGN(18, "0x%016RX64", num, int64_t, uint64_t)
577
578	#define PUT_SYMBOL_TWO(a_rcSym, a_szStart, a_chEnd) \
579	do { \
580	if (RT_SUCCESS(a_rcSym)) \
581	{ \
582	PUT_SZ(a_szStart); \
583	PUT_PSZ(szSymbol); \
584	if (off != 0) \
585	{ \
586	if ((int8_t)off == off) \
587	PUT_NUM_S8(off); \
588	else if ((int16_t)off == off) \
589	PUT_NUM_S16(off); \
590	else if ((int32_t)off == off) \
591	PUT_NUM_S32(off); \
592	else \
593	PUT_NUM_S64(off); \
594	} \
595	PUT_C(a_chEnd); \
596	} \
597	} while (0)
598
599	#define PUT_SYMBOL(a_uSeg, a_uAddr, a_szStart, a_chEnd) \
600	do { \
601	if (pfnGetSymbol) \
602	{ \
603	int rcSym = pfnGetSymbol(pDis, a_uSeg, a_uAddr, szSymbol, sizeof(szSymbol), &off, pvUser); \
604	PUT_SYMBOL_TWO(rcSym, a_szStart, a_chEnd); \
605	} \
606	} while (0)
607
608
609	/*
610	* The address?
611	*/
612	if (fFlags & DIS_FMT_FLAGS_ADDR_LEFT)
613	{
614	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
615	if (pDis->uInstrAddr >= _4G)
616	PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
617	#endif
618	PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
619	PUT_C(' ');
620	}
621
622	/*
623	* The opcode bytes?
624	*/
625	if (fFlags & DIS_FMT_FLAGS_BYTES_LEFT)
626	{
627	size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
628	cchOutput += cchTmp;
629	if (cchDst > 1)
630	{
631	if (cchTmp <= cchDst)
632	{
633	cchDst -= cchTmp;
634	pszDst += cchTmp;
635	}
636	else
637	{
638	pszDst += cchDst - 1;
639	cchDst = 1;
640	}
641	}
642
643	/* Some padding to align the instruction. */
644	size_t cchPadding = (7 * (2 + !!(fFlags & DIS_FMT_FLAGS_BYTES_SPACED)))
645	+ !!(fFlags & DIS_FMT_FLAGS_BYTES_BRACKETS) * 2
646	+ 2;
647	cchPadding = cchTmp + 1 >= cchPadding ? 1 : cchPadding - cchTmp;
648	PUT_STR(g_szSpaces, cchPadding);
649	}
650
651
652	/*
653	* Filter out invalid opcodes first as they need special
654	* treatment. UDF is an exception and should be handled normally.
655	*/
656	size_t const offInstruction = cchOutput;
657	if (pOp->uOpcode == OP_INVALID)
658	PUT_SZ("Illegal opcode");
659	else
660	{
661	/* Start with the instruction. */
662	PUT_PSZ(pOp->pszOpcode);
663
664	/* Add any conditionals. */
665	if (pDis->armv8.enmCond != kDisArmv8InstrCond_Al)
666	{
667	PUT_C('.');
668	Assert((uint16_t)pDis->armv8.enmCond < RT_ELEMENTS(g_aszArmV8Cond));
669	PUT_STR(g_aszArmV8Cond[pDis->armv8.enmCond], sizeof(g_aszArmV8Cond[0]) - 1);
670	}
671
672	/*
673	* Format the parameters.
674	*/
675	RTINTPTR off;
676	char szSymbol[128];
677	for (uint32_t i = 0; i < RT_ELEMENTS(pDis->aParams); i++)
678	{
679	PCDISOPPARAM pParam = &pDis->aParams[i];
680
681	/* First None parameter marks end of parameters. */
682	if (pParam->armv8.enmType == kDisArmv8OpParmNone)
683	break;
684
685	if (i > 0)
686	PUT_C(',');
687	PUT_C(' '); /** @todo Make the indenting configurable. */
688
689	switch (pParam->armv8.enmType)
690	{
691	case kDisArmv8OpParmImm:
692	{
693	PUT_C('#');
694	switch (pParam->fUse & ( DISUSE_IMMEDIATE8 \| DISUSE_IMMEDIATE16 \| DISUSE_IMMEDIATE32 \| DISUSE_IMMEDIATE64
695	\| DISUSE_IMMEDIATE16_SX8 \| DISUSE_IMMEDIATE32_SX8 \| DISUSE_IMMEDIATE64_SX8))
696	{
697	case DISUSE_IMMEDIATE8:
698	PUT_NUM_8(pParam->uValue);
699	break;
700	case DISUSE_IMMEDIATE16:
701	PUT_NUM_16(pParam->uValue);
702	break;
703	case DISUSE_IMMEDIATE16_SX8:
704	PUT_NUM_16(pParam->uValue);
705	break;
706	case DISUSE_IMMEDIATE32:
707	PUT_NUM_32(pParam->uValue);
708	/** @todo Symbols */
709	break;
710	case DISUSE_IMMEDIATE32_SX8:
711	PUT_NUM_32(pParam->uValue);
712	break;
713	case DISUSE_IMMEDIATE64_SX8:
714	PUT_NUM_64(pParam->uValue);
715	break;
716	case DISUSE_IMMEDIATE64:
717	PUT_NUM_64(pParam->uValue);
718	/** @todo Symbols */
719	break;
720	default:
721	AssertFailed();
722	break;
723	}
724	break;
725	}
726	case kDisArmv8OpParmImmRel:
727	/case kDisParmParseImmAdr:/
728	{
729	int32_t offDisplacement;
730
731	PUT_C('#');
732	if (pParam->fUse & DISUSE_IMMEDIATE8_REL)
733	{
734	offDisplacement = (int8_t)pParam->uValue;
735	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
736	PUT_NUM_S8(offDisplacement * sizeof(uint32_t));
737	}
738	else if (pParam->fUse & DISUSE_IMMEDIATE16_REL)
739	{
740	offDisplacement = (int16_t)pParam->uValue;
741	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
742	PUT_NUM_S16(offDisplacement * sizeof(uint32_t));
743	}
744	else
745	{
746	offDisplacement = (int32_t)pParam->uValue;
747	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
748	PUT_NUM_S32(offDisplacement * sizeof(uint32_t));
749	}
750	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
751	PUT_SZ(" ; (");
752
753	RTUINTPTR uTrgAddr = pDis->uInstrAddr + (offDisplacement * sizeof(uint32_t));
754	if ( pDis->uCpuMode == DISCPUMODE_ARMV8_A32
755	\|\| pDis->uCpuMode == DISCPUMODE_ARMV8_T32)
756	PUT_NUM_32(uTrgAddr);
757	else if (pDis->uCpuMode == DISCPUMODE_ARMV8_A64)
758	PUT_NUM_64(uTrgAddr);
759	else
760	AssertReleaseFailed();
761
762	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
763	{
764	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " = ", ' ');
765	PUT_C(')');
766	}
767	else
768	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " (", ')');
769	break;
770	}
771	case kDisArmv8OpParmReg:
772	{
773	Assert(!(pParam->fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32)));
774
775	size_t cchReg;
776	const char *pszReg = disasmFormatArmV8Reg(pDis, &pParam->armv8.Op.Reg, &cchReg);
777	PUT_STR(pszReg, cchReg);
778	break;
779	}
780	case kDisArmv8OpParmSysReg:
781	{
782	Assert(pParam->fUse == DISUSE_REG_SYSTEM);
783
784	size_t cchReg;
785	char achTmp[32];
786	const char *pszReg = disasmFormatArmV8SysReg(pDis, pParam, &achTmp[0], &cchReg);
787	PUT_STR(pszReg, cchReg);
788	break;
789	}
790	case kDisArmv8OpParmAddrInGpr:
791	{
792	Assert( (pParam->fUse & (DISUSE_PRE_INDEXED \| DISUSE_POST_INDEXED))
793	!= (DISUSE_PRE_INDEXED \| DISUSE_POST_INDEXED));
794	Assert( ( RT_BOOL(pParam->fUse & (DISUSE_PRE_INDEXED \| DISUSE_POST_INDEXED))
795	!= RT_BOOL(pParam->fUse & DISUSE_INDEX))
796	\|\| !(pParam->fUse & (DISUSE_PRE_INDEXED \| DISUSE_POST_INDEXED \| DISUSE_INDEX)));
797
798	PUT_C('[');
799
800	size_t cchReg;
801	const char *pszReg = disasmFormatArmV8Reg(pDis, &pParam->armv8.Op.Reg, &cchReg);
802	PUT_STR(pszReg, cchReg);
803
804	if (pParam->fUse & DISUSE_POST_INDEXED)
805	{
806	Assert(pParam->armv8.enmExtend == kDisArmv8OpParmExtendNone);
807	PUT_SZ("], #");
808	PUT_NUM_S16(pParam->armv8.u.offBase);
809	}
810	else
811	{
812	if (pParam->fUse & DISUSE_INDEX)
813	{
814	PUT_SZ(", ");
815
816	pszReg = disasmFormatArmV8Reg(pDis, &pParam->armv8.GprIndex, &cchReg);
817	PUT_STR(pszReg, cchReg);
818	}
819	else if ( pParam->armv8.u.offBase
820	\|\| (pParam->fUse & (DISUSE_POST_INDEXED \| DISUSE_PRE_INDEXED)))
821	{
822	PUT_SZ(", #");
823	PUT_NUM_S16(pParam->armv8.u.offBase);
824	}
825
826	if (pParam->armv8.enmExtend != kDisArmv8OpParmExtendNone)
827	{
828	PUT_SZ(", ");
829	switch (pParam->armv8.enmExtend)
830	{
831	case kDisArmv8OpParmExtendUxtX: /* UXTX is same as LSL which is preferred by most disassemblers/assemblers. */
832	case kDisArmv8OpParmExtendLsl:
833	PUT_SZ("LSL #");
834	break;
835	case kDisArmv8OpParmExtendUxtB: PUT_SZ("UXTB #"); break;
836	case kDisArmv8OpParmExtendUxtH: PUT_SZ("UXTH #"); break;
837	case kDisArmv8OpParmExtendUxtW: PUT_SZ("UXTW #"); break;
838	case kDisArmv8OpParmExtendSxtB: PUT_SZ("SXTB #"); break;
839	case kDisArmv8OpParmExtendSxtH: PUT_SZ("SXTH #"); break;
840	case kDisArmv8OpParmExtendSxtW: PUT_SZ("SXTW #"); break;
841	case kDisArmv8OpParmExtendSxtX: PUT_SZ("SXTX #"); break;
842	default:
843	AssertFailed();
844	}
845	PUT_NUM_8(pParam->armv8.u.cExtend);
846	}
847
848	PUT_C(']');
849
850	if (pParam->fUse & DISUSE_PRE_INDEXED)
851	PUT_C('!');
852	}
853
854	break;
855	}
856	case kDisArmv8OpParmCond:
857	{
858	Assert((uint16_t)pParam->armv8.Op.enmCond < RT_ELEMENTS(g_aszArmV8Cond));
859	PUT_STR(g_aszArmV8Cond[pParam->armv8.Op.enmCond], sizeof(g_aszArmV8Cond[0]) - 1);
860	break;
861	}
862	case kDisArmv8OpParmPState:
863	{
864	Assert((uint16_t)pParam->armv8.Op.enmPState < RT_ELEMENTS(g_apszArmV8PState));
865	PUT_PSZ(g_apszArmV8PState[pParam->armv8.Op.enmPState]);
866	break;
867	}
868	default:
869	AssertFailed();
870	}
871
872	if ( pParam->armv8.enmType != kDisArmv8OpParmAddrInGpr
873	&& pParam->armv8.enmExtend != kDisArmv8OpParmExtendNone)
874	{
875	Assert( pParam->armv8.enmType == kDisArmv8OpParmImm
876	\|\| pParam->armv8.enmType == kDisArmv8OpParmReg);
877	PUT_SZ(", ");
878	switch (pParam->armv8.enmExtend)
879	{
880	case kDisArmv8OpParmExtendLsl:
881	PUT_SZ("LSL #");
882	break;
883	case kDisArmv8OpParmExtendLsr:
884	PUT_SZ("LSR #");
885	break;
886	case kDisArmv8OpParmExtendAsr:
887	PUT_SZ("ASR #");
888	break;
889	case kDisArmv8OpParmExtendRor:
890	PUT_SZ("ROR #");
891	break;
892	default:
893	AssertFailed();
894	}
895	PUT_NUM_8(pParam->armv8.u.cExtend);
896	}
897	}
898	}
899
900	/*
901	* Any additional output to the right of the instruction?
902	*/
903	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
904	{
905	/* some up front padding. */
906	size_t cchPadding = cchOutput - offInstruction;
907	cchPadding = cchPadding + 1 >= 42 ? 1 : 42 - cchPadding;
908	PUT_STR(g_szSpaces, cchPadding);
909
910	/* comment? */
911	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
912	PUT_SZ(";");
913
914	/*
915	* The address?
916	*/
917	if (fFlags & DIS_FMT_FLAGS_ADDR_RIGHT)
918	{
919	PUT_C(' ');
920	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
921	if (pDis->uInstrAddr >= _4G)
922	PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
923	#endif
924	PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
925	}
926
927	/*
928	* Opcode bytes?
929	*/
930	if (fFlags & DIS_FMT_FLAGS_BYTES_RIGHT)
931	{
932	PUT_C(' ');
933	size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
934	cchOutput += cchTmp;
935	if (cchTmp >= cchDst)
936	cchTmp = cchDst - (cchDst != 0);
937	cchDst -= cchTmp;
938	pszDst += cchTmp;
939	}
940	}
941
942	/*
943	* Terminate it - on overflow we'll have reserved one byte for this.
944	*/
945	if (cchDst > 0)
946	*pszDst = '\0';
947	else
948	Assert(!cchBuf);
949
950	/* clean up macros */
951	#undef PUT_PSZ
952	#undef PUT_SZ
953	#undef PUT_STR
954	#undef PUT_C
955	return cchOutput;
956	}
957
958
959	/**
960	* Formats the current instruction in ARMv8 style.
961	*
962	* This is a simplified version of DISFormatArmV8Ex() provided for your convenience.
963	*
964	*
965	* @returns The number of output characters. If this is >= cchBuf, then the content
966	* of pszBuf will be truncated.
967	* @param pDis Pointer to the disassembler state.
968	* @param pszBuf The output buffer.
969	* @param cchBuf The size of the output buffer.
970	*/
971	DISDECL(size_t) DISFormatArmV8(PCDISSTATE pDis, char *pszBuf, size_t cchBuf)
972	{
973	return DISFormatArmV8Ex(pDis, pszBuf, cchBuf, 0 /* fFlags /, NULL / pfnGetSymbol /, NULL / pvUser */);
974	}

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source: vbox/trunk/src/VBox/Disassembler/DisasmFormatArmV8.cpp@ 106718

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