DisasmFormatArmV8.cpp@ 106056

Last change on this file since 106056 was 106004, checked in by vboxsync, 3 months ago
Disassembler/ArmV8: Updates and start on floating point and SIMD instructions, bugref:10394
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1	/* $Id: DisasmFormatArmV8.cpp 106004 2024-09-10 11:51:08Z vboxsync $ */
2	/** @file
3	* VBox Disassembler - ARMv8 Style Formatter.
4	*/
5
6	/*
7	* Copyright (C) 2008-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#include <VBox/dis.h>
33	#include "DisasmInternal.h"
34	#include "DisasmInternal-armv8.h"
35	#include <iprt/armv8.h>
36	#include <iprt/assert.h>
37	#include <iprt/ctype.h>
38	#include <iprt/errcore.h>
39	#include <iprt/string.h>
40
41
42	/*********************************************************************************************************************************
43	* Global Variables *
44	*********************************************************************************************************************************/
45	static const char g_szSpaces[] =
46	" ";
47	static const char g_aszArmV8RegGen32[32][4] =
48	{
49	"w0\0", "w1\0", "w2\0", "w3\0", "w4\0", "w5\0", "w6\0", "w7\0", "w8\0", "w9\0", "w10", "w11", "w12", "w13", "w14", "w15",
50	"w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wzr"
51	};
52	static const char g_aszArmV8RegGen64[32][4] =
53	{
54	"x0\0", "x1\0", "x2\0", "x3\0", "x4\0", "x5\0", "x6\0", "x7\0", "x8\0", "x9\0", "x10", "x11", "x12", "x13", "x14", "x15",
55	"x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "xzr"
56	};
57	static const char g_aszArmV8RegFpSingle[32][4] =
58	{
59	"s0\0", "s1\0", "s2\0", "s3\0", "s4\0", "s5\0", "s6\0", "s7\0", "s8\0", "s9\0", "s10", "s11", "s12", "s13", "s14", "s15",
60	"s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31"
61	};
62	static const char g_aszArmV8RegFpDouble[32][4] =
63	{
64	"d0\0", "d1\0", "d2\0", "d3\0", "d4\0", "d5\0", "d6\0", "d7\0", "d8\0", "d9\0", "d10", "d11", "d12", "d13", "d14", "d15",
65	"d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31"
66	};
67	static const char g_aszArmV8RegFpHalf[32][4] =
68	{
69	"h0\0", "h1\0", "h2\0", "h3\0", "h4\0", "h5\0", "h6\0", "h7\0", "h8\0", "h9\0", "h10", "h11", "h12", "h13", "h14", "h15",
70	"h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23", "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31"
71	};
72	static const char g_aszArmV8RegSimdScalar128Bit[32][4] =
73	{
74	"q0\0", "q1\0", "q2\0", "q3\0", "q4\0", "q5\0", "q6\0", "q7\0", "q8\0", "q9\0", "q10", "q11", "q12", "q13", "q14", "q15",
75	"q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23", "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31"
76	};
77	static const char g_aszArmV8Cond[16][3] =
78	{
79	"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", "hi", "ls", "ge", "lt", "gt", "le", "al", "al"
80	};
81	static const char *g_apszArmV8PState[] =
82	{
83	/* kDisArmv8InstrPState_SPSel */ "spsel",
84	/* kDisArmv8InstrPState_DAIFSet */ "daifset",
85	/* kDisArmv8InstrPState_DAIFClr */ "daifclr",
86	/* kDisArmv8InstrPState_UAO */ "uao",
87	/* kDisArmv8InstrPState_PAN */ "pan",
88	/* kDisArmv8InstrPState_ALLINT */ "allint",
89	/* kDisArmv8InstrPState_PM */ "pm",
90	/* kDisArmv8InstrPState_SSBS */ "ssbs",
91	/* kDisArmv8InstrPState_DIT */ "dit",
92	/* kDisArmv8InstrPState_SVCRSM */ "svcrsm",
93	/* kDisArmv8InstrPState_SVCRZA */ "svcrza",
94	/* kDisArmv8InstrPState_SVCRSMZA */ "svcrsmza",
95	/* kDisArmv8InstrPState_TCO */ "tco"
96	};
97
98
99	/**
100	* List of known system registers.
101	*
102	* The list MUST be in ascending order of the system register ID!
103	*/
104	static const struct
105	{
106	/** IPRT system register ID. */
107	uint32_t idSysReg;
108	/** Name of the system register. */
109	const char *pszSysReg;
110	/** Character count of the system register name. */
111	size_t cchSysReg;
112	} g_aArmV8SysReg64[] =
113	{
114	#define DIS_ARMV8_SYSREG(a_idSysReg) { (ARMV8_AARCH64_SYSREG_ ## a_idSysReg), #a_idSysReg, sizeof(#a_idSysReg) - 1 }
115	DIS_ARMV8_SYSREG(OSDTRRX_EL1),
116	DIS_ARMV8_SYSREG(MDSCR_EL1),
117	//DIS_ARMV8_SYSREG(DBGBVRn_EL1(a_Id)),
118	//DIS_ARMV8_SYSREG(DBGBCRn_EL1(a_Id)),
119	//DIS_ARMV8_SYSREG(DBGWVRn_EL1(a_Id)),
120	//DIS_ARMV8_SYSREG(DBGWCRn_EL1(a_Id)),
121	DIS_ARMV8_SYSREG(MDCCINT_EL1),
122	DIS_ARMV8_SYSREG(OSDTRTX_EL1),
123	DIS_ARMV8_SYSREG(OSECCR_EL1),
124	DIS_ARMV8_SYSREG(MDRAR_EL1),
125	DIS_ARMV8_SYSREG(OSLAR_EL1),
126	DIS_ARMV8_SYSREG(OSLSR_EL1),
127	DIS_ARMV8_SYSREG(OSDLR_EL1),
128	DIS_ARMV8_SYSREG(MIDR_EL1),
129	DIS_ARMV8_SYSREG(MPIDR_EL1),
130	DIS_ARMV8_SYSREG(REVIDR_EL1),
131	DIS_ARMV8_SYSREG(ID_PFR0_EL1),
132	DIS_ARMV8_SYSREG(ID_PFR1_EL1),
133	DIS_ARMV8_SYSREG(ID_DFR0_EL1),
134	DIS_ARMV8_SYSREG(ID_AFR0_EL1),
135	DIS_ARMV8_SYSREG(ID_MMFR0_EL1),
136	DIS_ARMV8_SYSREG(ID_MMFR1_EL1),
137	DIS_ARMV8_SYSREG(ID_MMFR2_EL1),
138	DIS_ARMV8_SYSREG(ID_MMFR3_EL1),
139	DIS_ARMV8_SYSREG(ID_ISAR0_EL1),
140	DIS_ARMV8_SYSREG(ID_ISAR1_EL1),
141	DIS_ARMV8_SYSREG(ID_ISAR2_EL1),
142	DIS_ARMV8_SYSREG(ID_ISAR3_EL1),
143	DIS_ARMV8_SYSREG(ID_ISAR4_EL1),
144	DIS_ARMV8_SYSREG(ID_ISAR5_EL1),
145	DIS_ARMV8_SYSREG(ID_MMFR4_EL1),
146	DIS_ARMV8_SYSREG(ID_ISAR6_EL1),
147	DIS_ARMV8_SYSREG(MVFR0_EL1),
148	DIS_ARMV8_SYSREG(MVFR1_EL1),
149	DIS_ARMV8_SYSREG(MVFR2_EL1),
150	DIS_ARMV8_SYSREG(ID_PFR2_EL1),
151	DIS_ARMV8_SYSREG(ID_DFR1_EL1),
152	DIS_ARMV8_SYSREG(ID_MMFR5_EL1),
153	DIS_ARMV8_SYSREG(ID_AA64PFR0_EL1),
154	DIS_ARMV8_SYSREG(ID_AA64PFR1_EL1),
155	DIS_ARMV8_SYSREG(ID_AA64ZFR0_EL1),
156	DIS_ARMV8_SYSREG(ID_AA64SMFR0_EL1),
157	DIS_ARMV8_SYSREG(ID_AA64DFR0_EL1),
158	DIS_ARMV8_SYSREG(ID_AA64DFR1_EL1),
159	DIS_ARMV8_SYSREG(ID_AA64AFR0_EL1),
160	DIS_ARMV8_SYSREG(ID_AA64AFR1_EL1),
161	DIS_ARMV8_SYSREG(ID_AA64ISAR0_EL1),
162	DIS_ARMV8_SYSREG(ID_AA64ISAR1_EL1),
163	DIS_ARMV8_SYSREG(ID_AA64ISAR2_EL1),
164	DIS_ARMV8_SYSREG(ID_AA64MMFR0_EL1),
165	DIS_ARMV8_SYSREG(ID_AA64MMFR1_EL1),
166	DIS_ARMV8_SYSREG(ID_AA64MMFR2_EL1),
167	DIS_ARMV8_SYSREG(SCTRL_EL1),
168	DIS_ARMV8_SYSREG(ACTRL_EL1),
169	DIS_ARMV8_SYSREG(CPACR_EL1),
170	DIS_ARMV8_SYSREG(RGSR_EL1),
171	DIS_ARMV8_SYSREG(GCR_EL1),
172	DIS_ARMV8_SYSREG(ZCR_EL1),
173	DIS_ARMV8_SYSREG(TRFCR_EL1),
174	DIS_ARMV8_SYSREG(SMPRI_EL1),
175	DIS_ARMV8_SYSREG(SMCR_EL1),
176	DIS_ARMV8_SYSREG(TTBR0_EL1),
177	DIS_ARMV8_SYSREG(TTBR1_EL1),
178	DIS_ARMV8_SYSREG(TCR_EL1),
179	DIS_ARMV8_SYSREG(APIAKeyLo_EL1),
180	DIS_ARMV8_SYSREG(APIAKeyHi_EL1),
181	DIS_ARMV8_SYSREG(APIBKeyLo_EL1),
182	DIS_ARMV8_SYSREG(APIBKeyHi_EL1),
183	DIS_ARMV8_SYSREG(APDAKeyLo_EL1),
184	DIS_ARMV8_SYSREG(APDAKeyHi_EL1),
185	DIS_ARMV8_SYSREG(APDBKeyLo_EL1),
186	DIS_ARMV8_SYSREG(APDBKeyHi_EL1),
187	DIS_ARMV8_SYSREG(APGAKeyLo_EL1),
188	DIS_ARMV8_SYSREG(APGAKeyHi_EL1),
189	DIS_ARMV8_SYSREG(SPSR_EL1),
190	DIS_ARMV8_SYSREG(ELR_EL1),
191	DIS_ARMV8_SYSREG(SP_EL0),
192	DIS_ARMV8_SYSREG(SPSEL),
193	DIS_ARMV8_SYSREG(CURRENTEL),
194	DIS_ARMV8_SYSREG(PAN),
195	DIS_ARMV8_SYSREG(UAO),
196	DIS_ARMV8_SYSREG(ALLINT),
197	DIS_ARMV8_SYSREG(ICC_PMR_EL1),
198	DIS_ARMV8_SYSREG(AFSR0_EL1),
199	DIS_ARMV8_SYSREG(AFSR1_EL1),
200	DIS_ARMV8_SYSREG(ESR_EL1),
201	DIS_ARMV8_SYSREG(ERRIDR_EL1),
202	DIS_ARMV8_SYSREG(ERRSELR_EL1),
203	DIS_ARMV8_SYSREG(FAR_EL1),
204	DIS_ARMV8_SYSREG(PAR_EL1),
205	DIS_ARMV8_SYSREG(MAIR_EL1),
206	DIS_ARMV8_SYSREG(AMAIR_EL1),
207	DIS_ARMV8_SYSREG(VBAR_EL1),
208	DIS_ARMV8_SYSREG(ICC_IAR0_EL1),
209	DIS_ARMV8_SYSREG(ICC_EOIR0_EL1),
210	DIS_ARMV8_SYSREG(ICC_HPPIR0_EL1),
211	DIS_ARMV8_SYSREG(ICC_BPR0_EL1),
212	DIS_ARMV8_SYSREG(ICC_AP0R0_EL1),
213	DIS_ARMV8_SYSREG(ICC_AP0R1_EL1),
214	DIS_ARMV8_SYSREG(ICC_AP0R2_EL1),
215	DIS_ARMV8_SYSREG(ICC_AP0R3_EL1),
216	DIS_ARMV8_SYSREG(ICC_AP1R0_EL1),
217	DIS_ARMV8_SYSREG(ICC_AP1R1_EL1),
218	DIS_ARMV8_SYSREG(ICC_AP1R2_EL1),
219	DIS_ARMV8_SYSREG(ICC_AP1R3_EL1),
220	DIS_ARMV8_SYSREG(ICC_NMIAR1_EL1),
221	DIS_ARMV8_SYSREG(ICC_DIR_EL1),
222	DIS_ARMV8_SYSREG(ICC_RPR_EL1),
223	DIS_ARMV8_SYSREG(ICC_SGI1R_EL1),
224	DIS_ARMV8_SYSREG(ICC_ASGI1R_EL1),
225	DIS_ARMV8_SYSREG(ICC_SGI0R_EL1),
226	DIS_ARMV8_SYSREG(ICC_IAR1_EL1),
227	DIS_ARMV8_SYSREG(ICC_EOIR1_EL1),
228	DIS_ARMV8_SYSREG(ICC_HPPIR1_EL1),
229	DIS_ARMV8_SYSREG(ICC_BPR1_EL1),
230	DIS_ARMV8_SYSREG(ICC_CTLR_EL1),
231	DIS_ARMV8_SYSREG(ICC_SRE_EL1),
232	DIS_ARMV8_SYSREG(ICC_IGRPEN0_EL1),
233	DIS_ARMV8_SYSREG(ICC_IGRPEN1_EL1),
234	DIS_ARMV8_SYSREG(CONTEXTIDR_EL1),
235	DIS_ARMV8_SYSREG(TPIDR_EL1),
236	DIS_ARMV8_SYSREG(CNTKCTL_EL1),
237	DIS_ARMV8_SYSREG(CSSELR_EL1),
238	DIS_ARMV8_SYSREG(NZCV),
239	DIS_ARMV8_SYSREG(DAIF),
240	DIS_ARMV8_SYSREG(SVCR),
241	DIS_ARMV8_SYSREG(DIT),
242	DIS_ARMV8_SYSREG(SSBS),
243	DIS_ARMV8_SYSREG(TCO),
244	DIS_ARMV8_SYSREG(FPCR),
245	DIS_ARMV8_SYSREG(FPSR),
246	DIS_ARMV8_SYSREG(ICC_SRE_EL2),
247	DIS_ARMV8_SYSREG(TPIDR_EL0),
248	DIS_ARMV8_SYSREG(TPIDRRO_EL0),
249	DIS_ARMV8_SYSREG(CNTFRQ_EL0),
250	DIS_ARMV8_SYSREG(CNTVCT_EL0),
251	DIS_ARMV8_SYSREG(CNTP_TVAL_EL0),
252	DIS_ARMV8_SYSREG(CNTP_CTL_EL0),
253	DIS_ARMV8_SYSREG(CNTP_CVAL_EL0),
254	DIS_ARMV8_SYSREG(CNTV_CTL_EL0),
255	DIS_ARMV8_SYSREG(VPIDR_EL2),
256	DIS_ARMV8_SYSREG(VMPIDR_EL2),
257	DIS_ARMV8_SYSREG(SCTLR_EL2),
258	DIS_ARMV8_SYSREG(ACTLR_EL2),
259	DIS_ARMV8_SYSREG(HCR_EL2),
260	DIS_ARMV8_SYSREG(MDCR_EL2),
261	DIS_ARMV8_SYSREG(CPTR_EL2),
262	DIS_ARMV8_SYSREG(HSTR_EL2),
263	DIS_ARMV8_SYSREG(HFGRTR_EL2),
264	DIS_ARMV8_SYSREG(HFGWTR_EL2),
265	DIS_ARMV8_SYSREG(HFGITR_EL2),
266	DIS_ARMV8_SYSREG(HACR_EL2),
267	DIS_ARMV8_SYSREG(ZCR_EL2),
268	DIS_ARMV8_SYSREG(TRFCR_EL2),
269	DIS_ARMV8_SYSREG(HCRX_EL2),
270	DIS_ARMV8_SYSREG(SDER32_EL2),
271	DIS_ARMV8_SYSREG(TTBR0_EL2),
272	DIS_ARMV8_SYSREG(TTBR1_EL2),
273	DIS_ARMV8_SYSREG(TCR_EL2),
274	DIS_ARMV8_SYSREG(VTTBR_EL2),
275	DIS_ARMV8_SYSREG(VTCR_EL2),
276	DIS_ARMV8_SYSREG(VNCR_EL2),
277	DIS_ARMV8_SYSREG(VSTTBR_EL2),
278	DIS_ARMV8_SYSREG(VSTCR_EL2),
279	DIS_ARMV8_SYSREG(DACR32_EL2),
280	DIS_ARMV8_SYSREG(HDFGRTR_EL2),
281	DIS_ARMV8_SYSREG(HDFGWTR_EL2),
282	DIS_ARMV8_SYSREG(HAFGRTR_EL2),
283	DIS_ARMV8_SYSREG(SPSR_EL2),
284	DIS_ARMV8_SYSREG(ELR_EL2),
285	DIS_ARMV8_SYSREG(SP_EL1),
286	DIS_ARMV8_SYSREG(IFSR32_EL2),
287	DIS_ARMV8_SYSREG(AFSR0_EL2),
288	DIS_ARMV8_SYSREG(AFSR1_EL2),
289	DIS_ARMV8_SYSREG(ESR_EL2),
290	DIS_ARMV8_SYSREG(VSESR_EL2),
291	DIS_ARMV8_SYSREG(FPEXC32_EL2),
292	DIS_ARMV8_SYSREG(TFSR_EL2),
293	DIS_ARMV8_SYSREG(FAR_EL2),
294	DIS_ARMV8_SYSREG(HPFAR_EL2),
295	DIS_ARMV8_SYSREG(PMSCR_EL2),
296	DIS_ARMV8_SYSREG(MAIR_EL2),
297	DIS_ARMV8_SYSREG(AMAIR_EL2),
298	DIS_ARMV8_SYSREG(MPAMHCR_EL2),
299	DIS_ARMV8_SYSREG(MPAMVPMV_EL2),
300	DIS_ARMV8_SYSREG(MPAM2_EL2),
301	DIS_ARMV8_SYSREG(MPAMVPM0_EL2),
302	DIS_ARMV8_SYSREG(MPAMVPM1_EL2),
303	DIS_ARMV8_SYSREG(MPAMVPM2_EL2),
304	DIS_ARMV8_SYSREG(MPAMVPM3_EL2),
305	DIS_ARMV8_SYSREG(MPAMVPM4_EL2),
306	DIS_ARMV8_SYSREG(MPAMVPM5_EL2),
307	DIS_ARMV8_SYSREG(MPAMVPM6_EL2),
308	DIS_ARMV8_SYSREG(MPAMVPM7_EL2),
309	DIS_ARMV8_SYSREG(VBAR_EL2),
310	DIS_ARMV8_SYSREG(RVBAR_EL2),
311	DIS_ARMV8_SYSREG(RMR_EL2),
312	DIS_ARMV8_SYSREG(VDISR_EL2),
313	DIS_ARMV8_SYSREG(CONTEXTIDR_EL2),
314	DIS_ARMV8_SYSREG(TPIDR_EL2),
315	DIS_ARMV8_SYSREG(SCXTNUM_EL2),
316	DIS_ARMV8_SYSREG(CNTVOFF_EL2),
317	DIS_ARMV8_SYSREG(CNTPOFF_EL2),
318	DIS_ARMV8_SYSREG(CNTHCTL_EL2),
319	DIS_ARMV8_SYSREG(CNTHP_TVAL_EL2),
320	DIS_ARMV8_SYSREG(CNTHP_CTL_EL2),
321	DIS_ARMV8_SYSREG(CNTHP_CVAL_EL2),
322	DIS_ARMV8_SYSREG(CNTHV_TVAL_EL2),
323	DIS_ARMV8_SYSREG(CNTHV_CTL_EL2),
324	DIS_ARMV8_SYSREG(CNTHV_CVAL_EL2),
325	DIS_ARMV8_SYSREG(CNTHVS_TVAL_EL2),
326	DIS_ARMV8_SYSREG(CNTHVS_CTL_EL2),
327	DIS_ARMV8_SYSREG(CNTHVS_CVAL_EL2),
328	DIS_ARMV8_SYSREG(CNTHPS_TVAL_EL2),
329	DIS_ARMV8_SYSREG(CNTHPS_CTL_EL2),
330	DIS_ARMV8_SYSREG(CNTHPS_CVAL_EL2),
331	DIS_ARMV8_SYSREG(SP_EL2)
332	#undef DIS_ARMV8_SYSREG
333	};
334
335
336	/**
337	* Gets the base register name for the given parameter.
338	*
339	* @returns Pointer to the register name.
340	* @param pDis The disassembler state.
341	* @param pParam The parameter.
342	* @param pcchReg Where to store the length of the name.
343	*/
344	DECLINLINE(const char ) disasmFormatArmV8Reg(PCDISSTATE pDis, PCDISOPPARAMARMV8REG pReg, size_t pcchReg)
345	{
346	RT_NOREF_PV(pDis);
347
348	switch (pReg->enmRegType)
349	{
350	case kDisOpParamArmV8RegType_Gpr_32Bit:
351	{
352	Assert(pReg->idReg < RT_ELEMENTS(g_aszArmV8RegGen32));
353	const char *psz = g_aszArmV8RegGen32[pReg->idReg];
354	*pcchReg = 2 + !!psz[2];
355	return psz;
356	}
357	case kDisOpParamArmV8RegType_Gpr_64Bit:
358	{
359	Assert(pReg->idReg < RT_ELEMENTS(g_aszArmV8RegGen64));
360	const char *psz = g_aszArmV8RegGen64[pReg->idReg];
361	*pcchReg = 2 + !!psz[2];
362	return psz;
363	}
364	case kDisOpParamArmV8RegType_FpReg_Single:
365	{
366	Assert(pDis->armv8.enmFpType != kDisArmv8InstrFpType_Invalid);
367	Assert(pReg->idReg < RT_ELEMENTS(g_aszArmV8RegFpSingle));
368	const char *psz = g_aszArmV8RegFpSingle[pReg->idReg];
369	*pcchReg = 2 + !!psz[2];
370	return psz;
371	}
372	case kDisOpParamArmV8RegType_FpReg_Double:
373	{
374	Assert(pDis->armv8.enmFpType != kDisArmv8InstrFpType_Invalid);
375	Assert(pReg->idReg < RT_ELEMENTS(g_aszArmV8RegFpDouble));
376	const char *psz = g_aszArmV8RegFpDouble[pReg->idReg];
377	*pcchReg = 2 + !!psz[2];
378	return psz;
379	}
380	case kDisOpParamArmV8RegType_FpReg_Half:
381	{
382	Assert(pDis->armv8.enmFpType != kDisArmv8InstrFpType_Invalid);
383	Assert(pReg->idReg < RT_ELEMENTS(g_aszArmV8RegFpHalf));
384	const char *psz = g_aszArmV8RegFpHalf[pReg->idReg];
385	*pcchReg = 2 + !!psz[2];
386	return psz;
387	}
388	case kDisOpParamArmV8RegType_Simd_Scalar_64Bit:
389	{
390	/* Using the floating point double register names here. */
391	Assert(pReg->idReg < RT_ELEMENTS(g_aszArmV8RegFpDouble));
392	const char *psz = g_aszArmV8RegFpDouble[pReg->idReg];
393	*pcchReg = 2 + !!psz[2];
394	return psz;
395	}
396	case kDisOpParamArmV8RegType_Simd_Scalar_128Bit:
397	{
398	Assert(pReg->idReg < RT_ELEMENTS(g_aszArmV8RegSimdScalar128Bit));
399	const char *psz = g_aszArmV8RegSimdScalar128Bit[pReg->idReg];
400	*pcchReg = 2 + !!psz[2];
401	return psz;
402	}
403	default:
404	AssertFailed();
405	*pcchReg = 0;
406	return NULL;
407	}
408	}
409
410
411	/**
412	* Gets the base register name for the given parameter.
413	*
414	* @returns Pointer to the register name.
415	* @param pDis The disassembler state.
416	* @param pParam The parameter.
417	* @param pachTmp Pointer to temporary string storage when building
418	* the register name.
419	* @param pcchReg Where to store the length of the name.
420	*/
421	static const char disasmFormatArmV8SysReg(PCDISSTATE pDis, PCDISOPPARAM pParam, char pachTmp, size_t *pcchReg)
422	{
423	RT_NOREF_PV(pDis);
424
425	/* Try to find the system register ID in the table. */
426	/** @todo Binary search (lazy). */
427	for (uint32_t i = 0; i < RT_ELEMENTS(g_aArmV8SysReg64); i++)
428	{
429	if (g_aArmV8SysReg64[i].idSysReg == pParam->armv8.Op.idSysReg)
430	{
431	*pcchReg = g_aArmV8SysReg64[i].cchSysReg;
432	return g_aArmV8SysReg64[i].pszSysReg;
433	}
434	}
435
436	/* Generate S<op0>_<op1>_<Cn>_<Cm>_<op2> identifier. */
437	uint32_t const idSysReg = pParam->armv8.Op.idSysReg;
438	uint8_t idx = 0;
439	pachTmp[idx++] = 'S';
440	pachTmp[idx++] = '2' + ((idSysReg >> 14) & 0x1);
441	pachTmp[idx++] = '_';
442	pachTmp[idx++] = '0' + ((idSysReg >> 11) & 0x7);
443	pachTmp[idx++] = '_';
444
445	uint8_t bTmp = (idSysReg >> 7) & 0xf;
446	if (bTmp >= 10)
447	{
448	pachTmp[idx++] = '1' + (bTmp - 10);
449	bTmp -= 10;
450	}
451	pachTmp[idx++] = '0' + bTmp;
452	pachTmp[idx++] = '_';
453
454	bTmp = (idSysReg >> 3) & 0xf;
455	if (bTmp >= 10)
456	{
457	pachTmp[idx++] = '1' + (bTmp - 10);
458	bTmp -= 10;
459	}
460	pachTmp[idx++] = '0' + bTmp;
461
462	pachTmp[idx++] = '_';
463	pachTmp[idx++] = '0' + (idSysReg & 0x7);
464	pachTmp[idx] = '\0';
465	*pcchReg = idx;
466	return pachTmp;
467	}
468
469
470	/**
471	* Formats the current instruction in ARMv8 style.
472	*
473	*
474	* @returns The number of output characters. If this is >= cchBuf, then the content
475	* of pszBuf will be truncated.
476	* @param pDis Pointer to the disassembler state.
477	* @param pszBuf The output buffer.
478	* @param cchBuf The size of the output buffer.
479	* @param fFlags Format flags, see DIS_FORMAT_FLAGS_*.
480	* @param pfnGetSymbol Get symbol name for a jmp or call target address. Optional.
481	* @param pvUser User argument for pfnGetSymbol.
482	*/
483	DISDECL(size_t) DISFormatArmV8Ex(PCDISSTATE pDis, char *pszBuf, size_t cchBuf, uint32_t fFlags,
484	PFNDISGETSYMBOL pfnGetSymbol, void *pvUser)
485	{
486	/*
487	* Input validation and massaging.
488	*/
489	AssertPtr(pDis);
490	AssertPtrNull(pszBuf);
491	Assert(pszBuf \|\| !cchBuf);
492	AssertPtrNull(pfnGetSymbol);
493	AssertMsg(DIS_FMT_FLAGS_IS_VALID(fFlags), ("%#x\n", fFlags));
494	if (fFlags & DIS_FMT_FLAGS_ADDR_COMMENT)
495	fFlags = (fFlags & ~DIS_FMT_FLAGS_ADDR_LEFT) \| DIS_FMT_FLAGS_ADDR_RIGHT;
496	if (fFlags & DIS_FMT_FLAGS_BYTES_COMMENT)
497	fFlags = (fFlags & ~DIS_FMT_FLAGS_BYTES_LEFT) \| DIS_FMT_FLAGS_BYTES_RIGHT;
498
499	PCDISOPCODE const pOp = pDis->pCurInstr;
500
501	/*
502	* Output macros
503	*/
504	char *pszDst = pszBuf;
505	size_t cchDst = cchBuf;
506	size_t cchOutput = 0;
507	#define PUT_C(ch) \
508	do { \
509	cchOutput++; \
510	if (cchDst > 1) \
511	{ \
512	cchDst--; \
513	*pszDst++ = (ch); \
514	} \
515	} while (0)
516	#define PUT_STR(pszSrc, cchSrc) \
517	do { \
518	cchOutput += (cchSrc); \
519	if (cchDst > (cchSrc)) \
520	{ \
521	memcpy(pszDst, (pszSrc), (cchSrc)); \
522	pszDst += (cchSrc); \
523	cchDst -= (cchSrc); \
524	} \
525	else if (cchDst > 1) \
526	{ \
527	memcpy(pszDst, (pszSrc), cchDst - 1); \
528	pszDst += cchDst - 1; \
529	cchDst = 1; \
530	} \
531	} while (0)
532	#define PUT_SZ(sz) \
533	PUT_STR((sz), sizeof(sz) - 1)
534	#define PUT_SZ_STRICT(szStrict, szRelaxed) \
535	do { if (fFlags & DIS_FMT_FLAGS_STRICT) PUT_SZ(szStrict); else PUT_SZ(szRelaxed); } while (0)
536	#define PUT_PSZ(psz) \
537	do { const size_t cchTmp = strlen(psz); PUT_STR((psz), cchTmp); } while (0)
538	#define PUT_NUM(cch, fmt, num) \
539	do { \
540	cchOutput += (cch); \
541	if (cchDst > 1) \
542	{ \
543	const size_t cchTmp = RTStrPrintf(pszDst, cchDst, fmt, (num)); \
544	pszDst += cchTmp; \
545	cchDst -= cchTmp; \
546	Assert(cchTmp == (cch) \|\| cchDst == 1); \
547	} \
548	} while (0)
549	/** @todo add two flags for choosing between %X / %x and h / 0x. */
550	#define PUT_NUM_8(num) PUT_NUM(4, "0x%02x", (uint8_t)(num))
551	#define PUT_NUM_16(num) PUT_NUM(6, "0x%04x", (uint16_t)(num))
552	#define PUT_NUM_32(num) PUT_NUM(10, "0x%08x", (uint32_t)(num))
553	#define PUT_NUM_64(num) PUT_NUM(18, "0x%016RX64", (uint64_t)(num))
554
555	#define PUT_NUM_SIGN(cch, fmt, num, stype, utype) \
556	do { \
557	if ((stype)(num) >= 0) \
558	{ \
559	PUT_C('+'); \
560	PUT_NUM(cch, fmt, (utype)(num)); \
561	} \
562	else \
563	{ \
564	PUT_C('-'); \
565	PUT_NUM(cch, fmt, (utype)-(stype)(num)); \
566	} \
567	} while (0)
568	#define PUT_NUM_S8(num) PUT_NUM_SIGN(4, "0x%02x", num, int8_t, uint8_t)
569	#define PUT_NUM_S16(num) PUT_NUM_SIGN(6, "0x%04x", num, int16_t, uint16_t)
570	#define PUT_NUM_S32(num) PUT_NUM_SIGN(10, "0x%08x", num, int32_t, uint32_t)
571	#define PUT_NUM_S64(num) PUT_NUM_SIGN(18, "0x%016RX64", num, int64_t, uint64_t)
572
573	#define PUT_SYMBOL_TWO(a_rcSym, a_szStart, a_chEnd) \
574	do { \
575	if (RT_SUCCESS(a_rcSym)) \
576	{ \
577	PUT_SZ(a_szStart); \
578	PUT_PSZ(szSymbol); \
579	if (off != 0) \
580	{ \
581	if ((int8_t)off == off) \
582	PUT_NUM_S8(off); \
583	else if ((int16_t)off == off) \
584	PUT_NUM_S16(off); \
585	else if ((int32_t)off == off) \
586	PUT_NUM_S32(off); \
587	else \
588	PUT_NUM_S64(off); \
589	} \
590	PUT_C(a_chEnd); \
591	} \
592	} while (0)
593
594	#define PUT_SYMBOL(a_uSeg, a_uAddr, a_szStart, a_chEnd) \
595	do { \
596	if (pfnGetSymbol) \
597	{ \
598	int rcSym = pfnGetSymbol(pDis, a_uSeg, a_uAddr, szSymbol, sizeof(szSymbol), &off, pvUser); \
599	PUT_SYMBOL_TWO(rcSym, a_szStart, a_chEnd); \
600	} \
601	} while (0)
602
603
604	/*
605	* The address?
606	*/
607	if (fFlags & DIS_FMT_FLAGS_ADDR_LEFT)
608	{
609	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
610	if (pDis->uInstrAddr >= _4G)
611	PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
612	#endif
613	PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
614	PUT_C(' ');
615	}
616
617	/*
618	* The opcode bytes?
619	*/
620	if (fFlags & DIS_FMT_FLAGS_BYTES_LEFT)
621	{
622	size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
623	cchOutput += cchTmp;
624	if (cchDst > 1)
625	{
626	if (cchTmp <= cchDst)
627	{
628	cchDst -= cchTmp;
629	pszDst += cchTmp;
630	}
631	else
632	{
633	pszDst += cchDst - 1;
634	cchDst = 1;
635	}
636	}
637
638	/* Some padding to align the instruction. */
639	size_t cchPadding = (7 * (2 + !!(fFlags & DIS_FMT_FLAGS_BYTES_SPACED)))
640	+ !!(fFlags & DIS_FMT_FLAGS_BYTES_BRACKETS) * 2
641	+ 2;
642	cchPadding = cchTmp + 1 >= cchPadding ? 1 : cchPadding - cchTmp;
643	PUT_STR(g_szSpaces, cchPadding);
644	}
645
646
647	/*
648	* Filter out invalid opcodes first as they need special
649	* treatment. UDF is an exception and should be handled normally.
650	*/
651	size_t const offInstruction = cchOutput;
652	if (pOp->uOpcode == OP_INVALID)
653	PUT_SZ("Illegal opcode");
654	else
655	{
656	/* Start with the instruction. */
657	PUT_PSZ(pOp->pszOpcode);
658
659	/* Add any conditionals. */
660	if (pDis->armv8.enmCond != kDisArmv8InstrCond_Al)
661	{
662	PUT_C('.');
663	Assert((uint16_t)pDis->armv8.enmCond < RT_ELEMENTS(g_aszArmV8Cond));
664	PUT_STR(g_aszArmV8Cond[pDis->armv8.enmCond], sizeof(g_aszArmV8Cond[0]) - 1);
665	}
666
667	/*
668	* Format the parameters.
669	*/
670	RTINTPTR off;
671	char szSymbol[128];
672	for (uint32_t i = 0; i < RT_ELEMENTS(pDis->aParams); i++)
673	{
674	PCDISOPPARAM pParam = &pDis->aParams[i];
675
676	/* First None parameter marks end of parameters. */
677	if (pParam->armv8.enmType == kDisArmv8OpParmNone)
678	break;
679
680	if (i > 0)
681	PUT_C(',');
682	PUT_C(' '); /** @todo Make the indenting configurable. */
683
684	switch (pParam->armv8.enmType)
685	{
686	case kDisArmv8OpParmImm:
687	{
688	PUT_C('#');
689	switch (pParam->fUse & ( DISUSE_IMMEDIATE8 \| DISUSE_IMMEDIATE16 \| DISUSE_IMMEDIATE32 \| DISUSE_IMMEDIATE64
690	\| DISUSE_IMMEDIATE16_SX8 \| DISUSE_IMMEDIATE32_SX8 \| DISUSE_IMMEDIATE64_SX8))
691	{
692	case DISUSE_IMMEDIATE8:
693	PUT_NUM_8(pParam->uValue);
694	break;
695	case DISUSE_IMMEDIATE16:
696	PUT_NUM_16(pParam->uValue);
697	break;
698	case DISUSE_IMMEDIATE16_SX8:
699	PUT_NUM_16(pParam->uValue);
700	break;
701	case DISUSE_IMMEDIATE32:
702	PUT_NUM_32(pParam->uValue);
703	/** @todo Symbols */
704	break;
705	case DISUSE_IMMEDIATE32_SX8:
706	PUT_NUM_32(pParam->uValue);
707	break;
708	case DISUSE_IMMEDIATE64_SX8:
709	PUT_NUM_64(pParam->uValue);
710	break;
711	case DISUSE_IMMEDIATE64:
712	PUT_NUM_64(pParam->uValue);
713	/** @todo Symbols */
714	break;
715	default:
716	AssertFailed();
717	break;
718	}
719	break;
720	}
721	case kDisArmv8OpParmImmRel:
722	/case kDisParmParseImmAdr:/
723	{
724	int32_t offDisplacement;
725
726	PUT_C('#');
727	if (pParam->fUse & DISUSE_IMMEDIATE8_REL)
728	{
729	offDisplacement = (int8_t)pParam->uValue;
730	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
731	PUT_NUM_S8(offDisplacement * sizeof(uint32_t));
732	}
733	else if (pParam->fUse & DISUSE_IMMEDIATE16_REL)
734	{
735	offDisplacement = (int16_t)pParam->uValue;
736	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
737	PUT_NUM_S16(offDisplacement * sizeof(uint32_t));
738	}
739	else
740	{
741	offDisplacement = (int32_t)pParam->uValue;
742	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
743	PUT_NUM_S32(offDisplacement * sizeof(uint32_t));
744	}
745	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
746	PUT_SZ(" ; (");
747
748	RTUINTPTR uTrgAddr = pDis->uInstrAddr + (offDisplacement * sizeof(uint32_t));
749	if ( pDis->uCpuMode == DISCPUMODE_ARMV8_A32
750	\|\| pDis->uCpuMode == DISCPUMODE_ARMV8_T32)
751	PUT_NUM_32(uTrgAddr);
752	else if (pDis->uCpuMode == DISCPUMODE_ARMV8_A64)
753	PUT_NUM_64(uTrgAddr);
754	else
755	AssertReleaseFailed();
756
757	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
758	{
759	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " = ", ' ');
760	PUT_C(')');
761	}
762	else
763	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " (", ')');
764	break;
765	}
766	case kDisArmv8OpParmReg:
767	{
768	Assert(!(pParam->fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32)));
769
770	size_t cchReg;
771	const char *pszReg = disasmFormatArmV8Reg(pDis, &pParam->armv8.Op.Reg, &cchReg);
772	PUT_STR(pszReg, cchReg);
773	break;
774	}
775	case kDisArmv8OpParmSysReg:
776	{
777	Assert(pParam->fUse == DISUSE_REG_SYSTEM);
778
779	size_t cchReg;
780	char achTmp[32];
781	const char *pszReg = disasmFormatArmV8SysReg(pDis, pParam, &achTmp[0], &cchReg);
782	PUT_STR(pszReg, cchReg);
783	break;
784	}
785	case kDisArmv8OpParmAddrInGpr:
786	{
787	Assert( (pParam->fUse & (DISUSE_PRE_INDEXED \| DISUSE_POST_INDEXED))
788	!= (DISUSE_PRE_INDEXED \| DISUSE_POST_INDEXED));
789	Assert( ( RT_BOOL(pParam->fUse & (DISUSE_PRE_INDEXED \| DISUSE_POST_INDEXED))
790	!= RT_BOOL(pParam->fUse & DISUSE_INDEX))
791	\|\| !(pParam->fUse & (DISUSE_PRE_INDEXED \| DISUSE_POST_INDEXED \| DISUSE_INDEX)));
792
793	PUT_C('[');
794
795	size_t cchReg;
796	const char *pszReg = disasmFormatArmV8Reg(pDis, &pParam->armv8.Op.Reg, &cchReg);
797	PUT_STR(pszReg, cchReg);
798
799	if (pParam->fUse & DISUSE_POST_INDEXED)
800	{
801	Assert(pParam->armv8.enmExtend == kDisArmv8OpParmExtendNone);
802	PUT_SZ("], #");
803	PUT_NUM_S16(pParam->armv8.u.offBase);
804	}
805	else
806	{
807	if (pParam->fUse & DISUSE_INDEX)
808	{
809	PUT_SZ(", ");
810
811	pszReg = disasmFormatArmV8Reg(pDis, &pParam->armv8.GprIndex, &cchReg);
812	PUT_STR(pszReg, cchReg);
813	}
814	else if (pParam->armv8.u.offBase)
815	{
816	PUT_SZ(", #");
817	PUT_NUM_S16(pParam->armv8.u.offBase);
818	}
819
820	if (pParam->armv8.enmExtend != kDisArmv8OpParmExtendNone)
821	{
822	PUT_SZ(", ");
823	switch (pParam->armv8.enmExtend)
824	{
825	case kDisArmv8OpParmExtendUxtX: /* UXTX is same as LSL which is preferred by most disassemblers/assemblers. */
826	case kDisArmv8OpParmExtendLsl:
827	PUT_SZ("LSL #");
828	break;
829	case kDisArmv8OpParmExtendUxtB: PUT_SZ("UXTB #"); break;
830	case kDisArmv8OpParmExtendUxtH: PUT_SZ("UXTH #"); break;
831	case kDisArmv8OpParmExtendUxtW: PUT_SZ("UXTW #"); break;
832	case kDisArmv8OpParmExtendSxtB: PUT_SZ("SXTB #"); break;
833	case kDisArmv8OpParmExtendSxtH: PUT_SZ("SXTH #"); break;
834	case kDisArmv8OpParmExtendSxtW: PUT_SZ("SXTW #"); break;
835	case kDisArmv8OpParmExtendSxtX: PUT_SZ("SXTX #"); break;
836	default:
837	AssertFailed();
838	}
839	PUT_NUM_8(pParam->armv8.u.cExtend);
840	}
841
842	PUT_C(']');
843
844	if (pParam->fUse & DISUSE_PRE_INDEXED)
845	PUT_C('!');
846	}
847
848	break;
849	}
850	case kDisArmv8OpParmCond:
851	{
852	Assert((uint16_t)pParam->armv8.Op.enmCond < RT_ELEMENTS(g_aszArmV8Cond));
853	PUT_STR(g_aszArmV8Cond[pParam->armv8.Op.enmCond], sizeof(g_aszArmV8Cond[0]) - 1);
854	break;
855	}
856	case kDisArmv8OpParmPState:
857	{
858	Assert((uint16_t)pParam->armv8.Op.enmPState < RT_ELEMENTS(g_apszArmV8PState));
859	PUT_PSZ(g_apszArmV8PState[pParam->armv8.Op.enmPState]);
860	break;
861	}
862	default:
863	AssertFailed();
864	}
865
866	if ( pParam->armv8.enmType != kDisArmv8OpParmAddrInGpr
867	&& pParam->armv8.enmExtend != kDisArmv8OpParmExtendNone)
868	{
869	Assert( pParam->armv8.enmType == kDisArmv8OpParmImm
870	\|\| pParam->armv8.enmType == kDisArmv8OpParmReg);
871	PUT_SZ(", ");
872	switch (pParam->armv8.enmExtend)
873	{
874	case kDisArmv8OpParmExtendLsl:
875	PUT_SZ("LSL #");
876	break;
877	case kDisArmv8OpParmExtendLsr:
878	PUT_SZ("LSR #");
879	break;
880	case kDisArmv8OpParmExtendAsr:
881	PUT_SZ("ASR #");
882	break;
883	case kDisArmv8OpParmExtendRor:
884	PUT_SZ("ROR #");
885	break;
886	default:
887	AssertFailed();
888	}
889	PUT_NUM_8(pParam->armv8.u.cExtend);
890	}
891	}
892	}
893
894	/*
895	* Any additional output to the right of the instruction?
896	*/
897	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
898	{
899	/* some up front padding. */
900	size_t cchPadding = cchOutput - offInstruction;
901	cchPadding = cchPadding + 1 >= 42 ? 1 : 42 - cchPadding;
902	PUT_STR(g_szSpaces, cchPadding);
903
904	/* comment? */
905	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
906	PUT_SZ(";");
907
908	/*
909	* The address?
910	*/
911	if (fFlags & DIS_FMT_FLAGS_ADDR_RIGHT)
912	{
913	PUT_C(' ');
914	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
915	if (pDis->uInstrAddr >= _4G)
916	PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
917	#endif
918	PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
919	}
920
921	/*
922	* Opcode bytes?
923	*/
924	if (fFlags & DIS_FMT_FLAGS_BYTES_RIGHT)
925	{
926	PUT_C(' ');
927	size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
928	cchOutput += cchTmp;
929	if (cchTmp >= cchDst)
930	cchTmp = cchDst - (cchDst != 0);
931	cchDst -= cchTmp;
932	pszDst += cchTmp;
933	}
934	}
935
936	/*
937	* Terminate it - on overflow we'll have reserved one byte for this.
938	*/
939	if (cchDst > 0)
940	*pszDst = '\0';
941	else
942	Assert(!cchBuf);
943
944	/* clean up macros */
945	#undef PUT_PSZ
946	#undef PUT_SZ
947	#undef PUT_STR
948	#undef PUT_C
949	return cchOutput;
950	}
951
952
953	/**
954	* Formats the current instruction in ARMv8 style.
955	*
956	* This is a simplified version of DISFormatArmV8Ex() provided for your convenience.
957	*
958	*
959	* @returns The number of output characters. If this is >= cchBuf, then the content
960	* of pszBuf will be truncated.
961	* @param pDis Pointer to the disassembler state.
962	* @param pszBuf The output buffer.
963	* @param cchBuf The size of the output buffer.
964	*/
965	DISDECL(size_t) DISFormatArmV8(PCDISSTATE pDis, char *pszBuf, size_t cchBuf)
966	{
967	return DISFormatArmV8Ex(pDis, pszBuf, cchBuf, 0 /* fFlags /, NULL / pfnGetSymbol /, NULL / pvUser */);
968	}

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source: vbox/trunk/src/VBox/Disassembler/DisasmFormatArmV8.cpp@ 106056

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