DisasmFormatYasm.cpp@ 41761

Last change on this file since 41761 was 41761, checked in by vboxsync, 13 years ago
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1	/* $Id: DisasmFormatYasm.cpp 41761 2012-06-15 16:03:37Z vboxsync $ */
2	/** @file
3	* VBox Disassembler - Yasm(/Nasm) Style Formatter.
4	*/
5
6	/*
7	* Copyright (C) 2008-2012 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#include <VBox/dis.h>
23	#include "DisasmInternal.h"
24	#include <iprt/string.h>
25	#include <iprt/assert.h>
26	#include <iprt/ctype.h>
27
28
29	/*******************************************************************************
30	* Global Variables *
31	*******************************************************************************/
32	static const char g_szSpaces[] =
33	" ";
34	static const char g_aszYasmRegGen8[20][5] =
35	{
36	"al\0\0", "cl\0\0", "dl\0\0", "bl\0\0", "ah\0\0", "ch\0\0", "dh\0\0", "bh\0\0", "r8b\0", "r9b\0", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b", "spl\0", "bpl\0", "sil\0", "dil\0"
37	};
38	static const char g_aszYasmRegGen16[16][5] =
39	{
40	"ax\0\0", "cx\0\0", "dx\0\0", "bx\0\0", "sp\0\0", "bp\0\0", "si\0\0", "di\0\0", "r8w\0", "r9w\0", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
41	};
42	static const char g_aszYasmRegGen1616[8][6] =
43	{
44	"bx+si", "bx+di", "bp+si", "bp+di", "si\0\0\0", "di\0\0\0", "bp\0\0\0", "bx\0\0\0"
45	};
46	static const char g_aszYasmRegGen32[16][5] =
47	{
48	"eax\0", "ecx\0", "edx\0", "ebx\0", "esp\0", "ebp\0", "esi\0", "edi\0", "r8d\0", "r9d\0", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
49	};
50	static const char g_aszYasmRegGen64[16][4] =
51	{
52	"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", "r8\0", "r9\0", "r10", "r11", "r12", "r13", "r14", "r15"
53	};
54	static const char g_aszYasmRegSeg[6][3] =
55	{
56	"es", "cs", "ss", "ds", "fs", "gs"
57	};
58	static const char g_aszYasmRegFP[8][4] =
59	{
60	"st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7"
61	};
62	static const char g_aszYasmRegMMX[8][4] =
63	{
64	"mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7"
65	};
66	static const char g_aszYasmRegXMM[16][6] =
67	{
68	"xmm0\0", "xmm1\0", "xmm2\0", "xmm3\0", "xmm4\0", "xmm5\0", "xmm6\0", "xmm7\0", "xmm8\0", "xmm9\0", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
69	};
70	static const char g_aszYasmRegCRx[16][5] =
71	{
72	"cr0\0", "cr1\0", "cr2\0", "cr3\0", "cr4\0", "cr5\0", "cr6\0", "cr7\0", "cr8\0", "cr9\0", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15"
73	};
74	static const char g_aszYasmRegDRx[16][5] =
75	{
76	"dr0\0", "dr1\0", "dr2\0", "dr3\0", "dr4\0", "dr5\0", "dr6\0", "dr7\0", "dr8\0", "dr9\0", "dr10", "dr11", "dr12", "dr13", "dr14", "dr15"
77	};
78	static const char g_aszYasmRegTRx[16][5] =
79	{
80	"tr0\0", "tr1\0", "tr2\0", "tr3\0", "tr4\0", "tr5\0", "tr6\0", "tr7\0", "tr8\0", "tr9\0", "tr10", "tr11", "tr12", "tr13", "tr14", "tr15"
81	};
82
83
84
85	/**
86	* Gets the base register name for the given parameter.
87	*
88	* @returns Pointer to the register name.
89	* @param pCpu The disassembler cpu state.
90	* @param pParam The parameter.
91	* @param pcchReg Where to store the length of the name.
92	*/
93	static const char disasmFormatYasmBaseReg(PCDISCPUSTATE pCpu, PCDISOPPARAM pParam, size_t pcchReg)
94	{
95	switch (pParam->fUse & ( DISUSE_REG_GEN8 \| DISUSE_REG_GEN16 \| DISUSE_REG_GEN32 \| DISUSE_REG_GEN64
96	\| DISUSE_REG_FP \| DISUSE_REG_MMX \| DISUSE_REG_XMM \| DISUSE_REG_CR
97	\| DISUSE_REG_DBG \| DISUSE_REG_SEG \| DISUSE_REG_TEST))
98
99	{
100	case DISUSE_REG_GEN8:
101	{
102	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen8));
103	const char *psz = g_aszYasmRegGen8[pParam->Base.idxGenReg];
104	*pcchReg = 2 + !!psz[2] + !!psz[3];
105	return psz;
106	}
107
108	case DISUSE_REG_GEN16:
109	{
110	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
111	const char *psz = g_aszYasmRegGen16[pParam->Base.idxGenReg];
112	*pcchReg = 2 + !!psz[2] + !!psz[3];
113	return psz;
114	}
115
116	case DISUSE_REG_GEN32:
117	{
118	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
119	const char *psz = g_aszYasmRegGen32[pParam->Base.idxGenReg];
120	*pcchReg = 2 + !!psz[2] + !!psz[3];
121	return psz;
122	}
123
124	case DISUSE_REG_GEN64:
125	{
126	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
127	const char *psz = g_aszYasmRegGen64[pParam->Base.idxGenReg];
128	*pcchReg = 2 + !!psz[2] + !!psz[3];
129	return psz;
130	}
131
132	case DISUSE_REG_FP:
133	{
134	Assert(pParam->Base.idxFpuReg < RT_ELEMENTS(g_aszYasmRegFP));
135	const char *psz = g_aszYasmRegFP[pParam->Base.idxFpuReg];
136	*pcchReg = 3;
137	return psz;
138	}
139
140	case DISUSE_REG_MMX:
141	{
142	Assert(pParam->Base.idxMmxReg < RT_ELEMENTS(g_aszYasmRegMMX));
143	const char *psz = g_aszYasmRegMMX[pParam->Base.idxMmxReg];
144	*pcchReg = 3;
145	return psz;
146	}
147
148	case DISUSE_REG_XMM:
149	{
150	Assert(pParam->Base.idxXmmReg < RT_ELEMENTS(g_aszYasmRegXMM));
151	const char *psz = g_aszYasmRegXMM[pParam->Base.idxMmxReg];
152	*pcchReg = 4 + !!psz[4];
153	return psz;
154	}
155
156	case DISUSE_REG_CR:
157	{
158	Assert(pParam->Base.idxCtrlReg < RT_ELEMENTS(g_aszYasmRegCRx));
159	const char *psz = g_aszYasmRegCRx[pParam->Base.idxCtrlReg];
160	*pcchReg = 3;
161	return psz;
162	}
163
164	case DISUSE_REG_DBG:
165	{
166	Assert(pParam->Base.idxDbgReg < RT_ELEMENTS(g_aszYasmRegDRx));
167	const char *psz = g_aszYasmRegDRx[pParam->Base.idxDbgReg];
168	*pcchReg = 3;
169	return psz;
170	}
171
172	case DISUSE_REG_SEG:
173	{
174	Assert(pParam->Base.idxSegReg < RT_ELEMENTS(g_aszYasmRegCRx));
175	const char *psz = g_aszYasmRegSeg[pParam->Base.idxSegReg];
176	*pcchReg = 2;
177	return psz;
178	}
179
180	case DISUSE_REG_TEST:
181	{
182	Assert(pParam->Base.idxTestReg < RT_ELEMENTS(g_aszYasmRegTRx));
183	const char *psz = g_aszYasmRegTRx[pParam->Base.idxTestReg];
184	*pcchReg = 3;
185	return psz;
186	}
187
188	default:
189	AssertMsgFailed(("%#x\n", pParam->fUse));
190	*pcchReg = 3;
191	return "r??";
192	}
193	}
194
195
196	/**
197	* Gets the index register name for the given parameter.
198	*
199	* @returns The index register name.
200	* @param pCpu The disassembler cpu state.
201	* @param pParam The parameter.
202	* @param pcchReg Where to store the length of the name.
203	*/
204	static const char disasmFormatYasmIndexReg(PCDISCPUSTATE pCpu, PCDISOPPARAM pParam, size_t pcchReg)
205	{
206	switch (pCpu->uAddrMode)
207	{
208	case DISCPUMODE_16BIT:
209	{
210	Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
211	const char *psz = g_aszYasmRegGen16[pParam->Index.idxGenReg];
212	*pcchReg = 2 + !!psz[2] + !!psz[3];
213	return psz;
214	}
215
216	case DISCPUMODE_32BIT:
217	{
218	Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
219	const char *psz = g_aszYasmRegGen32[pParam->Index.idxGenReg];
220	*pcchReg = 2 + !!psz[2] + !!psz[3];
221	return psz;
222	}
223
224	case DISCPUMODE_64BIT:
225	{
226	Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
227	const char *psz = g_aszYasmRegGen64[pParam->Index.idxGenReg];
228	*pcchReg = 2 + !!psz[2] + !!psz[3];
229	return psz;
230	}
231
232	default:
233	AssertMsgFailed(("%#x %#x\n", pParam->fUse, pCpu->uAddrMode));
234	*pcchReg = 3;
235	return "r??";
236	}
237	}
238
239
240	/**
241	* Formats the current instruction in Yasm (/ Nasm) style.
242	*
243	*
244	* @returns The number of output characters. If this is >= cchBuf, then the content
245	* of pszBuf will be truncated.
246	* @param pCpu Pointer to the disassembler CPU state.
247	* @param pszBuf The output buffer.
248	* @param cchBuf The size of the output buffer.
249	* @param fFlags Format flags, see DIS_FORMAT_FLAGS_*.
250	* @param pfnGetSymbol Get symbol name for a jmp or call target address. Optional.
251	* @param pvUser User argument for pfnGetSymbol.
252	*/
253	DISDECL(size_t) DISFormatYasmEx(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags,
254	PFNDISGETSYMBOL pfnGetSymbol, void *pvUser)
255	{
256	/*
257	* Input validation and massaging.
258	*/
259	AssertPtr(pCpu);
260	AssertPtrNull(pszBuf);
261	Assert(pszBuf \|\| !cchBuf);
262	AssertPtrNull(pfnGetSymbol);
263	AssertMsg(DIS_FMT_FLAGS_IS_VALID(fFlags), ("%#x\n", fFlags));
264	if (fFlags & DIS_FMT_FLAGS_ADDR_COMMENT)
265	fFlags = (fFlags & ~DIS_FMT_FLAGS_ADDR_LEFT) \| DIS_FMT_FLAGS_ADDR_RIGHT;
266	if (fFlags & DIS_FMT_FLAGS_BYTES_COMMENT)
267	fFlags = (fFlags & ~DIS_FMT_FLAGS_BYTES_LEFT) \| DIS_FMT_FLAGS_BYTES_RIGHT;
268
269	PCDISOPCODE const pOp = pCpu->pCurInstr;
270
271	/*
272	* Output macros
273	*/
274	char *pszDst = pszBuf;
275	size_t cchDst = cchBuf;
276	size_t cchOutput = 0;
277	#define PUT_C(ch) \
278	do { \
279	cchOutput++; \
280	if (cchDst > 1) \
281	{ \
282	cchDst--; \
283	*pszDst++ = (ch); \
284	} \
285	} while (0)
286	#define PUT_STR(pszSrc, cchSrc) \
287	do { \
288	cchOutput += (cchSrc); \
289	if (cchDst > (cchSrc)) \
290	{ \
291	memcpy(pszDst, (pszSrc), (cchSrc)); \
292	pszDst += (cchSrc); \
293	cchDst -= (cchSrc); \
294	} \
295	else if (cchDst > 1) \
296	{ \
297	memcpy(pszDst, (pszSrc), cchDst - 1); \
298	pszDst += cchDst - 1; \
299	cchDst = 1; \
300	} \
301	} while (0)
302	#define PUT_SZ(sz) \
303	PUT_STR((sz), sizeof(sz) - 1)
304	#define PUT_SZ_STRICT(szStrict, szRelaxed) \
305	do { if (fFlags & DIS_FMT_FLAGS_STRICT) PUT_SZ(szStrict); else PUT_SZ(szRelaxed); } while (0)
306	#define PUT_PSZ(psz) \
307	do { const size_t cchTmp = strlen(psz); PUT_STR((psz), cchTmp); } while (0)
308	#define PUT_NUM(cch, fmt, num) \
309	do { \
310	cchOutput += (cch); \
311	if (cchDst > 1) \
312	{ \
313	const size_t cchTmp = RTStrPrintf(pszDst, cchDst, fmt, (num)); \
314	pszDst += cchTmp; \
315	cchDst -= cchTmp; \
316	Assert(cchTmp == (cch) \|\| cchDst == 1); \
317	} \
318	} while (0)
319	/** @todo add two flags for choosing between %X / %x and h / 0x. */
320	#define PUT_NUM_8(num) PUT_NUM(4, "0%02xh", (uint8_t)(num))
321	#define PUT_NUM_16(num) PUT_NUM(6, "0%04xh", (uint16_t)(num))
322	#define PUT_NUM_32(num) PUT_NUM(10, "0%08xh", (uint32_t)(num))
323	#define PUT_NUM_64(num) PUT_NUM(18, "0%016RX64h", (uint64_t)(num))
324
325	#define PUT_NUM_SIGN(cch, fmt, num, stype, utype) \
326	do { \
327	if ((stype)(num) >= 0) \
328	{ \
329	PUT_C('+'); \
330	PUT_NUM(cch, fmt, (utype)(num)); \
331	} \
332	else \
333	{ \
334	PUT_C('-'); \
335	PUT_NUM(cch, fmt, (utype)-(stype)(num)); \
336	} \
337	} while (0)
338	#define PUT_NUM_S8(num) PUT_NUM_SIGN(4, "0%02xh", num, int8_t, uint8_t)
339	#define PUT_NUM_S16(num) PUT_NUM_SIGN(6, "0%04xh", num, int16_t, uint16_t)
340	#define PUT_NUM_S32(num) PUT_NUM_SIGN(10, "0%08xh", num, int32_t, uint32_t)
341	#define PUT_NUM_S64(num) PUT_NUM_SIGN(18, "0%016RX64h", num, int64_t, uint64_t)
342
343
344	/*
345	* The address?
346	*/
347	if (fFlags & DIS_FMT_FLAGS_ADDR_LEFT)
348	{
349	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
350	if (pCpu->uInstrAddr >= _4G)
351	PUT_NUM(9, "%08x`", (uint32_t)(pCpu->uInstrAddr >> 32));
352	#endif
353	PUT_NUM(8, "%08x", (uint32_t)pCpu->uInstrAddr);
354	PUT_C(' ');
355	}
356
357	/*
358	* The opcode bytes?
359	*/
360	if (fFlags & DIS_FMT_FLAGS_BYTES_LEFT)
361	{
362	size_t cchTmp = disFormatBytes(pCpu, pszDst, cchDst, fFlags);
363	cchOutput += cchTmp;
364	if (cchDst > 1)
365	{
366	if (cchTmp <= cchDst)
367	{
368	cchDst -= cchTmp;
369	pszDst += cchTmp;
370	}
371	else
372	{
373	pszDst += cchDst - 1;
374	cchDst = 1;
375	}
376	}
377
378	/* Some padding to align the instruction. */
379	size_t cchPadding = (7 * (2 + !!(fFlags & DIS_FMT_FLAGS_BYTES_SPACED)))
380	+ !!(fFlags & DIS_FMT_FLAGS_BYTES_BRACKETS) * 2
381	+ 2;
382	cchPadding = cchTmp + 1 >= cchPadding ? 1 : cchPadding - cchTmp;
383	PUT_STR(g_szSpaces, cchPadding);
384	}
385
386
387	/*
388	* Filter out invalid opcodes first as they need special
389	* treatment. UD2 is an exception and should be handled normally.
390	*/
391	size_t const offInstruction = cchOutput;
392	if ( pOp->uOpcode == OP_INVALID
393	\|\| ( pOp->uOpcode == OP_ILLUD2
394	&& (pCpu->fPrefix & DISPREFIX_LOCK)))
395	PUT_SZ("Illegal opcode");
396	//cchOutput += RTStrPrintf(pszDst, cchDst, "Illegal opcode %.*Rhxs", pCpu->cbInstr, pCpu->abInstr);
397	else
398	{
399	/*
400	* Prefixes
401	*/
402	if (pCpu->fPrefix & DISPREFIX_LOCK)
403	PUT_SZ("lock ");
404	if(pCpu->fPrefix & DISPREFIX_REP)
405	PUT_SZ("rep ");
406	else if(pCpu->fPrefix & DISPREFIX_REPNE)
407	PUT_SZ("repne ");
408
409	/*
410	* Adjust the format string to the correct mnemonic
411	* or to avoid things the assembler cannot handle correctly.
412	*/
413	char szTmpFmt[48];
414	const char *pszFmt = pOp->pszOpcode;
415	switch (pOp->uOpcode)
416	{
417	case OP_JECXZ:
418	pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "jcxz %Jb" : pCpu->uOpMode == DISCPUMODE_32BIT ? "jecxz %Jb" : "jrcxz %Jb";
419	break;
420	case OP_PUSHF:
421	pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "pushfw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "pushfd" : "pushfq";
422	break;
423	case OP_POPF:
424	pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "popfw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "popfd" : "popfq";
425	break;
426	case OP_PUSHA:
427	pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "pushaw" : "pushad";
428	break;
429	case OP_POPA:
430	pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "popaw" : "popad";
431	break;
432	case OP_INSB:
433	pszFmt = "insb";
434	break;
435	case OP_INSWD:
436	pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "insw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "insd" : "insq";
437	break;
438	case OP_OUTSB:
439	pszFmt = "outsb";
440	break;
441	case OP_OUTSWD:
442	pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "outsw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "outsd" : "outsq";
443	break;
444	case OP_MOVSB:
445	pszFmt = "movsb";
446	break;
447	case OP_MOVSWD:
448	pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "movsw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "movsd" : "movsq";
449	break;
450	case OP_CMPSB:
451	pszFmt = "cmpsb";
452	break;
453	case OP_CMPWD:
454	pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "cmpsw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "cmpsd" : "cmpsq";
455	break;
456	case OP_SCASB:
457	pszFmt = "scasb";
458	break;
459	case OP_SCASWD:
460	pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "scasw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "scasd" : "scasq";
461	break;
462	case OP_LODSB:
463	pszFmt = "lodsb";
464	break;
465	case OP_LODSWD:
466	pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "lodsw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "lodsd" : "lodsq";
467	break;
468	case OP_STOSB:
469	pszFmt = "stosb";
470	break;
471	case OP_STOSWD:
472	pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "stosw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "stosd" : "stosq";
473	break;
474	case OP_CBW:
475	pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "cbw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "cwde" : "cdqe";
476	break;
477	case OP_CWD:
478	pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "cwd" : pCpu->uOpMode == DISCPUMODE_32BIT ? "cdq" : "cqo";
479	break;
480	case OP_SHL:
481	Assert(pszFmt[3] == '/');
482	pszFmt += 4;
483	break;
484	case OP_XLAT:
485	pszFmt = "xlatb";
486	break;
487	case OP_INT3:
488	pszFmt = "int3";
489	break;
490
491	/*
492	* Don't know how to tell yasm to generate complicated nop stuff, so 'db' it.
493	*/
494	case OP_NOP:
495	if (pCpu->bOpCode == 0x90)
496	/* fine, fine */;
497	else if (pszFmt[sizeof("nop %Ev") - 1] == '/' && pszFmt[sizeof("nop %Ev")] == 'p')
498	pszFmt = "prefetch %Eb";
499	else if (pCpu->bOpCode == 0x1f)
500	{
501	Assert(pCpu->cbInstr >= 3);
502	PUT_SZ("db 00fh, 01fh,");
503	PUT_NUM_8(pCpu->ModRM.u);
504	for (unsigned i = 3; i < pCpu->cbInstr; i++)
505	{
506	PUT_C(',');
507	PUT_NUM_8(0x90); ///@todo fixme.
508	}
509	pszFmt = "";
510	}
511	break;
512
513	default:
514	/* ST(X) -> stX (floating point) */
515	if (*pszFmt == 'f' && strchr(pszFmt, '('))
516	{
517	char *pszFmtDst = szTmpFmt;
518	char ch;
519	do
520	{
521	ch = *pszFmt++;
522	if (ch == 'S' && pszFmt[0] == 'T' && pszFmt[1] == '(')
523	{
524	*pszFmtDst++ = 's';
525	*pszFmtDst++ = 't';
526	pszFmt += 2;
527	ch = *pszFmt;
528	Assert(pszFmt[1] == ')');
529	pszFmt += 2;
530	*pszFmtDst++ = ch;
531	}
532	else
533	*pszFmtDst++ = ch;
534	} while (ch != '\0');
535	pszFmt = szTmpFmt;
536	}
537	break;
538
539	/*
540	* Horrible hacks.
541	*/
542	case OP_FLD:
543	if (pCpu->bOpCode == 0xdb) /* m80fp workaround. */
544	(int )&pCpu->Param1.fParam &= ~0x1f; /* make it pure OP_PARM_M */
545	break;
546	case OP_LAR: /* hack w -> v, probably not correct. */
547	(int )&pCpu->Param2.fParam &= ~0x1f;
548	(int )&pCpu->Param2.fParam \|= OP_PARM_v;
549	break;
550	}
551
552	/*
553	* Formatting context and associated macros.
554	*/
555	PCDISOPPARAM pParam = &pCpu->Param1;
556	int iParam = 1;
557
558	#define PUT_FAR() \
559	do { \
560	if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_p \
561	&& pOp->uOpcode != OP_LDS /* table bugs? */ \
562	&& pOp->uOpcode != OP_LES \
563	&& pOp->uOpcode != OP_LFS \
564	&& pOp->uOpcode != OP_LGS \
565	&& pOp->uOpcode != OP_LSS ) \
566	PUT_SZ("far "); \
567	} while (0)
568	/** @todo mov ah,ch ends up with a byte 'override'... - check if this wasn't fixed. */
569	/** @todo drop the work/dword/qword override when the src/dst is a register (except for movsx/movzx). */
570	#define PUT_SIZE_OVERRIDE() \
571	do { \
572	switch (OP_PARM_VSUBTYPE(pParam->fParam)) \
573	{ \
574	case OP_PARM_v: \
575	switch (pCpu->uOpMode) \
576	{ \
577	case DISCPUMODE_16BIT: PUT_SZ("word "); break; \
578	case DISCPUMODE_32BIT: PUT_SZ("dword "); break; \
579	case DISCPUMODE_64BIT: PUT_SZ("qword "); break; \
580	default: break; \
581	} \
582	break; \
583	case OP_PARM_b: PUT_SZ("byte "); break; \
584	case OP_PARM_w: PUT_SZ("word "); break; \
585	case OP_PARM_d: PUT_SZ("dword "); break; \
586	case OP_PARM_q: PUT_SZ("qword "); break; \
587	case OP_PARM_dq: \
588	if (OP_PARM_VTYPE(pParam->fParam) != OP_PARM_W) /* these are 128 bit, pray they are all unambiguous.. */ \
589	PUT_SZ("qword "); \
590	break; \
591	case OP_PARM_p: break; /* see PUT_FAR */ \
592	case OP_PARM_s: if (pParam->fUse & DISUSE_REG_FP) PUT_SZ("tword "); break; /* ?? */ \
593	case OP_PARM_z: break; \
594	case OP_PARM_NONE: \
595	if ( OP_PARM_VTYPE(pParam->fParam) == OP_PARM_M \
596	&& ((pParam->fUse & DISUSE_REG_FP) \|\| pOp->uOpcode == OP_FLD)) \
597	PUT_SZ("tword "); \
598	break; \
599	default: break; /no pointer type specified/necessary/ \
600	} \
601	} while (0)
602	static const char s_szSegPrefix[6][4] = { "es:", "cs:", "ss:", "ds:", "fs:", "gs:" };
603	#define PUT_SEGMENT_OVERRIDE() \
604	do { \
605	if (pCpu->fPrefix & DISPREFIX_SEG) \
606	PUT_STR(s_szSegPrefix[pCpu->idxSegPrefix], 3); \
607	} while (0)
608
609
610	/*
611	* Segment prefixing for instructions that doesn't do memory access.
612	*/
613	if ( (pCpu->fPrefix & DISPREFIX_SEG)
614	&& !DISUSE_IS_EFFECTIVE_ADDR(pCpu->Param1.fUse)
615	&& !DISUSE_IS_EFFECTIVE_ADDR(pCpu->Param2.fUse)
616	&& !DISUSE_IS_EFFECTIVE_ADDR(pCpu->Param3.fUse))
617	{
618	PUT_STR(s_szSegPrefix[pCpu->idxSegPrefix], 2);
619	PUT_C(' ');
620	}
621
622
623	/*
624	* The formatting loop.
625	*/
626	RTINTPTR off;
627	char szSymbol[128];
628	char ch;
629	while ((ch = *pszFmt++) != '\0')
630	{
631	if (ch == '%')
632	{
633	ch = *pszFmt++;
634	switch (ch)
635	{
636	/*
637	* ModRM - Register only.
638	*/
639	case 'C': /* Control register (ParseModRM / UseModRM). */
640	case 'D': /* Debug register (ParseModRM / UseModRM). */
641	case 'G': /* ModRM selects general register (ParseModRM / UseModRM). */
642	case 'S': /* ModRM byte selects a segment register (ParseModRM / UseModRM). */
643	case 'T': /* ModRM byte selects a test register (ParseModRM / UseModRM). */
644	case 'V': /* ModRM byte selects an XMM/SSE register (ParseModRM / UseModRM). */
645	case 'P': /* ModRM byte selects MMX register (ParseModRM / UseModRM). */
646	{
647	pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
648	Assert(!(pParam->fUse & (DISUSE_INDEX \| DISUSE_SCALE) /* No SIB here... */));
649	Assert(!(pParam->fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32)));
650
651	size_t cchReg;
652	const char *pszReg = disasmFormatYasmBaseReg(pCpu, pParam, &cchReg);
653	PUT_STR(pszReg, cchReg);
654	break;
655	}
656
657	/*
658	* ModRM - Register or memory.
659	*/
660	case 'E': /* ModRM specifies parameter (ParseModRM / UseModRM / UseSIB). */
661	case 'Q': /* ModRM byte selects MMX register or memory address (ParseModRM / UseModRM). */
662	case 'R': /* ModRM byte may only refer to a general register (ParseModRM / UseModRM). */
663	case 'W': /* ModRM byte selects an XMM/SSE register or a memory address (ParseModRM / UseModRM). */
664	case 'M': /* ModRM may only refer to memory (ParseModRM / UseModRM). */
665	{
666	pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
667
668	PUT_FAR();
669	uint32_t const fUse = pParam->fUse;
670	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
671	{
672	/* Work around mov seg,[mem16] and mov [mem16],seg as these always make a 16-bit mem
673	while the register variants deals with 16, 32 & 64 in the normal fashion. */
674	if ( pParam->fParam != OP_PARM_Ev
675	\|\| pOp->uOpcode != OP_MOV
676	\|\| ( pOp->fParam1 != OP_PARM_Sw
677	&& pOp->fParam2 != OP_PARM_Sw))
678	PUT_SIZE_OVERRIDE();
679	PUT_C('[');
680	}
681	if ( (fFlags & DIS_FMT_FLAGS_STRICT)
682	&& (fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32)))
683	{
684	if ( (fUse & DISUSE_DISPLACEMENT8)
685	&& !pParam->uDisp.i8)
686	PUT_SZ("byte ");
687	else if ( (fUse & DISUSE_DISPLACEMENT16)
688	&& (int8_t)pParam->uDisp.i16 == (int16_t)pParam->uDisp.i16)
689	PUT_SZ("word ");
690	else if ( (fUse & DISUSE_DISPLACEMENT32)
691	&& (int16_t)pParam->uDisp.i32 == (int32_t)pParam->uDisp.i32) //??
692	PUT_SZ("dword ");
693	else if ( (fUse & DISUSE_DISPLACEMENT64)
694	&& (pCpu->SIB.Bits.Base != 5 \|\| pCpu->ModRM.Bits.Mod != 0)
695	&& (int32_t)pParam->uDisp.i64 == (int64_t)pParam->uDisp.i64) //??
696	PUT_SZ("qword ");
697	}
698	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
699	PUT_SEGMENT_OVERRIDE();
700
701	bool fBase = (fUse & DISUSE_BASE) /* When exactly is DISUSE_BASE supposed to be set? disasmModRMReg doesn't set it. */
702	\|\| ( (fUse & ( DISUSE_REG_GEN8
703	\| DISUSE_REG_GEN16
704	\| DISUSE_REG_GEN32
705	\| DISUSE_REG_GEN64
706	\| DISUSE_REG_FP
707	\| DISUSE_REG_MMX
708	\| DISUSE_REG_XMM
709	\| DISUSE_REG_CR
710	\| DISUSE_REG_DBG
711	\| DISUSE_REG_SEG
712	\| DISUSE_REG_TEST ))
713	&& !DISUSE_IS_EFFECTIVE_ADDR(fUse));
714	if (fBase)
715	{
716	size_t cchReg;
717	const char *pszReg = disasmFormatYasmBaseReg(pCpu, pParam, &cchReg);
718	PUT_STR(pszReg, cchReg);
719	}
720
721	if (fUse & DISUSE_INDEX)
722	{
723	if (fBase)
724	PUT_C('+');
725
726	size_t cchReg;
727	const char *pszReg = disasmFormatYasmIndexReg(pCpu, pParam, &cchReg);
728	PUT_STR(pszReg, cchReg);
729
730	if (fUse & DISUSE_SCALE)
731	{
732	PUT_C('*');
733	PUT_C('0' + pParam->uScale);
734	}
735	}
736	else
737	Assert(!(fUse & DISUSE_SCALE));
738
739	if (fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32))
740	{
741	int64_t off2;
742	if (fUse & DISUSE_DISPLACEMENT8)
743	off2 = pParam->uDisp.i8;
744	else if (fUse & DISUSE_DISPLACEMENT16)
745	off2 = pParam->uDisp.i16;
746	else if (fUse & (DISUSE_DISPLACEMENT32 \| DISUSE_RIPDISPLACEMENT32))
747	off2 = pParam->uDisp.i32;
748	else if (fUse & DISUSE_DISPLACEMENT64)
749	off2 = pParam->uDisp.i64;
750	else
751	{
752	AssertFailed();
753	off2 = 0;
754	}
755
756	if (fBase \|\| (fUse & DISUSE_INDEX))
757	{
758	PUT_C(off2 >= 0 ? '+' : '-');
759	if (off2 < 0)
760	off2 = -off2;
761	}
762	if (fUse & DISUSE_DISPLACEMENT8)
763	PUT_NUM_8( off2);
764	else if (fUse & DISUSE_DISPLACEMENT16)
765	PUT_NUM_16(off2);
766	else if (fUse & DISUSE_DISPLACEMENT32)
767	PUT_NUM_32(off2);
768	else if (fUse & DISUSE_DISPLACEMENT64)
769	PUT_NUM_64(off2);
770	else
771	{
772	PUT_NUM_32(off2);
773	PUT_SZ(" wrt rip"); //??
774	}
775	}
776
777	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
778	PUT_C(']');
779	break;
780	}
781
782	case 'F': /* Eflags register (0 - popf/pushf only, avoided in adjustments above). */
783	AssertFailed();
784	break;
785
786	case 'I': /* Immediate data (ParseImmByte, ParseImmByteSX, ParseImmV, ParseImmUshort, ParseImmZ). */
787	Assert(pszFmt == 'b' \|\| pszFmt == 'v' \|\| pszFmt == 'w' \|\| pszFmt == 'z'); pszFmt++;
788	switch (pParam->fUse & ( DISUSE_IMMEDIATE8 \| DISUSE_IMMEDIATE16 \| DISUSE_IMMEDIATE32 \| DISUSE_IMMEDIATE64
789	\| DISUSE_IMMEDIATE16_SX8 \| DISUSE_IMMEDIATE32_SX8 \| DISUSE_IMMEDIATE64_SX8))
790	{
791	case DISUSE_IMMEDIATE8:
792	if ( (fFlags & DIS_FMT_FLAGS_STRICT)
793	&& ( (pOp->fParam1 >= OP_PARM_REG_GEN8_START && pOp->fParam1 <= OP_PARM_REG_GEN8_END)
794	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN8_START && pOp->fParam2 <= OP_PARM_REG_GEN8_END))
795	)
796	PUT_SZ("strict byte ");
797	PUT_NUM_8(pParam->uValue);
798	break;
799
800	case DISUSE_IMMEDIATE16:
801	if ( pCpu->uCpuMode != pCpu->uOpMode
802	\|\| ( (fFlags & DIS_FMT_FLAGS_STRICT)
803	&& ( (int8_t)pParam->uValue == (int16_t)pParam->uValue
804	\|\| (pOp->fParam1 >= OP_PARM_REG_GEN16_START && pOp->fParam1 <= OP_PARM_REG_GEN16_END)
805	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN16_START && pOp->fParam2 <= OP_PARM_REG_GEN16_END))
806	)
807	)
808	{
809	if (OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_b)
810	PUT_SZ_STRICT("strict byte ", "byte ");
811	else if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_v
812	\|\| OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_z)
813	PUT_SZ_STRICT("strict word ", "word ");
814	}
815	PUT_NUM_16(pParam->uValue);
816	break;
817
818	case DISUSE_IMMEDIATE16_SX8:
819	PUT_SZ_STRICT("strict byte ", "byte ");
820	PUT_NUM_16(pParam->uValue);
821	break;
822
823	case DISUSE_IMMEDIATE32:
824	if ( pCpu->uOpMode != (pCpu->uCpuMode == DISCPUMODE_16BIT ? DISCPUMODE_16BIT : DISCPUMODE_32BIT) /* not perfect */
825	\|\| ( (fFlags & DIS_FMT_FLAGS_STRICT)
826	&& ( (int8_t)pParam->uValue == (int32_t)pParam->uValue
827	\|\| (pOp->fParam1 >= OP_PARM_REG_GEN32_START && pOp->fParam1 <= OP_PARM_REG_GEN32_END)
828	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN32_START && pOp->fParam2 <= OP_PARM_REG_GEN32_END))
829	)
830	)
831	{
832	if (OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_b)
833	PUT_SZ_STRICT("strict byte ", "byte ");
834	else if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_v
835	\|\| OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_z)
836	PUT_SZ_STRICT("strict dword ", "dword ");
837	}
838	PUT_NUM_32(pParam->uValue);
839	break;
840
841	case DISUSE_IMMEDIATE32_SX8:
842	PUT_SZ_STRICT("strict byte ", "byte ");
843	PUT_NUM_32(pParam->uValue);
844	break;
845
846	case DISUSE_IMMEDIATE64_SX8:
847	PUT_SZ_STRICT("strict byte ", "byte ");
848	PUT_NUM_64(pParam->uValue);
849	break;
850
851	case DISUSE_IMMEDIATE64:
852	PUT_NUM_64(pParam->uValue);
853	break;
854
855	default:
856	AssertFailed();
857	break;
858	}
859	break;
860
861	case 'J': /* Relative jump offset (ParseImmBRel + ParseImmVRel). */
862	{
863	int32_t offDisplacement;
864	Assert(iParam == 1);
865	bool fPrefix = (fFlags & DIS_FMT_FLAGS_STRICT)
866	&& pOp->uOpcode != OP_CALL
867	&& pOp->uOpcode != OP_LOOP
868	&& pOp->uOpcode != OP_LOOPE
869	&& pOp->uOpcode != OP_LOOPNE
870	&& pOp->uOpcode != OP_JECXZ;
871	if (pOp->uOpcode == OP_CALL)
872	fFlags &= ~DIS_FMT_FLAGS_RELATIVE_BRANCH;
873
874	if (pParam->fUse & DISUSE_IMMEDIATE8_REL)
875	{
876	if (fPrefix)
877	PUT_SZ("short ");
878	offDisplacement = (int8_t)pParam->uValue;
879	Assert(*pszFmt == 'b'); pszFmt++;
880
881	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
882	PUT_NUM_S8(offDisplacement);
883	}
884	else if (pParam->fUse & DISUSE_IMMEDIATE16_REL)
885	{
886	if (fPrefix)
887	PUT_SZ("near ");
888	offDisplacement = (int16_t)pParam->uValue;
889	Assert(*pszFmt == 'v'); pszFmt++;
890
891	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
892	PUT_NUM_S16(offDisplacement);
893	}
894	else
895	{
896	if (fPrefix)
897	PUT_SZ("near ");
898	offDisplacement = (int32_t)pParam->uValue;
899	Assert(pParam->fUse & (DISUSE_IMMEDIATE32_REL\|DISUSE_IMMEDIATE64_REL));
900	Assert(*pszFmt == 'v'); pszFmt++;
901
902	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
903	PUT_NUM_S32(offDisplacement);
904	}
905	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
906	PUT_SZ(" (");
907
908	RTUINTPTR uTrgAddr = pCpu->uInstrAddr + pCpu->cbInstr + offDisplacement;
909	if (pCpu->uCpuMode == DISCPUMODE_16BIT)
910	PUT_NUM_16(uTrgAddr);
911	else if (pCpu->uCpuMode == DISCPUMODE_32BIT)
912	PUT_NUM_32(uTrgAddr);
913	else
914	PUT_NUM_64(uTrgAddr);
915
916	if (pfnGetSymbol)
917	{
918	int rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, szSymbol, sizeof(szSymbol), &off, pvUser);
919	if (RT_SUCCESS(rc))
920	{
921	PUT_SZ(" [");
922	PUT_PSZ(szSymbol);
923	if (off != 0)
924	{
925	if ((int8_t)off == off)
926	PUT_NUM_S8(off);
927	else if ((int16_t)off == off)
928	PUT_NUM_S16(off);
929	else if ((int32_t)off == off)
930	PUT_NUM_S32(off);
931	else
932	PUT_NUM_S64(off);
933	}
934	PUT_C(']');
935	}
936	}
937
938	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
939	PUT_C(')');
940	break;
941	}
942
943	case 'A': /* Direct (jump/call) address (ParseImmAddr). */
944	{
945	Assert(*pszFmt == 'p'); pszFmt++;
946	PUT_FAR();
947	PUT_SIZE_OVERRIDE();
948	PUT_SEGMENT_OVERRIDE();
949	int rc = VERR_SYMBOL_NOT_FOUND;
950	switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 \| DISUSE_IMMEDIATE_ADDR_16_32 \| DISUSE_DISPLACEMENT64 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT16))
951	{
952	case DISUSE_IMMEDIATE_ADDR_16_16:
953	PUT_NUM_16(pParam->uValue >> 16);
954	PUT_C(':');
955	PUT_NUM_16(pParam->uValue);
956	if (pfnGetSymbol)
957	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
958	break;
959	case DISUSE_IMMEDIATE_ADDR_16_32:
960	PUT_NUM_16(pParam->uValue >> 32);
961	PUT_C(':');
962	PUT_NUM_32(pParam->uValue);
963	if (pfnGetSymbol)
964	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
965	break;
966	case DISUSE_DISPLACEMENT16:
967	PUT_NUM_16(pParam->uValue);
968	if (pfnGetSymbol)
969	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
970	break;
971	case DISUSE_DISPLACEMENT32:
972	PUT_NUM_32(pParam->uValue);
973	if (pfnGetSymbol)
974	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
975	break;
976	case DISUSE_DISPLACEMENT64:
977	PUT_NUM_64(pParam->uValue);
978	if (pfnGetSymbol)
979	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint64_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
980	break;
981	default:
982	AssertFailed();
983	break;
984	}
985
986	if (RT_SUCCESS(rc))
987	{
988	PUT_SZ(" [");
989	PUT_PSZ(szSymbol);
990	if (off != 0)
991	{
992	if ((int8_t)off == off)
993	PUT_NUM_S8(off);
994	else if ((int16_t)off == off)
995	PUT_NUM_S16(off);
996	else if ((int32_t)off == off)
997	PUT_NUM_S32(off);
998	else
999	PUT_NUM_S64(off);
1000	}
1001	PUT_C(']');
1002	}
1003	break;
1004	}
1005
1006	case 'O': /* No ModRM byte (ParseImmAddr). */
1007	{
1008	Assert(pszFmt == 'b' \|\| pszFmt == 'v'); pszFmt++;
1009	PUT_FAR();
1010	PUT_SIZE_OVERRIDE();
1011	PUT_C('[');
1012	PUT_SEGMENT_OVERRIDE();
1013	int rc = VERR_SYMBOL_NOT_FOUND;
1014	switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 \| DISUSE_IMMEDIATE_ADDR_16_32 \| DISUSE_DISPLACEMENT64 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT16))
1015	{
1016	case DISUSE_IMMEDIATE_ADDR_16_16:
1017	PUT_NUM_16(pParam->uValue >> 16);
1018	PUT_C(':');
1019	PUT_NUM_16(pParam->uValue);
1020	if (pfnGetSymbol)
1021	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1022	break;
1023	case DISUSE_IMMEDIATE_ADDR_16_32:
1024	PUT_NUM_16(pParam->uValue >> 32);
1025	PUT_C(':');
1026	PUT_NUM_32(pParam->uValue);
1027	if (pfnGetSymbol)
1028	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1029	break;
1030	case DISUSE_DISPLACEMENT16:
1031	PUT_NUM_16(pParam->uDisp.i16);
1032	if (pfnGetSymbol)
1033	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u16, szSymbol, sizeof(szSymbol), &off, pvUser);
1034	break;
1035	case DISUSE_DISPLACEMENT32:
1036	PUT_NUM_32(pParam->uDisp.i32);
1037	if (pfnGetSymbol)
1038	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u32, szSymbol, sizeof(szSymbol), &off, pvUser);
1039	break;
1040	case DISUSE_DISPLACEMENT64:
1041	PUT_NUM_64(pParam->uDisp.i64);
1042	if (pfnGetSymbol)
1043	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u64, szSymbol, sizeof(szSymbol), &off, pvUser);
1044	break;
1045	default:
1046	AssertFailed();
1047	break;
1048	}
1049	PUT_C(']');
1050
1051	if (RT_SUCCESS(rc))
1052	{
1053	PUT_SZ(" (");
1054	PUT_PSZ(szSymbol);
1055	if (off != 0)
1056	{
1057	if ((int8_t)off == off)
1058	PUT_NUM_S8(off);
1059	else if ((int16_t)off == off)
1060	PUT_NUM_S16(off);
1061	else if ((int32_t)off == off)
1062	PUT_NUM_S32(off);
1063	else
1064	PUT_NUM_S64(off);
1065	}
1066	PUT_C(')');
1067	}
1068	break;
1069	}
1070
1071	case 'X': /* DS:SI (ParseXb, ParseXv). */
1072	case 'Y': /* ES:DI (ParseYb, ParseYv). */
1073	{
1074	Assert(pszFmt == 'b' \|\| pszFmt == 'v'); pszFmt++;
1075	PUT_FAR();
1076	PUT_SIZE_OVERRIDE();
1077	PUT_C('[');
1078	if (pParam->fUse & DISUSE_POINTER_DS_BASED)
1079	PUT_SZ("ds:");
1080	else
1081	PUT_SZ("es:");
1082
1083	size_t cchReg;
1084	const char *pszReg = disasmFormatYasmBaseReg(pCpu, pParam, &cchReg);
1085	PUT_STR(pszReg, cchReg);
1086	PUT_C(']');
1087	break;
1088	}
1089
1090	case 'e': /* Register based on operand size (e.g. %eAX) (ParseFixedReg). */
1091	{
1092	Assert(RT_C_IS_ALPHA(pszFmt[0]) && RT_C_IS_ALPHA(pszFmt[1]) && !RT_C_IS_ALPHA(pszFmt[2])); pszFmt += 2;
1093	size_t cchReg;
1094	const char *pszReg = disasmFormatYasmBaseReg(pCpu, pParam, &cchReg);
1095	PUT_STR(pszReg, cchReg);
1096	break;
1097	}
1098
1099	default:
1100	AssertMsgFailed(("%c%s!\n", ch, pszFmt));
1101	break;
1102	}
1103	AssertMsg(pszFmt == ',' \|\| pszFmt == '\0', ("%c%s\n", ch, pszFmt));
1104	}
1105	else
1106	{
1107	PUT_C(ch);
1108	if (ch == ',')
1109	{
1110	Assert(*pszFmt != ' ');
1111	PUT_C(' ');
1112	switch (++iParam)
1113	{
1114	case 2: pParam = &pCpu->Param2; break;
1115	case 3: pParam = &pCpu->Param3; break;
1116	default: pParam = NULL; break;
1117	}
1118	}
1119	}
1120	} /* while more to format */
1121	}
1122
1123	/*
1124	* Any additional output to the right of the instruction?
1125	*/
1126	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
1127	{
1128	/* some up front padding. */
1129	size_t cchPadding = cchOutput - offInstruction;
1130	cchPadding = cchPadding + 1 >= 42 ? 1 : 42 - cchPadding;
1131	PUT_STR(g_szSpaces, cchPadding);
1132
1133	/* comment? */
1134	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
1135	PUT_SZ(";");
1136
1137	/*
1138	* The address?
1139	*/
1140	if (fFlags & DIS_FMT_FLAGS_ADDR_RIGHT)
1141	{
1142	PUT_C(' ');
1143	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
1144	if (pCpu->uInstrAddr >= _4G)
1145	PUT_NUM(9, "%08x`", (uint32_t)(pCpu->uInstrAddr >> 32));
1146	#endif
1147	PUT_NUM(8, "%08x", (uint32_t)pCpu->uInstrAddr);
1148	}
1149
1150	/*
1151	* Opcode bytes?
1152	*/
1153	if (fFlags & DIS_FMT_FLAGS_BYTES_RIGHT)
1154	{
1155	PUT_C(' ');
1156	size_t cchTmp = disFormatBytes(pCpu, pszDst, cchDst, fFlags);
1157	cchOutput += cchTmp;
1158	if (cchTmp >= cchDst)
1159	cchTmp = cchDst - (cchDst != 0);
1160	cchDst -= cchTmp;
1161	pszDst += cchTmp;
1162	}
1163	}
1164
1165	/*
1166	* Terminate it - on overflow we'll have reserved one byte for this.
1167	*/
1168	if (cchDst > 0)
1169	*pszDst = '\0';
1170	else
1171	Assert(!cchBuf);
1172
1173	/* clean up macros */
1174	#undef PUT_PSZ
1175	#undef PUT_SZ
1176	#undef PUT_STR
1177	#undef PUT_C
1178	return cchOutput;
1179	}
1180
1181
1182	/**
1183	* Formats the current instruction in Yasm (/ Nasm) style.
1184	*
1185	* This is a simplified version of DISFormatYasmEx() provided for your convenience.
1186	*
1187	*
1188	* @returns The number of output characters. If this is >= cchBuf, then the content
1189	* of pszBuf will be truncated.
1190	* @param pCpu Pointer to the disassembler CPU state.
1191	* @param pszBuf The output buffer.
1192	* @param cchBuf The size of the output buffer.
1193	*/
1194	DISDECL(size_t) DISFormatYasm(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf)
1195	{
1196	return DISFormatYasmEx(pCpu, pszBuf, cchBuf, 0 /* fFlags /, NULL / pfnGetSymbol /, NULL / pvUser */);
1197	}
1198
1199
1200	/**
1201	* Checks if the encoding of the given disassembled instruction is something we
1202	* can never get YASM to produce.
1203	*
1204	* @returns true if it's odd, false if it isn't.
1205	* @param pCpu The disassembler output. The byte fetcher callback will
1206	* be used if present as we might need to fetch opcode
1207	* bytes.
1208	*/
1209	DISDECL(bool) DISFormatYasmIsOddEncoding(PDISCPUSTATE pCpu)
1210	{
1211	/*
1212	* Mod rm + SIB: Check for duplicate EBP encodings that yasm won't use for very good reasons.
1213	*/
1214	if ( pCpu->uAddrMode != DISCPUMODE_16BIT ///@todo correct?
1215	&& pCpu->ModRM.Bits.Rm == 4
1216	&& pCpu->ModRM.Bits.Mod != 3)
1217	{
1218	/* No scaled index SIB (index=4), except for ESP. */
1219	if ( pCpu->SIB.Bits.Index == 4
1220	&& pCpu->SIB.Bits.Base != 4)
1221	return true;
1222
1223	/* EBP + displacement */
1224	if ( pCpu->ModRM.Bits.Mod != 0
1225	&& pCpu->SIB.Bits.Base == 5
1226	&& pCpu->SIB.Bits.Scale == 0)
1227	return true;
1228	}
1229
1230	/*
1231	* Seems to be an instruction alias here, but I cannot find any docs on it... hrmpf!
1232	*/
1233	if ( pCpu->pCurInstr->uOpcode == OP_SHL
1234	&& pCpu->ModRM.Bits.Reg == 6)
1235	return true;
1236
1237	/*
1238	* Check for multiple prefixes of the same kind.
1239	*/
1240	uint32_t fPrefixes = 0;
1241	for (uint32_t offOpcode = 0; offOpcode < RT_ELEMENTS(pCpu->abInstr); offOpcode++)
1242	{
1243	uint32_t f;
1244	switch (pCpu->abInstr[offOpcode])
1245	{
1246	case 0xf0:
1247	f = DISPREFIX_LOCK;
1248	break;
1249
1250	case 0xf2:
1251	case 0xf3:
1252	f = DISPREFIX_REP; /* yes, both */
1253	break;
1254
1255	case 0x2e:
1256	case 0x3e:
1257	case 0x26:
1258	case 0x36:
1259	case 0x64:
1260	case 0x65:
1261	f = DISPREFIX_SEG;
1262	break;
1263
1264	case 0x66:
1265	f = DISPREFIX_OPSIZE;
1266	break;
1267
1268	case 0x67:
1269	f = DISPREFIX_ADDRSIZE;
1270	break;
1271
1272	case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
1273	case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
1274	f = pCpu->uCpuMode == DISCPUMODE_64BIT ? DISPREFIX_REX : 0;
1275	break;
1276
1277	default:
1278	f = 0;
1279	break;
1280	}
1281	if (!f)
1282	break; /* done */
1283	if (fPrefixes & f)
1284	return true;
1285	fPrefixes \|= f;
1286	}
1287
1288	/* segment overrides are fun */
1289	if (fPrefixes & DISPREFIX_SEG)
1290	{
1291	/* no effective address which it may apply to. */
1292	Assert((pCpu->fPrefix & DISPREFIX_SEG) \|\| pCpu->uCpuMode == DISCPUMODE_64BIT);
1293	if ( !DISUSE_IS_EFFECTIVE_ADDR(pCpu->Param1.fUse)
1294	&& !DISUSE_IS_EFFECTIVE_ADDR(pCpu->Param2.fUse)
1295	&& !DISUSE_IS_EFFECTIVE_ADDR(pCpu->Param3.fUse))
1296	return true;
1297	}
1298
1299	/* fixed register + addr override doesn't go down all that well. */
1300	if (fPrefixes & DISPREFIX_ADDRSIZE)
1301	{
1302	Assert(pCpu->fPrefix & DISPREFIX_ADDRSIZE);
1303	if ( pCpu->pCurInstr->fParam3 == OP_PARM_NONE
1304	&& pCpu->pCurInstr->fParam2 == OP_PARM_NONE
1305	&& ( pCpu->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
1306	&& pCpu->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END))
1307	return true;
1308	}
1309
1310	/* Almost all prefixes are bad. */
1311	if (fPrefixes)
1312	{
1313	switch (pCpu->pCurInstr->uOpcode)
1314	{
1315	/* nop w/ prefix(es). */
1316	case OP_NOP:
1317	return true;
1318
1319	case OP_JMP:
1320	if ( pCpu->pCurInstr->fParam1 != OP_PARM_Jb
1321	&& pCpu->pCurInstr->fParam1 != OP_PARM_Jv)
1322	break;
1323	/* fall thru */
1324	case OP_JO:
1325	case OP_JNO:
1326	case OP_JC:
1327	case OP_JNC:
1328	case OP_JE:
1329	case OP_JNE:
1330	case OP_JBE:
1331	case OP_JNBE:
1332	case OP_JS:
1333	case OP_JNS:
1334	case OP_JP:
1335	case OP_JNP:
1336	case OP_JL:
1337	case OP_JNL:
1338	case OP_JLE:
1339	case OP_JNLE:
1340	/** @todo branch hinting 0x2e/0x3e... */
1341	return true;
1342	}
1343
1344	}
1345
1346	/* All but the segment prefix is bad news. */
1347	if (fPrefixes & ~DISPREFIX_SEG)
1348	{
1349	switch (pCpu->pCurInstr->uOpcode)
1350	{
1351	case OP_POP:
1352	case OP_PUSH:
1353	if ( pCpu->pCurInstr->fParam1 >= OP_PARM_REG_SEG_START
1354	&& pCpu->pCurInstr->fParam1 <= OP_PARM_REG_SEG_END)
1355	return true;
1356	if ( (fPrefixes & ~DISPREFIX_OPSIZE)
1357	&& pCpu->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
1358	&& pCpu->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END)
1359	return true;
1360	break;
1361
1362	case OP_POPA:
1363	case OP_POPF:
1364	case OP_PUSHA:
1365	case OP_PUSHF:
1366	if (fPrefixes & ~DISPREFIX_OPSIZE)
1367	return true;
1368	break;
1369	}
1370	}
1371
1372	/* Implicit 8-bit register instructions doesn't mix with operand size. */
1373	if ( (fPrefixes & DISPREFIX_OPSIZE)
1374	&& ( ( pCpu->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
1375	&& pCpu->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
1376	\|\| ( pCpu->pCurInstr->fParam2 == OP_PARM_Gb /* r8 */
1377	&& pCpu->pCurInstr->fParam1 == OP_PARM_Eb /* r8/mem8 */))
1378	)
1379	{
1380	switch (pCpu->pCurInstr->uOpcode)
1381	{
1382	case OP_ADD:
1383	case OP_OR:
1384	case OP_ADC:
1385	case OP_SBB:
1386	case OP_AND:
1387	case OP_SUB:
1388	case OP_XOR:
1389	case OP_CMP:
1390	return true;
1391	default:
1392	break;
1393	}
1394	}
1395
1396
1397	/*
1398	* Check for the version of xyz reg,reg instruction that the assembler doesn't use.
1399	*
1400	* For example:
1401	* expected: 1aee sbb ch, dh ; SBB r8, r/m8
1402	* yasm: 18F5 sbb ch, dh ; SBB r/m8, r8
1403	*/
1404	if (pCpu->ModRM.Bits.Mod == 3 /* reg,reg */)
1405	{
1406	switch (pCpu->pCurInstr->uOpcode)
1407	{
1408	case OP_ADD:
1409	case OP_OR:
1410	case OP_ADC:
1411	case OP_SBB:
1412	case OP_AND:
1413	case OP_SUB:
1414	case OP_XOR:
1415	case OP_CMP:
1416	if ( ( pCpu->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
1417	&& pCpu->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
1418	\|\| ( pCpu->pCurInstr->fParam1 == OP_PARM_Gv /* rX */
1419	&& pCpu->pCurInstr->fParam2 == OP_PARM_Ev /* rX/memX */))
1420	return true;
1421
1422	/* 82 (see table A-6). */
1423	if (pCpu->bOpCode == 0x82)
1424	return true;
1425	break;
1426
1427	/* ff /0, fe /0, ff /1, fe /0 */
1428	case OP_DEC:
1429	case OP_INC:
1430	return true;
1431
1432	case OP_POP:
1433	case OP_PUSH:
1434	Assert(pCpu->bOpCode == 0x8f);
1435	return true;
1436
1437	case OP_MOV:
1438	if ( pCpu->bOpCode == 0x8a
1439	\|\| pCpu->bOpCode == 0x8b)
1440	return true;
1441	break;
1442
1443	default:
1444	break;
1445	}
1446	}
1447
1448	/* shl eax,1 will be assembled to the form without the immediate byte. */
1449	if ( pCpu->pCurInstr->fParam2 == OP_PARM_Ib
1450	&& (uint8_t)pCpu->Param2.uValue == 1)
1451	{
1452	switch (pCpu->pCurInstr->uOpcode)
1453	{
1454	case OP_SHL:
1455	case OP_SHR:
1456	case OP_SAR:
1457	case OP_RCL:
1458	case OP_RCR:
1459	case OP_ROL:
1460	case OP_ROR:
1461	return true;
1462	}
1463	}
1464
1465	/* And some more - see table A-6. */
1466	if (pCpu->bOpCode == 0x82)
1467	{
1468	switch (pCpu->pCurInstr->uOpcode)
1469	{
1470	case OP_ADD:
1471	case OP_OR:
1472	case OP_ADC:
1473	case OP_SBB:
1474	case OP_AND:
1475	case OP_SUB:
1476	case OP_XOR:
1477	case OP_CMP:
1478	return true;
1479	break;
1480	}
1481	}
1482
1483
1484	/* check for REX.X = 1 without SIB. */
1485
1486	/* Yasm encodes setnbe al with /2 instead of /0 like the AMD manual
1487	says (intel doesn't appear to care). */
1488	switch (pCpu->pCurInstr->uOpcode)
1489	{
1490	case OP_SETO:
1491	case OP_SETNO:
1492	case OP_SETC:
1493	case OP_SETNC:
1494	case OP_SETE:
1495	case OP_SETNE:
1496	case OP_SETBE:
1497	case OP_SETNBE:
1498	case OP_SETS:
1499	case OP_SETNS:
1500	case OP_SETP:
1501	case OP_SETNP:
1502	case OP_SETL:
1503	case OP_SETNL:
1504	case OP_SETLE:
1505	case OP_SETNLE:
1506	AssertMsg(pCpu->bOpCode >= 0x90 && pCpu->bOpCode <= 0x9f, ("%#x\n", pCpu->bOpCode));
1507	if (pCpu->ModRM.Bits.Reg != 2)
1508	return true;
1509	break;
1510	}
1511
1512	/*
1513	* The MOVZX reg32,mem16 instruction without an operand size prefix
1514	* doesn't quite make sense...
1515	*/
1516	if ( pCpu->pCurInstr->uOpcode == OP_MOVZX
1517	&& pCpu->bOpCode == 0xB7
1518	&& (pCpu->uCpuMode == DISCPUMODE_16BIT) != !!(fPrefixes & DISPREFIX_OPSIZE))
1519	return true;
1520
1521	return false;
1522	}
1523

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source: vbox/trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp@ 41761

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