DisasmFormatYasm.cpp@ 49905

Last change on this file since 49905 was 48948, checked in by vboxsync, 11 years ago
Disassembler: Whitespace and svn:keyword cleanups by scm.
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1	/* $Id: DisasmFormatYasm.cpp 48948 2013-10-07 21:41:26Z vboxsync $ */
2	/** @file
3	* VBox Disassembler - Yasm(/Nasm) Style Formatter.
4	*/
5
6	/*
7	* Copyright (C) 2008-2012 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#include <VBox/dis.h>
23	#include "DisasmInternal.h"
24	#include <iprt/string.h>
25	#include <iprt/assert.h>
26	#include <iprt/ctype.h>
27
28
29	/*******************************************************************************
30	* Global Variables *
31	*******************************************************************************/
32	static const char g_szSpaces[] =
33	" ";
34	static const char g_aszYasmRegGen8[20][5] =
35	{
36	"al\0\0", "cl\0\0", "dl\0\0", "bl\0\0", "ah\0\0", "ch\0\0", "dh\0\0", "bh\0\0", "r8b\0", "r9b\0", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b", "spl\0", "bpl\0", "sil\0", "dil\0"
37	};
38	static const char g_aszYasmRegGen16[16][5] =
39	{
40	"ax\0\0", "cx\0\0", "dx\0\0", "bx\0\0", "sp\0\0", "bp\0\0", "si\0\0", "di\0\0", "r8w\0", "r9w\0", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
41	};
42	static const char g_aszYasmRegGen1616[8][6] =
43	{
44	"bx+si", "bx+di", "bp+si", "bp+di", "si\0\0\0", "di\0\0\0", "bp\0\0\0", "bx\0\0\0"
45	};
46	static const char g_aszYasmRegGen32[16][5] =
47	{
48	"eax\0", "ecx\0", "edx\0", "ebx\0", "esp\0", "ebp\0", "esi\0", "edi\0", "r8d\0", "r9d\0", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
49	};
50	static const char g_aszYasmRegGen64[16][4] =
51	{
52	"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", "r8\0", "r9\0", "r10", "r11", "r12", "r13", "r14", "r15"
53	};
54	static const char g_aszYasmRegSeg[6][3] =
55	{
56	"es", "cs", "ss", "ds", "fs", "gs"
57	};
58	static const char g_aszYasmRegFP[8][4] =
59	{
60	"st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7"
61	};
62	static const char g_aszYasmRegMMX[8][4] =
63	{
64	"mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7"
65	};
66	static const char g_aszYasmRegXMM[16][6] =
67	{
68	"xmm0\0", "xmm1\0", "xmm2\0", "xmm3\0", "xmm4\0", "xmm5\0", "xmm6\0", "xmm7\0", "xmm8\0", "xmm9\0", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
69	};
70	static const char g_aszYasmRegCRx[16][5] =
71	{
72	"cr0\0", "cr1\0", "cr2\0", "cr3\0", "cr4\0", "cr5\0", "cr6\0", "cr7\0", "cr8\0", "cr9\0", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15"
73	};
74	static const char g_aszYasmRegDRx[16][5] =
75	{
76	"dr0\0", "dr1\0", "dr2\0", "dr3\0", "dr4\0", "dr5\0", "dr6\0", "dr7\0", "dr8\0", "dr9\0", "dr10", "dr11", "dr12", "dr13", "dr14", "dr15"
77	};
78	static const char g_aszYasmRegTRx[16][5] =
79	{
80	"tr0\0", "tr1\0", "tr2\0", "tr3\0", "tr4\0", "tr5\0", "tr6\0", "tr7\0", "tr8\0", "tr9\0", "tr10", "tr11", "tr12", "tr13", "tr14", "tr15"
81	};
82
83
84
85	/**
86	* Gets the base register name for the given parameter.
87	*
88	* @returns Pointer to the register name.
89	* @param pDis The disassembler state.
90	* @param pParam The parameter.
91	* @param pcchReg Where to store the length of the name.
92	*/
93	static const char disasmFormatYasmBaseReg(PCDISSTATE pDis, PCDISOPPARAM pParam, size_t pcchReg)
94	{
95	switch (pParam->fUse & ( DISUSE_REG_GEN8 \| DISUSE_REG_GEN16 \| DISUSE_REG_GEN32 \| DISUSE_REG_GEN64
96	\| DISUSE_REG_FP \| DISUSE_REG_MMX \| DISUSE_REG_XMM \| DISUSE_REG_CR
97	\| DISUSE_REG_DBG \| DISUSE_REG_SEG \| DISUSE_REG_TEST))
98
99	{
100	case DISUSE_REG_GEN8:
101	{
102	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen8));
103	const char *psz = g_aszYasmRegGen8[pParam->Base.idxGenReg];
104	*pcchReg = 2 + !!psz[2] + !!psz[3];
105	return psz;
106	}
107
108	case DISUSE_REG_GEN16:
109	{
110	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
111	const char *psz = g_aszYasmRegGen16[pParam->Base.idxGenReg];
112	*pcchReg = 2 + !!psz[2] + !!psz[3];
113	return psz;
114	}
115
116	case DISUSE_REG_GEN32:
117	{
118	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
119	const char *psz = g_aszYasmRegGen32[pParam->Base.idxGenReg];
120	*pcchReg = 2 + !!psz[2] + !!psz[3];
121	return psz;
122	}
123
124	case DISUSE_REG_GEN64:
125	{
126	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
127	const char *psz = g_aszYasmRegGen64[pParam->Base.idxGenReg];
128	*pcchReg = 2 + !!psz[2] + !!psz[3];
129	return psz;
130	}
131
132	case DISUSE_REG_FP:
133	{
134	Assert(pParam->Base.idxFpuReg < RT_ELEMENTS(g_aszYasmRegFP));
135	const char *psz = g_aszYasmRegFP[pParam->Base.idxFpuReg];
136	*pcchReg = 3;
137	return psz;
138	}
139
140	case DISUSE_REG_MMX:
141	{
142	Assert(pParam->Base.idxMmxReg < RT_ELEMENTS(g_aszYasmRegMMX));
143	const char *psz = g_aszYasmRegMMX[pParam->Base.idxMmxReg];
144	*pcchReg = 3;
145	return psz;
146	}
147
148	case DISUSE_REG_XMM:
149	{
150	Assert(pParam->Base.idxXmmReg < RT_ELEMENTS(g_aszYasmRegXMM));
151	const char *psz = g_aszYasmRegXMM[pParam->Base.idxMmxReg];
152	*pcchReg = 4 + !!psz[4];
153	return psz;
154	}
155
156	case DISUSE_REG_CR:
157	{
158	Assert(pParam->Base.idxCtrlReg < RT_ELEMENTS(g_aszYasmRegCRx));
159	const char *psz = g_aszYasmRegCRx[pParam->Base.idxCtrlReg];
160	*pcchReg = 3;
161	return psz;
162	}
163
164	case DISUSE_REG_DBG:
165	{
166	Assert(pParam->Base.idxDbgReg < RT_ELEMENTS(g_aszYasmRegDRx));
167	const char *psz = g_aszYasmRegDRx[pParam->Base.idxDbgReg];
168	*pcchReg = 3;
169	return psz;
170	}
171
172	case DISUSE_REG_SEG:
173	{
174	Assert(pParam->Base.idxSegReg < RT_ELEMENTS(g_aszYasmRegCRx));
175	const char *psz = g_aszYasmRegSeg[pParam->Base.idxSegReg];
176	*pcchReg = 2;
177	return psz;
178	}
179
180	case DISUSE_REG_TEST:
181	{
182	Assert(pParam->Base.idxTestReg < RT_ELEMENTS(g_aszYasmRegTRx));
183	const char *psz = g_aszYasmRegTRx[pParam->Base.idxTestReg];
184	*pcchReg = 3;
185	return psz;
186	}
187
188	default:
189	AssertMsgFailed(("%#x\n", pParam->fUse));
190	*pcchReg = 3;
191	return "r??";
192	}
193	}
194
195
196	/**
197	* Gets the index register name for the given parameter.
198	*
199	* @returns The index register name.
200	* @param pDis The disassembler state.
201	* @param pParam The parameter.
202	* @param pcchReg Where to store the length of the name.
203	*/
204	static const char disasmFormatYasmIndexReg(PCDISSTATE pDis, PCDISOPPARAM pParam, size_t pcchReg)
205	{
206	switch (pDis->uAddrMode)
207	{
208	case DISCPUMODE_16BIT:
209	{
210	Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
211	const char *psz = g_aszYasmRegGen16[pParam->Index.idxGenReg];
212	*pcchReg = 2 + !!psz[2] + !!psz[3];
213	return psz;
214	}
215
216	case DISCPUMODE_32BIT:
217	{
218	Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
219	const char *psz = g_aszYasmRegGen32[pParam->Index.idxGenReg];
220	*pcchReg = 2 + !!psz[2] + !!psz[3];
221	return psz;
222	}
223
224	case DISCPUMODE_64BIT:
225	{
226	Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
227	const char *psz = g_aszYasmRegGen64[pParam->Index.idxGenReg];
228	*pcchReg = 2 + !!psz[2] + !!psz[3];
229	return psz;
230	}
231
232	default:
233	AssertMsgFailed(("%#x %#x\n", pParam->fUse, pDis->uAddrMode));
234	*pcchReg = 3;
235	return "r??";
236	}
237	}
238
239
240	/**
241	* Formats the current instruction in Yasm (/ Nasm) style.
242	*
243	*
244	* @returns The number of output characters. If this is >= cchBuf, then the content
245	* of pszBuf will be truncated.
246	* @param pDis Pointer to the disassembler state.
247	* @param pszBuf The output buffer.
248	* @param cchBuf The size of the output buffer.
249	* @param fFlags Format flags, see DIS_FORMAT_FLAGS_*.
250	* @param pfnGetSymbol Get symbol name for a jmp or call target address. Optional.
251	* @param pvUser User argument for pfnGetSymbol.
252	*/
253	DISDECL(size_t) DISFormatYasmEx(PCDISSTATE pDis, char *pszBuf, size_t cchBuf, uint32_t fFlags,
254	PFNDISGETSYMBOL pfnGetSymbol, void *pvUser)
255	{
256	/** @todo monitor and mwait aren't formatted correctly in 64-bit mode. */
257	/*
258	* Input validation and massaging.
259	*/
260	AssertPtr(pDis);
261	AssertPtrNull(pszBuf);
262	Assert(pszBuf \|\| !cchBuf);
263	AssertPtrNull(pfnGetSymbol);
264	AssertMsg(DIS_FMT_FLAGS_IS_VALID(fFlags), ("%#x\n", fFlags));
265	if (fFlags & DIS_FMT_FLAGS_ADDR_COMMENT)
266	fFlags = (fFlags & ~DIS_FMT_FLAGS_ADDR_LEFT) \| DIS_FMT_FLAGS_ADDR_RIGHT;
267	if (fFlags & DIS_FMT_FLAGS_BYTES_COMMENT)
268	fFlags = (fFlags & ~DIS_FMT_FLAGS_BYTES_LEFT) \| DIS_FMT_FLAGS_BYTES_RIGHT;
269
270	PCDISOPCODE const pOp = pDis->pCurInstr;
271
272	/*
273	* Output macros
274	*/
275	char *pszDst = pszBuf;
276	size_t cchDst = cchBuf;
277	size_t cchOutput = 0;
278	#define PUT_C(ch) \
279	do { \
280	cchOutput++; \
281	if (cchDst > 1) \
282	{ \
283	cchDst--; \
284	*pszDst++ = (ch); \
285	} \
286	} while (0)
287	#define PUT_STR(pszSrc, cchSrc) \
288	do { \
289	cchOutput += (cchSrc); \
290	if (cchDst > (cchSrc)) \
291	{ \
292	memcpy(pszDst, (pszSrc), (cchSrc)); \
293	pszDst += (cchSrc); \
294	cchDst -= (cchSrc); \
295	} \
296	else if (cchDst > 1) \
297	{ \
298	memcpy(pszDst, (pszSrc), cchDst - 1); \
299	pszDst += cchDst - 1; \
300	cchDst = 1; \
301	} \
302	} while (0)
303	#define PUT_SZ(sz) \
304	PUT_STR((sz), sizeof(sz) - 1)
305	#define PUT_SZ_STRICT(szStrict, szRelaxed) \
306	do { if (fFlags & DIS_FMT_FLAGS_STRICT) PUT_SZ(szStrict); else PUT_SZ(szRelaxed); } while (0)
307	#define PUT_PSZ(psz) \
308	do { const size_t cchTmp = strlen(psz); PUT_STR((psz), cchTmp); } while (0)
309	#define PUT_NUM(cch, fmt, num) \
310	do { \
311	cchOutput += (cch); \
312	if (cchDst > 1) \
313	{ \
314	const size_t cchTmp = RTStrPrintf(pszDst, cchDst, fmt, (num)); \
315	pszDst += cchTmp; \
316	cchDst -= cchTmp; \
317	Assert(cchTmp == (cch) \|\| cchDst == 1); \
318	} \
319	} while (0)
320	/** @todo add two flags for choosing between %X / %x and h / 0x. */
321	#define PUT_NUM_8(num) PUT_NUM(4, "0%02xh", (uint8_t)(num))
322	#define PUT_NUM_16(num) PUT_NUM(6, "0%04xh", (uint16_t)(num))
323	#define PUT_NUM_32(num) PUT_NUM(10, "0%08xh", (uint32_t)(num))
324	#define PUT_NUM_64(num) PUT_NUM(18, "0%016RX64h", (uint64_t)(num))
325
326	#define PUT_NUM_SIGN(cch, fmt, num, stype, utype) \
327	do { \
328	if ((stype)(num) >= 0) \
329	{ \
330	PUT_C('+'); \
331	PUT_NUM(cch, fmt, (utype)(num)); \
332	} \
333	else \
334	{ \
335	PUT_C('-'); \
336	PUT_NUM(cch, fmt, (utype)-(stype)(num)); \
337	} \
338	} while (0)
339	#define PUT_NUM_S8(num) PUT_NUM_SIGN(4, "0%02xh", num, int8_t, uint8_t)
340	#define PUT_NUM_S16(num) PUT_NUM_SIGN(6, "0%04xh", num, int16_t, uint16_t)
341	#define PUT_NUM_S32(num) PUT_NUM_SIGN(10, "0%08xh", num, int32_t, uint32_t)
342	#define PUT_NUM_S64(num) PUT_NUM_SIGN(18, "0%016RX64h", num, int64_t, uint64_t)
343
344	#define PUT_SYMBOL_TWO(a_rcSym, a_szStart, a_chEnd) \
345	do { \
346	if (RT_SUCCESS(a_rcSym)) \
347	{ \
348	PUT_SZ(a_szStart); \
349	PUT_PSZ(szSymbol); \
350	if (off != 0) \
351	{ \
352	if ((int8_t)off == off) \
353	PUT_NUM_S8(off); \
354	else if ((int16_t)off == off) \
355	PUT_NUM_S16(off); \
356	else if ((int32_t)off == off) \
357	PUT_NUM_S32(off); \
358	else \
359	PUT_NUM_S64(off); \
360	} \
361	PUT_C(a_chEnd); \
362	} \
363	} while (0)
364
365	#define PUT_SYMBOL(a_uSeg, a_uAddr, a_szStart, a_chEnd) \
366	do { \
367	if (pfnGetSymbol) \
368	{ \
369	int rcSym = pfnGetSymbol(pDis, a_uSeg, a_uAddr, szSymbol, sizeof(szSymbol), &off, pvUser); \
370	PUT_SYMBOL_TWO(rcSym, a_szStart, a_chEnd); \
371	} \
372	} while (0)
373
374
375	/*
376	* The address?
377	*/
378	if (fFlags & DIS_FMT_FLAGS_ADDR_LEFT)
379	{
380	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
381	if (pDis->uInstrAddr >= _4G)
382	PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
383	#endif
384	PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
385	PUT_C(' ');
386	}
387
388	/*
389	* The opcode bytes?
390	*/
391	if (fFlags & DIS_FMT_FLAGS_BYTES_LEFT)
392	{
393	size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
394	cchOutput += cchTmp;
395	if (cchDst > 1)
396	{
397	if (cchTmp <= cchDst)
398	{
399	cchDst -= cchTmp;
400	pszDst += cchTmp;
401	}
402	else
403	{
404	pszDst += cchDst - 1;
405	cchDst = 1;
406	}
407	}
408
409	/* Some padding to align the instruction. */
410	size_t cchPadding = (7 * (2 + !!(fFlags & DIS_FMT_FLAGS_BYTES_SPACED)))
411	+ !!(fFlags & DIS_FMT_FLAGS_BYTES_BRACKETS) * 2
412	+ 2;
413	cchPadding = cchTmp + 1 >= cchPadding ? 1 : cchPadding - cchTmp;
414	PUT_STR(g_szSpaces, cchPadding);
415	}
416
417
418	/*
419	* Filter out invalid opcodes first as they need special
420	* treatment. UD2 is an exception and should be handled normally.
421	*/
422	size_t const offInstruction = cchOutput;
423	if ( pOp->uOpcode == OP_INVALID
424	\|\| ( pOp->uOpcode == OP_ILLUD2
425	&& (pDis->fPrefix & DISPREFIX_LOCK)))
426	PUT_SZ("Illegal opcode");
427	else
428	{
429	/*
430	* Prefixes
431	*/
432	if (pDis->fPrefix & DISPREFIX_LOCK)
433	PUT_SZ("lock ");
434	if(pDis->fPrefix & DISPREFIX_REP)
435	PUT_SZ("rep ");
436	else if(pDis->fPrefix & DISPREFIX_REPNE)
437	PUT_SZ("repne ");
438
439	/*
440	* Adjust the format string to the correct mnemonic
441	* or to avoid things the assembler cannot handle correctly.
442	*/
443	char szTmpFmt[48];
444	const char *pszFmt = pOp->pszOpcode;
445	switch (pOp->uOpcode)
446	{
447	case OP_JECXZ:
448	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "jcxz %Jb" : pDis->uOpMode == DISCPUMODE_32BIT ? "jecxz %Jb" : "jrcxz %Jb";
449	break;
450	case OP_PUSHF:
451	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "pushfw" : pDis->uOpMode == DISCPUMODE_32BIT ? "pushfd" : "pushfq";
452	break;
453	case OP_POPF:
454	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "popfw" : pDis->uOpMode == DISCPUMODE_32BIT ? "popfd" : "popfq";
455	break;
456	case OP_PUSHA:
457	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "pushaw" : "pushad";
458	break;
459	case OP_POPA:
460	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "popaw" : "popad";
461	break;
462	case OP_INSB:
463	pszFmt = "insb";
464	break;
465	case OP_INSWD:
466	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "insw" : pDis->uOpMode == DISCPUMODE_32BIT ? "insd" : "insq";
467	break;
468	case OP_OUTSB:
469	pszFmt = "outsb";
470	break;
471	case OP_OUTSWD:
472	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "outsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "outsd" : "outsq";
473	break;
474	case OP_MOVSB:
475	pszFmt = "movsb";
476	break;
477	case OP_MOVSWD:
478	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "movsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "movsd" : "movsq";
479	break;
480	case OP_CMPSB:
481	pszFmt = "cmpsb";
482	break;
483	case OP_CMPWD:
484	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cmpsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "cmpsd" : "cmpsq";
485	break;
486	case OP_SCASB:
487	pszFmt = "scasb";
488	break;
489	case OP_SCASWD:
490	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "scasw" : pDis->uOpMode == DISCPUMODE_32BIT ? "scasd" : "scasq";
491	break;
492	case OP_LODSB:
493	pszFmt = "lodsb";
494	break;
495	case OP_LODSWD:
496	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "lodsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "lodsd" : "lodsq";
497	break;
498	case OP_STOSB:
499	pszFmt = "stosb";
500	break;
501	case OP_STOSWD:
502	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "stosw" : pDis->uOpMode == DISCPUMODE_32BIT ? "stosd" : "stosq";
503	break;
504	case OP_CBW:
505	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cbw" : pDis->uOpMode == DISCPUMODE_32BIT ? "cwde" : "cdqe";
506	break;
507	case OP_CWD:
508	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cwd" : pDis->uOpMode == DISCPUMODE_32BIT ? "cdq" : "cqo";
509	break;
510	case OP_SHL:
511	Assert(pszFmt[3] == '/');
512	pszFmt += 4;
513	break;
514	case OP_XLAT:
515	pszFmt = "xlatb";
516	break;
517	case OP_INT3:
518	pszFmt = "int3";
519	break;
520
521	/*
522	* Don't know how to tell yasm to generate complicated nop stuff, so 'db' it.
523	*/
524	case OP_NOP:
525	if (pDis->bOpCode == 0x90)
526	/* fine, fine */;
527	else if (pszFmt[sizeof("nop %Ev") - 1] == '/' && pszFmt[sizeof("nop %Ev")] == 'p')
528	pszFmt = "prefetch %Eb";
529	else if (pDis->bOpCode == 0x1f)
530	{
531	Assert(pDis->cbInstr >= 3);
532	PUT_SZ("db 00fh, 01fh,");
533	PUT_NUM_8(MAKE_MODRM(pDis->ModRM.Bits.Mod, pDis->ModRM.Bits.Reg, pDis->ModRM.Bits.Rm));
534	for (unsigned i = 3; i < pDis->cbInstr; i++)
535	{
536	PUT_C(',');
537	PUT_NUM_8(0x90); ///@todo fixme.
538	}
539	pszFmt = "";
540	}
541	break;
542
543	default:
544	/* ST(X) -> stX (floating point) */
545	if (*pszFmt == 'f' && strchr(pszFmt, '('))
546	{
547	char *pszFmtDst = szTmpFmt;
548	char ch;
549	do
550	{
551	ch = *pszFmt++;
552	if (ch == 'S' && pszFmt[0] == 'T' && pszFmt[1] == '(')
553	{
554	*pszFmtDst++ = 's';
555	*pszFmtDst++ = 't';
556	pszFmt += 2;
557	ch = *pszFmt;
558	Assert(pszFmt[1] == ')');
559	pszFmt += 2;
560	*pszFmtDst++ = ch;
561	}
562	else
563	*pszFmtDst++ = ch;
564	} while (ch != '\0');
565	pszFmt = szTmpFmt;
566	}
567	break;
568
569	/*
570	* Horrible hacks.
571	*/
572	case OP_FLD:
573	if (pDis->bOpCode == 0xdb) /* m80fp workaround. */
574	(int )&pDis->Param1.fParam &= ~0x1f; /* make it pure OP_PARM_M */
575	break;
576	case OP_LAR: /* hack w -> v, probably not correct. */
577	(int )&pDis->Param2.fParam &= ~0x1f;
578	(int )&pDis->Param2.fParam \|= OP_PARM_v;
579	break;
580	}
581
582	/*
583	* Formatting context and associated macros.
584	*/
585	PCDISOPPARAM pParam = &pDis->Param1;
586	int iParam = 1;
587
588	#define PUT_FAR() \
589	do { \
590	if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_p \
591	&& pOp->uOpcode != OP_LDS /* table bugs? */ \
592	&& pOp->uOpcode != OP_LES \
593	&& pOp->uOpcode != OP_LFS \
594	&& pOp->uOpcode != OP_LGS \
595	&& pOp->uOpcode != OP_LSS ) \
596	PUT_SZ("far "); \
597	} while (0)
598	/** @todo mov ah,ch ends up with a byte 'override'... - check if this wasn't fixed. */
599	/** @todo drop the work/dword/qword override when the src/dst is a register (except for movsx/movzx). */
600	#define PUT_SIZE_OVERRIDE() \
601	do { \
602	switch (OP_PARM_VSUBTYPE(pParam->fParam)) \
603	{ \
604	case OP_PARM_v: \
605	switch (pDis->uOpMode) \
606	{ \
607	case DISCPUMODE_16BIT: PUT_SZ("word "); break; \
608	case DISCPUMODE_32BIT: PUT_SZ("dword "); break; \
609	case DISCPUMODE_64BIT: PUT_SZ("qword "); break; \
610	default: break; \
611	} \
612	break; \
613	case OP_PARM_b: PUT_SZ("byte "); break; \
614	case OP_PARM_w: PUT_SZ("word "); break; \
615	case OP_PARM_d: PUT_SZ("dword "); break; \
616	case OP_PARM_q: PUT_SZ("qword "); break; \
617	case OP_PARM_dq: \
618	if (OP_PARM_VTYPE(pParam->fParam) != OP_PARM_W) /* these are 128 bit, pray they are all unambiguous.. */ \
619	PUT_SZ("qword "); \
620	break; \
621	case OP_PARM_p: break; /* see PUT_FAR */ \
622	case OP_PARM_s: if (pParam->fUse & DISUSE_REG_FP) PUT_SZ("tword "); break; /* ?? */ \
623	case OP_PARM_z: break; \
624	case OP_PARM_NONE: \
625	if ( OP_PARM_VTYPE(pParam->fParam) == OP_PARM_M \
626	&& ((pParam->fUse & DISUSE_REG_FP) \|\| pOp->uOpcode == OP_FLD)) \
627	PUT_SZ("tword "); \
628	break; \
629	default: break; /no pointer type specified/necessary/ \
630	} \
631	} while (0)
632	static const char s_szSegPrefix[6][4] = { "es:", "cs:", "ss:", "ds:", "fs:", "gs:" };
633	#define PUT_SEGMENT_OVERRIDE() \
634	do { \
635	if (pDis->fPrefix & DISPREFIX_SEG) \
636	PUT_STR(s_szSegPrefix[pDis->idxSegPrefix], 3); \
637	} while (0)
638
639
640	/*
641	* Segment prefixing for instructions that doesn't do memory access.
642	*/
643	if ( (pDis->fPrefix & DISPREFIX_SEG)
644	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
645	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
646	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse))
647	{
648	PUT_STR(s_szSegPrefix[pDis->idxSegPrefix], 2);
649	PUT_C(' ');
650	}
651
652
653	/*
654	* The formatting loop.
655	*/
656	RTINTPTR off;
657	char szSymbol[128];
658	char ch;
659	while ((ch = *pszFmt++) != '\0')
660	{
661	if (ch == '%')
662	{
663	ch = *pszFmt++;
664	switch (ch)
665	{
666	/*
667	* ModRM - Register only.
668	*/
669	case 'C': /* Control register (ParseModRM / UseModRM). */
670	case 'D': /* Debug register (ParseModRM / UseModRM). */
671	case 'G': /* ModRM selects general register (ParseModRM / UseModRM). */
672	case 'S': /* ModRM byte selects a segment register (ParseModRM / UseModRM). */
673	case 'T': /* ModRM byte selects a test register (ParseModRM / UseModRM). */
674	case 'V': /* ModRM byte selects an XMM/SSE register (ParseModRM / UseModRM). */
675	case 'P': /* ModRM byte selects MMX register (ParseModRM / UseModRM). */
676	{
677	pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
678	Assert(!(pParam->fUse & (DISUSE_INDEX \| DISUSE_SCALE) /* No SIB here... */));
679	Assert(!(pParam->fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32)));
680
681	size_t cchReg;
682	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
683	PUT_STR(pszReg, cchReg);
684	break;
685	}
686
687	/*
688	* ModRM - Register or memory.
689	*/
690	case 'E': /* ModRM specifies parameter (ParseModRM / UseModRM / UseSIB). */
691	case 'Q': /* ModRM byte selects MMX register or memory address (ParseModRM / UseModRM). */
692	case 'R': /* ModRM byte may only refer to a general register (ParseModRM / UseModRM). */
693	case 'W': /* ModRM byte selects an XMM/SSE register or a memory address (ParseModRM / UseModRM). */
694	case 'M': /* ModRM may only refer to memory (ParseModRM / UseModRM). */
695	{
696	pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
697
698	PUT_FAR();
699	uint32_t const fUse = pParam->fUse;
700	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
701	{
702	/* Work around mov seg,[mem16] and mov [mem16],seg as these always make a 16-bit mem
703	while the register variants deals with 16, 32 & 64 in the normal fashion. */
704	if ( pParam->fParam != OP_PARM_Ev
705	\|\| pOp->uOpcode != OP_MOV
706	\|\| ( pOp->fParam1 != OP_PARM_Sw
707	&& pOp->fParam2 != OP_PARM_Sw))
708	PUT_SIZE_OVERRIDE();
709	PUT_C('[');
710	}
711	if ( (fFlags & DIS_FMT_FLAGS_STRICT)
712	&& (fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32)))
713	{
714	if ( (fUse & DISUSE_DISPLACEMENT8)
715	&& !pParam->uDisp.i8)
716	PUT_SZ("byte ");
717	else if ( (fUse & DISUSE_DISPLACEMENT16)
718	&& (int8_t)pParam->uDisp.i16 == (int16_t)pParam->uDisp.i16)
719	PUT_SZ("word ");
720	else if ( (fUse & DISUSE_DISPLACEMENT32)
721	&& (int16_t)pParam->uDisp.i32 == (int32_t)pParam->uDisp.i32) //??
722	PUT_SZ("dword ");
723	else if ( (fUse & DISUSE_DISPLACEMENT64)
724	&& (pDis->SIB.Bits.Base != 5 \|\| pDis->ModRM.Bits.Mod != 0)
725	&& (int32_t)pParam->uDisp.i64 == (int64_t)pParam->uDisp.i64) //??
726	PUT_SZ("qword ");
727	}
728	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
729	PUT_SEGMENT_OVERRIDE();
730
731	bool fBase = (fUse & DISUSE_BASE) /* When exactly is DISUSE_BASE supposed to be set? disasmModRMReg doesn't set it. */
732	\|\| ( (fUse & ( DISUSE_REG_GEN8
733	\| DISUSE_REG_GEN16
734	\| DISUSE_REG_GEN32
735	\| DISUSE_REG_GEN64
736	\| DISUSE_REG_FP
737	\| DISUSE_REG_MMX
738	\| DISUSE_REG_XMM
739	\| DISUSE_REG_CR
740	\| DISUSE_REG_DBG
741	\| DISUSE_REG_SEG
742	\| DISUSE_REG_TEST ))
743	&& !DISUSE_IS_EFFECTIVE_ADDR(fUse));
744	if (fBase)
745	{
746	size_t cchReg;
747	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
748	PUT_STR(pszReg, cchReg);
749	}
750
751	if (fUse & DISUSE_INDEX)
752	{
753	if (fBase)
754	PUT_C('+');
755
756	size_t cchReg;
757	const char *pszReg = disasmFormatYasmIndexReg(pDis, pParam, &cchReg);
758	PUT_STR(pszReg, cchReg);
759
760	if (fUse & DISUSE_SCALE)
761	{
762	PUT_C('*');
763	PUT_C('0' + pParam->uScale);
764	}
765	}
766	else
767	Assert(!(fUse & DISUSE_SCALE));
768
769	int64_t off2 = 0;
770	if (fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32))
771	{
772	if (fUse & DISUSE_DISPLACEMENT8)
773	off2 = pParam->uDisp.i8;
774	else if (fUse & DISUSE_DISPLACEMENT16)
775	off2 = pParam->uDisp.i16;
776	else if (fUse & (DISUSE_DISPLACEMENT32 \| DISUSE_RIPDISPLACEMENT32))
777	off2 = pParam->uDisp.i32;
778	else if (fUse & DISUSE_DISPLACEMENT64)
779	off2 = pParam->uDisp.i64;
780	else
781	{
782	AssertFailed();
783	off2 = 0;
784	}
785
786	if (fBase \|\| (fUse & DISUSE_INDEX))
787	{
788	PUT_C(off2 >= 0 ? '+' : '-');
789	if (off2 < 0)
790	off2 = -off2;
791	}
792	if (fUse & DISUSE_DISPLACEMENT8)
793	PUT_NUM_8( off2);
794	else if (fUse & DISUSE_DISPLACEMENT16)
795	PUT_NUM_16(off2);
796	else if (fUse & DISUSE_DISPLACEMENT32)
797	PUT_NUM_32(off2);
798	else if (fUse & DISUSE_DISPLACEMENT64)
799	PUT_NUM_64(off2);
800	else
801	{
802	PUT_NUM_32(off2);
803	PUT_SZ(" wrt rip"); //??
804	}
805	}
806
807	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
808	{
809	if (pfnGetSymbol && !fBase && !(fUse & DISUSE_INDEX) && off2 != 0)
810	PUT_SYMBOL((pDis->fPrefix & DISPREFIX_SEG)
811	? DIS_FMT_SEL_FROM_REG(pDis->idxSegPrefix)
812	: DIS_FMT_SEL_FROM_REG(DISSELREG_DS),
813	pDis->uAddrMode == DISCPUMODE_64BIT
814	? (uint64_t)off2
815	: pDis->uAddrMode == DISCPUMODE_32BIT
816	? (uint32_t)off2
817	: (uint16_t)off2,
818	" (=", ')');
819	PUT_C(']');
820	}
821	break;
822	}
823
824	case 'F': /* Eflags register (0 - popf/pushf only, avoided in adjustments above). */
825	AssertFailed();
826	break;
827
828	case 'I': /* Immediate data (ParseImmByte, ParseImmByteSX, ParseImmV, ParseImmUshort, ParseImmZ). */
829	Assert(pszFmt == 'b' \|\| pszFmt == 'v' \|\| pszFmt == 'w' \|\| pszFmt == 'z'); pszFmt++;
830	switch (pParam->fUse & ( DISUSE_IMMEDIATE8 \| DISUSE_IMMEDIATE16 \| DISUSE_IMMEDIATE32 \| DISUSE_IMMEDIATE64
831	\| DISUSE_IMMEDIATE16_SX8 \| DISUSE_IMMEDIATE32_SX8 \| DISUSE_IMMEDIATE64_SX8))
832	{
833	case DISUSE_IMMEDIATE8:
834	if ( (fFlags & DIS_FMT_FLAGS_STRICT)
835	&& ( (pOp->fParam1 >= OP_PARM_REG_GEN8_START && pOp->fParam1 <= OP_PARM_REG_GEN8_END)
836	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN8_START && pOp->fParam2 <= OP_PARM_REG_GEN8_END))
837	)
838	PUT_SZ("strict byte ");
839	PUT_NUM_8(pParam->uValue);
840	break;
841
842	case DISUSE_IMMEDIATE16:
843	if ( pDis->uCpuMode != pDis->uOpMode
844	\|\| ( (fFlags & DIS_FMT_FLAGS_STRICT)
845	&& ( (int8_t)pParam->uValue == (int16_t)pParam->uValue
846	\|\| (pOp->fParam1 >= OP_PARM_REG_GEN16_START && pOp->fParam1 <= OP_PARM_REG_GEN16_END)
847	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN16_START && pOp->fParam2 <= OP_PARM_REG_GEN16_END))
848	)
849	)
850	{
851	if (OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_b)
852	PUT_SZ_STRICT("strict byte ", "byte ");
853	else if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_v
854	\|\| OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_z)
855	PUT_SZ_STRICT("strict word ", "word ");
856	}
857	PUT_NUM_16(pParam->uValue);
858	break;
859
860	case DISUSE_IMMEDIATE16_SX8:
861	if ( !(pDis->fPrefix & DISPREFIX_OPSIZE)
862	\|\| pDis->pCurInstr->uOpcode != OP_PUSH)
863	PUT_SZ_STRICT("strict byte ", "byte ");
864	else
865	PUT_SZ("word ");
866	PUT_NUM_16(pParam->uValue);
867	break;
868
869	case DISUSE_IMMEDIATE32:
870	if ( pDis->uOpMode != (pDis->uCpuMode == DISCPUMODE_16BIT ? DISCPUMODE_16BIT : DISCPUMODE_32BIT) /* not perfect */
871	\|\| ( (fFlags & DIS_FMT_FLAGS_STRICT)
872	&& ( (int8_t)pParam->uValue == (int32_t)pParam->uValue
873	\|\| (pOp->fParam1 >= OP_PARM_REG_GEN32_START && pOp->fParam1 <= OP_PARM_REG_GEN32_END)
874	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN32_START && pOp->fParam2 <= OP_PARM_REG_GEN32_END))
875	)
876	)
877	{
878	if (OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_b)
879	PUT_SZ_STRICT("strict byte ", "byte ");
880	else if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_v
881	\|\| OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_z)
882	PUT_SZ_STRICT("strict dword ", "dword ");
883	}
884	PUT_NUM_32(pParam->uValue);
885	if (pDis->uCpuMode == DISCPUMODE_32BIT)
886	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uValue, " (=", ')');
887	break;
888
889	case DISUSE_IMMEDIATE32_SX8:
890	if ( !(pDis->fPrefix & DISPREFIX_OPSIZE)
891	\|\| pDis->pCurInstr->uOpcode != OP_PUSH)
892	PUT_SZ_STRICT("strict byte ", "byte ");
893	else
894	PUT_SZ("dword ");
895	PUT_NUM_32(pParam->uValue);
896	break;
897
898	case DISUSE_IMMEDIATE64_SX8:
899	if ( !(pDis->fPrefix & DISPREFIX_OPSIZE)
900	\|\| pDis->pCurInstr->uOpcode != OP_PUSH)
901	PUT_SZ_STRICT("strict byte ", "byte ");
902	else
903	PUT_SZ("qword ");
904	PUT_NUM_64(pParam->uValue);
905	break;
906
907	case DISUSE_IMMEDIATE64:
908	PUT_NUM_64(pParam->uValue);
909	break;
910
911	default:
912	AssertFailed();
913	break;
914	}
915	break;
916
917	case 'J': /* Relative jump offset (ParseImmBRel + ParseImmVRel). */
918	{
919	int32_t offDisplacement;
920	Assert(iParam == 1);
921	bool fPrefix = (fFlags & DIS_FMT_FLAGS_STRICT)
922	&& pOp->uOpcode != OP_CALL
923	&& pOp->uOpcode != OP_LOOP
924	&& pOp->uOpcode != OP_LOOPE
925	&& pOp->uOpcode != OP_LOOPNE
926	&& pOp->uOpcode != OP_JECXZ;
927	if (pOp->uOpcode == OP_CALL)
928	fFlags &= ~DIS_FMT_FLAGS_RELATIVE_BRANCH;
929
930	if (pParam->fUse & DISUSE_IMMEDIATE8_REL)
931	{
932	if (fPrefix)
933	PUT_SZ("short ");
934	offDisplacement = (int8_t)pParam->uValue;
935	Assert(*pszFmt == 'b'); pszFmt++;
936
937	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
938	PUT_NUM_S8(offDisplacement);
939	}
940	else if (pParam->fUse & DISUSE_IMMEDIATE16_REL)
941	{
942	if (fPrefix)
943	PUT_SZ("near ");
944	offDisplacement = (int16_t)pParam->uValue;
945	Assert(*pszFmt == 'v'); pszFmt++;
946
947	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
948	PUT_NUM_S16(offDisplacement);
949	}
950	else
951	{
952	if (fPrefix)
953	PUT_SZ("near ");
954	offDisplacement = (int32_t)pParam->uValue;
955	Assert(pParam->fUse & (DISUSE_IMMEDIATE32_REL \| DISUSE_IMMEDIATE64_REL));
956	Assert(*pszFmt == 'v'); pszFmt++;
957
958	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
959	PUT_NUM_S32(offDisplacement);
960	}
961	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
962	PUT_SZ(" (");
963
964	RTUINTPTR uTrgAddr = pDis->uInstrAddr + pDis->cbInstr + offDisplacement;
965	if (pDis->uCpuMode == DISCPUMODE_16BIT)
966	PUT_NUM_16(uTrgAddr);
967	else if (pDis->uCpuMode == DISCPUMODE_32BIT)
968	PUT_NUM_32(uTrgAddr);
969	else
970	PUT_NUM_64(uTrgAddr);
971
972	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
973	{
974	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " = ", ' ');
975	PUT_C(')');
976	}
977	else
978	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " (", ')');
979	break;
980	}
981
982	case 'A': /* Direct (jump/call) address (ParseImmAddr). */
983	{
984	Assert(*pszFmt == 'p'); pszFmt++;
985	PUT_FAR();
986	PUT_SIZE_OVERRIDE();
987	PUT_SEGMENT_OVERRIDE();
988	int rc = VERR_SYMBOL_NOT_FOUND;
989	switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 \| DISUSE_IMMEDIATE_ADDR_16_32 \| DISUSE_DISPLACEMENT64 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT16))
990	{
991	case DISUSE_IMMEDIATE_ADDR_16_16:
992	PUT_NUM_16(pParam->uValue >> 16);
993	PUT_C(':');
994	PUT_NUM_16(pParam->uValue);
995	if (pfnGetSymbol)
996	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
997	break;
998	case DISUSE_IMMEDIATE_ADDR_16_32:
999	PUT_NUM_16(pParam->uValue >> 32);
1000	PUT_C(':');
1001	PUT_NUM_32(pParam->uValue);
1002	if (pfnGetSymbol)
1003	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1004	break;
1005	case DISUSE_DISPLACEMENT16:
1006	PUT_NUM_16(pParam->uValue);
1007	if (pfnGetSymbol)
1008	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1009	break;
1010	case DISUSE_DISPLACEMENT32:
1011	PUT_NUM_32(pParam->uValue);
1012	if (pfnGetSymbol)
1013	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1014	break;
1015	case DISUSE_DISPLACEMENT64:
1016	PUT_NUM_64(pParam->uValue);
1017	if (pfnGetSymbol)
1018	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint64_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1019	break;
1020	default:
1021	AssertFailed();
1022	break;
1023	}
1024
1025	PUT_SYMBOL_TWO(rc, " [", ']');
1026	break;
1027	}
1028
1029	case 'O': /* No ModRM byte (ParseImmAddr). */
1030	{
1031	Assert(pszFmt == 'b' \|\| pszFmt == 'v'); pszFmt++;
1032	PUT_FAR();
1033	PUT_SIZE_OVERRIDE();
1034	PUT_C('[');
1035	PUT_SEGMENT_OVERRIDE();
1036	int rc = VERR_SYMBOL_NOT_FOUND;
1037	switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 \| DISUSE_IMMEDIATE_ADDR_16_32 \| DISUSE_DISPLACEMENT64 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT16))
1038	{
1039	case DISUSE_IMMEDIATE_ADDR_16_16:
1040	PUT_NUM_16(pParam->uValue >> 16);
1041	PUT_C(':');
1042	PUT_NUM_16(pParam->uValue);
1043	if (pfnGetSymbol)
1044	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1045	break;
1046	case DISUSE_IMMEDIATE_ADDR_16_32:
1047	PUT_NUM_16(pParam->uValue >> 32);
1048	PUT_C(':');
1049	PUT_NUM_32(pParam->uValue);
1050	if (pfnGetSymbol)
1051	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1052	break;
1053	case DISUSE_DISPLACEMENT16:
1054	PUT_NUM_16(pParam->uDisp.i16);
1055	if (pfnGetSymbol)
1056	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u16, szSymbol, sizeof(szSymbol), &off, pvUser);
1057	break;
1058	case DISUSE_DISPLACEMENT32:
1059	PUT_NUM_32(pParam->uDisp.i32);
1060	if (pfnGetSymbol)
1061	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u32, szSymbol, sizeof(szSymbol), &off, pvUser);
1062	break;
1063	case DISUSE_DISPLACEMENT64:
1064	PUT_NUM_64(pParam->uDisp.i64);
1065	if (pfnGetSymbol)
1066	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u64, szSymbol, sizeof(szSymbol), &off, pvUser);
1067	break;
1068	default:
1069	AssertFailed();
1070	break;
1071	}
1072	PUT_C(']');
1073
1074	PUT_SYMBOL_TWO(rc, " (", ')');
1075	break;
1076	}
1077
1078	case 'X': /* DS:SI (ParseXb, ParseXv). */
1079	case 'Y': /* ES:DI (ParseYb, ParseYv). */
1080	{
1081	Assert(pszFmt == 'b' \|\| pszFmt == 'v'); pszFmt++;
1082	PUT_FAR();
1083	PUT_SIZE_OVERRIDE();
1084	PUT_C('[');
1085	if (pParam->fUse & DISUSE_POINTER_DS_BASED)
1086	PUT_SZ("ds:");
1087	else
1088	PUT_SZ("es:");
1089
1090	size_t cchReg;
1091	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
1092	PUT_STR(pszReg, cchReg);
1093	PUT_C(']');
1094	break;
1095	}
1096
1097	case 'e': /* Register based on operand size (e.g. %eAX, %eAH) (ParseFixedReg). */
1098	{
1099	Assert(RT_C_IS_ALPHA(pszFmt[0]) && RT_C_IS_ALPHA(pszFmt[1]) && !RT_C_IS_ALPHA(pszFmt[2]));
1100	pszFmt += 2;
1101	size_t cchReg;
1102	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
1103	PUT_STR(pszReg, cchReg);
1104	break;
1105	}
1106
1107	default:
1108	AssertMsgFailed(("%c%s!\n", ch, pszFmt));
1109	break;
1110	}
1111	AssertMsg(pszFmt == ',' \|\| pszFmt == '\0', ("%c%s\n", ch, pszFmt));
1112	}
1113	else
1114	{
1115	PUT_C(ch);
1116	if (ch == ',')
1117	{
1118	Assert(*pszFmt != ' ');
1119	PUT_C(' ');
1120	switch (++iParam)
1121	{
1122	case 2: pParam = &pDis->Param2; break;
1123	case 3: pParam = &pDis->Param3; break;
1124	default: pParam = NULL; break;
1125	}
1126	}
1127	}
1128	} /* while more to format */
1129	}
1130
1131	/*
1132	* Any additional output to the right of the instruction?
1133	*/
1134	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
1135	{
1136	/* some up front padding. */
1137	size_t cchPadding = cchOutput - offInstruction;
1138	cchPadding = cchPadding + 1 >= 42 ? 1 : 42 - cchPadding;
1139	PUT_STR(g_szSpaces, cchPadding);
1140
1141	/* comment? */
1142	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
1143	PUT_SZ(";");
1144
1145	/*
1146	* The address?
1147	*/
1148	if (fFlags & DIS_FMT_FLAGS_ADDR_RIGHT)
1149	{
1150	PUT_C(' ');
1151	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
1152	if (pDis->uInstrAddr >= _4G)
1153	PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
1154	#endif
1155	PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
1156	}
1157
1158	/*
1159	* Opcode bytes?
1160	*/
1161	if (fFlags & DIS_FMT_FLAGS_BYTES_RIGHT)
1162	{
1163	PUT_C(' ');
1164	size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
1165	cchOutput += cchTmp;
1166	if (cchTmp >= cchDst)
1167	cchTmp = cchDst - (cchDst != 0);
1168	cchDst -= cchTmp;
1169	pszDst += cchTmp;
1170	}
1171	}
1172
1173	/*
1174	* Terminate it - on overflow we'll have reserved one byte for this.
1175	*/
1176	if (cchDst > 0)
1177	*pszDst = '\0';
1178	else
1179	Assert(!cchBuf);
1180
1181	/* clean up macros */
1182	#undef PUT_PSZ
1183	#undef PUT_SZ
1184	#undef PUT_STR
1185	#undef PUT_C
1186	return cchOutput;
1187	}
1188
1189
1190	/**
1191	* Formats the current instruction in Yasm (/ Nasm) style.
1192	*
1193	* This is a simplified version of DISFormatYasmEx() provided for your convenience.
1194	*
1195	*
1196	* @returns The number of output characters. If this is >= cchBuf, then the content
1197	* of pszBuf will be truncated.
1198	* @param pDis Pointer to the disassembler state.
1199	* @param pszBuf The output buffer.
1200	* @param cchBuf The size of the output buffer.
1201	*/
1202	DISDECL(size_t) DISFormatYasm(PCDISSTATE pDis, char *pszBuf, size_t cchBuf)
1203	{
1204	return DISFormatYasmEx(pDis, pszBuf, cchBuf, 0 /* fFlags /, NULL / pfnGetSymbol /, NULL / pvUser */);
1205	}
1206
1207
1208	/**
1209	* Checks if the encoding of the given disassembled instruction is something we
1210	* can never get YASM to produce.
1211	*
1212	* @returns true if it's odd, false if it isn't.
1213	* @param pDis The disassembler output. The byte fetcher callback will
1214	* be used if present as we might need to fetch opcode
1215	* bytes.
1216	*/
1217	DISDECL(bool) DISFormatYasmIsOddEncoding(PDISSTATE pDis)
1218	{
1219	/*
1220	* Mod rm + SIB: Check for duplicate EBP encodings that yasm won't use for very good reasons.
1221	*/
1222	if ( pDis->uAddrMode != DISCPUMODE_16BIT ///@todo correct?
1223	&& pDis->ModRM.Bits.Rm == 4
1224	&& pDis->ModRM.Bits.Mod != 3)
1225	{
1226	/* No scaled index SIB (index=4), except for ESP. */
1227	if ( pDis->SIB.Bits.Index == 4
1228	&& pDis->SIB.Bits.Base != 4)
1229	return true;
1230
1231	/* EBP + displacement */
1232	if ( pDis->ModRM.Bits.Mod != 0
1233	&& pDis->SIB.Bits.Base == 5
1234	&& pDis->SIB.Bits.Scale == 0)
1235	return true;
1236	}
1237
1238	/*
1239	* Seems to be an instruction alias here, but I cannot find any docs on it... hrmpf!
1240	*/
1241	if ( pDis->pCurInstr->uOpcode == OP_SHL
1242	&& pDis->ModRM.Bits.Reg == 6)
1243	return true;
1244
1245	/*
1246	* Check for multiple prefixes of the same kind.
1247	*/
1248	uint8_t off1stSeg = UINT8_MAX;
1249	uint8_t offOpSize = UINT8_MAX;
1250	uint8_t offAddrSize = UINT8_MAX;
1251	uint32_t fPrefixes = 0;
1252	for (uint32_t offOpcode = 0; offOpcode < RT_ELEMENTS(pDis->abInstr); offOpcode++)
1253	{
1254	uint32_t f;
1255	switch (pDis->abInstr[offOpcode])
1256	{
1257	case 0xf0:
1258	f = DISPREFIX_LOCK;
1259	break;
1260
1261	case 0xf2:
1262	case 0xf3:
1263	f = DISPREFIX_REP; /* yes, both */
1264	break;
1265
1266	case 0x2e:
1267	case 0x3e:
1268	case 0x26:
1269	case 0x36:
1270	case 0x64:
1271	case 0x65:
1272	if (off1stSeg == UINT8_MAX)
1273	off1stSeg = offOpcode;
1274	f = DISPREFIX_SEG;
1275	break;
1276
1277	case 0x66:
1278	if (offOpSize == UINT8_MAX)
1279	offOpSize = offOpcode;
1280	f = DISPREFIX_OPSIZE;
1281	break;
1282
1283	case 0x67:
1284	if (offAddrSize == UINT8_MAX)
1285	offAddrSize = offOpcode;
1286	f = DISPREFIX_ADDRSIZE;
1287	break;
1288
1289	case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
1290	case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
1291	f = pDis->uCpuMode == DISCPUMODE_64BIT ? DISPREFIX_REX : 0;
1292	break;
1293
1294	default:
1295	f = 0;
1296	break;
1297	}
1298	if (!f)
1299	break; /* done */
1300	if (fPrefixes & f)
1301	return true;
1302	fPrefixes \|= f;
1303	}
1304
1305	/* segment overrides are fun */
1306	if (fPrefixes & DISPREFIX_SEG)
1307	{
1308	/* no effective address which it may apply to. */
1309	Assert((pDis->fPrefix & DISPREFIX_SEG) \|\| pDis->uCpuMode == DISCPUMODE_64BIT);
1310	if ( !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
1311	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
1312	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse))
1313	return true;
1314
1315	/* Yasm puts the segment prefixes before the operand prefix with no
1316	way of overriding it. */
1317	if (offOpSize < off1stSeg)
1318	return true;
1319	}
1320
1321	/* fixed register + addr override doesn't go down all that well. */
1322	if (fPrefixes & DISPREFIX_ADDRSIZE)
1323	{
1324	Assert(pDis->fPrefix & DISPREFIX_ADDRSIZE);
1325	if ( pDis->pCurInstr->fParam3 == OP_PARM_NONE
1326	&& pDis->pCurInstr->fParam2 == OP_PARM_NONE
1327	&& ( pDis->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
1328	&& pDis->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END))
1329	return true;
1330	}
1331
1332	/* Almost all prefixes are bad for jumps. */
1333	if (fPrefixes)
1334	{
1335	switch (pDis->pCurInstr->uOpcode)
1336	{
1337	/* nop w/ prefix(es). */
1338	case OP_NOP:
1339	return true;
1340
1341	case OP_JMP:
1342	if ( pDis->pCurInstr->fParam1 != OP_PARM_Jb
1343	&& pDis->pCurInstr->fParam1 != OP_PARM_Jv)
1344	break;
1345	/* fall thru */
1346	case OP_JO:
1347	case OP_JNO:
1348	case OP_JC:
1349	case OP_JNC:
1350	case OP_JE:
1351	case OP_JNE:
1352	case OP_JBE:
1353	case OP_JNBE:
1354	case OP_JS:
1355	case OP_JNS:
1356	case OP_JP:
1357	case OP_JNP:
1358	case OP_JL:
1359	case OP_JNL:
1360	case OP_JLE:
1361	case OP_JNLE:
1362	/** @todo branch hinting 0x2e/0x3e... */
1363	return true;
1364	}
1365
1366	}
1367
1368	/* All but the segment prefix is bad news for push/pop. */
1369	if (fPrefixes & ~DISPREFIX_SEG)
1370	{
1371	switch (pDis->pCurInstr->uOpcode)
1372	{
1373	case OP_POP:
1374	case OP_PUSH:
1375	if ( pDis->pCurInstr->fParam1 >= OP_PARM_REG_SEG_START
1376	&& pDis->pCurInstr->fParam1 <= OP_PARM_REG_SEG_END)
1377	return true;
1378	if ( (fPrefixes & ~DISPREFIX_OPSIZE)
1379	&& pDis->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
1380	&& pDis->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END)
1381	return true;
1382	break;
1383
1384	case OP_POPA:
1385	case OP_POPF:
1386	case OP_PUSHA:
1387	case OP_PUSHF:
1388	if (fPrefixes & ~DISPREFIX_OPSIZE)
1389	return true;
1390	break;
1391	}
1392	}
1393
1394	/* Implicit 8-bit register instructions doesn't mix with operand size. */
1395	if ( (fPrefixes & DISPREFIX_OPSIZE)
1396	&& ( ( pDis->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
1397	&& pDis->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
1398	\|\| ( pDis->pCurInstr->fParam2 == OP_PARM_Gb /* r8 */
1399	&& pDis->pCurInstr->fParam1 == OP_PARM_Eb /* r8/mem8 */))
1400	)
1401	{
1402	switch (pDis->pCurInstr->uOpcode)
1403	{
1404	case OP_ADD:
1405	case OP_OR:
1406	case OP_ADC:
1407	case OP_SBB:
1408	case OP_AND:
1409	case OP_SUB:
1410	case OP_XOR:
1411	case OP_CMP:
1412	return true;
1413	default:
1414	break;
1415	}
1416	}
1417
1418	/* Instructions taking no address or operand which thus may be annoyingly
1419	difficult to format for yasm. */
1420	if (fPrefixes)
1421	{
1422	switch (pDis->pCurInstr->uOpcode)
1423	{
1424	case OP_STI:
1425	case OP_STC:
1426	case OP_CLI:
1427	case OP_CLD:
1428	case OP_CLC:
1429	case OP_INT:
1430	case OP_INT3:
1431	case OP_INTO:
1432	case OP_HLT:
1433	/** @todo Many more to can be added here. */
1434	return true;
1435	default:
1436	break;
1437	}
1438	}
1439
1440	/* FPU and other instructions that ignores operand size override. */
1441	if (fPrefixes & DISPREFIX_OPSIZE)
1442	{
1443	switch (pDis->pCurInstr->uOpcode)
1444	{
1445	/* FPU: */
1446	case OP_FIADD:
1447	case OP_FIMUL:
1448	case OP_FISUB:
1449	case OP_FISUBR:
1450	case OP_FIDIV:
1451	case OP_FIDIVR:
1452	/** @todo there are many more. */
1453	return true;
1454
1455	case OP_MOV:
1456	/** @todo could be that we're not disassembling these correctly. */
1457	if (pDis->pCurInstr->fParam1 == OP_PARM_Sw)
1458	return true;
1459	/** @todo what about the other way? */
1460	break;
1461
1462	default:
1463	break;
1464	}
1465	}
1466
1467
1468	/*
1469	* Check for the version of xyz reg,reg instruction that the assembler doesn't use.
1470	*
1471	* For example:
1472	* expected: 1aee sbb ch, dh ; SBB r8, r/m8
1473	* yasm: 18F5 sbb ch, dh ; SBB r/m8, r8
1474	*/
1475	if (pDis->ModRM.Bits.Mod == 3 /* reg,reg */)
1476	{
1477	switch (pDis->pCurInstr->uOpcode)
1478	{
1479	case OP_ADD:
1480	case OP_OR:
1481	case OP_ADC:
1482	case OP_SBB:
1483	case OP_AND:
1484	case OP_SUB:
1485	case OP_XOR:
1486	case OP_CMP:
1487	if ( ( pDis->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
1488	&& pDis->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
1489	\|\| ( pDis->pCurInstr->fParam1 == OP_PARM_Gv /* rX */
1490	&& pDis->pCurInstr->fParam2 == OP_PARM_Ev /* rX/memX */))
1491	return true;
1492
1493	/* 82 (see table A-6). */
1494	if (pDis->bOpCode == 0x82)
1495	return true;
1496	break;
1497
1498	/* ff /0, fe /0, ff /1, fe /0 */
1499	case OP_DEC:
1500	case OP_INC:
1501	return true;
1502
1503	case OP_POP:
1504	case OP_PUSH:
1505	Assert(pDis->bOpCode == 0x8f);
1506	return true;
1507
1508	case OP_MOV:
1509	if ( pDis->bOpCode == 0x8a
1510	\|\| pDis->bOpCode == 0x8b)
1511	return true;
1512	break;
1513
1514	default:
1515	break;
1516	}
1517	}
1518
1519	/* shl eax,1 will be assembled to the form without the immediate byte. */
1520	if ( pDis->pCurInstr->fParam2 == OP_PARM_Ib
1521	&& (uint8_t)pDis->Param2.uValue == 1)
1522	{
1523	switch (pDis->pCurInstr->uOpcode)
1524	{
1525	case OP_SHL:
1526	case OP_SHR:
1527	case OP_SAR:
1528	case OP_RCL:
1529	case OP_RCR:
1530	case OP_ROL:
1531	case OP_ROR:
1532	return true;
1533	}
1534	}
1535
1536	/* And some more - see table A-6. */
1537	if (pDis->bOpCode == 0x82)
1538	{
1539	switch (pDis->pCurInstr->uOpcode)
1540	{
1541	case OP_ADD:
1542	case OP_OR:
1543	case OP_ADC:
1544	case OP_SBB:
1545	case OP_AND:
1546	case OP_SUB:
1547	case OP_XOR:
1548	case OP_CMP:
1549	return true;
1550	break;
1551	}
1552	}
1553
1554
1555	/* check for REX.X = 1 without SIB. */
1556
1557	/* Yasm encodes setnbe al with /2 instead of /0 like the AMD manual
1558	says (intel doesn't appear to care). */
1559	switch (pDis->pCurInstr->uOpcode)
1560	{
1561	case OP_SETO:
1562	case OP_SETNO:
1563	case OP_SETC:
1564	case OP_SETNC:
1565	case OP_SETE:
1566	case OP_SETNE:
1567	case OP_SETBE:
1568	case OP_SETNBE:
1569	case OP_SETS:
1570	case OP_SETNS:
1571	case OP_SETP:
1572	case OP_SETNP:
1573	case OP_SETL:
1574	case OP_SETNL:
1575	case OP_SETLE:
1576	case OP_SETNLE:
1577	AssertMsg(pDis->bOpCode >= 0x90 && pDis->bOpCode <= 0x9f, ("%#x\n", pDis->bOpCode));
1578	if (pDis->ModRM.Bits.Reg != 2)
1579	return true;
1580	break;
1581	}
1582
1583	/*
1584	* The MOVZX reg32,mem16 instruction without an operand size prefix
1585	* doesn't quite make sense...
1586	*/
1587	if ( pDis->pCurInstr->uOpcode == OP_MOVZX
1588	&& pDis->bOpCode == 0xB7
1589	&& (pDis->uCpuMode == DISCPUMODE_16BIT) != !!(fPrefixes & DISPREFIX_OPSIZE))
1590	return true;
1591
1592	return false;
1593	}
1594

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source: vbox/trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp@ 49905

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