DisasmFormatYasm.cpp@ 78412

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1	/* $Id: DisasmFormatYasm.cpp 76553 2019-01-01 01:45:53Z vboxsync $ */
2	/** @file
3	* VBox Disassembler - Yasm(/Nasm) Style Formatter.
4	*/
5
6	/*
7	* Copyright (C) 2008-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#include <VBox/dis.h>
23	#include "DisasmInternal.h"
24	#include <iprt/assert.h>
25	#include <iprt/ctype.h>
26	#include <iprt/err.h>
27	#include <iprt/string.h>
28
29
30	/*********************************************************************************************************************************
31	* Global Variables *
32	*********************************************************************************************************************************/
33	static const char g_szSpaces[] =
34	" ";
35	static const char g_aszYasmRegGen8[20][5] =
36	{
37	"al\0\0", "cl\0\0", "dl\0\0", "bl\0\0", "ah\0\0", "ch\0\0", "dh\0\0", "bh\0\0", "r8b\0", "r9b\0", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b", "spl\0", "bpl\0", "sil\0", "dil\0"
38	};
39	static const char g_aszYasmRegGen16[16][5] =
40	{
41	"ax\0\0", "cx\0\0", "dx\0\0", "bx\0\0", "sp\0\0", "bp\0\0", "si\0\0", "di\0\0", "r8w\0", "r9w\0", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
42	};
43	#if 0 /* unused */
44	static const char g_aszYasmRegGen1616[8][6] =
45	{
46	"bx+si", "bx+di", "bp+si", "bp+di", "si\0\0\0", "di\0\0\0", "bp\0\0\0", "bx\0\0\0"
47	};
48	#endif
49	static const char g_aszYasmRegGen32[16][5] =
50	{
51	"eax\0", "ecx\0", "edx\0", "ebx\0", "esp\0", "ebp\0", "esi\0", "edi\0", "r8d\0", "r9d\0", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
52	};
53	static const char g_aszYasmRegGen64[16][4] =
54	{
55	"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", "r8\0", "r9\0", "r10", "r11", "r12", "r13", "r14", "r15"
56	};
57	static const char g_aszYasmRegSeg[6][3] =
58	{
59	"es", "cs", "ss", "ds", "fs", "gs"
60	};
61	static const char g_aszYasmRegFP[8][4] =
62	{
63	"st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7"
64	};
65	static const char g_aszYasmRegMMX[8][4] =
66	{
67	"mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7"
68	};
69	static const char g_aszYasmRegXMM[16][6] =
70	{
71	"xmm0\0", "xmm1\0", "xmm2\0", "xmm3\0", "xmm4\0", "xmm5\0", "xmm6\0", "xmm7\0", "xmm8\0", "xmm9\0", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
72	};
73	static const char g_aszYasmRegYMM[16][6] =
74	{
75	"ymm0\0", "ymm1\0", "ymm2\0", "ymm3\0", "ymm4\0", "ymm5\0", "ymm6\0", "ymm7\0", "ymm8\0", "ymm9\0", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15"
76	};
77	static const char g_aszYasmRegCRx[16][5] =
78	{
79	"cr0\0", "cr1\0", "cr2\0", "cr3\0", "cr4\0", "cr5\0", "cr6\0", "cr7\0", "cr8\0", "cr9\0", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15"
80	};
81	static const char g_aszYasmRegDRx[16][5] =
82	{
83	"dr0\0", "dr1\0", "dr2\0", "dr3\0", "dr4\0", "dr5\0", "dr6\0", "dr7\0", "dr8\0", "dr9\0", "dr10", "dr11", "dr12", "dr13", "dr14", "dr15"
84	};
85	static const char g_aszYasmRegTRx[16][5] =
86	{
87	"tr0\0", "tr1\0", "tr2\0", "tr3\0", "tr4\0", "tr5\0", "tr6\0", "tr7\0", "tr8\0", "tr9\0", "tr10", "tr11", "tr12", "tr13", "tr14", "tr15"
88	};
89
90
91
92	/**
93	* Gets the base register name for the given parameter.
94	*
95	* @returns Pointer to the register name.
96	* @param pDis The disassembler state.
97	* @param pParam The parameter.
98	* @param pcchReg Where to store the length of the name.
99	*/
100	static const char disasmFormatYasmBaseReg(PCDISSTATE pDis, PCDISOPPARAM pParam, size_t pcchReg)
101	{
102	RT_NOREF_PV(pDis);
103
104	switch (pParam->fUse & ( DISUSE_REG_GEN8 \| DISUSE_REG_GEN16 \| DISUSE_REG_GEN32 \| DISUSE_REG_GEN64
105	\| DISUSE_REG_FP \| DISUSE_REG_MMX \| DISUSE_REG_XMM \| DISUSE_REG_YMM
106	\| DISUSE_REG_CR \| DISUSE_REG_DBG \| DISUSE_REG_SEG \| DISUSE_REG_TEST))
107
108	{
109	case DISUSE_REG_GEN8:
110	{
111	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen8));
112	const char *psz = g_aszYasmRegGen8[pParam->Base.idxGenReg];
113	*pcchReg = 2 + !!psz[2] + !!psz[3];
114	return psz;
115	}
116
117	case DISUSE_REG_GEN16:
118	{
119	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
120	const char *psz = g_aszYasmRegGen16[pParam->Base.idxGenReg];
121	*pcchReg = 2 + !!psz[2] + !!psz[3];
122	return psz;
123	}
124
125	// VSIB
126	case DISUSE_REG_XMM \| DISUSE_REG_GEN32:
127	case DISUSE_REG_YMM \| DISUSE_REG_GEN32:
128	case DISUSE_REG_GEN32:
129	{
130	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
131	const char *psz = g_aszYasmRegGen32[pParam->Base.idxGenReg];
132	*pcchReg = 2 + !!psz[2] + !!psz[3];
133	return psz;
134	}
135
136	// VSIB
137	case DISUSE_REG_XMM \| DISUSE_REG_GEN64:
138	case DISUSE_REG_YMM \| DISUSE_REG_GEN64:
139	case DISUSE_REG_GEN64:
140	{
141	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
142	const char *psz = g_aszYasmRegGen64[pParam->Base.idxGenReg];
143	*pcchReg = 2 + !!psz[2] + !!psz[3];
144	return psz;
145	}
146
147	case DISUSE_REG_FP:
148	{
149	Assert(pParam->Base.idxFpuReg < RT_ELEMENTS(g_aszYasmRegFP));
150	const char *psz = g_aszYasmRegFP[pParam->Base.idxFpuReg];
151	*pcchReg = 3;
152	return psz;
153	}
154
155	case DISUSE_REG_MMX:
156	{
157	Assert(pParam->Base.idxMmxReg < RT_ELEMENTS(g_aszYasmRegMMX));
158	const char *psz = g_aszYasmRegMMX[pParam->Base.idxMmxReg];
159	*pcchReg = 3;
160	return psz;
161	}
162
163	case DISUSE_REG_XMM:
164	{
165	Assert(pParam->Base.idxXmmReg < RT_ELEMENTS(g_aszYasmRegXMM));
166	const char *psz = g_aszYasmRegXMM[pParam->Base.idxXmmReg];
167	*pcchReg = 4 + !!psz[4];
168	return psz;
169	}
170
171	case DISUSE_REG_YMM:
172	{
173	Assert(pParam->Base.idxYmmReg < RT_ELEMENTS(g_aszYasmRegYMM));
174	const char *psz = g_aszYasmRegYMM[pParam->Base.idxYmmReg];
175	*pcchReg = 4 + !!psz[4];
176	return psz;
177	}
178
179	case DISUSE_REG_CR:
180	{
181	Assert(pParam->Base.idxCtrlReg < RT_ELEMENTS(g_aszYasmRegCRx));
182	const char *psz = g_aszYasmRegCRx[pParam->Base.idxCtrlReg];
183	*pcchReg = 3;
184	return psz;
185	}
186
187	case DISUSE_REG_DBG:
188	{
189	Assert(pParam->Base.idxDbgReg < RT_ELEMENTS(g_aszYasmRegDRx));
190	const char *psz = g_aszYasmRegDRx[pParam->Base.idxDbgReg];
191	*pcchReg = 3;
192	return psz;
193	}
194
195	case DISUSE_REG_SEG:
196	{
197	Assert(pParam->Base.idxSegReg < RT_ELEMENTS(g_aszYasmRegCRx));
198	const char *psz = g_aszYasmRegSeg[pParam->Base.idxSegReg];
199	*pcchReg = 2;
200	return psz;
201	}
202
203	case DISUSE_REG_TEST:
204	{
205	Assert(pParam->Base.idxTestReg < RT_ELEMENTS(g_aszYasmRegTRx));
206	const char *psz = g_aszYasmRegTRx[pParam->Base.idxTestReg];
207	*pcchReg = 3;
208	return psz;
209	}
210
211	default:
212	AssertMsgFailed(("%#x\n", pParam->fUse));
213	*pcchReg = 3;
214	return "r??";
215	}
216	}
217
218
219	/**
220	* Gets the index register name for the given parameter.
221	*
222	* @returns The index register name.
223	* @param pDis The disassembler state.
224	* @param pParam The parameter.
225	* @param pcchReg Where to store the length of the name.
226	*/
227	static const char disasmFormatYasmIndexReg(PCDISSTATE pDis, PCDISOPPARAM pParam, size_t pcchReg)
228	{
229	if (pParam->fUse & DISUSE_REG_XMM)
230	{
231	Assert(pParam->Index.idxXmmReg < RT_ELEMENTS(g_aszYasmRegXMM));
232	const char *psz = g_aszYasmRegXMM[pParam->Index.idxXmmReg];
233	*pcchReg = 4 + !!psz[4];
234	return psz;
235	}
236	else if (pParam->fUse & DISUSE_REG_YMM)
237	{
238	Assert(pParam->Index.idxYmmReg < RT_ELEMENTS(g_aszYasmRegYMM));
239	const char *psz = g_aszYasmRegYMM[pParam->Index.idxYmmReg];
240	*pcchReg = 4 + !!psz[4];
241	return psz;
242
243	}
244	else
245	switch (pDis->uAddrMode)
246	{
247	case DISCPUMODE_16BIT:
248	{
249	Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
250	const char *psz = g_aszYasmRegGen16[pParam->Index.idxGenReg];
251	*pcchReg = 2 + !!psz[2] + !!psz[3];
252	return psz;
253	}
254
255	case DISCPUMODE_32BIT:
256	{
257	Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
258	const char *psz = g_aszYasmRegGen32[pParam->Index.idxGenReg];
259	*pcchReg = 2 + !!psz[2] + !!psz[3];
260	return psz;
261	}
262
263	case DISCPUMODE_64BIT:
264	{
265	Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
266	const char *psz = g_aszYasmRegGen64[pParam->Index.idxGenReg];
267	*pcchReg = 2 + !!psz[2] + !!psz[3];
268	return psz;
269	}
270
271	default:
272	AssertMsgFailed(("%#x %#x\n", pParam->fUse, pDis->uAddrMode));
273	*pcchReg = 3;
274	return "r??";
275	}
276	}
277
278
279	/**
280	* Formats the current instruction in Yasm (/ Nasm) style.
281	*
282	*
283	* @returns The number of output characters. If this is >= cchBuf, then the content
284	* of pszBuf will be truncated.
285	* @param pDis Pointer to the disassembler state.
286	* @param pszBuf The output buffer.
287	* @param cchBuf The size of the output buffer.
288	* @param fFlags Format flags, see DIS_FORMAT_FLAGS_*.
289	* @param pfnGetSymbol Get symbol name for a jmp or call target address. Optional.
290	* @param pvUser User argument for pfnGetSymbol.
291	*/
292	DISDECL(size_t) DISFormatYasmEx(PCDISSTATE pDis, char *pszBuf, size_t cchBuf, uint32_t fFlags,
293	PFNDISGETSYMBOL pfnGetSymbol, void *pvUser)
294	{
295	/** @todo monitor and mwait aren't formatted correctly in 64-bit mode. */
296	/*
297	* Input validation and massaging.
298	*/
299	AssertPtr(pDis);
300	AssertPtrNull(pszBuf);
301	Assert(pszBuf \|\| !cchBuf);
302	AssertPtrNull(pfnGetSymbol);
303	AssertMsg(DIS_FMT_FLAGS_IS_VALID(fFlags), ("%#x\n", fFlags));
304	if (fFlags & DIS_FMT_FLAGS_ADDR_COMMENT)
305	fFlags = (fFlags & ~DIS_FMT_FLAGS_ADDR_LEFT) \| DIS_FMT_FLAGS_ADDR_RIGHT;
306	if (fFlags & DIS_FMT_FLAGS_BYTES_COMMENT)
307	fFlags = (fFlags & ~DIS_FMT_FLAGS_BYTES_LEFT) \| DIS_FMT_FLAGS_BYTES_RIGHT;
308
309	PCDISOPCODE const pOp = pDis->pCurInstr;
310
311	/*
312	* Output macros
313	*/
314	char *pszDst = pszBuf;
315	size_t cchDst = cchBuf;
316	size_t cchOutput = 0;
317	#define PUT_C(ch) \
318	do { \
319	cchOutput++; \
320	if (cchDst > 1) \
321	{ \
322	cchDst--; \
323	*pszDst++ = (ch); \
324	} \
325	} while (0)
326	#define PUT_STR(pszSrc, cchSrc) \
327	do { \
328	cchOutput += (cchSrc); \
329	if (cchDst > (cchSrc)) \
330	{ \
331	memcpy(pszDst, (pszSrc), (cchSrc)); \
332	pszDst += (cchSrc); \
333	cchDst -= (cchSrc); \
334	} \
335	else if (cchDst > 1) \
336	{ \
337	memcpy(pszDst, (pszSrc), cchDst - 1); \
338	pszDst += cchDst - 1; \
339	cchDst = 1; \
340	} \
341	} while (0)
342	#define PUT_SZ(sz) \
343	PUT_STR((sz), sizeof(sz) - 1)
344	#define PUT_SZ_STRICT(szStrict, szRelaxed) \
345	do { if (fFlags & DIS_FMT_FLAGS_STRICT) PUT_SZ(szStrict); else PUT_SZ(szRelaxed); } while (0)
346	#define PUT_PSZ(psz) \
347	do { const size_t cchTmp = strlen(psz); PUT_STR((psz), cchTmp); } while (0)
348	#define PUT_NUM(cch, fmt, num) \
349	do { \
350	cchOutput += (cch); \
351	if (cchDst > 1) \
352	{ \
353	const size_t cchTmp = RTStrPrintf(pszDst, cchDst, fmt, (num)); \
354	pszDst += cchTmp; \
355	cchDst -= cchTmp; \
356	Assert(cchTmp == (cch) \|\| cchDst == 1); \
357	} \
358	} while (0)
359	/** @todo add two flags for choosing between %X / %x and h / 0x. */
360	#define PUT_NUM_8(num) PUT_NUM(4, "0%02xh", (uint8_t)(num))
361	#define PUT_NUM_16(num) PUT_NUM(6, "0%04xh", (uint16_t)(num))
362	#define PUT_NUM_32(num) PUT_NUM(10, "0%08xh", (uint32_t)(num))
363	#define PUT_NUM_64(num) PUT_NUM(18, "0%016RX64h", (uint64_t)(num))
364
365	#define PUT_NUM_SIGN(cch, fmt, num, stype, utype) \
366	do { \
367	if ((stype)(num) >= 0) \
368	{ \
369	PUT_C('+'); \
370	PUT_NUM(cch, fmt, (utype)(num)); \
371	} \
372	else \
373	{ \
374	PUT_C('-'); \
375	PUT_NUM(cch, fmt, (utype)-(stype)(num)); \
376	} \
377	} while (0)
378	#define PUT_NUM_S8(num) PUT_NUM_SIGN(4, "0%02xh", num, int8_t, uint8_t)
379	#define PUT_NUM_S16(num) PUT_NUM_SIGN(6, "0%04xh", num, int16_t, uint16_t)
380	#define PUT_NUM_S32(num) PUT_NUM_SIGN(10, "0%08xh", num, int32_t, uint32_t)
381	#define PUT_NUM_S64(num) PUT_NUM_SIGN(18, "0%016RX64h", num, int64_t, uint64_t)
382
383	#define PUT_SYMBOL_TWO(a_rcSym, a_szStart, a_chEnd) \
384	do { \
385	if (RT_SUCCESS(a_rcSym)) \
386	{ \
387	PUT_SZ(a_szStart); \
388	PUT_PSZ(szSymbol); \
389	if (off != 0) \
390	{ \
391	if ((int8_t)off == off) \
392	PUT_NUM_S8(off); \
393	else if ((int16_t)off == off) \
394	PUT_NUM_S16(off); \
395	else if ((int32_t)off == off) \
396	PUT_NUM_S32(off); \
397	else \
398	PUT_NUM_S64(off); \
399	} \
400	PUT_C(a_chEnd); \
401	} \
402	} while (0)
403
404	#define PUT_SYMBOL(a_uSeg, a_uAddr, a_szStart, a_chEnd) \
405	do { \
406	if (pfnGetSymbol) \
407	{ \
408	int rcSym = pfnGetSymbol(pDis, a_uSeg, a_uAddr, szSymbol, sizeof(szSymbol), &off, pvUser); \
409	PUT_SYMBOL_TWO(rcSym, a_szStart, a_chEnd); \
410	} \
411	} while (0)
412
413
414	/*
415	* The address?
416	*/
417	if (fFlags & DIS_FMT_FLAGS_ADDR_LEFT)
418	{
419	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
420	if (pDis->uInstrAddr >= _4G)
421	PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
422	#endif
423	PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
424	PUT_C(' ');
425	}
426
427	/*
428	* The opcode bytes?
429	*/
430	if (fFlags & DIS_FMT_FLAGS_BYTES_LEFT)
431	{
432	size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
433	cchOutput += cchTmp;
434	if (cchDst > 1)
435	{
436	if (cchTmp <= cchDst)
437	{
438	cchDst -= cchTmp;
439	pszDst += cchTmp;
440	}
441	else
442	{
443	pszDst += cchDst - 1;
444	cchDst = 1;
445	}
446	}
447
448	/* Some padding to align the instruction. */
449	size_t cchPadding = (7 * (2 + !!(fFlags & DIS_FMT_FLAGS_BYTES_SPACED)))
450	+ !!(fFlags & DIS_FMT_FLAGS_BYTES_BRACKETS) * 2
451	+ 2;
452	cchPadding = cchTmp + 1 >= cchPadding ? 1 : cchPadding - cchTmp;
453	PUT_STR(g_szSpaces, cchPadding);
454	}
455
456
457	/*
458	* Filter out invalid opcodes first as they need special
459	* treatment. UD2 is an exception and should be handled normally.
460	*/
461	size_t const offInstruction = cchOutput;
462	if ( pOp->uOpcode == OP_INVALID
463	\|\| ( pOp->uOpcode == OP_ILLUD2
464	&& (pDis->fPrefix & DISPREFIX_LOCK)))
465	PUT_SZ("Illegal opcode");
466	else
467	{
468	/*
469	* Prefixes
470	*/
471	if (pDis->fPrefix & DISPREFIX_LOCK)
472	PUT_SZ("lock ");
473	if (pDis->fPrefix & DISPREFIX_REP)
474	PUT_SZ("rep ");
475	else if(pDis->fPrefix & DISPREFIX_REPNE)
476	PUT_SZ("repne ");
477
478	/*
479	* Adjust the format string to the correct mnemonic
480	* or to avoid things the assembler cannot handle correctly.
481	*/
482	char szTmpFmt[48];
483	const char *pszFmt = pOp->pszOpcode;
484	bool fIgnoresOpSize = false;
485	bool fMayNeedAddrSize = false;
486	switch (pOp->uOpcode)
487	{
488	case OP_JECXZ:
489	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "jcxz %Jb" : pDis->uOpMode == DISCPUMODE_32BIT ? "jecxz %Jb" : "jrcxz %Jb";
490	break;
491	case OP_PUSHF:
492	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "pushfw" : pDis->uOpMode == DISCPUMODE_32BIT ? "pushfd" : "pushfq";
493	break;
494	case OP_POPF:
495	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "popfw" : pDis->uOpMode == DISCPUMODE_32BIT ? "popfd" : "popfq";
496	break;
497	case OP_PUSHA:
498	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "pushaw" : "pushad";
499	break;
500	case OP_POPA:
501	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "popaw" : "popad";
502	break;
503	case OP_INSB:
504	pszFmt = "insb";
505	fIgnoresOpSize = fMayNeedAddrSize = true;
506	break;
507	case OP_INSWD:
508	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "insw" : pDis->uOpMode == DISCPUMODE_32BIT ? "insd" : "insq";
509	fMayNeedAddrSize = true;
510	break;
511	case OP_OUTSB:
512	pszFmt = "outsb";
513	fIgnoresOpSize = fMayNeedAddrSize = true;
514	break;
515	case OP_OUTSWD:
516	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "outsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "outsd" : "outsq";
517	fMayNeedAddrSize = true;
518	break;
519	case OP_MOVSB:
520	pszFmt = "movsb";
521	fIgnoresOpSize = fMayNeedAddrSize = true;
522	break;
523	case OP_MOVSWD:
524	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "movsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "movsd" : "movsq";
525	fMayNeedAddrSize = true;
526	break;
527	case OP_CMPSB:
528	pszFmt = "cmpsb";
529	fIgnoresOpSize = fMayNeedAddrSize = true;
530	break;
531	case OP_CMPWD:
532	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cmpsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "cmpsd" : "cmpsq";
533	fMayNeedAddrSize = true;
534	break;
535	case OP_SCASB:
536	pszFmt = "scasb";
537	fIgnoresOpSize = fMayNeedAddrSize = true;
538	break;
539	case OP_SCASWD:
540	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "scasw" : pDis->uOpMode == DISCPUMODE_32BIT ? "scasd" : "scasq";
541	fMayNeedAddrSize = true;
542	break;
543	case OP_LODSB:
544	pszFmt = "lodsb";
545	fIgnoresOpSize = fMayNeedAddrSize = true;
546	break;
547	case OP_LODSWD:
548	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "lodsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "lodsd" : "lodsq";
549	fMayNeedAddrSize = true;
550	break;
551	case OP_STOSB:
552	pszFmt = "stosb";
553	fIgnoresOpSize = fMayNeedAddrSize = true;
554	break;
555	case OP_STOSWD:
556	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "stosw" : pDis->uOpMode == DISCPUMODE_32BIT ? "stosd" : "stosq";
557	fMayNeedAddrSize = true;
558	break;
559	case OP_CBW:
560	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cbw" : pDis->uOpMode == DISCPUMODE_32BIT ? "cwde" : "cdqe";
561	break;
562	case OP_CWD:
563	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cwd" : pDis->uOpMode == DISCPUMODE_32BIT ? "cdq" : "cqo";
564	break;
565	case OP_SHL:
566	Assert(pszFmt[3] == '/');
567	pszFmt += 4;
568	break;
569	case OP_XLAT:
570	pszFmt = "xlatb";
571	break;
572	case OP_INT3:
573	pszFmt = "int3";
574	break;
575
576	/*
577	* Don't know how to tell yasm to generate complicated nop stuff, so 'db' it.
578	*/
579	case OP_NOP:
580	if (pDis->bOpCode == 0x90)
581	/* fine, fine */;
582	else if (pszFmt[sizeof("nop %Ev") - 1] == '/' && pszFmt[sizeof("nop %Ev")] == 'p')
583	pszFmt = "prefetch %Eb";
584	else if (pDis->bOpCode == 0x1f)
585	{
586	Assert(pDis->cbInstr >= 3);
587	PUT_SZ("db 00fh, 01fh,");
588	PUT_NUM_8(MAKE_MODRM(pDis->ModRM.Bits.Mod, pDis->ModRM.Bits.Reg, pDis->ModRM.Bits.Rm));
589	for (unsigned i = 3; i < pDis->cbInstr; i++)
590	{
591	PUT_C(',');
592	PUT_NUM_8(0x90); /// @todo fixme.
593	}
594	pszFmt = "";
595	}
596	break;
597
598	default:
599	/* ST(X) -> stX (floating point) */
600	if (*pszFmt == 'f' && strchr(pszFmt, '('))
601	{
602	char *pszFmtDst = szTmpFmt;
603	char ch;
604	do
605	{
606	ch = *pszFmt++;
607	if (ch == 'S' && pszFmt[0] == 'T' && pszFmt[1] == '(')
608	{
609	*pszFmtDst++ = 's';
610	*pszFmtDst++ = 't';
611	pszFmt += 2;
612	ch = *pszFmt;
613	Assert(pszFmt[1] == ')');
614	pszFmt += 2;
615	*pszFmtDst++ = ch;
616	}
617	else
618	*pszFmtDst++ = ch;
619	} while (ch != '\0');
620	pszFmt = szTmpFmt;
621	}
622	if (strchr ("#@&", *pszFmt))
623	{
624	const char *pszDelim = strchr(pszFmt, '/');
625	const char *pszSpace = (pszDelim ? strchr(pszDelim, ' ') : NULL);
626	if (pszDelim != NULL)
627	{
628	char *pszFmtDst = szTmpFmt;
629	if (pszSpace == NULL) pszSpace = strchr(pszDelim, 0);
630	if ( (*pszFmt == '#' && pDis->bVexWFlag)
631	\|\| (*pszFmt == '@' && !VEXREG_IS256B(pDis->bVexDestReg))
632	\|\| (*pszFmt == '&' && ( DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
633	\|\| DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
634	\|\| DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse)
635	\|\| DISUSE_IS_EFFECTIVE_ADDR(pDis->Param4.fUse))))
636	{
637	strncpy(pszFmtDst, pszFmt + 1, pszDelim - pszFmt - 1);
638	pszFmtDst += pszDelim - pszFmt - 1;
639	}
640	else
641	{
642	strncpy(pszFmtDst, pszDelim + 1, pszSpace - pszDelim - 1);
643	pszFmtDst += pszSpace - pszDelim - 1;
644	}
645	strcpy (pszFmtDst, pszSpace);
646	pszFmt = szTmpFmt;
647	}
648	}
649	break;
650
651	/*
652	* Horrible hacks.
653	*/
654	case OP_FLD:
655	if (pDis->bOpCode == 0xdb) /* m80fp workaround. */
656	(int )&pDis->Param1.fParam &= ~0x1f; /* make it pure OP_PARM_M */
657	break;
658	case OP_LAR: /* hack w -> v, probably not correct. */
659	(int )&pDis->Param2.fParam &= ~0x1f;
660	(int )&pDis->Param2.fParam \|= OP_PARM_v;
661	break;
662	}
663
664	/*
665	* Add operand size and address prefixes for outsb, movsb, etc.
666	*/
667	if (pDis->fPrefix & (DISPREFIX_OPSIZE \| DISPREFIX_ADDRSIZE))
668	{
669	if (fIgnoresOpSize && (pDis->fPrefix & DISPREFIX_OPSIZE) )
670	{
671	if (pDis->uCpuMode == DISCPUMODE_16BIT)
672	PUT_SZ("o32 ");
673	else
674	PUT_SZ("o16 ");
675	}
676	if (fMayNeedAddrSize && (pDis->fPrefix & DISPREFIX_ADDRSIZE) )
677	{
678	if (pDis->uCpuMode == DISCPUMODE_16BIT)
679	PUT_SZ("a32 ");
680	else
681	PUT_SZ("a16 ");
682	}
683	}
684
685	/*
686	* Formatting context and associated macros.
687	*/
688	PCDISOPPARAM pParam = &pDis->Param1;
689	int iParam = 1;
690
691	#define PUT_FAR() \
692	do { \
693	if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_p \
694	&& pOp->uOpcode != OP_LDS /* table bugs? */ \
695	&& pOp->uOpcode != OP_LES \
696	&& pOp->uOpcode != OP_LFS \
697	&& pOp->uOpcode != OP_LGS \
698	&& pOp->uOpcode != OP_LSS ) \
699	PUT_SZ("far "); \
700	} while (0)
701	/** @todo mov ah,ch ends up with a byte 'override'... - check if this wasn't fixed. */
702	/** @todo drop the work/dword/qword override when the src/dst is a register (except for movsx/movzx). */
703	#define PUT_SIZE_OVERRIDE() \
704	do { \
705	switch (OP_PARM_VSUBTYPE(pParam->fParam)) \
706	{ \
707	case OP_PARM_v: \
708	case OP_PARM_y: \
709	switch (pDis->uOpMode) \
710	{ \
711	case DISCPUMODE_16BIT: if (OP_PARM_VSUBTYPE(pParam->fParam) != OP_PARM_y) PUT_SZ("word "); break; \
712	case DISCPUMODE_32BIT: \
713	if (pDis->pCurInstr->uOpcode != OP_GATHER \|\| pDis->bVexWFlag) { PUT_SZ("dword "); break; } \
714	RT_FALL_THRU(); \
715	case DISCPUMODE_64BIT: PUT_SZ("qword "); break; \
716	default: break; \
717	} \
718	break; \
719	case OP_PARM_b: PUT_SZ("byte "); break; \
720	case OP_PARM_w: \
721	if (OP_PARM_VTYPE(pParam->fParam) == OP_PARM_W \|\| \
722	OP_PARM_VTYPE(pParam->fParam) == OP_PARM_M) \
723	{ \
724	if (VEXREG_IS256B(pDis->bVexDestReg)) PUT_SZ("dword "); \
725	else PUT_SZ("word "); \
726	} \
727	break; \
728	case OP_PARM_d: \
729	if (OP_PARM_VTYPE(pParam->fParam) == OP_PARM_W \|\| \
730	OP_PARM_VTYPE(pParam->fParam) == OP_PARM_M) \
731	{ \
732	if (VEXREG_IS256B(pDis->bVexDestReg)) PUT_SZ("qword "); \
733	else PUT_SZ("dword "); \
734	} \
735	break; \
736	case OP_PARM_q: \
737	if (OP_PARM_VTYPE(pParam->fParam) == OP_PARM_W \|\| \
738	OP_PARM_VTYPE(pParam->fParam) == OP_PARM_M) \
739	{ \
740	if (VEXREG_IS256B(pDis->bVexDestReg)) PUT_SZ("oword "); \
741	else PUT_SZ("qword "); \
742	} \
743	break; \
744	case OP_PARM_ps: \
745	case OP_PARM_pd: \
746	case OP_PARM_x: if (VEXREG_IS256B(pDis->bVexDestReg)) { PUT_SZ("yword "); break; } RT_FALL_THRU(); \
747	case OP_PARM_ss: \
748	case OP_PARM_sd: \
749	case OP_PARM_dq: PUT_SZ("oword "); break; \
750	case OP_PARM_qq: PUT_SZ("yword "); break; \
751	case OP_PARM_p: break; /* see PUT_FAR */ \
752	case OP_PARM_s: if (pParam->fUse & DISUSE_REG_FP) PUT_SZ("tword "); break; /* ?? */ \
753	case OP_PARM_z: break; \
754	case OP_PARM_NONE: \
755	if ( OP_PARM_VTYPE(pParam->fParam) == OP_PARM_M \
756	&& ((pParam->fUse & DISUSE_REG_FP) \|\| pOp->uOpcode == OP_FLD)) \
757	PUT_SZ("tword "); \
758	break; \
759	default: break; /no pointer type specified/necessary/ \
760	} \
761	} while (0)
762	static const char s_szSegPrefix[6][4] = { "es:", "cs:", "ss:", "ds:", "fs:", "gs:" };
763	#define PUT_SEGMENT_OVERRIDE() \
764	do { \
765	if (pDis->fPrefix & DISPREFIX_SEG) \
766	PUT_STR(s_szSegPrefix[pDis->idxSegPrefix], 3); \
767	} while (0)
768
769
770	/*
771	* Segment prefixing for instructions that doesn't do memory access.
772	*/
773	if ( (pDis->fPrefix & DISPREFIX_SEG)
774	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
775	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
776	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse))
777	{
778	PUT_STR(s_szSegPrefix[pDis->idxSegPrefix], 2);
779	PUT_C(' ');
780	}
781
782
783	/*
784	* The formatting loop.
785	*/
786	RTINTPTR off;
787	char szSymbol[128];
788	char ch;
789	while ((ch = *pszFmt++) != '\0')
790	{
791	if (ch == '%')
792	{
793	ch = *pszFmt++;
794	switch (ch)
795	{
796	/*
797	* ModRM - Register only.
798	*/
799	case 'C': /* Control register (ParseModRM / UseModRM). */
800	case 'D': /* Debug register (ParseModRM / UseModRM). */
801	case 'G': /* ModRM selects general register (ParseModRM / UseModRM). */
802	case 'S': /* ModRM byte selects a segment register (ParseModRM / UseModRM). */
803	case 'T': /* ModRM byte selects a test register (ParseModRM / UseModRM). */
804	case 'V': /* ModRM byte selects an XMM/SSE register (ParseModRM / UseModRM). */
805	case 'P': /* ModRM byte selects MMX register (ParseModRM / UseModRM). */
806	case 'H': /* The VEX.vvvv field of the VEX prefix selects a XMM/YMM register. */
807	case 'L': /* The upper 4 bits of the 8-bit immediate selects a XMM/YMM register. */
808	{
809	pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
810	Assert(!(pParam->fUse & (DISUSE_INDEX \| DISUSE_SCALE) /* No SIB here... */));
811	Assert(!(pParam->fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32)));
812
813	size_t cchReg;
814	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
815	PUT_STR(pszReg, cchReg);
816	break;
817	}
818
819	/*
820	* ModRM - Register or memory.
821	*/
822	case 'E': /* ModRM specifies parameter (ParseModRM / UseModRM / UseSIB). */
823	case 'Q': /* ModRM byte selects MMX register or memory address (ParseModRM / UseModRM). */
824	case 'R': /* ModRM byte may only refer to a general register (ParseModRM / UseModRM). */
825	case 'W': /* ModRM byte selects an XMM/SSE register or a memory address (ParseModRM / UseModRM). */
826	case 'M': /* ModRM may only refer to memory (ParseModRM / UseModRM). */
827	{
828	pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
829
830	PUT_FAR();
831	uint32_t const fUse = pParam->fUse;
832	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
833	{
834	/* Work around mov seg,[mem16] and mov [mem16],seg as these always make a 16-bit mem
835	while the register variants deals with 16, 32 & 64 in the normal fashion. */
836	if ( pParam->fParam != OP_PARM_Ev
837	\|\| pOp->uOpcode != OP_MOV
838	\|\| ( pOp->fParam1 != OP_PARM_Sw
839	&& pOp->fParam2 != OP_PARM_Sw))
840	PUT_SIZE_OVERRIDE();
841	PUT_C('[');
842	}
843	if ( (fFlags & DIS_FMT_FLAGS_STRICT)
844	&& (fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32)))
845	{
846	if ( (fUse & DISUSE_DISPLACEMENT8)
847	&& !pParam->uDisp.i8)
848	PUT_SZ("byte ");
849	else if ( (fUse & DISUSE_DISPLACEMENT16)
850	&& (int8_t)pParam->uDisp.i16 == (int16_t)pParam->uDisp.i16)
851	PUT_SZ("word ");
852	else if ( (fUse & DISUSE_DISPLACEMENT32)
853	&& (int16_t)pParam->uDisp.i32 == (int32_t)pParam->uDisp.i32) //??
854	PUT_SZ("dword ");
855	else if ( (fUse & DISUSE_DISPLACEMENT64)
856	&& (pDis->SIB.Bits.Base != 5 \|\| pDis->ModRM.Bits.Mod != 0)
857	&& (int32_t)pParam->uDisp.i64 == (int64_t)pParam->uDisp.i64) //??
858	PUT_SZ("qword ");
859	}
860	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
861	PUT_SEGMENT_OVERRIDE();
862
863	bool fBase = (fUse & DISUSE_BASE) /* When exactly is DISUSE_BASE supposed to be set? disasmModRMReg doesn't set it. */
864	\|\| ( (fUse & ( DISUSE_REG_GEN8
865	\| DISUSE_REG_GEN16
866	\| DISUSE_REG_GEN32
867	\| DISUSE_REG_GEN64
868	\| DISUSE_REG_FP
869	\| DISUSE_REG_MMX
870	\| DISUSE_REG_XMM
871	\| DISUSE_REG_YMM
872	\| DISUSE_REG_CR
873	\| DISUSE_REG_DBG
874	\| DISUSE_REG_SEG
875	\| DISUSE_REG_TEST ))
876	&& !DISUSE_IS_EFFECTIVE_ADDR(fUse));
877	if (fBase)
878	{
879	size_t cchReg;
880	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
881	PUT_STR(pszReg, cchReg);
882	}
883
884	if (fUse & DISUSE_INDEX)
885	{
886	if (fBase)
887	PUT_C('+');
888
889	size_t cchReg;
890	const char *pszReg = disasmFormatYasmIndexReg(pDis, pParam, &cchReg);
891	PUT_STR(pszReg, cchReg);
892
893	if (fUse & DISUSE_SCALE)
894	{
895	PUT_C('*');
896	PUT_C('0' + pParam->uScale);
897	}
898	}
899	else
900	Assert(!(fUse & DISUSE_SCALE));
901
902	int64_t off2 = 0;
903	if (fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32))
904	{
905	if (fUse & DISUSE_DISPLACEMENT8)
906	off2 = pParam->uDisp.i8;
907	else if (fUse & DISUSE_DISPLACEMENT16)
908	off2 = pParam->uDisp.i16;
909	else if (fUse & (DISUSE_DISPLACEMENT32 \| DISUSE_RIPDISPLACEMENT32))
910	off2 = pParam->uDisp.i32;
911	else if (fUse & DISUSE_DISPLACEMENT64)
912	off2 = pParam->uDisp.i64;
913	else
914	{
915	AssertFailed();
916	off2 = 0;
917	}
918
919	int64_t off3 = off2;
920	if (fBase \|\| (fUse & (DISUSE_INDEX \| DISUSE_RIPDISPLACEMENT32)))
921	{
922	PUT_C(off3 >= 0 ? '+' : '-');
923	if (off3 < 0)
924	off3 = -off3;
925	}
926	if (fUse & DISUSE_DISPLACEMENT8)
927	PUT_NUM_8( off3);
928	else if (fUse & DISUSE_DISPLACEMENT16)
929	PUT_NUM_16(off3);
930	else if (fUse & DISUSE_DISPLACEMENT32)
931	PUT_NUM_32(off3);
932	else if (fUse & DISUSE_DISPLACEMENT64)
933	PUT_NUM_64(off3);
934	else
935	{
936	PUT_NUM_32(off3);
937	PUT_SZ(" wrt rip (");
938	off2 += pDis->uInstrAddr + pDis->cbInstr;
939	PUT_NUM_64(off2);
940	if (pfnGetSymbol)
941	PUT_SYMBOL((pDis->fPrefix & DISPREFIX_SEG)
942	? DIS_FMT_SEL_FROM_REG(pDis->idxSegPrefix)
943	: DIS_FMT_SEL_FROM_REG(DISSELREG_DS),
944	pDis->uAddrMode == DISCPUMODE_64BIT
945	? (uint64_t)off2
946	: pDis->uAddrMode == DISCPUMODE_32BIT
947	? (uint32_t)off2
948	: (uint16_t)off2,
949	" = ",
950	')');
951	else
952	PUT_C(')');
953	}
954	}
955
956	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
957	{
958	if (pfnGetSymbol && !fBase && !(fUse & (DISUSE_INDEX \| DISUSE_RIPDISPLACEMENT32)) && off2 != 0)
959	PUT_SYMBOL((pDis->fPrefix & DISPREFIX_SEG)
960	? DIS_FMT_SEL_FROM_REG(pDis->idxSegPrefix)
961	: DIS_FMT_SEL_FROM_REG(DISSELREG_DS),
962	pDis->uAddrMode == DISCPUMODE_64BIT
963	? (uint64_t)off2
964	: pDis->uAddrMode == DISCPUMODE_32BIT
965	? (uint32_t)off2
966	: (uint16_t)off2,
967	" (=",
968	')');
969	PUT_C(']');
970	}
971	break;
972	}
973
974	case 'F': /* Eflags register (0 - popf/pushf only, avoided in adjustments above). */
975	AssertFailed();
976	break;
977
978	case 'I': /* Immediate data (ParseImmByte, ParseImmByteSX, ParseImmV, ParseImmUshort, ParseImmZ). */
979	Assert(pszFmt == 'b' \|\| pszFmt == 'v' \|\| pszFmt == 'w' \|\| pszFmt == 'z'); pszFmt++;
980	switch (pParam->fUse & ( DISUSE_IMMEDIATE8 \| DISUSE_IMMEDIATE16 \| DISUSE_IMMEDIATE32 \| DISUSE_IMMEDIATE64
981	\| DISUSE_IMMEDIATE16_SX8 \| DISUSE_IMMEDIATE32_SX8 \| DISUSE_IMMEDIATE64_SX8))
982	{
983	case DISUSE_IMMEDIATE8:
984	if ( (fFlags & DIS_FMT_FLAGS_STRICT)
985	&& ( (pOp->fParam1 >= OP_PARM_REG_GEN8_START && pOp->fParam1 <= OP_PARM_REG_GEN8_END)
986	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN8_START && pOp->fParam2 <= OP_PARM_REG_GEN8_END))
987	)
988	PUT_SZ("strict byte ");
989	PUT_NUM_8(pParam->uValue);
990	break;
991
992	case DISUSE_IMMEDIATE16:
993	if ( pDis->uCpuMode != pDis->uOpMode
994	\|\| ( (fFlags & DIS_FMT_FLAGS_STRICT)
995	&& ( (int8_t)pParam->uValue == (int16_t)pParam->uValue
996	\|\| (pOp->fParam1 >= OP_PARM_REG_GEN16_START && pOp->fParam1 <= OP_PARM_REG_GEN16_END)
997	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN16_START && pOp->fParam2 <= OP_PARM_REG_GEN16_END))
998	)
999	)
1000	{
1001	if (OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_b)
1002	PUT_SZ_STRICT("strict byte ", "byte ");
1003	else if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_v
1004	\|\| OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_z)
1005	PUT_SZ_STRICT("strict word ", "word ");
1006	}
1007	PUT_NUM_16(pParam->uValue);
1008	break;
1009
1010	case DISUSE_IMMEDIATE16_SX8:
1011	if ( !(pDis->fPrefix & DISPREFIX_OPSIZE)
1012	\|\| pDis->pCurInstr->uOpcode != OP_PUSH)
1013	PUT_SZ_STRICT("strict byte ", "byte ");
1014	else
1015	PUT_SZ("word ");
1016	PUT_NUM_16(pParam->uValue);
1017	break;
1018
1019	case DISUSE_IMMEDIATE32:
1020	if ( pDis->uOpMode != (pDis->uCpuMode == DISCPUMODE_16BIT ? DISCPUMODE_16BIT : DISCPUMODE_32BIT) /* not perfect */
1021	\|\| ( (fFlags & DIS_FMT_FLAGS_STRICT)
1022	&& ( (int8_t)pParam->uValue == (int32_t)pParam->uValue
1023	\|\| (pOp->fParam1 >= OP_PARM_REG_GEN32_START && pOp->fParam1 <= OP_PARM_REG_GEN32_END)
1024	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN32_START && pOp->fParam2 <= OP_PARM_REG_GEN32_END))
1025	)
1026	)
1027	{
1028	if (OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_b)
1029	PUT_SZ_STRICT("strict byte ", "byte ");
1030	else if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_v
1031	\|\| OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_z)
1032	PUT_SZ_STRICT("strict dword ", "dword ");
1033	}
1034	PUT_NUM_32(pParam->uValue);
1035	if (pDis->uCpuMode == DISCPUMODE_32BIT)
1036	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uValue, " (=", ')');
1037	break;
1038
1039	case DISUSE_IMMEDIATE32_SX8:
1040	if ( !(pDis->fPrefix & DISPREFIX_OPSIZE)
1041	\|\| pDis->pCurInstr->uOpcode != OP_PUSH)
1042	PUT_SZ_STRICT("strict byte ", "byte ");
1043	else
1044	PUT_SZ("dword ");
1045	PUT_NUM_32(pParam->uValue);
1046	break;
1047
1048	case DISUSE_IMMEDIATE64_SX8:
1049	if ( !(pDis->fPrefix & DISPREFIX_OPSIZE)
1050	\|\| pDis->pCurInstr->uOpcode != OP_PUSH)
1051	PUT_SZ_STRICT("strict byte ", "byte ");
1052	else
1053	PUT_SZ("qword ");
1054	PUT_NUM_64(pParam->uValue);
1055	break;
1056
1057	case DISUSE_IMMEDIATE64:
1058	PUT_NUM_64(pParam->uValue);
1059	break;
1060
1061	default:
1062	AssertFailed();
1063	break;
1064	}
1065	break;
1066
1067	case 'J': /* Relative jump offset (ParseImmBRel + ParseImmVRel). */
1068	{
1069	int32_t offDisplacement;
1070	Assert(iParam == 1);
1071	bool fPrefix = (fFlags & DIS_FMT_FLAGS_STRICT)
1072	&& pOp->uOpcode != OP_CALL
1073	&& pOp->uOpcode != OP_LOOP
1074	&& pOp->uOpcode != OP_LOOPE
1075	&& pOp->uOpcode != OP_LOOPNE
1076	&& pOp->uOpcode != OP_JECXZ;
1077	if (pOp->uOpcode == OP_CALL)
1078	fFlags &= ~DIS_FMT_FLAGS_RELATIVE_BRANCH;
1079
1080	if (pParam->fUse & DISUSE_IMMEDIATE8_REL)
1081	{
1082	if (fPrefix)
1083	PUT_SZ("short ");
1084	offDisplacement = (int8_t)pParam->uValue;
1085	Assert(*pszFmt == 'b'); pszFmt++;
1086
1087	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1088	PUT_NUM_S8(offDisplacement);
1089	}
1090	else if (pParam->fUse & DISUSE_IMMEDIATE16_REL)
1091	{
1092	if (fPrefix)
1093	PUT_SZ("near ");
1094	offDisplacement = (int16_t)pParam->uValue;
1095	Assert(*pszFmt == 'v'); pszFmt++;
1096
1097	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1098	PUT_NUM_S16(offDisplacement);
1099	}
1100	else
1101	{
1102	if (fPrefix)
1103	PUT_SZ("near ");
1104	offDisplacement = (int32_t)pParam->uValue;
1105	Assert(pParam->fUse & (DISUSE_IMMEDIATE32_REL \| DISUSE_IMMEDIATE64_REL));
1106	Assert(*pszFmt == 'v'); pszFmt++;
1107
1108	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1109	PUT_NUM_S32(offDisplacement);
1110	}
1111	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1112	PUT_SZ(" (");
1113
1114	RTUINTPTR uTrgAddr = pDis->uInstrAddr + pDis->cbInstr + offDisplacement;
1115	if (pDis->uCpuMode == DISCPUMODE_16BIT)
1116	PUT_NUM_16(uTrgAddr);
1117	else if (pDis->uCpuMode == DISCPUMODE_32BIT)
1118	PUT_NUM_32(uTrgAddr);
1119	else
1120	PUT_NUM_64(uTrgAddr);
1121
1122	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1123	{
1124	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " = ", ' ');
1125	PUT_C(')');
1126	}
1127	else
1128	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " (", ')');
1129	break;
1130	}
1131
1132	case 'A': /* Direct (jump/call) address (ParseImmAddr). */
1133	{
1134	Assert(*pszFmt == 'p'); pszFmt++;
1135	PUT_FAR();
1136	PUT_SIZE_OVERRIDE();
1137	PUT_SEGMENT_OVERRIDE();
1138	off = 0;
1139	int rc = VERR_SYMBOL_NOT_FOUND;
1140	switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 \| DISUSE_IMMEDIATE_ADDR_16_32 \| DISUSE_DISPLACEMENT64 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT16))
1141	{
1142	case DISUSE_IMMEDIATE_ADDR_16_16:
1143	PUT_NUM_16(pParam->uValue >> 16);
1144	PUT_C(':');
1145	PUT_NUM_16(pParam->uValue);
1146	if (pfnGetSymbol)
1147	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1148	break;
1149	case DISUSE_IMMEDIATE_ADDR_16_32:
1150	PUT_NUM_16(pParam->uValue >> 32);
1151	PUT_C(':');
1152	PUT_NUM_32(pParam->uValue);
1153	if (pfnGetSymbol)
1154	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1155	break;
1156	case DISUSE_DISPLACEMENT16:
1157	PUT_NUM_16(pParam->uValue);
1158	if (pfnGetSymbol)
1159	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1160	break;
1161	case DISUSE_DISPLACEMENT32:
1162	PUT_NUM_32(pParam->uValue);
1163	if (pfnGetSymbol)
1164	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1165	break;
1166	case DISUSE_DISPLACEMENT64:
1167	PUT_NUM_64(pParam->uValue);
1168	if (pfnGetSymbol)
1169	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint64_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1170	break;
1171	default:
1172	AssertFailed();
1173	break;
1174	}
1175
1176	PUT_SYMBOL_TWO(rc, " [", ']');
1177	break;
1178	}
1179
1180	case 'O': /* No ModRM byte (ParseImmAddr). */
1181	{
1182	Assert(pszFmt == 'b' \|\| pszFmt == 'v'); pszFmt++;
1183	PUT_FAR();
1184	PUT_SIZE_OVERRIDE();
1185	PUT_C('[');
1186	PUT_SEGMENT_OVERRIDE();
1187	off = 0;
1188	int rc = VERR_SYMBOL_NOT_FOUND;
1189	switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 \| DISUSE_IMMEDIATE_ADDR_16_32 \| DISUSE_DISPLACEMENT64 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT16))
1190	{
1191	case DISUSE_IMMEDIATE_ADDR_16_16:
1192	PUT_NUM_16(pParam->uValue >> 16);
1193	PUT_C(':');
1194	PUT_NUM_16(pParam->uValue);
1195	if (pfnGetSymbol)
1196	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1197	break;
1198	case DISUSE_IMMEDIATE_ADDR_16_32:
1199	PUT_NUM_16(pParam->uValue >> 32);
1200	PUT_C(':');
1201	PUT_NUM_32(pParam->uValue);
1202	if (pfnGetSymbol)
1203	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1204	break;
1205	case DISUSE_DISPLACEMENT16:
1206	PUT_NUM_16(pParam->uDisp.i16);
1207	if (pfnGetSymbol)
1208	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u16, szSymbol, sizeof(szSymbol), &off, pvUser);
1209	break;
1210	case DISUSE_DISPLACEMENT32:
1211	PUT_NUM_32(pParam->uDisp.i32);
1212	if (pfnGetSymbol)
1213	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u32, szSymbol, sizeof(szSymbol), &off, pvUser);
1214	break;
1215	case DISUSE_DISPLACEMENT64:
1216	PUT_NUM_64(pParam->uDisp.i64);
1217	if (pfnGetSymbol)
1218	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u64, szSymbol, sizeof(szSymbol), &off, pvUser);
1219	break;
1220	default:
1221	AssertFailed();
1222	break;
1223	}
1224	PUT_C(']');
1225
1226	PUT_SYMBOL_TWO(rc, " (", ')');
1227	break;
1228	}
1229
1230	case 'X': /* DS:SI (ParseXb, ParseXv). */
1231	case 'Y': /* ES:DI (ParseYb, ParseYv). */
1232	{
1233	Assert(pszFmt == 'b' \|\| pszFmt == 'v'); pszFmt++;
1234	PUT_FAR();
1235	PUT_SIZE_OVERRIDE();
1236	PUT_C('[');
1237	if (pParam->fUse & DISUSE_POINTER_DS_BASED)
1238	PUT_SZ("ds:");
1239	else
1240	PUT_SZ("es:");
1241
1242	size_t cchReg;
1243	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
1244	PUT_STR(pszReg, cchReg);
1245	PUT_C(']');
1246	break;
1247	}
1248
1249	case 'e': /* Register based on operand size (e.g. %eAX, %eAH) (ParseFixedReg). */
1250	{
1251	Assert(RT_C_IS_ALPHA(pszFmt[0]) && RT_C_IS_ALPHA(pszFmt[1]) && !RT_C_IS_ALPHA(pszFmt[2]));
1252	pszFmt += 2;
1253	size_t cchReg;
1254	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
1255	PUT_STR(pszReg, cchReg);
1256	break;
1257	}
1258
1259	default:
1260	AssertMsgFailed(("%c%s!\n", ch, pszFmt));
1261	break;
1262	}
1263	AssertMsg(pszFmt == ',' \|\| pszFmt == '\0', ("%c%s\n", ch, pszFmt));
1264	}
1265	else
1266	{
1267	PUT_C(ch);
1268	if (ch == ',')
1269	{
1270	Assert(*pszFmt != ' ');
1271	PUT_C(' ');
1272	switch (++iParam)
1273	{
1274	case 2: pParam = &pDis->Param2; break;
1275	case 3: pParam = &pDis->Param3; break;
1276	case 4: pParam = &pDis->Param4; break;
1277	default: pParam = NULL; break;
1278	}
1279	}
1280	}
1281	} /* while more to format */
1282	}
1283
1284	/*
1285	* Any additional output to the right of the instruction?
1286	*/
1287	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
1288	{
1289	/* some up front padding. */
1290	size_t cchPadding = cchOutput - offInstruction;
1291	cchPadding = cchPadding + 1 >= 42 ? 1 : 42 - cchPadding;
1292	PUT_STR(g_szSpaces, cchPadding);
1293
1294	/* comment? */
1295	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
1296	PUT_SZ(";");
1297
1298	/*
1299	* The address?
1300	*/
1301	if (fFlags & DIS_FMT_FLAGS_ADDR_RIGHT)
1302	{
1303	PUT_C(' ');
1304	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
1305	if (pDis->uInstrAddr >= _4G)
1306	PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
1307	#endif
1308	PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
1309	}
1310
1311	/*
1312	* Opcode bytes?
1313	*/
1314	if (fFlags & DIS_FMT_FLAGS_BYTES_RIGHT)
1315	{
1316	PUT_C(' ');
1317	size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
1318	cchOutput += cchTmp;
1319	if (cchTmp >= cchDst)
1320	cchTmp = cchDst - (cchDst != 0);
1321	cchDst -= cchTmp;
1322	pszDst += cchTmp;
1323	}
1324	}
1325
1326	/*
1327	* Terminate it - on overflow we'll have reserved one byte for this.
1328	*/
1329	if (cchDst > 0)
1330	*pszDst = '\0';
1331	else
1332	Assert(!cchBuf);
1333
1334	/* clean up macros */
1335	#undef PUT_PSZ
1336	#undef PUT_SZ
1337	#undef PUT_STR
1338	#undef PUT_C
1339	return cchOutput;
1340	}
1341
1342
1343	/**
1344	* Formats the current instruction in Yasm (/ Nasm) style.
1345	*
1346	* This is a simplified version of DISFormatYasmEx() provided for your convenience.
1347	*
1348	*
1349	* @returns The number of output characters. If this is >= cchBuf, then the content
1350	* of pszBuf will be truncated.
1351	* @param pDis Pointer to the disassembler state.
1352	* @param pszBuf The output buffer.
1353	* @param cchBuf The size of the output buffer.
1354	*/
1355	DISDECL(size_t) DISFormatYasm(PCDISSTATE pDis, char *pszBuf, size_t cchBuf)
1356	{
1357	return DISFormatYasmEx(pDis, pszBuf, cchBuf, 0 /* fFlags /, NULL / pfnGetSymbol /, NULL / pvUser */);
1358	}
1359
1360
1361	/**
1362	* Checks if the encoding of the given disassembled instruction is something we
1363	* can never get YASM to produce.
1364	*
1365	* @returns true if it's odd, false if it isn't.
1366	* @param pDis The disassembler output. The byte fetcher callback will
1367	* be used if present as we might need to fetch opcode
1368	* bytes.
1369	*/
1370	DISDECL(bool) DISFormatYasmIsOddEncoding(PDISSTATE pDis)
1371	{
1372	/*
1373	* Mod rm + SIB: Check for duplicate EBP encodings that yasm won't use for very good reasons.
1374	*/
1375	if ( pDis->uAddrMode != DISCPUMODE_16BIT /// @todo correct?
1376	&& pDis->ModRM.Bits.Rm == 4
1377	&& pDis->ModRM.Bits.Mod != 3)
1378	{
1379	/* No scaled index SIB (index=4), except for ESP. */
1380	if ( pDis->SIB.Bits.Index == 4
1381	&& pDis->SIB.Bits.Base != 4)
1382	return true;
1383
1384	/* EBP + displacement */
1385	if ( pDis->ModRM.Bits.Mod != 0
1386	&& pDis->SIB.Bits.Base == 5
1387	&& pDis->SIB.Bits.Scale == 0)
1388	return true;
1389	}
1390
1391	/*
1392	* Seems to be an instruction alias here, but I cannot find any docs on it... hrmpf!
1393	*/
1394	if ( pDis->pCurInstr->uOpcode == OP_SHL
1395	&& pDis->ModRM.Bits.Reg == 6)
1396	return true;
1397
1398	/*
1399	* Check for multiple prefixes of the same kind.
1400	*/
1401	uint8_t off1stSeg = UINT8_MAX;
1402	uint8_t offOpSize = UINT8_MAX;
1403	uint8_t offAddrSize = UINT8_MAX;
1404	uint32_t fPrefixes = 0;
1405	for (uint32_t offOpcode = 0; offOpcode < RT_ELEMENTS(pDis->abInstr); offOpcode++)
1406	{
1407	uint32_t f;
1408	switch (pDis->abInstr[offOpcode])
1409	{
1410	case 0xf0:
1411	f = DISPREFIX_LOCK;
1412	break;
1413
1414	case 0xf2:
1415	case 0xf3:
1416	f = DISPREFIX_REP; /* yes, both */
1417	break;
1418
1419	case 0x2e:
1420	case 0x3e:
1421	case 0x26:
1422	case 0x36:
1423	case 0x64:
1424	case 0x65:
1425	if (off1stSeg == UINT8_MAX)
1426	off1stSeg = offOpcode;
1427	f = DISPREFIX_SEG;
1428	break;
1429
1430	case 0x66:
1431	if (offOpSize == UINT8_MAX)
1432	offOpSize = offOpcode;
1433	f = DISPREFIX_OPSIZE;
1434	break;
1435
1436	case 0x67:
1437	if (offAddrSize == UINT8_MAX)
1438	offAddrSize = offOpcode;
1439	f = DISPREFIX_ADDRSIZE;
1440	break;
1441
1442	case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
1443	case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
1444	f = pDis->uCpuMode == DISCPUMODE_64BIT ? DISPREFIX_REX : 0;
1445	break;
1446
1447	default:
1448	f = 0;
1449	break;
1450	}
1451	if (!f)
1452	break; /* done */
1453	if (fPrefixes & f)
1454	return true;
1455	fPrefixes \|= f;
1456	}
1457
1458	/* segment overrides are fun */
1459	if (fPrefixes & DISPREFIX_SEG)
1460	{
1461	/* no effective address which it may apply to. */
1462	Assert((pDis->fPrefix & DISPREFIX_SEG) \|\| pDis->uCpuMode == DISCPUMODE_64BIT);
1463	if ( !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
1464	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
1465	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse))
1466	return true;
1467
1468	/* Yasm puts the segment prefixes before the operand prefix with no
1469	way of overriding it. */
1470	if (offOpSize < off1stSeg)
1471	return true;
1472	}
1473
1474	/* fixed register + addr override doesn't go down all that well. */
1475	if (fPrefixes & DISPREFIX_ADDRSIZE)
1476	{
1477	Assert(pDis->fPrefix & DISPREFIX_ADDRSIZE);
1478	if ( pDis->pCurInstr->fParam3 == OP_PARM_NONE
1479	&& pDis->pCurInstr->fParam2 == OP_PARM_NONE
1480	&& ( pDis->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
1481	&& pDis->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END))
1482	return true;
1483	}
1484
1485	/* Almost all prefixes are bad for jumps. */
1486	if (fPrefixes)
1487	{
1488	switch (pDis->pCurInstr->uOpcode)
1489	{
1490	/* nop w/ prefix(es). */
1491	case OP_NOP:
1492	return true;
1493
1494	case OP_JMP:
1495	if ( pDis->pCurInstr->fParam1 != OP_PARM_Jb
1496	&& pDis->pCurInstr->fParam1 != OP_PARM_Jv)
1497	break;
1498	RT_FALL_THRU();
1499	case OP_JO:
1500	case OP_JNO:
1501	case OP_JC:
1502	case OP_JNC:
1503	case OP_JE:
1504	case OP_JNE:
1505	case OP_JBE:
1506	case OP_JNBE:
1507	case OP_JS:
1508	case OP_JNS:
1509	case OP_JP:
1510	case OP_JNP:
1511	case OP_JL:
1512	case OP_JNL:
1513	case OP_JLE:
1514	case OP_JNLE:
1515	/** @todo branch hinting 0x2e/0x3e... */
1516	return true;
1517	}
1518
1519	}
1520
1521	/* All but the segment prefix is bad news for push/pop. */
1522	if (fPrefixes & ~DISPREFIX_SEG)
1523	{
1524	switch (pDis->pCurInstr->uOpcode)
1525	{
1526	case OP_POP:
1527	case OP_PUSH:
1528	if ( pDis->pCurInstr->fParam1 >= OP_PARM_REG_SEG_START
1529	&& pDis->pCurInstr->fParam1 <= OP_PARM_REG_SEG_END)
1530	return true;
1531	if ( (fPrefixes & ~DISPREFIX_OPSIZE)
1532	&& pDis->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
1533	&& pDis->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END)
1534	return true;
1535	break;
1536
1537	case OP_POPA:
1538	case OP_POPF:
1539	case OP_PUSHA:
1540	case OP_PUSHF:
1541	if (fPrefixes & ~DISPREFIX_OPSIZE)
1542	return true;
1543	break;
1544	}
1545	}
1546
1547	/* Implicit 8-bit register instructions doesn't mix with operand size. */
1548	if ( (fPrefixes & DISPREFIX_OPSIZE)
1549	&& ( ( pDis->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
1550	&& pDis->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
1551	\|\| ( pDis->pCurInstr->fParam2 == OP_PARM_Gb /* r8 */
1552	&& pDis->pCurInstr->fParam1 == OP_PARM_Eb /* r8/mem8 */))
1553	)
1554	{
1555	switch (pDis->pCurInstr->uOpcode)
1556	{
1557	case OP_ADD:
1558	case OP_OR:
1559	case OP_ADC:
1560	case OP_SBB:
1561	case OP_AND:
1562	case OP_SUB:
1563	case OP_XOR:
1564	case OP_CMP:
1565	return true;
1566	default:
1567	break;
1568	}
1569	}
1570
1571	/* Instructions taking no address or operand which thus may be annoyingly
1572	difficult to format for yasm. */
1573	if (fPrefixes)
1574	{
1575	switch (pDis->pCurInstr->uOpcode)
1576	{
1577	case OP_STI:
1578	case OP_STC:
1579	case OP_CLI:
1580	case OP_CLD:
1581	case OP_CLC:
1582	case OP_INT:
1583	case OP_INT3:
1584	case OP_INTO:
1585	case OP_HLT:
1586	/** @todo Many more to can be added here. */
1587	return true;
1588	default:
1589	break;
1590	}
1591	}
1592
1593	/* FPU and other instructions that ignores operand size override. */
1594	if (fPrefixes & DISPREFIX_OPSIZE)
1595	{
1596	switch (pDis->pCurInstr->uOpcode)
1597	{
1598	/* FPU: */
1599	case OP_FIADD:
1600	case OP_FIMUL:
1601	case OP_FISUB:
1602	case OP_FISUBR:
1603	case OP_FIDIV:
1604	case OP_FIDIVR:
1605	/** @todo there are many more. */
1606	return true;
1607
1608	case OP_MOV:
1609	/** @todo could be that we're not disassembling these correctly. */
1610	if (pDis->pCurInstr->fParam1 == OP_PARM_Sw)
1611	return true;
1612	/** @todo what about the other way? */
1613	break;
1614
1615	default:
1616	break;
1617	}
1618	}
1619
1620
1621	/*
1622	* Check for the version of xyz reg,reg instruction that the assembler doesn't use.
1623	*
1624	* For example:
1625	* expected: 1aee sbb ch, dh ; SBB r8, r/m8
1626	* yasm: 18F5 sbb ch, dh ; SBB r/m8, r8
1627	*/
1628	if (pDis->ModRM.Bits.Mod == 3 /* reg,reg */)
1629	{
1630	switch (pDis->pCurInstr->uOpcode)
1631	{
1632	case OP_ADD:
1633	case OP_OR:
1634	case OP_ADC:
1635	case OP_SBB:
1636	case OP_AND:
1637	case OP_SUB:
1638	case OP_XOR:
1639	case OP_CMP:
1640	if ( ( pDis->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
1641	&& pDis->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
1642	\|\| ( pDis->pCurInstr->fParam1 == OP_PARM_Gv /* rX */
1643	&& pDis->pCurInstr->fParam2 == OP_PARM_Ev /* rX/memX */))
1644	return true;
1645
1646	/* 82 (see table A-6). */
1647	if (pDis->bOpCode == 0x82)
1648	return true;
1649	break;
1650
1651	/* ff /0, fe /0, ff /1, fe /0 */
1652	case OP_DEC:
1653	case OP_INC:
1654	return true;
1655
1656	case OP_POP:
1657	case OP_PUSH:
1658	Assert(pDis->bOpCode == 0x8f);
1659	return true;
1660
1661	case OP_MOV:
1662	if ( pDis->bOpCode == 0x8a
1663	\|\| pDis->bOpCode == 0x8b)
1664	return true;
1665	break;
1666
1667	default:
1668	break;
1669	}
1670	}
1671
1672	/* shl eax,1 will be assembled to the form without the immediate byte. */
1673	if ( pDis->pCurInstr->fParam2 == OP_PARM_Ib
1674	&& (uint8_t)pDis->Param2.uValue == 1)
1675	{
1676	switch (pDis->pCurInstr->uOpcode)
1677	{
1678	case OP_SHL:
1679	case OP_SHR:
1680	case OP_SAR:
1681	case OP_RCL:
1682	case OP_RCR:
1683	case OP_ROL:
1684	case OP_ROR:
1685	return true;
1686	}
1687	}
1688
1689	/* And some more - see table A-6. */
1690	if (pDis->bOpCode == 0x82)
1691	{
1692	switch (pDis->pCurInstr->uOpcode)
1693	{
1694	case OP_ADD:
1695	case OP_OR:
1696	case OP_ADC:
1697	case OP_SBB:
1698	case OP_AND:
1699	case OP_SUB:
1700	case OP_XOR:
1701	case OP_CMP:
1702	return true;
1703	break;
1704	}
1705	}
1706
1707
1708	/* check for REX.X = 1 without SIB. */
1709
1710	/* Yasm encodes setnbe al with /2 instead of /0 like the AMD manual
1711	says (intel doesn't appear to care). */
1712	switch (pDis->pCurInstr->uOpcode)
1713	{
1714	case OP_SETO:
1715	case OP_SETNO:
1716	case OP_SETC:
1717	case OP_SETNC:
1718	case OP_SETE:
1719	case OP_SETNE:
1720	case OP_SETBE:
1721	case OP_SETNBE:
1722	case OP_SETS:
1723	case OP_SETNS:
1724	case OP_SETP:
1725	case OP_SETNP:
1726	case OP_SETL:
1727	case OP_SETNL:
1728	case OP_SETLE:
1729	case OP_SETNLE:
1730	AssertMsg(pDis->bOpCode >= 0x90 && pDis->bOpCode <= 0x9f, ("%#x\n", pDis->bOpCode));
1731	if (pDis->ModRM.Bits.Reg != 2)
1732	return true;
1733	break;
1734	}
1735
1736	/*
1737	* The MOVZX reg32,mem16 instruction without an operand size prefix
1738	* doesn't quite make sense...
1739	*/
1740	if ( pDis->pCurInstr->uOpcode == OP_MOVZX
1741	&& pDis->bOpCode == 0xB7
1742	&& (pDis->uCpuMode == DISCPUMODE_16BIT) != !!(fPrefixes & DISPREFIX_OPSIZE))
1743	return true;
1744
1745	return false;
1746	}
1747

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source: vbox/trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp@ 78412

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