DisasmFormatYasm.cpp@ 41737

Last change on this file since 41737 was 41737, checked in by vboxsync, 12 years ago
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1	/* $Id: DisasmFormatYasm.cpp 41737 2012-06-15 01:01:49Z vboxsync $ */
2	/** @file
3	* VBox Disassembler - Yasm(/Nasm) Style Formatter.
4	*/
5
6	/*
7	* Copyright (C) 2008-2012 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#include <VBox/dis.h>
23	#include "DisasmInternal.h"
24	#include <iprt/string.h>
25	#include <iprt/assert.h>
26	#include <iprt/ctype.h>
27
28
29	/*******************************************************************************
30	* Global Variables *
31	*******************************************************************************/
32	static const char g_szSpaces[] =
33	" ";
34	static const char g_aszYasmRegGen8[20][5] =
35	{
36	"al\0\0", "cl\0\0", "dl\0\0", "bl\0\0", "ah\0\0", "ch\0\0", "dh\0\0", "bh\0\0", "r8b\0", "r9b\0", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b", "spl\0", "bpl\0", "sil\0", "dil\0"
37	};
38	static const char g_aszYasmRegGen16[16][5] =
39	{
40	"ax\0\0", "cx\0\0", "dx\0\0", "bx\0\0", "sp\0\0", "bp\0\0", "si\0\0", "di\0\0", "r8w\0", "r9w\0", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
41	};
42	static const char g_aszYasmRegGen1616[8][6] =
43	{
44	"bx+si", "bx+di", "bp+si", "bp+di", "si\0\0\0", "di\0\0\0", "bp\0\0\0", "bx\0\0\0"
45	};
46	static const char g_aszYasmRegGen32[16][5] =
47	{
48	"eax\0", "ecx\0", "edx\0", "ebx\0", "esp\0", "ebp\0", "esi\0", "edi\0", "r8d\0", "r9d\0", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
49	};
50	static const char g_aszYasmRegGen64[16][4] =
51	{
52	"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", "r8\0", "r9\0", "r10", "r11", "r12", "r13", "r14", "r15"
53	};
54	static const char g_aszYasmRegSeg[6][3] =
55	{
56	"es", "cs", "ss", "ds", "fs", "gs"
57	};
58	static const char g_aszYasmRegFP[8][4] =
59	{
60	"st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7"
61	};
62	static const char g_aszYasmRegMMX[8][4] =
63	{
64	"mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7"
65	};
66	static const char g_aszYasmRegXMM[16][6] =
67	{
68	"xmm0\0", "xmm1\0", "xmm2\0", "xmm3\0", "xmm4\0", "xmm5\0", "xmm6\0", "xmm7\0", "xmm8\0", "xmm9\0", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
69	};
70	static const char g_aszYasmRegCRx[16][5] =
71	{
72	"cr0\0", "cr1\0", "cr2\0", "cr3\0", "cr4\0", "cr5\0", "cr6\0", "cr7\0", "cr8\0", "cr9\0", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15"
73	};
74	static const char g_aszYasmRegDRx[16][5] =
75	{
76	"dr0\0", "dr1\0", "dr2\0", "dr3\0", "dr4\0", "dr5\0", "dr6\0", "dr7\0", "dr8\0", "dr9\0", "dr10", "dr11", "dr12", "dr13", "dr14", "dr15"
77	};
78	static const char g_aszYasmRegTRx[16][5] =
79	{
80	"tr0\0", "tr1\0", "tr2\0", "tr3\0", "tr4\0", "tr5\0", "tr6\0", "tr7\0", "tr8\0", "tr9\0", "tr10", "tr11", "tr12", "tr13", "tr14", "tr15"
81	};
82
83
84
85	/**
86	* Gets the base register name for the given parameter.
87	*
88	* @returns Pointer to the register name.
89	* @param pCpu The disassembler cpu state.
90	* @param pParam The parameter.
91	* @param pcchReg Where to store the length of the name.
92	*/
93	static const char disasmFormatYasmBaseReg(PCDISCPUSTATE pCpu, PCDISOPPARAM pParam, size_t pcchReg)
94	{
95	switch (pParam->fUse & ( DISUSE_REG_GEN8 \| DISUSE_REG_GEN16 \| DISUSE_REG_GEN32 \| DISUSE_REG_GEN64
96	\| DISUSE_REG_FP \| DISUSE_REG_MMX \| DISUSE_REG_XMM \| DISUSE_REG_CR
97	\| DISUSE_REG_DBG \| DISUSE_REG_SEG \| DISUSE_REG_TEST))
98
99	{
100	case DISUSE_REG_GEN8:
101	{
102	Assert(pParam->base.reg_gen < RT_ELEMENTS(g_aszYasmRegGen8));
103	const char *psz = g_aszYasmRegGen8[pParam->base.reg_gen];
104	*pcchReg = 2 + !!psz[2] + !!psz[3];
105	return psz;
106	}
107
108	case DISUSE_REG_GEN16:
109	{
110	Assert(pParam->base.reg_gen < RT_ELEMENTS(g_aszYasmRegGen16));
111	const char *psz = g_aszYasmRegGen16[pParam->base.reg_gen];
112	*pcchReg = 2 + !!psz[2] + !!psz[3];
113	return psz;
114	}
115
116	case DISUSE_REG_GEN32:
117	{
118	Assert(pParam->base.reg_gen < RT_ELEMENTS(g_aszYasmRegGen32));
119	const char *psz = g_aszYasmRegGen32[pParam->base.reg_gen];
120	*pcchReg = 2 + !!psz[2] + !!psz[3];
121	return psz;
122	}
123
124	case DISUSE_REG_GEN64:
125	{
126	Assert(pParam->base.reg_gen < RT_ELEMENTS(g_aszYasmRegGen64));
127	const char *psz = g_aszYasmRegGen64[pParam->base.reg_gen];
128	*pcchReg = 2 + !!psz[2] + !!psz[3];
129	return psz;
130	}
131
132	case DISUSE_REG_FP:
133	{
134	Assert(pParam->base.reg_fp < RT_ELEMENTS(g_aszYasmRegFP));
135	const char *psz = g_aszYasmRegFP[pParam->base.reg_fp];
136	*pcchReg = 3;
137	return psz;
138	}
139
140	case DISUSE_REG_MMX:
141	{
142	Assert(pParam->base.reg_mmx < RT_ELEMENTS(g_aszYasmRegMMX));
143	const char *psz = g_aszYasmRegMMX[pParam->base.reg_mmx];
144	*pcchReg = 3;
145	return psz;
146	}
147
148	case DISUSE_REG_XMM:
149	{
150	Assert(pParam->base.reg_xmm < RT_ELEMENTS(g_aszYasmRegXMM));
151	const char *psz = g_aszYasmRegXMM[pParam->base.reg_mmx];
152	*pcchReg = 4 + !!psz[4];
153	return psz;
154	}
155
156	case DISUSE_REG_CR:
157	{
158	Assert(pParam->base.reg_ctrl < RT_ELEMENTS(g_aszYasmRegCRx));
159	const char *psz = g_aszYasmRegCRx[pParam->base.reg_ctrl];
160	*pcchReg = 3;
161	return psz;
162	}
163
164	case DISUSE_REG_DBG:
165	{
166	Assert(pParam->base.reg_dbg < RT_ELEMENTS(g_aszYasmRegDRx));
167	const char *psz = g_aszYasmRegDRx[pParam->base.reg_dbg];
168	*pcchReg = 3;
169	return psz;
170	}
171
172	case DISUSE_REG_SEG:
173	{
174	Assert(pParam->base.reg_seg < RT_ELEMENTS(g_aszYasmRegCRx));
175	const char *psz = g_aszYasmRegSeg[pParam->base.reg_seg];
176	*pcchReg = 2;
177	return psz;
178	}
179
180	case DISUSE_REG_TEST:
181	{
182	Assert(pParam->base.reg_test < RT_ELEMENTS(g_aszYasmRegTRx));
183	const char *psz = g_aszYasmRegTRx[pParam->base.reg_test];
184	*pcchReg = 3;
185	return psz;
186	}
187
188	default:
189	AssertMsgFailed(("%#x\n", pParam->fUse));
190	*pcchReg = 3;
191	return "r??";
192	}
193	}
194
195
196	/**
197	* Gets the index register name for the given parameter.
198	*
199	* @returns The index register name.
200	* @param pCpu The disassembler cpu state.
201	* @param pParam The parameter.
202	* @param pcchReg Where to store the length of the name.
203	*/
204	static const char disasmFormatYasmIndexReg(PCDISCPUSTATE pCpu, PCDISOPPARAM pParam, size_t pcchReg)
205	{
206	switch (pCpu->uAddrMode)
207	{
208	case DISCPUMODE_16BIT:
209	{
210	Assert(pParam->index.reg_gen < RT_ELEMENTS(g_aszYasmRegGen16));
211	const char *psz = g_aszYasmRegGen16[pParam->index.reg_gen];
212	*pcchReg = 2 + !!psz[2] + !!psz[3];
213	return psz;
214	}
215
216	case DISCPUMODE_32BIT:
217	{
218	Assert(pParam->index.reg_gen < RT_ELEMENTS(g_aszYasmRegGen32));
219	const char *psz = g_aszYasmRegGen32[pParam->index.reg_gen];
220	*pcchReg = 2 + !!psz[2] + !!psz[3];
221	return psz;
222	}
223
224	case DISCPUMODE_64BIT:
225	{
226	Assert(pParam->index.reg_gen < RT_ELEMENTS(g_aszYasmRegGen64));
227	const char *psz = g_aszYasmRegGen64[pParam->index.reg_gen];
228	*pcchReg = 2 + !!psz[2] + !!psz[3];
229	return psz;
230	}
231
232	default:
233	AssertMsgFailed(("%#x %#x\n", pParam->fUse, pCpu->uAddrMode));
234	*pcchReg = 3;
235	return "r??";
236	}
237	}
238
239
240	/**
241	* Formats the current instruction in Yasm (/ Nasm) style.
242	*
243	*
244	* @returns The number of output characters. If this is >= cchBuf, then the content
245	* of pszBuf will be truncated.
246	* @param pCpu Pointer to the disassembler CPU state.
247	* @param pszBuf The output buffer.
248	* @param cchBuf The size of the output buffer.
249	* @param fFlags Format flags, see DIS_FORMAT_FLAGS_*.
250	* @param pfnGetSymbol Get symbol name for a jmp or call target address. Optional.
251	* @param pvUser User argument for pfnGetSymbol.
252	*/
253	DISDECL(size_t) DISFormatYasmEx(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags,
254	PFNDISGETSYMBOL pfnGetSymbol, void *pvUser)
255	{
256	/*
257	* Input validation and massaging.
258	*/
259	AssertPtr(pCpu);
260	AssertPtrNull(pszBuf);
261	Assert(pszBuf \|\| !cchBuf);
262	AssertPtrNull(pfnGetSymbol);
263	AssertMsg(DIS_FMT_FLAGS_IS_VALID(fFlags), ("%#x\n", fFlags));
264	if (fFlags & DIS_FMT_FLAGS_ADDR_COMMENT)
265	fFlags = (fFlags & ~DIS_FMT_FLAGS_ADDR_LEFT) \| DIS_FMT_FLAGS_ADDR_RIGHT;
266	if (fFlags & DIS_FMT_FLAGS_BYTES_COMMENT)
267	fFlags = (fFlags & ~DIS_FMT_FLAGS_BYTES_LEFT) \| DIS_FMT_FLAGS_BYTES_RIGHT;
268
269	PCDISOPCODE const pOp = pCpu->pCurInstr;
270
271	/*
272	* Output macros
273	*/
274	char *pszDst = pszBuf;
275	size_t cchDst = cchBuf;
276	size_t cchOutput = 0;
277	#define PUT_C(ch) \
278	do { \
279	cchOutput++; \
280	if (cchDst > 1) \
281	{ \
282	cchDst--; \
283	*pszDst++ = (ch); \
284	} \
285	} while (0)
286	#define PUT_STR(pszSrc, cchSrc) \
287	do { \
288	cchOutput += (cchSrc); \
289	if (cchDst > (cchSrc)) \
290	{ \
291	memcpy(pszDst, (pszSrc), (cchSrc)); \
292	pszDst += (cchSrc); \
293	cchDst -= (cchSrc); \
294	} \
295	else if (cchDst > 1) \
296	{ \
297	memcpy(pszDst, (pszSrc), cchDst - 1); \
298	pszDst += cchDst - 1; \
299	cchDst = 1; \
300	} \
301	} while (0)
302	#define PUT_SZ(sz) \
303	PUT_STR((sz), sizeof(sz) - 1)
304	#define PUT_SZ_STRICT(szStrict, szRelaxed) \
305	do { if (fFlags & DIS_FMT_FLAGS_STRICT) PUT_SZ(szStrict); else PUT_SZ(szRelaxed); } while (0)
306	#define PUT_PSZ(psz) \
307	do { const size_t cchTmp = strlen(psz); PUT_STR((psz), cchTmp); } while (0)
308	#define PUT_NUM(cch, fmt, num) \
309	do { \
310	cchOutput += (cch); \
311	if (cchDst > 1) \
312	{ \
313	const size_t cchTmp = RTStrPrintf(pszDst, cchDst, fmt, (num)); \
314	pszDst += cchTmp; \
315	cchDst -= cchTmp; \
316	Assert(cchTmp == (cch) \|\| cchDst == 1); \
317	} \
318	} while (0)
319	/** @todo add two flags for choosing between %X / %x and h / 0x. */
320	#define PUT_NUM_8(num) PUT_NUM(4, "0%02xh", (uint8_t)(num))
321	#define PUT_NUM_16(num) PUT_NUM(6, "0%04xh", (uint16_t)(num))
322	#define PUT_NUM_32(num) PUT_NUM(10, "0%08xh", (uint32_t)(num))
323	#define PUT_NUM_64(num) PUT_NUM(18, "0%016RX64h", (uint64_t)(num))
324
325	#define PUT_NUM_SIGN(cch, fmt, num, stype, utype) \
326	do { \
327	if ((stype)(num) >= 0) \
328	{ \
329	PUT_C('+'); \
330	PUT_NUM(cch, fmt, (utype)(num)); \
331	} \
332	else \
333	{ \
334	PUT_C('-'); \
335	PUT_NUM(cch, fmt, (utype)-(stype)(num)); \
336	} \
337	} while (0)
338	#define PUT_NUM_S8(num) PUT_NUM_SIGN(4, "0%02xh", num, int8_t, uint8_t)
339	#define PUT_NUM_S16(num) PUT_NUM_SIGN(6, "0%04xh", num, int16_t, uint16_t)
340	#define PUT_NUM_S32(num) PUT_NUM_SIGN(10, "0%08xh", num, int32_t, uint32_t)
341	#define PUT_NUM_S64(num) PUT_NUM_SIGN(18, "0%016RX64h", num, int64_t, uint64_t)
342
343
344	/*
345	* The address?
346	*/
347	if (fFlags & DIS_FMT_FLAGS_ADDR_LEFT)
348	{
349	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
350	if (pCpu->uInstrAddr >= _4G)
351	PUT_NUM(9, "%08x`", (uint32_t)(pCpu->uInstrAddr >> 32));
352	#endif
353	PUT_NUM(8, "%08x", (uint32_t)pCpu->uInstrAddr);
354	PUT_C(' ');
355	}
356
357	/*
358	* The opcode bytes?
359	*/
360	if (fFlags & DIS_FMT_FLAGS_BYTES_LEFT)
361	{
362	size_t cchTmp = disFormatBytes(pCpu, pszDst, cchDst, fFlags);
363	cchOutput += cchTmp;
364	if (cchDst > 1)
365	{
366	if (cchTmp <= cchDst)
367	{
368	cchDst -= cchTmp;
369	pszDst += cchTmp;
370	}
371	else
372	{
373	pszDst += cchDst - 1;
374	cchDst = 1;
375	}
376	}
377
378	/* Some padding to align the instruction. */
379	size_t cchPadding = (7 * (2 + !!(fFlags & DIS_FMT_FLAGS_BYTES_SPACED)))
380	+ !!(fFlags & DIS_FMT_FLAGS_BYTES_BRACKETS) * 2
381	+ 2;
382	cchPadding = cchTmp + 1 >= cchPadding ? 1 : cchPadding - cchTmp;
383	PUT_STR(g_szSpaces, cchPadding);
384	}
385
386
387	/*
388	* Filter out invalid opcodes first as they need special
389	* treatment. UD2 is an exception and should be handled normally.
390	*/
391	size_t const offInstruction = cchOutput;
392	if ( pOp->uOpcode == OP_INVALID
393	\|\| ( pOp->uOpcode == OP_ILLUD2
394	&& (pCpu->fPrefix & DISPREFIX_LOCK)))
395	{
396
397	}
398	else
399	{
400	/*
401	* Prefixes
402	*/
403	if (pCpu->fPrefix & DISPREFIX_LOCK)
404	PUT_SZ("lock ");
405	if(pCpu->fPrefix & DISPREFIX_REP)
406	PUT_SZ("rep ");
407	else if(pCpu->fPrefix & DISPREFIX_REPNE)
408	PUT_SZ("repne ");
409
410	/*
411	* Adjust the format string to the correct mnemonic
412	* or to avoid things the assembler cannot handle correctly.
413	*/
414	char szTmpFmt[48];
415	const char *pszFmt = pOp->pszOpcode;
416	switch (pOp->uOpcode)
417	{
418	case OP_JECXZ:
419	pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "jcxz %Jb" : pCpu->uOpMode == DISCPUMODE_32BIT ? "jecxz %Jb" : "jrcxz %Jb";
420	break;
421	case OP_PUSHF:
422	pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "pushfw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "pushfd" : "pushfq";
423	break;
424	case OP_POPF:
425	pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "popfw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "popfd" : "popfq";
426	break;
427	case OP_PUSHA:
428	pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "pushaw" : "pushad";
429	break;
430	case OP_POPA:
431	pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "popaw" : "popad";
432	break;
433	case OP_INSB:
434	pszFmt = "insb";
435	break;
436	case OP_INSWD:
437	pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "insw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "insd" : "insq";
438	break;
439	case OP_OUTSB:
440	pszFmt = "outsb";
441	break;
442	case OP_OUTSWD:
443	pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "outsw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "outsd" : "outsq";
444	break;
445	case OP_MOVSB:
446	pszFmt = "movsb";
447	break;
448	case OP_MOVSWD:
449	pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "movsw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "movsd" : "movsq";
450	break;
451	case OP_CMPSB:
452	pszFmt = "cmpsb";
453	break;
454	case OP_CMPWD:
455	pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "cmpsw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "cmpsd" : "cmpsq";
456	break;
457	case OP_SCASB:
458	pszFmt = "scasb";
459	break;
460	case OP_SCASWD:
461	pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "scasw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "scasd" : "scasq";
462	break;
463	case OP_LODSB:
464	pszFmt = "lodsb";
465	break;
466	case OP_LODSWD:
467	pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "lodsw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "lodsd" : "lodsq";
468	break;
469	case OP_STOSB:
470	pszFmt = "stosb";
471	break;
472	case OP_STOSWD:
473	pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "stosw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "stosd" : "stosq";
474	break;
475	case OP_CBW:
476	pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "cbw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "cwde" : "cdqe";
477	break;
478	case OP_CWD:
479	pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "cwd" : pCpu->uOpMode == DISCPUMODE_32BIT ? "cdq" : "cqo";
480	break;
481	case OP_SHL:
482	Assert(pszFmt[3] == '/');
483	pszFmt += 4;
484	break;
485	case OP_XLAT:
486	pszFmt = "xlatb";
487	break;
488	case OP_INT3:
489	pszFmt = "int3";
490	break;
491
492	/*
493	* Don't know how to tell yasm to generate complicated nop stuff, so 'db' it.
494	*/
495	case OP_NOP:
496	if (pCpu->bOpCode == 0x90)
497	/* fine, fine */;
498	else if (pszFmt[sizeof("nop %Ev") - 1] == '/' && pszFmt[sizeof("nop %Ev")] == 'p')
499	pszFmt = "prefetch %Eb";
500	else if (pCpu->bOpCode == 0x1f)
501	{
502	Assert(pCpu->cbInstr >= 3);
503	PUT_SZ("db 00fh, 01fh,");
504	PUT_NUM_8(pCpu->ModRM.u);
505	for (unsigned i = 3; i < pCpu->cbInstr; i++)
506	{
507	PUT_C(',');
508	PUT_NUM_8(0x90); ///@todo fixme.
509	}
510	pszFmt = "";
511	}
512	break;
513
514	default:
515	/* ST(X) -> stX (floating point) */
516	if (*pszFmt == 'f' && strchr(pszFmt, '('))
517	{
518	char *pszFmtDst = szTmpFmt;
519	char ch;
520	do
521	{
522	ch = *pszFmt++;
523	if (ch == 'S' && pszFmt[0] == 'T' && pszFmt[1] == '(')
524	{
525	*pszFmtDst++ = 's';
526	*pszFmtDst++ = 't';
527	pszFmt += 2;
528	ch = *pszFmt;
529	Assert(pszFmt[1] == ')');
530	pszFmt += 2;
531	*pszFmtDst++ = ch;
532	}
533	else
534	*pszFmtDst++ = ch;
535	} while (ch != '\0');
536	pszFmt = szTmpFmt;
537	}
538	break;
539
540	/*
541	* Horrible hacks.
542	*/
543	case OP_FLD:
544	if (pCpu->bOpCode == 0xdb) /* m80fp workaround. */
545	(int )&pCpu->param1.param &= ~0x1f; /* make it pure OP_PARM_M */
546	break;
547	case OP_LAR: /* hack w -> v, probably not correct. */
548	(int )&pCpu->param2.param &= ~0x1f;
549	(int )&pCpu->param2.param \|= OP_PARM_v;
550	break;
551	}
552
553	/*
554	* Formatting context and associated macros.
555	*/
556	PCDISOPPARAM pParam = &pCpu->param1;
557	int iParam = 1;
558
559	#define PUT_FAR() \
560	do { \
561	if ( OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_p \
562	&& pOp->uOpcode != OP_LDS /* table bugs? */ \
563	&& pOp->uOpcode != OP_LES \
564	&& pOp->uOpcode != OP_LFS \
565	&& pOp->uOpcode != OP_LGS \
566	&& pOp->uOpcode != OP_LSS ) \
567	PUT_SZ("far "); \
568	} while (0)
569	/** @todo mov ah,ch ends up with a byte 'override'... - check if this wasn't fixed. */
570	/** @todo drop the work/dword/qword override when the src/dst is a register (except for movsx/movzx). */
571	#define PUT_SIZE_OVERRIDE() \
572	do { \
573	switch (OP_PARM_VSUBTYPE(pParam->param)) \
574	{ \
575	case OP_PARM_v: \
576	switch (pCpu->uOpMode) \
577	{ \
578	case DISCPUMODE_16BIT: PUT_SZ("word "); break; \
579	case DISCPUMODE_32BIT: PUT_SZ("dword "); break; \
580	case DISCPUMODE_64BIT: PUT_SZ("qword "); break; \
581	default: break; \
582	} \
583	break; \
584	case OP_PARM_b: PUT_SZ("byte "); break; \
585	case OP_PARM_w: PUT_SZ("word "); break; \
586	case OP_PARM_d: PUT_SZ("dword "); break; \
587	case OP_PARM_q: PUT_SZ("qword "); break; \
588	case OP_PARM_dq: \
589	if (OP_PARM_VTYPE(pParam->param) != OP_PARM_W) /* these are 128 bit, pray they are all unambiguous.. */ \
590	PUT_SZ("qword "); \
591	break; \
592	case OP_PARM_p: break; /* see PUT_FAR */ \
593	case OP_PARM_s: if (pParam->fUse & DISUSE_REG_FP) PUT_SZ("tword "); break; /* ?? */ \
594	case OP_PARM_z: break; \
595	case OP_PARM_NONE: \
596	if ( OP_PARM_VTYPE(pParam->param) == OP_PARM_M \
597	&& ((pParam->fUse & DISUSE_REG_FP) \|\| pOp->uOpcode == OP_FLD)) \
598	PUT_SZ("tword "); \
599	break; \
600	default: break; /no pointer type specified/necessary/ \
601	} \
602	} while (0)
603	static const char s_szSegPrefix[6][4] = { "es:", "cs:", "ss:", "ds:", "fs:", "gs:" };
604	#define PUT_SEGMENT_OVERRIDE() \
605	do { \
606	if (pCpu->fPrefix & DISPREFIX_SEG) \
607	PUT_STR(s_szSegPrefix[pCpu->idxSegPrefix], 3); \
608	} while (0)
609
610
611	/*
612	* Segment prefixing for instructions that doesn't do memory access.
613	*/
614	if ( (pCpu->fPrefix & DISPREFIX_SEG)
615	&& !DISUSE_IS_EFFECTIVE_ADDR(pCpu->param1.fUse)
616	&& !DISUSE_IS_EFFECTIVE_ADDR(pCpu->param2.fUse)
617	&& !DISUSE_IS_EFFECTIVE_ADDR(pCpu->param3.fUse))
618	{
619	PUT_STR(s_szSegPrefix[pCpu->idxSegPrefix], 2);
620	PUT_C(' ');
621	}
622
623
624	/*
625	* The formatting loop.
626	*/
627	RTINTPTR off;
628	char szSymbol[128];
629	char ch;
630	while ((ch = *pszFmt++) != '\0')
631	{
632	if (ch == '%')
633	{
634	ch = *pszFmt++;
635	switch (ch)
636	{
637	/*
638	* ModRM - Register only.
639	*/
640	case 'C': /* Control register (ParseModRM / UseModRM). */
641	case 'D': /* Debug register (ParseModRM / UseModRM). */
642	case 'G': /* ModRM selects general register (ParseModRM / UseModRM). */
643	case 'S': /* ModRM byte selects a segment register (ParseModRM / UseModRM). */
644	case 'T': /* ModRM byte selects a test register (ParseModRM / UseModRM). */
645	case 'V': /* ModRM byte selects an XMM/SSE register (ParseModRM / UseModRM). */
646	case 'P': /* ModRM byte selects MMX register (ParseModRM / UseModRM). */
647	{
648	pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
649	Assert(!(pParam->fUse & (DISUSE_INDEX \| DISUSE_SCALE) /* No SIB here... */));
650	Assert(!(pParam->fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32)));
651
652	size_t cchReg;
653	const char *pszReg = disasmFormatYasmBaseReg(pCpu, pParam, &cchReg);
654	PUT_STR(pszReg, cchReg);
655	break;
656	}
657
658	/*
659	* ModRM - Register or memory.
660	*/
661	case 'E': /* ModRM specifies parameter (ParseModRM / UseModRM / UseSIB). */
662	case 'Q': /* ModRM byte selects MMX register or memory address (ParseModRM / UseModRM). */
663	case 'R': /* ModRM byte may only refer to a general register (ParseModRM / UseModRM). */
664	case 'W': /* ModRM byte selects an XMM/SSE register or a memory address (ParseModRM / UseModRM). */
665	case 'M': /* ModRM may only refer to memory (ParseModRM / UseModRM). */
666	{
667	pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
668
669	PUT_FAR();
670	uint32_t const fUse = pParam->fUse;
671	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
672	{
673	/* Work around mov seg,[mem16] and mov [mem16],seg as these always make a 16-bit mem
674	while the register variants deals with 16, 32 & 64 in the normal fashion. */
675	if ( pParam->param != OP_PARM_Ev
676	\|\| pOp->uOpcode != OP_MOV
677	\|\| ( pOp->param1 != OP_PARM_Sw
678	&& pOp->param2 != OP_PARM_Sw))
679	PUT_SIZE_OVERRIDE();
680	PUT_C('[');
681	}
682	if ( (fFlags & DIS_FMT_FLAGS_STRICT)
683	&& (fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32)))
684	{
685	if ( (fUse & DISUSE_DISPLACEMENT8)
686	&& !pParam->uDisp.i8)
687	PUT_SZ("byte ");
688	else if ( (fUse & DISUSE_DISPLACEMENT16)
689	&& (int8_t)pParam->uDisp.i16 == (int16_t)pParam->uDisp.i16)
690	PUT_SZ("word ");
691	else if ( (fUse & DISUSE_DISPLACEMENT32)
692	&& (int16_t)pParam->uDisp.i32 == (int32_t)pParam->uDisp.i32) //??
693	PUT_SZ("dword ");
694	else if ( (fUse & DISUSE_DISPLACEMENT64)
695	&& (pCpu->SIB.Bits.Base != 5 \|\| pCpu->ModRM.Bits.Mod != 0)
696	&& (int32_t)pParam->uDisp.i64 == (int64_t)pParam->uDisp.i64) //??
697	PUT_SZ("qword ");
698	}
699	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
700	PUT_SEGMENT_OVERRIDE();
701
702	bool fBase = (fUse & DISUSE_BASE) /* When exactly is DISUSE_BASE supposed to be set? disasmModRMReg doesn't set it. */
703	\|\| ( (fUse & ( DISUSE_REG_GEN8
704	\| DISUSE_REG_GEN16
705	\| DISUSE_REG_GEN32
706	\| DISUSE_REG_GEN64
707	\| DISUSE_REG_FP
708	\| DISUSE_REG_MMX
709	\| DISUSE_REG_XMM
710	\| DISUSE_REG_CR
711	\| DISUSE_REG_DBG
712	\| DISUSE_REG_SEG
713	\| DISUSE_REG_TEST ))
714	&& !DISUSE_IS_EFFECTIVE_ADDR(fUse));
715	if (fBase)
716	{
717	size_t cchReg;
718	const char *pszReg = disasmFormatYasmBaseReg(pCpu, pParam, &cchReg);
719	PUT_STR(pszReg, cchReg);
720	}
721
722	if (fUse & DISUSE_INDEX)
723	{
724	if (fBase)
725	PUT_C('+');
726
727	size_t cchReg;
728	const char *pszReg = disasmFormatYasmIndexReg(pCpu, pParam, &cchReg);
729	PUT_STR(pszReg, cchReg);
730
731	if (fUse & DISUSE_SCALE)
732	{
733	PUT_C('*');
734	PUT_C('0' + pParam->scale);
735	}
736	}
737	else
738	Assert(!(fUse & DISUSE_SCALE));
739
740	if (fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32))
741	{
742	int64_t off2;
743	if (fUse & DISUSE_DISPLACEMENT8)
744	off2 = pParam->uDisp.i8;
745	else if (fUse & DISUSE_DISPLACEMENT16)
746	off2 = pParam->uDisp.i16;
747	else if (fUse & (DISUSE_DISPLACEMENT32 \| DISUSE_RIPDISPLACEMENT32))
748	off2 = pParam->uDisp.i32;
749	else if (fUse & DISUSE_DISPLACEMENT64)
750	off2 = pParam->uDisp.i64;
751	else
752	{
753	AssertFailed();
754	off2 = 0;
755	}
756
757	if (fBase \|\| (fUse & DISUSE_INDEX))
758	{
759	PUT_C(off2 >= 0 ? '+' : '-');
760	if (off2 < 0)
761	off2 = -off2;
762	}
763	if (fUse & DISUSE_DISPLACEMENT8)
764	PUT_NUM_8( off2);
765	else if (fUse & DISUSE_DISPLACEMENT16)
766	PUT_NUM_16(off2);
767	else if (fUse & DISUSE_DISPLACEMENT32)
768	PUT_NUM_32(off2);
769	else if (fUse & DISUSE_DISPLACEMENT64)
770	PUT_NUM_64(off2);
771	else
772	{
773	PUT_NUM_32(off2);
774	PUT_SZ(" wrt rip"); //??
775	}
776	}
777
778	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
779	PUT_C(']');
780	break;
781	}
782
783	case 'F': /* Eflags register (0 - popf/pushf only, avoided in adjustments above). */
784	AssertFailed();
785	break;
786
787	case 'I': /* Immediate data (ParseImmByte, ParseImmByteSX, ParseImmV, ParseImmUshort, ParseImmZ). */
788	Assert(pszFmt == 'b' \|\| pszFmt == 'v' \|\| pszFmt == 'w' \|\| pszFmt == 'z'); pszFmt++;
789	switch (pParam->fUse & ( DISUSE_IMMEDIATE8 \| DISUSE_IMMEDIATE16 \| DISUSE_IMMEDIATE32 \| DISUSE_IMMEDIATE64
790	\| DISUSE_IMMEDIATE16_SX8 \| DISUSE_IMMEDIATE32_SX8 \| DISUSE_IMMEDIATE64_SX8))
791	{
792	case DISUSE_IMMEDIATE8:
793	if ( (fFlags & DIS_FMT_FLAGS_STRICT)
794	&& ( (pOp->param1 >= OP_PARM_REG_GEN8_START && pOp->param1 <= OP_PARM_REG_GEN8_END)
795	\|\| (pOp->param2 >= OP_PARM_REG_GEN8_START && pOp->param2 <= OP_PARM_REG_GEN8_END))
796	)
797	PUT_SZ("strict byte ");
798	PUT_NUM_8(pParam->parval);
799	break;
800
801	case DISUSE_IMMEDIATE16:
802	if ( pCpu->uCpuMode != pCpu->uOpMode
803	\|\| ( (fFlags & DIS_FMT_FLAGS_STRICT)
804	&& ( (int8_t)pParam->parval == (int16_t)pParam->parval
805	\|\| (pOp->param1 >= OP_PARM_REG_GEN16_START && pOp->param1 <= OP_PARM_REG_GEN16_END)
806	\|\| (pOp->param2 >= OP_PARM_REG_GEN16_START && pOp->param2 <= OP_PARM_REG_GEN16_END))
807	)
808	)
809	{
810	if (OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_b)
811	PUT_SZ_STRICT("strict byte ", "byte ");
812	else if ( OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_v
813	\|\| OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_z)
814	PUT_SZ_STRICT("strict word ", "word ");
815	}
816	PUT_NUM_16(pParam->parval);
817	break;
818
819	case DISUSE_IMMEDIATE16_SX8:
820	PUT_SZ_STRICT("strict byte ", "byte ");
821	PUT_NUM_16(pParam->parval);
822	break;
823
824	case DISUSE_IMMEDIATE32:
825	if ( pCpu->uOpMode != (pCpu->uCpuMode == DISCPUMODE_16BIT ? DISCPUMODE_16BIT : DISCPUMODE_32BIT) /* not perfect */
826	\|\| ( (fFlags & DIS_FMT_FLAGS_STRICT)
827	&& ( (int8_t)pParam->parval == (int32_t)pParam->parval
828	\|\| (pOp->param1 >= OP_PARM_REG_GEN32_START && pOp->param1 <= OP_PARM_REG_GEN32_END)
829	\|\| (pOp->param2 >= OP_PARM_REG_GEN32_START && pOp->param2 <= OP_PARM_REG_GEN32_END))
830	)
831	)
832	{
833	if (OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_b)
834	PUT_SZ_STRICT("strict byte ", "byte ");
835	else if ( OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_v
836	\|\| OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_z)
837	PUT_SZ_STRICT("strict dword ", "dword ");
838	}
839	PUT_NUM_32(pParam->parval);
840	break;
841
842	case DISUSE_IMMEDIATE32_SX8:
843	PUT_SZ_STRICT("strict byte ", "byte ");
844	PUT_NUM_32(pParam->parval);
845	break;
846
847	case DISUSE_IMMEDIATE64_SX8:
848	PUT_SZ_STRICT("strict byte ", "byte ");
849	PUT_NUM_64(pParam->parval);
850	break;
851
852	case DISUSE_IMMEDIATE64:
853	PUT_NUM_64(pParam->parval);
854	break;
855
856	default:
857	AssertFailed();
858	break;
859	}
860	break;
861
862	case 'J': /* Relative jump offset (ParseImmBRel + ParseImmVRel). */
863	{
864	int32_t offDisplacement;
865	Assert(iParam == 1);
866	bool fPrefix = (fFlags & DIS_FMT_FLAGS_STRICT)
867	&& pOp->uOpcode != OP_CALL
868	&& pOp->uOpcode != OP_LOOP
869	&& pOp->uOpcode != OP_LOOPE
870	&& pOp->uOpcode != OP_LOOPNE
871	&& pOp->uOpcode != OP_JECXZ;
872	if (pOp->uOpcode == OP_CALL)
873	fFlags &= ~DIS_FMT_FLAGS_RELATIVE_BRANCH;
874
875	if (pParam->fUse & DISUSE_IMMEDIATE8_REL)
876	{
877	if (fPrefix)
878	PUT_SZ("short ");
879	offDisplacement = (int8_t)pParam->parval;
880	Assert(*pszFmt == 'b'); pszFmt++;
881
882	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
883	PUT_NUM_S8(offDisplacement);
884	}
885	else if (pParam->fUse & DISUSE_IMMEDIATE16_REL)
886	{
887	if (fPrefix)
888	PUT_SZ("near ");
889	offDisplacement = (int16_t)pParam->parval;
890	Assert(*pszFmt == 'v'); pszFmt++;
891
892	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
893	PUT_NUM_S16(offDisplacement);
894	}
895	else
896	{
897	if (fPrefix)
898	PUT_SZ("near ");
899	offDisplacement = (int32_t)pParam->parval;
900	Assert(pParam->fUse & (DISUSE_IMMEDIATE32_REL\|DISUSE_IMMEDIATE64_REL));
901	Assert(*pszFmt == 'v'); pszFmt++;
902
903	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
904	PUT_NUM_S32(offDisplacement);
905	}
906	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
907	PUT_SZ(" (");
908
909	RTUINTPTR uTrgAddr = pCpu->uInstrAddr + pCpu->cbInstr + offDisplacement;
910	if (pCpu->uCpuMode == DISCPUMODE_16BIT)
911	PUT_NUM_16(uTrgAddr);
912	else if (pCpu->uCpuMode == DISCPUMODE_32BIT)
913	PUT_NUM_32(uTrgAddr);
914	else
915	PUT_NUM_64(uTrgAddr);
916
917	if (pfnGetSymbol)
918	{
919	int rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, szSymbol, sizeof(szSymbol), &off, pvUser);
920	if (RT_SUCCESS(rc))
921	{
922	PUT_SZ(" [");
923	PUT_PSZ(szSymbol);
924	if (off != 0)
925	{
926	if ((int8_t)off == off)
927	PUT_NUM_S8(off);
928	else if ((int16_t)off == off)
929	PUT_NUM_S16(off);
930	else if ((int32_t)off == off)
931	PUT_NUM_S32(off);
932	else
933	PUT_NUM_S64(off);
934	}
935	PUT_C(']');
936	}
937	}
938
939	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
940	PUT_C(')');
941	break;
942	}
943
944	case 'A': /* Direct (jump/call) address (ParseImmAddr). */
945	{
946	Assert(*pszFmt == 'p'); pszFmt++;
947	PUT_FAR();
948	PUT_SIZE_OVERRIDE();
949	PUT_SEGMENT_OVERRIDE();
950	int rc = VERR_SYMBOL_NOT_FOUND;
951	switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 \| DISUSE_IMMEDIATE_ADDR_16_32 \| DISUSE_DISPLACEMENT64 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT16))
952	{
953	case DISUSE_IMMEDIATE_ADDR_16_16:
954	PUT_NUM_16(pParam->parval >> 16);
955	PUT_C(':');
956	PUT_NUM_16(pParam->parval);
957	if (pfnGetSymbol)
958	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_VALUE(pParam->parval >> 16), (uint16_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
959	break;
960	case DISUSE_IMMEDIATE_ADDR_16_32:
961	PUT_NUM_16(pParam->parval >> 32);
962	PUT_C(':');
963	PUT_NUM_32(pParam->parval);
964	if (pfnGetSymbol)
965	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_VALUE(pParam->parval >> 16), (uint32_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
966	break;
967	case DISUSE_DISPLACEMENT16:
968	PUT_NUM_16(pParam->parval);
969	if (pfnGetSymbol)
970	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint16_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
971	break;
972	case DISUSE_DISPLACEMENT32:
973	PUT_NUM_32(pParam->parval);
974	if (pfnGetSymbol)
975	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint32_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
976	break;
977	case DISUSE_DISPLACEMENT64:
978	PUT_NUM_64(pParam->parval);
979	if (pfnGetSymbol)
980	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint64_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
981	break;
982	default:
983	AssertFailed();
984	break;
985	}
986
987	if (RT_SUCCESS(rc))
988	{
989	PUT_SZ(" [");
990	PUT_PSZ(szSymbol);
991	if (off != 0)
992	{
993	if ((int8_t)off == off)
994	PUT_NUM_S8(off);
995	else if ((int16_t)off == off)
996	PUT_NUM_S16(off);
997	else if ((int32_t)off == off)
998	PUT_NUM_S32(off);
999	else
1000	PUT_NUM_S64(off);
1001	}
1002	PUT_C(']');
1003	}
1004	break;
1005	}
1006
1007	case 'O': /* No ModRM byte (ParseImmAddr). */
1008	{
1009	Assert(pszFmt == 'b' \|\| pszFmt == 'v'); pszFmt++;
1010	PUT_FAR();
1011	PUT_SIZE_OVERRIDE();
1012	PUT_C('[');
1013	PUT_SEGMENT_OVERRIDE();
1014	int rc = VERR_SYMBOL_NOT_FOUND;
1015	switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 \| DISUSE_IMMEDIATE_ADDR_16_32 \| DISUSE_DISPLACEMENT64 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT16))
1016	{
1017	case DISUSE_IMMEDIATE_ADDR_16_16:
1018	PUT_NUM_16(pParam->parval >> 16);
1019	PUT_C(':');
1020	PUT_NUM_16(pParam->parval);
1021	if (pfnGetSymbol)
1022	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_VALUE(pParam->parval >> 16), (uint16_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
1023	break;
1024	case DISUSE_IMMEDIATE_ADDR_16_32:
1025	PUT_NUM_16(pParam->parval >> 32);
1026	PUT_C(':');
1027	PUT_NUM_32(pParam->parval);
1028	if (pfnGetSymbol)
1029	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_VALUE(pParam->parval >> 16), (uint32_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
1030	break;
1031	case DISUSE_DISPLACEMENT16:
1032	PUT_NUM_16(pParam->uDisp.i16);
1033	if (pfnGetSymbol)
1034	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u16, szSymbol, sizeof(szSymbol), &off, pvUser);
1035	break;
1036	case DISUSE_DISPLACEMENT32:
1037	PUT_NUM_32(pParam->uDisp.i32);
1038	if (pfnGetSymbol)
1039	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u32, szSymbol, sizeof(szSymbol), &off, pvUser);
1040	break;
1041	case DISUSE_DISPLACEMENT64:
1042	PUT_NUM_64(pParam->uDisp.i64);
1043	if (pfnGetSymbol)
1044	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u64, szSymbol, sizeof(szSymbol), &off, pvUser);
1045	break;
1046	default:
1047	AssertFailed();
1048	break;
1049	}
1050	PUT_C(']');
1051
1052	if (RT_SUCCESS(rc))
1053	{
1054	PUT_SZ(" (");
1055	PUT_PSZ(szSymbol);
1056	if (off != 0)
1057	{
1058	if ((int8_t)off == off)
1059	PUT_NUM_S8(off);
1060	else if ((int16_t)off == off)
1061	PUT_NUM_S16(off);
1062	else if ((int32_t)off == off)
1063	PUT_NUM_S32(off);
1064	else
1065	PUT_NUM_S64(off);
1066	}
1067	PUT_C(')');
1068	}
1069	break;
1070	}
1071
1072	case 'X': /* DS:SI (ParseXb, ParseXv). */
1073	case 'Y': /* ES:DI (ParseYb, ParseYv). */
1074	{
1075	Assert(pszFmt == 'b' \|\| pszFmt == 'v'); pszFmt++;
1076	PUT_FAR();
1077	PUT_SIZE_OVERRIDE();
1078	PUT_C('[');
1079	if (pParam->fUse & DISUSE_POINTER_DS_BASED)
1080	PUT_SZ("ds:");
1081	else
1082	PUT_SZ("es:");
1083
1084	size_t cchReg;
1085	const char *pszReg = disasmFormatYasmBaseReg(pCpu, pParam, &cchReg);
1086	PUT_STR(pszReg, cchReg);
1087	PUT_C(']');
1088	break;
1089	}
1090
1091	case 'e': /* Register based on operand size (e.g. %eAX) (ParseFixedReg). */
1092	{
1093	Assert(RT_C_IS_ALPHA(pszFmt[0]) && RT_C_IS_ALPHA(pszFmt[1]) && !RT_C_IS_ALPHA(pszFmt[2])); pszFmt += 2;
1094	size_t cchReg;
1095	const char *pszReg = disasmFormatYasmBaseReg(pCpu, pParam, &cchReg);
1096	PUT_STR(pszReg, cchReg);
1097	break;
1098	}
1099
1100	default:
1101	AssertMsgFailed(("%c%s!\n", ch, pszFmt));
1102	break;
1103	}
1104	AssertMsg(pszFmt == ',' \|\| pszFmt == '\0', ("%c%s\n", ch, pszFmt));
1105	}
1106	else
1107	{
1108	PUT_C(ch);
1109	if (ch == ',')
1110	{
1111	Assert(*pszFmt != ' ');
1112	PUT_C(' ');
1113	switch (++iParam)
1114	{
1115	case 2: pParam = &pCpu->param2; break;
1116	case 3: pParam = &pCpu->param3; break;
1117	default: pParam = NULL; break;
1118	}
1119	}
1120	}
1121	} /* while more to format */
1122	}
1123
1124	/*
1125	* Any additional output to the right of the instruction?
1126	*/
1127	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
1128	{
1129	/* some up front padding. */
1130	size_t cchPadding = cchOutput - offInstruction;
1131	cchPadding = cchPadding + 1 >= 42 ? 1 : 42 - cchPadding;
1132	PUT_STR(g_szSpaces, cchPadding);
1133
1134	/* comment? */
1135	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
1136	PUT_SZ(";");
1137
1138	/*
1139	* The address?
1140	*/
1141	if (fFlags & DIS_FMT_FLAGS_ADDR_RIGHT)
1142	{
1143	PUT_C(' ');
1144	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
1145	if (pCpu->uInstrAddr >= _4G)
1146	PUT_NUM(9, "%08x`", (uint32_t)(pCpu->uInstrAddr >> 32));
1147	#endif
1148	PUT_NUM(8, "%08x", (uint32_t)pCpu->uInstrAddr);
1149	}
1150
1151	/*
1152	* Opcode bytes?
1153	*/
1154	if (fFlags & DIS_FMT_FLAGS_BYTES_RIGHT)
1155	{
1156	PUT_C(' ');
1157	size_t cchTmp = disFormatBytes(pCpu, pszDst, cchDst, fFlags);
1158	cchOutput += cchTmp;
1159	if (cchTmp >= cchDst)
1160	cchTmp = cchDst - (cchDst != 0);
1161	cchDst -= cchTmp;
1162	pszDst += cchTmp;
1163	}
1164	}
1165
1166	/*
1167	* Terminate it - on overflow we'll have reserved one byte for this.
1168	*/
1169	if (cchDst > 0)
1170	*pszDst = '\0';
1171	else
1172	Assert(!cchBuf);
1173
1174	/* clean up macros */
1175	#undef PUT_PSZ
1176	#undef PUT_SZ
1177	#undef PUT_STR
1178	#undef PUT_C
1179	return cchOutput;
1180	}
1181
1182
1183	/**
1184	* Formats the current instruction in Yasm (/ Nasm) style.
1185	*
1186	* This is a simplified version of DISFormatYasmEx() provided for your convenience.
1187	*
1188	*
1189	* @returns The number of output characters. If this is >= cchBuf, then the content
1190	* of pszBuf will be truncated.
1191	* @param pCpu Pointer to the disassembler CPU state.
1192	* @param pszBuf The output buffer.
1193	* @param cchBuf The size of the output buffer.
1194	*/
1195	DISDECL(size_t) DISFormatYasm(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf)
1196	{
1197	return DISFormatYasmEx(pCpu, pszBuf, cchBuf, 0 /* fFlags /, NULL / pfnGetSymbol /, NULL / pvUser */);
1198	}
1199
1200
1201	/**
1202	* Checks if the encoding of the given disassembled instruction is something we
1203	* can never get YASM to produce.
1204	*
1205	* @returns true if it's odd, false if it isn't.
1206	* @param pCpu The disassembler output. The byte fetcher callback will
1207	* be used if present as we might need to fetch opcode
1208	* bytes.
1209	*/
1210	DISDECL(bool) DISFormatYasmIsOddEncoding(PDISCPUSTATE pCpu)
1211	{
1212	/*
1213	* Mod rm + SIB: Check for duplicate EBP encodings that yasm won't use for very good reasons.
1214	*/
1215	if ( pCpu->uAddrMode != DISCPUMODE_16BIT ///@todo correct?
1216	&& pCpu->ModRM.Bits.Rm == 4
1217	&& pCpu->ModRM.Bits.Mod != 3)
1218	{
1219	/* No scaled index SIB (index=4), except for ESP. */
1220	if ( pCpu->SIB.Bits.Index == 4
1221	&& pCpu->SIB.Bits.Base != 4)
1222	return true;
1223
1224	/* EBP + displacement */
1225	if ( pCpu->ModRM.Bits.Mod != 0
1226	&& pCpu->SIB.Bits.Base == 5
1227	&& pCpu->SIB.Bits.Scale == 0)
1228	return true;
1229	}
1230
1231	/*
1232	* Seems to be an instruction alias here, but I cannot find any docs on it... hrmpf!
1233	*/
1234	if ( pCpu->pCurInstr->uOpcode == OP_SHL
1235	&& pCpu->ModRM.Bits.Reg == 6)
1236	return true;
1237
1238	/*
1239	* Check for multiple prefixes of the same kind.
1240	*/
1241	uint32_t fPrefixes = 0;
1242	for (uint32_t offOpcode = 0; offOpcode < RT_ELEMENTS(pCpu->abInstr); offOpcode++)
1243	{
1244	uint32_t f;
1245	switch (pCpu->abInstr[offOpcode])
1246	{
1247	case 0xf0:
1248	f = DISPREFIX_LOCK;
1249	break;
1250
1251	case 0xf2:
1252	case 0xf3:
1253	f = DISPREFIX_REP; /* yes, both */
1254	break;
1255
1256	case 0x2e:
1257	case 0x3e:
1258	case 0x26:
1259	case 0x36:
1260	case 0x64:
1261	case 0x65:
1262	f = DISPREFIX_SEG;
1263	break;
1264
1265	case 0x66:
1266	f = DISPREFIX_OPSIZE;
1267	break;
1268
1269	case 0x67:
1270	f = DISPREFIX_ADDRSIZE;
1271	break;
1272
1273	case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
1274	case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
1275	f = pCpu->uCpuMode == DISCPUMODE_64BIT ? DISPREFIX_REX : 0;
1276	break;
1277
1278	default:
1279	f = 0;
1280	break;
1281	}
1282	if (!f)
1283	break; /* done */
1284	if (fPrefixes & f)
1285	return true;
1286	fPrefixes \|= f;
1287	}
1288
1289	/* segment overrides are fun */
1290	if (fPrefixes & DISPREFIX_SEG)
1291	{
1292	/* no effective address which it may apply to. */
1293	Assert((pCpu->fPrefix & DISPREFIX_SEG) \|\| pCpu->uCpuMode == DISCPUMODE_64BIT);
1294	if ( !DISUSE_IS_EFFECTIVE_ADDR(pCpu->param1.fUse)
1295	&& !DISUSE_IS_EFFECTIVE_ADDR(pCpu->param2.fUse)
1296	&& !DISUSE_IS_EFFECTIVE_ADDR(pCpu->param3.fUse))
1297	return true;
1298	}
1299
1300	/* fixed register + addr override doesn't go down all that well. */
1301	if (fPrefixes & DISPREFIX_ADDRSIZE)
1302	{
1303	Assert(pCpu->fPrefix & DISPREFIX_ADDRSIZE);
1304	if ( pCpu->pCurInstr->param3 == OP_PARM_NONE
1305	&& pCpu->pCurInstr->param2 == OP_PARM_NONE
1306	&& ( pCpu->pCurInstr->param1 >= OP_PARM_REG_GEN32_START
1307	&& pCpu->pCurInstr->param1 <= OP_PARM_REG_GEN32_END))
1308	return true;
1309	}
1310
1311	/* Almost all prefixes are bad. */
1312	if (fPrefixes)
1313	{
1314	switch (pCpu->pCurInstr->uOpcode)
1315	{
1316	/* nop w/ prefix(es). */
1317	case OP_NOP:
1318	return true;
1319
1320	case OP_JMP:
1321	if ( pCpu->pCurInstr->param1 != OP_PARM_Jb
1322	&& pCpu->pCurInstr->param1 != OP_PARM_Jv)
1323	break;
1324	/* fall thru */
1325	case OP_JO:
1326	case OP_JNO:
1327	case OP_JC:
1328	case OP_JNC:
1329	case OP_JE:
1330	case OP_JNE:
1331	case OP_JBE:
1332	case OP_JNBE:
1333	case OP_JS:
1334	case OP_JNS:
1335	case OP_JP:
1336	case OP_JNP:
1337	case OP_JL:
1338	case OP_JNL:
1339	case OP_JLE:
1340	case OP_JNLE:
1341	/** @todo branch hinting 0x2e/0x3e... */
1342	return true;
1343	}
1344
1345	}
1346
1347	/* All but the segment prefix is bad news. */
1348	if (fPrefixes & ~DISPREFIX_SEG)
1349	{
1350	switch (pCpu->pCurInstr->uOpcode)
1351	{
1352	case OP_POP:
1353	case OP_PUSH:
1354	if ( pCpu->pCurInstr->param1 >= OP_PARM_REG_SEG_START
1355	&& pCpu->pCurInstr->param1 <= OP_PARM_REG_SEG_END)
1356	return true;
1357	if ( (fPrefixes & ~DISPREFIX_OPSIZE)
1358	&& pCpu->pCurInstr->param1 >= OP_PARM_REG_GEN32_START
1359	&& pCpu->pCurInstr->param1 <= OP_PARM_REG_GEN32_END)
1360	return true;
1361	break;
1362
1363	case OP_POPA:
1364	case OP_POPF:
1365	case OP_PUSHA:
1366	case OP_PUSHF:
1367	if (fPrefixes & ~DISPREFIX_OPSIZE)
1368	return true;
1369	break;
1370	}
1371	}
1372
1373	/* Implicit 8-bit register instructions doesn't mix with operand size. */
1374	if ( (fPrefixes & DISPREFIX_OPSIZE)
1375	&& ( ( pCpu->pCurInstr->param1 == OP_PARM_Gb /* r8 */
1376	&& pCpu->pCurInstr->param2 == OP_PARM_Eb /* r8/mem8 */)
1377	\|\| ( pCpu->pCurInstr->param2 == OP_PARM_Gb /* r8 */
1378	&& pCpu->pCurInstr->param1 == OP_PARM_Eb /* r8/mem8 */))
1379	)
1380	{
1381	switch (pCpu->pCurInstr->uOpcode)
1382	{
1383	case OP_ADD:
1384	case OP_OR:
1385	case OP_ADC:
1386	case OP_SBB:
1387	case OP_AND:
1388	case OP_SUB:
1389	case OP_XOR:
1390	case OP_CMP:
1391	return true;
1392	default:
1393	break;
1394	}
1395	}
1396
1397
1398	/*
1399	* Check for the version of xyz reg,reg instruction that the assembler doesn't use.
1400	*
1401	* For example:
1402	* expected: 1aee sbb ch, dh ; SBB r8, r/m8
1403	* yasm: 18F5 sbb ch, dh ; SBB r/m8, r8
1404	*/
1405	if (pCpu->ModRM.Bits.Mod == 3 /* reg,reg */)
1406	{
1407	switch (pCpu->pCurInstr->uOpcode)
1408	{
1409	case OP_ADD:
1410	case OP_OR:
1411	case OP_ADC:
1412	case OP_SBB:
1413	case OP_AND:
1414	case OP_SUB:
1415	case OP_XOR:
1416	case OP_CMP:
1417	if ( ( pCpu->pCurInstr->param1 == OP_PARM_Gb /* r8 */
1418	&& pCpu->pCurInstr->param2 == OP_PARM_Eb /* r8/mem8 */)
1419	\|\| ( pCpu->pCurInstr->param1 == OP_PARM_Gv /* rX */
1420	&& pCpu->pCurInstr->param2 == OP_PARM_Ev /* rX/memX */))
1421	return true;
1422
1423	/* 82 (see table A-6). */
1424	if (pCpu->bOpCode == 0x82)
1425	return true;
1426	break;
1427
1428	/* ff /0, fe /0, ff /1, fe /0 */
1429	case OP_DEC:
1430	case OP_INC:
1431	return true;
1432
1433	case OP_POP:
1434	case OP_PUSH:
1435	Assert(pCpu->bOpCode == 0x8f);
1436	return true;
1437
1438	case OP_MOV:
1439	if ( pCpu->bOpCode == 0x8a
1440	\|\| pCpu->bOpCode == 0x8b)
1441	return true;
1442	break;
1443
1444	default:
1445	break;
1446	}
1447	}
1448
1449	/* shl eax,1 will be assembled to the form without the immediate byte. */
1450	if ( pCpu->pCurInstr->param2 == OP_PARM_Ib
1451	&& (uint8_t)pCpu->param2.parval == 1)
1452	{
1453	switch (pCpu->pCurInstr->uOpcode)
1454	{
1455	case OP_SHL:
1456	case OP_SHR:
1457	case OP_SAR:
1458	case OP_RCL:
1459	case OP_RCR:
1460	case OP_ROL:
1461	case OP_ROR:
1462	return true;
1463	}
1464	}
1465
1466	/* And some more - see table A-6. */
1467	if (pCpu->bOpCode == 0x82)
1468	{
1469	switch (pCpu->pCurInstr->uOpcode)
1470	{
1471	case OP_ADD:
1472	case OP_OR:
1473	case OP_ADC:
1474	case OP_SBB:
1475	case OP_AND:
1476	case OP_SUB:
1477	case OP_XOR:
1478	case OP_CMP:
1479	return true;
1480	break;
1481	}
1482	}
1483
1484
1485	/* check for REX.X = 1 without SIB. */
1486
1487	/* Yasm encodes setnbe al with /2 instead of /0 like the AMD manual
1488	says (intel doesn't appear to care). */
1489	switch (pCpu->pCurInstr->uOpcode)
1490	{
1491	case OP_SETO:
1492	case OP_SETNO:
1493	case OP_SETC:
1494	case OP_SETNC:
1495	case OP_SETE:
1496	case OP_SETNE:
1497	case OP_SETBE:
1498	case OP_SETNBE:
1499	case OP_SETS:
1500	case OP_SETNS:
1501	case OP_SETP:
1502	case OP_SETNP:
1503	case OP_SETL:
1504	case OP_SETNL:
1505	case OP_SETLE:
1506	case OP_SETNLE:
1507	AssertMsg(pCpu->bOpCode >= 0x90 && pCpu->bOpCode <= 0x9f, ("%#x\n", pCpu->bOpCode));
1508	if (pCpu->ModRM.Bits.Reg != 2)
1509	return true;
1510	break;
1511	}
1512
1513	/*
1514	* The MOVZX reg32,mem16 instruction without an operand size prefix
1515	* doesn't quite make sense...
1516	*/
1517	if ( pCpu->pCurInstr->uOpcode == OP_MOVZX
1518	&& pCpu->bOpCode == 0xB7
1519	&& (pCpu->uCpuMode == DISCPUMODE_16BIT) != !!(fPrefixes & DISPREFIX_OPSIZE))
1520	return true;
1521
1522	return false;
1523	}
1524

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source: vbox/trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp@ 41737

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