DisasmFormatYasm.cpp@ 41871

Last change on this file since 41871 was 41792, checked in by vboxsync, 12 years ago
Some more DISSTATE adjustments.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 60.4 KB

Line
1	/* $Id: DisasmFormatYasm.cpp 41792 2012-06-16 23:41:11Z vboxsync $ */
2	/** @file
3	* VBox Disassembler - Yasm(/Nasm) Style Formatter.
4	*/
5
6	/*
7	* Copyright (C) 2008-2012 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#include <VBox/dis.h>
23	#include "DisasmInternal.h"
24	#include <iprt/string.h>
25	#include <iprt/assert.h>
26	#include <iprt/ctype.h>
27
28
29	/*******************************************************************************
30	* Global Variables *
31	*******************************************************************************/
32	static const char g_szSpaces[] =
33	" ";
34	static const char g_aszYasmRegGen8[20][5] =
35	{
36	"al\0\0", "cl\0\0", "dl\0\0", "bl\0\0", "ah\0\0", "ch\0\0", "dh\0\0", "bh\0\0", "r8b\0", "r9b\0", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b", "spl\0", "bpl\0", "sil\0", "dil\0"
37	};
38	static const char g_aszYasmRegGen16[16][5] =
39	{
40	"ax\0\0", "cx\0\0", "dx\0\0", "bx\0\0", "sp\0\0", "bp\0\0", "si\0\0", "di\0\0", "r8w\0", "r9w\0", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
41	};
42	static const char g_aszYasmRegGen1616[8][6] =
43	{
44	"bx+si", "bx+di", "bp+si", "bp+di", "si\0\0\0", "di\0\0\0", "bp\0\0\0", "bx\0\0\0"
45	};
46	static const char g_aszYasmRegGen32[16][5] =
47	{
48	"eax\0", "ecx\0", "edx\0", "ebx\0", "esp\0", "ebp\0", "esi\0", "edi\0", "r8d\0", "r9d\0", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
49	};
50	static const char g_aszYasmRegGen64[16][4] =
51	{
52	"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", "r8\0", "r9\0", "r10", "r11", "r12", "r13", "r14", "r15"
53	};
54	static const char g_aszYasmRegSeg[6][3] =
55	{
56	"es", "cs", "ss", "ds", "fs", "gs"
57	};
58	static const char g_aszYasmRegFP[8][4] =
59	{
60	"st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7"
61	};
62	static const char g_aszYasmRegMMX[8][4] =
63	{
64	"mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7"
65	};
66	static const char g_aszYasmRegXMM[16][6] =
67	{
68	"xmm0\0", "xmm1\0", "xmm2\0", "xmm3\0", "xmm4\0", "xmm5\0", "xmm6\0", "xmm7\0", "xmm8\0", "xmm9\0", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
69	};
70	static const char g_aszYasmRegCRx[16][5] =
71	{
72	"cr0\0", "cr1\0", "cr2\0", "cr3\0", "cr4\0", "cr5\0", "cr6\0", "cr7\0", "cr8\0", "cr9\0", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15"
73	};
74	static const char g_aszYasmRegDRx[16][5] =
75	{
76	"dr0\0", "dr1\0", "dr2\0", "dr3\0", "dr4\0", "dr5\0", "dr6\0", "dr7\0", "dr8\0", "dr9\0", "dr10", "dr11", "dr12", "dr13", "dr14", "dr15"
77	};
78	static const char g_aszYasmRegTRx[16][5] =
79	{
80	"tr0\0", "tr1\0", "tr2\0", "tr3\0", "tr4\0", "tr5\0", "tr6\0", "tr7\0", "tr8\0", "tr9\0", "tr10", "tr11", "tr12", "tr13", "tr14", "tr15"
81	};
82
83
84
85	/**
86	* Gets the base register name for the given parameter.
87	*
88	* @returns Pointer to the register name.
89	* @param pDis The disassembler state.
90	* @param pParam The parameter.
91	* @param pcchReg Where to store the length of the name.
92	*/
93	static const char disasmFormatYasmBaseReg(PCDISSTATE pDis, PCDISOPPARAM pParam, size_t pcchReg)
94	{
95	switch (pParam->fUse & ( DISUSE_REG_GEN8 \| DISUSE_REG_GEN16 \| DISUSE_REG_GEN32 \| DISUSE_REG_GEN64
96	\| DISUSE_REG_FP \| DISUSE_REG_MMX \| DISUSE_REG_XMM \| DISUSE_REG_CR
97	\| DISUSE_REG_DBG \| DISUSE_REG_SEG \| DISUSE_REG_TEST))
98
99	{
100	case DISUSE_REG_GEN8:
101	{
102	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen8));
103	const char *psz = g_aszYasmRegGen8[pParam->Base.idxGenReg];
104	*pcchReg = 2 + !!psz[2] + !!psz[3];
105	return psz;
106	}
107
108	case DISUSE_REG_GEN16:
109	{
110	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
111	const char *psz = g_aszYasmRegGen16[pParam->Base.idxGenReg];
112	*pcchReg = 2 + !!psz[2] + !!psz[3];
113	return psz;
114	}
115
116	case DISUSE_REG_GEN32:
117	{
118	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
119	const char *psz = g_aszYasmRegGen32[pParam->Base.idxGenReg];
120	*pcchReg = 2 + !!psz[2] + !!psz[3];
121	return psz;
122	}
123
124	case DISUSE_REG_GEN64:
125	{
126	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
127	const char *psz = g_aszYasmRegGen64[pParam->Base.idxGenReg];
128	*pcchReg = 2 + !!psz[2] + !!psz[3];
129	return psz;
130	}
131
132	case DISUSE_REG_FP:
133	{
134	Assert(pParam->Base.idxFpuReg < RT_ELEMENTS(g_aszYasmRegFP));
135	const char *psz = g_aszYasmRegFP[pParam->Base.idxFpuReg];
136	*pcchReg = 3;
137	return psz;
138	}
139
140	case DISUSE_REG_MMX:
141	{
142	Assert(pParam->Base.idxMmxReg < RT_ELEMENTS(g_aszYasmRegMMX));
143	const char *psz = g_aszYasmRegMMX[pParam->Base.idxMmxReg];
144	*pcchReg = 3;
145	return psz;
146	}
147
148	case DISUSE_REG_XMM:
149	{
150	Assert(pParam->Base.idxXmmReg < RT_ELEMENTS(g_aszYasmRegXMM));
151	const char *psz = g_aszYasmRegXMM[pParam->Base.idxMmxReg];
152	*pcchReg = 4 + !!psz[4];
153	return psz;
154	}
155
156	case DISUSE_REG_CR:
157	{
158	Assert(pParam->Base.idxCtrlReg < RT_ELEMENTS(g_aszYasmRegCRx));
159	const char *psz = g_aszYasmRegCRx[pParam->Base.idxCtrlReg];
160	*pcchReg = 3;
161	return psz;
162	}
163
164	case DISUSE_REG_DBG:
165	{
166	Assert(pParam->Base.idxDbgReg < RT_ELEMENTS(g_aszYasmRegDRx));
167	const char *psz = g_aszYasmRegDRx[pParam->Base.idxDbgReg];
168	*pcchReg = 3;
169	return psz;
170	}
171
172	case DISUSE_REG_SEG:
173	{
174	Assert(pParam->Base.idxSegReg < RT_ELEMENTS(g_aszYasmRegCRx));
175	const char *psz = g_aszYasmRegSeg[pParam->Base.idxSegReg];
176	*pcchReg = 2;
177	return psz;
178	}
179
180	case DISUSE_REG_TEST:
181	{
182	Assert(pParam->Base.idxTestReg < RT_ELEMENTS(g_aszYasmRegTRx));
183	const char *psz = g_aszYasmRegTRx[pParam->Base.idxTestReg];
184	*pcchReg = 3;
185	return psz;
186	}
187
188	default:
189	AssertMsgFailed(("%#x\n", pParam->fUse));
190	*pcchReg = 3;
191	return "r??";
192	}
193	}
194
195
196	/**
197	* Gets the index register name for the given parameter.
198	*
199	* @returns The index register name.
200	* @param pDis The disassembler state.
201	* @param pParam The parameter.
202	* @param pcchReg Where to store the length of the name.
203	*/
204	static const char disasmFormatYasmIndexReg(PCDISSTATE pDis, PCDISOPPARAM pParam, size_t pcchReg)
205	{
206	switch (pDis->uAddrMode)
207	{
208	case DISCPUMODE_16BIT:
209	{
210	Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
211	const char *psz = g_aszYasmRegGen16[pParam->Index.idxGenReg];
212	*pcchReg = 2 + !!psz[2] + !!psz[3];
213	return psz;
214	}
215
216	case DISCPUMODE_32BIT:
217	{
218	Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
219	const char *psz = g_aszYasmRegGen32[pParam->Index.idxGenReg];
220	*pcchReg = 2 + !!psz[2] + !!psz[3];
221	return psz;
222	}
223
224	case DISCPUMODE_64BIT:
225	{
226	Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
227	const char *psz = g_aszYasmRegGen64[pParam->Index.idxGenReg];
228	*pcchReg = 2 + !!psz[2] + !!psz[3];
229	return psz;
230	}
231
232	default:
233	AssertMsgFailed(("%#x %#x\n", pParam->fUse, pDis->uAddrMode));
234	*pcchReg = 3;
235	return "r??";
236	}
237	}
238
239
240	/**
241	* Formats the current instruction in Yasm (/ Nasm) style.
242	*
243	*
244	* @returns The number of output characters. If this is >= cchBuf, then the content
245	* of pszBuf will be truncated.
246	* @param pDis Pointer to the disassembler state.
247	* @param pszBuf The output buffer.
248	* @param cchBuf The size of the output buffer.
249	* @param fFlags Format flags, see DIS_FORMAT_FLAGS_*.
250	* @param pfnGetSymbol Get symbol name for a jmp or call target address. Optional.
251	* @param pvUser User argument for pfnGetSymbol.
252	*/
253	DISDECL(size_t) DISFormatYasmEx(PCDISSTATE pDis, char *pszBuf, size_t cchBuf, uint32_t fFlags,
254	PFNDISGETSYMBOL pfnGetSymbol, void *pvUser)
255	{
256	/*
257	* Input validation and massaging.
258	*/
259	AssertPtr(pDis);
260	AssertPtrNull(pszBuf);
261	Assert(pszBuf \|\| !cchBuf);
262	AssertPtrNull(pfnGetSymbol);
263	AssertMsg(DIS_FMT_FLAGS_IS_VALID(fFlags), ("%#x\n", fFlags));
264	if (fFlags & DIS_FMT_FLAGS_ADDR_COMMENT)
265	fFlags = (fFlags & ~DIS_FMT_FLAGS_ADDR_LEFT) \| DIS_FMT_FLAGS_ADDR_RIGHT;
266	if (fFlags & DIS_FMT_FLAGS_BYTES_COMMENT)
267	fFlags = (fFlags & ~DIS_FMT_FLAGS_BYTES_LEFT) \| DIS_FMT_FLAGS_BYTES_RIGHT;
268
269	PCDISOPCODE const pOp = pDis->pCurInstr;
270
271	/*
272	* Output macros
273	*/
274	char *pszDst = pszBuf;
275	size_t cchDst = cchBuf;
276	size_t cchOutput = 0;
277	#define PUT_C(ch) \
278	do { \
279	cchOutput++; \
280	if (cchDst > 1) \
281	{ \
282	cchDst--; \
283	*pszDst++ = (ch); \
284	} \
285	} while (0)
286	#define PUT_STR(pszSrc, cchSrc) \
287	do { \
288	cchOutput += (cchSrc); \
289	if (cchDst > (cchSrc)) \
290	{ \
291	memcpy(pszDst, (pszSrc), (cchSrc)); \
292	pszDst += (cchSrc); \
293	cchDst -= (cchSrc); \
294	} \
295	else if (cchDst > 1) \
296	{ \
297	memcpy(pszDst, (pszSrc), cchDst - 1); \
298	pszDst += cchDst - 1; \
299	cchDst = 1; \
300	} \
301	} while (0)
302	#define PUT_SZ(sz) \
303	PUT_STR((sz), sizeof(sz) - 1)
304	#define PUT_SZ_STRICT(szStrict, szRelaxed) \
305	do { if (fFlags & DIS_FMT_FLAGS_STRICT) PUT_SZ(szStrict); else PUT_SZ(szRelaxed); } while (0)
306	#define PUT_PSZ(psz) \
307	do { const size_t cchTmp = strlen(psz); PUT_STR((psz), cchTmp); } while (0)
308	#define PUT_NUM(cch, fmt, num) \
309	do { \
310	cchOutput += (cch); \
311	if (cchDst > 1) \
312	{ \
313	const size_t cchTmp = RTStrPrintf(pszDst, cchDst, fmt, (num)); \
314	pszDst += cchTmp; \
315	cchDst -= cchTmp; \
316	Assert(cchTmp == (cch) \|\| cchDst == 1); \
317	} \
318	} while (0)
319	/** @todo add two flags for choosing between %X / %x and h / 0x. */
320	#define PUT_NUM_8(num) PUT_NUM(4, "0%02xh", (uint8_t)(num))
321	#define PUT_NUM_16(num) PUT_NUM(6, "0%04xh", (uint16_t)(num))
322	#define PUT_NUM_32(num) PUT_NUM(10, "0%08xh", (uint32_t)(num))
323	#define PUT_NUM_64(num) PUT_NUM(18, "0%016RX64h", (uint64_t)(num))
324
325	#define PUT_NUM_SIGN(cch, fmt, num, stype, utype) \
326	do { \
327	if ((stype)(num) >= 0) \
328	{ \
329	PUT_C('+'); \
330	PUT_NUM(cch, fmt, (utype)(num)); \
331	} \
332	else \
333	{ \
334	PUT_C('-'); \
335	PUT_NUM(cch, fmt, (utype)-(stype)(num)); \
336	} \
337	} while (0)
338	#define PUT_NUM_S8(num) PUT_NUM_SIGN(4, "0%02xh", num, int8_t, uint8_t)
339	#define PUT_NUM_S16(num) PUT_NUM_SIGN(6, "0%04xh", num, int16_t, uint16_t)
340	#define PUT_NUM_S32(num) PUT_NUM_SIGN(10, "0%08xh", num, int32_t, uint32_t)
341	#define PUT_NUM_S64(num) PUT_NUM_SIGN(18, "0%016RX64h", num, int64_t, uint64_t)
342
343
344	/*
345	* The address?
346	*/
347	if (fFlags & DIS_FMT_FLAGS_ADDR_LEFT)
348	{
349	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
350	if (pDis->uInstrAddr >= _4G)
351	PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
352	#endif
353	PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
354	PUT_C(' ');
355	}
356
357	/*
358	* The opcode bytes?
359	*/
360	if (fFlags & DIS_FMT_FLAGS_BYTES_LEFT)
361	{
362	size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
363	cchOutput += cchTmp;
364	if (cchDst > 1)
365	{
366	if (cchTmp <= cchDst)
367	{
368	cchDst -= cchTmp;
369	pszDst += cchTmp;
370	}
371	else
372	{
373	pszDst += cchDst - 1;
374	cchDst = 1;
375	}
376	}
377
378	/* Some padding to align the instruction. */
379	size_t cchPadding = (7 * (2 + !!(fFlags & DIS_FMT_FLAGS_BYTES_SPACED)))
380	+ !!(fFlags & DIS_FMT_FLAGS_BYTES_BRACKETS) * 2
381	+ 2;
382	cchPadding = cchTmp + 1 >= cchPadding ? 1 : cchPadding - cchTmp;
383	PUT_STR(g_szSpaces, cchPadding);
384	}
385
386
387	/*
388	* Filter out invalid opcodes first as they need special
389	* treatment. UD2 is an exception and should be handled normally.
390	*/
391	size_t const offInstruction = cchOutput;
392	if ( pOp->uOpcode == OP_INVALID
393	\|\| ( pOp->uOpcode == OP_ILLUD2
394	&& (pDis->fPrefix & DISPREFIX_LOCK)))
395	PUT_SZ("Illegal opcode");
396	else
397	{
398	/*
399	* Prefixes
400	*/
401	if (pDis->fPrefix & DISPREFIX_LOCK)
402	PUT_SZ("lock ");
403	if(pDis->fPrefix & DISPREFIX_REP)
404	PUT_SZ("rep ");
405	else if(pDis->fPrefix & DISPREFIX_REPNE)
406	PUT_SZ("repne ");
407
408	/*
409	* Adjust the format string to the correct mnemonic
410	* or to avoid things the assembler cannot handle correctly.
411	*/
412	char szTmpFmt[48];
413	const char *pszFmt = pOp->pszOpcode;
414	switch (pOp->uOpcode)
415	{
416	case OP_JECXZ:
417	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "jcxz %Jb" : pDis->uOpMode == DISCPUMODE_32BIT ? "jecxz %Jb" : "jrcxz %Jb";
418	break;
419	case OP_PUSHF:
420	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "pushfw" : pDis->uOpMode == DISCPUMODE_32BIT ? "pushfd" : "pushfq";
421	break;
422	case OP_POPF:
423	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "popfw" : pDis->uOpMode == DISCPUMODE_32BIT ? "popfd" : "popfq";
424	break;
425	case OP_PUSHA:
426	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "pushaw" : "pushad";
427	break;
428	case OP_POPA:
429	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "popaw" : "popad";
430	break;
431	case OP_INSB:
432	pszFmt = "insb";
433	break;
434	case OP_INSWD:
435	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "insw" : pDis->uOpMode == DISCPUMODE_32BIT ? "insd" : "insq";
436	break;
437	case OP_OUTSB:
438	pszFmt = "outsb";
439	break;
440	case OP_OUTSWD:
441	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "outsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "outsd" : "outsq";
442	break;
443	case OP_MOVSB:
444	pszFmt = "movsb";
445	break;
446	case OP_MOVSWD:
447	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "movsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "movsd" : "movsq";
448	break;
449	case OP_CMPSB:
450	pszFmt = "cmpsb";
451	break;
452	case OP_CMPWD:
453	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cmpsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "cmpsd" : "cmpsq";
454	break;
455	case OP_SCASB:
456	pszFmt = "scasb";
457	break;
458	case OP_SCASWD:
459	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "scasw" : pDis->uOpMode == DISCPUMODE_32BIT ? "scasd" : "scasq";
460	break;
461	case OP_LODSB:
462	pszFmt = "lodsb";
463	break;
464	case OP_LODSWD:
465	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "lodsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "lodsd" : "lodsq";
466	break;
467	case OP_STOSB:
468	pszFmt = "stosb";
469	break;
470	case OP_STOSWD:
471	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "stosw" : pDis->uOpMode == DISCPUMODE_32BIT ? "stosd" : "stosq";
472	break;
473	case OP_CBW:
474	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cbw" : pDis->uOpMode == DISCPUMODE_32BIT ? "cwde" : "cdqe";
475	break;
476	case OP_CWD:
477	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cwd" : pDis->uOpMode == DISCPUMODE_32BIT ? "cdq" : "cqo";
478	break;
479	case OP_SHL:
480	Assert(pszFmt[3] == '/');
481	pszFmt += 4;
482	break;
483	case OP_XLAT:
484	pszFmt = "xlatb";
485	break;
486	case OP_INT3:
487	pszFmt = "int3";
488	break;
489
490	/*
491	* Don't know how to tell yasm to generate complicated nop stuff, so 'db' it.
492	*/
493	case OP_NOP:
494	if (pDis->bOpCode == 0x90)
495	/* fine, fine */;
496	else if (pszFmt[sizeof("nop %Ev") - 1] == '/' && pszFmt[sizeof("nop %Ev")] == 'p')
497	pszFmt = "prefetch %Eb";
498	else if (pDis->bOpCode == 0x1f)
499	{
500	Assert(pDis->cbInstr >= 3);
501	PUT_SZ("db 00fh, 01fh,");
502	PUT_NUM_8(MAKE_MODRM(pDis->ModRM.Bits.Mod, pDis->ModRM.Bits.Reg, pDis->ModRM.Bits.Rm));
503	for (unsigned i = 3; i < pDis->cbInstr; i++)
504	{
505	PUT_C(',');
506	PUT_NUM_8(0x90); ///@todo fixme.
507	}
508	pszFmt = "";
509	}
510	break;
511
512	default:
513	/* ST(X) -> stX (floating point) */
514	if (*pszFmt == 'f' && strchr(pszFmt, '('))
515	{
516	char *pszFmtDst = szTmpFmt;
517	char ch;
518	do
519	{
520	ch = *pszFmt++;
521	if (ch == 'S' && pszFmt[0] == 'T' && pszFmt[1] == '(')
522	{
523	*pszFmtDst++ = 's';
524	*pszFmtDst++ = 't';
525	pszFmt += 2;
526	ch = *pszFmt;
527	Assert(pszFmt[1] == ')');
528	pszFmt += 2;
529	*pszFmtDst++ = ch;
530	}
531	else
532	*pszFmtDst++ = ch;
533	} while (ch != '\0');
534	pszFmt = szTmpFmt;
535	}
536	break;
537
538	/*
539	* Horrible hacks.
540	*/
541	case OP_FLD:
542	if (pDis->bOpCode == 0xdb) /* m80fp workaround. */
543	(int )&pDis->Param1.fParam &= ~0x1f; /* make it pure OP_PARM_M */
544	break;
545	case OP_LAR: /* hack w -> v, probably not correct. */
546	(int )&pDis->Param2.fParam &= ~0x1f;
547	(int )&pDis->Param2.fParam \|= OP_PARM_v;
548	break;
549	}
550
551	/*
552	* Formatting context and associated macros.
553	*/
554	PCDISOPPARAM pParam = &pDis->Param1;
555	int iParam = 1;
556
557	#define PUT_FAR() \
558	do { \
559	if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_p \
560	&& pOp->uOpcode != OP_LDS /* table bugs? */ \
561	&& pOp->uOpcode != OP_LES \
562	&& pOp->uOpcode != OP_LFS \
563	&& pOp->uOpcode != OP_LGS \
564	&& pOp->uOpcode != OP_LSS ) \
565	PUT_SZ("far "); \
566	} while (0)
567	/** @todo mov ah,ch ends up with a byte 'override'... - check if this wasn't fixed. */
568	/** @todo drop the work/dword/qword override when the src/dst is a register (except for movsx/movzx). */
569	#define PUT_SIZE_OVERRIDE() \
570	do { \
571	switch (OP_PARM_VSUBTYPE(pParam->fParam)) \
572	{ \
573	case OP_PARM_v: \
574	switch (pDis->uOpMode) \
575	{ \
576	case DISCPUMODE_16BIT: PUT_SZ("word "); break; \
577	case DISCPUMODE_32BIT: PUT_SZ("dword "); break; \
578	case DISCPUMODE_64BIT: PUT_SZ("qword "); break; \
579	default: break; \
580	} \
581	break; \
582	case OP_PARM_b: PUT_SZ("byte "); break; \
583	case OP_PARM_w: PUT_SZ("word "); break; \
584	case OP_PARM_d: PUT_SZ("dword "); break; \
585	case OP_PARM_q: PUT_SZ("qword "); break; \
586	case OP_PARM_dq: \
587	if (OP_PARM_VTYPE(pParam->fParam) != OP_PARM_W) /* these are 128 bit, pray they are all unambiguous.. */ \
588	PUT_SZ("qword "); \
589	break; \
590	case OP_PARM_p: break; /* see PUT_FAR */ \
591	case OP_PARM_s: if (pParam->fUse & DISUSE_REG_FP) PUT_SZ("tword "); break; /* ?? */ \
592	case OP_PARM_z: break; \
593	case OP_PARM_NONE: \
594	if ( OP_PARM_VTYPE(pParam->fParam) == OP_PARM_M \
595	&& ((pParam->fUse & DISUSE_REG_FP) \|\| pOp->uOpcode == OP_FLD)) \
596	PUT_SZ("tword "); \
597	break; \
598	default: break; /no pointer type specified/necessary/ \
599	} \
600	} while (0)
601	static const char s_szSegPrefix[6][4] = { "es:", "cs:", "ss:", "ds:", "fs:", "gs:" };
602	#define PUT_SEGMENT_OVERRIDE() \
603	do { \
604	if (pDis->fPrefix & DISPREFIX_SEG) \
605	PUT_STR(s_szSegPrefix[pDis->idxSegPrefix], 3); \
606	} while (0)
607
608
609	/*
610	* Segment prefixing for instructions that doesn't do memory access.
611	*/
612	if ( (pDis->fPrefix & DISPREFIX_SEG)
613	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
614	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
615	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse))
616	{
617	PUT_STR(s_szSegPrefix[pDis->idxSegPrefix], 2);
618	PUT_C(' ');
619	}
620
621
622	/*
623	* The formatting loop.
624	*/
625	RTINTPTR off;
626	char szSymbol[128];
627	char ch;
628	while ((ch = *pszFmt++) != '\0')
629	{
630	if (ch == '%')
631	{
632	ch = *pszFmt++;
633	switch (ch)
634	{
635	/*
636	* ModRM - Register only.
637	*/
638	case 'C': /* Control register (ParseModRM / UseModRM). */
639	case 'D': /* Debug register (ParseModRM / UseModRM). */
640	case 'G': /* ModRM selects general register (ParseModRM / UseModRM). */
641	case 'S': /* ModRM byte selects a segment register (ParseModRM / UseModRM). */
642	case 'T': /* ModRM byte selects a test register (ParseModRM / UseModRM). */
643	case 'V': /* ModRM byte selects an XMM/SSE register (ParseModRM / UseModRM). */
644	case 'P': /* ModRM byte selects MMX register (ParseModRM / UseModRM). */
645	{
646	pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
647	Assert(!(pParam->fUse & (DISUSE_INDEX \| DISUSE_SCALE) /* No SIB here... */));
648	Assert(!(pParam->fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32)));
649
650	size_t cchReg;
651	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
652	PUT_STR(pszReg, cchReg);
653	break;
654	}
655
656	/*
657	* ModRM - Register or memory.
658	*/
659	case 'E': /* ModRM specifies parameter (ParseModRM / UseModRM / UseSIB). */
660	case 'Q': /* ModRM byte selects MMX register or memory address (ParseModRM / UseModRM). */
661	case 'R': /* ModRM byte may only refer to a general register (ParseModRM / UseModRM). */
662	case 'W': /* ModRM byte selects an XMM/SSE register or a memory address (ParseModRM / UseModRM). */
663	case 'M': /* ModRM may only refer to memory (ParseModRM / UseModRM). */
664	{
665	pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
666
667	PUT_FAR();
668	uint32_t const fUse = pParam->fUse;
669	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
670	{
671	/* Work around mov seg,[mem16] and mov [mem16],seg as these always make a 16-bit mem
672	while the register variants deals with 16, 32 & 64 in the normal fashion. */
673	if ( pParam->fParam != OP_PARM_Ev
674	\|\| pOp->uOpcode != OP_MOV
675	\|\| ( pOp->fParam1 != OP_PARM_Sw
676	&& pOp->fParam2 != OP_PARM_Sw))
677	PUT_SIZE_OVERRIDE();
678	PUT_C('[');
679	}
680	if ( (fFlags & DIS_FMT_FLAGS_STRICT)
681	&& (fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32)))
682	{
683	if ( (fUse & DISUSE_DISPLACEMENT8)
684	&& !pParam->uDisp.i8)
685	PUT_SZ("byte ");
686	else if ( (fUse & DISUSE_DISPLACEMENT16)
687	&& (int8_t)pParam->uDisp.i16 == (int16_t)pParam->uDisp.i16)
688	PUT_SZ("word ");
689	else if ( (fUse & DISUSE_DISPLACEMENT32)
690	&& (int16_t)pParam->uDisp.i32 == (int32_t)pParam->uDisp.i32) //??
691	PUT_SZ("dword ");
692	else if ( (fUse & DISUSE_DISPLACEMENT64)
693	&& (pDis->SIB.Bits.Base != 5 \|\| pDis->ModRM.Bits.Mod != 0)
694	&& (int32_t)pParam->uDisp.i64 == (int64_t)pParam->uDisp.i64) //??
695	PUT_SZ("qword ");
696	}
697	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
698	PUT_SEGMENT_OVERRIDE();
699
700	bool fBase = (fUse & DISUSE_BASE) /* When exactly is DISUSE_BASE supposed to be set? disasmModRMReg doesn't set it. */
701	\|\| ( (fUse & ( DISUSE_REG_GEN8
702	\| DISUSE_REG_GEN16
703	\| DISUSE_REG_GEN32
704	\| DISUSE_REG_GEN64
705	\| DISUSE_REG_FP
706	\| DISUSE_REG_MMX
707	\| DISUSE_REG_XMM
708	\| DISUSE_REG_CR
709	\| DISUSE_REG_DBG
710	\| DISUSE_REG_SEG
711	\| DISUSE_REG_TEST ))
712	&& !DISUSE_IS_EFFECTIVE_ADDR(fUse));
713	if (fBase)
714	{
715	size_t cchReg;
716	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
717	PUT_STR(pszReg, cchReg);
718	}
719
720	if (fUse & DISUSE_INDEX)
721	{
722	if (fBase)
723	PUT_C('+');
724
725	size_t cchReg;
726	const char *pszReg = disasmFormatYasmIndexReg(pDis, pParam, &cchReg);
727	PUT_STR(pszReg, cchReg);
728
729	if (fUse & DISUSE_SCALE)
730	{
731	PUT_C('*');
732	PUT_C('0' + pParam->uScale);
733	}
734	}
735	else
736	Assert(!(fUse & DISUSE_SCALE));
737
738	if (fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32))
739	{
740	int64_t off2;
741	if (fUse & DISUSE_DISPLACEMENT8)
742	off2 = pParam->uDisp.i8;
743	else if (fUse & DISUSE_DISPLACEMENT16)
744	off2 = pParam->uDisp.i16;
745	else if (fUse & (DISUSE_DISPLACEMENT32 \| DISUSE_RIPDISPLACEMENT32))
746	off2 = pParam->uDisp.i32;
747	else if (fUse & DISUSE_DISPLACEMENT64)
748	off2 = pParam->uDisp.i64;
749	else
750	{
751	AssertFailed();
752	off2 = 0;
753	}
754
755	if (fBase \|\| (fUse & DISUSE_INDEX))
756	{
757	PUT_C(off2 >= 0 ? '+' : '-');
758	if (off2 < 0)
759	off2 = -off2;
760	}
761	if (fUse & DISUSE_DISPLACEMENT8)
762	PUT_NUM_8( off2);
763	else if (fUse & DISUSE_DISPLACEMENT16)
764	PUT_NUM_16(off2);
765	else if (fUse & DISUSE_DISPLACEMENT32)
766	PUT_NUM_32(off2);
767	else if (fUse & DISUSE_DISPLACEMENT64)
768	PUT_NUM_64(off2);
769	else
770	{
771	PUT_NUM_32(off2);
772	PUT_SZ(" wrt rip"); //??
773	}
774	}
775
776	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
777	PUT_C(']');
778	break;
779	}
780
781	case 'F': /* Eflags register (0 - popf/pushf only, avoided in adjustments above). */
782	AssertFailed();
783	break;
784
785	case 'I': /* Immediate data (ParseImmByte, ParseImmByteSX, ParseImmV, ParseImmUshort, ParseImmZ). */
786	Assert(pszFmt == 'b' \|\| pszFmt == 'v' \|\| pszFmt == 'w' \|\| pszFmt == 'z'); pszFmt++;
787	switch (pParam->fUse & ( DISUSE_IMMEDIATE8 \| DISUSE_IMMEDIATE16 \| DISUSE_IMMEDIATE32 \| DISUSE_IMMEDIATE64
788	\| DISUSE_IMMEDIATE16_SX8 \| DISUSE_IMMEDIATE32_SX8 \| DISUSE_IMMEDIATE64_SX8))
789	{
790	case DISUSE_IMMEDIATE8:
791	if ( (fFlags & DIS_FMT_FLAGS_STRICT)
792	&& ( (pOp->fParam1 >= OP_PARM_REG_GEN8_START && pOp->fParam1 <= OP_PARM_REG_GEN8_END)
793	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN8_START && pOp->fParam2 <= OP_PARM_REG_GEN8_END))
794	)
795	PUT_SZ("strict byte ");
796	PUT_NUM_8(pParam->uValue);
797	break;
798
799	case DISUSE_IMMEDIATE16:
800	if ( pDis->uCpuMode != pDis->uOpMode
801	\|\| ( (fFlags & DIS_FMT_FLAGS_STRICT)
802	&& ( (int8_t)pParam->uValue == (int16_t)pParam->uValue
803	\|\| (pOp->fParam1 >= OP_PARM_REG_GEN16_START && pOp->fParam1 <= OP_PARM_REG_GEN16_END)
804	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN16_START && pOp->fParam2 <= OP_PARM_REG_GEN16_END))
805	)
806	)
807	{
808	if (OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_b)
809	PUT_SZ_STRICT("strict byte ", "byte ");
810	else if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_v
811	\|\| OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_z)
812	PUT_SZ_STRICT("strict word ", "word ");
813	}
814	PUT_NUM_16(pParam->uValue);
815	break;
816
817	case DISUSE_IMMEDIATE16_SX8:
818	PUT_SZ_STRICT("strict byte ", "byte ");
819	PUT_NUM_16(pParam->uValue);
820	break;
821
822	case DISUSE_IMMEDIATE32:
823	if ( pDis->uOpMode != (pDis->uCpuMode == DISCPUMODE_16BIT ? DISCPUMODE_16BIT : DISCPUMODE_32BIT) /* not perfect */
824	\|\| ( (fFlags & DIS_FMT_FLAGS_STRICT)
825	&& ( (int8_t)pParam->uValue == (int32_t)pParam->uValue
826	\|\| (pOp->fParam1 >= OP_PARM_REG_GEN32_START && pOp->fParam1 <= OP_PARM_REG_GEN32_END)
827	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN32_START && pOp->fParam2 <= OP_PARM_REG_GEN32_END))
828	)
829	)
830	{
831	if (OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_b)
832	PUT_SZ_STRICT("strict byte ", "byte ");
833	else if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_v
834	\|\| OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_z)
835	PUT_SZ_STRICT("strict dword ", "dword ");
836	}
837	PUT_NUM_32(pParam->uValue);
838	break;
839
840	case DISUSE_IMMEDIATE32_SX8:
841	PUT_SZ_STRICT("strict byte ", "byte ");
842	PUT_NUM_32(pParam->uValue);
843	break;
844
845	case DISUSE_IMMEDIATE64_SX8:
846	PUT_SZ_STRICT("strict byte ", "byte ");
847	PUT_NUM_64(pParam->uValue);
848	break;
849
850	case DISUSE_IMMEDIATE64:
851	PUT_NUM_64(pParam->uValue);
852	break;
853
854	default:
855	AssertFailed();
856	break;
857	}
858	break;
859
860	case 'J': /* Relative jump offset (ParseImmBRel + ParseImmVRel). */
861	{
862	int32_t offDisplacement;
863	Assert(iParam == 1);
864	bool fPrefix = (fFlags & DIS_FMT_FLAGS_STRICT)
865	&& pOp->uOpcode != OP_CALL
866	&& pOp->uOpcode != OP_LOOP
867	&& pOp->uOpcode != OP_LOOPE
868	&& pOp->uOpcode != OP_LOOPNE
869	&& pOp->uOpcode != OP_JECXZ;
870	if (pOp->uOpcode == OP_CALL)
871	fFlags &= ~DIS_FMT_FLAGS_RELATIVE_BRANCH;
872
873	if (pParam->fUse & DISUSE_IMMEDIATE8_REL)
874	{
875	if (fPrefix)
876	PUT_SZ("short ");
877	offDisplacement = (int8_t)pParam->uValue;
878	Assert(*pszFmt == 'b'); pszFmt++;
879
880	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
881	PUT_NUM_S8(offDisplacement);
882	}
883	else if (pParam->fUse & DISUSE_IMMEDIATE16_REL)
884	{
885	if (fPrefix)
886	PUT_SZ("near ");
887	offDisplacement = (int16_t)pParam->uValue;
888	Assert(*pszFmt == 'v'); pszFmt++;
889
890	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
891	PUT_NUM_S16(offDisplacement);
892	}
893	else
894	{
895	if (fPrefix)
896	PUT_SZ("near ");
897	offDisplacement = (int32_t)pParam->uValue;
898	Assert(pParam->fUse & (DISUSE_IMMEDIATE32_REL\|DISUSE_IMMEDIATE64_REL));
899	Assert(*pszFmt == 'v'); pszFmt++;
900
901	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
902	PUT_NUM_S32(offDisplacement);
903	}
904	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
905	PUT_SZ(" (");
906
907	RTUINTPTR uTrgAddr = pDis->uInstrAddr + pDis->cbInstr + offDisplacement;
908	if (pDis->uCpuMode == DISCPUMODE_16BIT)
909	PUT_NUM_16(uTrgAddr);
910	else if (pDis->uCpuMode == DISCPUMODE_32BIT)
911	PUT_NUM_32(uTrgAddr);
912	else
913	PUT_NUM_64(uTrgAddr);
914
915	if (pfnGetSymbol)
916	{
917	int rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, szSymbol, sizeof(szSymbol), &off, pvUser);
918	if (RT_SUCCESS(rc))
919	{
920	PUT_SZ(" [");
921	PUT_PSZ(szSymbol);
922	if (off != 0)
923	{
924	if ((int8_t)off == off)
925	PUT_NUM_S8(off);
926	else if ((int16_t)off == off)
927	PUT_NUM_S16(off);
928	else if ((int32_t)off == off)
929	PUT_NUM_S32(off);
930	else
931	PUT_NUM_S64(off);
932	}
933	PUT_C(']');
934	}
935	}
936
937	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
938	PUT_C(')');
939	break;
940	}
941
942	case 'A': /* Direct (jump/call) address (ParseImmAddr). */
943	{
944	Assert(*pszFmt == 'p'); pszFmt++;
945	PUT_FAR();
946	PUT_SIZE_OVERRIDE();
947	PUT_SEGMENT_OVERRIDE();
948	int rc = VERR_SYMBOL_NOT_FOUND;
949	switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 \| DISUSE_IMMEDIATE_ADDR_16_32 \| DISUSE_DISPLACEMENT64 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT16))
950	{
951	case DISUSE_IMMEDIATE_ADDR_16_16:
952	PUT_NUM_16(pParam->uValue >> 16);
953	PUT_C(':');
954	PUT_NUM_16(pParam->uValue);
955	if (pfnGetSymbol)
956	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
957	break;
958	case DISUSE_IMMEDIATE_ADDR_16_32:
959	PUT_NUM_16(pParam->uValue >> 32);
960	PUT_C(':');
961	PUT_NUM_32(pParam->uValue);
962	if (pfnGetSymbol)
963	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
964	break;
965	case DISUSE_DISPLACEMENT16:
966	PUT_NUM_16(pParam->uValue);
967	if (pfnGetSymbol)
968	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
969	break;
970	case DISUSE_DISPLACEMENT32:
971	PUT_NUM_32(pParam->uValue);
972	if (pfnGetSymbol)
973	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
974	break;
975	case DISUSE_DISPLACEMENT64:
976	PUT_NUM_64(pParam->uValue);
977	if (pfnGetSymbol)
978	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint64_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
979	break;
980	default:
981	AssertFailed();
982	break;
983	}
984
985	if (RT_SUCCESS(rc))
986	{
987	PUT_SZ(" [");
988	PUT_PSZ(szSymbol);
989	if (off != 0)
990	{
991	if ((int8_t)off == off)
992	PUT_NUM_S8(off);
993	else if ((int16_t)off == off)
994	PUT_NUM_S16(off);
995	else if ((int32_t)off == off)
996	PUT_NUM_S32(off);
997	else
998	PUT_NUM_S64(off);
999	}
1000	PUT_C(']');
1001	}
1002	break;
1003	}
1004
1005	case 'O': /* No ModRM byte (ParseImmAddr). */
1006	{
1007	Assert(pszFmt == 'b' \|\| pszFmt == 'v'); pszFmt++;
1008	PUT_FAR();
1009	PUT_SIZE_OVERRIDE();
1010	PUT_C('[');
1011	PUT_SEGMENT_OVERRIDE();
1012	int rc = VERR_SYMBOL_NOT_FOUND;
1013	switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 \| DISUSE_IMMEDIATE_ADDR_16_32 \| DISUSE_DISPLACEMENT64 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT16))
1014	{
1015	case DISUSE_IMMEDIATE_ADDR_16_16:
1016	PUT_NUM_16(pParam->uValue >> 16);
1017	PUT_C(':');
1018	PUT_NUM_16(pParam->uValue);
1019	if (pfnGetSymbol)
1020	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1021	break;
1022	case DISUSE_IMMEDIATE_ADDR_16_32:
1023	PUT_NUM_16(pParam->uValue >> 32);
1024	PUT_C(':');
1025	PUT_NUM_32(pParam->uValue);
1026	if (pfnGetSymbol)
1027	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1028	break;
1029	case DISUSE_DISPLACEMENT16:
1030	PUT_NUM_16(pParam->uDisp.i16);
1031	if (pfnGetSymbol)
1032	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u16, szSymbol, sizeof(szSymbol), &off, pvUser);
1033	break;
1034	case DISUSE_DISPLACEMENT32:
1035	PUT_NUM_32(pParam->uDisp.i32);
1036	if (pfnGetSymbol)
1037	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u32, szSymbol, sizeof(szSymbol), &off, pvUser);
1038	break;
1039	case DISUSE_DISPLACEMENT64:
1040	PUT_NUM_64(pParam->uDisp.i64);
1041	if (pfnGetSymbol)
1042	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u64, szSymbol, sizeof(szSymbol), &off, pvUser);
1043	break;
1044	default:
1045	AssertFailed();
1046	break;
1047	}
1048	PUT_C(']');
1049
1050	if (RT_SUCCESS(rc))
1051	{
1052	PUT_SZ(" (");
1053	PUT_PSZ(szSymbol);
1054	if (off != 0)
1055	{
1056	if ((int8_t)off == off)
1057	PUT_NUM_S8(off);
1058	else if ((int16_t)off == off)
1059	PUT_NUM_S16(off);
1060	else if ((int32_t)off == off)
1061	PUT_NUM_S32(off);
1062	else
1063	PUT_NUM_S64(off);
1064	}
1065	PUT_C(')');
1066	}
1067	break;
1068	}
1069
1070	case 'X': /* DS:SI (ParseXb, ParseXv). */
1071	case 'Y': /* ES:DI (ParseYb, ParseYv). */
1072	{
1073	Assert(pszFmt == 'b' \|\| pszFmt == 'v'); pszFmt++;
1074	PUT_FAR();
1075	PUT_SIZE_OVERRIDE();
1076	PUT_C('[');
1077	if (pParam->fUse & DISUSE_POINTER_DS_BASED)
1078	PUT_SZ("ds:");
1079	else
1080	PUT_SZ("es:");
1081
1082	size_t cchReg;
1083	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
1084	PUT_STR(pszReg, cchReg);
1085	PUT_C(']');
1086	break;
1087	}
1088
1089	case 'e': /* Register based on operand size (e.g. %eAX) (ParseFixedReg). */
1090	{
1091	Assert(RT_C_IS_ALPHA(pszFmt[0]) && RT_C_IS_ALPHA(pszFmt[1]) && !RT_C_IS_ALPHA(pszFmt[2])); pszFmt += 2;
1092	size_t cchReg;
1093	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
1094	PUT_STR(pszReg, cchReg);
1095	break;
1096	}
1097
1098	default:
1099	AssertMsgFailed(("%c%s!\n", ch, pszFmt));
1100	break;
1101	}
1102	AssertMsg(pszFmt == ',' \|\| pszFmt == '\0', ("%c%s\n", ch, pszFmt));
1103	}
1104	else
1105	{
1106	PUT_C(ch);
1107	if (ch == ',')
1108	{
1109	Assert(*pszFmt != ' ');
1110	PUT_C(' ');
1111	switch (++iParam)
1112	{
1113	case 2: pParam = &pDis->Param2; break;
1114	case 3: pParam = &pDis->Param3; break;
1115	default: pParam = NULL; break;
1116	}
1117	}
1118	}
1119	} /* while more to format */
1120	}
1121
1122	/*
1123	* Any additional output to the right of the instruction?
1124	*/
1125	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
1126	{
1127	/* some up front padding. */
1128	size_t cchPadding = cchOutput - offInstruction;
1129	cchPadding = cchPadding + 1 >= 42 ? 1 : 42 - cchPadding;
1130	PUT_STR(g_szSpaces, cchPadding);
1131
1132	/* comment? */
1133	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
1134	PUT_SZ(";");
1135
1136	/*
1137	* The address?
1138	*/
1139	if (fFlags & DIS_FMT_FLAGS_ADDR_RIGHT)
1140	{
1141	PUT_C(' ');
1142	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
1143	if (pDis->uInstrAddr >= _4G)
1144	PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
1145	#endif
1146	PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
1147	}
1148
1149	/*
1150	* Opcode bytes?
1151	*/
1152	if (fFlags & DIS_FMT_FLAGS_BYTES_RIGHT)
1153	{
1154	PUT_C(' ');
1155	size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
1156	cchOutput += cchTmp;
1157	if (cchTmp >= cchDst)
1158	cchTmp = cchDst - (cchDst != 0);
1159	cchDst -= cchTmp;
1160	pszDst += cchTmp;
1161	}
1162	}
1163
1164	/*
1165	* Terminate it - on overflow we'll have reserved one byte for this.
1166	*/
1167	if (cchDst > 0)
1168	*pszDst = '\0';
1169	else
1170	Assert(!cchBuf);
1171
1172	/* clean up macros */
1173	#undef PUT_PSZ
1174	#undef PUT_SZ
1175	#undef PUT_STR
1176	#undef PUT_C
1177	return cchOutput;
1178	}
1179
1180
1181	/**
1182	* Formats the current instruction in Yasm (/ Nasm) style.
1183	*
1184	* This is a simplified version of DISFormatYasmEx() provided for your convenience.
1185	*
1186	*
1187	* @returns The number of output characters. If this is >= cchBuf, then the content
1188	* of pszBuf will be truncated.
1189	* @param pDis Pointer to the disassembler state.
1190	* @param pszBuf The output buffer.
1191	* @param cchBuf The size of the output buffer.
1192	*/
1193	DISDECL(size_t) DISFormatYasm(PCDISSTATE pDis, char *pszBuf, size_t cchBuf)
1194	{
1195	return DISFormatYasmEx(pDis, pszBuf, cchBuf, 0 /* fFlags /, NULL / pfnGetSymbol /, NULL / pvUser */);
1196	}
1197
1198
1199	/**
1200	* Checks if the encoding of the given disassembled instruction is something we
1201	* can never get YASM to produce.
1202	*
1203	* @returns true if it's odd, false if it isn't.
1204	* @param pDis The disassembler output. The byte fetcher callback will
1205	* be used if present as we might need to fetch opcode
1206	* bytes.
1207	*/
1208	DISDECL(bool) DISFormatYasmIsOddEncoding(PDISSTATE pDis)
1209	{
1210	/*
1211	* Mod rm + SIB: Check for duplicate EBP encodings that yasm won't use for very good reasons.
1212	*/
1213	if ( pDis->uAddrMode != DISCPUMODE_16BIT ///@todo correct?
1214	&& pDis->ModRM.Bits.Rm == 4
1215	&& pDis->ModRM.Bits.Mod != 3)
1216	{
1217	/* No scaled index SIB (index=4), except for ESP. */
1218	if ( pDis->SIB.Bits.Index == 4
1219	&& pDis->SIB.Bits.Base != 4)
1220	return true;
1221
1222	/* EBP + displacement */
1223	if ( pDis->ModRM.Bits.Mod != 0
1224	&& pDis->SIB.Bits.Base == 5
1225	&& pDis->SIB.Bits.Scale == 0)
1226	return true;
1227	}
1228
1229	/*
1230	* Seems to be an instruction alias here, but I cannot find any docs on it... hrmpf!
1231	*/
1232	if ( pDis->pCurInstr->uOpcode == OP_SHL
1233	&& pDis->ModRM.Bits.Reg == 6)
1234	return true;
1235
1236	/*
1237	* Check for multiple prefixes of the same kind.
1238	*/
1239	uint32_t fPrefixes = 0;
1240	for (uint32_t offOpcode = 0; offOpcode < RT_ELEMENTS(pDis->abInstr); offOpcode++)
1241	{
1242	uint32_t f;
1243	switch (pDis->abInstr[offOpcode])
1244	{
1245	case 0xf0:
1246	f = DISPREFIX_LOCK;
1247	break;
1248
1249	case 0xf2:
1250	case 0xf3:
1251	f = DISPREFIX_REP; /* yes, both */
1252	break;
1253
1254	case 0x2e:
1255	case 0x3e:
1256	case 0x26:
1257	case 0x36:
1258	case 0x64:
1259	case 0x65:
1260	f = DISPREFIX_SEG;
1261	break;
1262
1263	case 0x66:
1264	f = DISPREFIX_OPSIZE;
1265	break;
1266
1267	case 0x67:
1268	f = DISPREFIX_ADDRSIZE;
1269	break;
1270
1271	case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
1272	case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
1273	f = pDis->uCpuMode == DISCPUMODE_64BIT ? DISPREFIX_REX : 0;
1274	break;
1275
1276	default:
1277	f = 0;
1278	break;
1279	}
1280	if (!f)
1281	break; /* done */
1282	if (fPrefixes & f)
1283	return true;
1284	fPrefixes \|= f;
1285	}
1286
1287	/* segment overrides are fun */
1288	if (fPrefixes & DISPREFIX_SEG)
1289	{
1290	/* no effective address which it may apply to. */
1291	Assert((pDis->fPrefix & DISPREFIX_SEG) \|\| pDis->uCpuMode == DISCPUMODE_64BIT);
1292	if ( !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
1293	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
1294	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse))
1295	return true;
1296	}
1297
1298	/* fixed register + addr override doesn't go down all that well. */
1299	if (fPrefixes & DISPREFIX_ADDRSIZE)
1300	{
1301	Assert(pDis->fPrefix & DISPREFIX_ADDRSIZE);
1302	if ( pDis->pCurInstr->fParam3 == OP_PARM_NONE
1303	&& pDis->pCurInstr->fParam2 == OP_PARM_NONE
1304	&& ( pDis->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
1305	&& pDis->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END))
1306	return true;
1307	}
1308
1309	/* Almost all prefixes are bad. */
1310	if (fPrefixes)
1311	{
1312	switch (pDis->pCurInstr->uOpcode)
1313	{
1314	/* nop w/ prefix(es). */
1315	case OP_NOP:
1316	return true;
1317
1318	case OP_JMP:
1319	if ( pDis->pCurInstr->fParam1 != OP_PARM_Jb
1320	&& pDis->pCurInstr->fParam1 != OP_PARM_Jv)
1321	break;
1322	/* fall thru */
1323	case OP_JO:
1324	case OP_JNO:
1325	case OP_JC:
1326	case OP_JNC:
1327	case OP_JE:
1328	case OP_JNE:
1329	case OP_JBE:
1330	case OP_JNBE:
1331	case OP_JS:
1332	case OP_JNS:
1333	case OP_JP:
1334	case OP_JNP:
1335	case OP_JL:
1336	case OP_JNL:
1337	case OP_JLE:
1338	case OP_JNLE:
1339	/** @todo branch hinting 0x2e/0x3e... */
1340	return true;
1341	}
1342
1343	}
1344
1345	/* All but the segment prefix is bad news. */
1346	if (fPrefixes & ~DISPREFIX_SEG)
1347	{
1348	switch (pDis->pCurInstr->uOpcode)
1349	{
1350	case OP_POP:
1351	case OP_PUSH:
1352	if ( pDis->pCurInstr->fParam1 >= OP_PARM_REG_SEG_START
1353	&& pDis->pCurInstr->fParam1 <= OP_PARM_REG_SEG_END)
1354	return true;
1355	if ( (fPrefixes & ~DISPREFIX_OPSIZE)
1356	&& pDis->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
1357	&& pDis->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END)
1358	return true;
1359	break;
1360
1361	case OP_POPA:
1362	case OP_POPF:
1363	case OP_PUSHA:
1364	case OP_PUSHF:
1365	if (fPrefixes & ~DISPREFIX_OPSIZE)
1366	return true;
1367	break;
1368	}
1369	}
1370
1371	/* Implicit 8-bit register instructions doesn't mix with operand size. */
1372	if ( (fPrefixes & DISPREFIX_OPSIZE)
1373	&& ( ( pDis->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
1374	&& pDis->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
1375	\|\| ( pDis->pCurInstr->fParam2 == OP_PARM_Gb /* r8 */
1376	&& pDis->pCurInstr->fParam1 == OP_PARM_Eb /* r8/mem8 */))
1377	)
1378	{
1379	switch (pDis->pCurInstr->uOpcode)
1380	{
1381	case OP_ADD:
1382	case OP_OR:
1383	case OP_ADC:
1384	case OP_SBB:
1385	case OP_AND:
1386	case OP_SUB:
1387	case OP_XOR:
1388	case OP_CMP:
1389	return true;
1390	default:
1391	break;
1392	}
1393	}
1394
1395
1396	/*
1397	* Check for the version of xyz reg,reg instruction that the assembler doesn't use.
1398	*
1399	* For example:
1400	* expected: 1aee sbb ch, dh ; SBB r8, r/m8
1401	* yasm: 18F5 sbb ch, dh ; SBB r/m8, r8
1402	*/
1403	if (pDis->ModRM.Bits.Mod == 3 /* reg,reg */)
1404	{
1405	switch (pDis->pCurInstr->uOpcode)
1406	{
1407	case OP_ADD:
1408	case OP_OR:
1409	case OP_ADC:
1410	case OP_SBB:
1411	case OP_AND:
1412	case OP_SUB:
1413	case OP_XOR:
1414	case OP_CMP:
1415	if ( ( pDis->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
1416	&& pDis->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
1417	\|\| ( pDis->pCurInstr->fParam1 == OP_PARM_Gv /* rX */
1418	&& pDis->pCurInstr->fParam2 == OP_PARM_Ev /* rX/memX */))
1419	return true;
1420
1421	/* 82 (see table A-6). */
1422	if (pDis->bOpCode == 0x82)
1423	return true;
1424	break;
1425
1426	/* ff /0, fe /0, ff /1, fe /0 */
1427	case OP_DEC:
1428	case OP_INC:
1429	return true;
1430
1431	case OP_POP:
1432	case OP_PUSH:
1433	Assert(pDis->bOpCode == 0x8f);
1434	return true;
1435
1436	case OP_MOV:
1437	if ( pDis->bOpCode == 0x8a
1438	\|\| pDis->bOpCode == 0x8b)
1439	return true;
1440	break;
1441
1442	default:
1443	break;
1444	}
1445	}
1446
1447	/* shl eax,1 will be assembled to the form without the immediate byte. */
1448	if ( pDis->pCurInstr->fParam2 == OP_PARM_Ib
1449	&& (uint8_t)pDis->Param2.uValue == 1)
1450	{
1451	switch (pDis->pCurInstr->uOpcode)
1452	{
1453	case OP_SHL:
1454	case OP_SHR:
1455	case OP_SAR:
1456	case OP_RCL:
1457	case OP_RCR:
1458	case OP_ROL:
1459	case OP_ROR:
1460	return true;
1461	}
1462	}
1463
1464	/* And some more - see table A-6. */
1465	if (pDis->bOpCode == 0x82)
1466	{
1467	switch (pDis->pCurInstr->uOpcode)
1468	{
1469	case OP_ADD:
1470	case OP_OR:
1471	case OP_ADC:
1472	case OP_SBB:
1473	case OP_AND:
1474	case OP_SUB:
1475	case OP_XOR:
1476	case OP_CMP:
1477	return true;
1478	break;
1479	}
1480	}
1481
1482
1483	/* check for REX.X = 1 without SIB. */
1484
1485	/* Yasm encodes setnbe al with /2 instead of /0 like the AMD manual
1486	says (intel doesn't appear to care). */
1487	switch (pDis->pCurInstr->uOpcode)
1488	{
1489	case OP_SETO:
1490	case OP_SETNO:
1491	case OP_SETC:
1492	case OP_SETNC:
1493	case OP_SETE:
1494	case OP_SETNE:
1495	case OP_SETBE:
1496	case OP_SETNBE:
1497	case OP_SETS:
1498	case OP_SETNS:
1499	case OP_SETP:
1500	case OP_SETNP:
1501	case OP_SETL:
1502	case OP_SETNL:
1503	case OP_SETLE:
1504	case OP_SETNLE:
1505	AssertMsg(pDis->bOpCode >= 0x90 && pDis->bOpCode <= 0x9f, ("%#x\n", pDis->bOpCode));
1506	if (pDis->ModRM.Bits.Reg != 2)
1507	return true;
1508	break;
1509	}
1510
1511	/*
1512	* The MOVZX reg32,mem16 instruction without an operand size prefix
1513	* doesn't quite make sense...
1514	*/
1515	if ( pDis->pCurInstr->uOpcode == OP_MOVZX
1516	&& pDis->bOpCode == 0xB7
1517	&& (pDis->uCpuMode == DISCPUMODE_16BIT) != !!(fPrefixes & DISPREFIX_OPSIZE))
1518	return true;
1519
1520	return false;
1521	}
1522

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source: vbox/trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp@ 41871

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