DisasmFormatYasm.cpp@ 53114

Last change on this file since 53114 was 53094, checked in by vboxsync, 10 years ago
DIS: #6251: AVX / VEX instructions support (two byte instructions only) and some fixes to the other tables.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 63.7 KB

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1	/* $Id: DisasmFormatYasm.cpp 53094 2014-10-20 16:04:09Z vboxsync $ */
2	/** @file
3	* VBox Disassembler - Yasm(/Nasm) Style Formatter.
4	*/
5
6	/*
7	* Copyright (C) 2008-2012 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#include <VBox/dis.h>
23	#include "DisasmInternal.h"
24	#include <iprt/string.h>
25	#include <iprt/assert.h>
26	#include <iprt/ctype.h>
27
28
29	/*******************************************************************************
30	* Global Variables *
31	*******************************************************************************/
32	static const char g_szSpaces[] =
33	" ";
34	static const char g_aszYasmRegGen8[20][5] =
35	{
36	"al\0\0", "cl\0\0", "dl\0\0", "bl\0\0", "ah\0\0", "ch\0\0", "dh\0\0", "bh\0\0", "r8b\0", "r9b\0", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b", "spl\0", "bpl\0", "sil\0", "dil\0"
37	};
38	static const char g_aszYasmRegGen16[16][5] =
39	{
40	"ax\0\0", "cx\0\0", "dx\0\0", "bx\0\0", "sp\0\0", "bp\0\0", "si\0\0", "di\0\0", "r8w\0", "r9w\0", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
41	};
42	static const char g_aszYasmRegGen1616[8][6] =
43	{
44	"bx+si", "bx+di", "bp+si", "bp+di", "si\0\0\0", "di\0\0\0", "bp\0\0\0", "bx\0\0\0"
45	};
46	static const char g_aszYasmRegGen32[16][5] =
47	{
48	"eax\0", "ecx\0", "edx\0", "ebx\0", "esp\0", "ebp\0", "esi\0", "edi\0", "r8d\0", "r9d\0", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
49	};
50	static const char g_aszYasmRegGen64[16][4] =
51	{
52	"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", "r8\0", "r9\0", "r10", "r11", "r12", "r13", "r14", "r15"
53	};
54	static const char g_aszYasmRegSeg[6][3] =
55	{
56	"es", "cs", "ss", "ds", "fs", "gs"
57	};
58	static const char g_aszYasmRegFP[8][4] =
59	{
60	"st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7"
61	};
62	static const char g_aszYasmRegMMX[8][4] =
63	{
64	"mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7"
65	};
66	static const char g_aszYasmRegXMM[16][6] =
67	{
68	"xmm0\0", "xmm1\0", "xmm2\0", "xmm3\0", "xmm4\0", "xmm5\0", "xmm6\0", "xmm7\0", "xmm8\0", "xmm9\0", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
69	};
70	static const char g_aszYasmRegYMM[16][6] =
71	{
72	"ymm0\0", "ymm1\0", "ymm2\0", "ymm3\0", "ymm4\0", "ymm5\0", "ymm6\0", "ymm7\0", "ymm8\0", "ymm9\0", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15"
73	};
74	static const char g_aszYasmRegCRx[16][5] =
75	{
76	"cr0\0", "cr1\0", "cr2\0", "cr3\0", "cr4\0", "cr5\0", "cr6\0", "cr7\0", "cr8\0", "cr9\0", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15"
77	};
78	static const char g_aszYasmRegDRx[16][5] =
79	{
80	"dr0\0", "dr1\0", "dr2\0", "dr3\0", "dr4\0", "dr5\0", "dr6\0", "dr7\0", "dr8\0", "dr9\0", "dr10", "dr11", "dr12", "dr13", "dr14", "dr15"
81	};
82	static const char g_aszYasmRegTRx[16][5] =
83	{
84	"tr0\0", "tr1\0", "tr2\0", "tr3\0", "tr4\0", "tr5\0", "tr6\0", "tr7\0", "tr8\0", "tr9\0", "tr10", "tr11", "tr12", "tr13", "tr14", "tr15"
85	};
86
87
88
89	/**
90	* Gets the base register name for the given parameter.
91	*
92	* @returns Pointer to the register name.
93	* @param pDis The disassembler state.
94	* @param pParam The parameter.
95	* @param pcchReg Where to store the length of the name.
96	*/
97	static const char disasmFormatYasmBaseReg(PCDISSTATE pDis, PCDISOPPARAM pParam, size_t pcchReg)
98	{
99	switch (pParam->fUse & ( DISUSE_REG_GEN8 \| DISUSE_REG_GEN16 \| DISUSE_REG_GEN32 \| DISUSE_REG_GEN64
100	\| DISUSE_REG_FP \| DISUSE_REG_MMX \| DISUSE_REG_XMM \| DISUSE_REG_YMM
101	\| DISUSE_REG_CR \| DISUSE_REG_DBG \| DISUSE_REG_SEG \| DISUSE_REG_TEST))
102
103	{
104	case DISUSE_REG_GEN8:
105	{
106	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen8));
107	const char *psz = g_aszYasmRegGen8[pParam->Base.idxGenReg];
108	*pcchReg = 2 + !!psz[2] + !!psz[3];
109	return psz;
110	}
111
112	case DISUSE_REG_GEN16:
113	{
114	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
115	const char *psz = g_aszYasmRegGen16[pParam->Base.idxGenReg];
116	*pcchReg = 2 + !!psz[2] + !!psz[3];
117	return psz;
118	}
119
120	case DISUSE_REG_GEN32:
121	{
122	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
123	const char *psz = g_aszYasmRegGen32[pParam->Base.idxGenReg];
124	*pcchReg = 2 + !!psz[2] + !!psz[3];
125	return psz;
126	}
127
128	case DISUSE_REG_GEN64:
129	{
130	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
131	const char *psz = g_aszYasmRegGen64[pParam->Base.idxGenReg];
132	*pcchReg = 2 + !!psz[2] + !!psz[3];
133	return psz;
134	}
135
136	case DISUSE_REG_FP:
137	{
138	Assert(pParam->Base.idxFpuReg < RT_ELEMENTS(g_aszYasmRegFP));
139	const char *psz = g_aszYasmRegFP[pParam->Base.idxFpuReg];
140	*pcchReg = 3;
141	return psz;
142	}
143
144	case DISUSE_REG_MMX:
145	{
146	Assert(pParam->Base.idxMmxReg < RT_ELEMENTS(g_aszYasmRegMMX));
147	const char *psz = g_aszYasmRegMMX[pParam->Base.idxMmxReg];
148	*pcchReg = 3;
149	return psz;
150	}
151
152	case DISUSE_REG_XMM:
153	{
154	Assert(pParam->Base.idxXmmReg < RT_ELEMENTS(g_aszYasmRegXMM));
155	const char *psz = g_aszYasmRegXMM[pParam->Base.idxXmmReg];
156	*pcchReg = 4 + !!psz[4];
157	return psz;
158	}
159
160	case DISUSE_REG_YMM:
161	{
162	Assert(pParam->Base.idxYmmReg < RT_ELEMENTS(g_aszYasmRegYMM));
163	const char *psz = g_aszYasmRegYMM[pParam->Base.idxYmmReg];
164	*pcchReg = 4 + !!psz[4];
165	return psz;
166	}
167
168	case DISUSE_REG_CR:
169	{
170	Assert(pParam->Base.idxCtrlReg < RT_ELEMENTS(g_aszYasmRegCRx));
171	const char *psz = g_aszYasmRegCRx[pParam->Base.idxCtrlReg];
172	*pcchReg = 3;
173	return psz;
174	}
175
176	case DISUSE_REG_DBG:
177	{
178	Assert(pParam->Base.idxDbgReg < RT_ELEMENTS(g_aszYasmRegDRx));
179	const char *psz = g_aszYasmRegDRx[pParam->Base.idxDbgReg];
180	*pcchReg = 3;
181	return psz;
182	}
183
184	case DISUSE_REG_SEG:
185	{
186	Assert(pParam->Base.idxSegReg < RT_ELEMENTS(g_aszYasmRegCRx));
187	const char *psz = g_aszYasmRegSeg[pParam->Base.idxSegReg];
188	*pcchReg = 2;
189	return psz;
190	}
191
192	case DISUSE_REG_TEST:
193	{
194	Assert(pParam->Base.idxTestReg < RT_ELEMENTS(g_aszYasmRegTRx));
195	const char *psz = g_aszYasmRegTRx[pParam->Base.idxTestReg];
196	*pcchReg = 3;
197	return psz;
198	}
199
200	default:
201	AssertMsgFailed(("%#x\n", pParam->fUse));
202	*pcchReg = 3;
203	return "r??";
204	}
205	}
206
207
208	/**
209	* Gets the index register name for the given parameter.
210	*
211	* @returns The index register name.
212	* @param pDis The disassembler state.
213	* @param pParam The parameter.
214	* @param pcchReg Where to store the length of the name.
215	*/
216	static const char disasmFormatYasmIndexReg(PCDISSTATE pDis, PCDISOPPARAM pParam, size_t pcchReg)
217	{
218	switch (pDis->uAddrMode)
219	{
220	case DISCPUMODE_16BIT:
221	{
222	Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
223	const char *psz = g_aszYasmRegGen16[pParam->Index.idxGenReg];
224	*pcchReg = 2 + !!psz[2] + !!psz[3];
225	return psz;
226	}
227
228	case DISCPUMODE_32BIT:
229	{
230	Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
231	const char *psz = g_aszYasmRegGen32[pParam->Index.idxGenReg];
232	*pcchReg = 2 + !!psz[2] + !!psz[3];
233	return psz;
234	}
235
236	case DISCPUMODE_64BIT:
237	{
238	Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
239	const char *psz = g_aszYasmRegGen64[pParam->Index.idxGenReg];
240	*pcchReg = 2 + !!psz[2] + !!psz[3];
241	return psz;
242	}
243
244	default:
245	AssertMsgFailed(("%#x %#x\n", pParam->fUse, pDis->uAddrMode));
246	*pcchReg = 3;
247	return "r??";
248	}
249	}
250
251
252	/**
253	* Formats the current instruction in Yasm (/ Nasm) style.
254	*
255	*
256	* @returns The number of output characters. If this is >= cchBuf, then the content
257	* of pszBuf will be truncated.
258	* @param pDis Pointer to the disassembler state.
259	* @param pszBuf The output buffer.
260	* @param cchBuf The size of the output buffer.
261	* @param fFlags Format flags, see DIS_FORMAT_FLAGS_*.
262	* @param pfnGetSymbol Get symbol name for a jmp or call target address. Optional.
263	* @param pvUser User argument for pfnGetSymbol.
264	*/
265	DISDECL(size_t) DISFormatYasmEx(PCDISSTATE pDis, char *pszBuf, size_t cchBuf, uint32_t fFlags,
266	PFNDISGETSYMBOL pfnGetSymbol, void *pvUser)
267	{
268	/** @todo monitor and mwait aren't formatted correctly in 64-bit mode. */
269	/*
270	* Input validation and massaging.
271	*/
272	AssertPtr(pDis);
273	AssertPtrNull(pszBuf);
274	Assert(pszBuf \|\| !cchBuf);
275	AssertPtrNull(pfnGetSymbol);
276	AssertMsg(DIS_FMT_FLAGS_IS_VALID(fFlags), ("%#x\n", fFlags));
277	if (fFlags & DIS_FMT_FLAGS_ADDR_COMMENT)
278	fFlags = (fFlags & ~DIS_FMT_FLAGS_ADDR_LEFT) \| DIS_FMT_FLAGS_ADDR_RIGHT;
279	if (fFlags & DIS_FMT_FLAGS_BYTES_COMMENT)
280	fFlags = (fFlags & ~DIS_FMT_FLAGS_BYTES_LEFT) \| DIS_FMT_FLAGS_BYTES_RIGHT;
281
282	PCDISOPCODE const pOp = pDis->pCurInstr;
283
284	/*
285	* Output macros
286	*/
287	char *pszDst = pszBuf;
288	size_t cchDst = cchBuf;
289	size_t cchOutput = 0;
290	#define PUT_C(ch) \
291	do { \
292	cchOutput++; \
293	if (cchDst > 1) \
294	{ \
295	cchDst--; \
296	*pszDst++ = (ch); \
297	} \
298	} while (0)
299	#define PUT_STR(pszSrc, cchSrc) \
300	do { \
301	cchOutput += (cchSrc); \
302	if (cchDst > (cchSrc)) \
303	{ \
304	memcpy(pszDst, (pszSrc), (cchSrc)); \
305	pszDst += (cchSrc); \
306	cchDst -= (cchSrc); \
307	} \
308	else if (cchDst > 1) \
309	{ \
310	memcpy(pszDst, (pszSrc), cchDst - 1); \
311	pszDst += cchDst - 1; \
312	cchDst = 1; \
313	} \
314	} while (0)
315	#define PUT_SZ(sz) \
316	PUT_STR((sz), sizeof(sz) - 1)
317	#define PUT_SZ_STRICT(szStrict, szRelaxed) \
318	do { if (fFlags & DIS_FMT_FLAGS_STRICT) PUT_SZ(szStrict); else PUT_SZ(szRelaxed); } while (0)
319	#define PUT_PSZ(psz) \
320	do { const size_t cchTmp = strlen(psz); PUT_STR((psz), cchTmp); } while (0)
321	#define PUT_NUM(cch, fmt, num) \
322	do { \
323	cchOutput += (cch); \
324	if (cchDst > 1) \
325	{ \
326	const size_t cchTmp = RTStrPrintf(pszDst, cchDst, fmt, (num)); \
327	pszDst += cchTmp; \
328	cchDst -= cchTmp; \
329	Assert(cchTmp == (cch) \|\| cchDst == 1); \
330	} \
331	} while (0)
332	/** @todo add two flags for choosing between %X / %x and h / 0x. */
333	#define PUT_NUM_8(num) PUT_NUM(4, "0%02xh", (uint8_t)(num))
334	#define PUT_NUM_16(num) PUT_NUM(6, "0%04xh", (uint16_t)(num))
335	#define PUT_NUM_32(num) PUT_NUM(10, "0%08xh", (uint32_t)(num))
336	#define PUT_NUM_64(num) PUT_NUM(18, "0%016RX64h", (uint64_t)(num))
337
338	#define PUT_NUM_SIGN(cch, fmt, num, stype, utype) \
339	do { \
340	if ((stype)(num) >= 0) \
341	{ \
342	PUT_C('+'); \
343	PUT_NUM(cch, fmt, (utype)(num)); \
344	} \
345	else \
346	{ \
347	PUT_C('-'); \
348	PUT_NUM(cch, fmt, (utype)-(stype)(num)); \
349	} \
350	} while (0)
351	#define PUT_NUM_S8(num) PUT_NUM_SIGN(4, "0%02xh", num, int8_t, uint8_t)
352	#define PUT_NUM_S16(num) PUT_NUM_SIGN(6, "0%04xh", num, int16_t, uint16_t)
353	#define PUT_NUM_S32(num) PUT_NUM_SIGN(10, "0%08xh", num, int32_t, uint32_t)
354	#define PUT_NUM_S64(num) PUT_NUM_SIGN(18, "0%016RX64h", num, int64_t, uint64_t)
355
356	#define PUT_SYMBOL_TWO(a_rcSym, a_szStart, a_chEnd) \
357	do { \
358	if (RT_SUCCESS(a_rcSym)) \
359	{ \
360	PUT_SZ(a_szStart); \
361	PUT_PSZ(szSymbol); \
362	if (off != 0) \
363	{ \
364	if ((int8_t)off == off) \
365	PUT_NUM_S8(off); \
366	else if ((int16_t)off == off) \
367	PUT_NUM_S16(off); \
368	else if ((int32_t)off == off) \
369	PUT_NUM_S32(off); \
370	else \
371	PUT_NUM_S64(off); \
372	} \
373	PUT_C(a_chEnd); \
374	} \
375	} while (0)
376
377	#define PUT_SYMBOL(a_uSeg, a_uAddr, a_szStart, a_chEnd) \
378	do { \
379	if (pfnGetSymbol) \
380	{ \
381	int rcSym = pfnGetSymbol(pDis, a_uSeg, a_uAddr, szSymbol, sizeof(szSymbol), &off, pvUser); \
382	PUT_SYMBOL_TWO(rcSym, a_szStart, a_chEnd); \
383	} \
384	} while (0)
385
386
387	/*
388	* The address?
389	*/
390	if (fFlags & DIS_FMT_FLAGS_ADDR_LEFT)
391	{
392	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
393	if (pDis->uInstrAddr >= _4G)
394	PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
395	#endif
396	PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
397	PUT_C(' ');
398	}
399
400	/*
401	* The opcode bytes?
402	*/
403	if (fFlags & DIS_FMT_FLAGS_BYTES_LEFT)
404	{
405	size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
406	cchOutput += cchTmp;
407	if (cchDst > 1)
408	{
409	if (cchTmp <= cchDst)
410	{
411	cchDst -= cchTmp;
412	pszDst += cchTmp;
413	}
414	else
415	{
416	pszDst += cchDst - 1;
417	cchDst = 1;
418	}
419	}
420
421	/* Some padding to align the instruction. */
422	size_t cchPadding = (7 * (2 + !!(fFlags & DIS_FMT_FLAGS_BYTES_SPACED)))
423	+ !!(fFlags & DIS_FMT_FLAGS_BYTES_BRACKETS) * 2
424	+ 2;
425	cchPadding = cchTmp + 1 >= cchPadding ? 1 : cchPadding - cchTmp;
426	PUT_STR(g_szSpaces, cchPadding);
427	}
428
429
430	/*
431	* Filter out invalid opcodes first as they need special
432	* treatment. UD2 is an exception and should be handled normally.
433	*/
434	size_t const offInstruction = cchOutput;
435	if ( pOp->uOpcode == OP_INVALID
436	\|\| ( pOp->uOpcode == OP_ILLUD2
437	&& (pDis->fPrefix & DISPREFIX_LOCK)))
438	PUT_SZ("Illegal opcode");
439	else
440	{
441	/*
442	* Prefixes
443	*/
444	if (pDis->fPrefix & DISPREFIX_LOCK)
445	PUT_SZ("lock ");
446	if(pDis->fPrefix & DISPREFIX_REP)
447	PUT_SZ("rep ");
448	else if(pDis->fPrefix & DISPREFIX_REPNE)
449	PUT_SZ("repne ");
450
451	/*
452	* Adjust the format string to the correct mnemonic
453	* or to avoid things the assembler cannot handle correctly.
454	*/
455	char szTmpFmt[48];
456	const char *pszFmt = pOp->pszOpcode;
457	switch (pOp->uOpcode)
458	{
459	case OP_JECXZ:
460	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "jcxz %Jb" : pDis->uOpMode == DISCPUMODE_32BIT ? "jecxz %Jb" : "jrcxz %Jb";
461	break;
462	case OP_PUSHF:
463	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "pushfw" : pDis->uOpMode == DISCPUMODE_32BIT ? "pushfd" : "pushfq";
464	break;
465	case OP_POPF:
466	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "popfw" : pDis->uOpMode == DISCPUMODE_32BIT ? "popfd" : "popfq";
467	break;
468	case OP_PUSHA:
469	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "pushaw" : "pushad";
470	break;
471	case OP_POPA:
472	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "popaw" : "popad";
473	break;
474	case OP_INSB:
475	pszFmt = "insb";
476	break;
477	case OP_INSWD:
478	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "insw" : pDis->uOpMode == DISCPUMODE_32BIT ? "insd" : "insq";
479	break;
480	case OP_OUTSB:
481	pszFmt = "outsb";
482	break;
483	case OP_OUTSWD:
484	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "outsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "outsd" : "outsq";
485	break;
486	case OP_MOVSB:
487	pszFmt = "movsb";
488	break;
489	case OP_MOVSWD:
490	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "movsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "movsd" : "movsq";
491	break;
492	case OP_CMPSB:
493	pszFmt = "cmpsb";
494	break;
495	case OP_CMPWD:
496	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cmpsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "cmpsd" : "cmpsq";
497	break;
498	case OP_SCASB:
499	pszFmt = "scasb";
500	break;
501	case OP_SCASWD:
502	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "scasw" : pDis->uOpMode == DISCPUMODE_32BIT ? "scasd" : "scasq";
503	break;
504	case OP_LODSB:
505	pszFmt = "lodsb";
506	break;
507	case OP_LODSWD:
508	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "lodsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "lodsd" : "lodsq";
509	break;
510	case OP_STOSB:
511	pszFmt = "stosb";
512	break;
513	case OP_STOSWD:
514	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "stosw" : pDis->uOpMode == DISCPUMODE_32BIT ? "stosd" : "stosq";
515	break;
516	case OP_CBW:
517	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cbw" : pDis->uOpMode == DISCPUMODE_32BIT ? "cwde" : "cdqe";
518	break;
519	case OP_CWD:
520	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cwd" : pDis->uOpMode == DISCPUMODE_32BIT ? "cdq" : "cqo";
521	break;
522	case OP_SHL:
523	Assert(pszFmt[3] == '/');
524	pszFmt += 4;
525	break;
526	case OP_XLAT:
527	pszFmt = "xlatb";
528	break;
529	case OP_INT3:
530	pszFmt = "int3";
531	break;
532
533	/*
534	* Don't know how to tell yasm to generate complicated nop stuff, so 'db' it.
535	*/
536	case OP_NOP:
537	if (pDis->bOpCode == 0x90)
538	/* fine, fine */;
539	else if (pszFmt[sizeof("nop %Ev") - 1] == '/' && pszFmt[sizeof("nop %Ev")] == 'p')
540	pszFmt = "prefetch %Eb";
541	else if (pDis->bOpCode == 0x1f)
542	{
543	Assert(pDis->cbInstr >= 3);
544	PUT_SZ("db 00fh, 01fh,");
545	PUT_NUM_8(MAKE_MODRM(pDis->ModRM.Bits.Mod, pDis->ModRM.Bits.Reg, pDis->ModRM.Bits.Rm));
546	for (unsigned i = 3; i < pDis->cbInstr; i++)
547	{
548	PUT_C(',');
549	PUT_NUM_8(0x90); ///@todo fixme.
550	}
551	pszFmt = "";
552	}
553	break;
554
555	default:
556	/* ST(X) -> stX (floating point) */
557	if (*pszFmt == 'f' && strchr(pszFmt, '('))
558	{
559	char *pszFmtDst = szTmpFmt;
560	char ch;
561	do
562	{
563	ch = *pszFmt++;
564	if (ch == 'S' && pszFmt[0] == 'T' && pszFmt[1] == '(')
565	{
566	*pszFmtDst++ = 's';
567	*pszFmtDst++ = 't';
568	pszFmt += 2;
569	ch = *pszFmt;
570	Assert(pszFmt[1] == ')');
571	pszFmt += 2;
572	*pszFmtDst++ = ch;
573	}
574	else
575	*pszFmtDst++ = ch;
576	} while (ch != '\0');
577	pszFmt = szTmpFmt;
578	}
579	break;
580
581	/*
582	* Horrible hacks.
583	*/
584	case OP_FLD:
585	if (pDis->bOpCode == 0xdb) /* m80fp workaround. */
586	(int )&pDis->Param1.fParam &= ~0x1f; /* make it pure OP_PARM_M */
587	break;
588	case OP_LAR: /* hack w -> v, probably not correct. */
589	(int )&pDis->Param2.fParam &= ~0x1f;
590	(int )&pDis->Param2.fParam \|= OP_PARM_v;
591	break;
592	}
593
594	/*
595	* Formatting context and associated macros.
596	*/
597	PCDISOPPARAM pParam = &pDis->Param1;
598	int iParam = 1;
599
600	#define PUT_FAR() \
601	do { \
602	if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_p \
603	&& pOp->uOpcode != OP_LDS /* table bugs? */ \
604	&& pOp->uOpcode != OP_LES \
605	&& pOp->uOpcode != OP_LFS \
606	&& pOp->uOpcode != OP_LGS \
607	&& pOp->uOpcode != OP_LSS ) \
608	PUT_SZ("far "); \
609	} while (0)
610	/** @todo mov ah,ch ends up with a byte 'override'... - check if this wasn't fixed. */
611	/** @todo drop the work/dword/qword override when the src/dst is a register (except for movsx/movzx). */
612	#define PUT_SIZE_OVERRIDE() \
613	do { \
614	switch (OP_PARM_VSUBTYPE(pParam->fParam)) \
615	{ \
616	case OP_PARM_v: \
617	case OP_PARM_y: \
618	switch (pDis->uOpMode) \
619	{ \
620	case DISCPUMODE_16BIT: PUT_SZ("word "); break; \
621	case DISCPUMODE_32BIT: PUT_SZ("dword "); break; \
622	case DISCPUMODE_64BIT: PUT_SZ("qword "); break; \
623	default: break; \
624	} \
625	break; \
626	case OP_PARM_b: PUT_SZ("byte "); break; \
627	case OP_PARM_w: PUT_SZ("word "); break; \
628	case OP_PARM_d: PUT_SZ("dword "); break; \
629	case OP_PARM_q: PUT_SZ("qword "); break; \
630	case OP_PARM_ps: \
631	case OP_PARM_pd: \
632	case OP_PARM_x: if (VEXREG_IS256B(pDis->bVexDestReg)) { PUT_SZ("yword"); break; } \
633	case OP_PARM_ss: \
634	case OP_PARM_sd: \
635	case OP_PARM_dq: PUT_SZ("oword "); break; \
636	case OP_PARM_p: break; /* see PUT_FAR */ \
637	case OP_PARM_s: if (pParam->fUse & DISUSE_REG_FP) PUT_SZ("tword "); break; /* ?? */ \
638	case OP_PARM_z: break; \
639	case OP_PARM_NONE: \
640	if ( OP_PARM_VTYPE(pParam->fParam) == OP_PARM_M \
641	&& ((pParam->fUse & DISUSE_REG_FP) \|\| pOp->uOpcode == OP_FLD)) \
642	PUT_SZ("tword "); \
643	break; \
644	default: break; /no pointer type specified/necessary/ \
645	} \
646	} while (0)
647	static const char s_szSegPrefix[6][4] = { "es:", "cs:", "ss:", "ds:", "fs:", "gs:" };
648	#define PUT_SEGMENT_OVERRIDE() \
649	do { \
650	if (pDis->fPrefix & DISPREFIX_SEG) \
651	PUT_STR(s_szSegPrefix[pDis->idxSegPrefix], 3); \
652	} while (0)
653
654
655	/*
656	* Segment prefixing for instructions that doesn't do memory access.
657	*/
658	if ( (pDis->fPrefix & DISPREFIX_SEG)
659	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
660	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
661	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse))
662	{
663	PUT_STR(s_szSegPrefix[pDis->idxSegPrefix], 2);
664	PUT_C(' ');
665	}
666
667
668	/*
669	* The formatting loop.
670	*/
671	RTINTPTR off;
672	char szSymbol[128];
673	char ch;
674	while ((ch = *pszFmt++) != '\0')
675	{
676	if (ch == '%')
677	{
678	ch = *pszFmt++;
679	switch (ch)
680	{
681	/*
682	* ModRM - Register only.
683	*/
684	case 'C': /* Control register (ParseModRM / UseModRM). */
685	case 'D': /* Debug register (ParseModRM / UseModRM). */
686	case 'G': /* ModRM selects general register (ParseModRM / UseModRM). */
687	case 'S': /* ModRM byte selects a segment register (ParseModRM / UseModRM). */
688	case 'T': /* ModRM byte selects a test register (ParseModRM / UseModRM). */
689	case 'V': /* ModRM byte selects an XMM/SSE register (ParseModRM / UseModRM). */
690	case 'P': /* ModRM byte selects MMX register (ParseModRM / UseModRM). */
691	case 'H': /* The VEX.vvvv field of the VEX prefix selects a XMM/YMM register. */
692	{
693	pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
694	Assert(!(pParam->fUse & (DISUSE_INDEX \| DISUSE_SCALE) /* No SIB here... */));
695	Assert(!(pParam->fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32)));
696
697	size_t cchReg;
698	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
699	PUT_STR(pszReg, cchReg);
700	break;
701	}
702
703	/*
704	* ModRM - Register or memory.
705	*/
706	case 'E': /* ModRM specifies parameter (ParseModRM / UseModRM / UseSIB). */
707	case 'Q': /* ModRM byte selects MMX register or memory address (ParseModRM / UseModRM). */
708	case 'R': /* ModRM byte may only refer to a general register (ParseModRM / UseModRM). */
709	case 'W': /* ModRM byte selects an XMM/SSE register or a memory address (ParseModRM / UseModRM). */
710	case 'M': /* ModRM may only refer to memory (ParseModRM / UseModRM). */
711	{
712	pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
713
714	PUT_FAR();
715	uint32_t const fUse = pParam->fUse;
716	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
717	{
718	/* Work around mov seg,[mem16] and mov [mem16],seg as these always make a 16-bit mem
719	while the register variants deals with 16, 32 & 64 in the normal fashion. */
720	if ( pParam->fParam != OP_PARM_Ev
721	\|\| pOp->uOpcode != OP_MOV
722	\|\| ( pOp->fParam1 != OP_PARM_Sw
723	&& pOp->fParam2 != OP_PARM_Sw))
724	PUT_SIZE_OVERRIDE();
725	PUT_C('[');
726	}
727	if ( (fFlags & DIS_FMT_FLAGS_STRICT)
728	&& (fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32)))
729	{
730	if ( (fUse & DISUSE_DISPLACEMENT8)
731	&& !pParam->uDisp.i8)
732	PUT_SZ("byte ");
733	else if ( (fUse & DISUSE_DISPLACEMENT16)
734	&& (int8_t)pParam->uDisp.i16 == (int16_t)pParam->uDisp.i16)
735	PUT_SZ("word ");
736	else if ( (fUse & DISUSE_DISPLACEMENT32)
737	&& (int16_t)pParam->uDisp.i32 == (int32_t)pParam->uDisp.i32) //??
738	PUT_SZ("dword ");
739	else if ( (fUse & DISUSE_DISPLACEMENT64)
740	&& (pDis->SIB.Bits.Base != 5 \|\| pDis->ModRM.Bits.Mod != 0)
741	&& (int32_t)pParam->uDisp.i64 == (int64_t)pParam->uDisp.i64) //??
742	PUT_SZ("qword ");
743	}
744	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
745	PUT_SEGMENT_OVERRIDE();
746
747	bool fBase = (fUse & DISUSE_BASE) /* When exactly is DISUSE_BASE supposed to be set? disasmModRMReg doesn't set it. */
748	\|\| ( (fUse & ( DISUSE_REG_GEN8
749	\| DISUSE_REG_GEN16
750	\| DISUSE_REG_GEN32
751	\| DISUSE_REG_GEN64
752	\| DISUSE_REG_FP
753	\| DISUSE_REG_MMX
754	\| DISUSE_REG_XMM
755	\| DISUSE_REG_YMM
756	\| DISUSE_REG_CR
757	\| DISUSE_REG_DBG
758	\| DISUSE_REG_SEG
759	\| DISUSE_REG_TEST ))
760	&& !DISUSE_IS_EFFECTIVE_ADDR(fUse));
761	if (fBase)
762	{
763	size_t cchReg;
764	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
765	PUT_STR(pszReg, cchReg);
766	}
767
768	if (fUse & DISUSE_INDEX)
769	{
770	if (fBase)
771	PUT_C('+');
772
773	size_t cchReg;
774	const char *pszReg = disasmFormatYasmIndexReg(pDis, pParam, &cchReg);
775	PUT_STR(pszReg, cchReg);
776
777	if (fUse & DISUSE_SCALE)
778	{
779	PUT_C('*');
780	PUT_C('0' + pParam->uScale);
781	}
782	}
783	else
784	Assert(!(fUse & DISUSE_SCALE));
785
786	int64_t off2 = 0;
787	if (fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32))
788	{
789	if (fUse & DISUSE_DISPLACEMENT8)
790	off2 = pParam->uDisp.i8;
791	else if (fUse & DISUSE_DISPLACEMENT16)
792	off2 = pParam->uDisp.i16;
793	else if (fUse & (DISUSE_DISPLACEMENT32 \| DISUSE_RIPDISPLACEMENT32))
794	off2 = pParam->uDisp.i32;
795	else if (fUse & DISUSE_DISPLACEMENT64)
796	off2 = pParam->uDisp.i64;
797	else
798	{
799	AssertFailed();
800	off2 = 0;
801	}
802
803	if (fBase \|\| (fUse & DISUSE_INDEX))
804	{
805	PUT_C(off2 >= 0 ? '+' : '-');
806	if (off2 < 0)
807	off2 = -off2;
808	}
809	if (fUse & DISUSE_DISPLACEMENT8)
810	PUT_NUM_8( off2);
811	else if (fUse & DISUSE_DISPLACEMENT16)
812	PUT_NUM_16(off2);
813	else if (fUse & DISUSE_DISPLACEMENT32)
814	PUT_NUM_32(off2);
815	else if (fUse & DISUSE_DISPLACEMENT64)
816	PUT_NUM_64(off2);
817	else
818	{
819	PUT_NUM_32(off2);
820	PUT_SZ(" wrt rip"); //??
821	}
822	}
823
824	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
825	{
826	if (pfnGetSymbol && !fBase && !(fUse & DISUSE_INDEX) && off2 != 0)
827	PUT_SYMBOL((pDis->fPrefix & DISPREFIX_SEG)
828	? DIS_FMT_SEL_FROM_REG(pDis->idxSegPrefix)
829	: DIS_FMT_SEL_FROM_REG(DISSELREG_DS),
830	pDis->uAddrMode == DISCPUMODE_64BIT
831	? (uint64_t)off2
832	: pDis->uAddrMode == DISCPUMODE_32BIT
833	? (uint32_t)off2
834	: (uint16_t)off2,
835	" (=", ')');
836	PUT_C(']');
837	}
838	break;
839	}
840
841	case 'F': /* Eflags register (0 - popf/pushf only, avoided in adjustments above). */
842	AssertFailed();
843	break;
844
845	case 'I': /* Immediate data (ParseImmByte, ParseImmByteSX, ParseImmV, ParseImmUshort, ParseImmZ). */
846	Assert(pszFmt == 'b' \|\| pszFmt == 'v' \|\| pszFmt == 'w' \|\| pszFmt == 'z'); pszFmt++;
847	switch (pParam->fUse & ( DISUSE_IMMEDIATE8 \| DISUSE_IMMEDIATE16 \| DISUSE_IMMEDIATE32 \| DISUSE_IMMEDIATE64
848	\| DISUSE_IMMEDIATE16_SX8 \| DISUSE_IMMEDIATE32_SX8 \| DISUSE_IMMEDIATE64_SX8))
849	{
850	case DISUSE_IMMEDIATE8:
851	if ( (fFlags & DIS_FMT_FLAGS_STRICT)
852	&& ( (pOp->fParam1 >= OP_PARM_REG_GEN8_START && pOp->fParam1 <= OP_PARM_REG_GEN8_END)
853	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN8_START && pOp->fParam2 <= OP_PARM_REG_GEN8_END))
854	)
855	PUT_SZ("strict byte ");
856	PUT_NUM_8(pParam->uValue);
857	break;
858
859	case DISUSE_IMMEDIATE16:
860	if ( pDis->uCpuMode != pDis->uOpMode
861	\|\| ( (fFlags & DIS_FMT_FLAGS_STRICT)
862	&& ( (int8_t)pParam->uValue == (int16_t)pParam->uValue
863	\|\| (pOp->fParam1 >= OP_PARM_REG_GEN16_START && pOp->fParam1 <= OP_PARM_REG_GEN16_END)
864	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN16_START && pOp->fParam2 <= OP_PARM_REG_GEN16_END))
865	)
866	)
867	{
868	if (OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_b)
869	PUT_SZ_STRICT("strict byte ", "byte ");
870	else if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_v
871	\|\| OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_z)
872	PUT_SZ_STRICT("strict word ", "word ");
873	}
874	PUT_NUM_16(pParam->uValue);
875	break;
876
877	case DISUSE_IMMEDIATE16_SX8:
878	if ( !(pDis->fPrefix & DISPREFIX_OPSIZE)
879	\|\| pDis->pCurInstr->uOpcode != OP_PUSH)
880	PUT_SZ_STRICT("strict byte ", "byte ");
881	else
882	PUT_SZ("word ");
883	PUT_NUM_16(pParam->uValue);
884	break;
885
886	case DISUSE_IMMEDIATE32:
887	if ( pDis->uOpMode != (pDis->uCpuMode == DISCPUMODE_16BIT ? DISCPUMODE_16BIT : DISCPUMODE_32BIT) /* not perfect */
888	\|\| ( (fFlags & DIS_FMT_FLAGS_STRICT)
889	&& ( (int8_t)pParam->uValue == (int32_t)pParam->uValue
890	\|\| (pOp->fParam1 >= OP_PARM_REG_GEN32_START && pOp->fParam1 <= OP_PARM_REG_GEN32_END)
891	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN32_START && pOp->fParam2 <= OP_PARM_REG_GEN32_END))
892	)
893	)
894	{
895	if (OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_b)
896	PUT_SZ_STRICT("strict byte ", "byte ");
897	else if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_v
898	\|\| OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_z)
899	PUT_SZ_STRICT("strict dword ", "dword ");
900	}
901	PUT_NUM_32(pParam->uValue);
902	if (pDis->uCpuMode == DISCPUMODE_32BIT)
903	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uValue, " (=", ')');
904	break;
905
906	case DISUSE_IMMEDIATE32_SX8:
907	if ( !(pDis->fPrefix & DISPREFIX_OPSIZE)
908	\|\| pDis->pCurInstr->uOpcode != OP_PUSH)
909	PUT_SZ_STRICT("strict byte ", "byte ");
910	else
911	PUT_SZ("dword ");
912	PUT_NUM_32(pParam->uValue);
913	break;
914
915	case DISUSE_IMMEDIATE64_SX8:
916	if ( !(pDis->fPrefix & DISPREFIX_OPSIZE)
917	\|\| pDis->pCurInstr->uOpcode != OP_PUSH)
918	PUT_SZ_STRICT("strict byte ", "byte ");
919	else
920	PUT_SZ("qword ");
921	PUT_NUM_64(pParam->uValue);
922	break;
923
924	case DISUSE_IMMEDIATE64:
925	PUT_NUM_64(pParam->uValue);
926	break;
927
928	default:
929	AssertFailed();
930	break;
931	}
932	break;
933
934	case 'J': /* Relative jump offset (ParseImmBRel + ParseImmVRel). */
935	{
936	int32_t offDisplacement;
937	Assert(iParam == 1);
938	bool fPrefix = (fFlags & DIS_FMT_FLAGS_STRICT)
939	&& pOp->uOpcode != OP_CALL
940	&& pOp->uOpcode != OP_LOOP
941	&& pOp->uOpcode != OP_LOOPE
942	&& pOp->uOpcode != OP_LOOPNE
943	&& pOp->uOpcode != OP_JECXZ;
944	if (pOp->uOpcode == OP_CALL)
945	fFlags &= ~DIS_FMT_FLAGS_RELATIVE_BRANCH;
946
947	if (pParam->fUse & DISUSE_IMMEDIATE8_REL)
948	{
949	if (fPrefix)
950	PUT_SZ("short ");
951	offDisplacement = (int8_t)pParam->uValue;
952	Assert(*pszFmt == 'b'); pszFmt++;
953
954	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
955	PUT_NUM_S8(offDisplacement);
956	}
957	else if (pParam->fUse & DISUSE_IMMEDIATE16_REL)
958	{
959	if (fPrefix)
960	PUT_SZ("near ");
961	offDisplacement = (int16_t)pParam->uValue;
962	Assert(*pszFmt == 'v'); pszFmt++;
963
964	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
965	PUT_NUM_S16(offDisplacement);
966	}
967	else
968	{
969	if (fPrefix)
970	PUT_SZ("near ");
971	offDisplacement = (int32_t)pParam->uValue;
972	Assert(pParam->fUse & (DISUSE_IMMEDIATE32_REL \| DISUSE_IMMEDIATE64_REL));
973	Assert(*pszFmt == 'v'); pszFmt++;
974
975	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
976	PUT_NUM_S32(offDisplacement);
977	}
978	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
979	PUT_SZ(" (");
980
981	RTUINTPTR uTrgAddr = pDis->uInstrAddr + pDis->cbInstr + offDisplacement;
982	if (pDis->uCpuMode == DISCPUMODE_16BIT)
983	PUT_NUM_16(uTrgAddr);
984	else if (pDis->uCpuMode == DISCPUMODE_32BIT)
985	PUT_NUM_32(uTrgAddr);
986	else
987	PUT_NUM_64(uTrgAddr);
988
989	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
990	{
991	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " = ", ' ');
992	PUT_C(')');
993	}
994	else
995	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " (", ')');
996	break;
997	}
998
999	case 'A': /* Direct (jump/call) address (ParseImmAddr). */
1000	{
1001	Assert(*pszFmt == 'p'); pszFmt++;
1002	PUT_FAR();
1003	PUT_SIZE_OVERRIDE();
1004	PUT_SEGMENT_OVERRIDE();
1005	int rc = VERR_SYMBOL_NOT_FOUND;
1006	switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 \| DISUSE_IMMEDIATE_ADDR_16_32 \| DISUSE_DISPLACEMENT64 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT16))
1007	{
1008	case DISUSE_IMMEDIATE_ADDR_16_16:
1009	PUT_NUM_16(pParam->uValue >> 16);
1010	PUT_C(':');
1011	PUT_NUM_16(pParam->uValue);
1012	if (pfnGetSymbol)
1013	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1014	break;
1015	case DISUSE_IMMEDIATE_ADDR_16_32:
1016	PUT_NUM_16(pParam->uValue >> 32);
1017	PUT_C(':');
1018	PUT_NUM_32(pParam->uValue);
1019	if (pfnGetSymbol)
1020	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1021	break;
1022	case DISUSE_DISPLACEMENT16:
1023	PUT_NUM_16(pParam->uValue);
1024	if (pfnGetSymbol)
1025	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1026	break;
1027	case DISUSE_DISPLACEMENT32:
1028	PUT_NUM_32(pParam->uValue);
1029	if (pfnGetSymbol)
1030	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1031	break;
1032	case DISUSE_DISPLACEMENT64:
1033	PUT_NUM_64(pParam->uValue);
1034	if (pfnGetSymbol)
1035	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint64_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1036	break;
1037	default:
1038	AssertFailed();
1039	break;
1040	}
1041
1042	PUT_SYMBOL_TWO(rc, " [", ']');
1043	break;
1044	}
1045
1046	case 'O': /* No ModRM byte (ParseImmAddr). */
1047	{
1048	Assert(pszFmt == 'b' \|\| pszFmt == 'v'); pszFmt++;
1049	PUT_FAR();
1050	PUT_SIZE_OVERRIDE();
1051	PUT_C('[');
1052	PUT_SEGMENT_OVERRIDE();
1053	int rc = VERR_SYMBOL_NOT_FOUND;
1054	switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 \| DISUSE_IMMEDIATE_ADDR_16_32 \| DISUSE_DISPLACEMENT64 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT16))
1055	{
1056	case DISUSE_IMMEDIATE_ADDR_16_16:
1057	PUT_NUM_16(pParam->uValue >> 16);
1058	PUT_C(':');
1059	PUT_NUM_16(pParam->uValue);
1060	if (pfnGetSymbol)
1061	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1062	break;
1063	case DISUSE_IMMEDIATE_ADDR_16_32:
1064	PUT_NUM_16(pParam->uValue >> 32);
1065	PUT_C(':');
1066	PUT_NUM_32(pParam->uValue);
1067	if (pfnGetSymbol)
1068	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1069	break;
1070	case DISUSE_DISPLACEMENT16:
1071	PUT_NUM_16(pParam->uDisp.i16);
1072	if (pfnGetSymbol)
1073	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u16, szSymbol, sizeof(szSymbol), &off, pvUser);
1074	break;
1075	case DISUSE_DISPLACEMENT32:
1076	PUT_NUM_32(pParam->uDisp.i32);
1077	if (pfnGetSymbol)
1078	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u32, szSymbol, sizeof(szSymbol), &off, pvUser);
1079	break;
1080	case DISUSE_DISPLACEMENT64:
1081	PUT_NUM_64(pParam->uDisp.i64);
1082	if (pfnGetSymbol)
1083	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u64, szSymbol, sizeof(szSymbol), &off, pvUser);
1084	break;
1085	default:
1086	AssertFailed();
1087	break;
1088	}
1089	PUT_C(']');
1090
1091	PUT_SYMBOL_TWO(rc, " (", ')');
1092	break;
1093	}
1094
1095	case 'X': /* DS:SI (ParseXb, ParseXv). */
1096	case 'Y': /* ES:DI (ParseYb, ParseYv). */
1097	{
1098	Assert(pszFmt == 'b' \|\| pszFmt == 'v'); pszFmt++;
1099	PUT_FAR();
1100	PUT_SIZE_OVERRIDE();
1101	PUT_C('[');
1102	if (pParam->fUse & DISUSE_POINTER_DS_BASED)
1103	PUT_SZ("ds:");
1104	else
1105	PUT_SZ("es:");
1106
1107	size_t cchReg;
1108	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
1109	PUT_STR(pszReg, cchReg);
1110	PUT_C(']');
1111	break;
1112	}
1113
1114	case 'e': /* Register based on operand size (e.g. %eAX, %eAH) (ParseFixedReg). */
1115	{
1116	Assert(RT_C_IS_ALPHA(pszFmt[0]) && RT_C_IS_ALPHA(pszFmt[1]) && !RT_C_IS_ALPHA(pszFmt[2]));
1117	pszFmt += 2;
1118	size_t cchReg;
1119	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
1120	PUT_STR(pszReg, cchReg);
1121	break;
1122	}
1123
1124	default:
1125	AssertMsgFailed(("%c%s!\n", ch, pszFmt));
1126	break;
1127	}
1128	AssertMsg(pszFmt == ',' \|\| pszFmt == '\0', ("%c%s\n", ch, pszFmt));
1129	}
1130	else
1131	{
1132	PUT_C(ch);
1133	if (ch == ',')
1134	{
1135	Assert(*pszFmt != ' ');
1136	PUT_C(' ');
1137	switch (++iParam)
1138	{
1139	case 2: pParam = &pDis->Param2; break;
1140	case 3: pParam = &pDis->Param3; break;
1141	case 4: pParam = &pDis->Param4; break;
1142	default: pParam = NULL; break;
1143	}
1144	}
1145	}
1146	} /* while more to format */
1147	}
1148
1149	/*
1150	* Any additional output to the right of the instruction?
1151	*/
1152	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
1153	{
1154	/* some up front padding. */
1155	size_t cchPadding = cchOutput - offInstruction;
1156	cchPadding = cchPadding + 1 >= 42 ? 1 : 42 - cchPadding;
1157	PUT_STR(g_szSpaces, cchPadding);
1158
1159	/* comment? */
1160	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
1161	PUT_SZ(";");
1162
1163	/*
1164	* The address?
1165	*/
1166	if (fFlags & DIS_FMT_FLAGS_ADDR_RIGHT)
1167	{
1168	PUT_C(' ');
1169	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
1170	if (pDis->uInstrAddr >= _4G)
1171	PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
1172	#endif
1173	PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
1174	}
1175
1176	/*
1177	* Opcode bytes?
1178	*/
1179	if (fFlags & DIS_FMT_FLAGS_BYTES_RIGHT)
1180	{
1181	PUT_C(' ');
1182	size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
1183	cchOutput += cchTmp;
1184	if (cchTmp >= cchDst)
1185	cchTmp = cchDst - (cchDst != 0);
1186	cchDst -= cchTmp;
1187	pszDst += cchTmp;
1188	}
1189	}
1190
1191	/*
1192	* Terminate it - on overflow we'll have reserved one byte for this.
1193	*/
1194	if (cchDst > 0)
1195	*pszDst = '\0';
1196	else
1197	Assert(!cchBuf);
1198
1199	/* clean up macros */
1200	#undef PUT_PSZ
1201	#undef PUT_SZ
1202	#undef PUT_STR
1203	#undef PUT_C
1204	return cchOutput;
1205	}
1206
1207
1208	/**
1209	* Formats the current instruction in Yasm (/ Nasm) style.
1210	*
1211	* This is a simplified version of DISFormatYasmEx() provided for your convenience.
1212	*
1213	*
1214	* @returns The number of output characters. If this is >= cchBuf, then the content
1215	* of pszBuf will be truncated.
1216	* @param pDis Pointer to the disassembler state.
1217	* @param pszBuf The output buffer.
1218	* @param cchBuf The size of the output buffer.
1219	*/
1220	DISDECL(size_t) DISFormatYasm(PCDISSTATE pDis, char *pszBuf, size_t cchBuf)
1221	{
1222	return DISFormatYasmEx(pDis, pszBuf, cchBuf, 0 /* fFlags /, NULL / pfnGetSymbol /, NULL / pvUser */);
1223	}
1224
1225
1226	/**
1227	* Checks if the encoding of the given disassembled instruction is something we
1228	* can never get YASM to produce.
1229	*
1230	* @returns true if it's odd, false if it isn't.
1231	* @param pDis The disassembler output. The byte fetcher callback will
1232	* be used if present as we might need to fetch opcode
1233	* bytes.
1234	*/
1235	DISDECL(bool) DISFormatYasmIsOddEncoding(PDISSTATE pDis)
1236	{
1237	/*
1238	* Mod rm + SIB: Check for duplicate EBP encodings that yasm won't use for very good reasons.
1239	*/
1240	if ( pDis->uAddrMode != DISCPUMODE_16BIT ///@todo correct?
1241	&& pDis->ModRM.Bits.Rm == 4
1242	&& pDis->ModRM.Bits.Mod != 3)
1243	{
1244	/* No scaled index SIB (index=4), except for ESP. */
1245	if ( pDis->SIB.Bits.Index == 4
1246	&& pDis->SIB.Bits.Base != 4)
1247	return true;
1248
1249	/* EBP + displacement */
1250	if ( pDis->ModRM.Bits.Mod != 0
1251	&& pDis->SIB.Bits.Base == 5
1252	&& pDis->SIB.Bits.Scale == 0)
1253	return true;
1254	}
1255
1256	/*
1257	* Seems to be an instruction alias here, but I cannot find any docs on it... hrmpf!
1258	*/
1259	if ( pDis->pCurInstr->uOpcode == OP_SHL
1260	&& pDis->ModRM.Bits.Reg == 6)
1261	return true;
1262
1263	/*
1264	* Check for multiple prefixes of the same kind.
1265	*/
1266	uint8_t off1stSeg = UINT8_MAX;
1267	uint8_t offOpSize = UINT8_MAX;
1268	uint8_t offAddrSize = UINT8_MAX;
1269	uint32_t fPrefixes = 0;
1270	for (uint32_t offOpcode = 0; offOpcode < RT_ELEMENTS(pDis->abInstr); offOpcode++)
1271	{
1272	uint32_t f;
1273	switch (pDis->abInstr[offOpcode])
1274	{
1275	case 0xf0:
1276	f = DISPREFIX_LOCK;
1277	break;
1278
1279	case 0xf2:
1280	case 0xf3:
1281	f = DISPREFIX_REP; /* yes, both */
1282	break;
1283
1284	case 0x2e:
1285	case 0x3e:
1286	case 0x26:
1287	case 0x36:
1288	case 0x64:
1289	case 0x65:
1290	if (off1stSeg == UINT8_MAX)
1291	off1stSeg = offOpcode;
1292	f = DISPREFIX_SEG;
1293	break;
1294
1295	case 0x66:
1296	if (offOpSize == UINT8_MAX)
1297	offOpSize = offOpcode;
1298	f = DISPREFIX_OPSIZE;
1299	break;
1300
1301	case 0x67:
1302	if (offAddrSize == UINT8_MAX)
1303	offAddrSize = offOpcode;
1304	f = DISPREFIX_ADDRSIZE;
1305	break;
1306
1307	case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
1308	case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
1309	f = pDis->uCpuMode == DISCPUMODE_64BIT ? DISPREFIX_REX : 0;
1310	break;
1311
1312	default:
1313	f = 0;
1314	break;
1315	}
1316	if (!f)
1317	break; /* done */
1318	if (fPrefixes & f)
1319	return true;
1320	fPrefixes \|= f;
1321	}
1322
1323	/* segment overrides are fun */
1324	if (fPrefixes & DISPREFIX_SEG)
1325	{
1326	/* no effective address which it may apply to. */
1327	Assert((pDis->fPrefix & DISPREFIX_SEG) \|\| pDis->uCpuMode == DISCPUMODE_64BIT);
1328	if ( !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
1329	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
1330	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse))
1331	return true;
1332
1333	/* Yasm puts the segment prefixes before the operand prefix with no
1334	way of overriding it. */
1335	if (offOpSize < off1stSeg)
1336	return true;
1337	}
1338
1339	/* fixed register + addr override doesn't go down all that well. */
1340	if (fPrefixes & DISPREFIX_ADDRSIZE)
1341	{
1342	Assert(pDis->fPrefix & DISPREFIX_ADDRSIZE);
1343	if ( pDis->pCurInstr->fParam3 == OP_PARM_NONE
1344	&& pDis->pCurInstr->fParam2 == OP_PARM_NONE
1345	&& ( pDis->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
1346	&& pDis->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END))
1347	return true;
1348	}
1349
1350	/* Almost all prefixes are bad for jumps. */
1351	if (fPrefixes)
1352	{
1353	switch (pDis->pCurInstr->uOpcode)
1354	{
1355	/* nop w/ prefix(es). */
1356	case OP_NOP:
1357	return true;
1358
1359	case OP_JMP:
1360	if ( pDis->pCurInstr->fParam1 != OP_PARM_Jb
1361	&& pDis->pCurInstr->fParam1 != OP_PARM_Jv)
1362	break;
1363	/* fall thru */
1364	case OP_JO:
1365	case OP_JNO:
1366	case OP_JC:
1367	case OP_JNC:
1368	case OP_JE:
1369	case OP_JNE:
1370	case OP_JBE:
1371	case OP_JNBE:
1372	case OP_JS:
1373	case OP_JNS:
1374	case OP_JP:
1375	case OP_JNP:
1376	case OP_JL:
1377	case OP_JNL:
1378	case OP_JLE:
1379	case OP_JNLE:
1380	/** @todo branch hinting 0x2e/0x3e... */
1381	return true;
1382	}
1383
1384	}
1385
1386	/* All but the segment prefix is bad news for push/pop. */
1387	if (fPrefixes & ~DISPREFIX_SEG)
1388	{
1389	switch (pDis->pCurInstr->uOpcode)
1390	{
1391	case OP_POP:
1392	case OP_PUSH:
1393	if ( pDis->pCurInstr->fParam1 >= OP_PARM_REG_SEG_START
1394	&& pDis->pCurInstr->fParam1 <= OP_PARM_REG_SEG_END)
1395	return true;
1396	if ( (fPrefixes & ~DISPREFIX_OPSIZE)
1397	&& pDis->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
1398	&& pDis->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END)
1399	return true;
1400	break;
1401
1402	case OP_POPA:
1403	case OP_POPF:
1404	case OP_PUSHA:
1405	case OP_PUSHF:
1406	if (fPrefixes & ~DISPREFIX_OPSIZE)
1407	return true;
1408	break;
1409	}
1410	}
1411
1412	/* Implicit 8-bit register instructions doesn't mix with operand size. */
1413	if ( (fPrefixes & DISPREFIX_OPSIZE)
1414	&& ( ( pDis->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
1415	&& pDis->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
1416	\|\| ( pDis->pCurInstr->fParam2 == OP_PARM_Gb /* r8 */
1417	&& pDis->pCurInstr->fParam1 == OP_PARM_Eb /* r8/mem8 */))
1418	)
1419	{
1420	switch (pDis->pCurInstr->uOpcode)
1421	{
1422	case OP_ADD:
1423	case OP_OR:
1424	case OP_ADC:
1425	case OP_SBB:
1426	case OP_AND:
1427	case OP_SUB:
1428	case OP_XOR:
1429	case OP_CMP:
1430	return true;
1431	default:
1432	break;
1433	}
1434	}
1435
1436	/* Instructions taking no address or operand which thus may be annoyingly
1437	difficult to format for yasm. */
1438	if (fPrefixes)
1439	{
1440	switch (pDis->pCurInstr->uOpcode)
1441	{
1442	case OP_STI:
1443	case OP_STC:
1444	case OP_CLI:
1445	case OP_CLD:
1446	case OP_CLC:
1447	case OP_INT:
1448	case OP_INT3:
1449	case OP_INTO:
1450	case OP_HLT:
1451	/** @todo Many more to can be added here. */
1452	return true;
1453	default:
1454	break;
1455	}
1456	}
1457
1458	/* FPU and other instructions that ignores operand size override. */
1459	if (fPrefixes & DISPREFIX_OPSIZE)
1460	{
1461	switch (pDis->pCurInstr->uOpcode)
1462	{
1463	/* FPU: */
1464	case OP_FIADD:
1465	case OP_FIMUL:
1466	case OP_FISUB:
1467	case OP_FISUBR:
1468	case OP_FIDIV:
1469	case OP_FIDIVR:
1470	/** @todo there are many more. */
1471	return true;
1472
1473	case OP_MOV:
1474	/** @todo could be that we're not disassembling these correctly. */
1475	if (pDis->pCurInstr->fParam1 == OP_PARM_Sw)
1476	return true;
1477	/** @todo what about the other way? */
1478	break;
1479
1480	default:
1481	break;
1482	}
1483	}
1484
1485
1486	/*
1487	* Check for the version of xyz reg,reg instruction that the assembler doesn't use.
1488	*
1489	* For example:
1490	* expected: 1aee sbb ch, dh ; SBB r8, r/m8
1491	* yasm: 18F5 sbb ch, dh ; SBB r/m8, r8
1492	*/
1493	if (pDis->ModRM.Bits.Mod == 3 /* reg,reg */)
1494	{
1495	switch (pDis->pCurInstr->uOpcode)
1496	{
1497	case OP_ADD:
1498	case OP_OR:
1499	case OP_ADC:
1500	case OP_SBB:
1501	case OP_AND:
1502	case OP_SUB:
1503	case OP_XOR:
1504	case OP_CMP:
1505	if ( ( pDis->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
1506	&& pDis->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
1507	\|\| ( pDis->pCurInstr->fParam1 == OP_PARM_Gv /* rX */
1508	&& pDis->pCurInstr->fParam2 == OP_PARM_Ev /* rX/memX */))
1509	return true;
1510
1511	/* 82 (see table A-6). */
1512	if (pDis->bOpCode == 0x82)
1513	return true;
1514	break;
1515
1516	/* ff /0, fe /0, ff /1, fe /0 */
1517	case OP_DEC:
1518	case OP_INC:
1519	return true;
1520
1521	case OP_POP:
1522	case OP_PUSH:
1523	Assert(pDis->bOpCode == 0x8f);
1524	return true;
1525
1526	case OP_MOV:
1527	if ( pDis->bOpCode == 0x8a
1528	\|\| pDis->bOpCode == 0x8b)
1529	return true;
1530	break;
1531
1532	default:
1533	break;
1534	}
1535	}
1536
1537	/* shl eax,1 will be assembled to the form without the immediate byte. */
1538	if ( pDis->pCurInstr->fParam2 == OP_PARM_Ib
1539	&& (uint8_t)pDis->Param2.uValue == 1)
1540	{
1541	switch (pDis->pCurInstr->uOpcode)
1542	{
1543	case OP_SHL:
1544	case OP_SHR:
1545	case OP_SAR:
1546	case OP_RCL:
1547	case OP_RCR:
1548	case OP_ROL:
1549	case OP_ROR:
1550	return true;
1551	}
1552	}
1553
1554	/* And some more - see table A-6. */
1555	if (pDis->bOpCode == 0x82)
1556	{
1557	switch (pDis->pCurInstr->uOpcode)
1558	{
1559	case OP_ADD:
1560	case OP_OR:
1561	case OP_ADC:
1562	case OP_SBB:
1563	case OP_AND:
1564	case OP_SUB:
1565	case OP_XOR:
1566	case OP_CMP:
1567	return true;
1568	break;
1569	}
1570	}
1571
1572
1573	/* check for REX.X = 1 without SIB. */
1574
1575	/* Yasm encodes setnbe al with /2 instead of /0 like the AMD manual
1576	says (intel doesn't appear to care). */
1577	switch (pDis->pCurInstr->uOpcode)
1578	{
1579	case OP_SETO:
1580	case OP_SETNO:
1581	case OP_SETC:
1582	case OP_SETNC:
1583	case OP_SETE:
1584	case OP_SETNE:
1585	case OP_SETBE:
1586	case OP_SETNBE:
1587	case OP_SETS:
1588	case OP_SETNS:
1589	case OP_SETP:
1590	case OP_SETNP:
1591	case OP_SETL:
1592	case OP_SETNL:
1593	case OP_SETLE:
1594	case OP_SETNLE:
1595	AssertMsg(pDis->bOpCode >= 0x90 && pDis->bOpCode <= 0x9f, ("%#x\n", pDis->bOpCode));
1596	if (pDis->ModRM.Bits.Reg != 2)
1597	return true;
1598	break;
1599	}
1600
1601	/*
1602	* The MOVZX reg32,mem16 instruction without an operand size prefix
1603	* doesn't quite make sense...
1604	*/
1605	if ( pDis->pCurInstr->uOpcode == OP_MOVZX
1606	&& pDis->bOpCode == 0xB7
1607	&& (pDis->uCpuMode == DISCPUMODE_16BIT) != !!(fPrefixes & DISPREFIX_OPSIZE))
1608	return true;
1609
1610	return false;
1611	}
1612

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source: vbox/trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp@ 53114

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