VirtualBox

source: vbox/trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp@ 59077

Last change on this file since 59077 was 57358, checked in by vboxsync, 9 years ago

*: scm cleanup run.

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1/* $Id: DisasmFormatYasm.cpp 57358 2015-08-14 15:16:38Z vboxsync $ */
2/** @file
3 * VBox Disassembler - Yasm(/Nasm) Style Formatter.
4 */
5
6/*
7 * Copyright (C) 2008-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#include <VBox/dis.h>
23#include "DisasmInternal.h"
24#include <iprt/string.h>
25#include <iprt/assert.h>
26#include <iprt/ctype.h>
27
28
29/*********************************************************************************************************************************
30* Global Variables *
31*********************************************************************************************************************************/
32static const char g_szSpaces[] =
33" ";
34static const char g_aszYasmRegGen8[20][5] =
35{
36 "al\0\0", "cl\0\0", "dl\0\0", "bl\0\0", "ah\0\0", "ch\0\0", "dh\0\0", "bh\0\0", "r8b\0", "r9b\0", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b", "spl\0", "bpl\0", "sil\0", "dil\0"
37};
38static const char g_aszYasmRegGen16[16][5] =
39{
40 "ax\0\0", "cx\0\0", "dx\0\0", "bx\0\0", "sp\0\0", "bp\0\0", "si\0\0", "di\0\0", "r8w\0", "r9w\0", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
41};
42static const char g_aszYasmRegGen1616[8][6] =
43{
44 "bx+si", "bx+di", "bp+si", "bp+di", "si\0\0\0", "di\0\0\0", "bp\0\0\0", "bx\0\0\0"
45};
46static const char g_aszYasmRegGen32[16][5] =
47{
48 "eax\0", "ecx\0", "edx\0", "ebx\0", "esp\0", "ebp\0", "esi\0", "edi\0", "r8d\0", "r9d\0", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
49};
50static const char g_aszYasmRegGen64[16][4] =
51{
52 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", "r8\0", "r9\0", "r10", "r11", "r12", "r13", "r14", "r15"
53};
54static const char g_aszYasmRegSeg[6][3] =
55{
56 "es", "cs", "ss", "ds", "fs", "gs"
57};
58static const char g_aszYasmRegFP[8][4] =
59{
60 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7"
61};
62static const char g_aszYasmRegMMX[8][4] =
63{
64 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7"
65};
66static const char g_aszYasmRegXMM[16][6] =
67{
68 "xmm0\0", "xmm1\0", "xmm2\0", "xmm3\0", "xmm4\0", "xmm5\0", "xmm6\0", "xmm7\0", "xmm8\0", "xmm9\0", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
69};
70static const char g_aszYasmRegYMM[16][6] =
71{
72 "ymm0\0", "ymm1\0", "ymm2\0", "ymm3\0", "ymm4\0", "ymm5\0", "ymm6\0", "ymm7\0", "ymm8\0", "ymm9\0", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15"
73};
74static const char g_aszYasmRegCRx[16][5] =
75{
76 "cr0\0", "cr1\0", "cr2\0", "cr3\0", "cr4\0", "cr5\0", "cr6\0", "cr7\0", "cr8\0", "cr9\0", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15"
77};
78static const char g_aszYasmRegDRx[16][5] =
79{
80 "dr0\0", "dr1\0", "dr2\0", "dr3\0", "dr4\0", "dr5\0", "dr6\0", "dr7\0", "dr8\0", "dr9\0", "dr10", "dr11", "dr12", "dr13", "dr14", "dr15"
81};
82static const char g_aszYasmRegTRx[16][5] =
83{
84 "tr0\0", "tr1\0", "tr2\0", "tr3\0", "tr4\0", "tr5\0", "tr6\0", "tr7\0", "tr8\0", "tr9\0", "tr10", "tr11", "tr12", "tr13", "tr14", "tr15"
85};
86
87
88
89/**
90 * Gets the base register name for the given parameter.
91 *
92 * @returns Pointer to the register name.
93 * @param pDis The disassembler state.
94 * @param pParam The parameter.
95 * @param pcchReg Where to store the length of the name.
96 */
97static const char *disasmFormatYasmBaseReg(PCDISSTATE pDis, PCDISOPPARAM pParam, size_t *pcchReg)
98{
99 switch (pParam->fUse & ( DISUSE_REG_GEN8 | DISUSE_REG_GEN16 | DISUSE_REG_GEN32 | DISUSE_REG_GEN64
100 | DISUSE_REG_FP | DISUSE_REG_MMX | DISUSE_REG_XMM | DISUSE_REG_YMM
101 | DISUSE_REG_CR | DISUSE_REG_DBG | DISUSE_REG_SEG | DISUSE_REG_TEST))
102
103 {
104 case DISUSE_REG_GEN8:
105 {
106 Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen8));
107 const char *psz = g_aszYasmRegGen8[pParam->Base.idxGenReg];
108 *pcchReg = 2 + !!psz[2] + !!psz[3];
109 return psz;
110 }
111
112 case DISUSE_REG_GEN16:
113 {
114 Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
115 const char *psz = g_aszYasmRegGen16[pParam->Base.idxGenReg];
116 *pcchReg = 2 + !!psz[2] + !!psz[3];
117 return psz;
118 }
119
120 // VSIB
121 case DISUSE_REG_XMM | DISUSE_REG_GEN32:
122 case DISUSE_REG_YMM | DISUSE_REG_GEN32:
123 case DISUSE_REG_GEN32:
124 {
125 Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
126 const char *psz = g_aszYasmRegGen32[pParam->Base.idxGenReg];
127 *pcchReg = 2 + !!psz[2] + !!psz[3];
128 return psz;
129 }
130
131 // VSIB
132 case DISUSE_REG_XMM | DISUSE_REG_GEN64:
133 case DISUSE_REG_YMM | DISUSE_REG_GEN64:
134 case DISUSE_REG_GEN64:
135 {
136 Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
137 const char *psz = g_aszYasmRegGen64[pParam->Base.idxGenReg];
138 *pcchReg = 2 + !!psz[2] + !!psz[3];
139 return psz;
140 }
141
142 case DISUSE_REG_FP:
143 {
144 Assert(pParam->Base.idxFpuReg < RT_ELEMENTS(g_aszYasmRegFP));
145 const char *psz = g_aszYasmRegFP[pParam->Base.idxFpuReg];
146 *pcchReg = 3;
147 return psz;
148 }
149
150 case DISUSE_REG_MMX:
151 {
152 Assert(pParam->Base.idxMmxReg < RT_ELEMENTS(g_aszYasmRegMMX));
153 const char *psz = g_aszYasmRegMMX[pParam->Base.idxMmxReg];
154 *pcchReg = 3;
155 return psz;
156 }
157
158 case DISUSE_REG_XMM:
159 {
160 Assert(pParam->Base.idxXmmReg < RT_ELEMENTS(g_aszYasmRegXMM));
161 const char *psz = g_aszYasmRegXMM[pParam->Base.idxXmmReg];
162 *pcchReg = 4 + !!psz[4];
163 return psz;
164 }
165
166 case DISUSE_REG_YMM:
167 {
168 Assert(pParam->Base.idxYmmReg < RT_ELEMENTS(g_aszYasmRegYMM));
169 const char *psz = g_aszYasmRegYMM[pParam->Base.idxYmmReg];
170 *pcchReg = 4 + !!psz[4];
171 return psz;
172 }
173
174 case DISUSE_REG_CR:
175 {
176 Assert(pParam->Base.idxCtrlReg < RT_ELEMENTS(g_aszYasmRegCRx));
177 const char *psz = g_aszYasmRegCRx[pParam->Base.idxCtrlReg];
178 *pcchReg = 3;
179 return psz;
180 }
181
182 case DISUSE_REG_DBG:
183 {
184 Assert(pParam->Base.idxDbgReg < RT_ELEMENTS(g_aszYasmRegDRx));
185 const char *psz = g_aszYasmRegDRx[pParam->Base.idxDbgReg];
186 *pcchReg = 3;
187 return psz;
188 }
189
190 case DISUSE_REG_SEG:
191 {
192 Assert(pParam->Base.idxSegReg < RT_ELEMENTS(g_aszYasmRegCRx));
193 const char *psz = g_aszYasmRegSeg[pParam->Base.idxSegReg];
194 *pcchReg = 2;
195 return psz;
196 }
197
198 case DISUSE_REG_TEST:
199 {
200 Assert(pParam->Base.idxTestReg < RT_ELEMENTS(g_aszYasmRegTRx));
201 const char *psz = g_aszYasmRegTRx[pParam->Base.idxTestReg];
202 *pcchReg = 3;
203 return psz;
204 }
205
206 default:
207 AssertMsgFailed(("%#x\n", pParam->fUse));
208 *pcchReg = 3;
209 return "r??";
210 }
211}
212
213
214/**
215 * Gets the index register name for the given parameter.
216 *
217 * @returns The index register name.
218 * @param pDis The disassembler state.
219 * @param pParam The parameter.
220 * @param pcchReg Where to store the length of the name.
221 */
222static const char *disasmFormatYasmIndexReg(PCDISSTATE pDis, PCDISOPPARAM pParam, size_t *pcchReg)
223{
224 if (pParam->fUse & DISUSE_REG_XMM)
225 {
226 Assert(pParam->Index.idxXmmReg < RT_ELEMENTS(g_aszYasmRegXMM));
227 const char *psz = g_aszYasmRegXMM[pParam->Index.idxXmmReg];
228 *pcchReg = 4 + !!psz[4];
229 return psz;
230 }
231 else if (pParam->fUse & DISUSE_REG_YMM)
232 {
233 Assert(pParam->Index.idxYmmReg < RT_ELEMENTS(g_aszYasmRegYMM));
234 const char *psz = g_aszYasmRegYMM[pParam->Index.idxYmmReg];
235 *pcchReg = 4 + !!psz[4];
236 return psz;
237
238 }
239 else
240 switch (pDis->uAddrMode)
241 {
242 case DISCPUMODE_16BIT:
243 {
244 Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
245 const char *psz = g_aszYasmRegGen16[pParam->Index.idxGenReg];
246 *pcchReg = 2 + !!psz[2] + !!psz[3];
247 return psz;
248 }
249
250 case DISCPUMODE_32BIT:
251 {
252 Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
253 const char *psz = g_aszYasmRegGen32[pParam->Index.idxGenReg];
254 *pcchReg = 2 + !!psz[2] + !!psz[3];
255 return psz;
256 }
257
258 case DISCPUMODE_64BIT:
259 {
260 Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
261 const char *psz = g_aszYasmRegGen64[pParam->Index.idxGenReg];
262 *pcchReg = 2 + !!psz[2] + !!psz[3];
263 return psz;
264 }
265
266 default:
267 AssertMsgFailed(("%#x %#x\n", pParam->fUse, pDis->uAddrMode));
268 *pcchReg = 3;
269 return "r??";
270 }
271}
272
273
274/**
275 * Formats the current instruction in Yasm (/ Nasm) style.
276 *
277 *
278 * @returns The number of output characters. If this is >= cchBuf, then the content
279 * of pszBuf will be truncated.
280 * @param pDis Pointer to the disassembler state.
281 * @param pszBuf The output buffer.
282 * @param cchBuf The size of the output buffer.
283 * @param fFlags Format flags, see DIS_FORMAT_FLAGS_*.
284 * @param pfnGetSymbol Get symbol name for a jmp or call target address. Optional.
285 * @param pvUser User argument for pfnGetSymbol.
286 */
287DISDECL(size_t) DISFormatYasmEx(PCDISSTATE pDis, char *pszBuf, size_t cchBuf, uint32_t fFlags,
288 PFNDISGETSYMBOL pfnGetSymbol, void *pvUser)
289{
290/** @todo monitor and mwait aren't formatted correctly in 64-bit mode. */
291 /*
292 * Input validation and massaging.
293 */
294 AssertPtr(pDis);
295 AssertPtrNull(pszBuf);
296 Assert(pszBuf || !cchBuf);
297 AssertPtrNull(pfnGetSymbol);
298 AssertMsg(DIS_FMT_FLAGS_IS_VALID(fFlags), ("%#x\n", fFlags));
299 if (fFlags & DIS_FMT_FLAGS_ADDR_COMMENT)
300 fFlags = (fFlags & ~DIS_FMT_FLAGS_ADDR_LEFT) | DIS_FMT_FLAGS_ADDR_RIGHT;
301 if (fFlags & DIS_FMT_FLAGS_BYTES_COMMENT)
302 fFlags = (fFlags & ~DIS_FMT_FLAGS_BYTES_LEFT) | DIS_FMT_FLAGS_BYTES_RIGHT;
303
304 PCDISOPCODE const pOp = pDis->pCurInstr;
305
306 /*
307 * Output macros
308 */
309 char *pszDst = pszBuf;
310 size_t cchDst = cchBuf;
311 size_t cchOutput = 0;
312#define PUT_C(ch) \
313 do { \
314 cchOutput++; \
315 if (cchDst > 1) \
316 { \
317 cchDst--; \
318 *pszDst++ = (ch); \
319 } \
320 } while (0)
321#define PUT_STR(pszSrc, cchSrc) \
322 do { \
323 cchOutput += (cchSrc); \
324 if (cchDst > (cchSrc)) \
325 { \
326 memcpy(pszDst, (pszSrc), (cchSrc)); \
327 pszDst += (cchSrc); \
328 cchDst -= (cchSrc); \
329 } \
330 else if (cchDst > 1) \
331 { \
332 memcpy(pszDst, (pszSrc), cchDst - 1); \
333 pszDst += cchDst - 1; \
334 cchDst = 1; \
335 } \
336 } while (0)
337#define PUT_SZ(sz) \
338 PUT_STR((sz), sizeof(sz) - 1)
339#define PUT_SZ_STRICT(szStrict, szRelaxed) \
340 do { if (fFlags & DIS_FMT_FLAGS_STRICT) PUT_SZ(szStrict); else PUT_SZ(szRelaxed); } while (0)
341#define PUT_PSZ(psz) \
342 do { const size_t cchTmp = strlen(psz); PUT_STR((psz), cchTmp); } while (0)
343#define PUT_NUM(cch, fmt, num) \
344 do { \
345 cchOutput += (cch); \
346 if (cchDst > 1) \
347 { \
348 const size_t cchTmp = RTStrPrintf(pszDst, cchDst, fmt, (num)); \
349 pszDst += cchTmp; \
350 cchDst -= cchTmp; \
351 Assert(cchTmp == (cch) || cchDst == 1); \
352 } \
353 } while (0)
354/** @todo add two flags for choosing between %X / %x and h / 0x. */
355#define PUT_NUM_8(num) PUT_NUM(4, "0%02xh", (uint8_t)(num))
356#define PUT_NUM_16(num) PUT_NUM(6, "0%04xh", (uint16_t)(num))
357#define PUT_NUM_32(num) PUT_NUM(10, "0%08xh", (uint32_t)(num))
358#define PUT_NUM_64(num) PUT_NUM(18, "0%016RX64h", (uint64_t)(num))
359
360#define PUT_NUM_SIGN(cch, fmt, num, stype, utype) \
361 do { \
362 if ((stype)(num) >= 0) \
363 { \
364 PUT_C('+'); \
365 PUT_NUM(cch, fmt, (utype)(num)); \
366 } \
367 else \
368 { \
369 PUT_C('-'); \
370 PUT_NUM(cch, fmt, (utype)-(stype)(num)); \
371 } \
372 } while (0)
373#define PUT_NUM_S8(num) PUT_NUM_SIGN(4, "0%02xh", num, int8_t, uint8_t)
374#define PUT_NUM_S16(num) PUT_NUM_SIGN(6, "0%04xh", num, int16_t, uint16_t)
375#define PUT_NUM_S32(num) PUT_NUM_SIGN(10, "0%08xh", num, int32_t, uint32_t)
376#define PUT_NUM_S64(num) PUT_NUM_SIGN(18, "0%016RX64h", num, int64_t, uint64_t)
377
378#define PUT_SYMBOL_TWO(a_rcSym, a_szStart, a_chEnd) \
379 do { \
380 if (RT_SUCCESS(a_rcSym)) \
381 { \
382 PUT_SZ(a_szStart); \
383 PUT_PSZ(szSymbol); \
384 if (off != 0) \
385 { \
386 if ((int8_t)off == off) \
387 PUT_NUM_S8(off); \
388 else if ((int16_t)off == off) \
389 PUT_NUM_S16(off); \
390 else if ((int32_t)off == off) \
391 PUT_NUM_S32(off); \
392 else \
393 PUT_NUM_S64(off); \
394 } \
395 PUT_C(a_chEnd); \
396 } \
397 } while (0)
398
399#define PUT_SYMBOL(a_uSeg, a_uAddr, a_szStart, a_chEnd) \
400 do { \
401 if (pfnGetSymbol) \
402 { \
403 int rcSym = pfnGetSymbol(pDis, a_uSeg, a_uAddr, szSymbol, sizeof(szSymbol), &off, pvUser); \
404 PUT_SYMBOL_TWO(rcSym, a_szStart, a_chEnd); \
405 } \
406 } while (0)
407
408
409 /*
410 * The address?
411 */
412 if (fFlags & DIS_FMT_FLAGS_ADDR_LEFT)
413 {
414#if HC_ARCH_BITS == 64 || GC_ARCH_BITS == 64
415 if (pDis->uInstrAddr >= _4G)
416 PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
417#endif
418 PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
419 PUT_C(' ');
420 }
421
422 /*
423 * The opcode bytes?
424 */
425 if (fFlags & DIS_FMT_FLAGS_BYTES_LEFT)
426 {
427 size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
428 cchOutput += cchTmp;
429 if (cchDst > 1)
430 {
431 if (cchTmp <= cchDst)
432 {
433 cchDst -= cchTmp;
434 pszDst += cchTmp;
435 }
436 else
437 {
438 pszDst += cchDst - 1;
439 cchDst = 1;
440 }
441 }
442
443 /* Some padding to align the instruction. */
444 size_t cchPadding = (7 * (2 + !!(fFlags & DIS_FMT_FLAGS_BYTES_SPACED)))
445 + !!(fFlags & DIS_FMT_FLAGS_BYTES_BRACKETS) * 2
446 + 2;
447 cchPadding = cchTmp + 1 >= cchPadding ? 1 : cchPadding - cchTmp;
448 PUT_STR(g_szSpaces, cchPadding);
449 }
450
451
452 /*
453 * Filter out invalid opcodes first as they need special
454 * treatment. UD2 is an exception and should be handled normally.
455 */
456 size_t const offInstruction = cchOutput;
457 if ( pOp->uOpcode == OP_INVALID
458 || ( pOp->uOpcode == OP_ILLUD2
459 && (pDis->fPrefix & DISPREFIX_LOCK)))
460 PUT_SZ("Illegal opcode");
461 else
462 {
463 /*
464 * Prefixes
465 */
466 if (pDis->fPrefix & DISPREFIX_LOCK)
467 PUT_SZ("lock ");
468 if(pDis->fPrefix & DISPREFIX_REP)
469 PUT_SZ("rep ");
470 else if(pDis->fPrefix & DISPREFIX_REPNE)
471 PUT_SZ("repne ");
472
473 /*
474 * Adjust the format string to the correct mnemonic
475 * or to avoid things the assembler cannot handle correctly.
476 */
477 char szTmpFmt[48];
478 const char *pszFmt = pOp->pszOpcode;
479 switch (pOp->uOpcode)
480 {
481 case OP_JECXZ:
482 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "jcxz %Jb" : pDis->uOpMode == DISCPUMODE_32BIT ? "jecxz %Jb" : "jrcxz %Jb";
483 break;
484 case OP_PUSHF:
485 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "pushfw" : pDis->uOpMode == DISCPUMODE_32BIT ? "pushfd" : "pushfq";
486 break;
487 case OP_POPF:
488 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "popfw" : pDis->uOpMode == DISCPUMODE_32BIT ? "popfd" : "popfq";
489 break;
490 case OP_PUSHA:
491 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "pushaw" : "pushad";
492 break;
493 case OP_POPA:
494 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "popaw" : "popad";
495 break;
496 case OP_INSB:
497 pszFmt = "insb";
498 break;
499 case OP_INSWD:
500 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "insw" : pDis->uOpMode == DISCPUMODE_32BIT ? "insd" : "insq";
501 break;
502 case OP_OUTSB:
503 pszFmt = "outsb";
504 break;
505 case OP_OUTSWD:
506 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "outsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "outsd" : "outsq";
507 break;
508 case OP_MOVSB:
509 pszFmt = "movsb";
510 break;
511 case OP_MOVSWD:
512 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "movsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "movsd" : "movsq";
513 break;
514 case OP_CMPSB:
515 pszFmt = "cmpsb";
516 break;
517 case OP_CMPWD:
518 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cmpsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "cmpsd" : "cmpsq";
519 break;
520 case OP_SCASB:
521 pszFmt = "scasb";
522 break;
523 case OP_SCASWD:
524 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "scasw" : pDis->uOpMode == DISCPUMODE_32BIT ? "scasd" : "scasq";
525 break;
526 case OP_LODSB:
527 pszFmt = "lodsb";
528 break;
529 case OP_LODSWD:
530 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "lodsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "lodsd" : "lodsq";
531 break;
532 case OP_STOSB:
533 pszFmt = "stosb";
534 break;
535 case OP_STOSWD:
536 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "stosw" : pDis->uOpMode == DISCPUMODE_32BIT ? "stosd" : "stosq";
537 break;
538 case OP_CBW:
539 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cbw" : pDis->uOpMode == DISCPUMODE_32BIT ? "cwde" : "cdqe";
540 break;
541 case OP_CWD:
542 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cwd" : pDis->uOpMode == DISCPUMODE_32BIT ? "cdq" : "cqo";
543 break;
544 case OP_SHL:
545 Assert(pszFmt[3] == '/');
546 pszFmt += 4;
547 break;
548 case OP_XLAT:
549 pszFmt = "xlatb";
550 break;
551 case OP_INT3:
552 pszFmt = "int3";
553 break;
554
555 /*
556 * Don't know how to tell yasm to generate complicated nop stuff, so 'db' it.
557 */
558 case OP_NOP:
559 if (pDis->bOpCode == 0x90)
560 /* fine, fine */;
561 else if (pszFmt[sizeof("nop %Ev") - 1] == '/' && pszFmt[sizeof("nop %Ev")] == 'p')
562 pszFmt = "prefetch %Eb";
563 else if (pDis->bOpCode == 0x1f)
564 {
565 Assert(pDis->cbInstr >= 3);
566 PUT_SZ("db 00fh, 01fh,");
567 PUT_NUM_8(MAKE_MODRM(pDis->ModRM.Bits.Mod, pDis->ModRM.Bits.Reg, pDis->ModRM.Bits.Rm));
568 for (unsigned i = 3; i < pDis->cbInstr; i++)
569 {
570 PUT_C(',');
571 PUT_NUM_8(0x90); ///@todo fixme.
572 }
573 pszFmt = "";
574 }
575 break;
576
577 default:
578 /* ST(X) -> stX (floating point) */
579 if (*pszFmt == 'f' && strchr(pszFmt, '('))
580 {
581 char *pszFmtDst = szTmpFmt;
582 char ch;
583 do
584 {
585 ch = *pszFmt++;
586 if (ch == 'S' && pszFmt[0] == 'T' && pszFmt[1] == '(')
587 {
588 *pszFmtDst++ = 's';
589 *pszFmtDst++ = 't';
590 pszFmt += 2;
591 ch = *pszFmt;
592 Assert(pszFmt[1] == ')');
593 pszFmt += 2;
594 *pszFmtDst++ = ch;
595 }
596 else
597 *pszFmtDst++ = ch;
598 } while (ch != '\0');
599 pszFmt = szTmpFmt;
600 }
601 if (strchr ("#@&", *pszFmt))
602 {
603 const char *pszDelim = strchr(pszFmt, '/');
604 const char *pszSpace = (pszDelim ? strchr(pszDelim, ' ') : NULL);
605 if (pszDelim != NULL)
606 {
607 char *pszFmtDst = szTmpFmt;
608 if (pszSpace == NULL) pszSpace = strchr(pszDelim, 0);
609 if ( (*pszFmt == '#' && pDis->bVexWFlag)
610 || (*pszFmt == '@' && !VEXREG_IS256B(pDis->bVexDestReg))
611 || (*pszFmt == '&' && ( DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
612 || DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
613 || DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse)
614 || DISUSE_IS_EFFECTIVE_ADDR(pDis->Param4.fUse))))
615 {
616 strncpy(pszFmtDst, pszFmt + 1, pszDelim - pszFmt - 1);
617 pszFmtDst += pszDelim - pszFmt - 1;
618 }
619 else
620 {
621 strncpy(pszFmtDst, pszDelim + 1, pszSpace - pszDelim - 1);
622 pszFmtDst += pszSpace - pszDelim - 1;
623 }
624 strcpy (pszFmtDst, pszSpace);
625 pszFmt = szTmpFmt;
626 }
627 }
628 break;
629
630 /*
631 * Horrible hacks.
632 */
633 case OP_FLD:
634 if (pDis->bOpCode == 0xdb) /* m80fp workaround. */
635 *(int *)&pDis->Param1.fParam &= ~0x1f; /* make it pure OP_PARM_M */
636 break;
637 case OP_LAR: /* hack w -> v, probably not correct. */
638 *(int *)&pDis->Param2.fParam &= ~0x1f;
639 *(int *)&pDis->Param2.fParam |= OP_PARM_v;
640 break;
641 }
642
643 /*
644 * Formatting context and associated macros.
645 */
646 PCDISOPPARAM pParam = &pDis->Param1;
647 int iParam = 1;
648
649#define PUT_FAR() \
650 do { \
651 if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_p \
652 && pOp->uOpcode != OP_LDS /* table bugs? */ \
653 && pOp->uOpcode != OP_LES \
654 && pOp->uOpcode != OP_LFS \
655 && pOp->uOpcode != OP_LGS \
656 && pOp->uOpcode != OP_LSS ) \
657 PUT_SZ("far "); \
658 } while (0)
659 /** @todo mov ah,ch ends up with a byte 'override'... - check if this wasn't fixed. */
660 /** @todo drop the work/dword/qword override when the src/dst is a register (except for movsx/movzx). */
661#define PUT_SIZE_OVERRIDE() \
662 do { \
663 switch (OP_PARM_VSUBTYPE(pParam->fParam)) \
664 { \
665 case OP_PARM_v: \
666 case OP_PARM_y: \
667 switch (pDis->uOpMode) \
668 { \
669 case DISCPUMODE_16BIT: if (OP_PARM_VSUBTYPE(pParam->fParam) != OP_PARM_y) PUT_SZ("word "); break; \
670 case DISCPUMODE_32BIT: \
671 if (pDis->pCurInstr->uOpcode != OP_GATHER || pDis->bVexWFlag) { PUT_SZ("dword "); break; } \
672 case DISCPUMODE_64BIT: PUT_SZ("qword "); break; \
673 default: break; \
674 } \
675 break; \
676 case OP_PARM_b: PUT_SZ("byte "); break; \
677 case OP_PARM_w: \
678 if (OP_PARM_VTYPE(pParam->fParam) == OP_PARM_W || \
679 OP_PARM_VTYPE(pParam->fParam) == OP_PARM_M) \
680 { \
681 if (VEXREG_IS256B(pDis->bVexDestReg)) PUT_SZ("dword "); \
682 else PUT_SZ("word "); \
683 } \
684 break; \
685 case OP_PARM_d: \
686 if (OP_PARM_VTYPE(pParam->fParam) == OP_PARM_W || \
687 OP_PARM_VTYPE(pParam->fParam) == OP_PARM_M) \
688 { \
689 if (VEXREG_IS256B(pDis->bVexDestReg)) PUT_SZ("qword "); \
690 else PUT_SZ("dword "); \
691 } \
692 break; \
693 case OP_PARM_q: \
694 if (OP_PARM_VTYPE(pParam->fParam) == OP_PARM_W || \
695 OP_PARM_VTYPE(pParam->fParam) == OP_PARM_M) \
696 { \
697 if (VEXREG_IS256B(pDis->bVexDestReg)) PUT_SZ("oword "); \
698 else PUT_SZ("qword "); \
699 } \
700 break; \
701 case OP_PARM_ps: \
702 case OP_PARM_pd: \
703 case OP_PARM_x: if (VEXREG_IS256B(pDis->bVexDestReg)) { PUT_SZ("yword "); break; } \
704 case OP_PARM_ss: \
705 case OP_PARM_sd: \
706 case OP_PARM_dq: PUT_SZ("oword "); break; \
707 case OP_PARM_qq: PUT_SZ("yword "); break; \
708 case OP_PARM_p: break; /* see PUT_FAR */ \
709 case OP_PARM_s: if (pParam->fUse & DISUSE_REG_FP) PUT_SZ("tword "); break; /* ?? */ \
710 case OP_PARM_z: break; \
711 case OP_PARM_NONE: \
712 if ( OP_PARM_VTYPE(pParam->fParam) == OP_PARM_M \
713 && ((pParam->fUse & DISUSE_REG_FP) || pOp->uOpcode == OP_FLD)) \
714 PUT_SZ("tword "); \
715 break; \
716 default: break; /*no pointer type specified/necessary*/ \
717 } \
718 } while (0)
719 static const char s_szSegPrefix[6][4] = { "es:", "cs:", "ss:", "ds:", "fs:", "gs:" };
720#define PUT_SEGMENT_OVERRIDE() \
721 do { \
722 if (pDis->fPrefix & DISPREFIX_SEG) \
723 PUT_STR(s_szSegPrefix[pDis->idxSegPrefix], 3); \
724 } while (0)
725
726
727 /*
728 * Segment prefixing for instructions that doesn't do memory access.
729 */
730 if ( (pDis->fPrefix & DISPREFIX_SEG)
731 && !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
732 && !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
733 && !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse))
734 {
735 PUT_STR(s_szSegPrefix[pDis->idxSegPrefix], 2);
736 PUT_C(' ');
737 }
738
739
740 /*
741 * The formatting loop.
742 */
743 RTINTPTR off;
744 char szSymbol[128];
745 char ch;
746 while ((ch = *pszFmt++) != '\0')
747 {
748 if (ch == '%')
749 {
750 ch = *pszFmt++;
751 switch (ch)
752 {
753 /*
754 * ModRM - Register only.
755 */
756 case 'C': /* Control register (ParseModRM / UseModRM). */
757 case 'D': /* Debug register (ParseModRM / UseModRM). */
758 case 'G': /* ModRM selects general register (ParseModRM / UseModRM). */
759 case 'S': /* ModRM byte selects a segment register (ParseModRM / UseModRM). */
760 case 'T': /* ModRM byte selects a test register (ParseModRM / UseModRM). */
761 case 'V': /* ModRM byte selects an XMM/SSE register (ParseModRM / UseModRM). */
762 case 'P': /* ModRM byte selects MMX register (ParseModRM / UseModRM). */
763 case 'H': /* The VEX.vvvv field of the VEX prefix selects a XMM/YMM register. */
764 case 'L': /* The upper 4 bits of the 8-bit immediate selects a XMM/YMM register. */
765 {
766 pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
767 Assert(!(pParam->fUse & (DISUSE_INDEX | DISUSE_SCALE) /* No SIB here... */));
768 Assert(!(pParam->fUse & (DISUSE_DISPLACEMENT8 | DISUSE_DISPLACEMENT16 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT64 | DISUSE_RIPDISPLACEMENT32)));
769
770 size_t cchReg;
771 const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
772 PUT_STR(pszReg, cchReg);
773 break;
774 }
775
776 /*
777 * ModRM - Register or memory.
778 */
779 case 'E': /* ModRM specifies parameter (ParseModRM / UseModRM / UseSIB). */
780 case 'Q': /* ModRM byte selects MMX register or memory address (ParseModRM / UseModRM). */
781 case 'R': /* ModRM byte may only refer to a general register (ParseModRM / UseModRM). */
782 case 'W': /* ModRM byte selects an XMM/SSE register or a memory address (ParseModRM / UseModRM). */
783 case 'M': /* ModRM may only refer to memory (ParseModRM / UseModRM). */
784 {
785 pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
786
787 PUT_FAR();
788 uint32_t const fUse = pParam->fUse;
789 if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
790 {
791 /* Work around mov seg,[mem16] and mov [mem16],seg as these always make a 16-bit mem
792 while the register variants deals with 16, 32 & 64 in the normal fashion. */
793 if ( pParam->fParam != OP_PARM_Ev
794 || pOp->uOpcode != OP_MOV
795 || ( pOp->fParam1 != OP_PARM_Sw
796 && pOp->fParam2 != OP_PARM_Sw))
797 PUT_SIZE_OVERRIDE();
798 PUT_C('[');
799 }
800 if ( (fFlags & DIS_FMT_FLAGS_STRICT)
801 && (fUse & (DISUSE_DISPLACEMENT8 | DISUSE_DISPLACEMENT16 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT64 | DISUSE_RIPDISPLACEMENT32)))
802 {
803 if ( (fUse & DISUSE_DISPLACEMENT8)
804 && !pParam->uDisp.i8)
805 PUT_SZ("byte ");
806 else if ( (fUse & DISUSE_DISPLACEMENT16)
807 && (int8_t)pParam->uDisp.i16 == (int16_t)pParam->uDisp.i16)
808 PUT_SZ("word ");
809 else if ( (fUse & DISUSE_DISPLACEMENT32)
810 && (int16_t)pParam->uDisp.i32 == (int32_t)pParam->uDisp.i32) //??
811 PUT_SZ("dword ");
812 else if ( (fUse & DISUSE_DISPLACEMENT64)
813 && (pDis->SIB.Bits.Base != 5 || pDis->ModRM.Bits.Mod != 0)
814 && (int32_t)pParam->uDisp.i64 == (int64_t)pParam->uDisp.i64) //??
815 PUT_SZ("qword ");
816 }
817 if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
818 PUT_SEGMENT_OVERRIDE();
819
820 bool fBase = (fUse & DISUSE_BASE) /* When exactly is DISUSE_BASE supposed to be set? disasmModRMReg doesn't set it. */
821 || ( (fUse & ( DISUSE_REG_GEN8
822 | DISUSE_REG_GEN16
823 | DISUSE_REG_GEN32
824 | DISUSE_REG_GEN64
825 | DISUSE_REG_FP
826 | DISUSE_REG_MMX
827 | DISUSE_REG_XMM
828 | DISUSE_REG_YMM
829 | DISUSE_REG_CR
830 | DISUSE_REG_DBG
831 | DISUSE_REG_SEG
832 | DISUSE_REG_TEST ))
833 && !DISUSE_IS_EFFECTIVE_ADDR(fUse));
834 if (fBase)
835 {
836 size_t cchReg;
837 const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
838 PUT_STR(pszReg, cchReg);
839 }
840
841 if (fUse & DISUSE_INDEX)
842 {
843 if (fBase)
844 PUT_C('+');
845
846 size_t cchReg;
847 const char *pszReg = disasmFormatYasmIndexReg(pDis, pParam, &cchReg);
848 PUT_STR(pszReg, cchReg);
849
850 if (fUse & DISUSE_SCALE)
851 {
852 PUT_C('*');
853 PUT_C('0' + pParam->uScale);
854 }
855 }
856 else
857 Assert(!(fUse & DISUSE_SCALE));
858
859 int64_t off2 = 0;
860 if (fUse & (DISUSE_DISPLACEMENT8 | DISUSE_DISPLACEMENT16 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT64 | DISUSE_RIPDISPLACEMENT32))
861 {
862 if (fUse & DISUSE_DISPLACEMENT8)
863 off2 = pParam->uDisp.i8;
864 else if (fUse & DISUSE_DISPLACEMENT16)
865 off2 = pParam->uDisp.i16;
866 else if (fUse & (DISUSE_DISPLACEMENT32 | DISUSE_RIPDISPLACEMENT32))
867 off2 = pParam->uDisp.i32;
868 else if (fUse & DISUSE_DISPLACEMENT64)
869 off2 = pParam->uDisp.i64;
870 else
871 {
872 AssertFailed();
873 off2 = 0;
874 }
875
876 int64_t off3 = off2;
877 if (fBase || (fUse & (DISUSE_INDEX | DISUSE_RIPDISPLACEMENT32)))
878 {
879 PUT_C(off3 >= 0 ? '+' : '-');
880 if (off3 < 0)
881 off3 = -off3;
882 }
883 if (fUse & DISUSE_DISPLACEMENT8)
884 PUT_NUM_8( off3);
885 else if (fUse & DISUSE_DISPLACEMENT16)
886 PUT_NUM_16(off3);
887 else if (fUse & DISUSE_DISPLACEMENT32)
888 PUT_NUM_32(off3);
889 else if (fUse & DISUSE_DISPLACEMENT64)
890 PUT_NUM_64(off3);
891 else
892 {
893 PUT_NUM_32(off3);
894 PUT_SZ(" wrt rip (");
895 off2 += pDis->uInstrAddr + pDis->cbInstr;
896 PUT_NUM_64(off2);
897 if (pfnGetSymbol)
898 PUT_SYMBOL((pDis->fPrefix & DISPREFIX_SEG)
899 ? DIS_FMT_SEL_FROM_REG(pDis->idxSegPrefix)
900 : DIS_FMT_SEL_FROM_REG(DISSELREG_DS),
901 pDis->uAddrMode == DISCPUMODE_64BIT
902 ? (uint64_t)off2
903 : pDis->uAddrMode == DISCPUMODE_32BIT
904 ? (uint32_t)off2
905 : (uint16_t)off2,
906 " = ",
907 ')');
908 else
909 PUT_C(')');
910 }
911 }
912
913 if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
914 {
915 if (pfnGetSymbol && !fBase && !(fUse & (DISUSE_INDEX | DISUSE_RIPDISPLACEMENT32)) && off2 != 0)
916 PUT_SYMBOL((pDis->fPrefix & DISPREFIX_SEG)
917 ? DIS_FMT_SEL_FROM_REG(pDis->idxSegPrefix)
918 : DIS_FMT_SEL_FROM_REG(DISSELREG_DS),
919 pDis->uAddrMode == DISCPUMODE_64BIT
920 ? (uint64_t)off2
921 : pDis->uAddrMode == DISCPUMODE_32BIT
922 ? (uint32_t)off2
923 : (uint16_t)off2,
924 " (=",
925 ')');
926 PUT_C(']');
927 }
928 break;
929 }
930
931 case 'F': /* Eflags register (0 - popf/pushf only, avoided in adjustments above). */
932 AssertFailed();
933 break;
934
935 case 'I': /* Immediate data (ParseImmByte, ParseImmByteSX, ParseImmV, ParseImmUshort, ParseImmZ). */
936 Assert(*pszFmt == 'b' || *pszFmt == 'v' || *pszFmt == 'w' || *pszFmt == 'z'); pszFmt++;
937 switch (pParam->fUse & ( DISUSE_IMMEDIATE8 | DISUSE_IMMEDIATE16 | DISUSE_IMMEDIATE32 | DISUSE_IMMEDIATE64
938 | DISUSE_IMMEDIATE16_SX8 | DISUSE_IMMEDIATE32_SX8 | DISUSE_IMMEDIATE64_SX8))
939 {
940 case DISUSE_IMMEDIATE8:
941 if ( (fFlags & DIS_FMT_FLAGS_STRICT)
942 && ( (pOp->fParam1 >= OP_PARM_REG_GEN8_START && pOp->fParam1 <= OP_PARM_REG_GEN8_END)
943 || (pOp->fParam2 >= OP_PARM_REG_GEN8_START && pOp->fParam2 <= OP_PARM_REG_GEN8_END))
944 )
945 PUT_SZ("strict byte ");
946 PUT_NUM_8(pParam->uValue);
947 break;
948
949 case DISUSE_IMMEDIATE16:
950 if ( pDis->uCpuMode != pDis->uOpMode
951 || ( (fFlags & DIS_FMT_FLAGS_STRICT)
952 && ( (int8_t)pParam->uValue == (int16_t)pParam->uValue
953 || (pOp->fParam1 >= OP_PARM_REG_GEN16_START && pOp->fParam1 <= OP_PARM_REG_GEN16_END)
954 || (pOp->fParam2 >= OP_PARM_REG_GEN16_START && pOp->fParam2 <= OP_PARM_REG_GEN16_END))
955 )
956 )
957 {
958 if (OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_b)
959 PUT_SZ_STRICT("strict byte ", "byte ");
960 else if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_v
961 || OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_z)
962 PUT_SZ_STRICT("strict word ", "word ");
963 }
964 PUT_NUM_16(pParam->uValue);
965 break;
966
967 case DISUSE_IMMEDIATE16_SX8:
968 if ( !(pDis->fPrefix & DISPREFIX_OPSIZE)
969 || pDis->pCurInstr->uOpcode != OP_PUSH)
970 PUT_SZ_STRICT("strict byte ", "byte ");
971 else
972 PUT_SZ("word ");
973 PUT_NUM_16(pParam->uValue);
974 break;
975
976 case DISUSE_IMMEDIATE32:
977 if ( pDis->uOpMode != (pDis->uCpuMode == DISCPUMODE_16BIT ? DISCPUMODE_16BIT : DISCPUMODE_32BIT) /* not perfect */
978 || ( (fFlags & DIS_FMT_FLAGS_STRICT)
979 && ( (int8_t)pParam->uValue == (int32_t)pParam->uValue
980 || (pOp->fParam1 >= OP_PARM_REG_GEN32_START && pOp->fParam1 <= OP_PARM_REG_GEN32_END)
981 || (pOp->fParam2 >= OP_PARM_REG_GEN32_START && pOp->fParam2 <= OP_PARM_REG_GEN32_END))
982 )
983 )
984 {
985 if (OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_b)
986 PUT_SZ_STRICT("strict byte ", "byte ");
987 else if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_v
988 || OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_z)
989 PUT_SZ_STRICT("strict dword ", "dword ");
990 }
991 PUT_NUM_32(pParam->uValue);
992 if (pDis->uCpuMode == DISCPUMODE_32BIT)
993 PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uValue, " (=", ')');
994 break;
995
996 case DISUSE_IMMEDIATE32_SX8:
997 if ( !(pDis->fPrefix & DISPREFIX_OPSIZE)
998 || pDis->pCurInstr->uOpcode != OP_PUSH)
999 PUT_SZ_STRICT("strict byte ", "byte ");
1000 else
1001 PUT_SZ("dword ");
1002 PUT_NUM_32(pParam->uValue);
1003 break;
1004
1005 case DISUSE_IMMEDIATE64_SX8:
1006 if ( !(pDis->fPrefix & DISPREFIX_OPSIZE)
1007 || pDis->pCurInstr->uOpcode != OP_PUSH)
1008 PUT_SZ_STRICT("strict byte ", "byte ");
1009 else
1010 PUT_SZ("qword ");
1011 PUT_NUM_64(pParam->uValue);
1012 break;
1013
1014 case DISUSE_IMMEDIATE64:
1015 PUT_NUM_64(pParam->uValue);
1016 break;
1017
1018 default:
1019 AssertFailed();
1020 break;
1021 }
1022 break;
1023
1024 case 'J': /* Relative jump offset (ParseImmBRel + ParseImmVRel). */
1025 {
1026 int32_t offDisplacement;
1027 Assert(iParam == 1);
1028 bool fPrefix = (fFlags & DIS_FMT_FLAGS_STRICT)
1029 && pOp->uOpcode != OP_CALL
1030 && pOp->uOpcode != OP_LOOP
1031 && pOp->uOpcode != OP_LOOPE
1032 && pOp->uOpcode != OP_LOOPNE
1033 && pOp->uOpcode != OP_JECXZ;
1034 if (pOp->uOpcode == OP_CALL)
1035 fFlags &= ~DIS_FMT_FLAGS_RELATIVE_BRANCH;
1036
1037 if (pParam->fUse & DISUSE_IMMEDIATE8_REL)
1038 {
1039 if (fPrefix)
1040 PUT_SZ("short ");
1041 offDisplacement = (int8_t)pParam->uValue;
1042 Assert(*pszFmt == 'b'); pszFmt++;
1043
1044 if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1045 PUT_NUM_S8(offDisplacement);
1046 }
1047 else if (pParam->fUse & DISUSE_IMMEDIATE16_REL)
1048 {
1049 if (fPrefix)
1050 PUT_SZ("near ");
1051 offDisplacement = (int16_t)pParam->uValue;
1052 Assert(*pszFmt == 'v'); pszFmt++;
1053
1054 if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1055 PUT_NUM_S16(offDisplacement);
1056 }
1057 else
1058 {
1059 if (fPrefix)
1060 PUT_SZ("near ");
1061 offDisplacement = (int32_t)pParam->uValue;
1062 Assert(pParam->fUse & (DISUSE_IMMEDIATE32_REL | DISUSE_IMMEDIATE64_REL));
1063 Assert(*pszFmt == 'v'); pszFmt++;
1064
1065 if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1066 PUT_NUM_S32(offDisplacement);
1067 }
1068 if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1069 PUT_SZ(" (");
1070
1071 RTUINTPTR uTrgAddr = pDis->uInstrAddr + pDis->cbInstr + offDisplacement;
1072 if (pDis->uCpuMode == DISCPUMODE_16BIT)
1073 PUT_NUM_16(uTrgAddr);
1074 else if (pDis->uCpuMode == DISCPUMODE_32BIT)
1075 PUT_NUM_32(uTrgAddr);
1076 else
1077 PUT_NUM_64(uTrgAddr);
1078
1079 if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1080 {
1081 PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " = ", ' ');
1082 PUT_C(')');
1083 }
1084 else
1085 PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " (", ')');
1086 break;
1087 }
1088
1089 case 'A': /* Direct (jump/call) address (ParseImmAddr). */
1090 {
1091 Assert(*pszFmt == 'p'); pszFmt++;
1092 PUT_FAR();
1093 PUT_SIZE_OVERRIDE();
1094 PUT_SEGMENT_OVERRIDE();
1095 int rc = VERR_SYMBOL_NOT_FOUND;
1096 switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 | DISUSE_IMMEDIATE_ADDR_16_32 | DISUSE_DISPLACEMENT64 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT16))
1097 {
1098 case DISUSE_IMMEDIATE_ADDR_16_16:
1099 PUT_NUM_16(pParam->uValue >> 16);
1100 PUT_C(':');
1101 PUT_NUM_16(pParam->uValue);
1102 if (pfnGetSymbol)
1103 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1104 break;
1105 case DISUSE_IMMEDIATE_ADDR_16_32:
1106 PUT_NUM_16(pParam->uValue >> 32);
1107 PUT_C(':');
1108 PUT_NUM_32(pParam->uValue);
1109 if (pfnGetSymbol)
1110 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1111 break;
1112 case DISUSE_DISPLACEMENT16:
1113 PUT_NUM_16(pParam->uValue);
1114 if (pfnGetSymbol)
1115 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1116 break;
1117 case DISUSE_DISPLACEMENT32:
1118 PUT_NUM_32(pParam->uValue);
1119 if (pfnGetSymbol)
1120 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1121 break;
1122 case DISUSE_DISPLACEMENT64:
1123 PUT_NUM_64(pParam->uValue);
1124 if (pfnGetSymbol)
1125 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint64_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1126 break;
1127 default:
1128 AssertFailed();
1129 break;
1130 }
1131
1132 PUT_SYMBOL_TWO(rc, " [", ']');
1133 break;
1134 }
1135
1136 case 'O': /* No ModRM byte (ParseImmAddr). */
1137 {
1138 Assert(*pszFmt == 'b' || *pszFmt == 'v'); pszFmt++;
1139 PUT_FAR();
1140 PUT_SIZE_OVERRIDE();
1141 PUT_C('[');
1142 PUT_SEGMENT_OVERRIDE();
1143 int rc = VERR_SYMBOL_NOT_FOUND;
1144 switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 | DISUSE_IMMEDIATE_ADDR_16_32 | DISUSE_DISPLACEMENT64 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT16))
1145 {
1146 case DISUSE_IMMEDIATE_ADDR_16_16:
1147 PUT_NUM_16(pParam->uValue >> 16);
1148 PUT_C(':');
1149 PUT_NUM_16(pParam->uValue);
1150 if (pfnGetSymbol)
1151 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1152 break;
1153 case DISUSE_IMMEDIATE_ADDR_16_32:
1154 PUT_NUM_16(pParam->uValue >> 32);
1155 PUT_C(':');
1156 PUT_NUM_32(pParam->uValue);
1157 if (pfnGetSymbol)
1158 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1159 break;
1160 case DISUSE_DISPLACEMENT16:
1161 PUT_NUM_16(pParam->uDisp.i16);
1162 if (pfnGetSymbol)
1163 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u16, szSymbol, sizeof(szSymbol), &off, pvUser);
1164 break;
1165 case DISUSE_DISPLACEMENT32:
1166 PUT_NUM_32(pParam->uDisp.i32);
1167 if (pfnGetSymbol)
1168 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u32, szSymbol, sizeof(szSymbol), &off, pvUser);
1169 break;
1170 case DISUSE_DISPLACEMENT64:
1171 PUT_NUM_64(pParam->uDisp.i64);
1172 if (pfnGetSymbol)
1173 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u64, szSymbol, sizeof(szSymbol), &off, pvUser);
1174 break;
1175 default:
1176 AssertFailed();
1177 break;
1178 }
1179 PUT_C(']');
1180
1181 PUT_SYMBOL_TWO(rc, " (", ')');
1182 break;
1183 }
1184
1185 case 'X': /* DS:SI (ParseXb, ParseXv). */
1186 case 'Y': /* ES:DI (ParseYb, ParseYv). */
1187 {
1188 Assert(*pszFmt == 'b' || *pszFmt == 'v'); pszFmt++;
1189 PUT_FAR();
1190 PUT_SIZE_OVERRIDE();
1191 PUT_C('[');
1192 if (pParam->fUse & DISUSE_POINTER_DS_BASED)
1193 PUT_SZ("ds:");
1194 else
1195 PUT_SZ("es:");
1196
1197 size_t cchReg;
1198 const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
1199 PUT_STR(pszReg, cchReg);
1200 PUT_C(']');
1201 break;
1202 }
1203
1204 case 'e': /* Register based on operand size (e.g. %eAX, %eAH) (ParseFixedReg). */
1205 {
1206 Assert(RT_C_IS_ALPHA(pszFmt[0]) && RT_C_IS_ALPHA(pszFmt[1]) && !RT_C_IS_ALPHA(pszFmt[2]));
1207 pszFmt += 2;
1208 size_t cchReg;
1209 const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
1210 PUT_STR(pszReg, cchReg);
1211 break;
1212 }
1213
1214 default:
1215 AssertMsgFailed(("%c%s!\n", ch, pszFmt));
1216 break;
1217 }
1218 AssertMsg(*pszFmt == ',' || *pszFmt == '\0', ("%c%s\n", ch, pszFmt));
1219 }
1220 else
1221 {
1222 PUT_C(ch);
1223 if (ch == ',')
1224 {
1225 Assert(*pszFmt != ' ');
1226 PUT_C(' ');
1227 switch (++iParam)
1228 {
1229 case 2: pParam = &pDis->Param2; break;
1230 case 3: pParam = &pDis->Param3; break;
1231 case 4: pParam = &pDis->Param4; break;
1232 default: pParam = NULL; break;
1233 }
1234 }
1235 }
1236 } /* while more to format */
1237 }
1238
1239 /*
1240 * Any additional output to the right of the instruction?
1241 */
1242 if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_ADDR_RIGHT))
1243 {
1244 /* some up front padding. */
1245 size_t cchPadding = cchOutput - offInstruction;
1246 cchPadding = cchPadding + 1 >= 42 ? 1 : 42 - cchPadding;
1247 PUT_STR(g_szSpaces, cchPadding);
1248
1249 /* comment? */
1250 if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_ADDR_RIGHT))
1251 PUT_SZ(";");
1252
1253 /*
1254 * The address?
1255 */
1256 if (fFlags & DIS_FMT_FLAGS_ADDR_RIGHT)
1257 {
1258 PUT_C(' ');
1259#if HC_ARCH_BITS == 64 || GC_ARCH_BITS == 64
1260 if (pDis->uInstrAddr >= _4G)
1261 PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
1262#endif
1263 PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
1264 }
1265
1266 /*
1267 * Opcode bytes?
1268 */
1269 if (fFlags & DIS_FMT_FLAGS_BYTES_RIGHT)
1270 {
1271 PUT_C(' ');
1272 size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
1273 cchOutput += cchTmp;
1274 if (cchTmp >= cchDst)
1275 cchTmp = cchDst - (cchDst != 0);
1276 cchDst -= cchTmp;
1277 pszDst += cchTmp;
1278 }
1279 }
1280
1281 /*
1282 * Terminate it - on overflow we'll have reserved one byte for this.
1283 */
1284 if (cchDst > 0)
1285 *pszDst = '\0';
1286 else
1287 Assert(!cchBuf);
1288
1289 /* clean up macros */
1290#undef PUT_PSZ
1291#undef PUT_SZ
1292#undef PUT_STR
1293#undef PUT_C
1294 return cchOutput;
1295}
1296
1297
1298/**
1299 * Formats the current instruction in Yasm (/ Nasm) style.
1300 *
1301 * This is a simplified version of DISFormatYasmEx() provided for your convenience.
1302 *
1303 *
1304 * @returns The number of output characters. If this is >= cchBuf, then the content
1305 * of pszBuf will be truncated.
1306 * @param pDis Pointer to the disassembler state.
1307 * @param pszBuf The output buffer.
1308 * @param cchBuf The size of the output buffer.
1309 */
1310DISDECL(size_t) DISFormatYasm(PCDISSTATE pDis, char *pszBuf, size_t cchBuf)
1311{
1312 return DISFormatYasmEx(pDis, pszBuf, cchBuf, 0 /* fFlags */, NULL /* pfnGetSymbol */, NULL /* pvUser */);
1313}
1314
1315
1316/**
1317 * Checks if the encoding of the given disassembled instruction is something we
1318 * can never get YASM to produce.
1319 *
1320 * @returns true if it's odd, false if it isn't.
1321 * @param pDis The disassembler output. The byte fetcher callback will
1322 * be used if present as we might need to fetch opcode
1323 * bytes.
1324 */
1325DISDECL(bool) DISFormatYasmIsOddEncoding(PDISSTATE pDis)
1326{
1327 /*
1328 * Mod rm + SIB: Check for duplicate EBP encodings that yasm won't use for very good reasons.
1329 */
1330 if ( pDis->uAddrMode != DISCPUMODE_16BIT ///@todo correct?
1331 && pDis->ModRM.Bits.Rm == 4
1332 && pDis->ModRM.Bits.Mod != 3)
1333 {
1334 /* No scaled index SIB (index=4), except for ESP. */
1335 if ( pDis->SIB.Bits.Index == 4
1336 && pDis->SIB.Bits.Base != 4)
1337 return true;
1338
1339 /* EBP + displacement */
1340 if ( pDis->ModRM.Bits.Mod != 0
1341 && pDis->SIB.Bits.Base == 5
1342 && pDis->SIB.Bits.Scale == 0)
1343 return true;
1344 }
1345
1346 /*
1347 * Seems to be an instruction alias here, but I cannot find any docs on it... hrmpf!
1348 */
1349 if ( pDis->pCurInstr->uOpcode == OP_SHL
1350 && pDis->ModRM.Bits.Reg == 6)
1351 return true;
1352
1353 /*
1354 * Check for multiple prefixes of the same kind.
1355 */
1356 uint8_t off1stSeg = UINT8_MAX;
1357 uint8_t offOpSize = UINT8_MAX;
1358 uint8_t offAddrSize = UINT8_MAX;
1359 uint32_t fPrefixes = 0;
1360 for (uint32_t offOpcode = 0; offOpcode < RT_ELEMENTS(pDis->abInstr); offOpcode++)
1361 {
1362 uint32_t f;
1363 switch (pDis->abInstr[offOpcode])
1364 {
1365 case 0xf0:
1366 f = DISPREFIX_LOCK;
1367 break;
1368
1369 case 0xf2:
1370 case 0xf3:
1371 f = DISPREFIX_REP; /* yes, both */
1372 break;
1373
1374 case 0x2e:
1375 case 0x3e:
1376 case 0x26:
1377 case 0x36:
1378 case 0x64:
1379 case 0x65:
1380 if (off1stSeg == UINT8_MAX)
1381 off1stSeg = offOpcode;
1382 f = DISPREFIX_SEG;
1383 break;
1384
1385 case 0x66:
1386 if (offOpSize == UINT8_MAX)
1387 offOpSize = offOpcode;
1388 f = DISPREFIX_OPSIZE;
1389 break;
1390
1391 case 0x67:
1392 if (offAddrSize == UINT8_MAX)
1393 offAddrSize = offOpcode;
1394 f = DISPREFIX_ADDRSIZE;
1395 break;
1396
1397 case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
1398 case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
1399 f = pDis->uCpuMode == DISCPUMODE_64BIT ? DISPREFIX_REX : 0;
1400 break;
1401
1402 default:
1403 f = 0;
1404 break;
1405 }
1406 if (!f)
1407 break; /* done */
1408 if (fPrefixes & f)
1409 return true;
1410 fPrefixes |= f;
1411 }
1412
1413 /* segment overrides are fun */
1414 if (fPrefixes & DISPREFIX_SEG)
1415 {
1416 /* no effective address which it may apply to. */
1417 Assert((pDis->fPrefix & DISPREFIX_SEG) || pDis->uCpuMode == DISCPUMODE_64BIT);
1418 if ( !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
1419 && !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
1420 && !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse))
1421 return true;
1422
1423 /* Yasm puts the segment prefixes before the operand prefix with no
1424 way of overriding it. */
1425 if (offOpSize < off1stSeg)
1426 return true;
1427 }
1428
1429 /* fixed register + addr override doesn't go down all that well. */
1430 if (fPrefixes & DISPREFIX_ADDRSIZE)
1431 {
1432 Assert(pDis->fPrefix & DISPREFIX_ADDRSIZE);
1433 if ( pDis->pCurInstr->fParam3 == OP_PARM_NONE
1434 && pDis->pCurInstr->fParam2 == OP_PARM_NONE
1435 && ( pDis->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
1436 && pDis->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END))
1437 return true;
1438 }
1439
1440 /* Almost all prefixes are bad for jumps. */
1441 if (fPrefixes)
1442 {
1443 switch (pDis->pCurInstr->uOpcode)
1444 {
1445 /* nop w/ prefix(es). */
1446 case OP_NOP:
1447 return true;
1448
1449 case OP_JMP:
1450 if ( pDis->pCurInstr->fParam1 != OP_PARM_Jb
1451 && pDis->pCurInstr->fParam1 != OP_PARM_Jv)
1452 break;
1453 /* fall thru */
1454 case OP_JO:
1455 case OP_JNO:
1456 case OP_JC:
1457 case OP_JNC:
1458 case OP_JE:
1459 case OP_JNE:
1460 case OP_JBE:
1461 case OP_JNBE:
1462 case OP_JS:
1463 case OP_JNS:
1464 case OP_JP:
1465 case OP_JNP:
1466 case OP_JL:
1467 case OP_JNL:
1468 case OP_JLE:
1469 case OP_JNLE:
1470 /** @todo branch hinting 0x2e/0x3e... */
1471 return true;
1472 }
1473
1474 }
1475
1476 /* All but the segment prefix is bad news for push/pop. */
1477 if (fPrefixes & ~DISPREFIX_SEG)
1478 {
1479 switch (pDis->pCurInstr->uOpcode)
1480 {
1481 case OP_POP:
1482 case OP_PUSH:
1483 if ( pDis->pCurInstr->fParam1 >= OP_PARM_REG_SEG_START
1484 && pDis->pCurInstr->fParam1 <= OP_PARM_REG_SEG_END)
1485 return true;
1486 if ( (fPrefixes & ~DISPREFIX_OPSIZE)
1487 && pDis->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
1488 && pDis->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END)
1489 return true;
1490 break;
1491
1492 case OP_POPA:
1493 case OP_POPF:
1494 case OP_PUSHA:
1495 case OP_PUSHF:
1496 if (fPrefixes & ~DISPREFIX_OPSIZE)
1497 return true;
1498 break;
1499 }
1500 }
1501
1502 /* Implicit 8-bit register instructions doesn't mix with operand size. */
1503 if ( (fPrefixes & DISPREFIX_OPSIZE)
1504 && ( ( pDis->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
1505 && pDis->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
1506 || ( pDis->pCurInstr->fParam2 == OP_PARM_Gb /* r8 */
1507 && pDis->pCurInstr->fParam1 == OP_PARM_Eb /* r8/mem8 */))
1508 )
1509 {
1510 switch (pDis->pCurInstr->uOpcode)
1511 {
1512 case OP_ADD:
1513 case OP_OR:
1514 case OP_ADC:
1515 case OP_SBB:
1516 case OP_AND:
1517 case OP_SUB:
1518 case OP_XOR:
1519 case OP_CMP:
1520 return true;
1521 default:
1522 break;
1523 }
1524 }
1525
1526 /* Instructions taking no address or operand which thus may be annoyingly
1527 difficult to format for yasm. */
1528 if (fPrefixes)
1529 {
1530 switch (pDis->pCurInstr->uOpcode)
1531 {
1532 case OP_STI:
1533 case OP_STC:
1534 case OP_CLI:
1535 case OP_CLD:
1536 case OP_CLC:
1537 case OP_INT:
1538 case OP_INT3:
1539 case OP_INTO:
1540 case OP_HLT:
1541 /** @todo Many more to can be added here. */
1542 return true;
1543 default:
1544 break;
1545 }
1546 }
1547
1548 /* FPU and other instructions that ignores operand size override. */
1549 if (fPrefixes & DISPREFIX_OPSIZE)
1550 {
1551 switch (pDis->pCurInstr->uOpcode)
1552 {
1553 /* FPU: */
1554 case OP_FIADD:
1555 case OP_FIMUL:
1556 case OP_FISUB:
1557 case OP_FISUBR:
1558 case OP_FIDIV:
1559 case OP_FIDIVR:
1560 /** @todo there are many more. */
1561 return true;
1562
1563 case OP_MOV:
1564 /** @todo could be that we're not disassembling these correctly. */
1565 if (pDis->pCurInstr->fParam1 == OP_PARM_Sw)
1566 return true;
1567 /** @todo what about the other way? */
1568 break;
1569
1570 default:
1571 break;
1572 }
1573 }
1574
1575
1576 /*
1577 * Check for the version of xyz reg,reg instruction that the assembler doesn't use.
1578 *
1579 * For example:
1580 * expected: 1aee sbb ch, dh ; SBB r8, r/m8
1581 * yasm: 18F5 sbb ch, dh ; SBB r/m8, r8
1582 */
1583 if (pDis->ModRM.Bits.Mod == 3 /* reg,reg */)
1584 {
1585 switch (pDis->pCurInstr->uOpcode)
1586 {
1587 case OP_ADD:
1588 case OP_OR:
1589 case OP_ADC:
1590 case OP_SBB:
1591 case OP_AND:
1592 case OP_SUB:
1593 case OP_XOR:
1594 case OP_CMP:
1595 if ( ( pDis->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
1596 && pDis->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
1597 || ( pDis->pCurInstr->fParam1 == OP_PARM_Gv /* rX */
1598 && pDis->pCurInstr->fParam2 == OP_PARM_Ev /* rX/memX */))
1599 return true;
1600
1601 /* 82 (see table A-6). */
1602 if (pDis->bOpCode == 0x82)
1603 return true;
1604 break;
1605
1606 /* ff /0, fe /0, ff /1, fe /0 */
1607 case OP_DEC:
1608 case OP_INC:
1609 return true;
1610
1611 case OP_POP:
1612 case OP_PUSH:
1613 Assert(pDis->bOpCode == 0x8f);
1614 return true;
1615
1616 case OP_MOV:
1617 if ( pDis->bOpCode == 0x8a
1618 || pDis->bOpCode == 0x8b)
1619 return true;
1620 break;
1621
1622 default:
1623 break;
1624 }
1625 }
1626
1627 /* shl eax,1 will be assembled to the form without the immediate byte. */
1628 if ( pDis->pCurInstr->fParam2 == OP_PARM_Ib
1629 && (uint8_t)pDis->Param2.uValue == 1)
1630 {
1631 switch (pDis->pCurInstr->uOpcode)
1632 {
1633 case OP_SHL:
1634 case OP_SHR:
1635 case OP_SAR:
1636 case OP_RCL:
1637 case OP_RCR:
1638 case OP_ROL:
1639 case OP_ROR:
1640 return true;
1641 }
1642 }
1643
1644 /* And some more - see table A-6. */
1645 if (pDis->bOpCode == 0x82)
1646 {
1647 switch (pDis->pCurInstr->uOpcode)
1648 {
1649 case OP_ADD:
1650 case OP_OR:
1651 case OP_ADC:
1652 case OP_SBB:
1653 case OP_AND:
1654 case OP_SUB:
1655 case OP_XOR:
1656 case OP_CMP:
1657 return true;
1658 break;
1659 }
1660 }
1661
1662
1663 /* check for REX.X = 1 without SIB. */
1664
1665 /* Yasm encodes setnbe al with /2 instead of /0 like the AMD manual
1666 says (intel doesn't appear to care). */
1667 switch (pDis->pCurInstr->uOpcode)
1668 {
1669 case OP_SETO:
1670 case OP_SETNO:
1671 case OP_SETC:
1672 case OP_SETNC:
1673 case OP_SETE:
1674 case OP_SETNE:
1675 case OP_SETBE:
1676 case OP_SETNBE:
1677 case OP_SETS:
1678 case OP_SETNS:
1679 case OP_SETP:
1680 case OP_SETNP:
1681 case OP_SETL:
1682 case OP_SETNL:
1683 case OP_SETLE:
1684 case OP_SETNLE:
1685 AssertMsg(pDis->bOpCode >= 0x90 && pDis->bOpCode <= 0x9f, ("%#x\n", pDis->bOpCode));
1686 if (pDis->ModRM.Bits.Reg != 2)
1687 return true;
1688 break;
1689 }
1690
1691 /*
1692 * The MOVZX reg32,mem16 instruction without an operand size prefix
1693 * doesn't quite make sense...
1694 */
1695 if ( pDis->pCurInstr->uOpcode == OP_MOVZX
1696 && pDis->bOpCode == 0xB7
1697 && (pDis->uCpuMode == DISCPUMODE_16BIT) != !!(fPrefixes & DISPREFIX_OPSIZE))
1698 return true;
1699
1700 return false;
1701}
1702
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