DisasmFormatYasm.cpp@ 62452

Last change on this file since 62452 was 62452, checked in by vboxsync, 8 years ago
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1	/* $Id: DisasmFormatYasm.cpp 62452 2016-07-22 15:16:45Z vboxsync $ */
2	/** @file
3	* VBox Disassembler - Yasm(/Nasm) Style Formatter.
4	*/
5
6	/*
7	* Copyright (C) 2008-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#include <VBox/dis.h>
23	#include "DisasmInternal.h"
24	#include <iprt/string.h>
25	#include <iprt/assert.h>
26	#include <iprt/ctype.h>
27
28
29	/*********************************************************************************************************************************
30	* Global Variables *
31	*********************************************************************************************************************************/
32	static const char g_szSpaces[] =
33	" ";
34	static const char g_aszYasmRegGen8[20][5] =
35	{
36	"al\0\0", "cl\0\0", "dl\0\0", "bl\0\0", "ah\0\0", "ch\0\0", "dh\0\0", "bh\0\0", "r8b\0", "r9b\0", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b", "spl\0", "bpl\0", "sil\0", "dil\0"
37	};
38	static const char g_aszYasmRegGen16[16][5] =
39	{
40	"ax\0\0", "cx\0\0", "dx\0\0", "bx\0\0", "sp\0\0", "bp\0\0", "si\0\0", "di\0\0", "r8w\0", "r9w\0", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
41	};
42	static const char g_aszYasmRegGen1616[8][6] =
43	{
44	"bx+si", "bx+di", "bp+si", "bp+di", "si\0\0\0", "di\0\0\0", "bp\0\0\0", "bx\0\0\0"
45	};
46	static const char g_aszYasmRegGen32[16][5] =
47	{
48	"eax\0", "ecx\0", "edx\0", "ebx\0", "esp\0", "ebp\0", "esi\0", "edi\0", "r8d\0", "r9d\0", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
49	};
50	static const char g_aszYasmRegGen64[16][4] =
51	{
52	"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", "r8\0", "r9\0", "r10", "r11", "r12", "r13", "r14", "r15"
53	};
54	static const char g_aszYasmRegSeg[6][3] =
55	{
56	"es", "cs", "ss", "ds", "fs", "gs"
57	};
58	static const char g_aszYasmRegFP[8][4] =
59	{
60	"st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7"
61	};
62	static const char g_aszYasmRegMMX[8][4] =
63	{
64	"mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7"
65	};
66	static const char g_aszYasmRegXMM[16][6] =
67	{
68	"xmm0\0", "xmm1\0", "xmm2\0", "xmm3\0", "xmm4\0", "xmm5\0", "xmm6\0", "xmm7\0", "xmm8\0", "xmm9\0", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
69	};
70	static const char g_aszYasmRegYMM[16][6] =
71	{
72	"ymm0\0", "ymm1\0", "ymm2\0", "ymm3\0", "ymm4\0", "ymm5\0", "ymm6\0", "ymm7\0", "ymm8\0", "ymm9\0", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15"
73	};
74	static const char g_aszYasmRegCRx[16][5] =
75	{
76	"cr0\0", "cr1\0", "cr2\0", "cr3\0", "cr4\0", "cr5\0", "cr6\0", "cr7\0", "cr8\0", "cr9\0", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15"
77	};
78	static const char g_aszYasmRegDRx[16][5] =
79	{
80	"dr0\0", "dr1\0", "dr2\0", "dr3\0", "dr4\0", "dr5\0", "dr6\0", "dr7\0", "dr8\0", "dr9\0", "dr10", "dr11", "dr12", "dr13", "dr14", "dr15"
81	};
82	static const char g_aszYasmRegTRx[16][5] =
83	{
84	"tr0\0", "tr1\0", "tr2\0", "tr3\0", "tr4\0", "tr5\0", "tr6\0", "tr7\0", "tr8\0", "tr9\0", "tr10", "tr11", "tr12", "tr13", "tr14", "tr15"
85	};
86
87
88
89	/**
90	* Gets the base register name for the given parameter.
91	*
92	* @returns Pointer to the register name.
93	* @param pDis The disassembler state.
94	* @param pParam The parameter.
95	* @param pcchReg Where to store the length of the name.
96	*/
97	static const char disasmFormatYasmBaseReg(PCDISSTATE pDis, PCDISOPPARAM pParam, size_t pcchReg)
98	{
99	switch (pParam->fUse & ( DISUSE_REG_GEN8 \| DISUSE_REG_GEN16 \| DISUSE_REG_GEN32 \| DISUSE_REG_GEN64
100	\| DISUSE_REG_FP \| DISUSE_REG_MMX \| DISUSE_REG_XMM \| DISUSE_REG_YMM
101	\| DISUSE_REG_CR \| DISUSE_REG_DBG \| DISUSE_REG_SEG \| DISUSE_REG_TEST))
102
103	{
104	case DISUSE_REG_GEN8:
105	{
106	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen8));
107	const char *psz = g_aszYasmRegGen8[pParam->Base.idxGenReg];
108	*pcchReg = 2 + !!psz[2] + !!psz[3];
109	return psz;
110	}
111
112	case DISUSE_REG_GEN16:
113	{
114	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
115	const char *psz = g_aszYasmRegGen16[pParam->Base.idxGenReg];
116	*pcchReg = 2 + !!psz[2] + !!psz[3];
117	return psz;
118	}
119
120	// VSIB
121	case DISUSE_REG_XMM \| DISUSE_REG_GEN32:
122	case DISUSE_REG_YMM \| DISUSE_REG_GEN32:
123	case DISUSE_REG_GEN32:
124	{
125	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
126	const char *psz = g_aszYasmRegGen32[pParam->Base.idxGenReg];
127	*pcchReg = 2 + !!psz[2] + !!psz[3];
128	return psz;
129	}
130
131	// VSIB
132	case DISUSE_REG_XMM \| DISUSE_REG_GEN64:
133	case DISUSE_REG_YMM \| DISUSE_REG_GEN64:
134	case DISUSE_REG_GEN64:
135	{
136	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
137	const char *psz = g_aszYasmRegGen64[pParam->Base.idxGenReg];
138	*pcchReg = 2 + !!psz[2] + !!psz[3];
139	return psz;
140	}
141
142	case DISUSE_REG_FP:
143	{
144	Assert(pParam->Base.idxFpuReg < RT_ELEMENTS(g_aszYasmRegFP));
145	const char *psz = g_aszYasmRegFP[pParam->Base.idxFpuReg];
146	*pcchReg = 3;
147	return psz;
148	}
149
150	case DISUSE_REG_MMX:
151	{
152	Assert(pParam->Base.idxMmxReg < RT_ELEMENTS(g_aszYasmRegMMX));
153	const char *psz = g_aszYasmRegMMX[pParam->Base.idxMmxReg];
154	*pcchReg = 3;
155	return psz;
156	}
157
158	case DISUSE_REG_XMM:
159	{
160	Assert(pParam->Base.idxXmmReg < RT_ELEMENTS(g_aszYasmRegXMM));
161	const char *psz = g_aszYasmRegXMM[pParam->Base.idxXmmReg];
162	*pcchReg = 4 + !!psz[4];
163	return psz;
164	}
165
166	case DISUSE_REG_YMM:
167	{
168	Assert(pParam->Base.idxYmmReg < RT_ELEMENTS(g_aszYasmRegYMM));
169	const char *psz = g_aszYasmRegYMM[pParam->Base.idxYmmReg];
170	*pcchReg = 4 + !!psz[4];
171	return psz;
172	}
173
174	case DISUSE_REG_CR:
175	{
176	Assert(pParam->Base.idxCtrlReg < RT_ELEMENTS(g_aszYasmRegCRx));
177	const char *psz = g_aszYasmRegCRx[pParam->Base.idxCtrlReg];
178	*pcchReg = 3;
179	return psz;
180	}
181
182	case DISUSE_REG_DBG:
183	{
184	Assert(pParam->Base.idxDbgReg < RT_ELEMENTS(g_aszYasmRegDRx));
185	const char *psz = g_aszYasmRegDRx[pParam->Base.idxDbgReg];
186	*pcchReg = 3;
187	return psz;
188	}
189
190	case DISUSE_REG_SEG:
191	{
192	Assert(pParam->Base.idxSegReg < RT_ELEMENTS(g_aszYasmRegCRx));
193	const char *psz = g_aszYasmRegSeg[pParam->Base.idxSegReg];
194	*pcchReg = 2;
195	return psz;
196	}
197
198	case DISUSE_REG_TEST:
199	{
200	Assert(pParam->Base.idxTestReg < RT_ELEMENTS(g_aszYasmRegTRx));
201	const char *psz = g_aszYasmRegTRx[pParam->Base.idxTestReg];
202	*pcchReg = 3;
203	return psz;
204	}
205
206	default:
207	AssertMsgFailed(("%#x\n", pParam->fUse));
208	*pcchReg = 3;
209	return "r??";
210	}
211	}
212
213
214	/**
215	* Gets the index register name for the given parameter.
216	*
217	* @returns The index register name.
218	* @param pDis The disassembler state.
219	* @param pParam The parameter.
220	* @param pcchReg Where to store the length of the name.
221	*/
222	static const char disasmFormatYasmIndexReg(PCDISSTATE pDis, PCDISOPPARAM pParam, size_t pcchReg)
223	{
224	if (pParam->fUse & DISUSE_REG_XMM)
225	{
226	Assert(pParam->Index.idxXmmReg < RT_ELEMENTS(g_aszYasmRegXMM));
227	const char *psz = g_aszYasmRegXMM[pParam->Index.idxXmmReg];
228	*pcchReg = 4 + !!psz[4];
229	return psz;
230	}
231	else if (pParam->fUse & DISUSE_REG_YMM)
232	{
233	Assert(pParam->Index.idxYmmReg < RT_ELEMENTS(g_aszYasmRegYMM));
234	const char *psz = g_aszYasmRegYMM[pParam->Index.idxYmmReg];
235	*pcchReg = 4 + !!psz[4];
236	return psz;
237
238	}
239	else
240	switch (pDis->uAddrMode)
241	{
242	case DISCPUMODE_16BIT:
243	{
244	Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
245	const char *psz = g_aszYasmRegGen16[pParam->Index.idxGenReg];
246	*pcchReg = 2 + !!psz[2] + !!psz[3];
247	return psz;
248	}
249
250	case DISCPUMODE_32BIT:
251	{
252	Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
253	const char *psz = g_aszYasmRegGen32[pParam->Index.idxGenReg];
254	*pcchReg = 2 + !!psz[2] + !!psz[3];
255	return psz;
256	}
257
258	case DISCPUMODE_64BIT:
259	{
260	Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
261	const char *psz = g_aszYasmRegGen64[pParam->Index.idxGenReg];
262	*pcchReg = 2 + !!psz[2] + !!psz[3];
263	return psz;
264	}
265
266	default:
267	AssertMsgFailed(("%#x %#x\n", pParam->fUse, pDis->uAddrMode));
268	*pcchReg = 3;
269	return "r??";
270	}
271	}
272
273
274	/**
275	* Formats the current instruction in Yasm (/ Nasm) style.
276	*
277	*
278	* @returns The number of output characters. If this is >= cchBuf, then the content
279	* of pszBuf will be truncated.
280	* @param pDis Pointer to the disassembler state.
281	* @param pszBuf The output buffer.
282	* @param cchBuf The size of the output buffer.
283	* @param fFlags Format flags, see DIS_FORMAT_FLAGS_*.
284	* @param pfnGetSymbol Get symbol name for a jmp or call target address. Optional.
285	* @param pvUser User argument for pfnGetSymbol.
286	*/
287	DISDECL(size_t) DISFormatYasmEx(PCDISSTATE pDis, char *pszBuf, size_t cchBuf, uint32_t fFlags,
288	PFNDISGETSYMBOL pfnGetSymbol, void *pvUser)
289	{
290	/** @todo monitor and mwait aren't formatted correctly in 64-bit mode. */
291	/*
292	* Input validation and massaging.
293	*/
294	AssertPtr(pDis);
295	AssertPtrNull(pszBuf);
296	Assert(pszBuf \|\| !cchBuf);
297	AssertPtrNull(pfnGetSymbol);
298	AssertMsg(DIS_FMT_FLAGS_IS_VALID(fFlags), ("%#x\n", fFlags));
299	if (fFlags & DIS_FMT_FLAGS_ADDR_COMMENT)
300	fFlags = (fFlags & ~DIS_FMT_FLAGS_ADDR_LEFT) \| DIS_FMT_FLAGS_ADDR_RIGHT;
301	if (fFlags & DIS_FMT_FLAGS_BYTES_COMMENT)
302	fFlags = (fFlags & ~DIS_FMT_FLAGS_BYTES_LEFT) \| DIS_FMT_FLAGS_BYTES_RIGHT;
303
304	PCDISOPCODE const pOp = pDis->pCurInstr;
305
306	/*
307	* Output macros
308	*/
309	char *pszDst = pszBuf;
310	size_t cchDst = cchBuf;
311	size_t cchOutput = 0;
312	#define PUT_C(ch) \
313	do { \
314	cchOutput++; \
315	if (cchDst > 1) \
316	{ \
317	cchDst--; \
318	*pszDst++ = (ch); \
319	} \
320	} while (0)
321	#define PUT_STR(pszSrc, cchSrc) \
322	do { \
323	cchOutput += (cchSrc); \
324	if (cchDst > (cchSrc)) \
325	{ \
326	memcpy(pszDst, (pszSrc), (cchSrc)); \
327	pszDst += (cchSrc); \
328	cchDst -= (cchSrc); \
329	} \
330	else if (cchDst > 1) \
331	{ \
332	memcpy(pszDst, (pszSrc), cchDst - 1); \
333	pszDst += cchDst - 1; \
334	cchDst = 1; \
335	} \
336	} while (0)
337	#define PUT_SZ(sz) \
338	PUT_STR((sz), sizeof(sz) - 1)
339	#define PUT_SZ_STRICT(szStrict, szRelaxed) \
340	do { if (fFlags & DIS_FMT_FLAGS_STRICT) PUT_SZ(szStrict); else PUT_SZ(szRelaxed); } while (0)
341	#define PUT_PSZ(psz) \
342	do { const size_t cchTmp = strlen(psz); PUT_STR((psz), cchTmp); } while (0)
343	#define PUT_NUM(cch, fmt, num) \
344	do { \
345	cchOutput += (cch); \
346	if (cchDst > 1) \
347	{ \
348	const size_t cchTmp = RTStrPrintf(pszDst, cchDst, fmt, (num)); \
349	pszDst += cchTmp; \
350	cchDst -= cchTmp; \
351	Assert(cchTmp == (cch) \|\| cchDst == 1); \
352	} \
353	} while (0)
354	/** @todo add two flags for choosing between %X / %x and h / 0x. */
355	#define PUT_NUM_8(num) PUT_NUM(4, "0%02xh", (uint8_t)(num))
356	#define PUT_NUM_16(num) PUT_NUM(6, "0%04xh", (uint16_t)(num))
357	#define PUT_NUM_32(num) PUT_NUM(10, "0%08xh", (uint32_t)(num))
358	#define PUT_NUM_64(num) PUT_NUM(18, "0%016RX64h", (uint64_t)(num))
359
360	#define PUT_NUM_SIGN(cch, fmt, num, stype, utype) \
361	do { \
362	if ((stype)(num) >= 0) \
363	{ \
364	PUT_C('+'); \
365	PUT_NUM(cch, fmt, (utype)(num)); \
366	} \
367	else \
368	{ \
369	PUT_C('-'); \
370	PUT_NUM(cch, fmt, (utype)-(stype)(num)); \
371	} \
372	} while (0)
373	#define PUT_NUM_S8(num) PUT_NUM_SIGN(4, "0%02xh", num, int8_t, uint8_t)
374	#define PUT_NUM_S16(num) PUT_NUM_SIGN(6, "0%04xh", num, int16_t, uint16_t)
375	#define PUT_NUM_S32(num) PUT_NUM_SIGN(10, "0%08xh", num, int32_t, uint32_t)
376	#define PUT_NUM_S64(num) PUT_NUM_SIGN(18, "0%016RX64h", num, int64_t, uint64_t)
377
378	#define PUT_SYMBOL_TWO(a_rcSym, a_szStart, a_chEnd) \
379	do { \
380	if (RT_SUCCESS(a_rcSym)) \
381	{ \
382	PUT_SZ(a_szStart); \
383	PUT_PSZ(szSymbol); \
384	if (off != 0) \
385	{ \
386	if ((int8_t)off == off) \
387	PUT_NUM_S8(off); \
388	else if ((int16_t)off == off) \
389	PUT_NUM_S16(off); \
390	else if ((int32_t)off == off) \
391	PUT_NUM_S32(off); \
392	else \
393	PUT_NUM_S64(off); \
394	} \
395	PUT_C(a_chEnd); \
396	} \
397	} while (0)
398
399	#define PUT_SYMBOL(a_uSeg, a_uAddr, a_szStart, a_chEnd) \
400	do { \
401	if (pfnGetSymbol) \
402	{ \
403	int rcSym = pfnGetSymbol(pDis, a_uSeg, a_uAddr, szSymbol, sizeof(szSymbol), &off, pvUser); \
404	PUT_SYMBOL_TWO(rcSym, a_szStart, a_chEnd); \
405	} \
406	} while (0)
407
408
409	/*
410	* The address?
411	*/
412	if (fFlags & DIS_FMT_FLAGS_ADDR_LEFT)
413	{
414	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
415	if (pDis->uInstrAddr >= _4G)
416	PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
417	#endif
418	PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
419	PUT_C(' ');
420	}
421
422	/*
423	* The opcode bytes?
424	*/
425	if (fFlags & DIS_FMT_FLAGS_BYTES_LEFT)
426	{
427	size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
428	cchOutput += cchTmp;
429	if (cchDst > 1)
430	{
431	if (cchTmp <= cchDst)
432	{
433	cchDst -= cchTmp;
434	pszDst += cchTmp;
435	}
436	else
437	{
438	pszDst += cchDst - 1;
439	cchDst = 1;
440	}
441	}
442
443	/* Some padding to align the instruction. */
444	size_t cchPadding = (7 * (2 + !!(fFlags & DIS_FMT_FLAGS_BYTES_SPACED)))
445	+ !!(fFlags & DIS_FMT_FLAGS_BYTES_BRACKETS) * 2
446	+ 2;
447	cchPadding = cchTmp + 1 >= cchPadding ? 1 : cchPadding - cchTmp;
448	PUT_STR(g_szSpaces, cchPadding);
449	}
450
451
452	/*
453	* Filter out invalid opcodes first as they need special
454	* treatment. UD2 is an exception and should be handled normally.
455	*/
456	size_t const offInstruction = cchOutput;
457	if ( pOp->uOpcode == OP_INVALID
458	\|\| ( pOp->uOpcode == OP_ILLUD2
459	&& (pDis->fPrefix & DISPREFIX_LOCK)))
460	PUT_SZ("Illegal opcode");
461	else
462	{
463	/*
464	* Prefixes
465	*/
466	if (pDis->fPrefix & DISPREFIX_LOCK)
467	PUT_SZ("lock ");
468	if (pDis->fPrefix & DISPREFIX_REP)
469	PUT_SZ("rep ");
470	else if(pDis->fPrefix & DISPREFIX_REPNE)
471	PUT_SZ("repne ");
472
473	/*
474	* Adjust the format string to the correct mnemonic
475	* or to avoid things the assembler cannot handle correctly.
476	*/
477	char szTmpFmt[48];
478	const char *pszFmt = pOp->pszOpcode;
479	bool fIgnoresOpSize = false;
480	bool fMayNeedAddrSize = false;
481	switch (pOp->uOpcode)
482	{
483	case OP_JECXZ:
484	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "jcxz %Jb" : pDis->uOpMode == DISCPUMODE_32BIT ? "jecxz %Jb" : "jrcxz %Jb";
485	break;
486	case OP_PUSHF:
487	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "pushfw" : pDis->uOpMode == DISCPUMODE_32BIT ? "pushfd" : "pushfq";
488	break;
489	case OP_POPF:
490	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "popfw" : pDis->uOpMode == DISCPUMODE_32BIT ? "popfd" : "popfq";
491	break;
492	case OP_PUSHA:
493	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "pushaw" : "pushad";
494	break;
495	case OP_POPA:
496	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "popaw" : "popad";
497	break;
498	case OP_INSB:
499	pszFmt = "insb";
500	fIgnoresOpSize = fMayNeedAddrSize = true;
501	break;
502	case OP_INSWD:
503	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "insw" : pDis->uOpMode == DISCPUMODE_32BIT ? "insd" : "insq";
504	fMayNeedAddrSize = true;
505	break;
506	case OP_OUTSB:
507	pszFmt = "outsb";
508	fIgnoresOpSize = fMayNeedAddrSize = true;
509	break;
510	case OP_OUTSWD:
511	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "outsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "outsd" : "outsq";
512	fMayNeedAddrSize = true;
513	break;
514	case OP_MOVSB:
515	pszFmt = "movsb";
516	fIgnoresOpSize = fMayNeedAddrSize = true;
517	break;
518	case OP_MOVSWD:
519	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "movsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "movsd" : "movsq";
520	fMayNeedAddrSize = true;
521	break;
522	case OP_CMPSB:
523	pszFmt = "cmpsb";
524	fIgnoresOpSize = fMayNeedAddrSize = true;
525	break;
526	case OP_CMPWD:
527	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cmpsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "cmpsd" : "cmpsq";
528	fMayNeedAddrSize = true;
529	break;
530	case OP_SCASB:
531	pszFmt = "scasb";
532	fIgnoresOpSize = fMayNeedAddrSize = true;
533	break;
534	case OP_SCASWD:
535	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "scasw" : pDis->uOpMode == DISCPUMODE_32BIT ? "scasd" : "scasq";
536	fMayNeedAddrSize = true;
537	break;
538	case OP_LODSB:
539	pszFmt = "lodsb";
540	fIgnoresOpSize = fMayNeedAddrSize = true;
541	break;
542	case OP_LODSWD:
543	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "lodsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "lodsd" : "lodsq";
544	fMayNeedAddrSize = true;
545	break;
546	case OP_STOSB:
547	pszFmt = "stosb";
548	fIgnoresOpSize = fMayNeedAddrSize = true;
549	break;
550	case OP_STOSWD:
551	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "stosw" : pDis->uOpMode == DISCPUMODE_32BIT ? "stosd" : "stosq";
552	fMayNeedAddrSize = true;
553	break;
554	case OP_CBW:
555	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cbw" : pDis->uOpMode == DISCPUMODE_32BIT ? "cwde" : "cdqe";
556	break;
557	case OP_CWD:
558	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cwd" : pDis->uOpMode == DISCPUMODE_32BIT ? "cdq" : "cqo";
559	break;
560	case OP_SHL:
561	Assert(pszFmt[3] == '/');
562	pszFmt += 4;
563	break;
564	case OP_XLAT:
565	pszFmt = "xlatb";
566	break;
567	case OP_INT3:
568	pszFmt = "int3";
569	break;
570
571	/*
572	* Don't know how to tell yasm to generate complicated nop stuff, so 'db' it.
573	*/
574	case OP_NOP:
575	if (pDis->bOpCode == 0x90)
576	/* fine, fine */;
577	else if (pszFmt[sizeof("nop %Ev") - 1] == '/' && pszFmt[sizeof("nop %Ev")] == 'p')
578	pszFmt = "prefetch %Eb";
579	else if (pDis->bOpCode == 0x1f)
580	{
581	Assert(pDis->cbInstr >= 3);
582	PUT_SZ("db 00fh, 01fh,");
583	PUT_NUM_8(MAKE_MODRM(pDis->ModRM.Bits.Mod, pDis->ModRM.Bits.Reg, pDis->ModRM.Bits.Rm));
584	for (unsigned i = 3; i < pDis->cbInstr; i++)
585	{
586	PUT_C(',');
587	PUT_NUM_8(0x90); ///@todo fixme.
588	}
589	pszFmt = "";
590	}
591	break;
592
593	default:
594	/* ST(X) -> stX (floating point) */
595	if (*pszFmt == 'f' && strchr(pszFmt, '('))
596	{
597	char *pszFmtDst = szTmpFmt;
598	char ch;
599	do
600	{
601	ch = *pszFmt++;
602	if (ch == 'S' && pszFmt[0] == 'T' && pszFmt[1] == '(')
603	{
604	*pszFmtDst++ = 's';
605	*pszFmtDst++ = 't';
606	pszFmt += 2;
607	ch = *pszFmt;
608	Assert(pszFmt[1] == ')');
609	pszFmt += 2;
610	*pszFmtDst++ = ch;
611	}
612	else
613	*pszFmtDst++ = ch;
614	} while (ch != '\0');
615	pszFmt = szTmpFmt;
616	}
617	if (strchr ("#@&", *pszFmt))
618	{
619	const char *pszDelim = strchr(pszFmt, '/');
620	const char *pszSpace = (pszDelim ? strchr(pszDelim, ' ') : NULL);
621	if (pszDelim != NULL)
622	{
623	char *pszFmtDst = szTmpFmt;
624	if (pszSpace == NULL) pszSpace = strchr(pszDelim, 0);
625	if ( (*pszFmt == '#' && pDis->bVexWFlag)
626	\|\| (*pszFmt == '@' && !VEXREG_IS256B(pDis->bVexDestReg))
627	\|\| (*pszFmt == '&' && ( DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
628	\|\| DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
629	\|\| DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse)
630	\|\| DISUSE_IS_EFFECTIVE_ADDR(pDis->Param4.fUse))))
631	{
632	strncpy(pszFmtDst, pszFmt + 1, pszDelim - pszFmt - 1);
633	pszFmtDst += pszDelim - pszFmt - 1;
634	}
635	else
636	{
637	strncpy(pszFmtDst, pszDelim + 1, pszSpace - pszDelim - 1);
638	pszFmtDst += pszSpace - pszDelim - 1;
639	}
640	strcpy (pszFmtDst, pszSpace);
641	pszFmt = szTmpFmt;
642	}
643	}
644	break;
645
646	/*
647	* Horrible hacks.
648	*/
649	case OP_FLD:
650	if (pDis->bOpCode == 0xdb) /* m80fp workaround. */
651	(int )&pDis->Param1.fParam &= ~0x1f; /* make it pure OP_PARM_M */
652	break;
653	case OP_LAR: /* hack w -> v, probably not correct. */
654	(int )&pDis->Param2.fParam &= ~0x1f;
655	(int )&pDis->Param2.fParam \|= OP_PARM_v;
656	break;
657	}
658
659	/*
660	* Add operand size and address prefixes for outsb, movsb, etc.
661	*/
662	if (pDis->fPrefix & (DISPREFIX_OPSIZE \| DISPREFIX_ADDRSIZE))
663	{
664	if (fIgnoresOpSize && (pDis->fPrefix & DISPREFIX_OPSIZE) )
665	{
666	if (pDis->uCpuMode == DISCPUMODE_16BIT)
667	PUT_SZ("o32 ");
668	else
669	PUT_SZ("o16 ");
670	}
671	if (fMayNeedAddrSize && (pDis->fPrefix & DISPREFIX_ADDRSIZE) )
672	{
673	if (pDis->uCpuMode == DISCPUMODE_16BIT)
674	PUT_SZ("a32 ");
675	else
676	PUT_SZ("a16 ");
677	}
678	}
679
680	/*
681	* Formatting context and associated macros.
682	*/
683	PCDISOPPARAM pParam = &pDis->Param1;
684	int iParam = 1;
685
686	#define PUT_FAR() \
687	do { \
688	if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_p \
689	&& pOp->uOpcode != OP_LDS /* table bugs? */ \
690	&& pOp->uOpcode != OP_LES \
691	&& pOp->uOpcode != OP_LFS \
692	&& pOp->uOpcode != OP_LGS \
693	&& pOp->uOpcode != OP_LSS ) \
694	PUT_SZ("far "); \
695	} while (0)
696	/** @todo mov ah,ch ends up with a byte 'override'... - check if this wasn't fixed. */
697	/** @todo drop the work/dword/qword override when the src/dst is a register (except for movsx/movzx). */
698	#define PUT_SIZE_OVERRIDE() \
699	do { \
700	switch (OP_PARM_VSUBTYPE(pParam->fParam)) \
701	{ \
702	case OP_PARM_v: \
703	case OP_PARM_y: \
704	switch (pDis->uOpMode) \
705	{ \
706	case DISCPUMODE_16BIT: if (OP_PARM_VSUBTYPE(pParam->fParam) != OP_PARM_y) PUT_SZ("word "); break; \
707	case DISCPUMODE_32BIT: \
708	if (pDis->pCurInstr->uOpcode != OP_GATHER \|\| pDis->bVexWFlag) { PUT_SZ("dword "); break; } \
709	case DISCPUMODE_64BIT: PUT_SZ("qword "); break; \
710	default: break; \
711	} \
712	break; \
713	case OP_PARM_b: PUT_SZ("byte "); break; \
714	case OP_PARM_w: \
715	if (OP_PARM_VTYPE(pParam->fParam) == OP_PARM_W \|\| \
716	OP_PARM_VTYPE(pParam->fParam) == OP_PARM_M) \
717	{ \
718	if (VEXREG_IS256B(pDis->bVexDestReg)) PUT_SZ("dword "); \
719	else PUT_SZ("word "); \
720	} \
721	break; \
722	case OP_PARM_d: \
723	if (OP_PARM_VTYPE(pParam->fParam) == OP_PARM_W \|\| \
724	OP_PARM_VTYPE(pParam->fParam) == OP_PARM_M) \
725	{ \
726	if (VEXREG_IS256B(pDis->bVexDestReg)) PUT_SZ("qword "); \
727	else PUT_SZ("dword "); \
728	} \
729	break; \
730	case OP_PARM_q: \
731	if (OP_PARM_VTYPE(pParam->fParam) == OP_PARM_W \|\| \
732	OP_PARM_VTYPE(pParam->fParam) == OP_PARM_M) \
733	{ \
734	if (VEXREG_IS256B(pDis->bVexDestReg)) PUT_SZ("oword "); \
735	else PUT_SZ("qword "); \
736	} \
737	break; \
738	case OP_PARM_ps: \
739	case OP_PARM_pd: \
740	case OP_PARM_x: if (VEXREG_IS256B(pDis->bVexDestReg)) { PUT_SZ("yword "); break; } \
741	case OP_PARM_ss: \
742	case OP_PARM_sd: \
743	case OP_PARM_dq: PUT_SZ("oword "); break; \
744	case OP_PARM_qq: PUT_SZ("yword "); break; \
745	case OP_PARM_p: break; /* see PUT_FAR */ \
746	case OP_PARM_s: if (pParam->fUse & DISUSE_REG_FP) PUT_SZ("tword "); break; /* ?? */ \
747	case OP_PARM_z: break; \
748	case OP_PARM_NONE: \
749	if ( OP_PARM_VTYPE(pParam->fParam) == OP_PARM_M \
750	&& ((pParam->fUse & DISUSE_REG_FP) \|\| pOp->uOpcode == OP_FLD)) \
751	PUT_SZ("tword "); \
752	break; \
753	default: break; /no pointer type specified/necessary/ \
754	} \
755	} while (0)
756	static const char s_szSegPrefix[6][4] = { "es:", "cs:", "ss:", "ds:", "fs:", "gs:" };
757	#define PUT_SEGMENT_OVERRIDE() \
758	do { \
759	if (pDis->fPrefix & DISPREFIX_SEG) \
760	PUT_STR(s_szSegPrefix[pDis->idxSegPrefix], 3); \
761	} while (0)
762
763
764	/*
765	* Segment prefixing for instructions that doesn't do memory access.
766	*/
767	if ( (pDis->fPrefix & DISPREFIX_SEG)
768	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
769	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
770	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse))
771	{
772	PUT_STR(s_szSegPrefix[pDis->idxSegPrefix], 2);
773	PUT_C(' ');
774	}
775
776
777	/*
778	* The formatting loop.
779	*/
780	RTINTPTR off;
781	char szSymbol[128];
782	char ch;
783	while ((ch = *pszFmt++) != '\0')
784	{
785	if (ch == '%')
786	{
787	ch = *pszFmt++;
788	switch (ch)
789	{
790	/*
791	* ModRM - Register only.
792	*/
793	case 'C': /* Control register (ParseModRM / UseModRM). */
794	case 'D': /* Debug register (ParseModRM / UseModRM). */
795	case 'G': /* ModRM selects general register (ParseModRM / UseModRM). */
796	case 'S': /* ModRM byte selects a segment register (ParseModRM / UseModRM). */
797	case 'T': /* ModRM byte selects a test register (ParseModRM / UseModRM). */
798	case 'V': /* ModRM byte selects an XMM/SSE register (ParseModRM / UseModRM). */
799	case 'P': /* ModRM byte selects MMX register (ParseModRM / UseModRM). */
800	case 'H': /* The VEX.vvvv field of the VEX prefix selects a XMM/YMM register. */
801	case 'L': /* The upper 4 bits of the 8-bit immediate selects a XMM/YMM register. */
802	{
803	pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
804	Assert(!(pParam->fUse & (DISUSE_INDEX \| DISUSE_SCALE) /* No SIB here... */));
805	Assert(!(pParam->fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32)));
806
807	size_t cchReg;
808	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
809	PUT_STR(pszReg, cchReg);
810	break;
811	}
812
813	/*
814	* ModRM - Register or memory.
815	*/
816	case 'E': /* ModRM specifies parameter (ParseModRM / UseModRM / UseSIB). */
817	case 'Q': /* ModRM byte selects MMX register or memory address (ParseModRM / UseModRM). */
818	case 'R': /* ModRM byte may only refer to a general register (ParseModRM / UseModRM). */
819	case 'W': /* ModRM byte selects an XMM/SSE register or a memory address (ParseModRM / UseModRM). */
820	case 'M': /* ModRM may only refer to memory (ParseModRM / UseModRM). */
821	{
822	pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
823
824	PUT_FAR();
825	uint32_t const fUse = pParam->fUse;
826	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
827	{
828	/* Work around mov seg,[mem16] and mov [mem16],seg as these always make a 16-bit mem
829	while the register variants deals with 16, 32 & 64 in the normal fashion. */
830	if ( pParam->fParam != OP_PARM_Ev
831	\|\| pOp->uOpcode != OP_MOV
832	\|\| ( pOp->fParam1 != OP_PARM_Sw
833	&& pOp->fParam2 != OP_PARM_Sw))
834	PUT_SIZE_OVERRIDE();
835	PUT_C('[');
836	}
837	if ( (fFlags & DIS_FMT_FLAGS_STRICT)
838	&& (fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32)))
839	{
840	if ( (fUse & DISUSE_DISPLACEMENT8)
841	&& !pParam->uDisp.i8)
842	PUT_SZ("byte ");
843	else if ( (fUse & DISUSE_DISPLACEMENT16)
844	&& (int8_t)pParam->uDisp.i16 == (int16_t)pParam->uDisp.i16)
845	PUT_SZ("word ");
846	else if ( (fUse & DISUSE_DISPLACEMENT32)
847	&& (int16_t)pParam->uDisp.i32 == (int32_t)pParam->uDisp.i32) //??
848	PUT_SZ("dword ");
849	else if ( (fUse & DISUSE_DISPLACEMENT64)
850	&& (pDis->SIB.Bits.Base != 5 \|\| pDis->ModRM.Bits.Mod != 0)
851	&& (int32_t)pParam->uDisp.i64 == (int64_t)pParam->uDisp.i64) //??
852	PUT_SZ("qword ");
853	}
854	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
855	PUT_SEGMENT_OVERRIDE();
856
857	bool fBase = (fUse & DISUSE_BASE) /* When exactly is DISUSE_BASE supposed to be set? disasmModRMReg doesn't set it. */
858	\|\| ( (fUse & ( DISUSE_REG_GEN8
859	\| DISUSE_REG_GEN16
860	\| DISUSE_REG_GEN32
861	\| DISUSE_REG_GEN64
862	\| DISUSE_REG_FP
863	\| DISUSE_REG_MMX
864	\| DISUSE_REG_XMM
865	\| DISUSE_REG_YMM
866	\| DISUSE_REG_CR
867	\| DISUSE_REG_DBG
868	\| DISUSE_REG_SEG
869	\| DISUSE_REG_TEST ))
870	&& !DISUSE_IS_EFFECTIVE_ADDR(fUse));
871	if (fBase)
872	{
873	size_t cchReg;
874	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
875	PUT_STR(pszReg, cchReg);
876	}
877
878	if (fUse & DISUSE_INDEX)
879	{
880	if (fBase)
881	PUT_C('+');
882
883	size_t cchReg;
884	const char *pszReg = disasmFormatYasmIndexReg(pDis, pParam, &cchReg);
885	PUT_STR(pszReg, cchReg);
886
887	if (fUse & DISUSE_SCALE)
888	{
889	PUT_C('*');
890	PUT_C('0' + pParam->uScale);
891	}
892	}
893	else
894	Assert(!(fUse & DISUSE_SCALE));
895
896	int64_t off2 = 0;
897	if (fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32))
898	{
899	if (fUse & DISUSE_DISPLACEMENT8)
900	off2 = pParam->uDisp.i8;
901	else if (fUse & DISUSE_DISPLACEMENT16)
902	off2 = pParam->uDisp.i16;
903	else if (fUse & (DISUSE_DISPLACEMENT32 \| DISUSE_RIPDISPLACEMENT32))
904	off2 = pParam->uDisp.i32;
905	else if (fUse & DISUSE_DISPLACEMENT64)
906	off2 = pParam->uDisp.i64;
907	else
908	{
909	AssertFailed();
910	off2 = 0;
911	}
912
913	int64_t off3 = off2;
914	if (fBase \|\| (fUse & (DISUSE_INDEX \| DISUSE_RIPDISPLACEMENT32)))
915	{
916	PUT_C(off3 >= 0 ? '+' : '-');
917	if (off3 < 0)
918	off3 = -off3;
919	}
920	if (fUse & DISUSE_DISPLACEMENT8)
921	PUT_NUM_8( off3);
922	else if (fUse & DISUSE_DISPLACEMENT16)
923	PUT_NUM_16(off3);
924	else if (fUse & DISUSE_DISPLACEMENT32)
925	PUT_NUM_32(off3);
926	else if (fUse & DISUSE_DISPLACEMENT64)
927	PUT_NUM_64(off3);
928	else
929	{
930	PUT_NUM_32(off3);
931	PUT_SZ(" wrt rip (");
932	off2 += pDis->uInstrAddr + pDis->cbInstr;
933	PUT_NUM_64(off2);
934	if (pfnGetSymbol)
935	PUT_SYMBOL((pDis->fPrefix & DISPREFIX_SEG)
936	? DIS_FMT_SEL_FROM_REG(pDis->idxSegPrefix)
937	: DIS_FMT_SEL_FROM_REG(DISSELREG_DS),
938	pDis->uAddrMode == DISCPUMODE_64BIT
939	? (uint64_t)off2
940	: pDis->uAddrMode == DISCPUMODE_32BIT
941	? (uint32_t)off2
942	: (uint16_t)off2,
943	" = ",
944	')');
945	else
946	PUT_C(')');
947	}
948	}
949
950	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
951	{
952	if (pfnGetSymbol && !fBase && !(fUse & (DISUSE_INDEX \| DISUSE_RIPDISPLACEMENT32)) && off2 != 0)
953	PUT_SYMBOL((pDis->fPrefix & DISPREFIX_SEG)
954	? DIS_FMT_SEL_FROM_REG(pDis->idxSegPrefix)
955	: DIS_FMT_SEL_FROM_REG(DISSELREG_DS),
956	pDis->uAddrMode == DISCPUMODE_64BIT
957	? (uint64_t)off2
958	: pDis->uAddrMode == DISCPUMODE_32BIT
959	? (uint32_t)off2
960	: (uint16_t)off2,
961	" (=",
962	')');
963	PUT_C(']');
964	}
965	break;
966	}
967
968	case 'F': /* Eflags register (0 - popf/pushf only, avoided in adjustments above). */
969	AssertFailed();
970	break;
971
972	case 'I': /* Immediate data (ParseImmByte, ParseImmByteSX, ParseImmV, ParseImmUshort, ParseImmZ). */
973	Assert(pszFmt == 'b' \|\| pszFmt == 'v' \|\| pszFmt == 'w' \|\| pszFmt == 'z'); pszFmt++;
974	switch (pParam->fUse & ( DISUSE_IMMEDIATE8 \| DISUSE_IMMEDIATE16 \| DISUSE_IMMEDIATE32 \| DISUSE_IMMEDIATE64
975	\| DISUSE_IMMEDIATE16_SX8 \| DISUSE_IMMEDIATE32_SX8 \| DISUSE_IMMEDIATE64_SX8))
976	{
977	case DISUSE_IMMEDIATE8:
978	if ( (fFlags & DIS_FMT_FLAGS_STRICT)
979	&& ( (pOp->fParam1 >= OP_PARM_REG_GEN8_START && pOp->fParam1 <= OP_PARM_REG_GEN8_END)
980	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN8_START && pOp->fParam2 <= OP_PARM_REG_GEN8_END))
981	)
982	PUT_SZ("strict byte ");
983	PUT_NUM_8(pParam->uValue);
984	break;
985
986	case DISUSE_IMMEDIATE16:
987	if ( pDis->uCpuMode != pDis->uOpMode
988	\|\| ( (fFlags & DIS_FMT_FLAGS_STRICT)
989	&& ( (int8_t)pParam->uValue == (int16_t)pParam->uValue
990	\|\| (pOp->fParam1 >= OP_PARM_REG_GEN16_START && pOp->fParam1 <= OP_PARM_REG_GEN16_END)
991	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN16_START && pOp->fParam2 <= OP_PARM_REG_GEN16_END))
992	)
993	)
994	{
995	if (OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_b)
996	PUT_SZ_STRICT("strict byte ", "byte ");
997	else if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_v
998	\|\| OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_z)
999	PUT_SZ_STRICT("strict word ", "word ");
1000	}
1001	PUT_NUM_16(pParam->uValue);
1002	break;
1003
1004	case DISUSE_IMMEDIATE16_SX8:
1005	if ( !(pDis->fPrefix & DISPREFIX_OPSIZE)
1006	\|\| pDis->pCurInstr->uOpcode != OP_PUSH)
1007	PUT_SZ_STRICT("strict byte ", "byte ");
1008	else
1009	PUT_SZ("word ");
1010	PUT_NUM_16(pParam->uValue);
1011	break;
1012
1013	case DISUSE_IMMEDIATE32:
1014	if ( pDis->uOpMode != (pDis->uCpuMode == DISCPUMODE_16BIT ? DISCPUMODE_16BIT : DISCPUMODE_32BIT) /* not perfect */
1015	\|\| ( (fFlags & DIS_FMT_FLAGS_STRICT)
1016	&& ( (int8_t)pParam->uValue == (int32_t)pParam->uValue
1017	\|\| (pOp->fParam1 >= OP_PARM_REG_GEN32_START && pOp->fParam1 <= OP_PARM_REG_GEN32_END)
1018	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN32_START && pOp->fParam2 <= OP_PARM_REG_GEN32_END))
1019	)
1020	)
1021	{
1022	if (OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_b)
1023	PUT_SZ_STRICT("strict byte ", "byte ");
1024	else if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_v
1025	\|\| OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_z)
1026	PUT_SZ_STRICT("strict dword ", "dword ");
1027	}
1028	PUT_NUM_32(pParam->uValue);
1029	if (pDis->uCpuMode == DISCPUMODE_32BIT)
1030	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uValue, " (=", ')');
1031	break;
1032
1033	case DISUSE_IMMEDIATE32_SX8:
1034	if ( !(pDis->fPrefix & DISPREFIX_OPSIZE)
1035	\|\| pDis->pCurInstr->uOpcode != OP_PUSH)
1036	PUT_SZ_STRICT("strict byte ", "byte ");
1037	else
1038	PUT_SZ("dword ");
1039	PUT_NUM_32(pParam->uValue);
1040	break;
1041
1042	case DISUSE_IMMEDIATE64_SX8:
1043	if ( !(pDis->fPrefix & DISPREFIX_OPSIZE)
1044	\|\| pDis->pCurInstr->uOpcode != OP_PUSH)
1045	PUT_SZ_STRICT("strict byte ", "byte ");
1046	else
1047	PUT_SZ("qword ");
1048	PUT_NUM_64(pParam->uValue);
1049	break;
1050
1051	case DISUSE_IMMEDIATE64:
1052	PUT_NUM_64(pParam->uValue);
1053	break;
1054
1055	default:
1056	AssertFailed();
1057	break;
1058	}
1059	break;
1060
1061	case 'J': /* Relative jump offset (ParseImmBRel + ParseImmVRel). */
1062	{
1063	int32_t offDisplacement;
1064	Assert(iParam == 1);
1065	bool fPrefix = (fFlags & DIS_FMT_FLAGS_STRICT)
1066	&& pOp->uOpcode != OP_CALL
1067	&& pOp->uOpcode != OP_LOOP
1068	&& pOp->uOpcode != OP_LOOPE
1069	&& pOp->uOpcode != OP_LOOPNE
1070	&& pOp->uOpcode != OP_JECXZ;
1071	if (pOp->uOpcode == OP_CALL)
1072	fFlags &= ~DIS_FMT_FLAGS_RELATIVE_BRANCH;
1073
1074	if (pParam->fUse & DISUSE_IMMEDIATE8_REL)
1075	{
1076	if (fPrefix)
1077	PUT_SZ("short ");
1078	offDisplacement = (int8_t)pParam->uValue;
1079	Assert(*pszFmt == 'b'); pszFmt++;
1080
1081	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1082	PUT_NUM_S8(offDisplacement);
1083	}
1084	else if (pParam->fUse & DISUSE_IMMEDIATE16_REL)
1085	{
1086	if (fPrefix)
1087	PUT_SZ("near ");
1088	offDisplacement = (int16_t)pParam->uValue;
1089	Assert(*pszFmt == 'v'); pszFmt++;
1090
1091	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1092	PUT_NUM_S16(offDisplacement);
1093	}
1094	else
1095	{
1096	if (fPrefix)
1097	PUT_SZ("near ");
1098	offDisplacement = (int32_t)pParam->uValue;
1099	Assert(pParam->fUse & (DISUSE_IMMEDIATE32_REL \| DISUSE_IMMEDIATE64_REL));
1100	Assert(*pszFmt == 'v'); pszFmt++;
1101
1102	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1103	PUT_NUM_S32(offDisplacement);
1104	}
1105	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1106	PUT_SZ(" (");
1107
1108	RTUINTPTR uTrgAddr = pDis->uInstrAddr + pDis->cbInstr + offDisplacement;
1109	if (pDis->uCpuMode == DISCPUMODE_16BIT)
1110	PUT_NUM_16(uTrgAddr);
1111	else if (pDis->uCpuMode == DISCPUMODE_32BIT)
1112	PUT_NUM_32(uTrgAddr);
1113	else
1114	PUT_NUM_64(uTrgAddr);
1115
1116	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1117	{
1118	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " = ", ' ');
1119	PUT_C(')');
1120	}
1121	else
1122	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " (", ')');
1123	break;
1124	}
1125
1126	case 'A': /* Direct (jump/call) address (ParseImmAddr). */
1127	{
1128	Assert(*pszFmt == 'p'); pszFmt++;
1129	PUT_FAR();
1130	PUT_SIZE_OVERRIDE();
1131	PUT_SEGMENT_OVERRIDE();
1132	off = 0;
1133	int rc = VERR_SYMBOL_NOT_FOUND;
1134	switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 \| DISUSE_IMMEDIATE_ADDR_16_32 \| DISUSE_DISPLACEMENT64 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT16))
1135	{
1136	case DISUSE_IMMEDIATE_ADDR_16_16:
1137	PUT_NUM_16(pParam->uValue >> 16);
1138	PUT_C(':');
1139	PUT_NUM_16(pParam->uValue);
1140	if (pfnGetSymbol)
1141	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1142	break;
1143	case DISUSE_IMMEDIATE_ADDR_16_32:
1144	PUT_NUM_16(pParam->uValue >> 32);
1145	PUT_C(':');
1146	PUT_NUM_32(pParam->uValue);
1147	if (pfnGetSymbol)
1148	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1149	break;
1150	case DISUSE_DISPLACEMENT16:
1151	PUT_NUM_16(pParam->uValue);
1152	if (pfnGetSymbol)
1153	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1154	break;
1155	case DISUSE_DISPLACEMENT32:
1156	PUT_NUM_32(pParam->uValue);
1157	if (pfnGetSymbol)
1158	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1159	break;
1160	case DISUSE_DISPLACEMENT64:
1161	PUT_NUM_64(pParam->uValue);
1162	if (pfnGetSymbol)
1163	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint64_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1164	break;
1165	default:
1166	AssertFailed();
1167	break;
1168	}
1169
1170	PUT_SYMBOL_TWO(rc, " [", ']');
1171	break;
1172	}
1173
1174	case 'O': /* No ModRM byte (ParseImmAddr). */
1175	{
1176	Assert(pszFmt == 'b' \|\| pszFmt == 'v'); pszFmt++;
1177	PUT_FAR();
1178	PUT_SIZE_OVERRIDE();
1179	PUT_C('[');
1180	PUT_SEGMENT_OVERRIDE();
1181	off = 0;
1182	int rc = VERR_SYMBOL_NOT_FOUND;
1183	switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 \| DISUSE_IMMEDIATE_ADDR_16_32 \| DISUSE_DISPLACEMENT64 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT16))
1184	{
1185	case DISUSE_IMMEDIATE_ADDR_16_16:
1186	PUT_NUM_16(pParam->uValue >> 16);
1187	PUT_C(':');
1188	PUT_NUM_16(pParam->uValue);
1189	if (pfnGetSymbol)
1190	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1191	break;
1192	case DISUSE_IMMEDIATE_ADDR_16_32:
1193	PUT_NUM_16(pParam->uValue >> 32);
1194	PUT_C(':');
1195	PUT_NUM_32(pParam->uValue);
1196	if (pfnGetSymbol)
1197	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1198	break;
1199	case DISUSE_DISPLACEMENT16:
1200	PUT_NUM_16(pParam->uDisp.i16);
1201	if (pfnGetSymbol)
1202	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u16, szSymbol, sizeof(szSymbol), &off, pvUser);
1203	break;
1204	case DISUSE_DISPLACEMENT32:
1205	PUT_NUM_32(pParam->uDisp.i32);
1206	if (pfnGetSymbol)
1207	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u32, szSymbol, sizeof(szSymbol), &off, pvUser);
1208	break;
1209	case DISUSE_DISPLACEMENT64:
1210	PUT_NUM_64(pParam->uDisp.i64);
1211	if (pfnGetSymbol)
1212	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u64, szSymbol, sizeof(szSymbol), &off, pvUser);
1213	break;
1214	default:
1215	AssertFailed();
1216	break;
1217	}
1218	PUT_C(']');
1219
1220	PUT_SYMBOL_TWO(rc, " (", ')');
1221	break;
1222	}
1223
1224	case 'X': /* DS:SI (ParseXb, ParseXv). */
1225	case 'Y': /* ES:DI (ParseYb, ParseYv). */
1226	{
1227	Assert(pszFmt == 'b' \|\| pszFmt == 'v'); pszFmt++;
1228	PUT_FAR();
1229	PUT_SIZE_OVERRIDE();
1230	PUT_C('[');
1231	if (pParam->fUse & DISUSE_POINTER_DS_BASED)
1232	PUT_SZ("ds:");
1233	else
1234	PUT_SZ("es:");
1235
1236	size_t cchReg;
1237	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
1238	PUT_STR(pszReg, cchReg);
1239	PUT_C(']');
1240	break;
1241	}
1242
1243	case 'e': /* Register based on operand size (e.g. %eAX, %eAH) (ParseFixedReg). */
1244	{
1245	Assert(RT_C_IS_ALPHA(pszFmt[0]) && RT_C_IS_ALPHA(pszFmt[1]) && !RT_C_IS_ALPHA(pszFmt[2]));
1246	pszFmt += 2;
1247	size_t cchReg;
1248	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
1249	PUT_STR(pszReg, cchReg);
1250	break;
1251	}
1252
1253	default:
1254	AssertMsgFailed(("%c%s!\n", ch, pszFmt));
1255	break;
1256	}
1257	AssertMsg(pszFmt == ',' \|\| pszFmt == '\0', ("%c%s\n", ch, pszFmt));
1258	}
1259	else
1260	{
1261	PUT_C(ch);
1262	if (ch == ',')
1263	{
1264	Assert(*pszFmt != ' ');
1265	PUT_C(' ');
1266	switch (++iParam)
1267	{
1268	case 2: pParam = &pDis->Param2; break;
1269	case 3: pParam = &pDis->Param3; break;
1270	case 4: pParam = &pDis->Param4; break;
1271	default: pParam = NULL; break;
1272	}
1273	}
1274	}
1275	} /* while more to format */
1276	}
1277
1278	/*
1279	* Any additional output to the right of the instruction?
1280	*/
1281	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
1282	{
1283	/* some up front padding. */
1284	size_t cchPadding = cchOutput - offInstruction;
1285	cchPadding = cchPadding + 1 >= 42 ? 1 : 42 - cchPadding;
1286	PUT_STR(g_szSpaces, cchPadding);
1287
1288	/* comment? */
1289	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
1290	PUT_SZ(";");
1291
1292	/*
1293	* The address?
1294	*/
1295	if (fFlags & DIS_FMT_FLAGS_ADDR_RIGHT)
1296	{
1297	PUT_C(' ');
1298	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
1299	if (pDis->uInstrAddr >= _4G)
1300	PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
1301	#endif
1302	PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
1303	}
1304
1305	/*
1306	* Opcode bytes?
1307	*/
1308	if (fFlags & DIS_FMT_FLAGS_BYTES_RIGHT)
1309	{
1310	PUT_C(' ');
1311	size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
1312	cchOutput += cchTmp;
1313	if (cchTmp >= cchDst)
1314	cchTmp = cchDst - (cchDst != 0);
1315	cchDst -= cchTmp;
1316	pszDst += cchTmp;
1317	}
1318	}
1319
1320	/*
1321	* Terminate it - on overflow we'll have reserved one byte for this.
1322	*/
1323	if (cchDst > 0)
1324	*pszDst = '\0';
1325	else
1326	Assert(!cchBuf);
1327
1328	/* clean up macros */
1329	#undef PUT_PSZ
1330	#undef PUT_SZ
1331	#undef PUT_STR
1332	#undef PUT_C
1333	return cchOutput;
1334	}
1335
1336
1337	/**
1338	* Formats the current instruction in Yasm (/ Nasm) style.
1339	*
1340	* This is a simplified version of DISFormatYasmEx() provided for your convenience.
1341	*
1342	*
1343	* @returns The number of output characters. If this is >= cchBuf, then the content
1344	* of pszBuf will be truncated.
1345	* @param pDis Pointer to the disassembler state.
1346	* @param pszBuf The output buffer.
1347	* @param cchBuf The size of the output buffer.
1348	*/
1349	DISDECL(size_t) DISFormatYasm(PCDISSTATE pDis, char *pszBuf, size_t cchBuf)
1350	{
1351	return DISFormatYasmEx(pDis, pszBuf, cchBuf, 0 /* fFlags /, NULL / pfnGetSymbol /, NULL / pvUser */);
1352	}
1353
1354
1355	/**
1356	* Checks if the encoding of the given disassembled instruction is something we
1357	* can never get YASM to produce.
1358	*
1359	* @returns true if it's odd, false if it isn't.
1360	* @param pDis The disassembler output. The byte fetcher callback will
1361	* be used if present as we might need to fetch opcode
1362	* bytes.
1363	*/
1364	DISDECL(bool) DISFormatYasmIsOddEncoding(PDISSTATE pDis)
1365	{
1366	/*
1367	* Mod rm + SIB: Check for duplicate EBP encodings that yasm won't use for very good reasons.
1368	*/
1369	if ( pDis->uAddrMode != DISCPUMODE_16BIT ///@todo correct?
1370	&& pDis->ModRM.Bits.Rm == 4
1371	&& pDis->ModRM.Bits.Mod != 3)
1372	{
1373	/* No scaled index SIB (index=4), except for ESP. */
1374	if ( pDis->SIB.Bits.Index == 4
1375	&& pDis->SIB.Bits.Base != 4)
1376	return true;
1377
1378	/* EBP + displacement */
1379	if ( pDis->ModRM.Bits.Mod != 0
1380	&& pDis->SIB.Bits.Base == 5
1381	&& pDis->SIB.Bits.Scale == 0)
1382	return true;
1383	}
1384
1385	/*
1386	* Seems to be an instruction alias here, but I cannot find any docs on it... hrmpf!
1387	*/
1388	if ( pDis->pCurInstr->uOpcode == OP_SHL
1389	&& pDis->ModRM.Bits.Reg == 6)
1390	return true;
1391
1392	/*
1393	* Check for multiple prefixes of the same kind.
1394	*/
1395	uint8_t off1stSeg = UINT8_MAX;
1396	uint8_t offOpSize = UINT8_MAX;
1397	uint8_t offAddrSize = UINT8_MAX;
1398	uint32_t fPrefixes = 0;
1399	for (uint32_t offOpcode = 0; offOpcode < RT_ELEMENTS(pDis->abInstr); offOpcode++)
1400	{
1401	uint32_t f;
1402	switch (pDis->abInstr[offOpcode])
1403	{
1404	case 0xf0:
1405	f = DISPREFIX_LOCK;
1406	break;
1407
1408	case 0xf2:
1409	case 0xf3:
1410	f = DISPREFIX_REP; /* yes, both */
1411	break;
1412
1413	case 0x2e:
1414	case 0x3e:
1415	case 0x26:
1416	case 0x36:
1417	case 0x64:
1418	case 0x65:
1419	if (off1stSeg == UINT8_MAX)
1420	off1stSeg = offOpcode;
1421	f = DISPREFIX_SEG;
1422	break;
1423
1424	case 0x66:
1425	if (offOpSize == UINT8_MAX)
1426	offOpSize = offOpcode;
1427	f = DISPREFIX_OPSIZE;
1428	break;
1429
1430	case 0x67:
1431	if (offAddrSize == UINT8_MAX)
1432	offAddrSize = offOpcode;
1433	f = DISPREFIX_ADDRSIZE;
1434	break;
1435
1436	case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
1437	case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
1438	f = pDis->uCpuMode == DISCPUMODE_64BIT ? DISPREFIX_REX : 0;
1439	break;
1440
1441	default:
1442	f = 0;
1443	break;
1444	}
1445	if (!f)
1446	break; /* done */
1447	if (fPrefixes & f)
1448	return true;
1449	fPrefixes \|= f;
1450	}
1451
1452	/* segment overrides are fun */
1453	if (fPrefixes & DISPREFIX_SEG)
1454	{
1455	/* no effective address which it may apply to. */
1456	Assert((pDis->fPrefix & DISPREFIX_SEG) \|\| pDis->uCpuMode == DISCPUMODE_64BIT);
1457	if ( !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
1458	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
1459	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse))
1460	return true;
1461
1462	/* Yasm puts the segment prefixes before the operand prefix with no
1463	way of overriding it. */
1464	if (offOpSize < off1stSeg)
1465	return true;
1466	}
1467
1468	/* fixed register + addr override doesn't go down all that well. */
1469	if (fPrefixes & DISPREFIX_ADDRSIZE)
1470	{
1471	Assert(pDis->fPrefix & DISPREFIX_ADDRSIZE);
1472	if ( pDis->pCurInstr->fParam3 == OP_PARM_NONE
1473	&& pDis->pCurInstr->fParam2 == OP_PARM_NONE
1474	&& ( pDis->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
1475	&& pDis->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END))
1476	return true;
1477	}
1478
1479	/* Almost all prefixes are bad for jumps. */
1480	if (fPrefixes)
1481	{
1482	switch (pDis->pCurInstr->uOpcode)
1483	{
1484	/* nop w/ prefix(es). */
1485	case OP_NOP:
1486	return true;
1487
1488	case OP_JMP:
1489	if ( pDis->pCurInstr->fParam1 != OP_PARM_Jb
1490	&& pDis->pCurInstr->fParam1 != OP_PARM_Jv)
1491	break;
1492	/* fall thru */
1493	case OP_JO:
1494	case OP_JNO:
1495	case OP_JC:
1496	case OP_JNC:
1497	case OP_JE:
1498	case OP_JNE:
1499	case OP_JBE:
1500	case OP_JNBE:
1501	case OP_JS:
1502	case OP_JNS:
1503	case OP_JP:
1504	case OP_JNP:
1505	case OP_JL:
1506	case OP_JNL:
1507	case OP_JLE:
1508	case OP_JNLE:
1509	/** @todo branch hinting 0x2e/0x3e... */
1510	return true;
1511	}
1512
1513	}
1514
1515	/* All but the segment prefix is bad news for push/pop. */
1516	if (fPrefixes & ~DISPREFIX_SEG)
1517	{
1518	switch (pDis->pCurInstr->uOpcode)
1519	{
1520	case OP_POP:
1521	case OP_PUSH:
1522	if ( pDis->pCurInstr->fParam1 >= OP_PARM_REG_SEG_START
1523	&& pDis->pCurInstr->fParam1 <= OP_PARM_REG_SEG_END)
1524	return true;
1525	if ( (fPrefixes & ~DISPREFIX_OPSIZE)
1526	&& pDis->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
1527	&& pDis->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END)
1528	return true;
1529	break;
1530
1531	case OP_POPA:
1532	case OP_POPF:
1533	case OP_PUSHA:
1534	case OP_PUSHF:
1535	if (fPrefixes & ~DISPREFIX_OPSIZE)
1536	return true;
1537	break;
1538	}
1539	}
1540
1541	/* Implicit 8-bit register instructions doesn't mix with operand size. */
1542	if ( (fPrefixes & DISPREFIX_OPSIZE)
1543	&& ( ( pDis->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
1544	&& pDis->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
1545	\|\| ( pDis->pCurInstr->fParam2 == OP_PARM_Gb /* r8 */
1546	&& pDis->pCurInstr->fParam1 == OP_PARM_Eb /* r8/mem8 */))
1547	)
1548	{
1549	switch (pDis->pCurInstr->uOpcode)
1550	{
1551	case OP_ADD:
1552	case OP_OR:
1553	case OP_ADC:
1554	case OP_SBB:
1555	case OP_AND:
1556	case OP_SUB:
1557	case OP_XOR:
1558	case OP_CMP:
1559	return true;
1560	default:
1561	break;
1562	}
1563	}
1564
1565	/* Instructions taking no address or operand which thus may be annoyingly
1566	difficult to format for yasm. */
1567	if (fPrefixes)
1568	{
1569	switch (pDis->pCurInstr->uOpcode)
1570	{
1571	case OP_STI:
1572	case OP_STC:
1573	case OP_CLI:
1574	case OP_CLD:
1575	case OP_CLC:
1576	case OP_INT:
1577	case OP_INT3:
1578	case OP_INTO:
1579	case OP_HLT:
1580	/** @todo Many more to can be added here. */
1581	return true;
1582	default:
1583	break;
1584	}
1585	}
1586
1587	/* FPU and other instructions that ignores operand size override. */
1588	if (fPrefixes & DISPREFIX_OPSIZE)
1589	{
1590	switch (pDis->pCurInstr->uOpcode)
1591	{
1592	/* FPU: */
1593	case OP_FIADD:
1594	case OP_FIMUL:
1595	case OP_FISUB:
1596	case OP_FISUBR:
1597	case OP_FIDIV:
1598	case OP_FIDIVR:
1599	/** @todo there are many more. */
1600	return true;
1601
1602	case OP_MOV:
1603	/** @todo could be that we're not disassembling these correctly. */
1604	if (pDis->pCurInstr->fParam1 == OP_PARM_Sw)
1605	return true;
1606	/** @todo what about the other way? */
1607	break;
1608
1609	default:
1610	break;
1611	}
1612	}
1613
1614
1615	/*
1616	* Check for the version of xyz reg,reg instruction that the assembler doesn't use.
1617	*
1618	* For example:
1619	* expected: 1aee sbb ch, dh ; SBB r8, r/m8
1620	* yasm: 18F5 sbb ch, dh ; SBB r/m8, r8
1621	*/
1622	if (pDis->ModRM.Bits.Mod == 3 /* reg,reg */)
1623	{
1624	switch (pDis->pCurInstr->uOpcode)
1625	{
1626	case OP_ADD:
1627	case OP_OR:
1628	case OP_ADC:
1629	case OP_SBB:
1630	case OP_AND:
1631	case OP_SUB:
1632	case OP_XOR:
1633	case OP_CMP:
1634	if ( ( pDis->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
1635	&& pDis->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
1636	\|\| ( pDis->pCurInstr->fParam1 == OP_PARM_Gv /* rX */
1637	&& pDis->pCurInstr->fParam2 == OP_PARM_Ev /* rX/memX */))
1638	return true;
1639
1640	/* 82 (see table A-6). */
1641	if (pDis->bOpCode == 0x82)
1642	return true;
1643	break;
1644
1645	/* ff /0, fe /0, ff /1, fe /0 */
1646	case OP_DEC:
1647	case OP_INC:
1648	return true;
1649
1650	case OP_POP:
1651	case OP_PUSH:
1652	Assert(pDis->bOpCode == 0x8f);
1653	return true;
1654
1655	case OP_MOV:
1656	if ( pDis->bOpCode == 0x8a
1657	\|\| pDis->bOpCode == 0x8b)
1658	return true;
1659	break;
1660
1661	default:
1662	break;
1663	}
1664	}
1665
1666	/* shl eax,1 will be assembled to the form without the immediate byte. */
1667	if ( pDis->pCurInstr->fParam2 == OP_PARM_Ib
1668	&& (uint8_t)pDis->Param2.uValue == 1)
1669	{
1670	switch (pDis->pCurInstr->uOpcode)
1671	{
1672	case OP_SHL:
1673	case OP_SHR:
1674	case OP_SAR:
1675	case OP_RCL:
1676	case OP_RCR:
1677	case OP_ROL:
1678	case OP_ROR:
1679	return true;
1680	}
1681	}
1682
1683	/* And some more - see table A-6. */
1684	if (pDis->bOpCode == 0x82)
1685	{
1686	switch (pDis->pCurInstr->uOpcode)
1687	{
1688	case OP_ADD:
1689	case OP_OR:
1690	case OP_ADC:
1691	case OP_SBB:
1692	case OP_AND:
1693	case OP_SUB:
1694	case OP_XOR:
1695	case OP_CMP:
1696	return true;
1697	break;
1698	}
1699	}
1700
1701
1702	/* check for REX.X = 1 without SIB. */
1703
1704	/* Yasm encodes setnbe al with /2 instead of /0 like the AMD manual
1705	says (intel doesn't appear to care). */
1706	switch (pDis->pCurInstr->uOpcode)
1707	{
1708	case OP_SETO:
1709	case OP_SETNO:
1710	case OP_SETC:
1711	case OP_SETNC:
1712	case OP_SETE:
1713	case OP_SETNE:
1714	case OP_SETBE:
1715	case OP_SETNBE:
1716	case OP_SETS:
1717	case OP_SETNS:
1718	case OP_SETP:
1719	case OP_SETNP:
1720	case OP_SETL:
1721	case OP_SETNL:
1722	case OP_SETLE:
1723	case OP_SETNLE:
1724	AssertMsg(pDis->bOpCode >= 0x90 && pDis->bOpCode <= 0x9f, ("%#x\n", pDis->bOpCode));
1725	if (pDis->ModRM.Bits.Reg != 2)
1726	return true;
1727	break;
1728	}
1729
1730	/*
1731	* The MOVZX reg32,mem16 instruction without an operand size prefix
1732	* doesn't quite make sense...
1733	*/
1734	if ( pDis->pCurInstr->uOpcode == OP_MOVZX
1735	&& pDis->bOpCode == 0xB7
1736	&& (pDis->uCpuMode == DISCPUMODE_16BIT) != !!(fPrefixes & DISPREFIX_OPSIZE))
1737	return true;
1738
1739	return false;
1740	}
1741

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source: vbox/trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp@ 62452

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