DisasmFormatYasm.cpp@ 63457

Last change on this file since 63457 was 63457, checked in by vboxsync, 8 years ago
unused static variable
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1	/* $Id: DisasmFormatYasm.cpp 63457 2016-08-15 07:36:59Z vboxsync $ */
2	/** @file
3	* VBox Disassembler - Yasm(/Nasm) Style Formatter.
4	*/
5
6	/*
7	* Copyright (C) 2008-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#include <VBox/dis.h>
23	#include "DisasmInternal.h"
24	#include <iprt/string.h>
25	#include <iprt/assert.h>
26	#include <iprt/ctype.h>
27
28
29	/*********************************************************************************************************************************
30	* Global Variables *
31	*********************************************************************************************************************************/
32	static const char g_szSpaces[] =
33	" ";
34	static const char g_aszYasmRegGen8[20][5] =
35	{
36	"al\0\0", "cl\0\0", "dl\0\0", "bl\0\0", "ah\0\0", "ch\0\0", "dh\0\0", "bh\0\0", "r8b\0", "r9b\0", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b", "spl\0", "bpl\0", "sil\0", "dil\0"
37	};
38	static const char g_aszYasmRegGen16[16][5] =
39	{
40	"ax\0\0", "cx\0\0", "dx\0\0", "bx\0\0", "sp\0\0", "bp\0\0", "si\0\0", "di\0\0", "r8w\0", "r9w\0", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
41	};
42	#if 0 /* unused */
43	static const char g_aszYasmRegGen1616[8][6] =
44	{
45	"bx+si", "bx+di", "bp+si", "bp+di", "si\0\0\0", "di\0\0\0", "bp\0\0\0", "bx\0\0\0"
46	};
47	#endif
48	static const char g_aszYasmRegGen32[16][5] =
49	{
50	"eax\0", "ecx\0", "edx\0", "ebx\0", "esp\0", "ebp\0", "esi\0", "edi\0", "r8d\0", "r9d\0", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
51	};
52	static const char g_aszYasmRegGen64[16][4] =
53	{
54	"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", "r8\0", "r9\0", "r10", "r11", "r12", "r13", "r14", "r15"
55	};
56	static const char g_aszYasmRegSeg[6][3] =
57	{
58	"es", "cs", "ss", "ds", "fs", "gs"
59	};
60	static const char g_aszYasmRegFP[8][4] =
61	{
62	"st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7"
63	};
64	static const char g_aszYasmRegMMX[8][4] =
65	{
66	"mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7"
67	};
68	static const char g_aszYasmRegXMM[16][6] =
69	{
70	"xmm0\0", "xmm1\0", "xmm2\0", "xmm3\0", "xmm4\0", "xmm5\0", "xmm6\0", "xmm7\0", "xmm8\0", "xmm9\0", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
71	};
72	static const char g_aszYasmRegYMM[16][6] =
73	{
74	"ymm0\0", "ymm1\0", "ymm2\0", "ymm3\0", "ymm4\0", "ymm5\0", "ymm6\0", "ymm7\0", "ymm8\0", "ymm9\0", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15"
75	};
76	static const char g_aszYasmRegCRx[16][5] =
77	{
78	"cr0\0", "cr1\0", "cr2\0", "cr3\0", "cr4\0", "cr5\0", "cr6\0", "cr7\0", "cr8\0", "cr9\0", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15"
79	};
80	static const char g_aszYasmRegDRx[16][5] =
81	{
82	"dr0\0", "dr1\0", "dr2\0", "dr3\0", "dr4\0", "dr5\0", "dr6\0", "dr7\0", "dr8\0", "dr9\0", "dr10", "dr11", "dr12", "dr13", "dr14", "dr15"
83	};
84	static const char g_aszYasmRegTRx[16][5] =
85	{
86	"tr0\0", "tr1\0", "tr2\0", "tr3\0", "tr4\0", "tr5\0", "tr6\0", "tr7\0", "tr8\0", "tr9\0", "tr10", "tr11", "tr12", "tr13", "tr14", "tr15"
87	};
88
89
90
91	/**
92	* Gets the base register name for the given parameter.
93	*
94	* @returns Pointer to the register name.
95	* @param pDis The disassembler state.
96	* @param pParam The parameter.
97	* @param pcchReg Where to store the length of the name.
98	*/
99	static const char disasmFormatYasmBaseReg(PCDISSTATE pDis, PCDISOPPARAM pParam, size_t pcchReg)
100	{
101	RT_NOREF_PV(pDis);
102
103	switch (pParam->fUse & ( DISUSE_REG_GEN8 \| DISUSE_REG_GEN16 \| DISUSE_REG_GEN32 \| DISUSE_REG_GEN64
104	\| DISUSE_REG_FP \| DISUSE_REG_MMX \| DISUSE_REG_XMM \| DISUSE_REG_YMM
105	\| DISUSE_REG_CR \| DISUSE_REG_DBG \| DISUSE_REG_SEG \| DISUSE_REG_TEST))
106
107	{
108	case DISUSE_REG_GEN8:
109	{
110	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen8));
111	const char *psz = g_aszYasmRegGen8[pParam->Base.idxGenReg];
112	*pcchReg = 2 + !!psz[2] + !!psz[3];
113	return psz;
114	}
115
116	case DISUSE_REG_GEN16:
117	{
118	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
119	const char *psz = g_aszYasmRegGen16[pParam->Base.idxGenReg];
120	*pcchReg = 2 + !!psz[2] + !!psz[3];
121	return psz;
122	}
123
124	// VSIB
125	case DISUSE_REG_XMM \| DISUSE_REG_GEN32:
126	case DISUSE_REG_YMM \| DISUSE_REG_GEN32:
127	case DISUSE_REG_GEN32:
128	{
129	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
130	const char *psz = g_aszYasmRegGen32[pParam->Base.idxGenReg];
131	*pcchReg = 2 + !!psz[2] + !!psz[3];
132	return psz;
133	}
134
135	// VSIB
136	case DISUSE_REG_XMM \| DISUSE_REG_GEN64:
137	case DISUSE_REG_YMM \| DISUSE_REG_GEN64:
138	case DISUSE_REG_GEN64:
139	{
140	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
141	const char *psz = g_aszYasmRegGen64[pParam->Base.idxGenReg];
142	*pcchReg = 2 + !!psz[2] + !!psz[3];
143	return psz;
144	}
145
146	case DISUSE_REG_FP:
147	{
148	Assert(pParam->Base.idxFpuReg < RT_ELEMENTS(g_aszYasmRegFP));
149	const char *psz = g_aszYasmRegFP[pParam->Base.idxFpuReg];
150	*pcchReg = 3;
151	return psz;
152	}
153
154	case DISUSE_REG_MMX:
155	{
156	Assert(pParam->Base.idxMmxReg < RT_ELEMENTS(g_aszYasmRegMMX));
157	const char *psz = g_aszYasmRegMMX[pParam->Base.idxMmxReg];
158	*pcchReg = 3;
159	return psz;
160	}
161
162	case DISUSE_REG_XMM:
163	{
164	Assert(pParam->Base.idxXmmReg < RT_ELEMENTS(g_aszYasmRegXMM));
165	const char *psz = g_aszYasmRegXMM[pParam->Base.idxXmmReg];
166	*pcchReg = 4 + !!psz[4];
167	return psz;
168	}
169
170	case DISUSE_REG_YMM:
171	{
172	Assert(pParam->Base.idxYmmReg < RT_ELEMENTS(g_aszYasmRegYMM));
173	const char *psz = g_aszYasmRegYMM[pParam->Base.idxYmmReg];
174	*pcchReg = 4 + !!psz[4];
175	return psz;
176	}
177
178	case DISUSE_REG_CR:
179	{
180	Assert(pParam->Base.idxCtrlReg < RT_ELEMENTS(g_aszYasmRegCRx));
181	const char *psz = g_aszYasmRegCRx[pParam->Base.idxCtrlReg];
182	*pcchReg = 3;
183	return psz;
184	}
185
186	case DISUSE_REG_DBG:
187	{
188	Assert(pParam->Base.idxDbgReg < RT_ELEMENTS(g_aszYasmRegDRx));
189	const char *psz = g_aszYasmRegDRx[pParam->Base.idxDbgReg];
190	*pcchReg = 3;
191	return psz;
192	}
193
194	case DISUSE_REG_SEG:
195	{
196	Assert(pParam->Base.idxSegReg < RT_ELEMENTS(g_aszYasmRegCRx));
197	const char *psz = g_aszYasmRegSeg[pParam->Base.idxSegReg];
198	*pcchReg = 2;
199	return psz;
200	}
201
202	case DISUSE_REG_TEST:
203	{
204	Assert(pParam->Base.idxTestReg < RT_ELEMENTS(g_aszYasmRegTRx));
205	const char *psz = g_aszYasmRegTRx[pParam->Base.idxTestReg];
206	*pcchReg = 3;
207	return psz;
208	}
209
210	default:
211	AssertMsgFailed(("%#x\n", pParam->fUse));
212	*pcchReg = 3;
213	return "r??";
214	}
215	}
216
217
218	/**
219	* Gets the index register name for the given parameter.
220	*
221	* @returns The index register name.
222	* @param pDis The disassembler state.
223	* @param pParam The parameter.
224	* @param pcchReg Where to store the length of the name.
225	*/
226	static const char disasmFormatYasmIndexReg(PCDISSTATE pDis, PCDISOPPARAM pParam, size_t pcchReg)
227	{
228	if (pParam->fUse & DISUSE_REG_XMM)
229	{
230	Assert(pParam->Index.idxXmmReg < RT_ELEMENTS(g_aszYasmRegXMM));
231	const char *psz = g_aszYasmRegXMM[pParam->Index.idxXmmReg];
232	*pcchReg = 4 + !!psz[4];
233	return psz;
234	}
235	else if (pParam->fUse & DISUSE_REG_YMM)
236	{
237	Assert(pParam->Index.idxYmmReg < RT_ELEMENTS(g_aszYasmRegYMM));
238	const char *psz = g_aszYasmRegYMM[pParam->Index.idxYmmReg];
239	*pcchReg = 4 + !!psz[4];
240	return psz;
241
242	}
243	else
244	switch (pDis->uAddrMode)
245	{
246	case DISCPUMODE_16BIT:
247	{
248	Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
249	const char *psz = g_aszYasmRegGen16[pParam->Index.idxGenReg];
250	*pcchReg = 2 + !!psz[2] + !!psz[3];
251	return psz;
252	}
253
254	case DISCPUMODE_32BIT:
255	{
256	Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
257	const char *psz = g_aszYasmRegGen32[pParam->Index.idxGenReg];
258	*pcchReg = 2 + !!psz[2] + !!psz[3];
259	return psz;
260	}
261
262	case DISCPUMODE_64BIT:
263	{
264	Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
265	const char *psz = g_aszYasmRegGen64[pParam->Index.idxGenReg];
266	*pcchReg = 2 + !!psz[2] + !!psz[3];
267	return psz;
268	}
269
270	default:
271	AssertMsgFailed(("%#x %#x\n", pParam->fUse, pDis->uAddrMode));
272	*pcchReg = 3;
273	return "r??";
274	}
275	}
276
277
278	/**
279	* Formats the current instruction in Yasm (/ Nasm) style.
280	*
281	*
282	* @returns The number of output characters. If this is >= cchBuf, then the content
283	* of pszBuf will be truncated.
284	* @param pDis Pointer to the disassembler state.
285	* @param pszBuf The output buffer.
286	* @param cchBuf The size of the output buffer.
287	* @param fFlags Format flags, see DIS_FORMAT_FLAGS_*.
288	* @param pfnGetSymbol Get symbol name for a jmp or call target address. Optional.
289	* @param pvUser User argument for pfnGetSymbol.
290	*/
291	DISDECL(size_t) DISFormatYasmEx(PCDISSTATE pDis, char *pszBuf, size_t cchBuf, uint32_t fFlags,
292	PFNDISGETSYMBOL pfnGetSymbol, void *pvUser)
293	{
294	/** @todo monitor and mwait aren't formatted correctly in 64-bit mode. */
295	/*
296	* Input validation and massaging.
297	*/
298	AssertPtr(pDis);
299	AssertPtrNull(pszBuf);
300	Assert(pszBuf \|\| !cchBuf);
301	AssertPtrNull(pfnGetSymbol);
302	AssertMsg(DIS_FMT_FLAGS_IS_VALID(fFlags), ("%#x\n", fFlags));
303	if (fFlags & DIS_FMT_FLAGS_ADDR_COMMENT)
304	fFlags = (fFlags & ~DIS_FMT_FLAGS_ADDR_LEFT) \| DIS_FMT_FLAGS_ADDR_RIGHT;
305	if (fFlags & DIS_FMT_FLAGS_BYTES_COMMENT)
306	fFlags = (fFlags & ~DIS_FMT_FLAGS_BYTES_LEFT) \| DIS_FMT_FLAGS_BYTES_RIGHT;
307
308	PCDISOPCODE const pOp = pDis->pCurInstr;
309
310	/*
311	* Output macros
312	*/
313	char *pszDst = pszBuf;
314	size_t cchDst = cchBuf;
315	size_t cchOutput = 0;
316	#define PUT_C(ch) \
317	do { \
318	cchOutput++; \
319	if (cchDst > 1) \
320	{ \
321	cchDst--; \
322	*pszDst++ = (ch); \
323	} \
324	} while (0)
325	#define PUT_STR(pszSrc, cchSrc) \
326	do { \
327	cchOutput += (cchSrc); \
328	if (cchDst > (cchSrc)) \
329	{ \
330	memcpy(pszDst, (pszSrc), (cchSrc)); \
331	pszDst += (cchSrc); \
332	cchDst -= (cchSrc); \
333	} \
334	else if (cchDst > 1) \
335	{ \
336	memcpy(pszDst, (pszSrc), cchDst - 1); \
337	pszDst += cchDst - 1; \
338	cchDst = 1; \
339	} \
340	} while (0)
341	#define PUT_SZ(sz) \
342	PUT_STR((sz), sizeof(sz) - 1)
343	#define PUT_SZ_STRICT(szStrict, szRelaxed) \
344	do { if (fFlags & DIS_FMT_FLAGS_STRICT) PUT_SZ(szStrict); else PUT_SZ(szRelaxed); } while (0)
345	#define PUT_PSZ(psz) \
346	do { const size_t cchTmp = strlen(psz); PUT_STR((psz), cchTmp); } while (0)
347	#define PUT_NUM(cch, fmt, num) \
348	do { \
349	cchOutput += (cch); \
350	if (cchDst > 1) \
351	{ \
352	const size_t cchTmp = RTStrPrintf(pszDst, cchDst, fmt, (num)); \
353	pszDst += cchTmp; \
354	cchDst -= cchTmp; \
355	Assert(cchTmp == (cch) \|\| cchDst == 1); \
356	} \
357	} while (0)
358	/** @todo add two flags for choosing between %X / %x and h / 0x. */
359	#define PUT_NUM_8(num) PUT_NUM(4, "0%02xh", (uint8_t)(num))
360	#define PUT_NUM_16(num) PUT_NUM(6, "0%04xh", (uint16_t)(num))
361	#define PUT_NUM_32(num) PUT_NUM(10, "0%08xh", (uint32_t)(num))
362	#define PUT_NUM_64(num) PUT_NUM(18, "0%016RX64h", (uint64_t)(num))
363
364	#define PUT_NUM_SIGN(cch, fmt, num, stype, utype) \
365	do { \
366	if ((stype)(num) >= 0) \
367	{ \
368	PUT_C('+'); \
369	PUT_NUM(cch, fmt, (utype)(num)); \
370	} \
371	else \
372	{ \
373	PUT_C('-'); \
374	PUT_NUM(cch, fmt, (utype)-(stype)(num)); \
375	} \
376	} while (0)
377	#define PUT_NUM_S8(num) PUT_NUM_SIGN(4, "0%02xh", num, int8_t, uint8_t)
378	#define PUT_NUM_S16(num) PUT_NUM_SIGN(6, "0%04xh", num, int16_t, uint16_t)
379	#define PUT_NUM_S32(num) PUT_NUM_SIGN(10, "0%08xh", num, int32_t, uint32_t)
380	#define PUT_NUM_S64(num) PUT_NUM_SIGN(18, "0%016RX64h", num, int64_t, uint64_t)
381
382	#define PUT_SYMBOL_TWO(a_rcSym, a_szStart, a_chEnd) \
383	do { \
384	if (RT_SUCCESS(a_rcSym)) \
385	{ \
386	PUT_SZ(a_szStart); \
387	PUT_PSZ(szSymbol); \
388	if (off != 0) \
389	{ \
390	if ((int8_t)off == off) \
391	PUT_NUM_S8(off); \
392	else if ((int16_t)off == off) \
393	PUT_NUM_S16(off); \
394	else if ((int32_t)off == off) \
395	PUT_NUM_S32(off); \
396	else \
397	PUT_NUM_S64(off); \
398	} \
399	PUT_C(a_chEnd); \
400	} \
401	} while (0)
402
403	#define PUT_SYMBOL(a_uSeg, a_uAddr, a_szStart, a_chEnd) \
404	do { \
405	if (pfnGetSymbol) \
406	{ \
407	int rcSym = pfnGetSymbol(pDis, a_uSeg, a_uAddr, szSymbol, sizeof(szSymbol), &off, pvUser); \
408	PUT_SYMBOL_TWO(rcSym, a_szStart, a_chEnd); \
409	} \
410	} while (0)
411
412
413	/*
414	* The address?
415	*/
416	if (fFlags & DIS_FMT_FLAGS_ADDR_LEFT)
417	{
418	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
419	if (pDis->uInstrAddr >= _4G)
420	PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
421	#endif
422	PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
423	PUT_C(' ');
424	}
425
426	/*
427	* The opcode bytes?
428	*/
429	if (fFlags & DIS_FMT_FLAGS_BYTES_LEFT)
430	{
431	size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
432	cchOutput += cchTmp;
433	if (cchDst > 1)
434	{
435	if (cchTmp <= cchDst)
436	{
437	cchDst -= cchTmp;
438	pszDst += cchTmp;
439	}
440	else
441	{
442	pszDst += cchDst - 1;
443	cchDst = 1;
444	}
445	}
446
447	/* Some padding to align the instruction. */
448	size_t cchPadding = (7 * (2 + !!(fFlags & DIS_FMT_FLAGS_BYTES_SPACED)))
449	+ !!(fFlags & DIS_FMT_FLAGS_BYTES_BRACKETS) * 2
450	+ 2;
451	cchPadding = cchTmp + 1 >= cchPadding ? 1 : cchPadding - cchTmp;
452	PUT_STR(g_szSpaces, cchPadding);
453	}
454
455
456	/*
457	* Filter out invalid opcodes first as they need special
458	* treatment. UD2 is an exception and should be handled normally.
459	*/
460	size_t const offInstruction = cchOutput;
461	if ( pOp->uOpcode == OP_INVALID
462	\|\| ( pOp->uOpcode == OP_ILLUD2
463	&& (pDis->fPrefix & DISPREFIX_LOCK)))
464	PUT_SZ("Illegal opcode");
465	else
466	{
467	/*
468	* Prefixes
469	*/
470	if (pDis->fPrefix & DISPREFIX_LOCK)
471	PUT_SZ("lock ");
472	if (pDis->fPrefix & DISPREFIX_REP)
473	PUT_SZ("rep ");
474	else if(pDis->fPrefix & DISPREFIX_REPNE)
475	PUT_SZ("repne ");
476
477	/*
478	* Adjust the format string to the correct mnemonic
479	* or to avoid things the assembler cannot handle correctly.
480	*/
481	char szTmpFmt[48];
482	const char *pszFmt = pOp->pszOpcode;
483	bool fIgnoresOpSize = false;
484	bool fMayNeedAddrSize = false;
485	switch (pOp->uOpcode)
486	{
487	case OP_JECXZ:
488	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "jcxz %Jb" : pDis->uOpMode == DISCPUMODE_32BIT ? "jecxz %Jb" : "jrcxz %Jb";
489	break;
490	case OP_PUSHF:
491	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "pushfw" : pDis->uOpMode == DISCPUMODE_32BIT ? "pushfd" : "pushfq";
492	break;
493	case OP_POPF:
494	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "popfw" : pDis->uOpMode == DISCPUMODE_32BIT ? "popfd" : "popfq";
495	break;
496	case OP_PUSHA:
497	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "pushaw" : "pushad";
498	break;
499	case OP_POPA:
500	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "popaw" : "popad";
501	break;
502	case OP_INSB:
503	pszFmt = "insb";
504	fIgnoresOpSize = fMayNeedAddrSize = true;
505	break;
506	case OP_INSWD:
507	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "insw" : pDis->uOpMode == DISCPUMODE_32BIT ? "insd" : "insq";
508	fMayNeedAddrSize = true;
509	break;
510	case OP_OUTSB:
511	pszFmt = "outsb";
512	fIgnoresOpSize = fMayNeedAddrSize = true;
513	break;
514	case OP_OUTSWD:
515	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "outsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "outsd" : "outsq";
516	fMayNeedAddrSize = true;
517	break;
518	case OP_MOVSB:
519	pszFmt = "movsb";
520	fIgnoresOpSize = fMayNeedAddrSize = true;
521	break;
522	case OP_MOVSWD:
523	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "movsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "movsd" : "movsq";
524	fMayNeedAddrSize = true;
525	break;
526	case OP_CMPSB:
527	pszFmt = "cmpsb";
528	fIgnoresOpSize = fMayNeedAddrSize = true;
529	break;
530	case OP_CMPWD:
531	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cmpsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "cmpsd" : "cmpsq";
532	fMayNeedAddrSize = true;
533	break;
534	case OP_SCASB:
535	pszFmt = "scasb";
536	fIgnoresOpSize = fMayNeedAddrSize = true;
537	break;
538	case OP_SCASWD:
539	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "scasw" : pDis->uOpMode == DISCPUMODE_32BIT ? "scasd" : "scasq";
540	fMayNeedAddrSize = true;
541	break;
542	case OP_LODSB:
543	pszFmt = "lodsb";
544	fIgnoresOpSize = fMayNeedAddrSize = true;
545	break;
546	case OP_LODSWD:
547	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "lodsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "lodsd" : "lodsq";
548	fMayNeedAddrSize = true;
549	break;
550	case OP_STOSB:
551	pszFmt = "stosb";
552	fIgnoresOpSize = fMayNeedAddrSize = true;
553	break;
554	case OP_STOSWD:
555	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "stosw" : pDis->uOpMode == DISCPUMODE_32BIT ? "stosd" : "stosq";
556	fMayNeedAddrSize = true;
557	break;
558	case OP_CBW:
559	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cbw" : pDis->uOpMode == DISCPUMODE_32BIT ? "cwde" : "cdqe";
560	break;
561	case OP_CWD:
562	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cwd" : pDis->uOpMode == DISCPUMODE_32BIT ? "cdq" : "cqo";
563	break;
564	case OP_SHL:
565	Assert(pszFmt[3] == '/');
566	pszFmt += 4;
567	break;
568	case OP_XLAT:
569	pszFmt = "xlatb";
570	break;
571	case OP_INT3:
572	pszFmt = "int3";
573	break;
574
575	/*
576	* Don't know how to tell yasm to generate complicated nop stuff, so 'db' it.
577	*/
578	case OP_NOP:
579	if (pDis->bOpCode == 0x90)
580	/* fine, fine */;
581	else if (pszFmt[sizeof("nop %Ev") - 1] == '/' && pszFmt[sizeof("nop %Ev")] == 'p')
582	pszFmt = "prefetch %Eb";
583	else if (pDis->bOpCode == 0x1f)
584	{
585	Assert(pDis->cbInstr >= 3);
586	PUT_SZ("db 00fh, 01fh,");
587	PUT_NUM_8(MAKE_MODRM(pDis->ModRM.Bits.Mod, pDis->ModRM.Bits.Reg, pDis->ModRM.Bits.Rm));
588	for (unsigned i = 3; i < pDis->cbInstr; i++)
589	{
590	PUT_C(',');
591	PUT_NUM_8(0x90); ///@todo fixme.
592	}
593	pszFmt = "";
594	}
595	break;
596
597	default:
598	/* ST(X) -> stX (floating point) */
599	if (*pszFmt == 'f' && strchr(pszFmt, '('))
600	{
601	char *pszFmtDst = szTmpFmt;
602	char ch;
603	do
604	{
605	ch = *pszFmt++;
606	if (ch == 'S' && pszFmt[0] == 'T' && pszFmt[1] == '(')
607	{
608	*pszFmtDst++ = 's';
609	*pszFmtDst++ = 't';
610	pszFmt += 2;
611	ch = *pszFmt;
612	Assert(pszFmt[1] == ')');
613	pszFmt += 2;
614	*pszFmtDst++ = ch;
615	}
616	else
617	*pszFmtDst++ = ch;
618	} while (ch != '\0');
619	pszFmt = szTmpFmt;
620	}
621	if (strchr ("#@&", *pszFmt))
622	{
623	const char *pszDelim = strchr(pszFmt, '/');
624	const char *pszSpace = (pszDelim ? strchr(pszDelim, ' ') : NULL);
625	if (pszDelim != NULL)
626	{
627	char *pszFmtDst = szTmpFmt;
628	if (pszSpace == NULL) pszSpace = strchr(pszDelim, 0);
629	if ( (*pszFmt == '#' && pDis->bVexWFlag)
630	\|\| (*pszFmt == '@' && !VEXREG_IS256B(pDis->bVexDestReg))
631	\|\| (*pszFmt == '&' && ( DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
632	\|\| DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
633	\|\| DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse)
634	\|\| DISUSE_IS_EFFECTIVE_ADDR(pDis->Param4.fUse))))
635	{
636	strncpy(pszFmtDst, pszFmt + 1, pszDelim - pszFmt - 1);
637	pszFmtDst += pszDelim - pszFmt - 1;
638	}
639	else
640	{
641	strncpy(pszFmtDst, pszDelim + 1, pszSpace - pszDelim - 1);
642	pszFmtDst += pszSpace - pszDelim - 1;
643	}
644	strcpy (pszFmtDst, pszSpace);
645	pszFmt = szTmpFmt;
646	}
647	}
648	break;
649
650	/*
651	* Horrible hacks.
652	*/
653	case OP_FLD:
654	if (pDis->bOpCode == 0xdb) /* m80fp workaround. */
655	(int )&pDis->Param1.fParam &= ~0x1f; /* make it pure OP_PARM_M */
656	break;
657	case OP_LAR: /* hack w -> v, probably not correct. */
658	(int )&pDis->Param2.fParam &= ~0x1f;
659	(int )&pDis->Param2.fParam \|= OP_PARM_v;
660	break;
661	}
662
663	/*
664	* Add operand size and address prefixes for outsb, movsb, etc.
665	*/
666	if (pDis->fPrefix & (DISPREFIX_OPSIZE \| DISPREFIX_ADDRSIZE))
667	{
668	if (fIgnoresOpSize && (pDis->fPrefix & DISPREFIX_OPSIZE) )
669	{
670	if (pDis->uCpuMode == DISCPUMODE_16BIT)
671	PUT_SZ("o32 ");
672	else
673	PUT_SZ("o16 ");
674	}
675	if (fMayNeedAddrSize && (pDis->fPrefix & DISPREFIX_ADDRSIZE) )
676	{
677	if (pDis->uCpuMode == DISCPUMODE_16BIT)
678	PUT_SZ("a32 ");
679	else
680	PUT_SZ("a16 ");
681	}
682	}
683
684	/*
685	* Formatting context and associated macros.
686	*/
687	PCDISOPPARAM pParam = &pDis->Param1;
688	int iParam = 1;
689
690	#define PUT_FAR() \
691	do { \
692	if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_p \
693	&& pOp->uOpcode != OP_LDS /* table bugs? */ \
694	&& pOp->uOpcode != OP_LES \
695	&& pOp->uOpcode != OP_LFS \
696	&& pOp->uOpcode != OP_LGS \
697	&& pOp->uOpcode != OP_LSS ) \
698	PUT_SZ("far "); \
699	} while (0)
700	/** @todo mov ah,ch ends up with a byte 'override'... - check if this wasn't fixed. */
701	/** @todo drop the work/dword/qword override when the src/dst is a register (except for movsx/movzx). */
702	#define PUT_SIZE_OVERRIDE() \
703	do { \
704	switch (OP_PARM_VSUBTYPE(pParam->fParam)) \
705	{ \
706	case OP_PARM_v: \
707	case OP_PARM_y: \
708	switch (pDis->uOpMode) \
709	{ \
710	case DISCPUMODE_16BIT: if (OP_PARM_VSUBTYPE(pParam->fParam) != OP_PARM_y) PUT_SZ("word "); break; \
711	case DISCPUMODE_32BIT: \
712	if (pDis->pCurInstr->uOpcode != OP_GATHER \|\| pDis->bVexWFlag) { PUT_SZ("dword "); break; } \
713	case DISCPUMODE_64BIT: PUT_SZ("qword "); break; \
714	default: break; \
715	} \
716	break; \
717	case OP_PARM_b: PUT_SZ("byte "); break; \
718	case OP_PARM_w: \
719	if (OP_PARM_VTYPE(pParam->fParam) == OP_PARM_W \|\| \
720	OP_PARM_VTYPE(pParam->fParam) == OP_PARM_M) \
721	{ \
722	if (VEXREG_IS256B(pDis->bVexDestReg)) PUT_SZ("dword "); \
723	else PUT_SZ("word "); \
724	} \
725	break; \
726	case OP_PARM_d: \
727	if (OP_PARM_VTYPE(pParam->fParam) == OP_PARM_W \|\| \
728	OP_PARM_VTYPE(pParam->fParam) == OP_PARM_M) \
729	{ \
730	if (VEXREG_IS256B(pDis->bVexDestReg)) PUT_SZ("qword "); \
731	else PUT_SZ("dword "); \
732	} \
733	break; \
734	case OP_PARM_q: \
735	if (OP_PARM_VTYPE(pParam->fParam) == OP_PARM_W \|\| \
736	OP_PARM_VTYPE(pParam->fParam) == OP_PARM_M) \
737	{ \
738	if (VEXREG_IS256B(pDis->bVexDestReg)) PUT_SZ("oword "); \
739	else PUT_SZ("qword "); \
740	} \
741	break; \
742	case OP_PARM_ps: \
743	case OP_PARM_pd: \
744	case OP_PARM_x: if (VEXREG_IS256B(pDis->bVexDestReg)) { PUT_SZ("yword "); break; } \
745	case OP_PARM_ss: \
746	case OP_PARM_sd: \
747	case OP_PARM_dq: PUT_SZ("oword "); break; \
748	case OP_PARM_qq: PUT_SZ("yword "); break; \
749	case OP_PARM_p: break; /* see PUT_FAR */ \
750	case OP_PARM_s: if (pParam->fUse & DISUSE_REG_FP) PUT_SZ("tword "); break; /* ?? */ \
751	case OP_PARM_z: break; \
752	case OP_PARM_NONE: \
753	if ( OP_PARM_VTYPE(pParam->fParam) == OP_PARM_M \
754	&& ((pParam->fUse & DISUSE_REG_FP) \|\| pOp->uOpcode == OP_FLD)) \
755	PUT_SZ("tword "); \
756	break; \
757	default: break; /no pointer type specified/necessary/ \
758	} \
759	} while (0)
760	static const char s_szSegPrefix[6][4] = { "es:", "cs:", "ss:", "ds:", "fs:", "gs:" };
761	#define PUT_SEGMENT_OVERRIDE() \
762	do { \
763	if (pDis->fPrefix & DISPREFIX_SEG) \
764	PUT_STR(s_szSegPrefix[pDis->idxSegPrefix], 3); \
765	} while (0)
766
767
768	/*
769	* Segment prefixing for instructions that doesn't do memory access.
770	*/
771	if ( (pDis->fPrefix & DISPREFIX_SEG)
772	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
773	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
774	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse))
775	{
776	PUT_STR(s_szSegPrefix[pDis->idxSegPrefix], 2);
777	PUT_C(' ');
778	}
779
780
781	/*
782	* The formatting loop.
783	*/
784	RTINTPTR off;
785	char szSymbol[128];
786	char ch;
787	while ((ch = *pszFmt++) != '\0')
788	{
789	if (ch == '%')
790	{
791	ch = *pszFmt++;
792	switch (ch)
793	{
794	/*
795	* ModRM - Register only.
796	*/
797	case 'C': /* Control register (ParseModRM / UseModRM). */
798	case 'D': /* Debug register (ParseModRM / UseModRM). */
799	case 'G': /* ModRM selects general register (ParseModRM / UseModRM). */
800	case 'S': /* ModRM byte selects a segment register (ParseModRM / UseModRM). */
801	case 'T': /* ModRM byte selects a test register (ParseModRM / UseModRM). */
802	case 'V': /* ModRM byte selects an XMM/SSE register (ParseModRM / UseModRM). */
803	case 'P': /* ModRM byte selects MMX register (ParseModRM / UseModRM). */
804	case 'H': /* The VEX.vvvv field of the VEX prefix selects a XMM/YMM register. */
805	case 'L': /* The upper 4 bits of the 8-bit immediate selects a XMM/YMM register. */
806	{
807	pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
808	Assert(!(pParam->fUse & (DISUSE_INDEX \| DISUSE_SCALE) /* No SIB here... */));
809	Assert(!(pParam->fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32)));
810
811	size_t cchReg;
812	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
813	PUT_STR(pszReg, cchReg);
814	break;
815	}
816
817	/*
818	* ModRM - Register or memory.
819	*/
820	case 'E': /* ModRM specifies parameter (ParseModRM / UseModRM / UseSIB). */
821	case 'Q': /* ModRM byte selects MMX register or memory address (ParseModRM / UseModRM). */
822	case 'R': /* ModRM byte may only refer to a general register (ParseModRM / UseModRM). */
823	case 'W': /* ModRM byte selects an XMM/SSE register or a memory address (ParseModRM / UseModRM). */
824	case 'M': /* ModRM may only refer to memory (ParseModRM / UseModRM). */
825	{
826	pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
827
828	PUT_FAR();
829	uint32_t const fUse = pParam->fUse;
830	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
831	{
832	/* Work around mov seg,[mem16] and mov [mem16],seg as these always make a 16-bit mem
833	while the register variants deals with 16, 32 & 64 in the normal fashion. */
834	if ( pParam->fParam != OP_PARM_Ev
835	\|\| pOp->uOpcode != OP_MOV
836	\|\| ( pOp->fParam1 != OP_PARM_Sw
837	&& pOp->fParam2 != OP_PARM_Sw))
838	PUT_SIZE_OVERRIDE();
839	PUT_C('[');
840	}
841	if ( (fFlags & DIS_FMT_FLAGS_STRICT)
842	&& (fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32)))
843	{
844	if ( (fUse & DISUSE_DISPLACEMENT8)
845	&& !pParam->uDisp.i8)
846	PUT_SZ("byte ");
847	else if ( (fUse & DISUSE_DISPLACEMENT16)
848	&& (int8_t)pParam->uDisp.i16 == (int16_t)pParam->uDisp.i16)
849	PUT_SZ("word ");
850	else if ( (fUse & DISUSE_DISPLACEMENT32)
851	&& (int16_t)pParam->uDisp.i32 == (int32_t)pParam->uDisp.i32) //??
852	PUT_SZ("dword ");
853	else if ( (fUse & DISUSE_DISPLACEMENT64)
854	&& (pDis->SIB.Bits.Base != 5 \|\| pDis->ModRM.Bits.Mod != 0)
855	&& (int32_t)pParam->uDisp.i64 == (int64_t)pParam->uDisp.i64) //??
856	PUT_SZ("qword ");
857	}
858	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
859	PUT_SEGMENT_OVERRIDE();
860
861	bool fBase = (fUse & DISUSE_BASE) /* When exactly is DISUSE_BASE supposed to be set? disasmModRMReg doesn't set it. */
862	\|\| ( (fUse & ( DISUSE_REG_GEN8
863	\| DISUSE_REG_GEN16
864	\| DISUSE_REG_GEN32
865	\| DISUSE_REG_GEN64
866	\| DISUSE_REG_FP
867	\| DISUSE_REG_MMX
868	\| DISUSE_REG_XMM
869	\| DISUSE_REG_YMM
870	\| DISUSE_REG_CR
871	\| DISUSE_REG_DBG
872	\| DISUSE_REG_SEG
873	\| DISUSE_REG_TEST ))
874	&& !DISUSE_IS_EFFECTIVE_ADDR(fUse));
875	if (fBase)
876	{
877	size_t cchReg;
878	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
879	PUT_STR(pszReg, cchReg);
880	}
881
882	if (fUse & DISUSE_INDEX)
883	{
884	if (fBase)
885	PUT_C('+');
886
887	size_t cchReg;
888	const char *pszReg = disasmFormatYasmIndexReg(pDis, pParam, &cchReg);
889	PUT_STR(pszReg, cchReg);
890
891	if (fUse & DISUSE_SCALE)
892	{
893	PUT_C('*');
894	PUT_C('0' + pParam->uScale);
895	}
896	}
897	else
898	Assert(!(fUse & DISUSE_SCALE));
899
900	int64_t off2 = 0;
901	if (fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32))
902	{
903	if (fUse & DISUSE_DISPLACEMENT8)
904	off2 = pParam->uDisp.i8;
905	else if (fUse & DISUSE_DISPLACEMENT16)
906	off2 = pParam->uDisp.i16;
907	else if (fUse & (DISUSE_DISPLACEMENT32 \| DISUSE_RIPDISPLACEMENT32))
908	off2 = pParam->uDisp.i32;
909	else if (fUse & DISUSE_DISPLACEMENT64)
910	off2 = pParam->uDisp.i64;
911	else
912	{
913	AssertFailed();
914	off2 = 0;
915	}
916
917	int64_t off3 = off2;
918	if (fBase \|\| (fUse & (DISUSE_INDEX \| DISUSE_RIPDISPLACEMENT32)))
919	{
920	PUT_C(off3 >= 0 ? '+' : '-');
921	if (off3 < 0)
922	off3 = -off3;
923	}
924	if (fUse & DISUSE_DISPLACEMENT8)
925	PUT_NUM_8( off3);
926	else if (fUse & DISUSE_DISPLACEMENT16)
927	PUT_NUM_16(off3);
928	else if (fUse & DISUSE_DISPLACEMENT32)
929	PUT_NUM_32(off3);
930	else if (fUse & DISUSE_DISPLACEMENT64)
931	PUT_NUM_64(off3);
932	else
933	{
934	PUT_NUM_32(off3);
935	PUT_SZ(" wrt rip (");
936	off2 += pDis->uInstrAddr + pDis->cbInstr;
937	PUT_NUM_64(off2);
938	if (pfnGetSymbol)
939	PUT_SYMBOL((pDis->fPrefix & DISPREFIX_SEG)
940	? DIS_FMT_SEL_FROM_REG(pDis->idxSegPrefix)
941	: DIS_FMT_SEL_FROM_REG(DISSELREG_DS),
942	pDis->uAddrMode == DISCPUMODE_64BIT
943	? (uint64_t)off2
944	: pDis->uAddrMode == DISCPUMODE_32BIT
945	? (uint32_t)off2
946	: (uint16_t)off2,
947	" = ",
948	')');
949	else
950	PUT_C(')');
951	}
952	}
953
954	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
955	{
956	if (pfnGetSymbol && !fBase && !(fUse & (DISUSE_INDEX \| DISUSE_RIPDISPLACEMENT32)) && off2 != 0)
957	PUT_SYMBOL((pDis->fPrefix & DISPREFIX_SEG)
958	? DIS_FMT_SEL_FROM_REG(pDis->idxSegPrefix)
959	: DIS_FMT_SEL_FROM_REG(DISSELREG_DS),
960	pDis->uAddrMode == DISCPUMODE_64BIT
961	? (uint64_t)off2
962	: pDis->uAddrMode == DISCPUMODE_32BIT
963	? (uint32_t)off2
964	: (uint16_t)off2,
965	" (=",
966	')');
967	PUT_C(']');
968	}
969	break;
970	}
971
972	case 'F': /* Eflags register (0 - popf/pushf only, avoided in adjustments above). */
973	AssertFailed();
974	break;
975
976	case 'I': /* Immediate data (ParseImmByte, ParseImmByteSX, ParseImmV, ParseImmUshort, ParseImmZ). */
977	Assert(pszFmt == 'b' \|\| pszFmt == 'v' \|\| pszFmt == 'w' \|\| pszFmt == 'z'); pszFmt++;
978	switch (pParam->fUse & ( DISUSE_IMMEDIATE8 \| DISUSE_IMMEDIATE16 \| DISUSE_IMMEDIATE32 \| DISUSE_IMMEDIATE64
979	\| DISUSE_IMMEDIATE16_SX8 \| DISUSE_IMMEDIATE32_SX8 \| DISUSE_IMMEDIATE64_SX8))
980	{
981	case DISUSE_IMMEDIATE8:
982	if ( (fFlags & DIS_FMT_FLAGS_STRICT)
983	&& ( (pOp->fParam1 >= OP_PARM_REG_GEN8_START && pOp->fParam1 <= OP_PARM_REG_GEN8_END)
984	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN8_START && pOp->fParam2 <= OP_PARM_REG_GEN8_END))
985	)
986	PUT_SZ("strict byte ");
987	PUT_NUM_8(pParam->uValue);
988	break;
989
990	case DISUSE_IMMEDIATE16:
991	if ( pDis->uCpuMode != pDis->uOpMode
992	\|\| ( (fFlags & DIS_FMT_FLAGS_STRICT)
993	&& ( (int8_t)pParam->uValue == (int16_t)pParam->uValue
994	\|\| (pOp->fParam1 >= OP_PARM_REG_GEN16_START && pOp->fParam1 <= OP_PARM_REG_GEN16_END)
995	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN16_START && pOp->fParam2 <= OP_PARM_REG_GEN16_END))
996	)
997	)
998	{
999	if (OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_b)
1000	PUT_SZ_STRICT("strict byte ", "byte ");
1001	else if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_v
1002	\|\| OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_z)
1003	PUT_SZ_STRICT("strict word ", "word ");
1004	}
1005	PUT_NUM_16(pParam->uValue);
1006	break;
1007
1008	case DISUSE_IMMEDIATE16_SX8:
1009	if ( !(pDis->fPrefix & DISPREFIX_OPSIZE)
1010	\|\| pDis->pCurInstr->uOpcode != OP_PUSH)
1011	PUT_SZ_STRICT("strict byte ", "byte ");
1012	else
1013	PUT_SZ("word ");
1014	PUT_NUM_16(pParam->uValue);
1015	break;
1016
1017	case DISUSE_IMMEDIATE32:
1018	if ( pDis->uOpMode != (pDis->uCpuMode == DISCPUMODE_16BIT ? DISCPUMODE_16BIT : DISCPUMODE_32BIT) /* not perfect */
1019	\|\| ( (fFlags & DIS_FMT_FLAGS_STRICT)
1020	&& ( (int8_t)pParam->uValue == (int32_t)pParam->uValue
1021	\|\| (pOp->fParam1 >= OP_PARM_REG_GEN32_START && pOp->fParam1 <= OP_PARM_REG_GEN32_END)
1022	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN32_START && pOp->fParam2 <= OP_PARM_REG_GEN32_END))
1023	)
1024	)
1025	{
1026	if (OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_b)
1027	PUT_SZ_STRICT("strict byte ", "byte ");
1028	else if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_v
1029	\|\| OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_z)
1030	PUT_SZ_STRICT("strict dword ", "dword ");
1031	}
1032	PUT_NUM_32(pParam->uValue);
1033	if (pDis->uCpuMode == DISCPUMODE_32BIT)
1034	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uValue, " (=", ')');
1035	break;
1036
1037	case DISUSE_IMMEDIATE32_SX8:
1038	if ( !(pDis->fPrefix & DISPREFIX_OPSIZE)
1039	\|\| pDis->pCurInstr->uOpcode != OP_PUSH)
1040	PUT_SZ_STRICT("strict byte ", "byte ");
1041	else
1042	PUT_SZ("dword ");
1043	PUT_NUM_32(pParam->uValue);
1044	break;
1045
1046	case DISUSE_IMMEDIATE64_SX8:
1047	if ( !(pDis->fPrefix & DISPREFIX_OPSIZE)
1048	\|\| pDis->pCurInstr->uOpcode != OP_PUSH)
1049	PUT_SZ_STRICT("strict byte ", "byte ");
1050	else
1051	PUT_SZ("qword ");
1052	PUT_NUM_64(pParam->uValue);
1053	break;
1054
1055	case DISUSE_IMMEDIATE64:
1056	PUT_NUM_64(pParam->uValue);
1057	break;
1058
1059	default:
1060	AssertFailed();
1061	break;
1062	}
1063	break;
1064
1065	case 'J': /* Relative jump offset (ParseImmBRel + ParseImmVRel). */
1066	{
1067	int32_t offDisplacement;
1068	Assert(iParam == 1);
1069	bool fPrefix = (fFlags & DIS_FMT_FLAGS_STRICT)
1070	&& pOp->uOpcode != OP_CALL
1071	&& pOp->uOpcode != OP_LOOP
1072	&& pOp->uOpcode != OP_LOOPE
1073	&& pOp->uOpcode != OP_LOOPNE
1074	&& pOp->uOpcode != OP_JECXZ;
1075	if (pOp->uOpcode == OP_CALL)
1076	fFlags &= ~DIS_FMT_FLAGS_RELATIVE_BRANCH;
1077
1078	if (pParam->fUse & DISUSE_IMMEDIATE8_REL)
1079	{
1080	if (fPrefix)
1081	PUT_SZ("short ");
1082	offDisplacement = (int8_t)pParam->uValue;
1083	Assert(*pszFmt == 'b'); pszFmt++;
1084
1085	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1086	PUT_NUM_S8(offDisplacement);
1087	}
1088	else if (pParam->fUse & DISUSE_IMMEDIATE16_REL)
1089	{
1090	if (fPrefix)
1091	PUT_SZ("near ");
1092	offDisplacement = (int16_t)pParam->uValue;
1093	Assert(*pszFmt == 'v'); pszFmt++;
1094
1095	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1096	PUT_NUM_S16(offDisplacement);
1097	}
1098	else
1099	{
1100	if (fPrefix)
1101	PUT_SZ("near ");
1102	offDisplacement = (int32_t)pParam->uValue;
1103	Assert(pParam->fUse & (DISUSE_IMMEDIATE32_REL \| DISUSE_IMMEDIATE64_REL));
1104	Assert(*pszFmt == 'v'); pszFmt++;
1105
1106	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1107	PUT_NUM_S32(offDisplacement);
1108	}
1109	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1110	PUT_SZ(" (");
1111
1112	RTUINTPTR uTrgAddr = pDis->uInstrAddr + pDis->cbInstr + offDisplacement;
1113	if (pDis->uCpuMode == DISCPUMODE_16BIT)
1114	PUT_NUM_16(uTrgAddr);
1115	else if (pDis->uCpuMode == DISCPUMODE_32BIT)
1116	PUT_NUM_32(uTrgAddr);
1117	else
1118	PUT_NUM_64(uTrgAddr);
1119
1120	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1121	{
1122	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " = ", ' ');
1123	PUT_C(')');
1124	}
1125	else
1126	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " (", ')');
1127	break;
1128	}
1129
1130	case 'A': /* Direct (jump/call) address (ParseImmAddr). */
1131	{
1132	Assert(*pszFmt == 'p'); pszFmt++;
1133	PUT_FAR();
1134	PUT_SIZE_OVERRIDE();
1135	PUT_SEGMENT_OVERRIDE();
1136	off = 0;
1137	int rc = VERR_SYMBOL_NOT_FOUND;
1138	switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 \| DISUSE_IMMEDIATE_ADDR_16_32 \| DISUSE_DISPLACEMENT64 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT16))
1139	{
1140	case DISUSE_IMMEDIATE_ADDR_16_16:
1141	PUT_NUM_16(pParam->uValue >> 16);
1142	PUT_C(':');
1143	PUT_NUM_16(pParam->uValue);
1144	if (pfnGetSymbol)
1145	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1146	break;
1147	case DISUSE_IMMEDIATE_ADDR_16_32:
1148	PUT_NUM_16(pParam->uValue >> 32);
1149	PUT_C(':');
1150	PUT_NUM_32(pParam->uValue);
1151	if (pfnGetSymbol)
1152	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1153	break;
1154	case DISUSE_DISPLACEMENT16:
1155	PUT_NUM_16(pParam->uValue);
1156	if (pfnGetSymbol)
1157	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1158	break;
1159	case DISUSE_DISPLACEMENT32:
1160	PUT_NUM_32(pParam->uValue);
1161	if (pfnGetSymbol)
1162	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1163	break;
1164	case DISUSE_DISPLACEMENT64:
1165	PUT_NUM_64(pParam->uValue);
1166	if (pfnGetSymbol)
1167	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint64_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1168	break;
1169	default:
1170	AssertFailed();
1171	break;
1172	}
1173
1174	PUT_SYMBOL_TWO(rc, " [", ']');
1175	break;
1176	}
1177
1178	case 'O': /* No ModRM byte (ParseImmAddr). */
1179	{
1180	Assert(pszFmt == 'b' \|\| pszFmt == 'v'); pszFmt++;
1181	PUT_FAR();
1182	PUT_SIZE_OVERRIDE();
1183	PUT_C('[');
1184	PUT_SEGMENT_OVERRIDE();
1185	off = 0;
1186	int rc = VERR_SYMBOL_NOT_FOUND;
1187	switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 \| DISUSE_IMMEDIATE_ADDR_16_32 \| DISUSE_DISPLACEMENT64 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT16))
1188	{
1189	case DISUSE_IMMEDIATE_ADDR_16_16:
1190	PUT_NUM_16(pParam->uValue >> 16);
1191	PUT_C(':');
1192	PUT_NUM_16(pParam->uValue);
1193	if (pfnGetSymbol)
1194	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1195	break;
1196	case DISUSE_IMMEDIATE_ADDR_16_32:
1197	PUT_NUM_16(pParam->uValue >> 32);
1198	PUT_C(':');
1199	PUT_NUM_32(pParam->uValue);
1200	if (pfnGetSymbol)
1201	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1202	break;
1203	case DISUSE_DISPLACEMENT16:
1204	PUT_NUM_16(pParam->uDisp.i16);
1205	if (pfnGetSymbol)
1206	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u16, szSymbol, sizeof(szSymbol), &off, pvUser);
1207	break;
1208	case DISUSE_DISPLACEMENT32:
1209	PUT_NUM_32(pParam->uDisp.i32);
1210	if (pfnGetSymbol)
1211	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u32, szSymbol, sizeof(szSymbol), &off, pvUser);
1212	break;
1213	case DISUSE_DISPLACEMENT64:
1214	PUT_NUM_64(pParam->uDisp.i64);
1215	if (pfnGetSymbol)
1216	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u64, szSymbol, sizeof(szSymbol), &off, pvUser);
1217	break;
1218	default:
1219	AssertFailed();
1220	break;
1221	}
1222	PUT_C(']');
1223
1224	PUT_SYMBOL_TWO(rc, " (", ')');
1225	break;
1226	}
1227
1228	case 'X': /* DS:SI (ParseXb, ParseXv). */
1229	case 'Y': /* ES:DI (ParseYb, ParseYv). */
1230	{
1231	Assert(pszFmt == 'b' \|\| pszFmt == 'v'); pszFmt++;
1232	PUT_FAR();
1233	PUT_SIZE_OVERRIDE();
1234	PUT_C('[');
1235	if (pParam->fUse & DISUSE_POINTER_DS_BASED)
1236	PUT_SZ("ds:");
1237	else
1238	PUT_SZ("es:");
1239
1240	size_t cchReg;
1241	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
1242	PUT_STR(pszReg, cchReg);
1243	PUT_C(']');
1244	break;
1245	}
1246
1247	case 'e': /* Register based on operand size (e.g. %eAX, %eAH) (ParseFixedReg). */
1248	{
1249	Assert(RT_C_IS_ALPHA(pszFmt[0]) && RT_C_IS_ALPHA(pszFmt[1]) && !RT_C_IS_ALPHA(pszFmt[2]));
1250	pszFmt += 2;
1251	size_t cchReg;
1252	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
1253	PUT_STR(pszReg, cchReg);
1254	break;
1255	}
1256
1257	default:
1258	AssertMsgFailed(("%c%s!\n", ch, pszFmt));
1259	break;
1260	}
1261	AssertMsg(pszFmt == ',' \|\| pszFmt == '\0', ("%c%s\n", ch, pszFmt));
1262	}
1263	else
1264	{
1265	PUT_C(ch);
1266	if (ch == ',')
1267	{
1268	Assert(*pszFmt != ' ');
1269	PUT_C(' ');
1270	switch (++iParam)
1271	{
1272	case 2: pParam = &pDis->Param2; break;
1273	case 3: pParam = &pDis->Param3; break;
1274	case 4: pParam = &pDis->Param4; break;
1275	default: pParam = NULL; break;
1276	}
1277	}
1278	}
1279	} /* while more to format */
1280	}
1281
1282	/*
1283	* Any additional output to the right of the instruction?
1284	*/
1285	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
1286	{
1287	/* some up front padding. */
1288	size_t cchPadding = cchOutput - offInstruction;
1289	cchPadding = cchPadding + 1 >= 42 ? 1 : 42 - cchPadding;
1290	PUT_STR(g_szSpaces, cchPadding);
1291
1292	/* comment? */
1293	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
1294	PUT_SZ(";");
1295
1296	/*
1297	* The address?
1298	*/
1299	if (fFlags & DIS_FMT_FLAGS_ADDR_RIGHT)
1300	{
1301	PUT_C(' ');
1302	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
1303	if (pDis->uInstrAddr >= _4G)
1304	PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
1305	#endif
1306	PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
1307	}
1308
1309	/*
1310	* Opcode bytes?
1311	*/
1312	if (fFlags & DIS_FMT_FLAGS_BYTES_RIGHT)
1313	{
1314	PUT_C(' ');
1315	size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
1316	cchOutput += cchTmp;
1317	if (cchTmp >= cchDst)
1318	cchTmp = cchDst - (cchDst != 0);
1319	cchDst -= cchTmp;
1320	pszDst += cchTmp;
1321	}
1322	}
1323
1324	/*
1325	* Terminate it - on overflow we'll have reserved one byte for this.
1326	*/
1327	if (cchDst > 0)
1328	*pszDst = '\0';
1329	else
1330	Assert(!cchBuf);
1331
1332	/* clean up macros */
1333	#undef PUT_PSZ
1334	#undef PUT_SZ
1335	#undef PUT_STR
1336	#undef PUT_C
1337	return cchOutput;
1338	}
1339
1340
1341	/**
1342	* Formats the current instruction in Yasm (/ Nasm) style.
1343	*
1344	* This is a simplified version of DISFormatYasmEx() provided for your convenience.
1345	*
1346	*
1347	* @returns The number of output characters. If this is >= cchBuf, then the content
1348	* of pszBuf will be truncated.
1349	* @param pDis Pointer to the disassembler state.
1350	* @param pszBuf The output buffer.
1351	* @param cchBuf The size of the output buffer.
1352	*/
1353	DISDECL(size_t) DISFormatYasm(PCDISSTATE pDis, char *pszBuf, size_t cchBuf)
1354	{
1355	return DISFormatYasmEx(pDis, pszBuf, cchBuf, 0 /* fFlags /, NULL / pfnGetSymbol /, NULL / pvUser */);
1356	}
1357
1358
1359	/**
1360	* Checks if the encoding of the given disassembled instruction is something we
1361	* can never get YASM to produce.
1362	*
1363	* @returns true if it's odd, false if it isn't.
1364	* @param pDis The disassembler output. The byte fetcher callback will
1365	* be used if present as we might need to fetch opcode
1366	* bytes.
1367	*/
1368	DISDECL(bool) DISFormatYasmIsOddEncoding(PDISSTATE pDis)
1369	{
1370	/*
1371	* Mod rm + SIB: Check for duplicate EBP encodings that yasm won't use for very good reasons.
1372	*/
1373	if ( pDis->uAddrMode != DISCPUMODE_16BIT ///@todo correct?
1374	&& pDis->ModRM.Bits.Rm == 4
1375	&& pDis->ModRM.Bits.Mod != 3)
1376	{
1377	/* No scaled index SIB (index=4), except for ESP. */
1378	if ( pDis->SIB.Bits.Index == 4
1379	&& pDis->SIB.Bits.Base != 4)
1380	return true;
1381
1382	/* EBP + displacement */
1383	if ( pDis->ModRM.Bits.Mod != 0
1384	&& pDis->SIB.Bits.Base == 5
1385	&& pDis->SIB.Bits.Scale == 0)
1386	return true;
1387	}
1388
1389	/*
1390	* Seems to be an instruction alias here, but I cannot find any docs on it... hrmpf!
1391	*/
1392	if ( pDis->pCurInstr->uOpcode == OP_SHL
1393	&& pDis->ModRM.Bits.Reg == 6)
1394	return true;
1395
1396	/*
1397	* Check for multiple prefixes of the same kind.
1398	*/
1399	uint8_t off1stSeg = UINT8_MAX;
1400	uint8_t offOpSize = UINT8_MAX;
1401	uint8_t offAddrSize = UINT8_MAX;
1402	uint32_t fPrefixes = 0;
1403	for (uint32_t offOpcode = 0; offOpcode < RT_ELEMENTS(pDis->abInstr); offOpcode++)
1404	{
1405	uint32_t f;
1406	switch (pDis->abInstr[offOpcode])
1407	{
1408	case 0xf0:
1409	f = DISPREFIX_LOCK;
1410	break;
1411
1412	case 0xf2:
1413	case 0xf3:
1414	f = DISPREFIX_REP; /* yes, both */
1415	break;
1416
1417	case 0x2e:
1418	case 0x3e:
1419	case 0x26:
1420	case 0x36:
1421	case 0x64:
1422	case 0x65:
1423	if (off1stSeg == UINT8_MAX)
1424	off1stSeg = offOpcode;
1425	f = DISPREFIX_SEG;
1426	break;
1427
1428	case 0x66:
1429	if (offOpSize == UINT8_MAX)
1430	offOpSize = offOpcode;
1431	f = DISPREFIX_OPSIZE;
1432	break;
1433
1434	case 0x67:
1435	if (offAddrSize == UINT8_MAX)
1436	offAddrSize = offOpcode;
1437	f = DISPREFIX_ADDRSIZE;
1438	break;
1439
1440	case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
1441	case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
1442	f = pDis->uCpuMode == DISCPUMODE_64BIT ? DISPREFIX_REX : 0;
1443	break;
1444
1445	default:
1446	f = 0;
1447	break;
1448	}
1449	if (!f)
1450	break; /* done */
1451	if (fPrefixes & f)
1452	return true;
1453	fPrefixes \|= f;
1454	}
1455
1456	/* segment overrides are fun */
1457	if (fPrefixes & DISPREFIX_SEG)
1458	{
1459	/* no effective address which it may apply to. */
1460	Assert((pDis->fPrefix & DISPREFIX_SEG) \|\| pDis->uCpuMode == DISCPUMODE_64BIT);
1461	if ( !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
1462	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
1463	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse))
1464	return true;
1465
1466	/* Yasm puts the segment prefixes before the operand prefix with no
1467	way of overriding it. */
1468	if (offOpSize < off1stSeg)
1469	return true;
1470	}
1471
1472	/* fixed register + addr override doesn't go down all that well. */
1473	if (fPrefixes & DISPREFIX_ADDRSIZE)
1474	{
1475	Assert(pDis->fPrefix & DISPREFIX_ADDRSIZE);
1476	if ( pDis->pCurInstr->fParam3 == OP_PARM_NONE
1477	&& pDis->pCurInstr->fParam2 == OP_PARM_NONE
1478	&& ( pDis->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
1479	&& pDis->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END))
1480	return true;
1481	}
1482
1483	/* Almost all prefixes are bad for jumps. */
1484	if (fPrefixes)
1485	{
1486	switch (pDis->pCurInstr->uOpcode)
1487	{
1488	/* nop w/ prefix(es). */
1489	case OP_NOP:
1490	return true;
1491
1492	case OP_JMP:
1493	if ( pDis->pCurInstr->fParam1 != OP_PARM_Jb
1494	&& pDis->pCurInstr->fParam1 != OP_PARM_Jv)
1495	break;
1496	/* fall thru */
1497	case OP_JO:
1498	case OP_JNO:
1499	case OP_JC:
1500	case OP_JNC:
1501	case OP_JE:
1502	case OP_JNE:
1503	case OP_JBE:
1504	case OP_JNBE:
1505	case OP_JS:
1506	case OP_JNS:
1507	case OP_JP:
1508	case OP_JNP:
1509	case OP_JL:
1510	case OP_JNL:
1511	case OP_JLE:
1512	case OP_JNLE:
1513	/** @todo branch hinting 0x2e/0x3e... */
1514	return true;
1515	}
1516
1517	}
1518
1519	/* All but the segment prefix is bad news for push/pop. */
1520	if (fPrefixes & ~DISPREFIX_SEG)
1521	{
1522	switch (pDis->pCurInstr->uOpcode)
1523	{
1524	case OP_POP:
1525	case OP_PUSH:
1526	if ( pDis->pCurInstr->fParam1 >= OP_PARM_REG_SEG_START
1527	&& pDis->pCurInstr->fParam1 <= OP_PARM_REG_SEG_END)
1528	return true;
1529	if ( (fPrefixes & ~DISPREFIX_OPSIZE)
1530	&& pDis->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
1531	&& pDis->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END)
1532	return true;
1533	break;
1534
1535	case OP_POPA:
1536	case OP_POPF:
1537	case OP_PUSHA:
1538	case OP_PUSHF:
1539	if (fPrefixes & ~DISPREFIX_OPSIZE)
1540	return true;
1541	break;
1542	}
1543	}
1544
1545	/* Implicit 8-bit register instructions doesn't mix with operand size. */
1546	if ( (fPrefixes & DISPREFIX_OPSIZE)
1547	&& ( ( pDis->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
1548	&& pDis->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
1549	\|\| ( pDis->pCurInstr->fParam2 == OP_PARM_Gb /* r8 */
1550	&& pDis->pCurInstr->fParam1 == OP_PARM_Eb /* r8/mem8 */))
1551	)
1552	{
1553	switch (pDis->pCurInstr->uOpcode)
1554	{
1555	case OP_ADD:
1556	case OP_OR:
1557	case OP_ADC:
1558	case OP_SBB:
1559	case OP_AND:
1560	case OP_SUB:
1561	case OP_XOR:
1562	case OP_CMP:
1563	return true;
1564	default:
1565	break;
1566	}
1567	}
1568
1569	/* Instructions taking no address or operand which thus may be annoyingly
1570	difficult to format for yasm. */
1571	if (fPrefixes)
1572	{
1573	switch (pDis->pCurInstr->uOpcode)
1574	{
1575	case OP_STI:
1576	case OP_STC:
1577	case OP_CLI:
1578	case OP_CLD:
1579	case OP_CLC:
1580	case OP_INT:
1581	case OP_INT3:
1582	case OP_INTO:
1583	case OP_HLT:
1584	/** @todo Many more to can be added here. */
1585	return true;
1586	default:
1587	break;
1588	}
1589	}
1590
1591	/* FPU and other instructions that ignores operand size override. */
1592	if (fPrefixes & DISPREFIX_OPSIZE)
1593	{
1594	switch (pDis->pCurInstr->uOpcode)
1595	{
1596	/* FPU: */
1597	case OP_FIADD:
1598	case OP_FIMUL:
1599	case OP_FISUB:
1600	case OP_FISUBR:
1601	case OP_FIDIV:
1602	case OP_FIDIVR:
1603	/** @todo there are many more. */
1604	return true;
1605
1606	case OP_MOV:
1607	/** @todo could be that we're not disassembling these correctly. */
1608	if (pDis->pCurInstr->fParam1 == OP_PARM_Sw)
1609	return true;
1610	/** @todo what about the other way? */
1611	break;
1612
1613	default:
1614	break;
1615	}
1616	}
1617
1618
1619	/*
1620	* Check for the version of xyz reg,reg instruction that the assembler doesn't use.
1621	*
1622	* For example:
1623	* expected: 1aee sbb ch, dh ; SBB r8, r/m8
1624	* yasm: 18F5 sbb ch, dh ; SBB r/m8, r8
1625	*/
1626	if (pDis->ModRM.Bits.Mod == 3 /* reg,reg */)
1627	{
1628	switch (pDis->pCurInstr->uOpcode)
1629	{
1630	case OP_ADD:
1631	case OP_OR:
1632	case OP_ADC:
1633	case OP_SBB:
1634	case OP_AND:
1635	case OP_SUB:
1636	case OP_XOR:
1637	case OP_CMP:
1638	if ( ( pDis->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
1639	&& pDis->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
1640	\|\| ( pDis->pCurInstr->fParam1 == OP_PARM_Gv /* rX */
1641	&& pDis->pCurInstr->fParam2 == OP_PARM_Ev /* rX/memX */))
1642	return true;
1643
1644	/* 82 (see table A-6). */
1645	if (pDis->bOpCode == 0x82)
1646	return true;
1647	break;
1648
1649	/* ff /0, fe /0, ff /1, fe /0 */
1650	case OP_DEC:
1651	case OP_INC:
1652	return true;
1653
1654	case OP_POP:
1655	case OP_PUSH:
1656	Assert(pDis->bOpCode == 0x8f);
1657	return true;
1658
1659	case OP_MOV:
1660	if ( pDis->bOpCode == 0x8a
1661	\|\| pDis->bOpCode == 0x8b)
1662	return true;
1663	break;
1664
1665	default:
1666	break;
1667	}
1668	}
1669
1670	/* shl eax,1 will be assembled to the form without the immediate byte. */
1671	if ( pDis->pCurInstr->fParam2 == OP_PARM_Ib
1672	&& (uint8_t)pDis->Param2.uValue == 1)
1673	{
1674	switch (pDis->pCurInstr->uOpcode)
1675	{
1676	case OP_SHL:
1677	case OP_SHR:
1678	case OP_SAR:
1679	case OP_RCL:
1680	case OP_RCR:
1681	case OP_ROL:
1682	case OP_ROR:
1683	return true;
1684	}
1685	}
1686
1687	/* And some more - see table A-6. */
1688	if (pDis->bOpCode == 0x82)
1689	{
1690	switch (pDis->pCurInstr->uOpcode)
1691	{
1692	case OP_ADD:
1693	case OP_OR:
1694	case OP_ADC:
1695	case OP_SBB:
1696	case OP_AND:
1697	case OP_SUB:
1698	case OP_XOR:
1699	case OP_CMP:
1700	return true;
1701	break;
1702	}
1703	}
1704
1705
1706	/* check for REX.X = 1 without SIB. */
1707
1708	/* Yasm encodes setnbe al with /2 instead of /0 like the AMD manual
1709	says (intel doesn't appear to care). */
1710	switch (pDis->pCurInstr->uOpcode)
1711	{
1712	case OP_SETO:
1713	case OP_SETNO:
1714	case OP_SETC:
1715	case OP_SETNC:
1716	case OP_SETE:
1717	case OP_SETNE:
1718	case OP_SETBE:
1719	case OP_SETNBE:
1720	case OP_SETS:
1721	case OP_SETNS:
1722	case OP_SETP:
1723	case OP_SETNP:
1724	case OP_SETL:
1725	case OP_SETNL:
1726	case OP_SETLE:
1727	case OP_SETNLE:
1728	AssertMsg(pDis->bOpCode >= 0x90 && pDis->bOpCode <= 0x9f, ("%#x\n", pDis->bOpCode));
1729	if (pDis->ModRM.Bits.Reg != 2)
1730	return true;
1731	break;
1732	}
1733
1734	/*
1735	* The MOVZX reg32,mem16 instruction without an operand size prefix
1736	* doesn't quite make sense...
1737	*/
1738	if ( pDis->pCurInstr->uOpcode == OP_MOVZX
1739	&& pDis->bOpCode == 0xB7
1740	&& (pDis->uCpuMode == DISCPUMODE_16BIT) != !!(fPrefixes & DISPREFIX_OPSIZE))
1741	return true;
1742
1743	return false;
1744	}
1745

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source: vbox/trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp@ 63457

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