DisasmFormatYasm.cpp@ 9271

Last change on this file since 9271 was 9271, checked in by vboxsync, 17 years ago
Implemented symbol lookup, strict / relaxed assembly, and relative (+/-off) branch formatting.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 48.8 KB

Line
1	/* $Id: DisasmFormatYasm.cpp 9271 2008-05-31 18:11:10Z vboxsync $ */
2	/** @file
3	* VBox Disassembler - Yasm(/Nasm) Style Formatter.
4	*/
5
6	/*
7	* Copyright (C) 2008 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#include <VBox/dis.h>
27	#include "DisasmInternal.h"
28	#include <iprt/string.h>
29	#include <iprt/assert.h>
30	#include <iprt/ctype.h>
31
32
33	/*******************************************************************************
34	* Global Variables *
35	*******************************************************************************/
36	static const char g_szSpaces[] =
37	" ";
38	static const char g_aszYasmRegGen8x86[8][4] =
39	{
40	"al\0", "cl\0", "dl\0", "bl\0", "ah\0", "ch\0", "dh\0", "bh\0"
41	};
42	static const char g_aszYasmRegGen8Amd64[16][5] =
43	{
44	"al\0\0", "cl\0\0", "dl\0\0", "bl\0\0", "spb\0", "bpb\0", "sib\0", "dib\0", "r8b\0", "r9b\0", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
45	};
46	static const char g_aszYasmRegGen16[16][5] =
47	{
48	"ax\0\0", "cx\0\0", "dx\0\0", "bx\0\0", "sp\0\0", "bp\0\0", "si\0\0", "di\0\0", "r8w\0", "r9w\0", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
49	};
50	static const char g_aszYasmRegGen1616[8][6] =
51	{
52	"bx+si", "bx+di", "bp+si", "bp+di", "si\0\0\0", "di\0\0\0", "bp\0\0\0", "bx\0\0\0"
53	};
54	static const char g_aszYasmRegGen32[16][5] =
55	{
56	"eax\0", "ecx\0", "edx\0", "ebx\0", "esp\0", "ebp\0", "esi\0", "edi\0", "r8d\0", "r9d\0", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
57	};
58	static const char g_aszYasmRegGen64[16][4] =
59	{
60	"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", "r8\0", "r9\0", "r10", "r11", "r12", "r13", "r14", "r15"
61	};
62	static const char g_aszYasmRegSeg[6][3] =
63	{
64	"es", "cs", "ss", "ds", "fs", "gs"
65	};
66	static const char g_aszYasmRegFP[8][4] =
67	{
68	"st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7"
69	};
70	static const char g_aszYasmRegMMX[8][4] =
71	{
72	"mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7"
73	};
74	static const char g_aszYasmRegXMM[16][6] =
75	{
76	"xmm0\0", "xmm1\0", "xmm2\0", "xmm3\0", "xmm4\0", "xmm5\0", "xmm6\0", "xmm7\0", "xmm8\0", "xmm9\0", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
77	};
78	static const char g_aszYasmRegCRx[16][5] =
79	{
80	"cr0\0", "cr1\0", "cr2\0", "cr3\0", "cr4\0", "cr5\0", "cr6\0", "cr7\0", "cr8\0", "cr9\0", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15"
81	};
82	static const char g_aszYasmRegDRx[16][5] =
83	{
84	"dr0\0", "dr1\0", "dr2\0", "dr3\0", "dr4\0", "dr5\0", "dr6\0", "dr7\0", "dr8\0", "dr9\0", "dr10", "dr11", "dr12", "dr13", "dr14", "dr15"
85	};
86	static const char g_aszYasmRegTRx[16][5] =
87	{
88	"tr0\0", "tr1\0", "tr2\0", "tr3\0", "tr4\0", "tr5\0", "tr6\0", "tr7\0", "tr8\0", "tr9\0", "tr10", "tr11", "tr12", "tr13", "tr14", "tr15"
89	};
90
91
92
93	/**
94	* Gets the base register name for the given parameter.
95	*
96	* @returns Pointer to the register name.
97	* @param pCpu The disassembler cpu state.
98	* @param pParam The parameter.
99	* @param pcchReg Where to store the length of the name.
100	*/
101	static const char disasmFormatYasmBaseReg(PCDISCPUSTATE pCpu, PCOP_PARAMETER pParam, size_t pcchReg)
102	{
103	switch (pParam->flags & ( USE_REG_GEN8 \| USE_REG_GEN16 \| USE_REG_GEN32 \| USE_REG_GEN64
104	\| USE_REG_FP \| USE_REG_MMX \| USE_REG_XMM \| USE_REG_CR
105	\| USE_REG_DBG \| USE_REG_SEG \| USE_REG_TEST))
106
107	{
108	case USE_REG_GEN8:
109	if (pCpu->opmode == CPUMODE_64BIT)
110	{
111	Assert(pParam->base.reg_gen < RT_ELEMENTS(g_aszYasmRegGen8Amd64));
112	const char *psz = g_aszYasmRegGen8Amd64[pParam->base.reg_gen];
113	*pcchReg = 2 + !!psz[2] + !!psz[3];
114	return psz;
115	}
116	*pcchReg = 2;
117	Assert(pParam->base.reg_gen < RT_ELEMENTS(g_aszYasmRegGen8x86));
118	return g_aszYasmRegGen8x86[pParam->base.reg_gen];
119
120	case USE_REG_GEN16:
121	{
122	Assert(pParam->base.reg_gen < RT_ELEMENTS(g_aszYasmRegGen16));
123	const char *psz = g_aszYasmRegGen16[pParam->base.reg_gen];
124	*pcchReg = 2 + !!psz[2] + !!psz[3];
125	return psz;
126	}
127
128	case USE_REG_GEN32:
129	{
130	Assert(pParam->base.reg_gen < RT_ELEMENTS(g_aszYasmRegGen32));
131	const char *psz = g_aszYasmRegGen32[pParam->base.reg_gen];
132	*pcchReg = 2 + !!psz[2] + !!psz[3];
133	return psz;
134	}
135
136	case USE_REG_GEN64:
137	{
138	Assert(pParam->base.reg_gen < RT_ELEMENTS(g_aszYasmRegGen64));
139	const char *psz = g_aszYasmRegGen64[pParam->base.reg_gen];
140	*pcchReg = 2 + !!psz[2] + !!psz[3];
141	return psz;
142	}
143
144	case USE_REG_FP:
145	{
146	Assert(pParam->base.reg_fp < RT_ELEMENTS(g_aszYasmRegFP));
147	const char *psz = g_aszYasmRegFP[pParam->base.reg_fp];
148	*pcchReg = 3;
149	return psz;
150	}
151
152	case USE_REG_MMX:
153	{
154	Assert(pParam->base.reg_mmx < RT_ELEMENTS(g_aszYasmRegMMX));
155	const char *psz = g_aszYasmRegMMX[pParam->base.reg_mmx];
156	*pcchReg = 3;
157	return psz;
158	}
159
160	case USE_REG_XMM:
161	{
162	Assert(pParam->base.reg_xmm < RT_ELEMENTS(g_aszYasmRegXMM));
163	const char *psz = g_aszYasmRegXMM[pParam->base.reg_mmx];
164	*pcchReg = 4 + !!psz[4];
165	return psz;
166	}
167
168	case USE_REG_CR:
169	{
170	Assert(pParam->base.reg_ctrl < RT_ELEMENTS(g_aszYasmRegCRx));
171	const char *psz = g_aszYasmRegCRx[pParam->base.reg_ctrl];
172	*pcchReg = 3;
173	return psz;
174	}
175
176	case USE_REG_DBG:
177	{
178	Assert(pParam->base.reg_dbg < RT_ELEMENTS(g_aszYasmRegDRx));
179	const char *psz = g_aszYasmRegDRx[pParam->base.reg_dbg];
180	*pcchReg = 3;
181	return psz;
182	}
183
184	case USE_REG_SEG:
185	{
186	Assert(pParam->base.reg_seg < RT_ELEMENTS(g_aszYasmRegCRx));
187	const char *psz = g_aszYasmRegSeg[pParam->base.reg_seg];
188	*pcchReg = 2;
189	return psz;
190	}
191
192	case USE_REG_TEST:
193	{
194	Assert(pParam->base.reg_test < RT_ELEMENTS(g_aszYasmRegTRx));
195	const char *psz = g_aszYasmRegTRx[pParam->base.reg_test];
196	*pcchReg = 3;
197	return psz;
198	}
199
200	default:
201	AssertMsgFailed(("%#x\n", pParam->flags));
202	*pcchReg = 3;
203	return "r??";
204	}
205	}
206
207
208	/**
209	* Gets the index register name for the given parameter.
210	*
211	* @returns The index register name.
212	* @param pCpu The disassembler cpu state.
213	* @param pParam The parameter.
214	* @param pcchReg Where to store the length of the name.
215	*/
216	static const char disasmFormatYasmIndexReg(PCDISCPUSTATE pCpu, PCOP_PARAMETER pParam, size_t pcchReg)
217	{
218	switch (pCpu->addrmode)
219	{
220	case CPUMODE_16BIT:
221	{
222	Assert(pParam->index.reg_gen < RT_ELEMENTS(g_aszYasmRegGen16));
223	const char *psz = g_aszYasmRegGen16[pParam->index.reg_gen];
224	*pcchReg = 2 + !!psz[2] + !!psz[3];
225	return psz;
226	}
227
228	case CPUMODE_32BIT:
229	{
230	Assert(pParam->index.reg_gen < RT_ELEMENTS(g_aszYasmRegGen32));
231	const char *psz = g_aszYasmRegGen32[pParam->index.reg_gen];
232	*pcchReg = 2 + !!psz[2] + !!psz[3];
233	return psz;
234	}
235
236	case CPUMODE_64BIT:
237	{
238	Assert(pParam->index.reg_gen < RT_ELEMENTS(g_aszYasmRegGen64));
239	const char *psz = g_aszYasmRegGen64[pParam->index.reg_gen];
240	*pcchReg = 2 + !!psz[2] + !!psz[3];
241	return psz;
242	}
243
244	default:
245	AssertMsgFailed(("%#x %#x\n", pParam->flags, pCpu->addrmode));
246	*pcchReg = 3;
247	return "r??";
248	}
249	}
250
251
252	/**
253	* Formats the current instruction in Yasm (/ Nasm) style.
254	*
255	*
256	* @returns The number of output characters. If this is >= cchBuf, then the content
257	* of pszBuf will be truncated.
258	* @param pCpu Pointer to the disassembler CPU state.
259	* @param pszBuf The output buffer.
260	* @param cchBuf The size of the output buffer.
261	* @param fFlags Format flags, see DIS_FORMAT_FLAGS_*.
262	* @param pfnGetSymbol Get symbol name for a jmp or call target address. Optional.
263	* @param pvUser User argument for pfnGetSymbol.
264	*/
265	DISDECL(size_t) DISFormatYasmEx(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags,
266	PFNDISGETSYMBOL pfnGetSymbol, void *pvUser)
267	{
268	/*
269	* Input validation and massaging.
270	*/
271	AssertPtr(pCpu);
272	AssertPtrNull(pszBuf);
273	Assert(pszBuf \|\| !cchBuf);
274	AssertPtrNull(pfnGetSymbol);
275	AssertMsg(DIS_FMT_FLAGS_IS_VALID(fFlags), ("%#x\n", fFlags));
276	if (fFlags & DIS_FMT_FLAGS_ADDR_COMMENT)
277	fFlags = (fFlags & ~DIS_FMT_FLAGS_ADDR_LEFT) \| DIS_FMT_FLAGS_ADDR_RIGHT;
278	if (fFlags & DIS_FMT_FLAGS_BYTES_COMMENT)
279	fFlags = (fFlags & ~DIS_FMT_FLAGS_BYTES_LEFT) \| DIS_FMT_FLAGS_BYTES_RIGHT;
280
281	PCOPCODE const pOp = pCpu->pCurInstr;
282
283	/*
284	* Output macros
285	*/
286	char *pszDst = pszBuf;
287	size_t cchDst = cchBuf;
288	size_t cchOutput = 0;
289	#define PUT_C(ch) \
290	do { \
291	cchOutput++; \
292	if (cchDst > 1) \
293	{ \
294	cchDst--; \
295	*pszDst++ = (ch); \
296	} \
297	} while (0)
298	#define PUT_STR(pszSrc, cchSrc) \
299	do { \
300	cchOutput += (cchSrc); \
301	if (cchDst > (cchSrc)) \
302	{ \
303	memcpy(pszDst, (pszSrc), (cchSrc)); \
304	pszDst += (cchSrc); \
305	cchDst -= (cchSrc); \
306	} \
307	else if (cchDst > 1) \
308	{ \
309	memcpy(pszDst, (pszSrc), cchDst - 1); \
310	pszDst += cchDst - 1; \
311	cchDst = 1; \
312	} \
313	} while (0)
314	#define PUT_SZ(sz) \
315	PUT_STR((sz), sizeof(sz) - 1)
316	#define PUT_SZ_STRICT(szStrict, szRelaxed) \
317	do { if (fFlags & DIS_FMT_FLAGS_STRICT) PUT_SZ(szStrict); else PUT_SZ(szRelaxed); } while (0)
318	#define PUT_PSZ(psz) \
319	do { const size_t cchTmp = strlen(psz); PUT_STR((psz), cchTmp); } while (0)
320	#define PUT_NUM(cch, fmt, num) \
321	do { \
322	cchOutput += (cch); \
323	if (cchDst > 1) \
324	{ \
325	const size_t cchTmp = RTStrPrintf(pszDst, cchDst, fmt, (num)); \
326	pszDst += cchTmp; \
327	cchDst -= cchTmp; \
328	Assert(cchTmp == (cch) \|\| cchDst == 1); \
329	} \
330	} while (0)
331	#define PUT_NUM_8(num) PUT_NUM(4, "0%02xh", (uint8_t)(num))
332	#define PUT_NUM_16(num) PUT_NUM(6, "0%04xh", (uint16_t)(num))
333	#define PUT_NUM_32(num) PUT_NUM(10, "0%08xh", (uint32_t)(num))
334	#define PUT_NUM_64(num) PUT_NUM(18, "0%08xh", (uint64_t)(num))
335
336	#define PUT_NUM_SIGN(cch, fmt, num, stype, utype) \
337	do { \
338	if ((stype)(num) >= 0) \
339	{ \
340	PUT_C('+'); \
341	PUT_NUM(cch, fmt, (utype)(num)); \
342	} \
343	else \
344	{ \
345	PUT_C('-'); \
346	PUT_NUM(cch, fmt, (utype)-(stype)(num)); \
347	} \
348	} while (0)
349	#define PUT_NUM_S8(num) PUT_NUM_SIGN(4, "0%02xh", num, int8_t, uint8_t)
350	#define PUT_NUM_S16(num) PUT_NUM_SIGN(6, "0%04xh", num, int16_t, uint16_t)
351	#define PUT_NUM_S32(num) PUT_NUM_SIGN(10, "0%08xh", num, int32_t, uint32_t)
352	#define PUT_NUM_S64(num) PUT_NUM_SIGN(18, "0%08xh", num, int64_t, uint64_t)
353
354
355	/*
356	* The address?
357	*/
358	if (fFlags & DIS_FMT_FLAGS_ADDR_LEFT)
359	{
360	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
361	if (pCpu->opaddr >= _4G)
362	PUT_NUM(9, "%08x`", (uint32_t)(pCpu->opaddr >> 32));
363	#endif
364	PUT_NUM(8, "%08x", (uint32_t)pCpu->opaddr);
365	PUT_C(' ');
366	}
367
368	/*
369	* The opcode bytes?
370	*/
371	if (fFlags & DIS_FMT_FLAGS_BYTES_LEFT)
372	{
373	size_t cchTmp = disFormatBytes(pCpu, pszDst, cchDst, fFlags);
374	cchOutput += cchTmp;
375	if (cchDst > 1)
376	{
377	if (cchTmp <= cchDst)
378	{
379	cchDst -= cchTmp;
380	pszDst += cchTmp;
381	}
382	else
383	{
384	pszDst += cchDst - 1;
385	cchDst = 1;
386	}
387	}
388
389	/* Some padding to align the instruction. */
390	size_t cchPadding = (7 * (2 + !!(fFlags & DIS_FMT_FLAGS_BYTES_SPACED)))
391	+ !!(fFlags & DIS_FMT_FLAGS_BYTES_BRACKETS) * 2
392	+ 2;
393	cchPadding = cchTmp + 1 >= cchPadding ? 1 : cchPadding - cchTmp;
394	PUT_STR(g_szSpaces, cchPadding);
395	}
396
397
398	/*
399	* Filter out invalid opcodes first as they need special
400	* treatment. UD2 is an exception and should be handled normally.
401	*/
402	size_t const offInstruction = cchOutput;
403	if ( pOp->opcode == OP_INVALID
404	\|\| ( pOp->opcode == OP_ILLUD2
405	&& (pCpu->prefix & PREFIX_LOCK)))
406	{
407
408	}
409	else
410	{
411	/*
412	* Prefixes
413	*/
414	if (pCpu->prefix & PREFIX_LOCK)
415	PUT_SZ("lock ");
416	if(pCpu->prefix & PREFIX_REP)
417	PUT_SZ("rep ");
418	else if(pCpu->prefix & PREFIX_REPNE)
419	PUT_SZ("repne ");
420
421	/*
422	* Adjust the format string to the correct mnemonic
423	* or to avoid things the assembler cannot handle correctly.
424	*/
425	char szTmpFmt[48];
426	const char *pszFmt = pOp->pszOpcode;
427	switch (pOp->opcode)
428	{
429	case OP_JECXZ:
430	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "jcxz %Jb" : pCpu->opmode == CPUMODE_32BIT ? "jecxz %Jb" : "jrcxz %Jb";
431	break;
432	case OP_PUSHF:
433	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "pushfw" : pCpu->opmode == CPUMODE_32BIT ? "pushfd" : "pushfq";
434	break;
435	case OP_POPF:
436	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "popfw" : pCpu->opmode == CPUMODE_32BIT ? "popfd" : "popfq";
437	break;
438	case OP_PUSHA:
439	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "pushaw" : "pushad";
440	break;
441	case OP_POPA:
442	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "popaw" : "popad";
443	break;
444	case OP_INSB:
445	pszFmt = "insb";
446	break;
447	case OP_INSWD:
448	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "insw" : pCpu->opmode == CPUMODE_32BIT ? "insd" : "insq";
449	break;
450	case OP_OUTSB:
451	pszFmt = "outsb";
452	break;
453	case OP_OUTSWD:
454	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "outsw" : pCpu->opmode == CPUMODE_32BIT ? "outsd" : "outsq";
455	break;
456	case OP_MOVSB:
457	pszFmt = "movsb";
458	break;
459	case OP_MOVSWD:
460	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "movsw" : pCpu->opmode == CPUMODE_32BIT ? "movsd" : "movsq";
461	break;
462	case OP_CMPSB:
463	pszFmt = "cmpsb";
464	break;
465	case OP_CMPWD:
466	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "cmpsw" : pCpu->opmode == CPUMODE_32BIT ? "cmpsd" : "cmpsq";
467	break;
468	case OP_SCASB:
469	pszFmt = "scasb";
470	break;
471	case OP_SCASWD:
472	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "scasw" : pCpu->opmode == CPUMODE_32BIT ? "scasd" : "scasq";
473	break;
474	case OP_LODSB:
475	pszFmt = "lodsb";
476	break;
477	case OP_LODSWD:
478	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "lodsw" : pCpu->opmode == CPUMODE_32BIT ? "lodsd" : "lodsq";
479	break;
480	case OP_STOSB:
481	pszFmt = "stosb";
482	break;
483	case OP_STOSWD:
484	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "stosw" : pCpu->opmode == CPUMODE_32BIT ? "stosd" : "stosq";
485	break;
486	case OP_CBW:
487	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "cbw" : pCpu->opmode == CPUMODE_32BIT ? "cwde" : "cdqe";
488	break;
489	case OP_CWD:
490	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "cwd" : pCpu->opmode == CPUMODE_32BIT ? "cdq" : "cqo";
491	break;
492	case OP_SHL:
493	Assert(pszFmt[3] == '/');
494	pszFmt += 4;
495	break;
496	case OP_XLAT:
497	pszFmt = "xlatb";
498	break;
499	case OP_INT3:
500	pszFmt = "int3";
501	break;
502
503	/*
504	* Don't know how to tell yasm to generate complicated nop stuff, so 'db' it.
505	*/
506	case OP_NOP:
507	if (pCpu->opcode == 0x90)
508	/* fine, fine */;
509	else if (pszFmt[sizeof("nop %Ev")] == '/' && pszFmt[sizeof("nop %Ev") + 1] == 'p')
510	pszFmt = "prefetch %Eb";
511	else if (pCpu->opcode == 0x1f)
512	{
513	Assert(pCpu->opsize >= 3);
514	PUT_SZ("db 00fh, 01fh,");
515	PUT_NUM_8(pCpu->ModRM.u);
516	for (unsigned i = 3; i < pCpu->opsize; i++)
517	{
518	PUT_C(',');
519	PUT_NUM_8(0x90); ///@todo fixme.
520	}
521	pszFmt = "";
522	}
523	break;
524
525	default:
526	/* ST(X) -> stX (floating point) */
527	if (*pszFmt == 'f' && strchr(pszFmt, '('))
528	{
529	char *pszFmtDst = szTmpFmt;
530	char ch;
531	do
532	{
533	ch = *pszFmt++;
534	if (ch == 'S' && pszFmt[0] == 'T' && pszFmt[1] == '(')
535	{
536	*pszFmtDst++ = 's';
537	*pszFmtDst++ = 't';
538	pszFmt += 2;
539	ch = *pszFmt;
540	Assert(pszFmt[1] == ')');
541	pszFmt += 2;
542	*pszFmtDst++ = ch;
543	}
544	else
545	*pszFmtDst++ = ch;
546	} while (ch != '\0');
547	pszFmt = szTmpFmt;
548	}
549	break;
550
551	/*
552	* Horrible hacks.
553	*/
554	case OP_FLD:
555	if (pCpu->opcode == 0xdb) /* m80fp workaround. */
556	(int )&pCpu->param1.param &= ~0x1f; /* make it pure OP_PARM_M */
557	break;
558	case OP_LAR: /* hack w -> v, probably not correct. */
559	(int )&pCpu->param2.param &= ~0x1f;
560	(int )&pCpu->param2.param \|= OP_PARM_v;
561	break;
562	}
563
564	/*
565	* Formatting context and associated macros.
566	*/
567	PCOP_PARAMETER pParam = &pCpu->param1;
568	int iParam = 1;
569
570	#define PUT_FAR() \
571	do { \
572	if ( OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_p \
573	&& pOp->opcode != OP_LDS /* table bugs? */ \
574	&& pOp->opcode != OP_LES \
575	&& pOp->opcode != OP_LFS \
576	&& pOp->opcode != OP_LGS \
577	&& pOp->opcode != OP_LSS ) \
578	PUT_SZ("far "); \
579	} while (0)
580	/** @todo mov ah,ch ends up with a byte 'override'... */
581	#define PUT_SIZE_OVERRIDE() \
582	do { \
583	switch (OP_PARM_VSUBTYPE(pParam->param)) \
584	{ \
585	case OP_PARM_v: \
586	switch (pCpu->opmode) \
587	{ \
588	case CPUMODE_16BIT: PUT_SZ("word "); break; \
589	case CPUMODE_32BIT: PUT_SZ("dword "); break; \
590	case CPUMODE_64BIT: PUT_SZ("qword "); break; \
591	default: break; \
592	} \
593	break; \
594	case OP_PARM_b: PUT_SZ("byte "); break; \
595	case OP_PARM_w: PUT_SZ("word "); break; \
596	case OP_PARM_d: PUT_SZ("dword "); break; \
597	case OP_PARM_q: PUT_SZ("qword "); break; \
598	case OP_PARM_dq: \
599	if (OP_PARM_VTYPE(pParam->param) != OP_PARM_W) /* these are 128 bit, pray they are all unambiguous.. */ \
600	PUT_SZ("qword "); \
601	break; \
602	case OP_PARM_p: break; /* see PUT_FAR */ \
603	case OP_PARM_s: if (pParam->flags & USE_REG_FP) PUT_SZ("tword "); break; /* ?? */ \
604	case OP_PARM_z: break; \
605	case OP_PARM_NONE: \
606	if ( OP_PARM_VTYPE(pParam->param) == OP_PARM_M \
607	&& ((pParam->flags & USE_REG_FP) \|\| pOp->opcode == OP_FLD)) \
608	PUT_SZ("tword "); \
609	break; \
610	default: break; /no pointer type specified/necessary/ \
611	} \
612	} while (0)
613	static const char s_szSegPrefix[6][4] = { "es:", "cs:", "ss:", "ds:", "fs:", "gs:" };
614	#define PUT_SEGMENT_OVERRIDE() \
615	do { \
616	if (pCpu->prefix & PREFIX_SEG) \
617	PUT_STR(s_szSegPrefix[pCpu->prefix_seg], 3); \
618	} while (0)
619
620
621	/*
622	* Segment prefixing for instructions that doesn't do memory access.
623	*/
624	if ( (pCpu->prefix & PREFIX_SEG)
625	&& !DIS_IS_EFFECTIVE_ADDR(pCpu->param1.flags)
626	&& !DIS_IS_EFFECTIVE_ADDR(pCpu->param2.flags)
627	&& !DIS_IS_EFFECTIVE_ADDR(pCpu->param3.flags))
628	{
629	PUT_STR(s_szSegPrefix[pCpu->prefix_seg], 2);
630	PUT_C(' ');
631	}
632
633
634	/*
635	* The formatting loop.
636	*/
637	RTINTPTR off;
638	char szSymbol[128];
639	char ch;
640	while ((ch = *pszFmt++) != '\0')
641	{
642	if (ch == '%')
643	{
644	ch = *pszFmt++;
645	switch (ch)
646	{
647	/*
648	* ModRM - Register only.
649	*/
650	case 'C': /* Control register (ParseModRM / UseModRM). */
651	case 'D': /* Debug register (ParseModRM / UseModRM). */
652	case 'G': /* ModRM selects general register (ParseModRM / UseModRM). */
653	case 'S': /* ModRM byte selects a segment register (ParseModRM / UseModRM). */
654	case 'T': /* ModRM byte selects a test register (ParseModRM / UseModRM). */
655	case 'V': /* ModRM byte selects an XMM/SSE register (ParseModRM / UseModRM). */
656	case 'P': /* ModRM byte selects MMX register (ParseModRM / UseModRM). */
657	{
658	pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
659	Assert(!(pParam->flags & (USE_INDEX \| USE_SCALE) /* No SIB here... */));
660	Assert(!(pParam->flags & (USE_DISPLACEMENT8 \| USE_DISPLACEMENT16 \| USE_DISPLACEMENT32 \| USE_DISPLACEMENT64 \| USE_RIPDISPLACEMENT32)));
661
662	size_t cchReg;
663	const char *pszReg = disasmFormatYasmBaseReg(pCpu, pParam, &cchReg);
664	PUT_STR(pszReg, cchReg);
665	break;
666	}
667
668	/*
669	* ModRM - Register or memory.
670	*/
671	case 'E': /* ModRM specifies parameter (ParseModRM / UseModRM / UseSIB). */
672	case 'Q': /* ModRM byte selects MMX register or memory address (ParseModRM / UseModRM). */
673	case 'R': /* ModRM byte may only refer to a general register (ParseModRM / UseModRM). */
674	case 'W': /* ModRM byte selects an XMM/SSE register or a memory address (ParseModRM / UseModRM). */
675	case 'M': /* ModRM may only refer to memory (ParseModRM / UseModRM). */
676	{
677	pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
678
679	PUT_FAR();
680	if (DIS_IS_EFFECTIVE_ADDR(pParam->flags))
681	{
682	/* Work around mov seg,[mem16] and mov [mem16],seg as these always make a 16-bit mem
683	while the register variants deals with 16, 32 & 64 in the normal fashion. */
684	if ( pParam->param != OP_PARM_Ev
685	\|\| pOp->opcode != OP_MOV
686	\|\| ( pOp->param1 != OP_PARM_Sw
687	&& pOp->param2 != OP_PARM_Sw))
688	PUT_SIZE_OVERRIDE();
689	PUT_C('[');
690	}
691	if ( (fFlags & DIS_FMT_FLAGS_STRICT)
692	&& (pParam->flags & (USE_DISPLACEMENT8 \| USE_DISPLACEMENT16 \| USE_DISPLACEMENT32 \| USE_DISPLACEMENT64 \| USE_RIPDISPLACEMENT32)))
693	{
694	if ( (pParam->flags & USE_DISPLACEMENT8)
695	&& !pParam->disp8)
696	PUT_SZ("byte ");
697	else if ( (pParam->flags & USE_DISPLACEMENT16)
698	&& (int8_t)pParam->disp16 == (int16_t)pParam->disp16)
699	PUT_SZ("word ");
700	else if ( (pParam->flags & USE_DISPLACEMENT32)
701	&& (int8_t)pParam->disp32 == (int32_t)pParam->disp32)
702	PUT_SZ("dword ");
703	}
704	if (DIS_IS_EFFECTIVE_ADDR(pParam->flags))
705	PUT_SEGMENT_OVERRIDE();
706
707	bool fBase = (pParam->flags & USE_BASE) /* When exactly is USE_BASE supposed to be set? disasmModRMReg doesn't set it. */
708	\|\| ( (pParam->flags & (USE_REG_GEN8 \| USE_REG_GEN16 \| USE_REG_GEN32 \| USE_REG_GEN64))
709	&& !DIS_IS_EFFECTIVE_ADDR(pParam->flags));
710	if (fBase)
711	{
712	size_t cchReg;
713	const char *pszReg = disasmFormatYasmBaseReg(pCpu, pParam, &cchReg);
714	PUT_STR(pszReg, cchReg);
715	}
716
717	if (pParam->flags & USE_INDEX)
718	{
719	if (fBase)
720	PUT_C('+');
721
722	size_t cchReg;
723	const char *pszReg = disasmFormatYasmIndexReg(pCpu, pParam, &cchReg);
724	PUT_STR(pszReg, cchReg);
725
726	if (pParam->flags & USE_SCALE)
727	{
728	PUT_C('*');
729	PUT_C('0' + pParam->scale);
730	}
731	}
732	else
733	Assert(!(pParam->flags & USE_SCALE));
734
735	if (pParam->flags & (USE_DISPLACEMENT8 \| USE_DISPLACEMENT16 \| USE_DISPLACEMENT32 \| USE_DISPLACEMENT64 \| USE_RIPDISPLACEMENT32))
736	{
737	Assert(!(pParam->flags & USE_DISPLACEMENT64));
738	int32_t off;
739	if (pParam->flags & USE_DISPLACEMENT8)
740	off = pParam->disp8;
741	else if (pParam->flags & USE_DISPLACEMENT16)
742	off = pParam->disp16;
743	else if (pParam->flags & (USE_DISPLACEMENT32 \| USE_RIPDISPLACEMENT32))
744	off = pParam->disp32;
745
746	if (fBase \|\| (pParam->flags & USE_INDEX))
747	PUT_C(off >= 0 ? '+' : '-');
748
749	if (off < 0)
750	off = -off;
751	if (pParam->flags & USE_DISPLACEMENT8)
752	PUT_NUM_8( off);
753	else if (pParam->flags & USE_DISPLACEMENT16)
754	PUT_NUM_16(off);
755	else if (pParam->flags & USE_DISPLACEMENT32)
756	PUT_NUM_32(off);
757	else
758	{
759	PUT_NUM_32(off);
760	PUT_SZ(" wrt rip"); //??
761	}
762	}
763
764	if (DIS_IS_EFFECTIVE_ADDR(pParam->flags))
765	PUT_C(']');
766	break;
767	}
768
769	case 'F': /* Eflags register (0 - popf/pushf only, avoided in adjustments above). */
770	AssertFailed();
771	break;
772
773	case 'I': /* Immediate data (ParseImmByte, ParseImmByteSX, ParseImmV, ParseImmUshort, ParseImmZ). */
774	Assert(pszFmt == 'b' \|\| pszFmt == 'v' \|\| pszFmt == 'w' \|\| pszFmt == 'z'); pszFmt++;
775	switch (pParam->flags & ( USE_IMMEDIATE8 \| USE_IMMEDIATE16 \| USE_IMMEDIATE32 \| USE_IMMEDIATE64
776	\| USE_IMMEDIATE16_SX8 \| USE_IMMEDIATE32_SX8))
777	{
778	case USE_IMMEDIATE8:
779	if ( (fFlags & DIS_FMT_FLAGS_STRICT)
780	&& ( (pOp->param1 >= OP_PARM_REG_GEN8_START && pOp->param1 <= OP_PARM_REG_GEN8_END)
781	\|\| (pOp->param2 >= OP_PARM_REG_GEN8_START && pOp->param2 <= OP_PARM_REG_GEN8_END))
782	)
783	PUT_SZ("strict byte ");
784	PUT_NUM_8(pParam->parval);
785	break;
786
787	case USE_IMMEDIATE16:
788	if ( pCpu->mode != pCpu->opmode
789	\|\| ( (fFlags & DIS_FMT_FLAGS_STRICT)
790	&& ( (int8_t)pParam->parval == (int16_t)pParam->parval
791	\|\| (pOp->param1 >= OP_PARM_REG_GEN16_START && pOp->param1 <= OP_PARM_REG_GEN16_END)
792	\|\| (pOp->param2 >= OP_PARM_REG_GEN16_START && pOp->param2 <= OP_PARM_REG_GEN16_END))
793	)
794	)
795	{
796	if (OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_b)
797	PUT_SZ_STRICT("strict byte ", "byte ");
798	else if (OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_v)
799	PUT_SZ_STRICT("strict word ", "word ");
800	}
801	PUT_NUM_16(pParam->parval);
802	break;
803
804	case USE_IMMEDIATE16_SX8:
805	PUT_SZ_STRICT("strict byte ", "byte ");
806	PUT_NUM_16(pParam->parval);
807	break;
808
809	case USE_IMMEDIATE32:
810	if ( pCpu->opmode != (pCpu->mode == CPUMODE_16BIT ? CPUMODE_16BIT : CPUMODE_32BIT) /* not perfect */
811	\|\| ( (fFlags & DIS_FMT_FLAGS_STRICT)
812	&& ( (int8_t)pParam->parval == (int32_t)pParam->parval
813	\|\| (pOp->param1 >= OP_PARM_REG_GEN32_START && pOp->param1 <= OP_PARM_REG_GEN32_END)
814	\|\| (pOp->param2 >= OP_PARM_REG_GEN32_START && pOp->param2 <= OP_PARM_REG_GEN32_END))
815	)
816	)
817	{
818	if (OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_b)
819	PUT_SZ_STRICT("strict byte ", "byte ");
820	else if (OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_v)
821	PUT_SZ_STRICT("strict dword ", "dword ");
822	}
823	PUT_NUM_32(pParam->parval);
824	break;
825
826	case USE_IMMEDIATE32_SX8:
827	PUT_SZ_STRICT("strict byte ", "byte ");
828	PUT_NUM_32(pParam->parval);
829	break;
830
831	case USE_IMMEDIATE64:
832	PUT_NUM_64(pParam->parval);
833	break;
834
835	default:
836	AssertFailed();
837	break;
838	}
839	break;
840
841	case 'J': /* Relative jump offset (ParseImmBRel + ParseImmVRel). */
842	{
843	int32_t offDisplacement;
844	Assert(iParam == 1);
845	bool fPrefix = (fFlags & DIS_FMT_FLAGS_STRICT)
846	&& pOp->opcode != OP_CALL
847	&& pOp->opcode != OP_LOOP
848	&& pOp->opcode != OP_LOOPE
849	&& pOp->opcode != OP_LOOPNE
850	&& pOp->opcode != OP_JECXZ;
851
852	if (pParam->flags & USE_IMMEDIATE8_REL)
853	{
854	if (fPrefix)
855	PUT_SZ("short ");
856	offDisplacement = (int8_t)pParam->parval;
857	Assert(*pszFmt == 'b'); pszFmt++;
858
859	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
860	PUT_NUM_S8(offDisplacement);
861	}
862	else if (pParam->flags & USE_IMMEDIATE16_REL)
863	{
864	if (fPrefix)
865	PUT_SZ("near ");
866	offDisplacement = (int16_t)pParam->parval;
867	Assert(*pszFmt == 'v'); pszFmt++;
868
869	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
870	PUT_NUM_S16(offDisplacement);
871	}
872	else
873	{
874	if (fPrefix)
875	PUT_SZ("near ");
876	offDisplacement = (int32_t)pParam->parval;
877	Assert(pParam->flags & USE_IMMEDIATE32_REL);
878	Assert(*pszFmt == 'v'); pszFmt++;
879
880	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
881	PUT_NUM_S32(offDisplacement);
882	}
883	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
884	PUT_SZ(" (");
885
886	RTUINTPTR uTrgAddr = pCpu->opaddr + pCpu->opsize + offDisplacement;
887	if (pCpu->mode == CPUMODE_16BIT)
888	PUT_NUM_16(uTrgAddr);
889	else if (pCpu->mode == CPUMODE_32BIT)
890	PUT_NUM_32(uTrgAddr);
891	else
892	PUT_NUM_64(uTrgAddr);
893
894	if (pfnGetSymbol)
895	{
896	int rc = pfnGetSymbol(DIS_FMT_SEL_FROM_REG(USE_REG_CS), uTrgAddr, szSymbol, sizeof(szSymbol), &off, pvUser);
897	if (RT_SUCCESS(rc))
898	{
899	PUT_SZ(" [");
900	PUT_PSZ(szSymbol);
901	if (off != 0)
902	{
903	if ((int8_t)off == off)
904	PUT_NUM_S8(off);
905	else if ((int16_t)off == off)
906	PUT_NUM_S16(off);
907	else if ((int32_t)off == off)
908	PUT_NUM_S32(off);
909	else
910	PUT_NUM_S64(off);
911	}
912	PUT_C(']');
913	}
914	}
915
916	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
917	PUT_C(')');
918	break;
919	}
920
921	case 'A': /* Direct (jump/call) address (ParseImmAddr). */
922	{
923	Assert(*pszFmt == 'p'); pszFmt++;
924	PUT_FAR();
925	PUT_SIZE_OVERRIDE();
926	PUT_SEGMENT_OVERRIDE();
927	int rc;
928	switch (pParam->flags & (USE_IMMEDIATE_ADDR_16_16 \| USE_IMMEDIATE_ADDR_16_32 \| USE_DISPLACEMENT64 \| USE_DISPLACEMENT32 \| USE_DISPLACEMENT16))
929	{
930	case USE_IMMEDIATE_ADDR_16_16:
931	PUT_NUM_16(pParam->parval >> 16);
932	PUT_C(':');
933	PUT_NUM_16(pParam->parval);
934	if (pfnGetSymbol)
935	rc = pfnGetSymbol(DIS_FMT_SEL_FROM_VALUE(pParam->parval >> 16), (uint16_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
936	break;
937	case USE_IMMEDIATE_ADDR_16_32:
938	PUT_NUM_16(pParam->parval >> 32);
939	PUT_C(':');
940	PUT_NUM_32(pParam->parval);
941	if (pfnGetSymbol)
942	rc = pfnGetSymbol(DIS_FMT_SEL_FROM_VALUE(pParam->parval >> 16), (uint32_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
943	break;
944	case USE_DISPLACEMENT16:
945	PUT_NUM_16(pParam->parval);
946	if (pfnGetSymbol)
947	rc = pfnGetSymbol(DIS_FMT_SEL_FROM_REG(USE_REG_CS), (uint16_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
948	break;
949	case USE_DISPLACEMENT32:
950	PUT_NUM_32(pParam->parval);
951	if (pfnGetSymbol)
952	rc = pfnGetSymbol(DIS_FMT_SEL_FROM_REG(USE_REG_CS), (uint32_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
953	break;
954	case USE_DISPLACEMENT64:
955	PUT_NUM_64(pParam->parval);
956	if (pfnGetSymbol)
957	rc = pfnGetSymbol(DIS_FMT_SEL_FROM_REG(USE_REG_CS), (uint64_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
958	break;
959	default:
960	AssertFailed();
961	break;
962	}
963
964	if (pfnGetSymbol && RT_SUCCESS(rc))
965	{
966	PUT_SZ(" [");
967	PUT_PSZ(szSymbol);
968	if (off != 0)
969	{
970	if ((int8_t)off == off)
971	PUT_NUM_S8(off);
972	else if ((int16_t)off == off)
973	PUT_NUM_S16(off);
974	else if ((int32_t)off == off)
975	PUT_NUM_S32(off);
976	else
977	PUT_NUM_S64(off);
978	}
979	PUT_C(']');
980	}
981	break;
982	}
983
984	case 'O': /* No ModRM byte (ParseImmAddr). */
985	{
986	Assert(pszFmt == 'b' \|\| pszFmt == 'v'); pszFmt++;
987	PUT_FAR();
988	PUT_SIZE_OVERRIDE();
989	PUT_C('[');
990	PUT_SEGMENT_OVERRIDE();
991	int rc;
992	switch (pParam->flags & (USE_IMMEDIATE_ADDR_16_16 \| USE_IMMEDIATE_ADDR_16_32 \| USE_DISPLACEMENT64 \| USE_DISPLACEMENT32 \| USE_DISPLACEMENT16))
993	{
994	case USE_IMMEDIATE_ADDR_16_16:
995	PUT_NUM_16(pParam->parval >> 16);
996	PUT_C(':');
997	PUT_NUM_16(pParam->parval);
998	if (pfnGetSymbol)
999	rc = pfnGetSymbol(DIS_FMT_SEL_FROM_VALUE(pParam->parval >> 16), (uint16_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
1000	break;
1001	case USE_IMMEDIATE_ADDR_16_32:
1002	PUT_NUM_16(pParam->parval >> 32);
1003	PUT_C(':');
1004	PUT_NUM_32(pParam->parval);
1005	if (pfnGetSymbol)
1006	rc = pfnGetSymbol(DIS_FMT_SEL_FROM_VALUE(pParam->parval >> 16), (uint32_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
1007	break;
1008	case USE_DISPLACEMENT16:
1009	PUT_NUM_16(pParam->disp16);
1010	if (pfnGetSymbol)
1011	rc = pfnGetSymbol(DIS_FMT_SEL_FROM_REG(USE_REG_CS), (uint16_t)pParam->disp16, szSymbol, sizeof(szSymbol), &off, pvUser);
1012	break;
1013	case USE_DISPLACEMENT32:
1014	PUT_NUM_32(pParam->disp32);
1015	if (pfnGetSymbol)
1016	rc = pfnGetSymbol(DIS_FMT_SEL_FROM_REG(USE_REG_CS), (uint32_t)pParam->disp32, szSymbol, sizeof(szSymbol), &off, pvUser);
1017	break;
1018	case USE_DISPLACEMENT64:
1019	PUT_NUM_64(pParam->disp64);
1020	if (pfnGetSymbol)
1021	rc = pfnGetSymbol(DIS_FMT_SEL_FROM_REG(USE_REG_CS), (uint64_t)pParam->disp64, szSymbol, sizeof(szSymbol), &off, pvUser);
1022	break;
1023	default:
1024	AssertFailed();
1025	break;
1026	}
1027	PUT_C(']');
1028
1029	if (pfnGetSymbol && RT_SUCCESS(rc))
1030	{
1031	PUT_SZ(" (");
1032	PUT_PSZ(szSymbol);
1033	if (off != 0)
1034	{
1035	if ((int8_t)off == off)
1036	PUT_NUM_S8(off);
1037	else if ((int16_t)off == off)
1038	PUT_NUM_S16(off);
1039	else if ((int32_t)off == off)
1040	PUT_NUM_S32(off);
1041	else
1042	PUT_NUM_S64(off);
1043	}
1044	PUT_C(')');
1045	}
1046	break;
1047	}
1048
1049	case 'X': /* DS:SI (ParseXb, ParseXv). */
1050	case 'Y': /* ES:DI (ParseYb, ParseYv). */
1051	{
1052	Assert(pszFmt == 'b' \|\| pszFmt == 'v'); pszFmt++;
1053	PUT_FAR();
1054	PUT_SIZE_OVERRIDE();
1055	PUT_C('[');
1056	if (pParam->flags & USE_POINTER_DS_BASED)
1057	PUT_SZ("ds:");
1058	else
1059	PUT_SZ("es:");
1060
1061	size_t cchReg;
1062	const char *pszReg = disasmFormatYasmBaseReg(pCpu, pParam, &cchReg);
1063	PUT_STR(pszReg, cchReg);
1064	PUT_C(']');
1065	break;
1066	}
1067
1068	case 'e': /* Register based on operand size (e.g. %eAX) (ParseFixedReg). */
1069	{
1070	Assert(RT_C_IS_ALPHA(pszFmt[0]) && RT_C_IS_ALPHA(pszFmt[1]) && !RT_C_IS_ALPHA(pszFmt[2])); pszFmt += 2;
1071	size_t cchReg;
1072	const char *pszReg = disasmFormatYasmBaseReg(pCpu, pParam, &cchReg);
1073	PUT_STR(pszReg, cchReg);
1074	break;
1075	}
1076
1077	default:
1078	AssertMsgFailed(("%c%s!\n", ch, pszFmt));
1079	break;
1080	}
1081	AssertMsg(pszFmt == ',' \|\| pszFmt == '\0', ("%c%s\n", ch, pszFmt));
1082	}
1083	else
1084	{
1085	PUT_C(ch);
1086	if (ch == ',')
1087	{
1088	Assert(*pszFmt != ' ');
1089	PUT_C(' ');
1090	switch (++iParam)
1091	{
1092	case 2: pParam = &pCpu->param2; break;
1093	case 3: pParam = &pCpu->param3; break;
1094	default: pParam = NULL; break;
1095	}
1096	}
1097	}
1098	} /* while more to format */
1099	}
1100
1101	/*
1102	* Any additional output to the right of the instruction?
1103	*/
1104	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
1105	{
1106	/* some up front padding. */
1107	size_t cchPadding = cchOutput - offInstruction;
1108	cchPadding = cchPadding + 1 >= 42 ? 1 : 42 - cchPadding;
1109	PUT_STR(g_szSpaces, cchPadding);
1110
1111	/* comment? */
1112	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
1113	PUT_SZ(";");
1114
1115	/*
1116	* The address?
1117	*/
1118	if (fFlags & DIS_FMT_FLAGS_ADDR_RIGHT)
1119	{
1120	PUT_C(' ');
1121	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
1122	if (pCpu->opaddr >= _4G)
1123	PUT_NUM(9, "%08x`", (uint32_t)(pCpu->opaddr >> 32));
1124	#endif
1125	PUT_NUM(8, "%08x", (uint32_t)pCpu->opaddr);
1126	}
1127
1128	/*
1129	* Opcode bytes?
1130	*/
1131	if (fFlags & DIS_FMT_FLAGS_BYTES_RIGHT)
1132	{
1133	PUT_C(' ');
1134	size_t cchTmp = disFormatBytes(pCpu, pszDst, cchDst, fFlags);
1135	cchOutput += cchTmp;
1136	if (cchTmp >= cchDst)
1137	cchTmp = cchDst - (cchDst != 0);
1138	cchDst -= cchTmp;
1139	pszDst += cchTmp;
1140	}
1141	}
1142
1143	/*
1144	* Terminate it - on overflow we'll have reserved one byte for this.
1145	*/
1146	if (cchDst > 0)
1147	*pszDst = '\0';
1148	else
1149	Assert(!cchBuf);
1150
1151	/* clean up macros */
1152	#undef PUT_PSZ
1153	#undef PUT_SZ
1154	#undef PUT_STR
1155	#undef PUT_C
1156	return cchOutput;
1157	}
1158
1159
1160	/**
1161	* Formats the current instruction in Yasm (/ Nasm) style.
1162	*
1163	* This is a simplified version of DISFormatYasmEx() provided for your convenience.
1164	*
1165	*
1166	* @returns The number of output characters. If this is >= cchBuf, then the content
1167	* of pszBuf will be truncated.
1168	* @param pCpu Pointer to the disassembler CPU state.
1169	* @param pszBuf The output buffer.
1170	* @param cchBuf The size of the output buffer.
1171	*/
1172	DISDECL(size_t) DISFormatYasm(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf)
1173	{
1174	return DISFormatYasmEx(pCpu, pszBuf, cchBuf, 0 /* fFlags /, NULL / pfnGetSymbol /, NULL / pvUser */);
1175	}
1176

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source: vbox/trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp@ 9271

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