DisasmFormatYasm.cpp@ 9642

Last change on this file since 9642 was 9342, checked in by vboxsync, 17 years ago
Corrected the array index.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 49.3 KB

Line
1	/* $Id: DisasmFormatYasm.cpp 9342 2008-06-03 09:09:32Z vboxsync $ */
2	/** @file
3	* VBox Disassembler - Yasm(/Nasm) Style Formatter.
4	*/
5
6	/*
7	* Copyright (C) 2008 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#include <VBox/dis.h>
27	#include "DisasmInternal.h"
28	#include <iprt/string.h>
29	#include <iprt/assert.h>
30	#include <iprt/ctype.h>
31
32
33	/*******************************************************************************
34	* Global Variables *
35	*******************************************************************************/
36	static const char g_szSpaces[] =
37	" ";
38	static const char g_aszYasmRegGen8x86[8][4] =
39	{
40	"al\0", "cl\0", "dl\0", "bl\0", "ah\0", "ch\0", "dh\0", "bh\0"
41	};
42	static const char g_aszYasmRegGen8Amd64[16][5] =
43	{
44	"al\0\0", "cl\0\0", "dl\0\0", "bl\0\0", "spb\0", "bpb\0", "sib\0", "dib\0", "r8b\0", "r9b\0", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
45	};
46	static const char g_aszYasmRegGen16[16][5] =
47	{
48	"ax\0\0", "cx\0\0", "dx\0\0", "bx\0\0", "sp\0\0", "bp\0\0", "si\0\0", "di\0\0", "r8w\0", "r9w\0", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
49	};
50	static const char g_aszYasmRegGen1616[8][6] =
51	{
52	"bx+si", "bx+di", "bp+si", "bp+di", "si\0\0\0", "di\0\0\0", "bp\0\0\0", "bx\0\0\0"
53	};
54	static const char g_aszYasmRegGen32[16][5] =
55	{
56	"eax\0", "ecx\0", "edx\0", "ebx\0", "esp\0", "ebp\0", "esi\0", "edi\0", "r8d\0", "r9d\0", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
57	};
58	static const char g_aszYasmRegGen64[16][4] =
59	{
60	"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", "r8\0", "r9\0", "r10", "r11", "r12", "r13", "r14", "r15"
61	};
62	static const char g_aszYasmRegSeg[6][3] =
63	{
64	"es", "cs", "ss", "ds", "fs", "gs"
65	};
66	static const char g_aszYasmRegFP[8][4] =
67	{
68	"st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7"
69	};
70	static const char g_aszYasmRegMMX[8][4] =
71	{
72	"mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7"
73	};
74	static const char g_aszYasmRegXMM[16][6] =
75	{
76	"xmm0\0", "xmm1\0", "xmm2\0", "xmm3\0", "xmm4\0", "xmm5\0", "xmm6\0", "xmm7\0", "xmm8\0", "xmm9\0", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
77	};
78	static const char g_aszYasmRegCRx[16][5] =
79	{
80	"cr0\0", "cr1\0", "cr2\0", "cr3\0", "cr4\0", "cr5\0", "cr6\0", "cr7\0", "cr8\0", "cr9\0", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15"
81	};
82	static const char g_aszYasmRegDRx[16][5] =
83	{
84	"dr0\0", "dr1\0", "dr2\0", "dr3\0", "dr4\0", "dr5\0", "dr6\0", "dr7\0", "dr8\0", "dr9\0", "dr10", "dr11", "dr12", "dr13", "dr14", "dr15"
85	};
86	static const char g_aszYasmRegTRx[16][5] =
87	{
88	"tr0\0", "tr1\0", "tr2\0", "tr3\0", "tr4\0", "tr5\0", "tr6\0", "tr7\0", "tr8\0", "tr9\0", "tr10", "tr11", "tr12", "tr13", "tr14", "tr15"
89	};
90
91
92
93	/**
94	* Gets the base register name for the given parameter.
95	*
96	* @returns Pointer to the register name.
97	* @param pCpu The disassembler cpu state.
98	* @param pParam The parameter.
99	* @param pcchReg Where to store the length of the name.
100	*/
101	static const char disasmFormatYasmBaseReg(PCDISCPUSTATE pCpu, PCOP_PARAMETER pParam, size_t pcchReg)
102	{
103	switch (pParam->flags & ( USE_REG_GEN8 \| USE_REG_GEN16 \| USE_REG_GEN32 \| USE_REG_GEN64
104	\| USE_REG_FP \| USE_REG_MMX \| USE_REG_XMM \| USE_REG_CR
105	\| USE_REG_DBG \| USE_REG_SEG \| USE_REG_TEST))
106
107	{
108	case USE_REG_GEN8:
109	if (pCpu->opmode == CPUMODE_64BIT)
110	{
111	Assert(pParam->base.reg_gen < RT_ELEMENTS(g_aszYasmRegGen8Amd64));
112	const char *psz = g_aszYasmRegGen8Amd64[pParam->base.reg_gen];
113	*pcchReg = 2 + !!psz[2] + !!psz[3];
114	return psz;
115	}
116	*pcchReg = 2;
117	Assert(pParam->base.reg_gen < RT_ELEMENTS(g_aszYasmRegGen8x86));
118	return g_aszYasmRegGen8x86[pParam->base.reg_gen];
119
120	case USE_REG_GEN16:
121	{
122	Assert(pParam->base.reg_gen < RT_ELEMENTS(g_aszYasmRegGen16));
123	const char *psz = g_aszYasmRegGen16[pParam->base.reg_gen];
124	*pcchReg = 2 + !!psz[2] + !!psz[3];
125	return psz;
126	}
127
128	case USE_REG_GEN32:
129	{
130	Assert(pParam->base.reg_gen < RT_ELEMENTS(g_aszYasmRegGen32));
131	const char *psz = g_aszYasmRegGen32[pParam->base.reg_gen];
132	*pcchReg = 2 + !!psz[2] + !!psz[3];
133	return psz;
134	}
135
136	case USE_REG_GEN64:
137	{
138	Assert(pParam->base.reg_gen < RT_ELEMENTS(g_aszYasmRegGen64));
139	const char *psz = g_aszYasmRegGen64[pParam->base.reg_gen];
140	*pcchReg = 2 + !!psz[2] + !!psz[3];
141	return psz;
142	}
143
144	case USE_REG_FP:
145	{
146	Assert(pParam->base.reg_fp < RT_ELEMENTS(g_aszYasmRegFP));
147	const char *psz = g_aszYasmRegFP[pParam->base.reg_fp];
148	*pcchReg = 3;
149	return psz;
150	}
151
152	case USE_REG_MMX:
153	{
154	Assert(pParam->base.reg_mmx < RT_ELEMENTS(g_aszYasmRegMMX));
155	const char *psz = g_aszYasmRegMMX[pParam->base.reg_mmx];
156	*pcchReg = 3;
157	return psz;
158	}
159
160	case USE_REG_XMM:
161	{
162	Assert(pParam->base.reg_xmm < RT_ELEMENTS(g_aszYasmRegXMM));
163	const char *psz = g_aszYasmRegXMM[pParam->base.reg_mmx];
164	*pcchReg = 4 + !!psz[4];
165	return psz;
166	}
167
168	case USE_REG_CR:
169	{
170	Assert(pParam->base.reg_ctrl < RT_ELEMENTS(g_aszYasmRegCRx));
171	const char *psz = g_aszYasmRegCRx[pParam->base.reg_ctrl];
172	*pcchReg = 3;
173	return psz;
174	}
175
176	case USE_REG_DBG:
177	{
178	Assert(pParam->base.reg_dbg < RT_ELEMENTS(g_aszYasmRegDRx));
179	const char *psz = g_aszYasmRegDRx[pParam->base.reg_dbg];
180	*pcchReg = 3;
181	return psz;
182	}
183
184	case USE_REG_SEG:
185	{
186	Assert(pParam->base.reg_seg < RT_ELEMENTS(g_aszYasmRegCRx));
187	const char *psz = g_aszYasmRegSeg[pParam->base.reg_seg];
188	*pcchReg = 2;
189	return psz;
190	}
191
192	case USE_REG_TEST:
193	{
194	Assert(pParam->base.reg_test < RT_ELEMENTS(g_aszYasmRegTRx));
195	const char *psz = g_aszYasmRegTRx[pParam->base.reg_test];
196	*pcchReg = 3;
197	return psz;
198	}
199
200	default:
201	AssertMsgFailed(("%#x\n", pParam->flags));
202	*pcchReg = 3;
203	return "r??";
204	}
205	}
206
207
208	/**
209	* Gets the index register name for the given parameter.
210	*
211	* @returns The index register name.
212	* @param pCpu The disassembler cpu state.
213	* @param pParam The parameter.
214	* @param pcchReg Where to store the length of the name.
215	*/
216	static const char disasmFormatYasmIndexReg(PCDISCPUSTATE pCpu, PCOP_PARAMETER pParam, size_t pcchReg)
217	{
218	switch (pCpu->addrmode)
219	{
220	case CPUMODE_16BIT:
221	{
222	Assert(pParam->index.reg_gen < RT_ELEMENTS(g_aszYasmRegGen16));
223	const char *psz = g_aszYasmRegGen16[pParam->index.reg_gen];
224	*pcchReg = 2 + !!psz[2] + !!psz[3];
225	return psz;
226	}
227
228	case CPUMODE_32BIT:
229	{
230	Assert(pParam->index.reg_gen < RT_ELEMENTS(g_aszYasmRegGen32));
231	const char *psz = g_aszYasmRegGen32[pParam->index.reg_gen];
232	*pcchReg = 2 + !!psz[2] + !!psz[3];
233	return psz;
234	}
235
236	case CPUMODE_64BIT:
237	{
238	Assert(pParam->index.reg_gen < RT_ELEMENTS(g_aszYasmRegGen64));
239	const char *psz = g_aszYasmRegGen64[pParam->index.reg_gen];
240	*pcchReg = 2 + !!psz[2] + !!psz[3];
241	return psz;
242	}
243
244	default:
245	AssertMsgFailed(("%#x %#x\n", pParam->flags, pCpu->addrmode));
246	*pcchReg = 3;
247	return "r??";
248	}
249	}
250
251
252	/**
253	* Formats the current instruction in Yasm (/ Nasm) style.
254	*
255	*
256	* @returns The number of output characters. If this is >= cchBuf, then the content
257	* of pszBuf will be truncated.
258	* @param pCpu Pointer to the disassembler CPU state.
259	* @param pszBuf The output buffer.
260	* @param cchBuf The size of the output buffer.
261	* @param fFlags Format flags, see DIS_FORMAT_FLAGS_*.
262	* @param pfnGetSymbol Get symbol name for a jmp or call target address. Optional.
263	* @param pvUser User argument for pfnGetSymbol.
264	*/
265	DISDECL(size_t) DISFormatYasmEx(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags,
266	PFNDISGETSYMBOL pfnGetSymbol, void *pvUser)
267	{
268	/*
269	* Input validation and massaging.
270	*/
271	AssertPtr(pCpu);
272	AssertPtrNull(pszBuf);
273	Assert(pszBuf \|\| !cchBuf);
274	AssertPtrNull(pfnGetSymbol);
275	AssertMsg(DIS_FMT_FLAGS_IS_VALID(fFlags), ("%#x\n", fFlags));
276	if (fFlags & DIS_FMT_FLAGS_ADDR_COMMENT)
277	fFlags = (fFlags & ~DIS_FMT_FLAGS_ADDR_LEFT) \| DIS_FMT_FLAGS_ADDR_RIGHT;
278	if (fFlags & DIS_FMT_FLAGS_BYTES_COMMENT)
279	fFlags = (fFlags & ~DIS_FMT_FLAGS_BYTES_LEFT) \| DIS_FMT_FLAGS_BYTES_RIGHT;
280
281	PCOPCODE const pOp = pCpu->pCurInstr;
282
283	/*
284	* Output macros
285	*/
286	char *pszDst = pszBuf;
287	size_t cchDst = cchBuf;
288	size_t cchOutput = 0;
289	#define PUT_C(ch) \
290	do { \
291	cchOutput++; \
292	if (cchDst > 1) \
293	{ \
294	cchDst--; \
295	*pszDst++ = (ch); \
296	} \
297	} while (0)
298	#define PUT_STR(pszSrc, cchSrc) \
299	do { \
300	cchOutput += (cchSrc); \
301	if (cchDst > (cchSrc)) \
302	{ \
303	memcpy(pszDst, (pszSrc), (cchSrc)); \
304	pszDst += (cchSrc); \
305	cchDst -= (cchSrc); \
306	} \
307	else if (cchDst > 1) \
308	{ \
309	memcpy(pszDst, (pszSrc), cchDst - 1); \
310	pszDst += cchDst - 1; \
311	cchDst = 1; \
312	} \
313	} while (0)
314	#define PUT_SZ(sz) \
315	PUT_STR((sz), sizeof(sz) - 1)
316	#define PUT_SZ_STRICT(szStrict, szRelaxed) \
317	do { if (fFlags & DIS_FMT_FLAGS_STRICT) PUT_SZ(szStrict); else PUT_SZ(szRelaxed); } while (0)
318	#define PUT_PSZ(psz) \
319	do { const size_t cchTmp = strlen(psz); PUT_STR((psz), cchTmp); } while (0)
320	#define PUT_NUM(cch, fmt, num) \
321	do { \
322	cchOutput += (cch); \
323	if (cchDst > 1) \
324	{ \
325	const size_t cchTmp = RTStrPrintf(pszDst, cchDst, fmt, (num)); \
326	pszDst += cchTmp; \
327	cchDst -= cchTmp; \
328	Assert(cchTmp == (cch) \|\| cchDst == 1); \
329	} \
330	} while (0)
331	/** @todo add two flags for choosing between %X / %x and h / 0x. */
332	#define PUT_NUM_8(num) PUT_NUM(4, "0%02xh", (uint8_t)(num))
333	#define PUT_NUM_16(num) PUT_NUM(6, "0%04xh", (uint16_t)(num))
334	#define PUT_NUM_32(num) PUT_NUM(10, "0%08xh", (uint32_t)(num))
335	#define PUT_NUM_64(num) PUT_NUM(18, "0%08xh", (uint64_t)(num))
336
337	#define PUT_NUM_SIGN(cch, fmt, num, stype, utype) \
338	do { \
339	if ((stype)(num) >= 0) \
340	{ \
341	PUT_C('+'); \
342	PUT_NUM(cch, fmt, (utype)(num)); \
343	} \
344	else \
345	{ \
346	PUT_C('-'); \
347	PUT_NUM(cch, fmt, (utype)-(stype)(num)); \
348	} \
349	} while (0)
350	#define PUT_NUM_S8(num) PUT_NUM_SIGN(4, "0%02xh", num, int8_t, uint8_t)
351	#define PUT_NUM_S16(num) PUT_NUM_SIGN(6, "0%04xh", num, int16_t, uint16_t)
352	#define PUT_NUM_S32(num) PUT_NUM_SIGN(10, "0%08xh", num, int32_t, uint32_t)
353	#define PUT_NUM_S64(num) PUT_NUM_SIGN(18, "0%08xh", num, int64_t, uint64_t)
354
355
356	/*
357	* The address?
358	*/
359	if (fFlags & DIS_FMT_FLAGS_ADDR_LEFT)
360	{
361	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
362	if (pCpu->opaddr >= _4G)
363	PUT_NUM(9, "%08x`", (uint32_t)(pCpu->opaddr >> 32));
364	#endif
365	PUT_NUM(8, "%08x", (uint32_t)pCpu->opaddr);
366	PUT_C(' ');
367	}
368
369	/*
370	* The opcode bytes?
371	*/
372	if (fFlags & DIS_FMT_FLAGS_BYTES_LEFT)
373	{
374	size_t cchTmp = disFormatBytes(pCpu, pszDst, cchDst, fFlags);
375	cchOutput += cchTmp;
376	if (cchDst > 1)
377	{
378	if (cchTmp <= cchDst)
379	{
380	cchDst -= cchTmp;
381	pszDst += cchTmp;
382	}
383	else
384	{
385	pszDst += cchDst - 1;
386	cchDst = 1;
387	}
388	}
389
390	/* Some padding to align the instruction. */
391	size_t cchPadding = (7 * (2 + !!(fFlags & DIS_FMT_FLAGS_BYTES_SPACED)))
392	+ !!(fFlags & DIS_FMT_FLAGS_BYTES_BRACKETS) * 2
393	+ 2;
394	cchPadding = cchTmp + 1 >= cchPadding ? 1 : cchPadding - cchTmp;
395	PUT_STR(g_szSpaces, cchPadding);
396	}
397
398
399	/*
400	* Filter out invalid opcodes first as they need special
401	* treatment. UD2 is an exception and should be handled normally.
402	*/
403	size_t const offInstruction = cchOutput;
404	if ( pOp->opcode == OP_INVALID
405	\|\| ( pOp->opcode == OP_ILLUD2
406	&& (pCpu->prefix & PREFIX_LOCK)))
407	{
408
409	}
410	else
411	{
412	/*
413	* Prefixes
414	*/
415	if (pCpu->prefix & PREFIX_LOCK)
416	PUT_SZ("lock ");
417	if(pCpu->prefix & PREFIX_REP)
418	PUT_SZ("rep ");
419	else if(pCpu->prefix & PREFIX_REPNE)
420	PUT_SZ("repne ");
421
422	/*
423	* Adjust the format string to the correct mnemonic
424	* or to avoid things the assembler cannot handle correctly.
425	*/
426	char szTmpFmt[48];
427	const char *pszFmt = pOp->pszOpcode;
428	switch (pOp->opcode)
429	{
430	case OP_JECXZ:
431	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "jcxz %Jb" : pCpu->opmode == CPUMODE_32BIT ? "jecxz %Jb" : "jrcxz %Jb";
432	break;
433	case OP_PUSHF:
434	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "pushfw" : pCpu->opmode == CPUMODE_32BIT ? "pushfd" : "pushfq";
435	break;
436	case OP_POPF:
437	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "popfw" : pCpu->opmode == CPUMODE_32BIT ? "popfd" : "popfq";
438	break;
439	case OP_PUSHA:
440	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "pushaw" : "pushad";
441	break;
442	case OP_POPA:
443	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "popaw" : "popad";
444	break;
445	case OP_INSB:
446	pszFmt = "insb";
447	break;
448	case OP_INSWD:
449	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "insw" : pCpu->opmode == CPUMODE_32BIT ? "insd" : "insq";
450	break;
451	case OP_OUTSB:
452	pszFmt = "outsb";
453	break;
454	case OP_OUTSWD:
455	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "outsw" : pCpu->opmode == CPUMODE_32BIT ? "outsd" : "outsq";
456	break;
457	case OP_MOVSB:
458	pszFmt = "movsb";
459	break;
460	case OP_MOVSWD:
461	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "movsw" : pCpu->opmode == CPUMODE_32BIT ? "movsd" : "movsq";
462	break;
463	case OP_CMPSB:
464	pszFmt = "cmpsb";
465	break;
466	case OP_CMPWD:
467	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "cmpsw" : pCpu->opmode == CPUMODE_32BIT ? "cmpsd" : "cmpsq";
468	break;
469	case OP_SCASB:
470	pszFmt = "scasb";
471	break;
472	case OP_SCASWD:
473	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "scasw" : pCpu->opmode == CPUMODE_32BIT ? "scasd" : "scasq";
474	break;
475	case OP_LODSB:
476	pszFmt = "lodsb";
477	break;
478	case OP_LODSWD:
479	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "lodsw" : pCpu->opmode == CPUMODE_32BIT ? "lodsd" : "lodsq";
480	break;
481	case OP_STOSB:
482	pszFmt = "stosb";
483	break;
484	case OP_STOSWD:
485	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "stosw" : pCpu->opmode == CPUMODE_32BIT ? "stosd" : "stosq";
486	break;
487	case OP_CBW:
488	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "cbw" : pCpu->opmode == CPUMODE_32BIT ? "cwde" : "cdqe";
489	break;
490	case OP_CWD:
491	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "cwd" : pCpu->opmode == CPUMODE_32BIT ? "cdq" : "cqo";
492	break;
493	case OP_SHL:
494	Assert(pszFmt[3] == '/');
495	pszFmt += 4;
496	break;
497	case OP_XLAT:
498	pszFmt = "xlatb";
499	break;
500	case OP_INT3:
501	pszFmt = "int3";
502	break;
503
504	/*
505	* Don't know how to tell yasm to generate complicated nop stuff, so 'db' it.
506	*/
507	case OP_NOP:
508	if (pCpu->opcode == 0x90)
509	/* fine, fine */;
510	else if (pszFmt[sizeof("nop %Ev") - 1] == '/' && pszFmt[sizeof("nop %Ev")] == 'p')
511	pszFmt = "prefetch %Eb";
512	else if (pCpu->opcode == 0x1f)
513	{
514	Assert(pCpu->opsize >= 3);
515	PUT_SZ("db 00fh, 01fh,");
516	PUT_NUM_8(pCpu->ModRM.u);
517	for (unsigned i = 3; i < pCpu->opsize; i++)
518	{
519	PUT_C(',');
520	PUT_NUM_8(0x90); ///@todo fixme.
521	}
522	pszFmt = "";
523	}
524	break;
525
526	default:
527	/* ST(X) -> stX (floating point) */
528	if (*pszFmt == 'f' && strchr(pszFmt, '('))
529	{
530	char *pszFmtDst = szTmpFmt;
531	char ch;
532	do
533	{
534	ch = *pszFmt++;
535	if (ch == 'S' && pszFmt[0] == 'T' && pszFmt[1] == '(')
536	{
537	*pszFmtDst++ = 's';
538	*pszFmtDst++ = 't';
539	pszFmt += 2;
540	ch = *pszFmt;
541	Assert(pszFmt[1] == ')');
542	pszFmt += 2;
543	*pszFmtDst++ = ch;
544	}
545	else
546	*pszFmtDst++ = ch;
547	} while (ch != '\0');
548	pszFmt = szTmpFmt;
549	}
550	break;
551
552	/*
553	* Horrible hacks.
554	*/
555	case OP_FLD:
556	if (pCpu->opcode == 0xdb) /* m80fp workaround. */
557	(int )&pCpu->param1.param &= ~0x1f; /* make it pure OP_PARM_M */
558	break;
559	case OP_LAR: /* hack w -> v, probably not correct. */
560	(int )&pCpu->param2.param &= ~0x1f;
561	(int )&pCpu->param2.param \|= OP_PARM_v;
562	break;
563	}
564
565	/*
566	* Formatting context and associated macros.
567	*/
568	PCOP_PARAMETER pParam = &pCpu->param1;
569	int iParam = 1;
570
571	#define PUT_FAR() \
572	do { \
573	if ( OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_p \
574	&& pOp->opcode != OP_LDS /* table bugs? */ \
575	&& pOp->opcode != OP_LES \
576	&& pOp->opcode != OP_LFS \
577	&& pOp->opcode != OP_LGS \
578	&& pOp->opcode != OP_LSS ) \
579	PUT_SZ("far "); \
580	} while (0)
581	/** @todo mov ah,ch ends up with a byte 'override'... - check if this wasn't fixed. */
582	/** @todo drop the work/dword/qword override when the src/dst is a register (except for movsx/movzx). */
583	#define PUT_SIZE_OVERRIDE() \
584	do { \
585	switch (OP_PARM_VSUBTYPE(pParam->param)) \
586	{ \
587	case OP_PARM_v: \
588	switch (pCpu->opmode) \
589	{ \
590	case CPUMODE_16BIT: PUT_SZ("word "); break; \
591	case CPUMODE_32BIT: PUT_SZ("dword "); break; \
592	case CPUMODE_64BIT: PUT_SZ("qword "); break; \
593	default: break; \
594	} \
595	break; \
596	case OP_PARM_b: PUT_SZ("byte "); break; \
597	case OP_PARM_w: PUT_SZ("word "); break; \
598	case OP_PARM_d: PUT_SZ("dword "); break; \
599	case OP_PARM_q: PUT_SZ("qword "); break; \
600	case OP_PARM_dq: \
601	if (OP_PARM_VTYPE(pParam->param) != OP_PARM_W) /* these are 128 bit, pray they are all unambiguous.. */ \
602	PUT_SZ("qword "); \
603	break; \
604	case OP_PARM_p: break; /* see PUT_FAR */ \
605	case OP_PARM_s: if (pParam->flags & USE_REG_FP) PUT_SZ("tword "); break; /* ?? */ \
606	case OP_PARM_z: break; \
607	case OP_PARM_NONE: \
608	if ( OP_PARM_VTYPE(pParam->param) == OP_PARM_M \
609	&& ((pParam->flags & USE_REG_FP) \|\| pOp->opcode == OP_FLD)) \
610	PUT_SZ("tword "); \
611	break; \
612	default: break; /no pointer type specified/necessary/ \
613	} \
614	} while (0)
615	static const char s_szSegPrefix[6][4] = { "es:", "cs:", "ss:", "ds:", "fs:", "gs:" };
616	#define PUT_SEGMENT_OVERRIDE() \
617	do { \
618	if (pCpu->prefix & PREFIX_SEG) \
619	PUT_STR(s_szSegPrefix[pCpu->prefix_seg], 3); \
620	} while (0)
621
622
623	/*
624	* Segment prefixing for instructions that doesn't do memory access.
625	*/
626	if ( (pCpu->prefix & PREFIX_SEG)
627	&& !DIS_IS_EFFECTIVE_ADDR(pCpu->param1.flags)
628	&& !DIS_IS_EFFECTIVE_ADDR(pCpu->param2.flags)
629	&& !DIS_IS_EFFECTIVE_ADDR(pCpu->param3.flags))
630	{
631	PUT_STR(s_szSegPrefix[pCpu->prefix_seg], 2);
632	PUT_C(' ');
633	}
634
635
636	/*
637	* The formatting loop.
638	*/
639	RTINTPTR off;
640	char szSymbol[128];
641	char ch;
642	while ((ch = *pszFmt++) != '\0')
643	{
644	if (ch == '%')
645	{
646	ch = *pszFmt++;
647	switch (ch)
648	{
649	/*
650	* ModRM - Register only.
651	*/
652	case 'C': /* Control register (ParseModRM / UseModRM). */
653	case 'D': /* Debug register (ParseModRM / UseModRM). */
654	case 'G': /* ModRM selects general register (ParseModRM / UseModRM). */
655	case 'S': /* ModRM byte selects a segment register (ParseModRM / UseModRM). */
656	case 'T': /* ModRM byte selects a test register (ParseModRM / UseModRM). */
657	case 'V': /* ModRM byte selects an XMM/SSE register (ParseModRM / UseModRM). */
658	case 'P': /* ModRM byte selects MMX register (ParseModRM / UseModRM). */
659	{
660	pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
661	Assert(!(pParam->flags & (USE_INDEX \| USE_SCALE) /* No SIB here... */));
662	Assert(!(pParam->flags & (USE_DISPLACEMENT8 \| USE_DISPLACEMENT16 \| USE_DISPLACEMENT32 \| USE_DISPLACEMENT64 \| USE_RIPDISPLACEMENT32)));
663
664	size_t cchReg;
665	const char *pszReg = disasmFormatYasmBaseReg(pCpu, pParam, &cchReg);
666	PUT_STR(pszReg, cchReg);
667	break;
668	}
669
670	/*
671	* ModRM - Register or memory.
672	*/
673	case 'E': /* ModRM specifies parameter (ParseModRM / UseModRM / UseSIB). */
674	case 'Q': /* ModRM byte selects MMX register or memory address (ParseModRM / UseModRM). */
675	case 'R': /* ModRM byte may only refer to a general register (ParseModRM / UseModRM). */
676	case 'W': /* ModRM byte selects an XMM/SSE register or a memory address (ParseModRM / UseModRM). */
677	case 'M': /* ModRM may only refer to memory (ParseModRM / UseModRM). */
678	{
679	pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
680
681	PUT_FAR();
682	if (DIS_IS_EFFECTIVE_ADDR(pParam->flags))
683	{
684	/* Work around mov seg,[mem16] and mov [mem16],seg as these always make a 16-bit mem
685	while the register variants deals with 16, 32 & 64 in the normal fashion. */
686	if ( pParam->param != OP_PARM_Ev
687	\|\| pOp->opcode != OP_MOV
688	\|\| ( pOp->param1 != OP_PARM_Sw
689	&& pOp->param2 != OP_PARM_Sw))
690	PUT_SIZE_OVERRIDE();
691	PUT_C('[');
692	}
693	if ( (fFlags & DIS_FMT_FLAGS_STRICT)
694	&& (pParam->flags & (USE_DISPLACEMENT8 \| USE_DISPLACEMENT16 \| USE_DISPLACEMENT32 \| USE_DISPLACEMENT64 \| USE_RIPDISPLACEMENT32)))
695	{
696	if ( (pParam->flags & USE_DISPLACEMENT8)
697	&& !pParam->disp8)
698	PUT_SZ("byte ");
699	else if ( (pParam->flags & USE_DISPLACEMENT16)
700	&& (int8_t)pParam->disp16 == (int16_t)pParam->disp16)
701	PUT_SZ("word ");
702	else if ( (pParam->flags & USE_DISPLACEMENT32)
703	&& (int8_t)pParam->disp32 == (int32_t)pParam->disp32)
704	PUT_SZ("dword ");
705	}
706	if (DIS_IS_EFFECTIVE_ADDR(pParam->flags))
707	PUT_SEGMENT_OVERRIDE();
708
709	bool fBase = (pParam->flags & USE_BASE) /* When exactly is USE_BASE supposed to be set? disasmModRMReg doesn't set it. */
710	\|\| ( (pParam->flags & (USE_REG_GEN8 \| USE_REG_GEN16 \| USE_REG_GEN32 \| USE_REG_GEN64))
711	&& !DIS_IS_EFFECTIVE_ADDR(pParam->flags));
712	if (fBase)
713	{
714	size_t cchReg;
715	const char *pszReg = disasmFormatYasmBaseReg(pCpu, pParam, &cchReg);
716	PUT_STR(pszReg, cchReg);
717	}
718
719	if (pParam->flags & USE_INDEX)
720	{
721	if (fBase)
722	PUT_C('+');
723
724	size_t cchReg;
725	const char *pszReg = disasmFormatYasmIndexReg(pCpu, pParam, &cchReg);
726	PUT_STR(pszReg, cchReg);
727
728	if (pParam->flags & USE_SCALE)
729	{
730	PUT_C('*');
731	PUT_C('0' + pParam->scale);
732	}
733	}
734	else
735	Assert(!(pParam->flags & USE_SCALE));
736
737	if (pParam->flags & (USE_DISPLACEMENT8 \| USE_DISPLACEMENT16 \| USE_DISPLACEMENT32 \| USE_DISPLACEMENT64 \| USE_RIPDISPLACEMENT32))
738	{
739	Assert(!(pParam->flags & USE_DISPLACEMENT64));
740	int32_t off;
741	if (pParam->flags & USE_DISPLACEMENT8)
742	off = pParam->disp8;
743	else if (pParam->flags & USE_DISPLACEMENT16)
744	off = pParam->disp16;
745	else if (pParam->flags & (USE_DISPLACEMENT32 \| USE_RIPDISPLACEMENT32))
746	off = pParam->disp32;
747
748	if (fBase \|\| (pParam->flags & USE_INDEX))
749	{
750	PUT_C(off >= 0 ? '+' : '-');
751	if (off < 0)
752	off = -off;
753	}
754	if (pParam->flags & USE_DISPLACEMENT8)
755	PUT_NUM_8( off);
756	else if (pParam->flags & USE_DISPLACEMENT16)
757	PUT_NUM_16(off);
758	else if (pParam->flags & USE_DISPLACEMENT32)
759	PUT_NUM_32(off);
760	else
761	{
762	PUT_NUM_32(off);
763	PUT_SZ(" wrt rip"); //??
764	}
765	}
766
767	if (DIS_IS_EFFECTIVE_ADDR(pParam->flags))
768	PUT_C(']');
769	break;
770	}
771
772	case 'F': /* Eflags register (0 - popf/pushf only, avoided in adjustments above). */
773	AssertFailed();
774	break;
775
776	case 'I': /* Immediate data (ParseImmByte, ParseImmByteSX, ParseImmV, ParseImmUshort, ParseImmZ). */
777	Assert(pszFmt == 'b' \|\| pszFmt == 'v' \|\| pszFmt == 'w' \|\| pszFmt == 'z'); pszFmt++;
778	switch (pParam->flags & ( USE_IMMEDIATE8 \| USE_IMMEDIATE16 \| USE_IMMEDIATE32 \| USE_IMMEDIATE64
779	\| USE_IMMEDIATE16_SX8 \| USE_IMMEDIATE32_SX8))
780	{
781	case USE_IMMEDIATE8:
782	if ( (fFlags & DIS_FMT_FLAGS_STRICT)
783	&& ( (pOp->param1 >= OP_PARM_REG_GEN8_START && pOp->param1 <= OP_PARM_REG_GEN8_END)
784	\|\| (pOp->param2 >= OP_PARM_REG_GEN8_START && pOp->param2 <= OP_PARM_REG_GEN8_END))
785	)
786	PUT_SZ("strict byte ");
787	PUT_NUM_8(pParam->parval);
788	break;
789
790	case USE_IMMEDIATE16:
791	if ( pCpu->mode != pCpu->opmode
792	\|\| ( (fFlags & DIS_FMT_FLAGS_STRICT)
793	&& ( (int8_t)pParam->parval == (int16_t)pParam->parval
794	\|\| (pOp->param1 >= OP_PARM_REG_GEN16_START && pOp->param1 <= OP_PARM_REG_GEN16_END)
795	\|\| (pOp->param2 >= OP_PARM_REG_GEN16_START && pOp->param2 <= OP_PARM_REG_GEN16_END))
796	)
797	)
798	{
799	if (OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_b)
800	PUT_SZ_STRICT("strict byte ", "byte ");
801	else if (OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_v)
802	PUT_SZ_STRICT("strict word ", "word ");
803	}
804	PUT_NUM_16(pParam->parval);
805	break;
806
807	case USE_IMMEDIATE16_SX8:
808	PUT_SZ_STRICT("strict byte ", "byte ");
809	PUT_NUM_16(pParam->parval);
810	break;
811
812	case USE_IMMEDIATE32:
813	if ( pCpu->opmode != (pCpu->mode == CPUMODE_16BIT ? CPUMODE_16BIT : CPUMODE_32BIT) /* not perfect */
814	\|\| ( (fFlags & DIS_FMT_FLAGS_STRICT)
815	&& ( (int8_t)pParam->parval == (int32_t)pParam->parval
816	\|\| (pOp->param1 >= OP_PARM_REG_GEN32_START && pOp->param1 <= OP_PARM_REG_GEN32_END)
817	\|\| (pOp->param2 >= OP_PARM_REG_GEN32_START && pOp->param2 <= OP_PARM_REG_GEN32_END))
818	)
819	)
820	{
821	if (OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_b)
822	PUT_SZ_STRICT("strict byte ", "byte ");
823	else if (OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_v)
824	PUT_SZ_STRICT("strict dword ", "dword ");
825	}
826	PUT_NUM_32(pParam->parval);
827	break;
828
829	case USE_IMMEDIATE32_SX8:
830	PUT_SZ_STRICT("strict byte ", "byte ");
831	PUT_NUM_32(pParam->parval);
832	break;
833
834	case USE_IMMEDIATE64:
835	PUT_NUM_64(pParam->parval);
836	break;
837
838	default:
839	AssertFailed();
840	break;
841	}
842	break;
843
844	case 'J': /* Relative jump offset (ParseImmBRel + ParseImmVRel). */
845	{
846	int32_t offDisplacement;
847	Assert(iParam == 1);
848	bool fPrefix = (fFlags & DIS_FMT_FLAGS_STRICT)
849	&& pOp->opcode != OP_CALL
850	&& pOp->opcode != OP_LOOP
851	&& pOp->opcode != OP_LOOPE
852	&& pOp->opcode != OP_LOOPNE
853	&& pOp->opcode != OP_JECXZ;
854	if (pOp->opcode == OP_CALL)
855	fFlags &= ~DIS_FMT_FLAGS_RELATIVE_BRANCH;
856
857	if (pParam->flags & USE_IMMEDIATE8_REL)
858	{
859	if (fPrefix)
860	PUT_SZ("short ");
861	offDisplacement = (int8_t)pParam->parval;
862	Assert(*pszFmt == 'b'); pszFmt++;
863
864	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
865	PUT_NUM_S8(offDisplacement);
866	}
867	else if (pParam->flags & USE_IMMEDIATE16_REL)
868	{
869	if (fPrefix)
870	PUT_SZ("near ");
871	offDisplacement = (int16_t)pParam->parval;
872	Assert(*pszFmt == 'v'); pszFmt++;
873
874	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
875	PUT_NUM_S16(offDisplacement);
876	}
877	else
878	{
879	if (fPrefix)
880	PUT_SZ("near ");
881	offDisplacement = (int32_t)pParam->parval;
882	Assert(pParam->flags & USE_IMMEDIATE32_REL);
883	Assert(*pszFmt == 'v'); pszFmt++;
884
885	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
886	PUT_NUM_S32(offDisplacement);
887	}
888	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
889	PUT_SZ(" (");
890
891	RTUINTPTR uTrgAddr = pCpu->opaddr + pCpu->opsize + offDisplacement;
892	if (pCpu->mode == CPUMODE_16BIT)
893	PUT_NUM_16(uTrgAddr);
894	else if (pCpu->mode == CPUMODE_32BIT)
895	PUT_NUM_32(uTrgAddr);
896	else
897	PUT_NUM_64(uTrgAddr);
898
899	if (pfnGetSymbol)
900	{
901	int rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(USE_REG_CS), uTrgAddr, szSymbol, sizeof(szSymbol), &off, pvUser);
902	if (RT_SUCCESS(rc))
903	{
904	PUT_SZ(" [");
905	PUT_PSZ(szSymbol);
906	if (off != 0)
907	{
908	if ((int8_t)off == off)
909	PUT_NUM_S8(off);
910	else if ((int16_t)off == off)
911	PUT_NUM_S16(off);
912	else if ((int32_t)off == off)
913	PUT_NUM_S32(off);
914	else
915	PUT_NUM_S64(off);
916	}
917	PUT_C(']');
918	}
919	}
920
921	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
922	PUT_C(')');
923	break;
924	}
925
926	case 'A': /* Direct (jump/call) address (ParseImmAddr). */
927	{
928	Assert(*pszFmt == 'p'); pszFmt++;
929	PUT_FAR();
930	PUT_SIZE_OVERRIDE();
931	PUT_SEGMENT_OVERRIDE();
932	int rc;
933	switch (pParam->flags & (USE_IMMEDIATE_ADDR_16_16 \| USE_IMMEDIATE_ADDR_16_32 \| USE_DISPLACEMENT64 \| USE_DISPLACEMENT32 \| USE_DISPLACEMENT16))
934	{
935	case USE_IMMEDIATE_ADDR_16_16:
936	PUT_NUM_16(pParam->parval >> 16);
937	PUT_C(':');
938	PUT_NUM_16(pParam->parval);
939	if (pfnGetSymbol)
940	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_VALUE(pParam->parval >> 16), (uint16_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
941	break;
942	case USE_IMMEDIATE_ADDR_16_32:
943	PUT_NUM_16(pParam->parval >> 32);
944	PUT_C(':');
945	PUT_NUM_32(pParam->parval);
946	if (pfnGetSymbol)
947	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_VALUE(pParam->parval >> 16), (uint32_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
948	break;
949	case USE_DISPLACEMENT16:
950	PUT_NUM_16(pParam->parval);
951	if (pfnGetSymbol)
952	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(USE_REG_CS), (uint16_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
953	break;
954	case USE_DISPLACEMENT32:
955	PUT_NUM_32(pParam->parval);
956	if (pfnGetSymbol)
957	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(USE_REG_CS), (uint32_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
958	break;
959	case USE_DISPLACEMENT64:
960	PUT_NUM_64(pParam->parval);
961	if (pfnGetSymbol)
962	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(USE_REG_CS), (uint64_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
963	break;
964	default:
965	AssertFailed();
966	break;
967	}
968
969	if (pfnGetSymbol && RT_SUCCESS(rc))
970	{
971	PUT_SZ(" [");
972	PUT_PSZ(szSymbol);
973	if (off != 0)
974	{
975	if ((int8_t)off == off)
976	PUT_NUM_S8(off);
977	else if ((int16_t)off == off)
978	PUT_NUM_S16(off);
979	else if ((int32_t)off == off)
980	PUT_NUM_S32(off);
981	else
982	PUT_NUM_S64(off);
983	}
984	PUT_C(']');
985	}
986	break;
987	}
988
989	case 'O': /* No ModRM byte (ParseImmAddr). */
990	{
991	Assert(pszFmt == 'b' \|\| pszFmt == 'v'); pszFmt++;
992	PUT_FAR();
993	PUT_SIZE_OVERRIDE();
994	PUT_C('[');
995	PUT_SEGMENT_OVERRIDE();
996	int rc;
997	switch (pParam->flags & (USE_IMMEDIATE_ADDR_16_16 \| USE_IMMEDIATE_ADDR_16_32 \| USE_DISPLACEMENT64 \| USE_DISPLACEMENT32 \| USE_DISPLACEMENT16))
998	{
999	case USE_IMMEDIATE_ADDR_16_16:
1000	PUT_NUM_16(pParam->parval >> 16);
1001	PUT_C(':');
1002	PUT_NUM_16(pParam->parval);
1003	if (pfnGetSymbol)
1004	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_VALUE(pParam->parval >> 16), (uint16_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
1005	break;
1006	case USE_IMMEDIATE_ADDR_16_32:
1007	PUT_NUM_16(pParam->parval >> 32);
1008	PUT_C(':');
1009	PUT_NUM_32(pParam->parval);
1010	if (pfnGetSymbol)
1011	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_VALUE(pParam->parval >> 16), (uint32_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
1012	break;
1013	case USE_DISPLACEMENT16:
1014	PUT_NUM_16(pParam->disp16);
1015	if (pfnGetSymbol)
1016	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(USE_REG_CS), (uint16_t)pParam->disp16, szSymbol, sizeof(szSymbol), &off, pvUser);
1017	break;
1018	case USE_DISPLACEMENT32:
1019	PUT_NUM_32(pParam->disp32);
1020	if (pfnGetSymbol)
1021	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(USE_REG_CS), (uint32_t)pParam->disp32, szSymbol, sizeof(szSymbol), &off, pvUser);
1022	break;
1023	case USE_DISPLACEMENT64:
1024	PUT_NUM_64(pParam->disp64);
1025	if (pfnGetSymbol)
1026	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(USE_REG_CS), (uint64_t)pParam->disp64, szSymbol, sizeof(szSymbol), &off, pvUser);
1027	break;
1028	default:
1029	AssertFailed();
1030	break;
1031	}
1032	PUT_C(']');
1033
1034	if (pfnGetSymbol && RT_SUCCESS(rc))
1035	{
1036	PUT_SZ(" (");
1037	PUT_PSZ(szSymbol);
1038	if (off != 0)
1039	{
1040	if ((int8_t)off == off)
1041	PUT_NUM_S8(off);
1042	else if ((int16_t)off == off)
1043	PUT_NUM_S16(off);
1044	else if ((int32_t)off == off)
1045	PUT_NUM_S32(off);
1046	else
1047	PUT_NUM_S64(off);
1048	}
1049	PUT_C(')');
1050	}
1051	break;
1052	}
1053
1054	case 'X': /* DS:SI (ParseXb, ParseXv). */
1055	case 'Y': /* ES:DI (ParseYb, ParseYv). */
1056	{
1057	Assert(pszFmt == 'b' \|\| pszFmt == 'v'); pszFmt++;
1058	PUT_FAR();
1059	PUT_SIZE_OVERRIDE();
1060	PUT_C('[');
1061	if (pParam->flags & USE_POINTER_DS_BASED)
1062	PUT_SZ("ds:");
1063	else
1064	PUT_SZ("es:");
1065
1066	size_t cchReg;
1067	const char *pszReg = disasmFormatYasmBaseReg(pCpu, pParam, &cchReg);
1068	PUT_STR(pszReg, cchReg);
1069	PUT_C(']');
1070	break;
1071	}
1072
1073	case 'e': /* Register based on operand size (e.g. %eAX) (ParseFixedReg). */
1074	{
1075	Assert(RT_C_IS_ALPHA(pszFmt[0]) && RT_C_IS_ALPHA(pszFmt[1]) && !RT_C_IS_ALPHA(pszFmt[2])); pszFmt += 2;
1076	size_t cchReg;
1077	const char *pszReg = disasmFormatYasmBaseReg(pCpu, pParam, &cchReg);
1078	PUT_STR(pszReg, cchReg);
1079	break;
1080	}
1081
1082	default:
1083	AssertMsgFailed(("%c%s!\n", ch, pszFmt));
1084	break;
1085	}
1086	AssertMsg(pszFmt == ',' \|\| pszFmt == '\0', ("%c%s\n", ch, pszFmt));
1087	}
1088	else
1089	{
1090	PUT_C(ch);
1091	if (ch == ',')
1092	{
1093	Assert(*pszFmt != ' ');
1094	PUT_C(' ');
1095	switch (++iParam)
1096	{
1097	case 2: pParam = &pCpu->param2; break;
1098	case 3: pParam = &pCpu->param3; break;
1099	default: pParam = NULL; break;
1100	}
1101	}
1102	}
1103	} /* while more to format */
1104	}
1105
1106	/*
1107	* Any additional output to the right of the instruction?
1108	*/
1109	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
1110	{
1111	/* some up front padding. */
1112	size_t cchPadding = cchOutput - offInstruction;
1113	cchPadding = cchPadding + 1 >= 42 ? 1 : 42 - cchPadding;
1114	PUT_STR(g_szSpaces, cchPadding);
1115
1116	/* comment? */
1117	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
1118	PUT_SZ(";");
1119
1120	/*
1121	* The address?
1122	*/
1123	if (fFlags & DIS_FMT_FLAGS_ADDR_RIGHT)
1124	{
1125	PUT_C(' ');
1126	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
1127	if (pCpu->opaddr >= _4G)
1128	PUT_NUM(9, "%08x`", (uint32_t)(pCpu->opaddr >> 32));
1129	#endif
1130	PUT_NUM(8, "%08x", (uint32_t)pCpu->opaddr);
1131	}
1132
1133	/*
1134	* Opcode bytes?
1135	*/
1136	if (fFlags & DIS_FMT_FLAGS_BYTES_RIGHT)
1137	{
1138	PUT_C(' ');
1139	size_t cchTmp = disFormatBytes(pCpu, pszDst, cchDst, fFlags);
1140	cchOutput += cchTmp;
1141	if (cchTmp >= cchDst)
1142	cchTmp = cchDst - (cchDst != 0);
1143	cchDst -= cchTmp;
1144	pszDst += cchTmp;
1145	}
1146	}
1147
1148	/*
1149	* Terminate it - on overflow we'll have reserved one byte for this.
1150	*/
1151	if (cchDst > 0)
1152	*pszDst = '\0';
1153	else
1154	Assert(!cchBuf);
1155
1156	/* clean up macros */
1157	#undef PUT_PSZ
1158	#undef PUT_SZ
1159	#undef PUT_STR
1160	#undef PUT_C
1161	return cchOutput;
1162	}
1163
1164
1165	/**
1166	* Formats the current instruction in Yasm (/ Nasm) style.
1167	*
1168	* This is a simplified version of DISFormatYasmEx() provided for your convenience.
1169	*
1170	*
1171	* @returns The number of output characters. If this is >= cchBuf, then the content
1172	* of pszBuf will be truncated.
1173	* @param pCpu Pointer to the disassembler CPU state.
1174	* @param pszBuf The output buffer.
1175	* @param cchBuf The size of the output buffer.
1176	*/
1177	DISDECL(size_t) DISFormatYasm(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf)
1178	{
1179	return DISFormatYasmEx(pCpu, pszBuf, cchBuf, 0 /* fFlags /, NULL / pfnGetSymbol /, NULL / pvUser */);
1180	}
1181

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source: vbox/trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp@ 9642

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