VirtualBox

source: vbox/trunk/src/VBox/Disassembler/DisasmInternal-armv8.h@ 106782

Last change on this file since 106782 was 106770, checked in by vboxsync, 3 months ago

Disassembler: Decode load/store memory tags instructions, bugref:10394
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File size: 10.8 KB
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1/* $Id: DisasmInternal-armv8.h 106770 2024-10-29 13:09:50Z vboxsync $ */
2/** @file
3 * VBox disassembler - Internal header.
4 */
5
6/*
7 * Copyright (C) 2023-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VBOX_INCLUDED_SRC_DisasmInternal_armv8_h
29#define VBOX_INCLUDED_SRC_DisasmInternal_armv8_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <VBox/types.h>
35#include <VBox/err.h>
36#include <VBox/dis.h>
37#include <VBox/log.h>
38
39#include <iprt/param.h>
40#include "DisasmInternal.h"
41
42
43/** @addtogroup grp_dis_int Internals.
44 * @ingroup grp_dis
45 * @{
46 */
47
48/** @name Index into g_apfnFullDisasm.
49 * @{ */
50typedef enum DISPARMPARSEIDX
51{
52 kDisParmParseNop = 0,
53 kDisParmParseSize,
54 kDisParmParseImm,
55 kDisParmParseImmRel,
56 kDisParmParseImmAdr,
57 kDisParmParseImmZero,
58 kDisParmParseGprZr,
59 kDisParmParseGprZr32,
60 kDisParmParseGprZr64,
61 kDisParmParseGprSp,
62 kDisParmParseGprOff,
63 kDisParmParseAddrGprSp,
64 kDisParmParseRegFixed31,
65 kDisParmParseImmsImmrN,
66 kDisParmParseHw,
67 kDisParmParseCond,
68 kDisParmParsePState,
69 kDisParmParseCRnCRm,
70 kDisParmParseSysReg,
71 kDisParmParseSh12,
72 kDisParmParseImmTbz,
73 kDisParmParseShift,
74 kDisParmParseShiftAmount,
75 kDisParmParseImmMemOff,
76 kDisParmParseSImmMemOff,
77 kDisParmParseSImmMemOffUnscaled,
78 kDisParmParseOption,
79 kDisParmParseS,
80 kDisParmParseSetPreIndexed,
81 kDisParmParseSetPostIndexed,
82 kDisParmParseFpType,
83 kDisParmParseFpReg,
84 kDisParmParseFpScale,
85 kDisParmParseFpFixupFCvt,
86 kDisParmParseSimdRegSize,
87 kDisParmParseSimdRegSize32,
88 kDisParmParseSimdRegSize64,
89 kDisParmParseSimdRegSize128,
90 kDisParmParseSimdRegScalar,
91 kDisParmParseImmHImmB,
92 kDisParmParseSf,
93 kDisParmParseImmX16,
94 kDisParmParseSImmTags,
95 kDisParmParseLdrPacImm,
96 kDisParmParseLdrPacW,
97 kDisParmParseMax
98} DISPARMPARSEIDX;
99/** @} */
100
101
102/**
103 * Decoder step.
104 */
105typedef struct DISARMV8INSNPARAM
106{
107 /** The parser to use for the decode step. */
108 DISPARMPARSEIDX idxParse;
109 /** Bit index at which the field starts. */
110 uint8_t idxBitStart;
111 /** Size of the bit field. */
112 uint8_t cBits;
113 /** The parameter this decoder param contributes to. */
114 uint8_t idxParam;
115} DISARMV8INSNPARAM;
116typedef DISARMV8INSNPARAM *PDISARMV8INSNPARAM;
117typedef const DISARMV8INSNPARAM *PCDISARMV8INSNPARAM;
118
119#define DIS_ARMV8_INSN_DECODE_TERM { kDisParmParseNop, 0, 0, DIS_ARMV8_INSN_PARAM_UNSET }
120#define DIS_ARMV8_INSN_DECODE(a_idxParse, a_idxBitStart, a_cBits, a_idxParam) \
121 { a_idxParse, a_idxBitStart, a_cBits, a_idxParam }
122
123#define DIS_ARMV8_INSN_PARAM_UNSET UINT8_MAX
124
125
126/**
127 * Opcode structure.
128 */
129typedef struct DISARMV8OPCODE
130{
131 /** The value of the fixed bits of the instruction. */
132 uint32_t fValue;
133 /** Special flags for the opcode. */
134 uint32_t fFlags;
135 /** Pointer to an alternative decoder overriding the default one for the instruction class. */
136 PCDISARMV8INSNPARAM paDecode;
137 /** The generic opcode structure. */
138 DISOPCODE Opc;
139} DISARMV8OPCODE;
140/** Pointer to a const opcode. */
141typedef const DISARMV8OPCODE *PCDISARMV8OPCODE;
142
143
144/**
145 * Opcode decode index.
146 */
147typedef enum DISARMV8OPCDECODE
148{
149 kDisArmV8OpcDecodeNop = 0,
150 kDisArmV8OpcDecodeLookup,
151 kDisArmV8OpcDecodeCollate,
152 kDisArmV8OpcDecodeMax
153} DISARMV8OPCDECODE;
154
155
156/**
157 * Decoder stage type.
158 */
159typedef enum kDisArmV8DecodeType
160{
161 kDisArmV8DecodeType_Invalid = 0,
162 kDisArmV8DecodeType_Map,
163 kDisArmV8DecodeType_Table,
164 kDisArmV8DecodeType_InsnClass,
165 kDisArmV8DecodeType_32Bit_Hack = 0x7fffffff
166} kDisArmV8DecodeType;
167
168
169/**
170 * Decode header.
171 */
172typedef struct DISARMV8DECODEHDR
173{
174 /** Next stage decoding type. */
175 kDisArmV8DecodeType enmDecodeType;
176 /** Number of entries in the next decoder stage or
177 * opcodes in the instruction class. */
178 uint32_t cDecode;
179} DISARMV8DECODEHDR;
180/** Pointer to a decode header. */
181typedef DISARMV8DECODEHDR *PDISARMV8DECODEHDR;
182/** Pointer to a const decode header. */
183typedef const DISARMV8DECODEHDR *PCDISARMV8DECODEHDR;
184typedef const PCDISARMV8DECODEHDR *PPCDISARMV8DECODEHDR;
185
186
187/**
188 * Instruction class descriptor.
189 */
190typedef struct DISARMV8INSNCLASS
191{
192 /** Decoder header. */
193 DISARMV8DECODEHDR Hdr;
194 /** Pointer to the arry of opcodes. */
195 PCDISARMV8OPCODE paOpcodes;
196 /** The mask of fixed instruction bits. */
197 uint32_t fFixedInsn;
198 /** Opcode decoder function. */
199 DISARMV8OPCDECODE enmOpcDecode;
200 /** The mask of the bits relevant for decoding. */
201 uint32_t fMask;
202 /** Number of bits to shift to get an index. */
203 uint32_t cShift;
204 /** The array of decoding steps. */
205 PCDISARMV8INSNPARAM paParms;
206} DISARMV8INSNCLASS;
207/** Pointer to a constant instruction class descriptor. */
208typedef const DISARMV8INSNCLASS *PCDISARMV8INSNCLASS;
209
210/** The N bit in an N:ImmR:ImmS bit vector must be 1 for 64-bit instruction variants. */
211#define DISARMV8INSNCLASS_F_N_FORCED_1_ON_64BIT RT_BIT_32(1)
212/** The instruction class is using the 64-bit register encoding only. */
213#define DISARMV8INSNCLASS_F_FORCED_64BIT RT_BIT_32(2)
214/** The instruction class is using the 32-bit register encoding only. */
215#define DISARMV8INSNCLASS_F_FORCED_32BIT RT_BIT_32(3)
216
217
218#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(a_Name) \
219 static const DISARMV8INSNPARAM g_aArmV8A64Insn ## a_Name ## Decode[] = {
220#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(a_Name) \
221 DIS_ARMV8_INSN_DECODE_TERM \
222 }; \
223 static const DISARMV8INSNPARAM g_aArmV8A64Insn ## a_Name ## Decode[] = {
224#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(a_Name) \
225 DIS_ARMV8_INSN_DECODE_TERM \
226 }; \
227 static const DISARMV8OPCODE g_aArmV8A64Insn ## a_Name ## Opcodes[] = {
228#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(a_Name, a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift) \
229 }; \
230 static const DISARMV8INSNCLASS g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_InsnClass, \
231 RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## Opcodes) }, \
232 & g_aArmV8A64Insn ## a_Name ## Opcodes[0], \
233 a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift, \
234 & g_aArmV8A64Insn ## a_Name ## Decode[0] }
235
236/**
237 * Decoder lookup table entry.
238 */
239typedef struct DISARMV8DECODETBLENTRY
240{
241 /** The mask to apply to the instruction. */
242 uint32_t fMask;
243 /** The value the masked instruction must match for the entry to match. */
244 uint32_t fValue;
245 /** The next stage followed when there is a match. */
246 PCDISARMV8DECODEHDR pHdrNext;
247} DISARMV8DECODETBLENTRY;
248typedef struct DISARMV8DECODETBLENTRY *PDISARMV8DECODETBLENTRY;
249typedef const DISARMV8DECODETBLENTRY *PCDISARMV8DECODETBLENTRY;
250
251
252#define DIS_ARMV8_DECODE_TBL_ENTRY_INIT(a_fMask, a_fValue, a_pNext) \
253 { a_fMask, a_fValue, & g_aArmV8A64Insn ## a_pNext.Hdr }
254
255
256/**
257 * Decoder lookup table using masks and values.
258 */
259typedef struct DISARMV8DECODETBL
260{
261 /** The header for the decoder lookup table. */
262 DISARMV8DECODEHDR Hdr;
263 /** Pointer to the individual entries. */
264 PCDISARMV8DECODETBLENTRY paEntries;
265} DISARMV8DECODETBL;
266/** Pointer to a const decode table. */
267typedef const struct DISARMV8DECODETBL *PCDISARMV8DECODETBL;
268
269
270#define DIS_ARMV8_DECODE_TBL_DEFINE_BEGIN(a_Name) \
271 static const DISARMV8DECODETBLENTRY g_aArmV8A64Insn ## a_Name ## TblEnt[] = {
272
273#define DIS_ARMV8_DECODE_TBL_DEFINE_END(a_Name) \
274 }; \
275 static const DISARMV8DECODETBL g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Table, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## TblEnt) }, \
276 & g_aArmV8A64Insn ## a_Name ## TblEnt[0] }
277
278
279/**
280 * Decoder map when direct indexing is possible.
281 */
282typedef struct DISARMV8DECODEMAP
283{
284 /** The header for the decoder map. */
285 DISARMV8DECODEHDR Hdr;
286 /** The bitmask used to decide where to go next. */
287 uint32_t fMask;
288 /** Amount to shift to get at the index. */
289 uint32_t cShift;
290 /** Pointer to the array of pointers to the next stage to index into. */
291 PPCDISARMV8DECODEHDR papNext;
292} DISARMV8DECODEMAP;
293/** Pointer to a const decode map. */
294typedef const struct DISARMV8DECODEMAP *PCDISARMV8DECODEMAP;
295
296#define DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(a_Name) \
297 static const PCDISARMV8DECODEHDR g_aArmV8A64Insn ## a_Name ## MapHdrs[] = {
298
299#define DIS_ARMV8_DECODE_MAP_DEFINE_END(a_Name, a_fMask, a_cShift) \
300 }; \
301 static const DISARMV8DECODEMAP g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
302 a_fMask, a_cShift, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
303
304#define DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(a_Name, a_idxBit) \
305 }; \
306 static const DISARMV8DECODEMAP g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
307 RT_BIT_32(a_idxBit), a_idxBit, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
308
309
310#define DIS_ARMV8_DECODE_MAP_DEFINE_END_NON_STATIC(a_Name, a_fMask, a_cShift) \
311 }; \
312 DECL_HIDDEN_CONST(DISARMV8DECODEMAP) g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
313 a_fMask, a_cShift, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
314
315#define DIS_ARMV8_DECODE_MAP_INVALID_ENTRY NULL
316#define DIS_ARMV8_DECODE_MAP_ENTRY(a_Next) & g_aArmV8A64Insn ## a_Next.Hdr
317
318
319/** @name Decoder maps.
320 * @{ */
321extern DECL_HIDDEN_DATA(DISOPCODE) g_ArmV8A64InvalidOpcode[1];
322
323extern DECL_HIDDEN_DATA(DISARMV8DECODEMAP) g_aArmV8A64InsnDecodeL0;
324/** @} */
325
326
327/** @} */
328#endif /* !VBOX_INCLUDED_SRC_DisasmInternal_armv8_h */
329
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