VirtualBox

source: vbox/trunk/src/VBox/Disassembler/DisasmInternal-armv8.h@ 105806

Last change on this file since 105806 was 105806, checked in by vboxsync, 5 months ago

Disassembler/ARMv8: Rework the disassembler tables to allow for an arbitrary number of decode steps and make the tables a bit more compact, bugref:10394
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File size: 11.4 KB
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1/* $Id: DisasmInternal-armv8.h 105806 2024-08-22 07:36:59Z vboxsync $ */
2/** @file
3 * VBox disassembler - Internal header.
4 */
5
6/*
7 * Copyright (C) 2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VBOX_INCLUDED_SRC_DisasmInternal_armv8_h
29#define VBOX_INCLUDED_SRC_DisasmInternal_armv8_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <VBox/types.h>
35#include <VBox/err.h>
36#include <VBox/dis.h>
37#include <VBox/log.h>
38
39#include <iprt/param.h>
40#include "DisasmInternal.h"
41
42
43/** @addtogroup grp_dis_int Internals.
44 * @ingroup grp_dis
45 * @{
46 */
47
48/** @name Index into g_apfnFullDisasm.
49 * @{ */
50typedef enum DISPARMPARSEIDX
51{
52 kDisParmParseNop = 0,
53 kDisParmParseIs32Bit,
54 kDisParmParseImm,
55 kDisParmParseImmRel,
56 kDisParmParseImmAdr,
57 kDisParmParseReg,
58 kDisParmParseImmsImmrN,
59 kDisParmParseHw,
60 kDisParmParseCond,
61 kDisParmParsePState,
62 kDisParmParseCRnCRm,
63 kDisParmParseSysReg,
64 kDisParmParseSh12,
65 kDisParmParseImmTbz,
66 kDisParmParseShift,
67 kDisParmParseShiftAmount,
68 kDisParmParseImmMemOff,
69 kDisParmParseMax
70} DISPARMPARSEIDX;
71/** @} */
72
73
74/**
75 * Opcode structure.
76 */
77typedef struct DISARMV8OPCODE
78{
79 /** The value of masked bits of the isntruction. */
80 uint32_t fValue;
81 /** The generic opcode structure. */
82 DISOPCODE Opc;
83} DISARMV8OPCODE;
84/** Pointer to a const opcode. */
85typedef const DISARMV8OPCODE *PCDISARMV8OPCODE;
86
87
88typedef struct DISARMV8INSNPARAM
89{
90 /** The parser to use for the decode step. */
91 DISPARMPARSEIDX idxParse;
92 /** Bit index at which the field starts. */
93 uint8_t idxBitStart;
94 /** Size of the bit field. */
95 uint8_t cBits;
96 /** The parameter this decoder param contributes to. */
97 uint8_t idxParam;
98} DISARMV8INSNPARAM;
99typedef DISARMV8INSNPARAM *PDISARMV8INSNPARAM;
100typedef const DISARMV8INSNPARAM *PCDISARMV8INSNPARAM;
101
102#define DIS_ARMV8_INSN_PARAM_NONE { kDisParmParseNop, 0, 0, DIS_ARMV8_INSN_PARAM_UNSET }
103#define DIS_ARMV8_INSN_PARAM_CREATE(a_idxParse, a_idxBitStart, a_cBits, a_idxParam) \
104 { a_idxParse, a_idxBitStart, a_cBits, a_idxParam }
105
106#define DIS_ARMV8_INSN_PARAM_UNSET UINT8_MAX
107
108/**
109 * Opcode decode index.
110 */
111typedef enum DISARMV8OPCDECODE
112{
113 kDisArmV8OpcDecodeNop = 0,
114 kDisArmV8OpcDecodeLookup,
115 kDisArmV8OpcDecodeMax
116} DISARMV8OPCDECODE;
117
118
119/**
120 * Decoder stage type.
121 */
122typedef enum kDisArmV8DecodeType
123{
124 kDisArmV8DecodeType_Invalid = 0,
125 kDisArmV8DecodeType_Map,
126 kDisArmV8DecodeType_Table,
127 kDisArmV8DecodeType_InsnClass,
128 kDisArmV8DecodeType_32Bit_Hack = 0x7fffffff
129} kDisArmV8DecodeType;
130
131
132/**
133 * Decode header.
134 */
135typedef struct DISARMV8DECODEHDR
136{
137 /** Next stage decoding type. */
138 kDisArmV8DecodeType enmDecodeType;
139 /** Number of entries in the next decoder stage or
140 * opcodes in the instruction class. */
141 uint32_t cDecode;
142} DISARMV8DECODEHDR;
143/** Pointer to a decode header. */
144typedef DISARMV8DECODEHDR *PDISARMV8DECODEHDR;
145/** Pointer to a const decode header. */
146typedef const DISARMV8DECODEHDR *PCDISARMV8DECODEHDR;
147typedef const PCDISARMV8DECODEHDR *PPCDISARMV8DECODEHDR;
148
149
150/**
151 * Instruction class descriptor.
152 */
153typedef struct DISARMV8INSNCLASS
154{
155 /** Decoder header. */
156 DISARMV8DECODEHDR Hdr;
157 /** Pointer to the arry of opcodes. */
158 PCDISARMV8OPCODE paOpcodes;
159 /** The mask of fixed instruction bits. */
160 uint32_t fFixedInsn;
161 /** Some flags for this instruction class. */
162 uint32_t fClass;
163 /** Opcode decoder function. */
164 DISARMV8OPCDECODE enmOpcDecode;
165 /** The mask of the bits relevant for decoding. */
166 uint32_t fMask;
167 /** Number of bits to shift to get an index. */
168 uint32_t cShift;
169 /** Parameter types. */
170 DISARMV8OPPARM aenmParamTypes[4];
171 /** The array of decoding steps. */
172 PCDISARMV8INSNPARAM paParms;
173} DISARMV8INSNCLASS;
174/** Pointer to a constant instruction class descriptor. */
175typedef const DISARMV8INSNCLASS *PCDISARMV8INSNCLASS;
176
177/** The instruction class distinguishes between a 32-bit and 64-bit variant using the sf bit (bit 31). */
178#define DISARMV8INSNCLASS_F_SF RT_BIT_32(0)
179/** The N bit in an N:ImmR:ImmS bit vector must be 1 for 64-bit instruction variants. */
180#define DISARMV8INSNCLASS_F_N_FORCED_1_ON_64BIT RT_BIT_32(1)
181/** The instruction class is using the 64-bit register encoding only. */
182#define DISARMV8INSNCLASS_F_FORCED_64BIT RT_BIT_32(2)
183
184
185#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(a_Name) \
186 static const DISARMV8OPCODE g_aArmV8A64Insn ## a_Name ## Opcodes[] = {
187#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(a_Name) \
188 }; \
189 static const DISARMV8INSNPARAM g_aArmV8A64Insn ## a_Name ## Decode[] = {
190#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_4(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
191 a_enmParamType1, a_enmParamType2, a_enmParamType3, a_enmParamType4) \
192 DIS_ARMV8_INSN_PARAM_NONE \
193 }; \
194 static const DISARMV8INSNCLASS g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_InsnClass, \
195 RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## Opcodes) }, \
196 & g_aArmV8A64Insn ## a_Name ## Opcodes[0], \
197 a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
198 { a_enmParamType1, a_enmParamType2, a_enmParamType3, a_enmParamType4 }, \
199 & g_aArmV8A64Insn ## a_Name ## Decode[0] };
200#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
201 a_enmParamType1, a_enmParamType2, a_enmParamType3) \
202 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_4(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
203 a_enmParamType1, a_enmParamType2, a_enmParamType3, kDisArmv8OpParmNone)
204#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
205 a_enmParamType1, a_enmParamType2) \
206 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
207 a_enmParamType1, a_enmParamType2, kDisArmv8OpParmNone)
208#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
209 a_enmParamType1) \
210 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
211 a_enmParamType1, kDisArmv8OpParmNone)
212#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_0(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift) \
213 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
214 kDisArmv8OpParmNone)
215
216#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END \
217 DIS_ARMV8_INSN_PARAM_NONE }
218
219/**
220 * Decoder lookup table entry.
221 */
222typedef struct DISARMV8DECODETBLENTRY
223{
224 /** The mask to apply to the instruction. */
225 uint32_t fMask;
226 /** The value the masked instruction must match for the entry to match. */
227 uint32_t fValue;
228 /** The next stage followed when there is a match. */
229 PCDISARMV8DECODEHDR pHdrNext;
230} DISARMV8DECODETBLENTRY;
231typedef struct DISARMV8DECODETBLENTRY *PDISARMV8DECODETBLENTRY;
232typedef const DISARMV8DECODETBLENTRY *PCDISARMV8DECODETBLENTRY;
233
234
235#define DIS_ARMV8_DECODE_TBL_ENTRY_INIT(a_fMask, a_fValue, a_pNext) \
236 { a_fMask, a_fValue, & g_aArmV8A64Insn ## a_pNext.Hdr }
237
238
239/**
240 * Decoder lookup table using masks and values.
241 */
242typedef struct DISARMV8DECODETBL
243{
244 /** The header for the decoder lookup table. */
245 DISARMV8DECODEHDR Hdr;
246 /** Pointer to the individual entries. */
247 PCDISARMV8DECODETBLENTRY paEntries;
248} DISARMV8DECODETBL;
249/** Pointer to a const decode table. */
250typedef const struct DISARMV8DECODETBL *PCDISARMV8DECODETBL;
251
252
253#define DIS_ARMV8_DECODE_TBL_DEFINE_BEGIN(a_Name) \
254 static const DISARMV8DECODETBLENTRY g_aArmV8A64Insn ## a_Name ## TblEnt[] = {
255
256#define DIS_ARMV8_DECODE_TBL_DEFINE_END(a_Name) \
257 }; \
258 static const DISARMV8DECODETBL g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Table, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## TblEnt) }, \
259 & g_aArmV8A64Insn ## a_Name ## TblEnt[0] }
260
261
262/**
263 * Decoder map when direct indexing is possible.
264 */
265typedef struct DISARMV8DECODEMAP
266{
267 /** The header for the decoder map. */
268 DISARMV8DECODEHDR Hdr;
269 /** The bitmask used to decide where to go next. */
270 uint32_t fMask;
271 /** Amount to shift to get at the index. */
272 uint32_t cShift;
273 /** Pointer to the array of pointers to the next stage to index into. */
274 PPCDISARMV8DECODEHDR papNext;
275} DISARMV8DECODEMAP;
276/** Pointer to a const decode map. */
277typedef const struct DISARMV8DECODEMAP *PCDISARMV8DECODEMAP;
278
279#define DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(a_Name) \
280 static const PCDISARMV8DECODEHDR g_aArmV8A64Insn ## a_Name ## MapHdrs[] = {
281
282#define DIS_ARMV8_DECODE_MAP_DEFINE_END(a_Name, a_fMask, a_cShift) \
283 }; \
284 static const DISARMV8DECODEMAP g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
285 a_fMask, a_cShift, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
286
287#define DIS_ARMV8_DECODE_MAP_DEFINE_END_NON_STATIC(a_Name, a_fMask, a_cShift) \
288 }; \
289 DECL_HIDDEN_CONST(DISARMV8DECODEMAP) g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
290 a_fMask, a_cShift, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
291
292#define DIS_ARMV8_DECODE_MAP_INVALID_ENTRY NULL
293#define DIS_ARMV8_DECODE_MAP_ENTRY(a_Next) & g_aArmV8A64Insn ## a_Next.Hdr
294
295
296/** @name Decoder maps.
297 * @{ */
298extern DECL_HIDDEN_DATA(DISOPCODE) g_ArmV8A64InvalidOpcode[1];
299
300extern DECL_HIDDEN_DATA(DISARMV8DECODEMAP) g_aArmV8A64InsnDecodeL0;
301/** @} */
302
303
304/** @} */
305#endif /* !VBOX_INCLUDED_SRC_DisasmInternal_armv8_h */
306
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