VirtualBox

source: vbox/trunk/src/VBox/Disassembler/DisasmInternal-armv8.h@ 105815

Last change on this file since 105815 was 105815, checked in by vboxsync, 5 months ago

Disassembler/ARMv8: Started decoding more ldr/str instruction variants, bugref:10394

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File size: 11.5 KB
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1/* $Id: DisasmInternal-armv8.h 105815 2024-08-22 12:25:28Z vboxsync $ */
2/** @file
3 * VBox disassembler - Internal header.
4 */
5
6/*
7 * Copyright (C) 2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VBOX_INCLUDED_SRC_DisasmInternal_armv8_h
29#define VBOX_INCLUDED_SRC_DisasmInternal_armv8_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <VBox/types.h>
35#include <VBox/err.h>
36#include <VBox/dis.h>
37#include <VBox/log.h>
38
39#include <iprt/param.h>
40#include "DisasmInternal.h"
41
42
43/** @addtogroup grp_dis_int Internals.
44 * @ingroup grp_dis
45 * @{
46 */
47
48/** @name Index into g_apfnFullDisasm.
49 * @{ */
50typedef enum DISPARMPARSEIDX
51{
52 kDisParmParseNop = 0,
53 kDisParmParseSize,
54 kDisParmParseImm,
55 kDisParmParseImmRel,
56 kDisParmParseImmAdr,
57 kDisParmParseReg,
58 kDisParmParseImmsImmrN,
59 kDisParmParseHw,
60 kDisParmParseCond,
61 kDisParmParsePState,
62 kDisParmParseCRnCRm,
63 kDisParmParseSysReg,
64 kDisParmParseSh12,
65 kDisParmParseImmTbz,
66 kDisParmParseShift,
67 kDisParmParseShiftAmount,
68 kDisParmParseImmMemOff,
69 kDisParmParseMax
70} DISPARMPARSEIDX;
71/** @} */
72
73
74/**
75 * Opcode structure.
76 */
77typedef struct DISARMV8OPCODE
78{
79 /** The value of the fixed bits of the instruction. */
80 uint32_t fValue;
81 /** Special flags for the opcode. */
82 uint32_t fFlags;
83 /** The generic opcode structure. */
84 DISOPCODE Opc;
85} DISARMV8OPCODE;
86/** Pointer to a const opcode. */
87typedef const DISARMV8OPCODE *PCDISARMV8OPCODE;
88
89
90typedef struct DISARMV8INSNPARAM
91{
92 /** The parser to use for the decode step. */
93 DISPARMPARSEIDX idxParse;
94 /** Bit index at which the field starts. */
95 uint8_t idxBitStart;
96 /** Size of the bit field. */
97 uint8_t cBits;
98 /** The parameter this decoder param contributes to. */
99 uint8_t idxParam;
100} DISARMV8INSNPARAM;
101typedef DISARMV8INSNPARAM *PDISARMV8INSNPARAM;
102typedef const DISARMV8INSNPARAM *PCDISARMV8INSNPARAM;
103
104#define DIS_ARMV8_INSN_DECODE_TERM { kDisParmParseNop, 0, 0, DIS_ARMV8_INSN_PARAM_UNSET }
105#define DIS_ARMV8_INSN_DECODE(a_idxParse, a_idxBitStart, a_cBits, a_idxParam) \
106 { a_idxParse, a_idxBitStart, a_cBits, a_idxParam }
107
108#define DIS_ARMV8_INSN_PARAM_UNSET UINT8_MAX
109
110/**
111 * Opcode decode index.
112 */
113typedef enum DISARMV8OPCDECODE
114{
115 kDisArmV8OpcDecodeNop = 0,
116 kDisArmV8OpcDecodeLookup,
117 kDisArmV8OpcDecodeCollate,
118 kDisArmV8OpcDecodeMax
119} DISARMV8OPCDECODE;
120
121
122/**
123 * Decoder stage type.
124 */
125typedef enum kDisArmV8DecodeType
126{
127 kDisArmV8DecodeType_Invalid = 0,
128 kDisArmV8DecodeType_Map,
129 kDisArmV8DecodeType_Table,
130 kDisArmV8DecodeType_InsnClass,
131 kDisArmV8DecodeType_32Bit_Hack = 0x7fffffff
132} kDisArmV8DecodeType;
133
134
135/**
136 * Decode header.
137 */
138typedef struct DISARMV8DECODEHDR
139{
140 /** Next stage decoding type. */
141 kDisArmV8DecodeType enmDecodeType;
142 /** Number of entries in the next decoder stage or
143 * opcodes in the instruction class. */
144 uint32_t cDecode;
145} DISARMV8DECODEHDR;
146/** Pointer to a decode header. */
147typedef DISARMV8DECODEHDR *PDISARMV8DECODEHDR;
148/** Pointer to a const decode header. */
149typedef const DISARMV8DECODEHDR *PCDISARMV8DECODEHDR;
150typedef const PCDISARMV8DECODEHDR *PPCDISARMV8DECODEHDR;
151
152
153/**
154 * Instruction class descriptor.
155 */
156typedef struct DISARMV8INSNCLASS
157{
158 /** Decoder header. */
159 DISARMV8DECODEHDR Hdr;
160 /** Pointer to the arry of opcodes. */
161 PCDISARMV8OPCODE paOpcodes;
162 /** The mask of fixed instruction bits. */
163 uint32_t fFixedInsn;
164 /** Some flags for this instruction class. */
165 uint32_t fClass;
166 /** Opcode decoder function. */
167 DISARMV8OPCDECODE enmOpcDecode;
168 /** The mask of the bits relevant for decoding. */
169 uint32_t fMask;
170 /** Number of bits to shift to get an index. */
171 uint32_t cShift;
172 /** Parameter types. */
173 DISARMV8OPPARM aenmParamTypes[4];
174 /** The array of decoding steps. */
175 PCDISARMV8INSNPARAM paParms;
176} DISARMV8INSNCLASS;
177/** Pointer to a constant instruction class descriptor. */
178typedef const DISARMV8INSNCLASS *PCDISARMV8INSNCLASS;
179
180/** The instruction class distinguishes between a 32-bit and 64-bit variant using the sf bit (bit 31). */
181#define DISARMV8INSNCLASS_F_SF RT_BIT_32(0)
182/** The N bit in an N:ImmR:ImmS bit vector must be 1 for 64-bit instruction variants. */
183#define DISARMV8INSNCLASS_F_N_FORCED_1_ON_64BIT RT_BIT_32(1)
184/** The instruction class is using the 64-bit register encoding only. */
185#define DISARMV8INSNCLASS_F_FORCED_64BIT RT_BIT_32(2)
186
187
188#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(a_Name) \
189 static const DISARMV8OPCODE g_aArmV8A64Insn ## a_Name ## Opcodes[] = {
190#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(a_Name) \
191 }; \
192 static const DISARMV8INSNPARAM g_aArmV8A64Insn ## a_Name ## Decode[] = {
193#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_4(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
194 a_enmParamType1, a_enmParamType2, a_enmParamType3, a_enmParamType4) \
195 DIS_ARMV8_INSN_DECODE_TERM \
196 }; \
197 static const DISARMV8INSNCLASS g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_InsnClass, \
198 RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## Opcodes) }, \
199 & g_aArmV8A64Insn ## a_Name ## Opcodes[0], \
200 a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
201 { a_enmParamType1, a_enmParamType2, a_enmParamType3, a_enmParamType4 }, \
202 & g_aArmV8A64Insn ## a_Name ## Decode[0] }
203#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
204 a_enmParamType1, a_enmParamType2, a_enmParamType3) \
205 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_4(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
206 a_enmParamType1, a_enmParamType2, a_enmParamType3, kDisArmv8OpParmNone)
207#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
208 a_enmParamType1, a_enmParamType2) \
209 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
210 a_enmParamType1, a_enmParamType2, kDisArmv8OpParmNone)
211#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
212 a_enmParamType1) \
213 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
214 a_enmParamType1, kDisArmv8OpParmNone)
215#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_0(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift) \
216 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
217 kDisArmv8OpParmNone)
218
219#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END \
220 DIS_ARMV8_INSN_PARAM_NONE }
221
222/**
223 * Decoder lookup table entry.
224 */
225typedef struct DISARMV8DECODETBLENTRY
226{
227 /** The mask to apply to the instruction. */
228 uint32_t fMask;
229 /** The value the masked instruction must match for the entry to match. */
230 uint32_t fValue;
231 /** The next stage followed when there is a match. */
232 PCDISARMV8DECODEHDR pHdrNext;
233} DISARMV8DECODETBLENTRY;
234typedef struct DISARMV8DECODETBLENTRY *PDISARMV8DECODETBLENTRY;
235typedef const DISARMV8DECODETBLENTRY *PCDISARMV8DECODETBLENTRY;
236
237
238#define DIS_ARMV8_DECODE_TBL_ENTRY_INIT(a_fMask, a_fValue, a_pNext) \
239 { a_fMask, a_fValue, & g_aArmV8A64Insn ## a_pNext.Hdr }
240
241
242/**
243 * Decoder lookup table using masks and values.
244 */
245typedef struct DISARMV8DECODETBL
246{
247 /** The header for the decoder lookup table. */
248 DISARMV8DECODEHDR Hdr;
249 /** Pointer to the individual entries. */
250 PCDISARMV8DECODETBLENTRY paEntries;
251} DISARMV8DECODETBL;
252/** Pointer to a const decode table. */
253typedef const struct DISARMV8DECODETBL *PCDISARMV8DECODETBL;
254
255
256#define DIS_ARMV8_DECODE_TBL_DEFINE_BEGIN(a_Name) \
257 static const DISARMV8DECODETBLENTRY g_aArmV8A64Insn ## a_Name ## TblEnt[] = {
258
259#define DIS_ARMV8_DECODE_TBL_DEFINE_END(a_Name) \
260 }; \
261 static const DISARMV8DECODETBL g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Table, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## TblEnt) }, \
262 & g_aArmV8A64Insn ## a_Name ## TblEnt[0] }
263
264
265/**
266 * Decoder map when direct indexing is possible.
267 */
268typedef struct DISARMV8DECODEMAP
269{
270 /** The header for the decoder map. */
271 DISARMV8DECODEHDR Hdr;
272 /** The bitmask used to decide where to go next. */
273 uint32_t fMask;
274 /** Amount to shift to get at the index. */
275 uint32_t cShift;
276 /** Pointer to the array of pointers to the next stage to index into. */
277 PPCDISARMV8DECODEHDR papNext;
278} DISARMV8DECODEMAP;
279/** Pointer to a const decode map. */
280typedef const struct DISARMV8DECODEMAP *PCDISARMV8DECODEMAP;
281
282#define DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(a_Name) \
283 static const PCDISARMV8DECODEHDR g_aArmV8A64Insn ## a_Name ## MapHdrs[] = {
284
285#define DIS_ARMV8_DECODE_MAP_DEFINE_END(a_Name, a_fMask, a_cShift) \
286 }; \
287 static const DISARMV8DECODEMAP g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
288 a_fMask, a_cShift, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
289
290#define DIS_ARMV8_DECODE_MAP_DEFINE_END_NON_STATIC(a_Name, a_fMask, a_cShift) \
291 }; \
292 DECL_HIDDEN_CONST(DISARMV8DECODEMAP) g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
293 a_fMask, a_cShift, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
294
295#define DIS_ARMV8_DECODE_MAP_INVALID_ENTRY NULL
296#define DIS_ARMV8_DECODE_MAP_ENTRY(a_Next) & g_aArmV8A64Insn ## a_Next.Hdr
297
298
299/** @name Decoder maps.
300 * @{ */
301extern DECL_HIDDEN_DATA(DISOPCODE) g_ArmV8A64InvalidOpcode[1];
302
303extern DECL_HIDDEN_DATA(DISARMV8DECODEMAP) g_aArmV8A64InsnDecodeL0;
304/** @} */
305
306
307/** @} */
308#endif /* !VBOX_INCLUDED_SRC_DisasmInternal_armv8_h */
309
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