VirtualBox

source: vbox/trunk/src/VBox/Disassembler/DisasmInternal-armv8.h@ 105848

Last change on this file since 105848 was 105848, checked in by vboxsync, 3 months ago

Disassembler/ARMv8: Support disassembling the load/store register offset instruction variants, bugref:10394
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  • Property svn:keywords set to Author Date Id Revision
File size: 11.7 KB
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1/* $Id: DisasmInternal-armv8.h 105848 2024-08-23 16:05:23Z vboxsync $ */
2/** @file
3 * VBox disassembler - Internal header.
4 */
5
6/*
7 * Copyright (C) 2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VBOX_INCLUDED_SRC_DisasmInternal_armv8_h
29#define VBOX_INCLUDED_SRC_DisasmInternal_armv8_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <VBox/types.h>
35#include <VBox/err.h>
36#include <VBox/dis.h>
37#include <VBox/log.h>
38
39#include <iprt/param.h>
40#include "DisasmInternal.h"
41
42
43/** @addtogroup grp_dis_int Internals.
44 * @ingroup grp_dis
45 * @{
46 */
47
48/** @name Index into g_apfnFullDisasm.
49 * @{ */
50typedef enum DISPARMPARSEIDX
51{
52 kDisParmParseNop = 0,
53 kDisParmParseSize,
54 kDisParmParseImm,
55 kDisParmParseImmRel,
56 kDisParmParseImmAdr,
57 kDisParmParseReg,
58 kDisParmParseRegOff,
59 kDisParmParseImmsImmrN,
60 kDisParmParseHw,
61 kDisParmParseCond,
62 kDisParmParsePState,
63 kDisParmParseCRnCRm,
64 kDisParmParseSysReg,
65 kDisParmParseSh12,
66 kDisParmParseImmTbz,
67 kDisParmParseShift,
68 kDisParmParseShiftAmount,
69 kDisParmParseImmMemOff,
70 kDisParmParseSImmMemOff,
71 kDisParmParseOption,
72 kDisParmParseS,
73 kDisParmParseMax
74} DISPARMPARSEIDX;
75/** @} */
76
77
78/**
79 * Opcode structure.
80 */
81typedef struct DISARMV8OPCODE
82{
83 /** The value of the fixed bits of the instruction. */
84 uint32_t fValue;
85 /** Special flags for the opcode. */
86 uint32_t fFlags;
87 /** The generic opcode structure. */
88 DISOPCODE Opc;
89} DISARMV8OPCODE;
90/** Pointer to a const opcode. */
91typedef const DISARMV8OPCODE *PCDISARMV8OPCODE;
92
93
94typedef struct DISARMV8INSNPARAM
95{
96 /** The parser to use for the decode step. */
97 DISPARMPARSEIDX idxParse;
98 /** Bit index at which the field starts. */
99 uint8_t idxBitStart;
100 /** Size of the bit field. */
101 uint8_t cBits;
102 /** The parameter this decoder param contributes to. */
103 uint8_t idxParam;
104} DISARMV8INSNPARAM;
105typedef DISARMV8INSNPARAM *PDISARMV8INSNPARAM;
106typedef const DISARMV8INSNPARAM *PCDISARMV8INSNPARAM;
107
108#define DIS_ARMV8_INSN_DECODE_TERM { kDisParmParseNop, 0, 0, DIS_ARMV8_INSN_PARAM_UNSET }
109#define DIS_ARMV8_INSN_DECODE(a_idxParse, a_idxBitStart, a_cBits, a_idxParam) \
110 { a_idxParse, a_idxBitStart, a_cBits, a_idxParam }
111
112#define DIS_ARMV8_INSN_PARAM_UNSET UINT8_MAX
113
114/**
115 * Opcode decode index.
116 */
117typedef enum DISARMV8OPCDECODE
118{
119 kDisArmV8OpcDecodeNop = 0,
120 kDisArmV8OpcDecodeLookup,
121 kDisArmV8OpcDecodeCollate,
122 kDisArmV8OpcDecodeMax
123} DISARMV8OPCDECODE;
124
125
126/**
127 * Decoder stage type.
128 */
129typedef enum kDisArmV8DecodeType
130{
131 kDisArmV8DecodeType_Invalid = 0,
132 kDisArmV8DecodeType_Map,
133 kDisArmV8DecodeType_Table,
134 kDisArmV8DecodeType_InsnClass,
135 kDisArmV8DecodeType_32Bit_Hack = 0x7fffffff
136} kDisArmV8DecodeType;
137
138
139/**
140 * Decode header.
141 */
142typedef struct DISARMV8DECODEHDR
143{
144 /** Next stage decoding type. */
145 kDisArmV8DecodeType enmDecodeType;
146 /** Number of entries in the next decoder stage or
147 * opcodes in the instruction class. */
148 uint32_t cDecode;
149} DISARMV8DECODEHDR;
150/** Pointer to a decode header. */
151typedef DISARMV8DECODEHDR *PDISARMV8DECODEHDR;
152/** Pointer to a const decode header. */
153typedef const DISARMV8DECODEHDR *PCDISARMV8DECODEHDR;
154typedef const PCDISARMV8DECODEHDR *PPCDISARMV8DECODEHDR;
155
156
157/**
158 * Instruction class descriptor.
159 */
160typedef struct DISARMV8INSNCLASS
161{
162 /** Decoder header. */
163 DISARMV8DECODEHDR Hdr;
164 /** Pointer to the arry of opcodes. */
165 PCDISARMV8OPCODE paOpcodes;
166 /** The mask of fixed instruction bits. */
167 uint32_t fFixedInsn;
168 /** Some flags for this instruction class. */
169 uint32_t fClass;
170 /** Opcode decoder function. */
171 DISARMV8OPCDECODE enmOpcDecode;
172 /** The mask of the bits relevant for decoding. */
173 uint32_t fMask;
174 /** Number of bits to shift to get an index. */
175 uint32_t cShift;
176 /** Parameter types. */
177 DISARMV8OPPARM aenmParamTypes[4];
178 /** The array of decoding steps. */
179 PCDISARMV8INSNPARAM paParms;
180} DISARMV8INSNCLASS;
181/** Pointer to a constant instruction class descriptor. */
182typedef const DISARMV8INSNCLASS *PCDISARMV8INSNCLASS;
183
184/** The instruction class distinguishes between a 32-bit and 64-bit variant using the sf bit (bit 31). */
185#define DISARMV8INSNCLASS_F_SF RT_BIT_32(0)
186/** The N bit in an N:ImmR:ImmS bit vector must be 1 for 64-bit instruction variants. */
187#define DISARMV8INSNCLASS_F_N_FORCED_1_ON_64BIT RT_BIT_32(1)
188/** The instruction class is using the 64-bit register encoding only. */
189#define DISARMV8INSNCLASS_F_FORCED_64BIT RT_BIT_32(2)
190/** The instruction class is using the 32-bit register encoding only. */
191#define DISARMV8INSNCLASS_F_FORCED_32BIT RT_BIT_32(3)
192
193
194#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(a_Name) \
195 static const DISARMV8OPCODE g_aArmV8A64Insn ## a_Name ## Opcodes[] = {
196#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(a_Name) \
197 }; \
198 static const DISARMV8INSNPARAM g_aArmV8A64Insn ## a_Name ## Decode[] = {
199#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_4(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
200 a_enmParamType1, a_enmParamType2, a_enmParamType3, a_enmParamType4) \
201 DIS_ARMV8_INSN_DECODE_TERM \
202 }; \
203 static const DISARMV8INSNCLASS g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_InsnClass, \
204 RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## Opcodes) }, \
205 & g_aArmV8A64Insn ## a_Name ## Opcodes[0], \
206 a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
207 { a_enmParamType1, a_enmParamType2, a_enmParamType3, a_enmParamType4 }, \
208 & g_aArmV8A64Insn ## a_Name ## Decode[0] }
209#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
210 a_enmParamType1, a_enmParamType2, a_enmParamType3) \
211 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_4(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
212 a_enmParamType1, a_enmParamType2, a_enmParamType3, kDisArmv8OpParmNone)
213#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
214 a_enmParamType1, a_enmParamType2) \
215 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
216 a_enmParamType1, a_enmParamType2, kDisArmv8OpParmNone)
217#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
218 a_enmParamType1) \
219 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
220 a_enmParamType1, kDisArmv8OpParmNone)
221#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_0(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift) \
222 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
223 kDisArmv8OpParmNone)
224
225#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END \
226 DIS_ARMV8_INSN_PARAM_NONE }
227
228/**
229 * Decoder lookup table entry.
230 */
231typedef struct DISARMV8DECODETBLENTRY
232{
233 /** The mask to apply to the instruction. */
234 uint32_t fMask;
235 /** The value the masked instruction must match for the entry to match. */
236 uint32_t fValue;
237 /** The next stage followed when there is a match. */
238 PCDISARMV8DECODEHDR pHdrNext;
239} DISARMV8DECODETBLENTRY;
240typedef struct DISARMV8DECODETBLENTRY *PDISARMV8DECODETBLENTRY;
241typedef const DISARMV8DECODETBLENTRY *PCDISARMV8DECODETBLENTRY;
242
243
244#define DIS_ARMV8_DECODE_TBL_ENTRY_INIT(a_fMask, a_fValue, a_pNext) \
245 { a_fMask, a_fValue, & g_aArmV8A64Insn ## a_pNext.Hdr }
246
247
248/**
249 * Decoder lookup table using masks and values.
250 */
251typedef struct DISARMV8DECODETBL
252{
253 /** The header for the decoder lookup table. */
254 DISARMV8DECODEHDR Hdr;
255 /** Pointer to the individual entries. */
256 PCDISARMV8DECODETBLENTRY paEntries;
257} DISARMV8DECODETBL;
258/** Pointer to a const decode table. */
259typedef const struct DISARMV8DECODETBL *PCDISARMV8DECODETBL;
260
261
262#define DIS_ARMV8_DECODE_TBL_DEFINE_BEGIN(a_Name) \
263 static const DISARMV8DECODETBLENTRY g_aArmV8A64Insn ## a_Name ## TblEnt[] = {
264
265#define DIS_ARMV8_DECODE_TBL_DEFINE_END(a_Name) \
266 }; \
267 static const DISARMV8DECODETBL g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Table, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## TblEnt) }, \
268 & g_aArmV8A64Insn ## a_Name ## TblEnt[0] }
269
270
271/**
272 * Decoder map when direct indexing is possible.
273 */
274typedef struct DISARMV8DECODEMAP
275{
276 /** The header for the decoder map. */
277 DISARMV8DECODEHDR Hdr;
278 /** The bitmask used to decide where to go next. */
279 uint32_t fMask;
280 /** Amount to shift to get at the index. */
281 uint32_t cShift;
282 /** Pointer to the array of pointers to the next stage to index into. */
283 PPCDISARMV8DECODEHDR papNext;
284} DISARMV8DECODEMAP;
285/** Pointer to a const decode map. */
286typedef const struct DISARMV8DECODEMAP *PCDISARMV8DECODEMAP;
287
288#define DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(a_Name) \
289 static const PCDISARMV8DECODEHDR g_aArmV8A64Insn ## a_Name ## MapHdrs[] = {
290
291#define DIS_ARMV8_DECODE_MAP_DEFINE_END(a_Name, a_fMask, a_cShift) \
292 }; \
293 static const DISARMV8DECODEMAP g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
294 a_fMask, a_cShift, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
295
296#define DIS_ARMV8_DECODE_MAP_DEFINE_END_NON_STATIC(a_Name, a_fMask, a_cShift) \
297 }; \
298 DECL_HIDDEN_CONST(DISARMV8DECODEMAP) g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
299 a_fMask, a_cShift, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
300
301#define DIS_ARMV8_DECODE_MAP_INVALID_ENTRY NULL
302#define DIS_ARMV8_DECODE_MAP_ENTRY(a_Next) & g_aArmV8A64Insn ## a_Next.Hdr
303
304
305/** @name Decoder maps.
306 * @{ */
307extern DECL_HIDDEN_DATA(DISOPCODE) g_ArmV8A64InvalidOpcode[1];
308
309extern DECL_HIDDEN_DATA(DISARMV8DECODEMAP) g_aArmV8A64InsnDecodeL0;
310/** @} */
311
312
313/** @} */
314#endif /* !VBOX_INCLUDED_SRC_DisasmInternal_armv8_h */
315
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