VirtualBox

source: vbox/trunk/src/VBox/Disassembler/DisasmInternal-armv8.h@ 106616

Last change on this file since 106616 was 106616, checked in by vboxsync, 5 weeks ago

Disassembler: Fix decoding instructions which take sp as a register instead of of xzr/wzr, bugref:10394
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  • Property svn:keywords set to Author Date Id Revision
File size: 12.4 KB
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1/* $Id: DisasmInternal-armv8.h 106616 2024-10-23 10:41:19Z vboxsync $ */
2/** @file
3 * VBox disassembler - Internal header.
4 */
5
6/*
7 * Copyright (C) 2023-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VBOX_INCLUDED_SRC_DisasmInternal_armv8_h
29#define VBOX_INCLUDED_SRC_DisasmInternal_armv8_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <VBox/types.h>
35#include <VBox/err.h>
36#include <VBox/dis.h>
37#include <VBox/log.h>
38
39#include <iprt/param.h>
40#include "DisasmInternal.h"
41
42
43/** @addtogroup grp_dis_int Internals.
44 * @ingroup grp_dis
45 * @{
46 */
47
48/** @name Index into g_apfnFullDisasm.
49 * @{ */
50typedef enum DISPARMPARSEIDX
51{
52 kDisParmParseNop = 0,
53 kDisParmParseSize,
54 kDisParmParseImm,
55 kDisParmParseImmRel,
56 kDisParmParseImmAdr,
57 kDisParmParseImmZero,
58 kDisParmParseGprZr,
59 kDisParmParseGprSp,
60 kDisParmParseGprOff,
61 kDisParmParseImmsImmrN,
62 kDisParmParseHw,
63 kDisParmParseCond,
64 kDisParmParsePState,
65 kDisParmParseCRnCRm,
66 kDisParmParseSysReg,
67 kDisParmParseSh12,
68 kDisParmParseImmTbz,
69 kDisParmParseShift,
70 kDisParmParseShiftAmount,
71 kDisParmParseImmMemOff,
72 kDisParmParseSImmMemOff,
73 kDisParmParseSImmMemOffUnscaled,
74 kDisParmParseOption,
75 kDisParmParseS,
76 kDisParmParseSetPreIndexed,
77 kDisParmParseSetPostIndexed,
78 kDisParmParseFpType,
79 kDisParmParseFpReg,
80 kDisParmParseFpScale,
81 kDisParmParseFpFixupFCvt,
82 kDisParmParseSimdRegScalar,
83 kDisParmParseImmHImmB,
84 kDisParmParseMax
85} DISPARMPARSEIDX;
86/** @} */
87
88
89/**
90 * Opcode structure.
91 */
92typedef struct DISARMV8OPCODE
93{
94 /** The value of the fixed bits of the instruction. */
95 uint32_t fValue;
96 /** Special flags for the opcode. */
97 uint32_t fFlags;
98 /** The generic opcode structure. */
99 DISOPCODE Opc;
100} DISARMV8OPCODE;
101/** Pointer to a const opcode. */
102typedef const DISARMV8OPCODE *PCDISARMV8OPCODE;
103
104
105typedef struct DISARMV8INSNPARAM
106{
107 /** The parser to use for the decode step. */
108 DISPARMPARSEIDX idxParse;
109 /** Bit index at which the field starts. */
110 uint8_t idxBitStart;
111 /** Size of the bit field. */
112 uint8_t cBits;
113 /** The parameter this decoder param contributes to. */
114 uint8_t idxParam;
115} DISARMV8INSNPARAM;
116typedef DISARMV8INSNPARAM *PDISARMV8INSNPARAM;
117typedef const DISARMV8INSNPARAM *PCDISARMV8INSNPARAM;
118
119#define DIS_ARMV8_INSN_DECODE_TERM { kDisParmParseNop, 0, 0, DIS_ARMV8_INSN_PARAM_UNSET }
120#define DIS_ARMV8_INSN_DECODE(a_idxParse, a_idxBitStart, a_cBits, a_idxParam) \
121 { a_idxParse, a_idxBitStart, a_cBits, a_idxParam }
122
123#define DIS_ARMV8_INSN_PARAM_UNSET UINT8_MAX
124
125/**
126 * Opcode decode index.
127 */
128typedef enum DISARMV8OPCDECODE
129{
130 kDisArmV8OpcDecodeNop = 0,
131 kDisArmV8OpcDecodeLookup,
132 kDisArmV8OpcDecodeCollate,
133 kDisArmV8OpcDecodeMax
134} DISARMV8OPCDECODE;
135
136
137/**
138 * Decoder stage type.
139 */
140typedef enum kDisArmV8DecodeType
141{
142 kDisArmV8DecodeType_Invalid = 0,
143 kDisArmV8DecodeType_Map,
144 kDisArmV8DecodeType_Table,
145 kDisArmV8DecodeType_InsnClass,
146 kDisArmV8DecodeType_32Bit_Hack = 0x7fffffff
147} kDisArmV8DecodeType;
148
149
150/**
151 * Decode header.
152 */
153typedef struct DISARMV8DECODEHDR
154{
155 /** Next stage decoding type. */
156 kDisArmV8DecodeType enmDecodeType;
157 /** Number of entries in the next decoder stage or
158 * opcodes in the instruction class. */
159 uint32_t cDecode;
160} DISARMV8DECODEHDR;
161/** Pointer to a decode header. */
162typedef DISARMV8DECODEHDR *PDISARMV8DECODEHDR;
163/** Pointer to a const decode header. */
164typedef const DISARMV8DECODEHDR *PCDISARMV8DECODEHDR;
165typedef const PCDISARMV8DECODEHDR *PPCDISARMV8DECODEHDR;
166
167
168/**
169 * Instruction class descriptor.
170 */
171typedef struct DISARMV8INSNCLASS
172{
173 /** Decoder header. */
174 DISARMV8DECODEHDR Hdr;
175 /** Pointer to the arry of opcodes. */
176 PCDISARMV8OPCODE paOpcodes;
177 /** The mask of fixed instruction bits. */
178 uint32_t fFixedInsn;
179 /** Some flags for this instruction class. */
180 uint32_t fClass;
181 /** Opcode decoder function. */
182 DISARMV8OPCDECODE enmOpcDecode;
183 /** The mask of the bits relevant for decoding. */
184 uint32_t fMask;
185 /** Number of bits to shift to get an index. */
186 uint32_t cShift;
187 /** Parameter types. */
188 DISARMV8OPPARM aenmParamTypes[4];
189 /** The array of decoding steps. */
190 PCDISARMV8INSNPARAM paParms;
191} DISARMV8INSNCLASS;
192/** Pointer to a constant instruction class descriptor. */
193typedef const DISARMV8INSNCLASS *PCDISARMV8INSNCLASS;
194
195/** The instruction class distinguishes between a 32-bit and 64-bit variant using the sf bit (bit 31). */
196#define DISARMV8INSNCLASS_F_SF RT_BIT_32(0)
197/** The N bit in an N:ImmR:ImmS bit vector must be 1 for 64-bit instruction variants. */
198#define DISARMV8INSNCLASS_F_N_FORCED_1_ON_64BIT RT_BIT_32(1)
199/** The instruction class is using the 64-bit register encoding only. */
200#define DISARMV8INSNCLASS_F_FORCED_64BIT RT_BIT_32(2)
201/** The instruction class is using the 32-bit register encoding only. */
202#define DISARMV8INSNCLASS_F_FORCED_32BIT RT_BIT_32(3)
203
204
205#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(a_Name) \
206 static const DISARMV8OPCODE g_aArmV8A64Insn ## a_Name ## Opcodes[] = {
207#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(a_Name) \
208 }; \
209 static const DISARMV8INSNPARAM g_aArmV8A64Insn ## a_Name ## Decode[] = {
210#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_4(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
211 a_enmParamType1, a_enmParamType2, a_enmParamType3, a_enmParamType4) \
212 DIS_ARMV8_INSN_DECODE_TERM \
213 }; \
214 static const DISARMV8INSNCLASS g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_InsnClass, \
215 RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## Opcodes) }, \
216 & g_aArmV8A64Insn ## a_Name ## Opcodes[0], \
217 a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
218 { a_enmParamType1, a_enmParamType2, a_enmParamType3, a_enmParamType4 }, \
219 & g_aArmV8A64Insn ## a_Name ## Decode[0] }
220#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
221 a_enmParamType1, a_enmParamType2, a_enmParamType3) \
222 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_4(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
223 a_enmParamType1, a_enmParamType2, a_enmParamType3, kDisArmv8OpParmNone)
224#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
225 a_enmParamType1, a_enmParamType2) \
226 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
227 a_enmParamType1, a_enmParamType2, kDisArmv8OpParmNone)
228#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
229 a_enmParamType1) \
230 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
231 a_enmParamType1, kDisArmv8OpParmNone)
232#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_0(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift) \
233 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \
234 kDisArmv8OpParmNone)
235
236#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END \
237 DIS_ARMV8_INSN_PARAM_NONE }
238
239/**
240 * Decoder lookup table entry.
241 */
242typedef struct DISARMV8DECODETBLENTRY
243{
244 /** The mask to apply to the instruction. */
245 uint32_t fMask;
246 /** The value the masked instruction must match for the entry to match. */
247 uint32_t fValue;
248 /** The next stage followed when there is a match. */
249 PCDISARMV8DECODEHDR pHdrNext;
250} DISARMV8DECODETBLENTRY;
251typedef struct DISARMV8DECODETBLENTRY *PDISARMV8DECODETBLENTRY;
252typedef const DISARMV8DECODETBLENTRY *PCDISARMV8DECODETBLENTRY;
253
254
255#define DIS_ARMV8_DECODE_TBL_ENTRY_INIT(a_fMask, a_fValue, a_pNext) \
256 { a_fMask, a_fValue, & g_aArmV8A64Insn ## a_pNext.Hdr }
257
258
259/**
260 * Decoder lookup table using masks and values.
261 */
262typedef struct DISARMV8DECODETBL
263{
264 /** The header for the decoder lookup table. */
265 DISARMV8DECODEHDR Hdr;
266 /** Pointer to the individual entries. */
267 PCDISARMV8DECODETBLENTRY paEntries;
268} DISARMV8DECODETBL;
269/** Pointer to a const decode table. */
270typedef const struct DISARMV8DECODETBL *PCDISARMV8DECODETBL;
271
272
273#define DIS_ARMV8_DECODE_TBL_DEFINE_BEGIN(a_Name) \
274 static const DISARMV8DECODETBLENTRY g_aArmV8A64Insn ## a_Name ## TblEnt[] = {
275
276#define DIS_ARMV8_DECODE_TBL_DEFINE_END(a_Name) \
277 }; \
278 static const DISARMV8DECODETBL g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Table, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## TblEnt) }, \
279 & g_aArmV8A64Insn ## a_Name ## TblEnt[0] }
280
281
282/**
283 * Decoder map when direct indexing is possible.
284 */
285typedef struct DISARMV8DECODEMAP
286{
287 /** The header for the decoder map. */
288 DISARMV8DECODEHDR Hdr;
289 /** The bitmask used to decide where to go next. */
290 uint32_t fMask;
291 /** Amount to shift to get at the index. */
292 uint32_t cShift;
293 /** Pointer to the array of pointers to the next stage to index into. */
294 PPCDISARMV8DECODEHDR papNext;
295} DISARMV8DECODEMAP;
296/** Pointer to a const decode map. */
297typedef const struct DISARMV8DECODEMAP *PCDISARMV8DECODEMAP;
298
299#define DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(a_Name) \
300 static const PCDISARMV8DECODEHDR g_aArmV8A64Insn ## a_Name ## MapHdrs[] = {
301
302#define DIS_ARMV8_DECODE_MAP_DEFINE_END(a_Name, a_fMask, a_cShift) \
303 }; \
304 static const DISARMV8DECODEMAP g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
305 a_fMask, a_cShift, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
306
307#define DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(a_Name, a_idxBit) \
308 }; \
309 static const DISARMV8DECODEMAP g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
310 RT_BIT_32(a_idxBit), a_idxBit, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
311
312
313#define DIS_ARMV8_DECODE_MAP_DEFINE_END_NON_STATIC(a_Name, a_fMask, a_cShift) \
314 }; \
315 DECL_HIDDEN_CONST(DISARMV8DECODEMAP) g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
316 a_fMask, a_cShift, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
317
318#define DIS_ARMV8_DECODE_MAP_INVALID_ENTRY NULL
319#define DIS_ARMV8_DECODE_MAP_ENTRY(a_Next) & g_aArmV8A64Insn ## a_Next.Hdr
320
321
322/** @name Decoder maps.
323 * @{ */
324extern DECL_HIDDEN_DATA(DISOPCODE) g_ArmV8A64InvalidOpcode[1];
325
326extern DECL_HIDDEN_DATA(DISARMV8DECODEMAP) g_aArmV8A64InsnDecodeL0;
327/** @} */
328
329
330/** @} */
331#endif /* !VBOX_INCLUDED_SRC_DisasmInternal_armv8_h */
332
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