VirtualBox

source: vbox/trunk/src/VBox/Disassembler/DisasmInternal-armv8.h@ 106618

Last change on this file since 106618 was 106618, checked in by vboxsync, 5 weeks ago

Disassembler: Get rid of fClass member and convert the only real use to a decoder step, bugref:10394
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  • Property svn:keywords set to Author Date Id Revision
File size: 12.1 KB
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1/* $Id: DisasmInternal-armv8.h 106618 2024-10-23 11:59:34Z vboxsync $ */
2/** @file
3 * VBox disassembler - Internal header.
4 */
5
6/*
7 * Copyright (C) 2023-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VBOX_INCLUDED_SRC_DisasmInternal_armv8_h
29#define VBOX_INCLUDED_SRC_DisasmInternal_armv8_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <VBox/types.h>
35#include <VBox/err.h>
36#include <VBox/dis.h>
37#include <VBox/log.h>
38
39#include <iprt/param.h>
40#include "DisasmInternal.h"
41
42
43/** @addtogroup grp_dis_int Internals.
44 * @ingroup grp_dis
45 * @{
46 */
47
48/** @name Index into g_apfnFullDisasm.
49 * @{ */
50typedef enum DISPARMPARSEIDX
51{
52 kDisParmParseNop = 0,
53 kDisParmParseSize,
54 kDisParmParseImm,
55 kDisParmParseImmRel,
56 kDisParmParseImmAdr,
57 kDisParmParseImmZero,
58 kDisParmParseGprZr,
59 kDisParmParseGprSp,
60 kDisParmParseGprOff,
61 kDisParmParseImmsImmrN,
62 kDisParmParseHw,
63 kDisParmParseCond,
64 kDisParmParsePState,
65 kDisParmParseCRnCRm,
66 kDisParmParseSysReg,
67 kDisParmParseSh12,
68 kDisParmParseImmTbz,
69 kDisParmParseShift,
70 kDisParmParseShiftAmount,
71 kDisParmParseImmMemOff,
72 kDisParmParseSImmMemOff,
73 kDisParmParseSImmMemOffUnscaled,
74 kDisParmParseOption,
75 kDisParmParseS,
76 kDisParmParseSetPreIndexed,
77 kDisParmParseSetPostIndexed,
78 kDisParmParseFpType,
79 kDisParmParseFpReg,
80 kDisParmParseFpScale,
81 kDisParmParseFpFixupFCvt,
82 kDisParmParseSimdRegScalar,
83 kDisParmParseImmHImmB,
84 kDisParmParseSf,
85 kDisParmParseMax
86} DISPARMPARSEIDX;
87/** @} */
88
89
90/**
91 * Opcode structure.
92 */
93typedef struct DISARMV8OPCODE
94{
95 /** The value of the fixed bits of the instruction. */
96 uint32_t fValue;
97 /** Special flags for the opcode. */
98 uint32_t fFlags;
99 /** The generic opcode structure. */
100 DISOPCODE Opc;
101} DISARMV8OPCODE;
102/** Pointer to a const opcode. */
103typedef const DISARMV8OPCODE *PCDISARMV8OPCODE;
104
105
106typedef struct DISARMV8INSNPARAM
107{
108 /** The parser to use for the decode step. */
109 DISPARMPARSEIDX idxParse;
110 /** Bit index at which the field starts. */
111 uint8_t idxBitStart;
112 /** Size of the bit field. */
113 uint8_t cBits;
114 /** The parameter this decoder param contributes to. */
115 uint8_t idxParam;
116} DISARMV8INSNPARAM;
117typedef DISARMV8INSNPARAM *PDISARMV8INSNPARAM;
118typedef const DISARMV8INSNPARAM *PCDISARMV8INSNPARAM;
119
120#define DIS_ARMV8_INSN_DECODE_TERM { kDisParmParseNop, 0, 0, DIS_ARMV8_INSN_PARAM_UNSET }
121#define DIS_ARMV8_INSN_DECODE(a_idxParse, a_idxBitStart, a_cBits, a_idxParam) \
122 { a_idxParse, a_idxBitStart, a_cBits, a_idxParam }
123
124#define DIS_ARMV8_INSN_PARAM_UNSET UINT8_MAX
125
126/**
127 * Opcode decode index.
128 */
129typedef enum DISARMV8OPCDECODE
130{
131 kDisArmV8OpcDecodeNop = 0,
132 kDisArmV8OpcDecodeLookup,
133 kDisArmV8OpcDecodeCollate,
134 kDisArmV8OpcDecodeMax
135} DISARMV8OPCDECODE;
136
137
138/**
139 * Decoder stage type.
140 */
141typedef enum kDisArmV8DecodeType
142{
143 kDisArmV8DecodeType_Invalid = 0,
144 kDisArmV8DecodeType_Map,
145 kDisArmV8DecodeType_Table,
146 kDisArmV8DecodeType_InsnClass,
147 kDisArmV8DecodeType_32Bit_Hack = 0x7fffffff
148} kDisArmV8DecodeType;
149
150
151/**
152 * Decode header.
153 */
154typedef struct DISARMV8DECODEHDR
155{
156 /** Next stage decoding type. */
157 kDisArmV8DecodeType enmDecodeType;
158 /** Number of entries in the next decoder stage or
159 * opcodes in the instruction class. */
160 uint32_t cDecode;
161} DISARMV8DECODEHDR;
162/** Pointer to a decode header. */
163typedef DISARMV8DECODEHDR *PDISARMV8DECODEHDR;
164/** Pointer to a const decode header. */
165typedef const DISARMV8DECODEHDR *PCDISARMV8DECODEHDR;
166typedef const PCDISARMV8DECODEHDR *PPCDISARMV8DECODEHDR;
167
168
169/**
170 * Instruction class descriptor.
171 */
172typedef struct DISARMV8INSNCLASS
173{
174 /** Decoder header. */
175 DISARMV8DECODEHDR Hdr;
176 /** Pointer to the arry of opcodes. */
177 PCDISARMV8OPCODE paOpcodes;
178 /** The mask of fixed instruction bits. */
179 uint32_t fFixedInsn;
180 /** Opcode decoder function. */
181 DISARMV8OPCDECODE enmOpcDecode;
182 /** The mask of the bits relevant for decoding. */
183 uint32_t fMask;
184 /** Number of bits to shift to get an index. */
185 uint32_t cShift;
186 /** Parameter types. */
187 DISARMV8OPPARM aenmParamTypes[4];
188 /** The array of decoding steps. */
189 PCDISARMV8INSNPARAM paParms;
190} DISARMV8INSNCLASS;
191/** Pointer to a constant instruction class descriptor. */
192typedef const DISARMV8INSNCLASS *PCDISARMV8INSNCLASS;
193
194/** The N bit in an N:ImmR:ImmS bit vector must be 1 for 64-bit instruction variants. */
195#define DISARMV8INSNCLASS_F_N_FORCED_1_ON_64BIT RT_BIT_32(1)
196/** The instruction class is using the 64-bit register encoding only. */
197#define DISARMV8INSNCLASS_F_FORCED_64BIT RT_BIT_32(2)
198/** The instruction class is using the 32-bit register encoding only. */
199#define DISARMV8INSNCLASS_F_FORCED_32BIT RT_BIT_32(3)
200
201
202#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(a_Name) \
203 static const DISARMV8OPCODE g_aArmV8A64Insn ## a_Name ## Opcodes[] = {
204#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(a_Name) \
205 }; \
206 static const DISARMV8INSNPARAM g_aArmV8A64Insn ## a_Name ## Decode[] = {
207#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_4(a_Name, a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift, \
208 a_enmParamType1, a_enmParamType2, a_enmParamType3, a_enmParamType4) \
209 DIS_ARMV8_INSN_DECODE_TERM \
210 }; \
211 static const DISARMV8INSNCLASS g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_InsnClass, \
212 RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## Opcodes) }, \
213 & g_aArmV8A64Insn ## a_Name ## Opcodes[0], \
214 a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift, \
215 { a_enmParamType1, a_enmParamType2, a_enmParamType3, a_enmParamType4 }, \
216 & g_aArmV8A64Insn ## a_Name ## Decode[0] }
217#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(a_Name, a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift, \
218 a_enmParamType1, a_enmParamType2, a_enmParamType3) \
219 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_4(a_Name, a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift, \
220 a_enmParamType1, a_enmParamType2, a_enmParamType3, kDisArmv8OpParmNone)
221#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(a_Name, a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift, \
222 a_enmParamType1, a_enmParamType2) \
223 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(a_Name, a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift, \
224 a_enmParamType1, a_enmParamType2, kDisArmv8OpParmNone)
225#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(a_Name, a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift, \
226 a_enmParamType1) \
227 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(a_Name, a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift, \
228 a_enmParamType1, kDisArmv8OpParmNone)
229#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_0(a_Name, a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift) \
230 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(a_Name, a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift, \
231 kDisArmv8OpParmNone)
232
233#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END \
234 DIS_ARMV8_INSN_PARAM_NONE }
235
236/**
237 * Decoder lookup table entry.
238 */
239typedef struct DISARMV8DECODETBLENTRY
240{
241 /** The mask to apply to the instruction. */
242 uint32_t fMask;
243 /** The value the masked instruction must match for the entry to match. */
244 uint32_t fValue;
245 /** The next stage followed when there is a match. */
246 PCDISARMV8DECODEHDR pHdrNext;
247} DISARMV8DECODETBLENTRY;
248typedef struct DISARMV8DECODETBLENTRY *PDISARMV8DECODETBLENTRY;
249typedef const DISARMV8DECODETBLENTRY *PCDISARMV8DECODETBLENTRY;
250
251
252#define DIS_ARMV8_DECODE_TBL_ENTRY_INIT(a_fMask, a_fValue, a_pNext) \
253 { a_fMask, a_fValue, & g_aArmV8A64Insn ## a_pNext.Hdr }
254
255
256/**
257 * Decoder lookup table using masks and values.
258 */
259typedef struct DISARMV8DECODETBL
260{
261 /** The header for the decoder lookup table. */
262 DISARMV8DECODEHDR Hdr;
263 /** Pointer to the individual entries. */
264 PCDISARMV8DECODETBLENTRY paEntries;
265} DISARMV8DECODETBL;
266/** Pointer to a const decode table. */
267typedef const struct DISARMV8DECODETBL *PCDISARMV8DECODETBL;
268
269
270#define DIS_ARMV8_DECODE_TBL_DEFINE_BEGIN(a_Name) \
271 static const DISARMV8DECODETBLENTRY g_aArmV8A64Insn ## a_Name ## TblEnt[] = {
272
273#define DIS_ARMV8_DECODE_TBL_DEFINE_END(a_Name) \
274 }; \
275 static const DISARMV8DECODETBL g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Table, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## TblEnt) }, \
276 & g_aArmV8A64Insn ## a_Name ## TblEnt[0] }
277
278
279/**
280 * Decoder map when direct indexing is possible.
281 */
282typedef struct DISARMV8DECODEMAP
283{
284 /** The header for the decoder map. */
285 DISARMV8DECODEHDR Hdr;
286 /** The bitmask used to decide where to go next. */
287 uint32_t fMask;
288 /** Amount to shift to get at the index. */
289 uint32_t cShift;
290 /** Pointer to the array of pointers to the next stage to index into. */
291 PPCDISARMV8DECODEHDR papNext;
292} DISARMV8DECODEMAP;
293/** Pointer to a const decode map. */
294typedef const struct DISARMV8DECODEMAP *PCDISARMV8DECODEMAP;
295
296#define DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(a_Name) \
297 static const PCDISARMV8DECODEHDR g_aArmV8A64Insn ## a_Name ## MapHdrs[] = {
298
299#define DIS_ARMV8_DECODE_MAP_DEFINE_END(a_Name, a_fMask, a_cShift) \
300 }; \
301 static const DISARMV8DECODEMAP g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
302 a_fMask, a_cShift, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
303
304#define DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(a_Name, a_idxBit) \
305 }; \
306 static const DISARMV8DECODEMAP g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
307 RT_BIT_32(a_idxBit), a_idxBit, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
308
309
310#define DIS_ARMV8_DECODE_MAP_DEFINE_END_NON_STATIC(a_Name, a_fMask, a_cShift) \
311 }; \
312 DECL_HIDDEN_CONST(DISARMV8DECODEMAP) g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
313 a_fMask, a_cShift, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
314
315#define DIS_ARMV8_DECODE_MAP_INVALID_ENTRY NULL
316#define DIS_ARMV8_DECODE_MAP_ENTRY(a_Next) & g_aArmV8A64Insn ## a_Next.Hdr
317
318
319/** @name Decoder maps.
320 * @{ */
321extern DECL_HIDDEN_DATA(DISOPCODE) g_ArmV8A64InvalidOpcode[1];
322
323extern DECL_HIDDEN_DATA(DISARMV8DECODEMAP) g_aArmV8A64InsnDecodeL0;
324/** @} */
325
326
327/** @} */
328#endif /* !VBOX_INCLUDED_SRC_DisasmInternal_armv8_h */
329
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